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git-svn-id: http://moon:8086/svn/vhdl/trunk@938 cc03376c-175c-47c8-b038-4cd826a8556b

lib/misc/wire_delay.vhd

@@ -0,0 +1,42 @@
+library IEEE;  
+  use IEEE.Std_Logic_1164.all;
+
+entity wire_delay is
+  generic(a_to_b_loss : time := 1 ns;
+          b_to_a_loss : time := 2 ns);
+  port
+    (A : inout Std_Logic;
+     B : inout Std_Logic
+     );
+end wire_delay;
+
+architecture behave of wire_delay is
+begin
+
+  ABC0_Lbl: process
+    variable ThenTime_v : time := 0 ns;
+
+    function max(t1,t2 : time) return time is
+    begin
+        if (t1 > t2) then
+          return t1;
+        else
+          return t2;
+        end if;
+    end;
+
+  begin
+    wait on A'transaction, B'transaction
+                      until ThenTime_v + max(a_to_b_loss, b_to_a_loss) < now;
+    -- Break
+    ThenTime_v := now;
+    A <= 'Z';
+    B <= 'Z';
+    wait for 0 ns;
+
+    -- Make
+    A <= transport B after b_to_a_loss;
+    B <= transport A after a_to_b_loss;
+
+  end process ABC0_Lbl;
+end behave;