- cleaned up

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git-svn-id: http://moon:8086/svn/vhdl/trunk@582 cc03376c-175c-47c8-b038-4cd826a8556b

lib/VGA_ctrl/src/clkgen_virtex4.vhd

@@ -21,7 +21,8 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
 
-use work.vga_types.all;
+library work;
+use work.utils_pkg.all;
 
 ---- Uncomment the following library declaration if instantiating
 ---- any Xilinx primitives in this code.
@@ -31,21 +32,20 @@ use UNISIM.vcomponents.all;
 entity clkgen is
 	Generic
 	(
-		sys_freq	: integer  			:= 100E6;
+		clk_in_freq_hz		: integer	:= 100E6;
-		tsvga       : vga_timespec_t	:= ts_vga_800_600_72
+		clk_out_freq_hz		: integer	:= 100E6
 	);
 	Port
 	(
 		rst			: in std_logic;
-		clk			: in std_logic;
+		clk_in		: in std_logic;
-		vga_clk		: out std_logic;
+		clk_out		: out std_logic;
-		dcm_locked	: out std_logic
+		locked		: out std_logic
 	);
 end clkgen;
 
 architecture tech of clkgen is
 
-	signal vga_clk0               : std_logic;
 	signal dcm_clk0               : std_logic;
 	signal dcm_clk_fb             : std_logic;
 
@@ -56,10 +56,10 @@ architecture tech of clkgen is
 	generic map (
 		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
 						   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-		CLKFX_DIVIDE => DCM_FREQ_D(sys_freq, tsvga.f_pxl_clk),   -- Can be any interger from 1 to 32
+		CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq_hz, clk_out_freq_hz),   -- Can be any interger from 1 to 32
-		CLKFX_MULTIPLY => DCM_FREQ_M(sys_freq, tsvga.f_pxl_clk), -- Can be any integer from 2 to 32
+		CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq_hz, clk_out_freq_hz), -- Can be any integer from 2 to 32
 		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
-		CLKIN_PERIOD => DCM_PERIOD(sys_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
+		CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
 		CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
 		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
 		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
@@ -79,11 +79,11 @@ architecture tech of clkgen is
 		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
 		CLK90 => open,       -- 90 degree DCM CLK output
 		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
-		CLKFX => vga_clk0,       -- DCM CLK synthesis out (M/D)
+		CLKFX => clk_out,       -- DCM CLK synthesis out (M/D)
 		CLKFX180 => open, -- 180 degree CLK synthesis out
-		LOCKED => dcm_locked,     -- DCM LOCK status output
+		LOCKED => locked,     -- DCM LOCK status output
 		CLKFB => dcm_clk_fb,       -- DCM clock feedback
-		CLKIN => clk,       -- Clock input (from IBUFG, BUFG or DCM)
+		CLKIN => clk_in,       -- Clock input (from IBUFG, BUFG or DCM)
 		RST => rst            -- DCM asynchronous reset input
 	);
 
@@ -94,12 +94,4 @@ architecture tech of clkgen is
 		I => dcm_clk0        -- Clock buffer input
 	);
 
-	BUFG_vga_clk : BUFG
-	port map
-	(
-		O => vga_clk,     -- Clock buffer output
-		I => vga_clk0     -- Clock buffer input
-	);
-
-
 end tech;