From 0bc9ef0b0009da2d4b40c85459984b9653f1fc60 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 12 Oct 2008 12:50:01 +0000 Subject: [PATCH] - Simplfied (better timing) git-svn-id: http://moon:8086/svn/vhdl/trunk@51 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/src/core/dcache.vhd | 41 +++++++++++-------------------- 1 file changed, 14 insertions(+), 27 deletions(-) diff --git a/lib/CPUs/MIPS/src/core/dcache.vhd b/lib/CPUs/MIPS/src/core/dcache.vhd index 39dc123..5093add 100644 --- a/lib/CPUs/MIPS/src/core/dcache.vhd +++ b/lib/CPUs/MIPS/src/core/dcache.vhd @@ -130,11 +130,11 @@ END COMPONENT; return result; end to_tram_data; - type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache, wr_cache); + type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache); signal s, sn : cache_state_t; signal cache_busy : std_logic; - signal cache_miss : std_logic; + signal cache_hit : std_logic; signal tag_match : std_logic; signal word_index_reg : unsigned(word_index_width-1 downto 0); signal cache_index_reg : unsigned(cache_index_width-1 downto 0); @@ -147,13 +147,13 @@ END COMPONENT; signal cpu_dram_din : word_t; signal cpu_data_reg : word_t; signal cpu_be_reg : unsigned(3 downto 0); - signal ctrl_force_be : unsigned(3 downto 0); signal cpu_we_reg : std_logic; + signal ctrl_dram_en : std_logic; signal ctrl_dram_addr : unsigned(lg2(cache_size)-1 downto 0); signal ctrl_dram_din : word_t; signal ctrl_dram_we : unsigned(3 downto 0); signal cpu_dram_we : unsigned(3 downto 0); - signal dram_en : std_logic; + signal cpu_dram_en : std_logic; signal cpu_en2 : std_logic; signal cpu_we2 : std_logic; @@ -179,7 +179,7 @@ END COMPONENT; begin - cpu_hit_we <= cpu_we2 and not cache_miss; + cpu_hit_we <= cpu_we2 and cache_hit; cpu_index_register: process(CLK_I) @@ -261,8 +261,8 @@ gen_data_ram: PORT MAP ( clk_a => CLK_I, clk_b => CLK_I, - en_a => '1', - en_b => dram_en, + en_a => ctrl_dram_en, + en_b => '1', we_a => ctrl_dram_we(i), we_b => cpu_dram_we(i), addr_a => ctrl_dram_addr, @@ -290,7 +290,7 @@ cache_state_next: cpu_dout <= cpu_dram_dout; tag_match <= '1' when tag_index_reg = cache_entry_out.tag else '0'; - cache_miss <= not (tag_match and cache_entry_out.valid); + cache_hit <= tag_match and cache_entry_out.valid; tram_din <= to_tram_data(cache_entry_in); tram_addr_rd <= cpu_cache_index when was_miss = '0' else cache_index_reg; cache_entry_out <= to_dcache_entry(tram_dout); @@ -298,11 +298,12 @@ cache_state_next: ADDR_O <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00"; ctrl_dram_addr <= cache_index_reg & to_unsigned(ram_index_count, word_index_width); ctrl_dram_din <= DAT_I; - ctrl_dram_we <= (3 downto 0 => (data_write and ACK_I)) or ctrl_force_be; + ctrl_dram_we <= (others => '1'); + ctrl_dram_en <= data_write and ACK_I; cpu_dram_we <= cpu_be_reg when (cpu_hit_we = '1') else (others => '0'); cache_state: - process(s, instant_raw, cache_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, SRDY_I, cpu_en2, cpu_we_reg, cpu_be_reg) + process(s, instant_raw, cache_hit, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, SRDY_I, cpu_en2, cpu_we_reg) begin cpu_reg_en <= '0'; cache_busy <= '1'; @@ -313,7 +314,6 @@ cache_state: mem_index_count_rst <= '0'; CYC_O <= '0'; STB_O <= '0'; - dram_en <= '0'; tram_re <= '0'; was_miss <= '0'; data_write <= '0'; @@ -322,7 +322,6 @@ cache_state: cache_entry_in.tag <= tag_index_reg; cache_entry_in.valid <= '0'; cache_entry_in.dirty <= '0'; - ctrl_force_be <= (others => '0'); sn <= s; case s is @@ -331,10 +330,9 @@ cache_state: when ready => cache_busy <= '0'; cpu_reg_en <= '1'; - dram_en <= cpu_en or cpu_en2; tram_re <= cpu_en; if cpu_en2 = '1' then - if cache_miss = '1' and cpu_we_reg = '0' then + if cache_hit = '0' and cpu_we_reg = '0' then sn <= mem_request; cpu_reg_en <= '0'; cache_busy <= '1'; @@ -351,8 +349,7 @@ cache_state: sn <= ready; if cpu_en = '1' then cpu_reg_en <= '1'; - dram_en <= '1'; - tram_re <= '1'; + tram_re <= '1'; end if; end if; when mem_request => @@ -385,22 +382,12 @@ cache_state: tram_addr_wr <= cache_index_reg; tram_we <= '1'; cache_entry_in.valid <= '1'; - if cpu_we_reg = '1' then - sn <= wr_cache; - else - sn <= rd_cache; - end if; - + sn <= rd_cache; when rd_cache => tram_re <= '1'; - dram_en <= '1'; was_miss <= '1'; sn <= ready; - when wr_cache => - tram_re <= '1'; - ctrl_force_be <= cpu_be_reg; - sn <= ready; when others => sn <= ready; end case;