diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.wdo b/lib/CPUs/MIPS/sim/tb_mips_top.wdo
index aed7c0b..1895f12 100644
--- a/lib/CPUs/MIPS/sim/tb_mips_top.wdo
+++ b/lib/CPUs/MIPS/sim/tb_mips_top.wdo
@@ -25,7 +25,6 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi0
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi1
 add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_complete
 add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_empty
-add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_busy
 add wave -noupdate -format Literal /tb_mips_top/inst_uart/uart_status_port
 add wave -noupdate -divider {Interrupt Timer}
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cnt
@@ -44,9 +43,17 @@ add wave -noupdate -format Logic /tb_mips_top/clk
 add wave -noupdate -format Literal /tb_mips_top/mem_area
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d
+add wave -noupdate -format Literal /tb_mips_top/inst_flash_port/s
+add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/ack
+add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/cc_rst
+add wave -noupdate -format Literal /tb_mips_top/inst_flash_port/cycle_cnt
+add wave -noupdate -format Literal /tb_mips_top/inst_flash_port/cycle_reload
+add wave -noupdate -format Literal /tb_mips_top/inst_flash_port/data_reg
+add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/write
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d
 add wave -noupdate -format Logic /tb_mips_top/flash_cs_n
+add wave -noupdate -format Logic /tb_mips_top/flash_we_n
 add wave -noupdate -format Logic /tb_mips_top/flash_oe_n
 add wave -noupdate -format Literal /tb_mips_top/flash_be_n
 add wave -noupdate -format Logic /tb_mips_top/sram_cs_n
@@ -179,7 +186,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_cache_index
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_word_index
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {3998985921 ps} 0}
+WaveRestoreCursors {{Cursor 1} {2560000000 ps} 0}
 configure wave -namecolwidth 188
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left
@@ -193,4 +200,4 @@ configure wave -gridperiod 100
 configure wave -griddelta 40
 configure wave -timeline 1
 update
-WaveRestoreZoom {3998701179 ps} {4000068359 ps}
+WaveRestoreZoom {0 ps} {4200 us}