diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32.wdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32.wdo
index 14ef372..50e4c36 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32.wdo
+++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32.wdo
@@ -43,6 +43,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/inst
 add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/phy_ctrl
 add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_clk
 add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_dqm
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/clk0_rd
 add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_data
 add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_ba
 add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_addr
@@ -56,10 +57,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/inst
 add wave -noupdate -format Literal -expand /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_ctrl_reg
 add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/we_reg
 add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/clk0
-add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/clk0_s
 add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/rst0
-add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/clk_rd
-add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/clk_wr
 add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/locked
 add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/error
 add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/u_tag_pipe
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_virtex4.vhd
index 18a6c27..e4ed6a8 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_virtex4.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_virtex4.vhd
@@ -68,10 +68,9 @@ architecture tech of sdram_phy is
 	signal we_reg			: std_logic;
 	
 	signal clk0				: std_logic;
-	signal clk0_s			: std_logic;
+	signal clk0_temp		: std_logic;
 	signal rst0				: std_logic;
-	signal clk_rd			: std_logic;
-	signal clk_wr			: std_logic;
+	signal clk0_rd			: std_logic;
 
 	signal locked			: std_logic;  
 	signal error			: std_logic;  
@@ -84,9 +83,10 @@ architecture tech of sdram_phy is
 
 begin
 
-	clk0_out	<= clk0_s;
-	clk0		<= clk0_s after 10 ps;		-- fix delta delay
+	clk0_out	<= clk0_temp;
+	clk0		<= clk0_temp after 10 ps;		-- fix delta delay
 	rst0_out	<= rst0;
+	clk0_rd		<= clk_fb;
 	
 ------------------------------------------------------------------------------------------------------------------------------------------------
 inst_sdram_clk : entity work.sdram_clk
@@ -102,7 +102,7 @@ inst_sdram_clk : entity work.sdram_clk
 		rst				=> rst,   -- external async reset, low active
 		clk_in			=> clk,   -- system clock (e.g. 100MHz), from board
 		clk_fb_in		=> clk_fb,   -- feedback clock
-		clk0_0_out		=> clk0_s,  -- System clock #0, dcm#0 output 0°
+		clk0_0_out		=> clk0_temp,  -- System clock #0, dcm#0 output 0°
 		clk0_270_out	=> open,  -- System clock #0, dcm#0 output 270°
 		clk1_0_out		=> open,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
 		clk1_270_out	=> open,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
@@ -110,9 +110,6 @@ inst_sdram_clk : entity work.sdram_clk
 		error_out		=> error
 	);
 
-	clk_wr	<= clk0;
-	clk_rd	<= clk_fb;
-	
 rst0_gen:
 	process(clk0)
 	begin
@@ -161,9 +158,9 @@ part_clk		<= clk0 after TPD_BOARD_SIM;
 
 ------------------------------------------------------------------------------------------------------------------------------------------------
 -- Data OUT FFs
-	process (clk_wr) is
+	process (clk0) is
 	begin  
-		if falling_edge(clk_wr) then
+		if falling_edge(clk0) then
 			part_data <= (others => 'Z') after TPD_BOARD_SIM;
 			if (drive = '1') then
 				part_data	<= phy_in.wr_data after TPD_BOARD_SIM;
@@ -173,9 +170,9 @@ part_clk		<= clk0 after TPD_BOARD_SIM;
 
 ------------------------------------------------------------------------------------------------------------------------------------------------
 -- Data-mask OUT DDR-FFs
-	process (clk_wr) is
+	process (clk0) is
 	begin  
-		if falling_edge(clk_wr) then
+		if falling_edge(clk0) then
 			part_dqm	<= phy_in.wr_dm after TPD_BOARD_SIM;
 		end if;
 	end process;
@@ -212,9 +209,9 @@ part_clk		<= clk0 after TPD_BOARD_SIM;
 -- READ DATA Processing
 -----------------------------------------------------------------
 data_sample_stage:
-	process (clk0)
+	process (clk0_rd)
 	begin
-		if falling_edge(clk0) then
+		if rising_edge(clk0_rd) then
 			data_reg_r	<= part_data;
 		end if;
 	end process;