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git-svn-id: http://moon:8086/svn/vhdl/trunk@1418 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-21 11:05:13 +00:00
parent 097032e4d5
commit 0a2abde8bf
30 changed files with 4955 additions and 0 deletions
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projects/vga_ctrl/syn/ise/project/bitgen.ut
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-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g ConfigRate:4
-g CclkPin:PullUp
-g M0Pin:PullUp
-g M1Pin:PullUp
-g M2Pin:PullUp
-g ProgPin:PullUp
-g DonePin:PullUp
-g InitPin:Pullup
-g CsPin:Pullup
-g DinPin:Pullup
-g BusyPin:Pullup
-g RdWrPin:Pullup
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g DCMShutDown:Disable
-g DCIUpdateMode:AsRequired
-g StartUpClk:JtagClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g Encrypt:No
projects/vga_ctrl/syn/ise/project/pepExtractor.prj
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work "fsm_scan.vhd"
work "sdcwr.vhd"
work "vga_ctrl_core.vhd"
work "vga_types.vhd"
projects/vga_ctrl/syn/ise/project/prjname.lso
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work
projects/vga_ctrl/syn/ise/project/system.ucf
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#
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE.
#
# (c) Copyright 2005 Xilinx, Inc.
# All rights reserved.
#
CONFIG STEPPING = "ES";
# Bus clock nets
NET sys_clk_in TNM_NET = "sys_clk_in";
TIMESPEC "TS_sys_clk_in" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %;
NET "inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
TIMESPEC TS_unrelate = FROM sys_clk_in TO vga_clk TIG;
NET sys_clk_in LOC = AE14;
NET sys_clk_in IOSTANDARD = LVCMOS33;
NET sys_rstn_in LOC = D6;
NET sys_rstn_in PULLUP;
NET sys_rstn_in TIG;
NET sys_rstn_in IOSTANDARD = LVCMOS33;
////////////////////////////////////////////////////////////////////////////
// Buttons, LEDs, and DIP Switches
////////////////////////////////////////////////////////////////////////////
# GPLED 0-3
NET "sys_led<0>" LOC = "G5"; #GPLED0
NET "sys_led<1>" LOC = "G6"; #GPLED1
NET "sys_led<2>" LOC = "A11"; #GPLED2
NET "sys_led<3>" LOC = "A12"; #GPLED3
# North-East-South-West-Center LEDs
NET "sys_led<4>" LOC = "F9"; # W LED
NET "sys_led<5>" LOC = "E2"; # N LED
NET "sys_led<6>" LOC = "E10"; # E LED
NET "sys_led<7>" LOC = "A5"; # S LED
NET "sys_led<8>" LOC = "C6"; # C LED
NET "sys_led<*>" TIG;
NET "sys_led<*>" SLEW = SLOW;
NET "sys_led<*>" DRIVE = 2;
NET "sys_led<*>" IOSTANDARD = LVCMOS33;
# North-East-South-West-Center Buttons
NET "sys_btn<0>" LOC = "E9"; # W Button
NET "sys_btn<1>" LOC = "E7"; # N Button
NET "sys_btn<2>" LOC = "F10"; # E Button
NET "sys_btn<3>" LOC = "A6"; # S Button
NET "sys_btn<4>" LOC = "B6"; # C Button
NET "sys_btn<*>" TIG;
NET "sys_btn<*>" PULLDOWN;
NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
# Dip Switches 1-8
NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
NET "sys_dip<*>" PULLDOWN;
NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
NET "sys_dip<*>" TIG;
#------------------------------------------------------------------------------
# IO Pad Location Constraints / Properties for TFT VGA LCD Controller
#------------------------------------------------------------------------------
NET sys_vga_blue<0> LOC = M21; # VGA_B0
NET sys_vga_blue<1> LOC = M26; # VGA_B1
NET sys_vga_blue<2> LOC = L26; # VGA_B2
NET sys_vga_blue<3> LOC = C5; # VGA_B3
NET sys_vga_blue<4> LOC = C7; # VGA_B4
NET sys_vga_blue<5> LOC = B7; # VGA_B5
NET sys_vga_blue<6> LOC = G8; # VGA_B6
NET sys_vga_blue<7> LOC = F8; # VGA_B7
NET sys_vga_blue<*> IOSTANDARD = LVCMOS33;
NET sys_vga_blue<*> SLEW = FAST;
NET sys_vga_blue<*> DRIVE = 8;
NET sys_vga_clk LOC = AF8;
NET sys_vga_clk IOSTANDARD = LVDCI_33;
NET sys_vga_clk SLEW = FAST;
NET sys_vga_clk DRIVE = 8;
NET sys_vga_green<0> LOC = M22; # VGA_G0
NET sys_vga_green<1> LOC = M23; # VGA_G1
NET sys_vga_green<2> LOC = M20; # VGA_G2
NET sys_vga_green<3> LOC = E4; # VGA_G3
NET sys_vga_green<4> LOC = D3; # VGA_G4
NET sys_vga_green<5> LOC = H7; # VGA_G5
NET sys_vga_green<6> LOC = H8; # VGA_G6
NET sys_vga_green<7> LOC = C1; # VGA_G7
NET sys_vga_green<*> IOSTANDARD = LVCMOS33;
NET sys_vga_green<*> SLEW = FAST;
NET sys_vga_green<*> DRIVE = 8;
NET sys_vga_hsync LOC = C10;
NET sys_vga_hsync SLEW = FAST;
NET sys_vga_hsync DRIVE = 8;
NET sys_vga_hsync IOSTANDARD = LVCMOS33;
NET sys_vga_red<0> LOC = N23; #VGA_R0
NET sys_vga_red<1> LOC = N24; #VGA_R1
NET sys_vga_red<2> LOC = N25; #VGA_R2
NET sys_vga_red<3> LOC = C2; #VGA_R3
NET sys_vga_red<4> LOC = G7; #VGA_R4
NET sys_vga_red<5> LOC = F7; #VGA_R5
NET sys_vga_red<6> LOC = E5; #VGA_R6
NET sys_vga_red<7> LOC = E6; #VGA_R7
NET sys_vga_red<*> IOSTANDARD = LVCMOS33;
NET sys_vga_red<*> SLEW = FAST;
NET sys_vga_red<*> DRIVE = 8;
NET sys_vga_vsync LOC = A8;
NET sys_vga_vsync SLEW = FAST;
NET sys_vga_vsync DRIVE = 8;
NET sys_vga_vsync IOSTANDARD = LVCMOS33;
NET sys_vga_blank_n LOC = M24;
NET sys_vga_blank_n SLEW = FAST;
NET sys_vga_blank_n DRIVE = 8;
NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
NET sys_vga_sync_n LOC = L23;
NET sys_vga_sync_n SLEW = FAST;
NET sys_vga_sync_n DRIVE = 8;
NET sys_vga_sync_n IOSTANDARD = LVCMOS33;
projects/vga_ctrl/syn/ise/project/tb_vga_ctrl.do
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## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
##
vlib work
vcom -explicit -93 "vga_types.vhd"
vcom -explicit -93 "sdcwr.vhd"
vcom -explicit -93 "fsm_scan.vhd"
vcom -explicit -93 "vga_ctrl_core.vhd"
vcom -explicit -93 "vga_ctrl_top.vhd"
vcom -explicit -93 "tb_vga_ctrl.vhd"
vsim -t 1ps -lib work tb_vga_ctrl_vhd
view wave
do {wave_vga_ctrl.do}
view structure
view signals
run 10us
projects/vga_ctrl/syn/ise/project/tb_vga_ctrl_vhd.udo
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-- ProjNav VHDL simulation template: tb_vga_ctrl_vhd.udo
-- You may edit this file after the line that starts with
-- '-- START' to customize your simulation
-- START user-defined simulation commands
projects/vga_ctrl/syn/ise/project/vga_ctrl_core.lso
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work
projects/vga_ctrl/syn/ise/project/vga_ctrl_core.prj
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vhdl work "sdcwr.vhd"
vhdl work "vga_types.vhd"
vhdl work "fsm_scan.vhd"
vhdl work "vga_ctrl_core.vhd"
projects/vga_ctrl/syn/ise/project/vga_ctrl_top.lso
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work
projects/vga_ctrl/syn/ise/project/vga_ctrl_top.prj
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vhdl work "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
vhdl work "../../../lib/VGA_ctrl/src/vga_types.vhd"
vhdl work "../src/cpu_pkg.vhd"
vhdl work "../../../lib/FIFO/src/gray_counter.vhd"
vhdl work "../../../lib/VGA_ctrl/src/vga_sync.vhd"
vhdl work "../../../lib/VGA_ctrl/src/dpram.vhd"
vhdl work "../../../lib/FIFO/src/async_fifo_ctrl.vhd"
vhdl work "../src/main_irom_ld.vhdl"
vhdl work "../../../lib/VGA_ctrl/src/vga_timing.vhd"
vhdl work "../../../lib/VGA_ctrl/src/linefifo.vhd"
vhdl work "../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
vhdl work "../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
vhdl work "../src/main_xrom_ld.vhdl"
vhdl work "../src/cpu_embedded.vhd"
vhdl work "../../../lib/VGA_ctrl/src/vga_backend.vhd"
vhdl work "../../../lib/VGA_ctrl/src/char_gen.vhd"
vhdl work "../src/vga_ctrl_top.vhd"
projects/vga_ctrl/syn/ise/project/vga_ctrl_top.ut
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-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g ConfigRate:4
-g CclkPin:PullUp
-g M0Pin:PullUp
-g M1Pin:PullUp
-g M2Pin:PullUp
-g ProgPin:PullUp
-g DonePin:PullUp
-g InitPin:Pullup
-g CsPin:Pullup
-g DinPin:Pullup
-g BusyPin:Pullup
-g RdWrPin:Pullup
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0x4A454E53
-g DCIUpdateMode:AsRequired
-g StartUpClk:JtagClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Match_cycle:Auto
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g Encrypt:No
projects/vga_ctrl/syn/ise/project/vga_ctrl_top.xst
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set -tmpdir "./xst/projnav.tmp"
set -xsthdpdir "./xst"
run
-ifn vga_ctrl_top.prj
-ifmt mixed
-ofn vga_ctrl_top
-ofmt NGC
-p xc4vsx35-10-ff668
-top vga_ctrl_top
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-lso vga_ctrl_top.lso
-keep_hierarchy NO
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract YES
-resource_sharing YES
-async_to_sync NO
-use_dsp48 auto
-iobuf YES
-max_fanout 500
-bufg 32
-bufr 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob false
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
projects/vga_ctrl/syn/ise/project/vga_ctrl_top_vhdl.prj
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vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd"
vhdl work "W:\vhdl\projects\vga_ctrl\src\cpu_pkg.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\dpram.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\async_fifo_ctrl.vhd"
vhdl work "W:\vhdl\projects\vga_ctrl\src\main_irom_ld.vhdl"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\linefifo.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
vhdl work "W:\vhdl\projects\vga_ctrl\src\main_xrom_ld.vhdl"
vhdl work "W:\vhdl\projects\vga_ctrl\src\cpu_embedded.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
vhdl work "W:\vhdl\projects\vga_ctrl\src\vga_ctrl_top.vhd"
projects/vga_ctrl/syn/ise/project/vga_types_vhdl.prj
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work "vga_types.vhd"
projects/vga_ctrl/syn/ise/project/wave_vga_ctrl.do
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_vga_ctrl_vhd/sys_rstn_in
add wave -noupdate -format Logic /tb_vga_ctrl_vhd/sys_clk_in
add wave -noupdate -format Logic /tb_vga_ctrl_vhd/sys_vga_clk
add wave -noupdate -format Logic /tb_vga_ctrl_vhd/uut/hsync_i
add wave -noupdate -format Logic /tb_vga_ctrl_vhd/uut/vsync_i
add wave -noupdate -format Literal /tb_vga_ctrl_vhd/sys_vga_red
add wave -noupdate -format Literal /tb_vga_ctrl_vhd/sys_vga_green
add wave -noupdate -format Literal /tb_vga_ctrl_vhd/sys_vga_blue
add wave -noupdate -format Logic /tb_vga_ctrl_vhd/sys_vga_clk
add wave -noupdate -format Logic /tb_vga_ctrl_vhd/sys_vga_hsync
add wave -noupdate -format Logic /tb_vga_ctrl_vhd/sys_vga_vsync
add wave -noupdate -format Logic /tb_vga_ctrl_vhd/uut/is_scan_h
add wave -noupdate -format Logic /tb_vga_ctrl_vhd/uut/is_scan_v
add wave -noupdate -format Logic /tb_vga_ctrl_vhd/uut/h_scan_rdy
add wave -noupdate -format Logic /tb_vga_ctrl_vhd/uut/v_scan_rdy
add wave -noupdate -format Logic /tb_vga_ctrl_vhd/sys_dcm_locked
add wave -noupdate -format Logic /tb_vga_ctrl_vhd/uut/clk_scan_rdy
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1908400 ps} 0}
configure wave -namecolwidth 212
configure wave -valuecolwidth 68
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {993377 ps} {2954189 ps}