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- Added bus error signals for IBE/DBE generation

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git-svn-id: http://moon:8086/svn/vhdl/trunk@32 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2008-10-09 11:51:17 +00:00
parent 2a0d20f4b2
commit 098b5982b2
1 changed files with 2 additions and 0 deletions
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lib/CPUs/MIPS/src/core/mips_pipeline.vhd
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@@ -35,10 +35,12 @@ entity pipeline is
clk : in STD_LOGIC; clk : in STD_LOGIC;
halt : in STD_LOGIC; halt : in STD_LOGIC;
int : in unsigned(5 downto 0); int : in unsigned(5 downto 0);
imem_err : in STD_LOGIC;
imem_rdy : in STD_LOGIC; imem_rdy : in STD_LOGIC;
imem_en : out STD_LOGIC; imem_en : out STD_LOGIC;
imem_addr : out word_t; imem_addr : out word_t;
imem_data : in word_t; imem_data : in word_t;
dmem_err : in STD_LOGIC;
dmem_rdy : in STD_LOGIC; dmem_rdy : in STD_LOGIC;
dmem_en : out STD_LOGIC; dmem_en : out STD_LOGIC;
dmem_re : out STD_LOGIC; dmem_re : out STD_LOGIC;