From 08e1a114c487d4edb0011cdc697f50d5e58dc89c Mon Sep 17 00:00:00 2001 From: jens Date: Thu, 8 Sep 2022 10:46:03 +0200 Subject: [PATCH] Use genwopt --- lib/CPUs/MIPS/ghdl/tb_mips_top.gtkw | 16 +- lib/CPUs/MIPS/ghdl/tb_mips_top.make | 3 +- lib/CPUs/MIPS/ghdl/tb_mips_top.wopt.templ | 1062 +++++++++++++++++++++ 3 files changed, 1073 insertions(+), 8 deletions(-) create mode 100644 lib/CPUs/MIPS/ghdl/tb_mips_top.wopt.templ diff --git a/lib/CPUs/MIPS/ghdl/tb_mips_top.gtkw b/lib/CPUs/MIPS/ghdl/tb_mips_top.gtkw index 4a18159..71227c4 100644 --- a/lib/CPUs/MIPS/ghdl/tb_mips_top.gtkw +++ b/lib/CPUs/MIPS/ghdl/tb_mips_top.gtkw @@ -1,13 +1,15 @@ [*] [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI -[*] Tue Mar 23 20:38:28 2021 +[*] Thu Sep 8 07:15:28 2022 [*] +[dumpfile] "/home/jens/work/projects/vhdl/lib/CPUs/MIPS/ghdl/build/tb_mips_top/tb_mips_top.fst" +[dumpfile_mtime] "Thu Sep 8 07:12:59 2022" +[dumpfile_size] 2671748 +[savefile] "/home/jens/work/projects/vhdl/lib/CPUs/MIPS/ghdl/tb_mips_top.gtkw" [timestart] 0 -[size] 1856 1136 -[pos] -51 -51 +[size] 1854 1136 +[pos] -1 -1 *-37.625370 355000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] tb_mips_top. -[treeopen] tb_mips_top.inst_uart. [sst_width] 233 [signals_width] 288 [sst_expanded] 1 @@ -16,11 +18,11 @@ clk rst @22 -flash_a[16:0] flash_d[31:0] gpi_0[31:0] gpo_0[31:0] -@23 inst_uart.reg_uart_tx[7:0] +@23 +uut.addr_o[31:0] [pattern_trace] 1 [pattern_trace] 0 diff --git a/lib/CPUs/MIPS/ghdl/tb_mips_top.make b/lib/CPUs/MIPS/ghdl/tb_mips_top.make index 077ae0e..0ff06a9 100644 --- a/lib/CPUs/MIPS/ghdl/tb_mips_top.make +++ b/lib/CPUs/MIPS/ghdl/tb_mips_top.make @@ -32,7 +32,8 @@ SRCS += ../src/tb_mips_top.vhd # Compile TARGET := tb_mips_top ENTITY := tb_mips_top -RUN_TIME ?= 1500us +RUN_TIME := 150us +WAVE_FORMAT := ghw include $(VHDL_MAKE_HOME)/ghdl.mk diff --git a/lib/CPUs/MIPS/ghdl/tb_mips_top.wopt.templ b/lib/CPUs/MIPS/ghdl/tb_mips_top.wopt.templ new file mode 100644 index 0000000..7ee5a6f --- /dev/null +++ b/lib/CPUs/MIPS/ghdl/tb_mips_top.wopt.templ @@ -0,0 +1,1062 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/tb_mips_top/debug +/tb_mips_top/nmi +/tb_mips_top/rst +/tb_mips_top/clk +/tb_mips_top/eb +/tb_mips_top/ack_i +/tb_mips_top/srdy_i +/tb_mips_top/addr_o +/tb_mips_top/dat_i +/tb_mips_top/dat_o +/tb_mips_top/we_o +/tb_mips_top/sel_o +/tb_mips_top/cyc_o +/tb_mips_top/stb_o +/tb_mips_top/mrdy_o +/tb_mips_top/int +/tb_mips_top/cyc_i_rom +/tb_mips_top/ack_o_rom +/tb_mips_top/srdy_o_rom +/tb_mips_top/dat_o_rom +/tb_mips_top/cyc_i_flash +/tb_mips_top/ack_o_flash +/tb_mips_top/srdy_o_flash +/tb_mips_top/dat_o_flash +/tb_mips_top/cyc_i_sram +/tb_mips_top/ack_o_sram +/tb_mips_top/srdy_o_sram +/tb_mips_top/dat_o_sram +/tb_mips_top/cyc_i_gpio +/tb_mips_top/ack_o_gpio +/tb_mips_top/srdy_o_gpio +/tb_mips_top/dat_o_gpio +/tb_mips_top/cyc_i_uart +/tb_mips_top/ack_o_uart +/tb_mips_top/srdy_o_uart +/tb_mips_top/dat_o_uart +/tb_mips_top/flash_cs_n +/tb_mips_top/flash_we_n +/tb_mips_top/flash_oe_n +/tb_mips_top/flash_be_n +/tb_mips_top/sram_cs_n +/tb_mips_top/sram_be_n +/tb_mips_top/sram_wr_n +/tb_mips_top/sram_oe_n +/tb_mips_top/sram_a +/tb_mips_top/sram_d +/tb_mips_top/flash_a +/tb_mips_top/flash_d +/tb_mips_top/flash_page_mode_en +/tb_mips_top/gpi_0 +/tb_mips_top/gpo_0 +/tb_mips_top/int_timer +/tb_mips_top/int_uart +/tb_mips_top/rx +/tb_mips_top/tx +/tb_mips_top/mem_area +/tb_mips_top/sram_data +/tb_mips_top/flash_data +/tb_mips_top/uut/debug +/tb_mips_top/uut/eb +/tb_mips_top/uut/nmi +/tb_mips_top/uut/cpu_clk +/tb_mips_top/uut/rst_i +/tb_mips_top/uut/clk_i +/tb_mips_top/uut/ack_i +/tb_mips_top/uut/srdy_i +/tb_mips_top/uut/addr_o +/tb_mips_top/uut/dat_i +/tb_mips_top/uut/dat_o +/tb_mips_top/uut/we_o +/tb_mips_top/uut/sel_o +/tb_mips_top/uut/cyc_o +/tb_mips_top/uut/stb_o +/tb_mips_top/uut/mrdy_o +/tb_mips_top/uut/int +/tb_mips_top/uut/imem_err +/tb_mips_top/uut/imem_rdy +/tb_mips_top/uut/imem_en +/tb_mips_top/uut/imem_addr +/tb_mips_top/uut/imem_din +/tb_mips_top/uut/dmem_err +/tb_mips_top/uut/dmem_rdy +/tb_mips_top/uut/dmem_en +/tb_mips_top/uut/dmem_we +/tb_mips_top/uut/dmem_addr +/tb_mips_top/uut/dmem_dout +/tb_mips_top/uut/dmem_din +/tb_mips_top/uut/dmem_be +/tb_mips_top/uut/biu_rst +/tb_mips_top/uut/cpu_rst +/tb_mips_top/uut/cpu_run +/tb_mips_top/uut/pipe_cop_ir +/tb_mips_top/uut/pipe_cop_ir_en +/tb_mips_top/uut/pipe_cop_din +/tb_mips_top/uut/pipe_cop_dout +/tb_mips_top/uut/pipe_c0_ctrl_out +/tb_mips_top/uut/pipe_c0_ctrl_in +/tb_mips_top/uut/inst_pipeline/rst +/tb_mips_top/uut/inst_pipeline/clk +/tb_mips_top/uut/inst_pipeline/ce +/tb_mips_top/uut/inst_pipeline/imem_rdy +/tb_mips_top/uut/inst_pipeline/imem_en +/tb_mips_top/uut/inst_pipeline/imem_addr +/tb_mips_top/uut/inst_pipeline/imem_data +/tb_mips_top/uut/inst_pipeline/dmem_rdy +/tb_mips_top/uut/inst_pipeline/dmem_en +/tb_mips_top/uut/inst_pipeline/dmem_we +/tb_mips_top/uut/inst_pipeline/dmem_be +/tb_mips_top/uut/inst_pipeline/dmem_addr +/tb_mips_top/uut/inst_pipeline/dmem_din +/tb_mips_top/uut/inst_pipeline/dmem_dout +/tb_mips_top/uut/inst_pipeline/cop_ir +/tb_mips_top/uut/inst_pipeline/cop_ir_en +/tb_mips_top/uut/inst_pipeline/cop_din +/tb_mips_top/uut/inst_pipeline/cop_dout +/tb_mips_top/uut/inst_pipeline/c0_ctrl_out +/tb_mips_top/uut/inst_pipeline/c0_ctrl_in +/tb_mips_top/uut/inst_pipeline/id_stage +/tb_mips_top/uut/inst_pipeline/ex_stage +/tb_mips_top/uut/inst_pipeline/mem_stage +/tb_mips_top/uut/inst_pipeline/wb_stage +/tb_mips_top/uut/inst_pipeline/hdu +/tb_mips_top/uut/inst_pipeline/sdu +/tb_mips_top/uut/inst_pipeline/reg_a +/tb_mips_top/uut/inst_pipeline/reg_b +/tb_mips_top/uut/inst_pipeline/branch_taken +/tb_mips_top/uut/inst_pipeline/alu_result +/tb_mips_top/uut/inst_pipeline/mul_result +/tb_mips_top/uut/inst_pipeline/mul_busy +/tb_mips_top/uut/inst_pipeline/ex_events_instr +/tb_mips_top/uut/inst_pipeline/ex_events_alu +/tb_mips_top/uut/inst_pipeline/ex_events_mem +/tb_mips_top/uut/inst_pipeline/ex_events +/tb_mips_top/uut/inst_pipeline/mem_events +/tb_mips_top/uut/inst_pipeline/bcu_op_a +/tb_mips_top/uut/inst_pipeline/bcu_op_b +/tb_mips_top/uut/inst_pipeline/bcu_flags +/tb_mips_top/uut/inst_pipeline/vaddr +/tb_mips_top/uut/inst_pipeline/dmem_src +/tb_mips_top/uut/inst_pipeline/pc +/tb_mips_top/uut/inst_pipeline/pc_branch +/tb_mips_top/uut/inst_pipeline/pc_curr +/tb_mips_top/uut/inst_pipeline/pc_last +/tb_mips_top/uut/inst_pipeline/pc_nxt +/tb_mips_top/uut/inst_pipeline/pc_branch_take +/tb_mips_top/uut/inst_pipeline/id_ctrl_branch +/tb_mips_top/uut/inst_pipeline/ex_ctrl_branch +/tb_mips_top/uut/inst_pipeline/mem_ctrl_branch +/tb_mips_top/uut/inst_pipeline/sdu_id_stall +/tb_mips_top/uut/inst_pipeline/sdu_id_nop +/tb_mips_top/uut/inst_pipeline/c0_ctrl_in_exc_pending +/tb_mips_top/uut/inst_pipeline/c0_ctrl_in_exc_inject +/tb_mips_top/uut/inst_pipeline/inst_muldiv/rst +/tb_mips_top/uut/inst_pipeline/inst_muldiv/clk +/tb_mips_top/uut/inst_pipeline/inst_muldiv/hilo_we +/tb_mips_top/uut/inst_pipeline/inst_muldiv/din_hi +/tb_mips_top/uut/inst_pipeline/inst_muldiv/din_lo +/tb_mips_top/uut/inst_pipeline/inst_muldiv/mul_divn +/tb_mips_top/uut/inst_pipeline/inst_muldiv/start +/tb_mips_top/uut/inst_pipeline/inst_muldiv/s_un +/tb_mips_top/uut/inst_pipeline/inst_muldiv/hilo_sel +/tb_mips_top/uut/inst_pipeline/inst_muldiv/busy +/tb_mips_top/uut/inst_pipeline/inst_muldiv/dout +/tb_mips_top/uut/inst_pipeline/inst_muldiv/pprod +/tb_mips_top/uut/inst_pipeline/inst_muldiv/sign1 +/tb_mips_top/uut/inst_pipeline/inst_muldiv/sign2 +/tb_mips_top/uut/inst_pipeline/inst_muldiv/s1_r +/tb_mips_top/uut/inst_pipeline/inst_muldiv/s2_r +/tb_mips_top/uut/inst_pipeline/inst_muldiv/sr_r +/tb_mips_top/uut/inst_pipeline/inst_muldiv/cy +/tb_mips_top/uut/inst_pipeline/inst_muldiv/mul_start +/tb_mips_top/uut/inst_pipeline/inst_muldiv/mul_en +/tb_mips_top/uut/inst_pipeline/inst_muldiv/sum_en +/tb_mips_top/uut/inst_pipeline/inst_muldiv/pre_sum_vld +/tb_mips_top/uut/inst_pipeline/inst_muldiv/pp_reg +/tb_mips_top/uut/inst_pipeline/inst_muldiv/pre_const +/tb_mips_top/uut/inst_pipeline/inst_muldiv/result +/tb_mips_top/uut/inst_pipeline/inst_muldiv/add_op1 +/tb_mips_top/uut/inst_pipeline/inst_muldiv/add_op2 +/tb_mips_top/uut/inst_pipeline/inst_muldiv/add_res +/tb_mips_top/uut/inst_pipeline/inst_muldiv/ppadd_op1 +/tb_mips_top/uut/inst_pipeline/inst_muldiv/ppadd_op2 +/tb_mips_top/uut/inst_pipeline/inst_muldiv/ppadd_res +/tb_mips_top/uut/inst_pipeline/inst_muldiv/ppadd_cyi +/tb_mips_top/uut/inst_pipeline/inst_muldiv/ppadd_cyo +/tb_mips_top/uut/inst_pipeline/inst_muldiv/pp_op1_r +/tb_mips_top/uut/inst_pipeline/inst_muldiv/pp_op1 +/tb_mips_top/uut/inst_pipeline/inst_muldiv/pp_op2 +/tb_mips_top/uut/inst_pipeline/inst_muldiv/pp_op2_r +/tb_mips_top/uut/inst_pipeline/inst_muldiv/bsy +/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_add_res +/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_add_op1 +/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_add_op2 +/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_add_cyi +/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_qbit +/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_start +/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_en +/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_a +/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_m +/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_m_n +/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_q +/tb_mips_top/uut/inst_pipeline/inst_muldiv/s +/tb_mips_top/uut/inst_pipeline/inst_muldiv/sn +/tb_mips_top/uut/inst_pipeline/inst_muldiv/cycle_cnt +/tb_mips_top/uut/inst_pipeline/inst_muldiv/cycle_cnt_preset +/tb_mips_top/uut/inst_pipeline/inst_muldiv/cycle_cnt_load +/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_fin_en +/tb_mips_top/uut/inst_pipeline/inst_reg_dual/clk_w +/tb_mips_top/uut/inst_pipeline/inst_reg_dual/we +/tb_mips_top/uut/inst_pipeline/inst_reg_dual/en +/tb_mips_top/uut/inst_pipeline/inst_reg_dual/wptr +/tb_mips_top/uut/inst_pipeline/inst_reg_dual/din +/tb_mips_top/uut/inst_pipeline/inst_reg_dual/rptr_a +/tb_mips_top/uut/inst_pipeline/inst_reg_dual/rptr_b +/tb_mips_top/uut/inst_pipeline/inst_reg_dual/dout_a +/tb_mips_top/uut/inst_pipeline/inst_reg_dual/dout_b +/tb_mips_top/uut/inst_pipeline/inst_reg_dual/reg_mem +/tb_mips_top/uut/inst_pipeline/inst_shifter/shift_ctrl +/tb_mips_top/uut/inst_pipeline/inst_shifter/din +/tb_mips_top/uut/inst_pipeline/inst_shifter/dout +/tb_mips_top/uut/inst_pipeline/inst_shifter/rot_data +/tb_mips_top/uut/inst_pipeline/inst_shifter/sa_rnd +/tb_mips_top/uut/inst_pipeline/inst_shifter/fill +/tb_mips_top/uut/inst_pipeline/inst_shifter/fill_mask +/tb_mips_top/uut/inst_pipeline/inst_shifter/fill_mask_addr +/tb_mips_top/uut/inst_pipeline/inst_shifter/dout_filled +/tb_mips_top/uut/inst_pipeline/inst_alu/op1_in +/tb_mips_top/uut/inst_pipeline/inst_alu/op2_in +/tb_mips_top/uut/inst_pipeline/inst_alu/op2_shifted +/tb_mips_top/uut/inst_pipeline/inst_alu/ctrl +/tb_mips_top/uut/inst_pipeline/inst_alu/result +/tb_mips_top/uut/inst_pipeline/inst_alu/flags +/tb_mips_top/uut/inst_pipeline/inst_alu/sum_res +/tb_mips_top/uut/inst_pipeline/inst_alu/and_res +/tb_mips_top/uut/inst_pipeline/inst_alu/xor_res +/tb_mips_top/uut/inst_pipeline/inst_alu/nor_res +/tb_mips_top/uut/inst_pipeline/inst_alu/or_res +/tb_mips_top/uut/inst_pipeline/inst_alu/eq +/tb_mips_top/uut/inst_pipeline/inst_alu/sa +/tb_mips_top/uut/inst_pipeline/inst_alu/sb +/tb_mips_top/uut/inst_pipeline/inst_alu/sr +/tb_mips_top/uut/inst_pipeline/inst_alu/c +/tb_mips_top/uut/inst_pipeline/inst_alu/lts +/tb_mips_top/uut/inst_pipeline/inst_alu/ltu +/tb_mips_top/uut/inst_pipeline/inst_bcu/op1_in +/tb_mips_top/uut/inst_pipeline/inst_bcu/op2_in +/tb_mips_top/uut/inst_pipeline/inst_bcu/flags +/tb_mips_top/uut/inst_cop/rst +/tb_mips_top/uut/inst_cop/clk +/tb_mips_top/uut/inst_cop/eb +/tb_mips_top/uut/inst_cop/int +/tb_mips_top/uut/inst_cop/nmi +/tb_mips_top/uut/inst_cop/ir_en +/tb_mips_top/uut/inst_cop/ir +/tb_mips_top/uut/inst_cop/ctrl_in +/tb_mips_top/uut/inst_cop/ctrl_out +/tb_mips_top/uut/inst_cop/din +/tb_mips_top/uut/inst_cop/dout +/tb_mips_top/uut/inst_cop/epc +/tb_mips_top/uut/inst_cop/cause +/tb_mips_top/uut/inst_cop/status +/tb_mips_top/uut/inst_cop/imem_addr +/tb_mips_top/uut/inst_cop/imem_addr_we +/tb_mips_top/uut/inst_cop/badvaddr +/tb_mips_top/uut/inst_cop/exc_code +/tb_mips_top/uut/inst_cop/test_reg +/tb_mips_top/uut/inst_cop/test_reg_we +/tb_mips_top/uut/inst_cop/stat_reg_we +/tb_mips_top/uut/inst_cop/epc_reg_we +/tb_mips_top/uut/inst_cop/code_reg_we +/tb_mips_top/uut/inst_cop/ip_reg_we +/tb_mips_top/uut/inst_cop/bd +/tb_mips_top/uut/inst_cop/sw_int +/tb_mips_top/uut/inst_cop/ip +/tb_mips_top/uut/inst_cop/im +/tb_mips_top/uut/inst_cop/status_save +/tb_mips_top/uut/inst_cop/status_rest +/tb_mips_top/uut/inst_cop/eflags +/tb_mips_top/uut/inst_cop/eb_reg +/tb_mips_top/uut/inst_cop/icache_info +/tb_mips_top/uut/inst_cop/dcache_info +/tb_mips_top/uut/inst_cop/reg_rptr +/tb_mips_top/uut/inst_cop/reg_wptr +/tb_mips_top/uut/inst_cop/inject_exc +/tb_mips_top/uut/inst_cop/latch_vect_en +/tb_mips_top/uut/inst_cop/int_nmi +/tb_mips_top/uut/inst_cop/nmi_asserted +/tb_mips_top/uut/inst_cop/cop_pipe_id +/tb_mips_top/uut/inst_cop/cop_pipe_ex +/tb_mips_top/uut/inst_cop/exc_state +/tb_mips_top/uut/inst_cop/exc_staten +/tb_mips_top/uut/inst_biu/rst_i +/tb_mips_top/uut/inst_biu/clk_i +/tb_mips_top/uut/inst_biu/ack_i +/tb_mips_top/uut/inst_biu/srdy_i +/tb_mips_top/uut/inst_biu/addr_o +/tb_mips_top/uut/inst_biu/dat_i +/tb_mips_top/uut/inst_biu/dat_o +/tb_mips_top/uut/inst_biu/we_o +/tb_mips_top/uut/inst_biu/sel_o +/tb_mips_top/uut/inst_biu/cyc_o +/tb_mips_top/uut/inst_biu/stb_o +/tb_mips_top/uut/inst_biu/mrdy_o +/tb_mips_top/uut/inst_biu/cop0_ctrl_in +/tb_mips_top/uut/inst_biu/cpu_clk +/tb_mips_top/uut/inst_biu/cpu_imem_err +/tb_mips_top/uut/inst_biu/cpu_imem_rdy +/tb_mips_top/uut/inst_biu/cpu_imem_en +/tb_mips_top/uut/inst_biu/cpu_imem_addr +/tb_mips_top/uut/inst_biu/cpu_imem_din +/tb_mips_top/uut/inst_biu/cpu_dmem_err +/tb_mips_top/uut/inst_biu/cpu_dmem_rdy +/tb_mips_top/uut/inst_biu/cpu_dmem_en +/tb_mips_top/uut/inst_biu/cpu_dmem_we +/tb_mips_top/uut/inst_biu/cpu_dmem_be +/tb_mips_top/uut/inst_biu/cpu_dmem_dout +/tb_mips_top/uut/inst_biu/cpu_dmem_din +/tb_mips_top/uut/inst_biu/cpu_dmem_addr +/tb_mips_top/uut/inst_biu/s +/tb_mips_top/uut/inst_biu/sn +/tb_mips_top/uut/inst_biu/bus_idle +/tb_mips_top/uut/inst_biu/busy +/tb_mips_top/uut/inst_biu/dmem_be +/tb_mips_top/uut/inst_biu/dcache_dout +/tb_mips_top/uut/inst_biu/dcache_mem_gnt +/tb_mips_top/uut/inst_biu/icache_mem_gnt +/tb_mips_top/uut/inst_biu/dmem_mem_wr_gnt +/tb_mips_top/uut/inst_biu/dmem_mem_rd_gnt +/tb_mips_top/uut/inst_biu/dcache_busy +/tb_mips_top/uut/inst_biu/icache_busy +/tb_mips_top/uut/inst_biu/cyc_o_icache +/tb_mips_top/uut/inst_biu/cyc_o_dcache +/tb_mips_top/uut/inst_biu/cyc_o_dmem_rd +/tb_mips_top/uut/inst_biu/cyc_o_dmem_wr +/tb_mips_top/uut/inst_biu/srdy_i_icache +/tb_mips_top/uut/inst_biu/srdy_i_dcache +/tb_mips_top/uut/inst_biu/mrdy_o_icache +/tb_mips_top/uut/inst_biu/mrdy_o_dcache +/tb_mips_top/uut/inst_biu/addr_o_icache +/tb_mips_top/uut/inst_biu/addr_o_dcache +/tb_mips_top/uut/inst_biu/addr_o_dmem_rd +/tb_mips_top/uut/inst_biu/addr_o_dmem_wr +/tb_mips_top/uut/inst_biu/stb_o_icache +/tb_mips_top/uut/inst_biu/stb_o_dcache +/tb_mips_top/uut/inst_biu/stb_o_dmem_rd +/tb_mips_top/uut/inst_biu/stb_o_dmem_wr +/tb_mips_top/uut/inst_biu/dat_i_dmem_rd +/tb_mips_top/uut/inst_biu/dat_o_dmem_wr +/tb_mips_top/uut/inst_biu/sel_o_dmem_wr +/tb_mips_top/uut/inst_biu/sel_o_dmem_rd +/tb_mips_top/uut/inst_biu/dcached +/tb_mips_top/uut/inst_biu/dcache_en2 +/tb_mips_top/uut/inst_biu/dcache_en +/tb_mips_top/uut/inst_biu/uncached_access +/tb_mips_top/uut/inst_biu/ack +/tb_mips_top/uut/inst_biu/dat +/tb_mips_top/uut/inst_biu/bus_timeout_cnt +/tb_mips_top/uut/inst_biu/bus_timeout +/tb_mips_top/uut/inst_biu/bout_fifo_din +/tb_mips_top/uut/inst_biu/bout_fifo_dout +/tb_mips_top/uut/inst_biu/bout_fifo_re +/tb_mips_top/uut/inst_biu/bout_fifo_we +/tb_mips_top/uut/inst_biu/bout_fifo_full +/tb_mips_top/uut/inst_biu/bout_fifo_empty +/tb_mips_top/uut/inst_biu/bout_rdy +/tb_mips_top/uut/inst_biu/bin_fifo_din +/tb_mips_top/uut/inst_biu/bin_fifo_dout +/tb_mips_top/uut/inst_biu/bin_fifo_re +/tb_mips_top/uut/inst_biu/bin_fifo_we +/tb_mips_top/uut/inst_biu/bin_fifo_full +/tb_mips_top/uut/inst_biu/bin_fifo_empty +/tb_mips_top/uut/inst_biu/write_fifo_din +/tb_mips_top/uut/inst_biu/write_fifo_dout +/tb_mips_top/uut/inst_biu/write_fifo_re +/tb_mips_top/uut/inst_biu/write_fifo_we +/tb_mips_top/uut/inst_biu/write_fifo_full +/tb_mips_top/uut/inst_biu/write_fifo_empty +/tb_mips_top/uut/inst_biu/read_cycle +/tb_mips_top/uut/inst_biu/inst_icache/rst_i +/tb_mips_top/uut/inst_biu/inst_icache/clk_i +/tb_mips_top/uut/inst_biu/inst_icache/ack_i +/tb_mips_top/uut/inst_biu/inst_icache/srdy_i +/tb_mips_top/uut/inst_biu/inst_icache/mrdy_o +/tb_mips_top/uut/inst_biu/inst_icache/addr_o +/tb_mips_top/uut/inst_biu/inst_icache/dat_i +/tb_mips_top/uut/inst_biu/inst_icache/stb_o +/tb_mips_top/uut/inst_biu/inst_icache/cyc_o +/tb_mips_top/uut/inst_biu/inst_icache/ctrl +/tb_mips_top/uut/inst_biu/inst_icache/cpu_en +/tb_mips_top/uut/inst_biu/inst_icache/cpu_addr +/tb_mips_top/uut/inst_biu/inst_icache/cpu_dout +/tb_mips_top/uut/inst_biu/inst_icache/cpu_busy +/tb_mips_top/uut/inst_biu/inst_icache/s +/tb_mips_top/uut/inst_biu/inst_icache/sn +/tb_mips_top/uut/inst_biu/inst_icache/cache_req +/tb_mips_top/uut/inst_biu/inst_icache/cache_ack +/tb_mips_top/uut/inst_biu/inst_icache/cache_busy +/tb_mips_top/uut/inst_biu/inst_icache/cache_hit +/tb_mips_top/uut/inst_biu/inst_icache/tag_match +/tb_mips_top/uut/inst_biu/inst_icache/cache_hit_inv +/tb_mips_top/uut/inst_biu/inst_icache/tag_match_inv +/tb_mips_top/uut/inst_biu/inst_icache/request_addr +/tb_mips_top/uut/inst_biu/inst_icache/fill_addr +/tb_mips_top/uut/inst_biu/inst_icache/cache_index_inv +/tb_mips_top/uut/inst_biu/inst_icache/tag_inv +/tb_mips_top/uut/inst_biu/inst_icache/tag_reg_inv +/tb_mips_top/uut/inst_biu/inst_icache/cache_entry_in +/tb_mips_top/uut/inst_biu/inst_icache/cache_entry_out +/tb_mips_top/uut/inst_biu/inst_icache/cache_entry_out_inv +/tb_mips_top/uut/inst_biu/inst_icache/data_ram_addr_rd +/tb_mips_top/uut/inst_biu/inst_icache/data_ram_data_rd +/tb_mips_top/uut/inst_biu/inst_icache/data_ram_addr_wr +/tb_mips_top/uut/inst_biu/inst_icache/data_ram_data_wr +/tb_mips_top/uut/inst_biu/inst_icache/data_ram_we +/tb_mips_top/uut/inst_biu/inst_icache/data_ram_re +/tb_mips_top/uut/inst_biu/inst_icache/tag_ram_addr_rd +/tb_mips_top/uut/inst_biu/inst_icache/tag_ram_data_rd +/tb_mips_top/uut/inst_biu/inst_icache/tag_ram_data_rd_inv +/tb_mips_top/uut/inst_biu/inst_icache/tag_ram_addr_wr +/tb_mips_top/uut/inst_biu/inst_icache/tag_ram_data_wr +/tb_mips_top/uut/inst_biu/inst_icache/tag_ram_we +/tb_mips_top/uut/inst_biu/inst_icache/fill_count +/tb_mips_top/uut/inst_biu/inst_icache/fill_count_en +/tb_mips_top/uut/inst_biu/inst_icache/fill_count_rdy +/tb_mips_top/uut/inst_biu/inst_icache/flush_load_en +/tb_mips_top/uut/inst_biu/inst_icache/flush_addr_preset +/tb_mips_top/uut/inst_biu/inst_icache/flush_count_preset +/tb_mips_top/uut/inst_biu/inst_icache/flush_addr +/tb_mips_top/uut/inst_biu/inst_icache/flush_count +/tb_mips_top/uut/inst_biu/inst_icache/flush_count_en +/tb_mips_top/uut/inst_biu/inst_icache/flush_count_rdy +/tb_mips_top/uut/inst_biu/inst_icache/request_count +/tb_mips_top/uut/inst_biu/inst_icache/request_count_en +/tb_mips_top/uut/inst_biu/inst_icache/request_count_rdy +/tb_mips_top/uut/inst_biu/inst_icache/was_miss +/tb_mips_top/uut/inst_biu/inst_icache/invalidate_all +/tb_mips_top/uut/inst_biu/inst_icache/invalidate_ack +/tb_mips_top/uut/inst_biu/inst_icache/invalidate_en +/tb_mips_top/uut/inst_biu/inst_icache/invalidate_req +/tb_mips_top/uut/inst_biu/inst_icache/dat_i_r +/tb_mips_top/uut/inst_biu/inst_icache/ack_i_r +/tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/clk_a +/tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/clk_b +/tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/re_a +/tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/re_b +/tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/we_a +/tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/we_b +/tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/addr_a +/tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/addr_b +/tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/din_a +/tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/din_b +/tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/dout_a +/tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/dout_b +/tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/addr_a_r +/tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/addr_b_r +/tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/ram +/tb_mips_top/uut/inst_biu/inst_icache/inst_data_ram/clk_a +/tb_mips_top/uut/inst_biu/inst_icache/inst_data_ram/clk_b +/tb_mips_top/uut/inst_biu/inst_icache/inst_data_ram/we_a +/tb_mips_top/uut/inst_biu/inst_icache/inst_data_ram/re_b +/tb_mips_top/uut/inst_biu/inst_icache/inst_data_ram/addr_a +/tb_mips_top/uut/inst_biu/inst_icache/inst_data_ram/addr_b +/tb_mips_top/uut/inst_biu/inst_icache/inst_data_ram/din_a +/tb_mips_top/uut/inst_biu/inst_icache/inst_data_ram/dout_b +/tb_mips_top/uut/inst_biu/inst_icache/inst_data_ram/ram +/tb_mips_top/uut/inst_biu/inst_icache/inst_data_ram/addr_b_r +/tb_mips_top/uut/inst_biu/inst_dcache/rst_i +/tb_mips_top/uut/inst_biu/inst_dcache/clk_i +/tb_mips_top/uut/inst_biu/inst_dcache/ack_i +/tb_mips_top/uut/inst_biu/inst_dcache/srdy_i +/tb_mips_top/uut/inst_biu/inst_dcache/mrdy_o +/tb_mips_top/uut/inst_biu/inst_dcache/addr_o +/tb_mips_top/uut/inst_biu/inst_dcache/dat_i +/tb_mips_top/uut/inst_biu/inst_dcache/stb_o +/tb_mips_top/uut/inst_biu/inst_dcache/cyc_o +/tb_mips_top/uut/inst_biu/inst_dcache/ctrl +/tb_mips_top/uut/inst_biu/inst_dcache/cpu_en +/tb_mips_top/uut/inst_biu/inst_dcache/cpu_we +/tb_mips_top/uut/inst_biu/inst_dcache/cpu_be +/tb_mips_top/uut/inst_biu/inst_dcache/cpu_addr +/tb_mips_top/uut/inst_biu/inst_dcache/cpu_din +/tb_mips_top/uut/inst_biu/inst_dcache/cpu_dout +/tb_mips_top/uut/inst_biu/inst_dcache/cpu_busy +/tb_mips_top/uut/inst_biu/inst_dcache/s +/tb_mips_top/uut/inst_biu/inst_dcache/sn +/tb_mips_top/uut/inst_biu/inst_dcache/cache_req +/tb_mips_top/uut/inst_biu/inst_dcache/cache_ack +/tb_mips_top/uut/inst_biu/inst_dcache/cache_busy +/tb_mips_top/uut/inst_biu/inst_dcache/cache_hit +/tb_mips_top/uut/inst_biu/inst_dcache/tag_match +/tb_mips_top/uut/inst_biu/inst_dcache/cache_hit_inv +/tb_mips_top/uut/inst_biu/inst_dcache/tag_match_inv +/tb_mips_top/uut/inst_biu/inst_dcache/request_addr +/tb_mips_top/uut/inst_biu/inst_dcache/fill_addr +/tb_mips_top/uut/inst_biu/inst_dcache/cache_index_inv +/tb_mips_top/uut/inst_biu/inst_dcache/tag_inv +/tb_mips_top/uut/inst_biu/inst_dcache/tag_reg_inv +/tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_in +/tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_out +/tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_out_inv +/tb_mips_top/uut/inst_biu/inst_dcache/cpu_data_ram_addr +/tb_mips_top/uut/inst_biu/inst_dcache/cpu_data_ram_dout +/tb_mips_top/uut/inst_biu/inst_dcache/cpu_data_reg +/tb_mips_top/uut/inst_biu/inst_dcache/cpu_be_reg +/tb_mips_top/uut/inst_biu/inst_dcache/cpu_we_reg +/tb_mips_top/uut/inst_biu/inst_dcache/ctrl_data_ram_addr +/tb_mips_top/uut/inst_biu/inst_dcache/ctrl_data_ram_we +/tb_mips_top/uut/inst_biu/inst_dcache/cpu_data_ram_we +/tb_mips_top/uut/inst_biu/inst_dcache/cpu_we2 +/tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_addr_rd +/tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_dout +/tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_dout_inv +/tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_addr_wr +/tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_din +/tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_we +/tb_mips_top/uut/inst_biu/inst_dcache/fill_count +/tb_mips_top/uut/inst_biu/inst_dcache/fill_count_en +/tb_mips_top/uut/inst_biu/inst_dcache/fill_count_rdy +/tb_mips_top/uut/inst_biu/inst_dcache/flush_load_en +/tb_mips_top/uut/inst_biu/inst_dcache/flush_addr_preset +/tb_mips_top/uut/inst_biu/inst_dcache/flush_count_preset +/tb_mips_top/uut/inst_biu/inst_dcache/flush_addr +/tb_mips_top/uut/inst_biu/inst_dcache/flush_count +/tb_mips_top/uut/inst_biu/inst_dcache/flush_count_en +/tb_mips_top/uut/inst_biu/inst_dcache/flush_count_rdy +/tb_mips_top/uut/inst_biu/inst_dcache/request_count +/tb_mips_top/uut/inst_biu/inst_dcache/request_count_en +/tb_mips_top/uut/inst_biu/inst_dcache/request_count_rdy +/tb_mips_top/uut/inst_biu/inst_dcache/was_miss +/tb_mips_top/uut/inst_biu/inst_dcache/invalidate_all +/tb_mips_top/uut/inst_biu/inst_dcache/invalidate_ack +/tb_mips_top/uut/inst_biu/inst_dcache/invalidate_en +/tb_mips_top/uut/inst_biu/inst_dcache/invalidate_req +/tb_mips_top/uut/inst_biu/inst_dcache/cpu_hit_we +/tb_mips_top/uut/inst_biu/inst_dcache/instant_raw +/tb_mips_top/uut/inst_biu/inst_dcache/hit_cache_index +/tb_mips_top/uut/inst_biu/inst_dcache/dat_i_r +/tb_mips_top/uut/inst_biu/inst_dcache/ack_i_r +/tb_mips_top/uut/inst_biu/inst_dcache/inst_tag_ram/clk_a +/tb_mips_top/uut/inst_biu/inst_dcache/inst_tag_ram/clk_b +/tb_mips_top/uut/inst_biu/inst_dcache/inst_tag_ram/re_a +/tb_mips_top/uut/inst_biu/inst_dcache/inst_tag_ram/re_b +/tb_mips_top/uut/inst_biu/inst_dcache/inst_tag_ram/we_a +/tb_mips_top/uut/inst_biu/inst_dcache/inst_tag_ram/we_b +/tb_mips_top/uut/inst_biu/inst_dcache/inst_tag_ram/addr_a +/tb_mips_top/uut/inst_biu/inst_dcache/inst_tag_ram/addr_b +/tb_mips_top/uut/inst_biu/inst_dcache/inst_tag_ram/din_a +/tb_mips_top/uut/inst_biu/inst_dcache/inst_tag_ram/din_b +/tb_mips_top/uut/inst_biu/inst_dcache/inst_tag_ram/dout_a +/tb_mips_top/uut/inst_biu/inst_dcache/inst_tag_ram/dout_b +/tb_mips_top/uut/inst_biu/inst_dcache/inst_tag_ram/addr_a_r +/tb_mips_top/uut/inst_biu/inst_dcache/inst_tag_ram/addr_b_r +/tb_mips_top/uut/inst_biu/inst_dcache/inst_tag_ram/ram +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/clk_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/clk_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/re_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/re_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/we_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/we_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/addr_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/addr_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/din_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/din_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/dout_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/dout_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/addr_a_r +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/addr_b_r +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/ram +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/clk_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/clk_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/re_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/re_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/we_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/we_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/addr_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/addr_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/din_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/din_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/dout_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/dout_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/addr_a_r +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/addr_b_r +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/ram +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/clk_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/clk_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/re_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/re_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/we_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/we_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/addr_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/addr_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/din_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/din_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/dout_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/dout_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/addr_a_r +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/addr_b_r +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/ram +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/clk_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/clk_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/re_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/re_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/we_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/we_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/addr_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/addr_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/din_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/din_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/dout_a +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/dout_b +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/addr_a_r +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/addr_b_r +/tb_mips_top/uut/inst_biu/inst_dcache/gen_data_ram/inst_data_ram/ram +/tb_mips_top/uut/inst_biu/inst_bin_fifo/rst +/tb_mips_top/uut/inst_biu/inst_bin_fifo/clk_w +/tb_mips_top/uut/inst_biu/inst_bin_fifo/clk_r +/tb_mips_top/uut/inst_biu/inst_bin_fifo/we +/tb_mips_top/uut/inst_biu/inst_bin_fifo/re +/tb_mips_top/uut/inst_biu/inst_bin_fifo/fifo_full +/tb_mips_top/uut/inst_biu/inst_bin_fifo/fifo_empty +/tb_mips_top/uut/inst_biu/inst_bin_fifo/fifo_afull +/tb_mips_top/uut/inst_biu/inst_bin_fifo/fifo_aempty +/tb_mips_top/uut/inst_biu/inst_bin_fifo/data_w +/tb_mips_top/uut/inst_biu/inst_bin_fifo/data_r +/tb_mips_top/uut/inst_biu/inst_bin_fifo/reg_we +/tb_mips_top/uut/inst_biu/inst_bin_fifo/reg_vld +/tb_mips_top/uut/inst_biu/inst_bin_fifo/reg_full +/tb_mips_top/uut/inst_biu/inst_bin_fifo/fifo_dout +/tb_mips_top/uut/inst_biu/inst_bin_fifo/fifo_rd +/tb_mips_top/uut/inst_biu/inst_bin_fifo/fifo_empty_s +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/rst +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/clk_w +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/clk_r +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/we +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/re +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/fifo_full +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/fifo_empty +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/fifo_afull +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/fifo_aempty +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/data_w +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/data_r +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/mem_wr_en +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/mem_rd_en +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/ptr_w +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/ptr_r +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/full +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/empty +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/pre_empty +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/rinc +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/rst +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/clk_w +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/clk_r +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/winc +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/rinc +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/ptr_w +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/ptr_r +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/fifo_pre_full +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/fifo_pre_empty +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/fifo_full +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/fifo_empty +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/fifo_afull +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/fifo_aempty +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/gcnt_w +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/gcnt2_w +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/bcnt2_aw +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/bcnt_w +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/gnxt_w +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/bnxt_w +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/gcnt_r +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/gcnt2_r +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/bcnt2_ar +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/bcnt_r +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/gnxt_r +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/bnxt_r +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/pre_empty +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/pre_full +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/full +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/empty +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/rst_w +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/rst_r +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/diffw +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/diffr +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/rst +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/clk +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/ce +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/bcnt +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/bnxt +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/gcnt +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/gnxt +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/cntg +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/cntb +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/nxtg +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/rst +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/clk +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/ce +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/bnxt +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/gnxt +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/cntg +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/cntb +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_dpram_1w1r2c/clk_a +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_dpram_1w1r2c/clk_b +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_dpram_1w1r2c/we_a +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_dpram_1w1r2c/re_b +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_dpram_1w1r2c/addr_a +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_dpram_1w1r2c/addr_b +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_dpram_1w1r2c/din_a +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_dpram_1w1r2c/dout_b +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_dpram_1w1r2c/ram +/tb_mips_top/uut/inst_biu/inst_bin_fifo/inst_fifo_async_stage/inst_dpram_1w1r2c/addr_b_r +/tb_mips_top/uut/inst_biu/inst_bout_fifo/rst +/tb_mips_top/uut/inst_biu/inst_bout_fifo/clk_w +/tb_mips_top/uut/inst_biu/inst_bout_fifo/clk_r +/tb_mips_top/uut/inst_biu/inst_bout_fifo/we +/tb_mips_top/uut/inst_biu/inst_bout_fifo/re +/tb_mips_top/uut/inst_biu/inst_bout_fifo/fifo_full +/tb_mips_top/uut/inst_biu/inst_bout_fifo/fifo_empty +/tb_mips_top/uut/inst_biu/inst_bout_fifo/fifo_afull +/tb_mips_top/uut/inst_biu/inst_bout_fifo/fifo_aempty +/tb_mips_top/uut/inst_biu/inst_bout_fifo/data_w +/tb_mips_top/uut/inst_biu/inst_bout_fifo/data_r +/tb_mips_top/uut/inst_biu/inst_bout_fifo/reg_we +/tb_mips_top/uut/inst_biu/inst_bout_fifo/reg_vld +/tb_mips_top/uut/inst_biu/inst_bout_fifo/reg_full +/tb_mips_top/uut/inst_biu/inst_bout_fifo/fifo_dout +/tb_mips_top/uut/inst_biu/inst_bout_fifo/fifo_rd +/tb_mips_top/uut/inst_biu/inst_bout_fifo/fifo_empty_s +/tb_mips_top/uut/inst_biu/inst_bout_fifo/gen_extra_regs/inst_reg_stage/rst +/tb_mips_top/uut/inst_biu/inst_bout_fifo/gen_extra_regs/inst_reg_stage/clk +/tb_mips_top/uut/inst_biu/inst_bout_fifo/gen_extra_regs/inst_reg_stage/we +/tb_mips_top/uut/inst_biu/inst_bout_fifo/gen_extra_regs/inst_reg_stage/re +/tb_mips_top/uut/inst_biu/inst_bout_fifo/gen_extra_regs/inst_reg_stage/full +/tb_mips_top/uut/inst_biu/inst_bout_fifo/gen_extra_regs/inst_reg_stage/vld_dout +/tb_mips_top/uut/inst_biu/inst_bout_fifo/gen_extra_regs/inst_reg_stage/din +/tb_mips_top/uut/inst_biu/inst_bout_fifo/gen_extra_regs/inst_reg_stage/dout +/tb_mips_top/uut/inst_biu/inst_bout_fifo/gen_extra_regs/inst_reg_stage/dvld +/tb_mips_top/uut/inst_biu/inst_bout_fifo/gen_extra_regs/inst_reg_stage/fct +/tb_mips_top/uut/inst_biu/inst_bout_fifo/gen_extra_regs/inst_reg_stage/full_s +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/rst +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/clk_w +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/clk_r +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/we +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/re +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/fifo_full +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/fifo_empty +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/fifo_afull +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/fifo_aempty +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/data_w +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/data_r +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/mem_wr_en +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/mem_rd_en +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/ptr_w +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/ptr_r +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/full +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/empty +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/pre_empty +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/rinc +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/rst +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/clk_w +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/clk_r +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/winc +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/rinc +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/ptr_w +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/ptr_r +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/fifo_pre_full +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/fifo_pre_empty +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/fifo_full +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/fifo_empty +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/fifo_afull +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/fifo_aempty +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/gcnt_w +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/gcnt2_w +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/bcnt2_aw +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/bcnt_w +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/gnxt_w +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/bnxt_w +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/gcnt_r +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/gcnt2_r +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/bcnt2_ar +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/bcnt_r +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/gnxt_r +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/bnxt_r +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/pre_empty +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/pre_full +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/full +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/empty +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/rst_w +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/rst_r +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/diffw +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/diffr +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/rst +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/clk +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/ce +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/bcnt +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/bnxt +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/gcnt +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/gnxt +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/cntg +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/cntb +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_w/nxtg +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/rst +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/clk +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/ce +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/bnxt +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/gnxt +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/cntg +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/cntb +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_dpram_1w1r2c/clk_a +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_dpram_1w1r2c/clk_b +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_dpram_1w1r2c/we_a +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_dpram_1w1r2c/re_b +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_dpram_1w1r2c/addr_a +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_dpram_1w1r2c/addr_b +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_dpram_1w1r2c/din_a +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_dpram_1w1r2c/dout_b +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_dpram_1w1r2c/ram +/tb_mips_top/uut/inst_biu/inst_bout_fifo/inst_fifo_async_stage/inst_dpram_1w1r2c/addr_b_r +/tb_mips_top/uut/inst_biu/inst_write_fifo/rst +/tb_mips_top/uut/inst_biu/inst_write_fifo/clk +/tb_mips_top/uut/inst_biu/inst_write_fifo/we +/tb_mips_top/uut/inst_biu/inst_write_fifo/re +/tb_mips_top/uut/inst_biu/inst_write_fifo/fifo_full +/tb_mips_top/uut/inst_biu/inst_write_fifo/fifo_empty +/tb_mips_top/uut/inst_biu/inst_write_fifo/fifo_afull +/tb_mips_top/uut/inst_biu/inst_write_fifo/fifo_aempty +/tb_mips_top/uut/inst_biu/inst_write_fifo/data_w +/tb_mips_top/uut/inst_biu/inst_write_fifo/data_r +/tb_mips_top/uut/inst_biu/inst_write_fifo/reg_we +/tb_mips_top/uut/inst_biu/inst_write_fifo/reg_vld +/tb_mips_top/uut/inst_biu/inst_write_fifo/reg_full +/tb_mips_top/uut/inst_biu/inst_write_fifo/fifo_dout +/tb_mips_top/uut/inst_biu/inst_write_fifo/fifo_rd +/tb_mips_top/uut/inst_biu/inst_write_fifo/fifo_empty_s +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/rst +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/clk +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/we +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/re +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/fifo_full +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/fifo_empty +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/fifo_afull +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/fifo_aempty +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/data_w +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/data_r +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/mem_wr_en +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/mem_rd_en +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/ptr_w +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/ptr_r +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/full +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/empty +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/pre_empty +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/rinc +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/rst +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/clk +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/winc +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/rinc +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/ptr_w +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/ptr_r +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/fifo_pre_full +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/fifo_pre_empty +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/fifo_full +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/fifo_empty +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/fifo_afull +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/fifo_aempty +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/pw +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/pw_cnt +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/pw_next +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/pr +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/pr_cnt +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/pr_next +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/empty +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/full +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/pre_empty +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/pre_full +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/was_write +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_fifo_sync_ctrl/diff +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_dpram_1w1r2c/clk_a +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_dpram_1w1r2c/clk_b +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_dpram_1w1r2c/we_a +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_dpram_1w1r2c/re_b +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_dpram_1w1r2c/addr_a +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_dpram_1w1r2c/addr_b +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_dpram_1w1r2c/din_a +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_dpram_1w1r2c/dout_b +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_dpram_1w1r2c/ram +/tb_mips_top/uut/inst_biu/inst_write_fifo/inst_fifo_sync_stage/inst_dpram_1w1r2c/addr_b_r +/tb_mips_top/inst_rom/clk_i +/tb_mips_top/inst_rom/rst_i +/tb_mips_top/inst_rom/cyc_i +/tb_mips_top/inst_rom/we_i +/tb_mips_top/inst_rom/stb_i +/tb_mips_top/inst_rom/ack_o +/tb_mips_top/inst_rom/mrdy_i +/tb_mips_top/inst_rom/srdy_o +/tb_mips_top/inst_rom/addr_i +/tb_mips_top/inst_rom/dat_o +/tb_mips_top/inst_rom/data_en +/tb_mips_top/inst_rom/inst_rom/clk +/tb_mips_top/inst_rom/inst_rom/ce +/tb_mips_top/inst_rom/inst_rom/addr +/tb_mips_top/inst_rom/inst_rom/dout +/tb_mips_top/inst_gpio/clk_i +/tb_mips_top/inst_gpio/rst_i +/tb_mips_top/inst_gpio/cyc_i +/tb_mips_top/inst_gpio/stb_i +/tb_mips_top/inst_gpio/sel_i +/tb_mips_top/inst_gpio/we_i +/tb_mips_top/inst_gpio/ack_o +/tb_mips_top/inst_gpio/srdy_o +/tb_mips_top/inst_gpio/mrdy_i +/tb_mips_top/inst_gpio/addr_i +/tb_mips_top/inst_gpio/dat_i +/tb_mips_top/inst_gpio/dat_o +/tb_mips_top/inst_gpio/int_tim_o +/tb_mips_top/inst_gpio/sys_gpi_0 +/tb_mips_top/inst_gpio/sys_gpo_0 +/tb_mips_top/inst_gpio/gpio_0_dout_reg +/tb_mips_top/inst_gpio/gpio_0_dir_reg +/tb_mips_top/inst_gpio/gpio_0_din_reg +/tb_mips_top/inst_gpio/tick_usec +/tb_mips_top/inst_gpio/cnt_usec +/tb_mips_top/inst_gpio/cnt_sec +/tb_mips_top/inst_gpio/cnt_usec_preset +/tb_mips_top/inst_gpio/cnt_sec_preset +/tb_mips_top/inst_gpio/cnt_usec_en +/tb_mips_top/inst_gpio/cnt_usec_we +/tb_mips_top/inst_gpio/cnt_sec_en +/tb_mips_top/inst_gpio/cnt_sec_we +/tb_mips_top/inst_gpio/timer_cnt +/tb_mips_top/inst_gpio/timer_cmp +/tb_mips_top/inst_gpio/timer_en +/tb_mips_top/inst_gpio/timer_inten +/tb_mips_top/inst_gpio/timer_irq +/tb_mips_top/inst_gpio/timer_ovl +/tb_mips_top/inst_gpio/timer_irq_ack +/tb_mips_top/inst_gpio/timer_cnt_we +/tb_mips_top/inst_gpio/timer_cmp_we +/tb_mips_top/inst_gpio/reg_data_wr +/tb_mips_top/inst_flash_port/clk_i +/tb_mips_top/inst_flash_port/rst_i +/tb_mips_top/inst_flash_port/cyc_i +/tb_mips_top/inst_flash_port/stb_i +/tb_mips_top/inst_flash_port/we_i +/tb_mips_top/inst_flash_port/ack_o +/tb_mips_top/inst_flash_port/srdy_o +/tb_mips_top/inst_flash_port/mrdy_i +/tb_mips_top/inst_flash_port/sel_i +/tb_mips_top/inst_flash_port/addr_i +/tb_mips_top/inst_flash_port/dat_i +/tb_mips_top/inst_flash_port/dat_o +/tb_mips_top/inst_flash_port/page_mode_en +/tb_mips_top/inst_flash_port/async_a +/tb_mips_top/inst_flash_port/async_d +/tb_mips_top/inst_flash_port/async_cs +/tb_mips_top/inst_flash_port/async_wr +/tb_mips_top/inst_flash_port/async_rd +/tb_mips_top/inst_flash_port/async_be +/tb_mips_top/inst_flash_port/async_rst +/tb_mips_top/inst_flash_port/s +/tb_mips_top/inst_flash_port/sn +/tb_mips_top/inst_flash_port/as +/tb_mips_top/inst_flash_port/ack +/tb_mips_top/inst_flash_port/cc_rst +/tb_mips_top/inst_flash_port/cycle_cnt +/tb_mips_top/inst_flash_port/cycle_reload +/tb_mips_top/inst_flash_port/rdy +/tb_mips_top/inst_flash_port/rdyo +/tb_mips_top/inst_flash_port/en +/tb_mips_top/inst_flash_port/is_idle +/tb_mips_top/inst_flash_port/dat_i_r +/tb_mips_top/inst_flash_port/sel_i_r +/tb_mips_top/inst_flash_port/we_i_r +/tb_mips_top/inst_flash_port/addr_i_r +/tb_mips_top/inst_flash_port/page_mode_en_r +/tb_mips_top/inst_flash_port/do_page_read +/tb_mips_top/inst_sram_port/clk_i +/tb_mips_top/inst_sram_port/rst_i +/tb_mips_top/inst_sram_port/cyc_i +/tb_mips_top/inst_sram_port/stb_i +/tb_mips_top/inst_sram_port/we_i +/tb_mips_top/inst_sram_port/ack_o +/tb_mips_top/inst_sram_port/srdy_o +/tb_mips_top/inst_sram_port/mrdy_i +/tb_mips_top/inst_sram_port/sel_i +/tb_mips_top/inst_sram_port/addr_i +/tb_mips_top/inst_sram_port/dat_i +/tb_mips_top/inst_sram_port/dat_o +/tb_mips_top/inst_sram_port/page_mode_en +/tb_mips_top/inst_sram_port/async_a +/tb_mips_top/inst_sram_port/async_d +/tb_mips_top/inst_sram_port/async_cs +/tb_mips_top/inst_sram_port/async_wr +/tb_mips_top/inst_sram_port/async_rd +/tb_mips_top/inst_sram_port/async_be +/tb_mips_top/inst_sram_port/async_rst +/tb_mips_top/inst_sram_port/s +/tb_mips_top/inst_sram_port/sn +/tb_mips_top/inst_sram_port/as +/tb_mips_top/inst_sram_port/ack +/tb_mips_top/inst_sram_port/cc_rst +/tb_mips_top/inst_sram_port/cycle_cnt +/tb_mips_top/inst_sram_port/cycle_reload +/tb_mips_top/inst_sram_port/rdy +/tb_mips_top/inst_sram_port/rdyo +/tb_mips_top/inst_sram_port/en +/tb_mips_top/inst_sram_port/is_idle +/tb_mips_top/inst_sram_port/dat_i_r +/tb_mips_top/inst_sram_port/sel_i_r +/tb_mips_top/inst_sram_port/we_i_r +/tb_mips_top/inst_sram_port/addr_i_r +/tb_mips_top/inst_sram_port/page_mode_en_r +/tb_mips_top/inst_sram_port/do_page_read +/tb_mips_top/inst_uart/clk_i +/tb_mips_top/inst_uart/rst_i +/tb_mips_top/inst_uart/int_o +/tb_mips_top/inst_uart/cyc_i +/tb_mips_top/inst_uart/stb_i +/tb_mips_top/inst_uart/sel_i +/tb_mips_top/inst_uart/we_i +/tb_mips_top/inst_uart/ack_o +/tb_mips_top/inst_uart/srdy_o +/tb_mips_top/inst_uart/mrdy_i +/tb_mips_top/inst_uart/addr_i +/tb_mips_top/inst_uart/dat_i +/tb_mips_top/inst_uart/dat_o +/tb_mips_top/inst_uart/ser_rx +/tb_mips_top/inst_uart/ser_tx +/tb_mips_top/inst_uart/reg_uart_baud +/tb_mips_top/inst_uart/reg_we_uart_tx +/tb_mips_top/inst_uart/reg_re_uart_rx +/tb_mips_top/inst_uart/reg_uart_tx +/tb_mips_top/inst_uart/reg_uart_rx +/tb_mips_top/inst_uart/uart_status_port +/tb_mips_top/inst_uart/rx_int_en +/tb_mips_top/inst_uart/tx_int_en +/tb_mips_top/inst_uart/irq_rx +/tb_mips_top/inst_uart/irq_tx +/tb_mips_top/inst_uart/ctrl +/tb_mips_top/inst_uart/status +/tb_mips_top/inst_uart/inst_uart/clk +/tb_mips_top/inst_uart/inst_uart/rst +/tb_mips_top/inst_uart/inst_uart/we +/tb_mips_top/inst_uart/inst_uart/re +/tb_mips_top/inst_uart/inst_uart/din +/tb_mips_top/inst_uart/inst_uart/dout +/tb_mips_top/inst_uart/inst_uart/ser_rx +/tb_mips_top/inst_uart/inst_uart/ser_tx +/tb_mips_top/inst_uart/inst_uart/ctrl +/tb_mips_top/inst_uart/inst_uart/status