From 087210ce5cdc62f0738be26e61a7499e7471a3e0 Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Sun, 15 Jan 2017 13:18:04 +0000
Subject: [PATCH] [DE0-Nano] - cleaned up top level - removed jtag regs - added
 SPI clk to SDC

git-svn-id: http://moon:8086/svn/vhdl/trunk@1370 cc03376c-175c-47c8-b038-4cd826a8556b
---
 projects/mips_de0_nano/quartus/mips/JMips.sdc |  3 +-
 .../mips_de0_nano/quartus/mips/mips_sys.vhd   | 40 -------------------
 2 files changed, 1 insertion(+), 42 deletions(-)

diff --git a/projects/mips_de0_nano/quartus/mips/JMips.sdc b/projects/mips_de0_nano/quartus/mips/JMips.sdc
index 17f30e1..5f687b1 100644
--- a/projects/mips_de0_nano/quartus/mips/JMips.sdc
+++ b/projects/mips_de0_nano/quartus/mips/JMips.sdc
@@ -39,9 +39,9 @@ set_time_format -unit ns -decimal_places 3
 # Create Clock
 #**************************************************************
 
-create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
 create_clock -name {sys_clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports { sys_clk }]
 create_clock -name {SDRAM_clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {sys_sdram_clk}]
+create_clock -name {spi_clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {spi_clk}]
 
 
 #**************************************************************
@@ -78,7 +78,6 @@ derive_clock_uncertainty
 # Set Clock Groups
 #**************************************************************
 
-set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 
 
 
 #**************************************************************
diff --git a/projects/mips_de0_nano/quartus/mips/mips_sys.vhd b/projects/mips_de0_nano/quartus/mips/mips_sys.vhd
index 25f57b5..b28cf7d 100644
--- a/projects/mips_de0_nano/quartus/mips/mips_sys.vhd
+++ b/projects/mips_de0_nano/quartus/mips/mips_sys.vhd
@@ -137,51 +137,11 @@ ARCHITECTURE behavior OF mips_sys IS
 	signal cpu_rst_count	: unsigned(23 downto 0) := (others => '1');		-- pre-init for POR
 	signal sys_rst_count	: unsigned(7 downto 0) := (others => '1');		-- pre-init for POR
 	
-	subtype addr_t is unsigned (2 downto 0);
-	subtype reg_t is unsigned (7 downto 0);
-	type reg_map_t is array (0 to 7) of reg_t;
-	
-	signal regs				: reg_map_t;
-	signal reg_addr			: addr_t;
-	signal reg_din			: reg_t;
-	signal reg_dout			: reg_t;
-	signal reg_re			: STD_LOGIC;
-	signal reg_we			: STD_LOGIC;
-
 BEGIN
 	sys_nmi		<= not sys_nmi_n;
 	sys_leds	<= cpu_debug & gpo0(5 downto 0);
 	spi_ss_n	<= not spi_ss;
 	
-	reg_dout	<= regs(to_integer(reg_addr));
-	
-	process(sys_clk)
-	begin
-		if rising_edge(sys_clk) then
-			if reg_we = '1' then
-				regs(to_integer(reg_addr)) <= reg_din;
-			end if;
-		end if;
-	end process;
-
-inst_jtag_reg:  entity work.jtag_reg
-	GENERIC MAP
-	(
-		INSTANCE_INDEX		=> 1,
-		DATA_WIDTH			=> reg_t'length,		-- bits
-		ADDR_WIDTH			=> addr_t'length		-- bits
-	)
-	PORT MAP
-	(
-		rst					=> sys_rst,
-		clk					=> sys_clk,
-		addr_o				=> reg_addr,
-		reg_i				=> reg_dout,
-		reg_o				=> reg_din,
-		we_o				=> reg_we,
-		re_o				=> reg_re
-	);
-	
 sys_reset:
 	process(sys_clk)
 	begin