diff --git a/lib/radio/cordic/src/cordic_pipe_top.vhd b/lib/radio/cordic/src/cordic_pipe_top.vhd index bfc1c90..94eea52 100644 --- a/lib/radio/cordic/src/cordic_pipe_top.vhd +++ b/lib/radio/cordic/src/cordic_pipe_top.vhd @@ -33,7 +33,7 @@ Generic ( cordic_mode : cordic_mode_t := cordic_mode_rotate; z_range : real := pi; - gain_corr_mode : gain_corr_mode_t := gain_mode_unity; + gain_corr_mode : gain_corr_mode_t := gain_mode_disabled; nstages : integer := 18; nbits_x_in : integer := 18; nbits_y_in : integer := 18; @@ -184,7 +184,7 @@ signal post_zin : sfixed(shi(nbits_z_out, nbits_frac_z_out) downto slo(nbits_z_ signal post_xout : sfixed(shi(nbits_x_out, nbits_frac_x_out) downto slo(nbits_x_out, nbits_frac_x_out)); signal post_yout : sfixed(shi(nbits_y_out, nbits_frac_y_out) downto slo(nbits_y_out, nbits_frac_y_out)); signal post_zout : sfixed(shi(nbits_z_out, nbits_frac_z_out) downto slo(nbits_z_out, nbits_frac_z_out)); - +signal post_vld : std_logic; begin @@ -206,6 +206,7 @@ gen_output_unity: xout <= post_xout; yout <= post_yout; zout <= post_zout; + vld_out <= post_vld; end generate; gen_output_disabled: @@ -214,6 +215,7 @@ gen_output_disabled: xout <= post_xin; yout <= post_yin; zout <= post_zin; + vld_out <= stage_vld(nstages); end generate; ----------------------------------------------------------------------- @@ -275,31 +277,37 @@ gen_pipe: end generate; -Inst_cordic_pipe_post: cordic_pipe_post -GENERIC MAP -( - cordic_mode => cordic_mode_rotate, - nstages => nstages, - nbits_x => nbits_x_out, - nbits_x_frac => nbits_frac_x_out, - nbits_y => nbits_y_out, - nbits_y_frac => nbits_frac_y_out, - nbits_z => nbits_z_out, - nbits_z_frac => nbits_frac_z_out -) -PORT MAP -( - rst => rst, - clk => clk, - vld_in => stage_vld(nstages), - xin => post_xin, - yin => post_yin, - zin => post_zin, - xout => post_xout, - yout => post_yout, - zout => post_zout, - vld_out => vld_out -); +gen_post_process: + if gain_corr_mode = gain_mode_unity generate + begin + + Inst_cordic_pipe_post: cordic_pipe_post + GENERIC MAP + ( + cordic_mode => cordic_mode_rotate, + nstages => nstages, + nbits_x => nbits_x_out, + nbits_x_frac => nbits_frac_x_out, + nbits_y => nbits_y_out, + nbits_y_frac => nbits_frac_y_out, + nbits_z => nbits_z_out, + nbits_z_frac => nbits_frac_z_out + ) + PORT MAP + ( + rst => rst, + clk => clk, + vld_in => stage_vld(nstages), + xin => post_xin, + yin => post_yin, + zin => post_zin, + xout => post_xout, + yout => post_yout, + zout => post_zout, + vld_out => post_vld + ); + + end generate; -------------------------------------------------------------------- end Behavioral;