diff --git a/lib/CPUs/MIPS/tools/insrom.rb b/lib/CPUs/MIPS/tools/insrom.rb
deleted file mode 100644
index fdbf1ed..0000000
--- a/lib/CPUs/MIPS/tools/insrom.rb
+++ /dev/null
@@ -1,46 +0,0 @@
-#!/usr/bin/env ruby
-
-# ----------------------------------------------------------------------
-# Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-# This file: Insertion of code fragments into templates
-#
-# Copyright (C) 2008 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see .
-#
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-arg = $*
-rom_filename = arg[0].to_s
-tpl_filename = arg[1].to_s
-
-subst_pattern = "ROM_INSERT_HERE"
-
-# --------------------------------------------------------
-# Open file
-# --------------------------------------------------------
-romfile = File.open(rom_filename, "r")
-tplfile = File.open(tpl_filename, "r")
-re = Regexp.new(subst_pattern)
-
-while (line = tplfile.gets)
- puts line
- line.scan(re).each do |word|
- romfile.each do |raw_line|
- puts raw_line
- end
- end
-end
diff --git a/lib/CPUs/MIPS/tools/irom.vhd.tpl b/lib/CPUs/MIPS/tools/irom.vhd.tpl
deleted file mode 100644
index 5ffd6d7..0000000
--- a/lib/CPUs/MIPS/tools/irom.vhd.tpl
+++ /dev/null
@@ -1,29 +0,0 @@
--------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
--- ROM_INSERT_HERE
-
diff --git a/lib/CPUs/MIPS/tools/irom_ld.vhd.tpl b/lib/CPUs/MIPS/tools/irom_ld.vhd.tpl
deleted file mode 100644
index 3bd3afb..0000000
--- a/lib/CPUs/MIPS/tools/irom_ld.vhd.tpl
+++ /dev/null
@@ -1,147 +0,0 @@
--------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: loadable ROM
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-ENTITY irom IS
- Port (
- clk : in STD_LOGIC;
- addr : in inst_addr_t;
- dout : out inst_t
- );
-
-END irom;
-
-ARCHITECTURE loadable OF irom IS
-
- -- JASM_ROM_INSERT_HERE
-
- signal jtag_ld_clk : STD_LOGIC;
- signal jtag_ld_we : STD_LOGIC;
- signal jtag_ld_addr : unsigned (15 downto 0);
- signal jtag_ld_dout : unsigned (31 downto 0);
- signal jtag_ld_din : unsigned (31 downto 0);
- signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
- signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
- signal user_regi, user_rego : unsigned (47 downto 0);
- constant id : unsigned (47 downto 0) := X"DEAD" & X"BEEF" & "X"BABE";
-
-begin
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
- i00_BUFG : BUFG
- port map
- (
- O => bs_clk1,
- I => bs_clk0
- );
-
- i01_BUFG : BUFG
- port map
- (
- O => bs_update1,
- I => bs_update0
- );
-
- BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4
- generic map
- (
- JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
- )
- port map
- (
- CAPTURE => bs_capture, -- CAPTURE output from TAP controller
- DRCK => bs_clk0, -- Data register output for USER functions
- RESET => bs_rst, -- Reset output from TAP controller
- SEL => bs_sel, -- USER active output
- SHIFT => bs_shift, -- SHIFT output from TAP controller
- TDI => bs_tdi, -- TDI output from TAP controller
- UPDATE => bs_update0, -- UPDATE output from TAP controller
- TDO => bs_tdo -- Data input for USER function
- );
-
- jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);
- jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);
- jtag_ld_clk <= bs_update1;
- jtag_ld_we <= bs_sel;
-
-sipo:
- process (bs_rst, bs_clk1, bs_tdi, bs_shift)
- begin
- if bs_rst = '1' then
- user_regi <= (others => '0');
- elsif rising_edge(bs_clk1) then
- if bs_shift = '1' then
- user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
- end if;
- end if;
- end process;
-
-piso:
- process (bs_rst, bs_clk1, bs_shift, user_rego)
- begin
- bs_tdo <= user_rego(0);
- if bs_rst = '1' then
- user_rego <= (others => '0');
- elsif rising_edge(bs_clk1) then
- if bs_shift = '1' then
- user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
- else
- user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;
--- user_rego <= id;
- end if;
- end if;
- end process;
-
-PROM_WRITE:
- process(jtag_ld_clk, jtag_ld_we)
- begin
- if rising_edge(jtag_ld_clk) then
- if jtag_ld_we = '1' then
- imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
- else
- jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
- end if;
- end if;
- end process;
-
---------------------------------------------------------------------------
--- ROM Read/Write
---------------------------------------------------------------------------
-PROM_READ:
- process(clk)
- begin
- if rising_edge(clk) then
- dout <= imem_rom(to_integer(addr));
- end if;
- end process;
-
---------------------------------------------------------------------------
-end loadable;
diff --git a/lib/CPUs/MIPS/tools/make.sh b/lib/CPUs/MIPS/tools/make.sh
deleted file mode 100644
index b9b349b..0000000
--- a/lib/CPUs/MIPS/tools/make.sh
+++ /dev/null
@@ -1,51 +0,0 @@
-#!/bin/sh
-
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: rom-file generation for cpu_core
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see .
-#
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-# $Header: /tmp/cvsroot/VHDL/lib/CPUs/MIPS/tools/make.sh,v 1.1 2008-08-25 08:29:55 Jens Exp $
-# ----------------------------------------------------------------------
-TARGET=$2
-DSTDIR=$1
-
-JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
-
-$JASM_HOME/jasm.rb $TARGET.jsm
-
-irom_tcl_snippet="$TARGET.irom.tcl.snip"
-irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
-irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
-xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
-xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
-xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
-
-$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
-$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
-
-$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
-$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
-
-cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
-cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
-$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
-
-rm -f *.snip
diff --git a/lib/CPUs/MIPS/tools/rom.tcl.tpl b/lib/CPUs/MIPS/tools/rom.tcl.tpl
deleted file mode 100644
index 9f5c0dc..0000000
--- a/lib/CPUs/MIPS/tools/rom.tcl.tpl
+++ /dev/null
@@ -1,61 +0,0 @@
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: The ROM file for upload to target over JTAG
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see .
-#
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-# ---------------------------------------------------------------------
-# For Chipscope 9.1
-# ---------------------------------------------------------------------
-# Source JTAG/TCL frame work
-cd $env(CHIPSCOPE)\\bin\\nt
-source csejtag.tcl
-
-namespace import ::chipscope::*
-
-# Platform USB Cable
-set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
-# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
-
-# Create session
-set handle [::chipscope::csejtag_session create 0]
-
-# Open JTAG and lock
-set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
-set lock_result [::chipscope::csejtag_target lock $handle 1000]
-
-set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
-
-# Get Device ID
-set devtype "Virtex-4SX"
-set devid 2
-set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
-set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
-
-set CSE_OP $CSEJTAG_SHIFT_READWRITE
-set CSE_ES $CSEJTAG_RUN_TEST_IDLE
-
-# Write Program
-# JASM_ROM_INSERT_HERE
-
-::chipscope::csejtag_target unlock $handle
-::chipscope::csejtag_target close $handle
-::chipscope::csejtag_session destroy $handle
-exit