- Blitter now works correctly. Supports non-aligned load/store.
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@957 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
+351
-290
@@ -22,15 +22,14 @@ use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.utils_pkg.all;
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use work.align_types.all;
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use work.vga_types.all;
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entity vga_frontend64 is
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Generic
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(
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fifo_depth : integer := 2048;
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fifo_almost_full_thresh : natural := 2000;
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fifo_almost_empty_thresh : natural := 48;
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fifo_depth : integer := 4096;
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fifo_almost_full_thresh : natural := 4000;
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fifo_almost_empty_thresh : natural := 800;
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BLIT_CHUNK_SIZE : natural := 512;
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tsvga : vga_timespec_t := ts_vga_800_600_72
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);
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@@ -171,59 +170,58 @@ architecture Behavioral of vga_frontend64 is
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-- Blitter vars
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signal blit_chunk_cnt : natural range 0 to BLIT_CHUNK_SIZE-1;
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signal blit_chunk_cnt_rst : std_logic;
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signal blit_chunk_cnt_en : std_logic;
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signal blit_chunk_full : std_logic;
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-- Blitter FIFO signals
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signal blitfifo_dout_vld : std_logic;
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signal blitfifo_write_en : std_logic;
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signal blitfifo_read_en : std_logic;
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signal blitfifo_full : unsigned(1 downto 0);
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signal blitfifo_empty : unsigned(1 downto 0);
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signal blitfifo_we : unsigned(1 downto 0);
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signal blitfifo_re : unsigned(1 downto 0);
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signal blitfifo_din : unsigned(63 downto 0);
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signal blitfifo_dout_0 : unsigned(31 downto 0);
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signal blitfifo_dout_1 : unsigned(31 downto 0);
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-- Source Blitter FIFO signals
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signal blitfifo_src_full : std_logic;
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signal blitfifo_src_empty : std_logic;
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signal blitfifo_src_re : std_logic;
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signal blitfifo_src_we : std_logic;
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signal blitfifo_src_out : unsigned(63 downto 0);
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signal blitfifo_src_in : unsigned(63 downto 0);
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-- Source alignment register
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signal blit_src_addr : unsigned(2 downto 0);
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signal blit_src_reg_vld : std_logic;
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signal blit_src_reg : unsigned(63 downto 0);
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signal blit_src_rdy : std_logic;
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signal blit_src_we : std_logic;
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signal blit_src_re : std_logic;
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signal blit_src_unaligned : std_logic;
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signal blit_src_do_extra : std_logic;
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signal blit_src_do_extra2 : std_logic;
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signal blit_src_row_cnt : unsigned(31 downto 0);
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signal blit_src_first : std_logic;
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signal blit_src_last : std_logic;
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-- BLIT Source register
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signal blit_src_cnt_x_next : unsigned(32 downto 0);
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signal blit_src_cnt_x : unsigned(31 downto 0);
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signal blit_src_cnt_y : unsigned(31 downto 0);
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signal blit_src_off_y : unsigned(31 downto 0);
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signal blit_src_offset : unsigned(31 downto 0);
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signal blit_src_addr_next : unsigned(31 downto 0);
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signal blit_src_finish : std_logic;
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signal blit_src_START_U : std_logic;
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signal blit_src_START_A : std_logic;
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signal blit_src_STOP_U : std_logic;
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signal blit_src_STOP_A : std_logic;
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signal CYC_O_blit_src : std_logic;
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signal STB_O_blit_src : std_logic;
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signal ADDR_O_blit_src : unsigned(31 downto 0);
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signal blit_src_nx : unsigned(31 downto 0);
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-- Destination alignment register
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signal blit_dst_cmd_rdy : std_logic;
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signal blit_dst_cmd_vld : std_logic;
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signal blit_dst_din_rdy : std_logic;
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signal blit_dst_din_vld : std_logic;
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signal blit_dst_dout_re : std_logic;
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signal blit_dst_dout_be : unsigned(7 downto 0);
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signal blit_dst_dout_vld : std_logic;
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-- BLIT Destination register
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signal blit_dst_cnt_x_next : unsigned(32 downto 0);
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signal blit_dst_cnt_x : unsigned(31 downto 0);
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signal blit_dst_cnt_y : unsigned(31 downto 0);
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signal blit_dst_offset : unsigned(31 downto 0);
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signal blit_dst_dout : unsigned(63 downto 0);
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signal blit_dst_addr_next : unsigned(31 downto 0);
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signal blit_dst_finish : std_logic;
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signal blit_dst_cmd : align_cmd_in_t;
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signal blitfifo_empty_read : std_logic;
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signal blit_dst_suspend : std_logic;
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signal blit_dst_be : unsigned(7 downto 0);
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-- BLIT Source Tracker
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signal blit_fill_cnt_x_next : unsigned(32 downto 0);
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signal blit_fill_cnt_x : unsigned(31 downto 0);
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signal blit_fill_cnt_y : unsigned(31 downto 0);
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signal blit_fill_offset : unsigned(2 downto 0);
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signal blit_fill_finish : std_logic;
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signal blit_fill_addr : unsigned(2 downto 0);
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signal blit_const_color : unsigned(31 downto 0);
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signal blit_const_color_en : std_logic;
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signal blit_const_color_vld : std_logic;
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signal CYC_O_blit_dst : std_logic;
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signal STB_O_blit_dst : std_logic;
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@@ -231,6 +229,7 @@ architecture Behavioral of vga_frontend64 is
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signal odd_pixel : unsigned(NextExpBaseTwo(tsvga.ts_h.ncyc_scan)-1 downto 0);
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-- Bus output FIFO
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signal busout_fifo_din : unsigned(104 downto 0);
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signal busout_fifo_dout : unsigned(104 downto 0);
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@@ -260,9 +259,23 @@ architecture Behavioral of vga_frontend64 is
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signal busin_fifo_rdy : std_logic;
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signal busin_fifo_dout_vld : std_logic;
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type vm_state_t is (init, rdy, scan_bus_request, scan_bus_read, blit_src_bus_request, blit_src_bus_read, blit_dst_prime_pipe, blit_dst_bus_request, bus_fin);
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type vm_state_t is (init, rdy, scan_bus_request, scan_bus_read, blit_src_bus_request, blit_src_bus_read, blit_dst_bus_request, const_dst_bus_request, bus_fin);
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signal s, sn : vm_state_t;
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type debug_t is
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record
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FIRST : std_logic;
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LAST : std_logic;
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UNALIGNED : std_logic;
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PARTIAL : std_logic;
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N_ODD : std_logic;
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re : unsigned(1 downto 0);
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end record debug_t;
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signal src_dbg : debug_t;
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signal fill_dbg : debug_t;
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signal dst_dbg : debug_t;
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--------------------------------------------------------------------------
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begin
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@@ -406,6 +419,7 @@ inst_linefifo: entity work.fifo_async
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fifo_color_re <= stat_scan and odd_pixel(0);
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fifo_color_we <= busin_fifo_dout_vld and CYC_O_scan; -- TODO:
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-- Bus input FIFO
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inst_busin_fifo: entity work.fifo_sync
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GENERIC MAP
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@@ -431,7 +445,7 @@ inst_busin_fifo: entity work.fifo_sync
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busin_fifo_din <= MDAT_I;
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busin_fifo_we <= ACK_I and bus_cycle_en and bus_read_en;
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busin_fifo_dout_vld <= not busin_fifo_empty;
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busin_fifo_re <= not fifo_full when CYC_O_scan = '1' else blit_src_we;
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busin_fifo_re <= not fifo_full when CYC_O_scan = '1' else CYC_O_blit_src;
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-- Bus output FIFO
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inst_busout_fifo: entity work.fifo_sync
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@@ -457,14 +471,40 @@ inst_busout_fifo: entity work.fifo_sync
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busout_fifo_rdy <= not busout_fifo_full;
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busout_fifo_re <= not busout_fifo_empty and SRDY_I;
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busout_fifo_we <= bus_cycle_en and (STB_O_scan or STB_O_blit_src or STB_O_blit_dst);
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busout_fifo_data_in <= blit_dst_dout;
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busout_fifo_data_in <= (blitfifo_dout_1 & blitfifo_dout_0) when blit_const_color_en = '0' else (blit_const_color & blit_const_color);
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busout_fifo_addr_in <= ADDR_O_blit_src when CYC_O_blit_src = '1' else
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ADDR_O_blit_dst when CYC_O_blit_dst = '1' else
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ADDR_O_scan;
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busout_fifo_sel_in <= blit_dst_dout_be when CYC_O_blit_dst = '1' else (others => '1');
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busout_fifo_sel_in <= blit_dst_be;
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busout_fifo_we_in <= CYC_O_blit_dst;
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request_en <= bus_cycle_en and busout_fifo_we and busout_fifo_rdy;
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CYC_O <= bus_cycle_en;
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---------------------------------------------------------------------------------
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ADDR_O_scan <= front + (to_unsigned(pixel_cnt, 29) & "000");
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proc_scan_addr:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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bufchg <= '0';
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if vga_scan_dma_en2 = '0' then
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pixel_cnt <= 0;
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front <= host_fb_front;
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elsif STB_O_scan = '1' and busout_fifo_rdy = '1' then
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if pixel_cnt /= MAX_REQUEST_CNT/2-1 then
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pixel_cnt <= pixel_cnt + 1;
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else
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pixel_cnt <= 0;
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front <= host_fb_back;
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bufchg <= '1';
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end if;
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end if;
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vga_fb_front <= front;
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vga_fb_back <= back;
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end if;
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end process;
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------------------------------------------------------------------------------------
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-- VGA master FSM
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vga_master_next:
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@@ -480,7 +520,7 @@ vga_master_next:
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end process;
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vga_master:
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process(s, stat_vga_rdy, vga_scan_dma_en2, fifo_almost_empty, fifo_almost_full, bus_read_fin, busout_fifo_rdy, busout_fifo_empty, blit_chunk_cnt, blitfifo_src_empty, blit_dst_dout_vld, blit_src_finish, blit_const_color_en)
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process(s, stat_vga_rdy, vga_scan_dma_en2, fifo_almost_empty, fifo_almost_full, bus_read_fin, busout_fifo_empty, blit_request, blit_dst_suspend, blit_chunk_full, blitfifo_dout_vld, blit_src_finish, blitfifo_empty_read, blit_dst_finish, blit_const_color_en)
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begin
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CYC_O_scan <= '0';
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@@ -490,12 +530,8 @@ vga_master:
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CYC_O_blit_dst <= '0';
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STB_O_blit_dst <= '0';
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request_cnt_rst <= '0';
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request_en <= '0';
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bus_read_en <= '0';
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bus_cycle_en <= '0';
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blit_chunk_cnt_rst <= '0';
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blit_chunk_cnt_en <= '0';
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sn <= s;
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case s is
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@@ -506,14 +542,15 @@ vga_master:
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when rdy =>
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request_cnt_rst <= '1';
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blit_chunk_cnt_rst <= '1';
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if fifo_almost_empty = '1' and vga_scan_dma_en2 = '1' then
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sn <= scan_bus_request;
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elsif blit_request = '1' then -- ToDo: richtig prüfen anhand eines states wer dran ist. Nicht auf FIFO state prüfen
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if blit_dst_dout_vld = '1' then
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sn <= blit_dst_bus_request;
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elsif blit_const_color_en = '0' then
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sn <= blit_dst_bus_request;
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if blitfifo_dout_vld = '0' or blit_dst_suspend = '1' then
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sn <= blit_src_bus_request;
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if blit_const_color_en = '1' then
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sn <= const_dst_bus_request;
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end if;
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end if;
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end if;
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@@ -521,7 +558,6 @@ vga_master:
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bus_cycle_en <= '1';
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CYC_O_scan <= '1';
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STB_O_scan <= '1';
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request_en <= '1';
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bus_read_en <= '1';
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if fifo_almost_full = '1' then
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sn <= scan_bus_read;
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@@ -537,39 +573,38 @@ vga_master:
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when blit_src_bus_request =>
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bus_cycle_en <= '1';
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bus_read_en <= '1';
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CYC_O_blit_src <= '1';
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STB_O_blit_src <= '1';
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request_en <= '1';
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bus_read_en <= '1';
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blit_chunk_cnt_en <= '1';
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if blit_chunk_cnt = 0 or blit_src_finish = '1' then
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if blit_chunk_full = '1' or blit_src_finish = '1' then
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STB_O_blit_src <= '0';
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sn <= blit_src_bus_read;
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end if;
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when blit_src_bus_read =>
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bus_cycle_en <= '1';
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CYC_O_blit_src <= '1';
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bus_read_en <= '1';
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CYC_O_blit_src <= '1';
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if bus_read_fin = '1' then
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sn <= rdy;
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end if;
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-- when blit_dst_prime_pipe =>
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-- bus_cycle_en <= '1';
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-- CYC_O_blit_dst <= '1';
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-- STB_O_blit_dst <= blit_dst_dout_vld;
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-- blit_chunk_cnt_en <= blit_dst_dout_vld;
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-- if blit_dst_dout_vld = '1' then
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-- sn <= blit_dst_bus_request;
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-- end if;
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when blit_dst_bus_request =>
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bus_cycle_en <= '1';
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CYC_O_blit_dst <= '1';
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STB_O_blit_dst <= blit_dst_dout_vld;
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blit_chunk_cnt_en <= blit_dst_dout_vld;
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if blit_chunk_cnt = 0 or blit_dst_dout_vld = '0' then
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sn <= bus_fin;
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STB_O_blit_dst <= '1';
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if blitfifo_empty_read = '1' or blitfifo_dout_vld = '0' or blit_dst_finish = '1' then
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STB_O_blit_dst <= '0';
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sn <= bus_fin;
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end if;
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when const_dst_bus_request =>
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bus_cycle_en <= '1';
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CYC_O_blit_dst <= '1';
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STB_O_blit_dst <= '1';
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if blit_chunk_full = '1' or blit_dst_finish = '1' then
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STB_O_blit_dst <= '0';
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sn <= bus_fin;
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end if;
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when bus_fin =>
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@@ -591,7 +626,7 @@ proc_bus_request_counter:
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if rising_edge(CLK_I) then
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if request_cnt_rst = '1' then
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request_cnt <= (others => '0');
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elsif request_en = '1' and busout_fifo_rdy = '1' then
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elsif request_en = '1' then
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request_cnt <= request_cnt + 1;
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end if;
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end if;
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@@ -624,259 +659,285 @@ proc_blit_chunk_counter:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if blit_chunk_cnt_rst = '1' then
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blit_chunk_cnt <= BLIT_CHUNK_SIZE-1;
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elsif blit_chunk_cnt_en = '1' and busout_fifo_rdy = '1' then
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if blit_chunk_cnt /= 0 then
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if request_cnt_rst = '1' then
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blit_chunk_full <= '0';
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blit_chunk_cnt <= BLIT_CHUNK_SIZE-2;
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elsif request_en = '1' then
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if blit_chunk_cnt = 0 then
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blit_chunk_full <= '1';
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else
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blit_chunk_cnt <= blit_chunk_cnt - 1;
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end if;
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end if;
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end if;
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end process;
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---------------------------------------------------------------------------------
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blit_reset <= RST_I or (blit_request_set and not blit_request);
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ADDR_O_scan <= front + (to_unsigned(pixel_cnt, 29) & "000");
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proc_scan_addr:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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bufchg <= '0';
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if vga_scan_dma_en2 = '0' then
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pixel_cnt <= 0;
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front <= host_fb_front;
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elsif STB_O_scan = '1' and busout_fifo_rdy = '1' then
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if pixel_cnt /= MAX_REQUEST_CNT/2-1 then
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pixel_cnt <= pixel_cnt + 1;
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else
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pixel_cnt <= 0;
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front <= host_fb_back;
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bufchg <= '1';
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end if;
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end if;
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vga_fb_front <= front;
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vga_fb_back <= back;
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end if;
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end process;
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---------------------------------------------------------------------------------
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inst_align_src : entity work.align
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GENERIC MAP
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(
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data_width => 64,
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aggregate_size => 8
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)
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PORT MAP
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(
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rst => blit_reset,
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clk => CLK_I,
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ce => blit_src_re,
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eb => '1',
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offset => blit_src_addr,
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din_vld => blit_src_we,
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din => busin_fifo_dout,
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dout_vld => blit_src_reg_vld,
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dout => blit_src_reg,
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byte_en => open
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);
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blit_src_we <= busin_fifo_dout_vld and CYC_O_blit_src; -- TODO:
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blit_src_re <= not blitfifo_src_full; -- TODO:
|
||||
|
||||
proc_blit_src_counter:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if blit_reset = '1' then
|
||||
blit_src_row_cnt <= to_unsigned(1, 32);
|
||||
blit_src_unaligned <= '0';
|
||||
blit_src_first <= '0';
|
||||
blit_src_last <= '0';
|
||||
blit_src_do_extra2 <= '0';
|
||||
if blit_src_addr (2 downto 0) /= "000" then
|
||||
blit_src_unaligned <= not blit_const_color_en;
|
||||
blit_src_first <= not blit_const_color_en;
|
||||
blit_src_do_extra2 <= not blit_const_color_en;
|
||||
end if;
|
||||
blit_src_nx <= '0' & blit_nx(blit_nx'left downto 1);
|
||||
elsif blit_src_re = '1' then
|
||||
if blit_src_reg_vld = '1' then
|
||||
blit_src_first <= '0';
|
||||
if blit_src_row_cnt /= blit_src_nx then
|
||||
blit_src_row_cnt <= blit_src_row_cnt + 1;
|
||||
elsif blit_src_do_extra2 = '1' then
|
||||
blit_src_do_extra2 <= '0';
|
||||
else
|
||||
if blit_src_unaligned = '1' then
|
||||
blit_src_do_extra2 <= '1';
|
||||
end if;
|
||||
blit_src_row_cnt <= to_unsigned(1, 32);
|
||||
blit_src_first <= blit_src_unaligned;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_blitfifo_src: entity work.fifo_sync
|
||||
inst_blitfifo_src0: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(BLIT_CHUNK_SIZE),
|
||||
data_width => blitfifo_src_in'length
|
||||
data_width => 32,
|
||||
|
||||
do_last_read_update => false
|
||||
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => blit_reset,
|
||||
clk => CLK_I,
|
||||
we => blitfifo_src_we,
|
||||
re => blitfifo_src_re,
|
||||
data_w => blitfifo_src_in,
|
||||
data_r => blitfifo_src_out,
|
||||
fifo_full => blitfifo_src_full,
|
||||
fifo_empty => blitfifo_src_empty,
|
||||
we => blitfifo_we(0),
|
||||
re => blitfifo_re(0),
|
||||
data_w => blitfifo_din(31 downto 0),
|
||||
data_r => blitfifo_dout_0,
|
||||
fifo_full => blitfifo_full(0),
|
||||
fifo_empty => blitfifo_empty(0),
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open
|
||||
|
||||
);
|
||||
|
||||
blitfifo_src_we <= (blit_src_reg_vld and not blit_src_first) when blit_const_color_en = '0' else (blit_request and not blit_src_finish);
|
||||
blitfifo_src_in <= blit_src_reg when blit_const_color_en = '0' else (blit_const_color & blit_const_color);
|
||||
blitfifo_src_re <= blit_dst_din_rdy;
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
ADDR_O_blit_src <= blit_addr_src_0(31 downto 3) & "000" + blit_src_offset;
|
||||
blit_src_addr <= blit_addr_src_0(2 downto 0);
|
||||
|
||||
proc_blit_addr_src:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if blit_reset = '1' then
|
||||
blit_src_cnt_x <= to_unsigned(1, 32);
|
||||
blit_src_cnt_y <= to_unsigned(1, 32);
|
||||
blit_src_offset <= (others => '0');
|
||||
blit_src_off_y <= blit_dimx_src_0;
|
||||
blit_src_finish <= '0';
|
||||
blit_src_do_extra <= '0';
|
||||
if blit_src_addr (2 downto 0) /= "000" then
|
||||
blit_src_do_extra <= not blit_const_color_en;
|
||||
end if;
|
||||
elsif blit_src_finish = '0' and ((STB_O_blit_src = '1' and busout_fifo_rdy = '1') or (blit_const_color_en = '1' and blitfifo_src_full = '0')) then
|
||||
blit_src_offset <= blit_src_offset + 8;
|
||||
if blit_src_cnt_x /= blit_src_nx then
|
||||
blit_src_cnt_x <= blit_src_cnt_x + 1;
|
||||
elsif blit_src_do_extra = '1' then
|
||||
blit_src_do_extra <= '0';
|
||||
else
|
||||
if blit_src_unaligned = '1' then
|
||||
blit_src_do_extra <= '1';
|
||||
end if;
|
||||
if blit_src_cnt_y /= blit_ny then
|
||||
blit_src_cnt_x <= to_unsigned(1, 32);
|
||||
blit_src_offset <= blit_src_off_y;
|
||||
blit_src_cnt_y <= blit_src_cnt_y + 1;
|
||||
blit_src_off_y <= blit_src_off_y + blit_dimx_src_0;
|
||||
else
|
||||
blit_src_finish <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
inst_align_out : entity work.align_out
|
||||
GENERIC MAP
|
||||
inst_blitfifo_src1: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
data_width => 64,
|
||||
addr_width => 32,
|
||||
byte_size => 8
|
||||
addr_width => NextExpBaseTwo(BLIT_CHUNK_SIZE),
|
||||
data_width => 32,
|
||||
|
||||
do_last_read_update => false
|
||||
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => blit_reset,
|
||||
clk => CLK_I,
|
||||
cmd_rdy => blit_dst_cmd_rdy,
|
||||
cmd_vld => blit_dst_cmd_vld,
|
||||
cmd_in => blit_dst_cmd,
|
||||
din_rdy => blit_dst_din_rdy,
|
||||
din_vld => blit_dst_din_vld,
|
||||
din => blitfifo_src_out,
|
||||
dout_vld => blit_dst_dout_vld,
|
||||
dout => blit_dst_dout,
|
||||
dout_be => blit_dst_dout_be,
|
||||
dout_re => blit_dst_dout_re,
|
||||
addr_out => ADDR_O_blit_dst
|
||||
rst => blit_reset,
|
||||
clk => CLK_I,
|
||||
we => blitfifo_we(1),
|
||||
re => blitfifo_re(1),
|
||||
data_w => blitfifo_din(63 downto 32),
|
||||
data_r => blitfifo_dout_1,
|
||||
fifo_full => blitfifo_full(1),
|
||||
fifo_empty => blitfifo_empty(1),
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open
|
||||
|
||||
);
|
||||
blit_dst_din_vld <= not blitfifo_src_empty;
|
||||
blit_dst_dout_re <= CYC_O_blit_dst and busout_fifo_rdy;
|
||||
|
||||
-- inst_align_dst : entity work.align
|
||||
-- GENERIC MAP
|
||||
-- (
|
||||
-- data_width => 64,
|
||||
-- aggregate_size => 8
|
||||
-- )
|
||||
-- PORT MAP
|
||||
-- (
|
||||
-- rst => blit_reset,
|
||||
-- clk => CLK_I,
|
||||
-- eb => '1',
|
||||
-- ce => blit_dst_re,
|
||||
-- offset => blit_addr_dst(2 downto 0),
|
||||
-- din_vld => blit_dst_we,
|
||||
-- din => blitfifo_src_out,
|
||||
-- dout_vld => blit_dst_reg_vld,
|
||||
-- dout => blit_dst_reg,
|
||||
-- byte_en => blit_dst_reg_be
|
||||
--
|
||||
-- );
|
||||
|
||||
-- blit_dst_be <= blit_dst_reg_be when blit_dst_first = '1' else
|
||||
-- not blit_dst_reg_be when blit_dst_last = '1' else
|
||||
-- (others => '1');
|
||||
|
||||
|
||||
-- blit_dst_we <= not blitfifo_src_empty;
|
||||
-- blit_dst_re <= CYC_O_blit_dst and busout_fifo_rdy and not blit_dst_last;
|
||||
-- blit_dst_vld <= blit_dst_reg_vld or blit_dst_last;
|
||||
blitfifo_din <= busin_fifo_dout;
|
||||
blitfifo_write_en <= busin_fifo_dout_vld and CYC_O_blit_src;
|
||||
blitfifo_read_en <= busout_fifo_rdy and CYC_O_blit_dst;
|
||||
blitfifo_dout_vld <= not (blitfifo_empty(0) and blitfifo_empty(1));
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
blit_reset <= RST_I or (blit_request_set and not blit_request);
|
||||
|
||||
proc_blit_addr_dst:
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
blit_dst_be_gen:
|
||||
process(dst_dbg)
|
||||
begin
|
||||
blit_dst_be <= "11111111";
|
||||
if dst_dbg.UNALIGNED = '1' then
|
||||
if dst_dbg.FIRST = '1' then
|
||||
blit_dst_be <= "00001111";
|
||||
elsif dst_dbg.LAST = '1' then
|
||||
if dst_dbg.PARTIAL = '1' then
|
||||
blit_dst_be <= "11110000";
|
||||
end if;
|
||||
end if;
|
||||
elsif dst_dbg.LAST = '1' then
|
||||
if dst_dbg.PARTIAL = '1' then
|
||||
blit_dst_be <= "00001111";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
blitfifo_we_gen:
|
||||
process(fill_dbg, blitfifo_write_en)
|
||||
begin
|
||||
blitfifo_we <= (blitfifo_write_en & blitfifo_write_en);
|
||||
if fill_dbg.UNALIGNED = '1' then
|
||||
if fill_dbg.FIRST = '1' then
|
||||
blitfifo_we <= ('0' & blitfifo_write_en);
|
||||
elsif fill_dbg.LAST = '1' then
|
||||
if fill_dbg.PARTIAL = '1' then
|
||||
blitfifo_we <= (blitfifo_write_en & '0');
|
||||
end if;
|
||||
end if;
|
||||
elsif fill_dbg.LAST = '1' then
|
||||
if fill_dbg.PARTIAL = '1' then
|
||||
blitfifo_we <= ('0' & blitfifo_write_en);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
blitfifo_re_gen:
|
||||
process(dst_dbg, blitfifo_empty, blitfifo_read_en)
|
||||
variable fifo_re : unsigned(1 downto 0);
|
||||
variable empty_read : std_logic;
|
||||
begin
|
||||
fifo_re := (blitfifo_read_en & blitfifo_read_en);
|
||||
if dst_dbg.UNALIGNED = '1' then
|
||||
if dst_dbg.FIRST = '1' then
|
||||
fifo_re := ('0' & blitfifo_read_en);
|
||||
elsif dst_dbg.LAST = '1' then
|
||||
if dst_dbg.PARTIAL = '1' then
|
||||
fifo_re := (blitfifo_read_en & '0');
|
||||
end if;
|
||||
end if;
|
||||
elsif dst_dbg.LAST = '1' then
|
||||
if dst_dbg.PARTIAL = '1' then
|
||||
fifo_re := ('0' & blitfifo_read_en);
|
||||
end if;
|
||||
end if;
|
||||
empty_read := (blitfifo_empty(0) and fifo_re(0)) or (blitfifo_empty(1) and fifo_re(1));
|
||||
blitfifo_re <= fifo_re and not (empty_read & empty_read);
|
||||
blitfifo_empty_read <= empty_read;
|
||||
dst_dbg.re <= fifo_re;
|
||||
end process;
|
||||
|
||||
blit_dst_suspend_gen:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
blit_dst_finish <= '1';
|
||||
blit_dst_cmd_vld <= '0';
|
||||
elsif blit_reset = '1' then
|
||||
blit_dst_cmd.num_bytes <= blit_nx(blit_nx'left-2 downto 0) & "00";
|
||||
blit_dst_cmd.num_bytes_per_word <= 4;
|
||||
blit_dst_cmd.addr_start <= blit_addr_dst;
|
||||
blit_dst_cmd.eb <= '1';
|
||||
blit_dst_cnt_y <= to_unsigned(1, 32);
|
||||
blit_dst_offset <= blit_addr_dst;
|
||||
blit_dst_cmd_vld <= '1';
|
||||
blit_dst_finish <= '0';
|
||||
elsif blit_dst_finish = '0' then
|
||||
if blit_dst_cnt_y /= blit_ny then
|
||||
if blit_dst_cmd_rdy = '1' then
|
||||
blit_dst_cmd.addr_start <= blit_dst_cmd.addr_start + blit_dimx_dst;
|
||||
blit_dst_cnt_y <= blit_dst_cnt_y + 1;
|
||||
end if;
|
||||
else
|
||||
blit_dst_cmd_vld <= '0';
|
||||
blit_dst_finish <= '1';
|
||||
if blit_reset = '1' or CYC_O_blit_src = '1' then
|
||||
blit_dst_suspend <= '0';
|
||||
elsif blitfifo_read_en = '1' and blitfifo_empty_read = '1' then
|
||||
blit_dst_suspend <= not (blitfifo_empty(0) and blitfifo_empty(1));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
fill_dbg.LAST <= '1' when blit_fill_cnt_x_next = '0' & X"0000_0000" or blit_fill_cnt_x_next(32) = '1' else '0';
|
||||
fill_dbg.PARTIAL <= blit_fill_cnt_x_next(32);
|
||||
fill_dbg.N_ODD <= blit_nx(1);
|
||||
|
||||
blit_fill_cnt_x_next <= ('0' & blit_fill_cnt_x - 1) when fill_dbg.FIRST = '1' and fill_dbg.UNALIGNED = '1' else ('0' & blit_fill_cnt_x - 2);
|
||||
|
||||
blitfifo_fill_src_0:
|
||||
process(CLK_I)
|
||||
variable addr_next : unsigned(31 downto 0);
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if blit_reset = '1' then
|
||||
blit_fill_addr <= blit_addr_src_0(2) & "00";
|
||||
blit_fill_cnt_x <= blit_nx;
|
||||
blit_fill_cnt_y <= blit_ny;
|
||||
blit_fill_offset <= blit_dimx_src_0(2 downto 0);
|
||||
blit_fill_finish <= blit_const_color_en;
|
||||
fill_dbg.FIRST <= not blit_const_color_en;
|
||||
fill_dbg.UNALIGNED <= blit_addr_src_0(2);
|
||||
elsif blit_request = '1' then
|
||||
if blit_fill_finish = '0' and blitfifo_write_en = '1' then
|
||||
fill_dbg.FIRST <= '0';
|
||||
if blit_fill_cnt_x_next = '0' & X"0000_0000" or blit_fill_cnt_x_next(32) = '1' then
|
||||
if blit_fill_cnt_y < X"0000_0002" then
|
||||
blit_fill_finish <= '1';
|
||||
else
|
||||
addr_next := (blit_addr_src_0(31 downto 2) & "00") + blit_fill_offset;
|
||||
blit_fill_addr <= addr_next(2 downto 0);
|
||||
blit_fill_offset <= blit_fill_offset + blit_dimx_src_0(2 downto 0);
|
||||
blit_fill_cnt_x <= blit_nx;
|
||||
blit_fill_cnt_y <= blit_fill_cnt_y - 1;
|
||||
fill_dbg.FIRST <= '1';
|
||||
fill_dbg.UNALIGNED <= addr_next(2);
|
||||
end if;
|
||||
else
|
||||
blit_fill_cnt_x <= blit_fill_cnt_x_next(31 downto 0);
|
||||
blit_fill_addr <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
src_dbg.LAST <= '1' when blit_src_cnt_x_next = '0' & X"0000_0000" or blit_src_cnt_x_next(32) = '1' else '0';
|
||||
src_dbg.PARTIAL <= blit_src_cnt_x_next(32);
|
||||
src_dbg.N_ODD <= blit_nx(1);
|
||||
|
||||
blit_src_addr_next <= ADDR_O_blit_src + 8;
|
||||
blit_src_cnt_x_next <= ('0' & blit_src_cnt_x - 1) when src_dbg.FIRST = '1' and src_dbg.UNALIGNED = '1' else ('0' & blit_src_cnt_x - 2);
|
||||
|
||||
blit_request_addr_src:
|
||||
process(CLK_I)
|
||||
variable addr_next : unsigned(31 downto 0);
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if blit_reset = '1' then
|
||||
ADDR_O_blit_src <= blit_addr_src_0(31 downto 2) & "00";
|
||||
blit_src_cnt_x <= blit_nx;
|
||||
blit_src_cnt_y <= blit_ny;
|
||||
blit_src_offset <= blit_dimx_src_0;
|
||||
blit_src_finish <= blit_const_color_en;
|
||||
src_dbg.FIRST <= not blit_const_color_en;
|
||||
src_dbg.UNALIGNED <= blit_addr_src_0(2);
|
||||
elsif blit_request = '1' then
|
||||
if blit_src_finish = '0' and (STB_O_blit_src = '1' and busout_fifo_rdy = '1') then
|
||||
src_dbg.FIRST <= '0';
|
||||
if blit_src_cnt_x_next = '0' & X"0000_0000" or blit_src_cnt_x_next(32) = '1' then
|
||||
if blit_src_cnt_y < X"0000_0002" then
|
||||
blit_src_finish <= '1';
|
||||
else
|
||||
addr_next := (blit_addr_src_0(31 downto 2) & "00") + blit_src_offset;
|
||||
ADDR_O_blit_src <= addr_next;
|
||||
blit_src_offset <= blit_src_offset + blit_dimx_src_0;
|
||||
blit_src_cnt_x <= blit_nx;
|
||||
blit_src_cnt_y <= blit_src_cnt_y - 1;
|
||||
src_dbg.FIRST <= '1';
|
||||
src_dbg.UNALIGNED <= addr_next(2);
|
||||
end if;
|
||||
else
|
||||
ADDR_O_blit_src <= blit_src_addr_next;
|
||||
blit_src_cnt_x <= blit_src_cnt_x_next(31 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
dst_dbg.LAST <= '1' when blit_dst_cnt_x_next = '0' & X"0000_0000" or blit_dst_cnt_x_next(32) = '1' else '0';
|
||||
dst_dbg.PARTIAL <= blit_dst_cnt_x_next(32);
|
||||
dst_dbg.N_ODD <= blit_nx(1);
|
||||
|
||||
blit_dst_addr_next <= ADDR_O_blit_dst + 8;
|
||||
blit_dst_cnt_x_next <= ('0' & blit_dst_cnt_x - 1) when dst_dbg.FIRST = '1' and dst_dbg.UNALIGNED = '1' else ('0' & blit_dst_cnt_x - 2);
|
||||
|
||||
blit_request_addr_dst:
|
||||
process(CLK_I)
|
||||
variable addr_next : unsigned(31 downto 0);
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if blit_reset = '1' then
|
||||
ADDR_O_blit_dst <= blit_addr_dst(31 downto 2) & "00";
|
||||
blit_dst_cnt_x <= blit_nx;
|
||||
blit_dst_cnt_y <= blit_ny;
|
||||
blit_dst_offset <= blit_dimx_dst;
|
||||
blit_dst_finish <= '0';
|
||||
dst_dbg.FIRST <= '1';
|
||||
dst_dbg.UNALIGNED <= blit_addr_dst(2);
|
||||
elsif blit_request = '1' then
|
||||
if blit_dst_finish = '0' and (STB_O_blit_dst = '1' and busout_fifo_rdy = '1') then
|
||||
dst_dbg.FIRST <= '0';
|
||||
if blit_dst_cnt_x_next = '0' & X"0000_0000" or blit_dst_cnt_x_next(32) = '1' then
|
||||
if blit_dst_cnt_y < X"0000_0002" then
|
||||
blit_dst_finish <= '1';
|
||||
else
|
||||
addr_next := (blit_addr_dst(31 downto 2) & "00") + blit_dst_offset;
|
||||
ADDR_O_blit_dst <= addr_next;
|
||||
blit_dst_offset <= blit_dst_offset + blit_dimx_dst;
|
||||
blit_dst_cnt_x <= blit_nx;
|
||||
blit_dst_cnt_y <= blit_dst_cnt_y - 1;
|
||||
dst_dbg.FIRST <= '1';
|
||||
dst_dbg.UNALIGNED <= addr_next(2);
|
||||
end if;
|
||||
else
|
||||
ADDR_O_blit_dst <= blit_dst_addr_next;
|
||||
blit_dst_cnt_x <= blit_dst_cnt_x_next(31 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
inst_char_gen : entity work.char_gen
|
||||
GENERIC MAP
|
||||
|
||||
Reference in New Issue
Block a user