- Blitter now works correctly. Supports non-aligned load/store.
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@957 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -60,13 +60,13 @@ ARCHITECTURE behavior OF tb_vga_frontend64 IS
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signal ACK_O : std_logic;
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signal MRDY_I : std_logic;
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signal SRDY_O : std_logic;
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signal ADDR_I : unsigned(31 downto 0) := (others => '-');
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signal ADDR_I : unsigned(31 downto 0) := (others => '0');
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signal SDAT_I : unsigned(31 downto 0) := (others => '-');
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signal SDAT_O : unsigned(31 downto 0) := (others => '-');
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signal rdy : std_logic := '0';
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signal read_reg : unsigned(31 downto 0) := (others => '-');
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signal const_color : unsigned(31 downto 0) := X"1111_1111";
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signal const_color : unsigned(31 downto 0) := X"0000_0000";
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-- VGA signals
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signal vga_clk : std_logic := '1';
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@@ -79,20 +79,305 @@ ARCHITECTURE behavior OF tb_vga_frontend64 IS
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signal vga_vsync : std_logic;
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signal vga_en : std_logic;
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type blit_size_array_t is array (0 to 6) of natural;
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type blit_size_array_t is array (0 to 9) of natural;
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constant blit_size_x : blit_size_array_t := (32, 31, 32, 31, 1, 32, 1);
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constant blit_size_y : blit_size_array_t := (32, 32, 31, 31, 32, 1, 1);
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constant blit_size_x : blit_size_array_t := (8, 1, 2, 7, 8, 7, 1, 8, 8, 0);
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constant blit_size_y : blit_size_array_t := (8, 1, 2, 8, 7, 7, 8, 1, 0, 8);
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signal blit_count_rst : std_logic := '0';
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type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU);
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signal state : state_t := IDLE;
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type ram_t is array (0 to 127) of unsigned(63 downto 0);
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signal ram_src : ram_t :=
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(
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X"B000_0000_A000_0000",
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X"B000_0001_A000_0001",
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X"B000_0002_A000_0002",
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X"B000_0003_A000_0003",
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X"B000_0004_A000_0004",
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X"B000_0005_A000_0005",
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X"B000_0006_A000_0006",
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X"B000_0007_A000_0007",
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X"B000_0008_A000_0008",
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X"B000_0009_A000_0009",
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X"B000_000A_A000_000A",
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X"B000_000B_A000_000B",
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X"B000_000C_A000_000C",
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X"B000_000D_A000_000D",
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X"B000_000E_A000_000E",
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X"B000_000F_A000_000F",
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X"B000_0010_A000_0010",
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X"B000_0011_A000_0011",
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X"B000_0012_A000_0012",
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X"B000_0013_A000_0013",
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X"B000_0014_A000_0014",
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X"B000_0015_A000_0015",
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X"B000_0016_A000_0016",
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X"B000_0017_A000_0017",
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X"B000_0018_A000_0018",
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X"B000_0019_A000_0019",
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X"B000_001A_A000_001A",
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X"B000_001B_A000_001B",
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X"B000_001C_A000_001C",
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X"B000_001D_A000_001D",
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X"B000_001E_A000_001E",
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X"B000_001F_A000_001F",
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X"B000_0020_A000_0020",
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X"B000_0021_A000_0021",
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X"B000_0022_A000_0022",
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X"B000_0023_A000_0023",
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X"B000_0024_A000_0024",
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X"B000_0025_A000_0025",
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X"B000_0026_A000_0026",
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X"B000_0027_A000_0027",
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X"B000_0028_A000_0028",
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X"B000_0029_A000_0029",
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X"B000_002A_A000_002A",
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X"B000_002B_A000_002B",
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X"B000_002C_A000_002C",
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X"B000_002D_A000_002D",
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X"B000_002E_A000_002E",
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X"B000_002F_A000_002F",
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X"B000_0030_A000_0030",
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X"B000_0031_A000_0031",
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X"B000_0032_A000_0032",
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X"B000_0033_A000_0033",
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X"B000_0034_A000_0034",
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X"B000_0035_A000_0035",
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X"B000_0036_A000_0036",
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X"B000_0037_A000_0037",
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X"B000_0038_A000_0038",
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X"B000_0039_A000_0039",
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X"B000_003A_A000_003A",
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X"B000_003B_A000_003B",
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X"B000_003C_A000_003C",
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X"B000_003D_A000_003D",
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X"B000_003E_A000_003E",
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X"B000_003F_A000_003F",
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X"B000_0040_A000_0040",
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X"B000_0041_A000_0041",
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X"B000_0042_A000_0042",
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X"B000_0043_A000_0043",
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X"B000_0044_A000_0044",
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X"B000_0045_A000_0045",
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X"B000_0046_A000_0046",
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X"B000_0047_A000_0047",
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X"B000_0048_A000_0048",
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X"B000_0049_A000_0049",
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X"B000_004A_A000_004A",
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X"B000_004B_A000_004B",
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X"B000_004C_A000_004C",
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X"B000_004D_A000_004D",
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X"B000_004E_A000_004E",
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X"B000_004F_A000_004F",
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X"B000_0050_A000_0050",
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X"B000_0051_A000_0051",
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X"B000_0052_A000_0052",
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X"B000_0053_A000_0053",
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X"B000_0054_A000_0054",
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X"B000_0055_A000_0055",
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X"B000_0056_A000_0056",
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X"B000_0057_A000_0057",
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X"B000_0058_A000_0058",
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X"B000_0059_A000_0059",
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X"B000_005A_A000_005A",
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X"B000_005B_A000_005B",
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X"B000_005C_A000_005C",
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X"B000_005D_A000_005D",
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X"B000_005E_A000_005E",
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X"B000_005F_A000_005F",
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X"B000_0060_A000_0060",
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X"B000_0061_A000_0061",
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X"B000_0062_A000_0062",
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X"B000_0063_A000_0063",
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X"B000_0064_A000_0064",
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X"B000_0065_A000_0065",
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X"B000_0066_A000_0066",
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X"B000_0067_A000_0067",
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X"B000_0068_A000_0068",
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X"B000_0069_A000_0069",
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X"B000_006A_A000_006A",
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X"B000_006B_A000_006B",
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X"B000_006C_A000_006C",
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X"B000_006D_A000_006D",
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X"B000_006E_A000_006E",
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X"B000_006F_A000_006F",
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X"B000_0070_A000_0070",
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X"B000_0071_A000_0071",
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X"B000_0072_A000_0072",
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X"B000_0073_A000_0073",
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X"B000_0074_A000_0074",
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X"B000_0075_A000_0075",
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X"B000_0076_A000_0076",
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X"B000_0077_A000_0077",
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X"B000_0078_A000_0078",
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X"B000_0079_A000_0079",
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X"B000_007A_A000_007A",
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X"B000_007B_A000_007B",
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X"B000_007C_A000_007C",
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X"B000_007D_A000_007D",
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X"B000_007E_A000_007E",
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X"B000_007F_A000_007F"
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);
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signal ram_dst : ram_t :=
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(
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000"
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);
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BEGIN
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inst_vga_frontend64 : entity work.vga_frontend64
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GENERIC MAP
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(
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fifo_depth => 2048,
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fifo_almost_full_thresh => 2048-128,
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fifo_almost_empty_thresh => 512,
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BLIT_CHUNK_SIZE => 512,
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fifo_depth => 64,
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fifo_almost_full_thresh => 48,
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fifo_almost_empty_thresh => 16,
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BLIT_CHUNK_SIZE => 16,
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tsvga => tsvga
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)
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PORT MAP
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@@ -168,31 +453,66 @@ VGA_CLK_GEN: process
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variable dat_v : arr64_t;
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variable res: unsigned(63 downto 0);
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variable scan_count: unsigned(31 downto 0);
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variable blit_count: unsigned(31 downto 0);
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variable ram_data : unsigned(63 downto 0);
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begin
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if rising_edge(CLK_O) then
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if RST_O = '1' then
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scan_count := X"00000000";
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blit_count := X"00000000";
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for i in 0 to 11 loop
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dat_v(i) := X"FFFFFFFF_FFFFFFFF";
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ack_v(i) := '0';
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end loop;
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else
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if (CYC_I and STB_I) = '1' and rdy = '1' and WE_I = '0' then
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if ADDR_I(24) = '0' then
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res := ADDR_I & scan_count;
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scan_count := scan_count + 8;
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else
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res := ADDR_I & blit_count;
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blit_count := blit_count + 8;
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if blit_count_rst = '1' then
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for i in 0 to 127 loop
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-- ram_dst(i) <= X"DEADBEEF" & X"DEADBEEF";
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ram_dst(i) <= (others => '-');
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end loop;
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end if;
|
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if (CYC_I and STB_I) = '1' and rdy = '1' then
|
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if WE_I = '0' then
|
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if ADDR_I(30) = '1' then
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if ADDR_I(2) = '0' then
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res := ADDR_I & scan_count;
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else
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res := scan_count & ADDR_I;
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end if;
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scan_count := scan_count + 8;
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else
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ram_data := ram_src(to_integer(ADDR_I(31 downto 3)));
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if ADDR_I(2) = '0' then
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res := ram_data;
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else
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res := ram_data(31 downto 0) & ram_data(63 downto 32);
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end if;
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end if;
|
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dat_v := dat_v(10 downto 0) & res;
|
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ack_v := ack_v(10 downto 0) & '1';
|
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else -- WE=1
|
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ram_data := ram_dst(to_integer(ADDR_I(31 downto 3)));
|
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if ADDR_I(2) = '0' then
|
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if SEL_I = "11111111" then
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ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I;
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elsif SEL_I = "00001111" then
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ram_dst(to_integer(ADDR_I(31 downto 3))) <= ram_data(63 downto 32) & MDAT_I(31 downto 0);
|
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elsif SEL_I = "11110000" then
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ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I(63 downto 32) & ram_data(31 downto 0);
|
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end if;
|
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else
|
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if SEL_I = "11111111" then
|
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ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I(31 downto 0) & MDAT_I(63 downto 32);
|
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elsif SEL_I = "00001111" then
|
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ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I(31 downto 0) & ram_data(31 downto 0);
|
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elsif SEL_I = "11110000" then
|
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ram_dst(to_integer(ADDR_I(31 downto 3))) <= ram_data(63 downto 32) & MDAT_I(63 downto 32);
|
||||
end if;
|
||||
end if;
|
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end if;
|
||||
dat_v := dat_v(10 downto 0) & res;
|
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ack_v := ack_v(10 downto 0) & '1';
|
||||
else
|
||||
dat_v := dat_v(10 downto 0) & X"FFFFFFFF_FFFFFFFF";
|
||||
ack_v := ack_v(10 downto 0) & '0';
|
||||
end if;
|
||||
|
||||
MDAT_O <= dat_v(dat_v'left);
|
||||
ACK_O <= ack_v(ack_v'left);
|
||||
end if;
|
||||
@@ -393,6 +713,7 @@ STIMULUS: process
|
||||
|
||||
for i in 0 to blit_size_array_t'length-1 loop
|
||||
|
||||
wait for 600*CLK_PERIOD;
|
||||
|
||||
-------------------------------------------------
|
||||
-- BLIT aligned => aligned test
|
||||
@@ -403,21 +724,26 @@ STIMULUS: process
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
state <= LA_SA;
|
||||
|
||||
blit_count_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
blit_count_rst <= '0';
|
||||
|
||||
-- set source start address
|
||||
reg_write(X"0000_0020", X"4100_0000");
|
||||
reg_write(X"0000_0020", X"0000_0000");
|
||||
|
||||
-- set src dim-x
|
||||
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0028", to_unsigned(4*32, 32));
|
||||
|
||||
-- set destination start address
|
||||
reg_write(X"0000_0050", X"4200_0000");
|
||||
reg_write(X"0000_0050", X"0000_0000");
|
||||
|
||||
-- set constant color
|
||||
reg_write(X"0000_0054", const_color);
|
||||
|
||||
-- set dst dim-x
|
||||
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0058", to_unsigned(4*32, 32));
|
||||
|
||||
-- set nx
|
||||
reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32));
|
||||
@@ -428,8 +754,8 @@ STIMULUS: process
|
||||
-- set blit request
|
||||
reg_read(X"0000_0000");
|
||||
reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
|
||||
|
||||
|
||||
wait for 600*CLK_PERIOD;
|
||||
-------------------------------------------------
|
||||
-- BLIT unaligned => aligned test
|
||||
-------------------------------------------------
|
||||
@@ -439,21 +765,25 @@ STIMULUS: process
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
blit_count_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
blit_count_rst <= '0';
|
||||
state <= LU_SA;
|
||||
|
||||
-- set source start address
|
||||
reg_write(X"0000_0020", X"4100_0004");
|
||||
reg_write(X"0000_0020", X"0000_0004");
|
||||
|
||||
-- set src dim-x
|
||||
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0028", to_unsigned(4*32, 32));
|
||||
|
||||
-- set destination start address
|
||||
reg_write(X"0000_0050", X"4200_0000");
|
||||
reg_write(X"0000_0050", X"0000_0000");
|
||||
|
||||
-- set constant color
|
||||
reg_write(X"0000_0054", const_color);
|
||||
|
||||
-- set dst dim-x
|
||||
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0058", to_unsigned(4*32, 32));
|
||||
|
||||
-- set nx
|
||||
reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32));
|
||||
@@ -465,6 +795,7 @@ STIMULUS: process
|
||||
reg_read(X"0000_0000");
|
||||
reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
|
||||
|
||||
wait for 600*CLK_PERIOD;
|
||||
|
||||
-------------------------------------------------
|
||||
-- BLIT aligned => unaligned test
|
||||
@@ -475,21 +806,25 @@ STIMULUS: process
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
blit_count_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
blit_count_rst <= '0';
|
||||
state <= LA_SU;
|
||||
|
||||
-- set source start address
|
||||
reg_write(X"0000_0020", X"4100_0000");
|
||||
reg_write(X"0000_0020", X"0000_0000");
|
||||
|
||||
-- set src dim-x
|
||||
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0028", to_unsigned(4*32, 32));
|
||||
|
||||
-- set destination start address
|
||||
reg_write(X"0000_0050", X"4200_0004");
|
||||
reg_write(X"0000_0050", X"0000_0004");
|
||||
|
||||
-- set constant color
|
||||
reg_write(X"0000_0054", const_color);
|
||||
|
||||
-- set dst dim-x
|
||||
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0058", to_unsigned(4*32, 32));
|
||||
|
||||
-- set nx
|
||||
reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32));
|
||||
@@ -501,7 +836,7 @@ STIMULUS: process
|
||||
reg_read(X"0000_0000");
|
||||
reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
|
||||
|
||||
|
||||
wait for 600*CLK_PERIOD;
|
||||
-------------------------------------------------
|
||||
-- BLIT unaligned => unaligned test
|
||||
-------------------------------------------------
|
||||
@@ -511,21 +846,25 @@ STIMULUS: process
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
blit_count_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
blit_count_rst <= '0';
|
||||
state <= LU_SU;
|
||||
|
||||
-- set source start address
|
||||
reg_write(X"0000_0020", X"4100_0004");
|
||||
reg_write(X"0000_0020", X"0000_0004");
|
||||
|
||||
-- set src dim-x
|
||||
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0028", to_unsigned(4*32, 32));
|
||||
|
||||
-- set destination start address
|
||||
reg_write(X"0000_0050", X"4200_0004");
|
||||
reg_write(X"0000_0050", X"0000_0004");
|
||||
|
||||
-- set constant color
|
||||
reg_write(X"0000_0054", const_color);
|
||||
|
||||
-- set dst dim-x
|
||||
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0058", to_unsigned(4*32, 32));
|
||||
|
||||
-- set nx
|
||||
reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32));
|
||||
@@ -537,6 +876,7 @@ STIMULUS: process
|
||||
reg_read(X"0000_0000");
|
||||
reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
|
||||
|
||||
wait for 600*CLK_PERIOD;
|
||||
-------------------------------------------------
|
||||
-- BLIT const => aligned test
|
||||
-------------------------------------------------
|
||||
@@ -546,21 +886,27 @@ STIMULUS: process
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
blit_count_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
blit_count_rst <= '0';
|
||||
state <= CC_SA;
|
||||
|
||||
const_color <= const_color + X"1111_1111";
|
||||
|
||||
-- set source start address
|
||||
reg_write(X"0000_0020", X"4100_0000");
|
||||
reg_write(X"0000_0020", X"0000_0000");
|
||||
|
||||
-- set src dim-x
|
||||
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0028", to_unsigned(4*32, 32));
|
||||
|
||||
-- set destination start address
|
||||
reg_write(X"0000_0050", X"4200_0000");
|
||||
reg_write(X"0000_0050", X"0000_0000");
|
||||
|
||||
-- set constant color
|
||||
reg_write(X"0000_0054", const_color);
|
||||
|
||||
-- set dst dim-x
|
||||
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0058", to_unsigned(4*32, 32));
|
||||
|
||||
-- set nx
|
||||
reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32));
|
||||
@@ -572,6 +918,7 @@ STIMULUS: process
|
||||
reg_read(X"0000_0000");
|
||||
reg_write(X"0000_0000", result or X"0001_0100");
|
||||
|
||||
wait for 600*CLK_PERIOD;
|
||||
-------------------------------------------------
|
||||
-- BLIT const => unaligned test
|
||||
-------------------------------------------------
|
||||
@@ -581,21 +928,27 @@ STIMULUS: process
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
blit_count_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
blit_count_rst <= '0';
|
||||
state <= CC_SU;
|
||||
|
||||
const_color <= const_color + X"1111_1111";
|
||||
|
||||
-- set source start address
|
||||
reg_write(X"0000_0020", X"4100_0000");
|
||||
reg_write(X"0000_0020", X"0000_0000");
|
||||
|
||||
-- set src dim-x
|
||||
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0028", to_unsigned(4*32, 32));
|
||||
|
||||
-- set destination start address
|
||||
reg_write(X"0000_0050", X"4200_0004");
|
||||
reg_write(X"0000_0050", X"0000_0004");
|
||||
|
||||
-- set constant color
|
||||
reg_write(X"0000_0054", const_color);
|
||||
|
||||
-- set dst dim-x
|
||||
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0058", to_unsigned(4*32, 32));
|
||||
|
||||
-- set nx
|
||||
reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32));
|
||||
@@ -607,10 +960,10 @@ STIMULUS: process
|
||||
reg_read(X"0000_0000");
|
||||
reg_write(X"0000_0000", result or X"0001_0100");
|
||||
|
||||
wait for 60000*CLK_PERIOD;
|
||||
const_color <= const_color + X"1111_1111";
|
||||
|
||||
wait for 600*CLK_PERIOD;
|
||||
|
||||
end loop;
|
||||
state <= IDLE;
|
||||
|
||||
wait;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user