- Blitter now works correctly. Supports non-aligned load/store.
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@957 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -60,13 +60,13 @@ ARCHITECTURE behavior OF tb_vga_frontend64 IS
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signal ACK_O : std_logic;
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signal MRDY_I : std_logic;
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signal SRDY_O : std_logic;
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signal ADDR_I : unsigned(31 downto 0) := (others => '-');
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signal ADDR_I : unsigned(31 downto 0) := (others => '0');
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signal SDAT_I : unsigned(31 downto 0) := (others => '-');
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signal SDAT_O : unsigned(31 downto 0) := (others => '-');
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signal rdy : std_logic := '0';
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signal read_reg : unsigned(31 downto 0) := (others => '-');
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signal const_color : unsigned(31 downto 0) := X"1111_1111";
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signal const_color : unsigned(31 downto 0) := X"0000_0000";
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-- VGA signals
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signal vga_clk : std_logic := '1';
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@@ -79,20 +79,305 @@ ARCHITECTURE behavior OF tb_vga_frontend64 IS
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signal vga_vsync : std_logic;
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signal vga_en : std_logic;
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type blit_size_array_t is array (0 to 6) of natural;
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type blit_size_array_t is array (0 to 9) of natural;
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constant blit_size_x : blit_size_array_t := (32, 31, 32, 31, 1, 32, 1);
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constant blit_size_y : blit_size_array_t := (32, 32, 31, 31, 32, 1, 1);
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constant blit_size_x : blit_size_array_t := (8, 1, 2, 7, 8, 7, 1, 8, 8, 0);
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constant blit_size_y : blit_size_array_t := (8, 1, 2, 8, 7, 7, 8, 1, 0, 8);
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signal blit_count_rst : std_logic := '0';
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type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU);
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signal state : state_t := IDLE;
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type ram_t is array (0 to 127) of unsigned(63 downto 0);
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signal ram_src : ram_t :=
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(
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X"B000_0000_A000_0000",
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X"B000_0001_A000_0001",
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X"B000_0002_A000_0002",
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X"B000_0003_A000_0003",
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X"B000_0004_A000_0004",
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X"B000_0005_A000_0005",
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X"B000_0006_A000_0006",
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X"B000_0007_A000_0007",
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X"B000_0008_A000_0008",
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X"B000_0009_A000_0009",
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X"B000_000A_A000_000A",
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X"B000_000B_A000_000B",
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X"B000_000C_A000_000C",
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X"B000_000D_A000_000D",
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X"B000_000E_A000_000E",
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X"B000_000F_A000_000F",
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X"B000_0010_A000_0010",
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X"B000_0011_A000_0011",
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X"B000_0012_A000_0012",
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X"B000_0013_A000_0013",
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X"B000_0014_A000_0014",
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X"B000_0015_A000_0015",
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X"B000_0016_A000_0016",
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X"B000_0017_A000_0017",
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X"B000_0018_A000_0018",
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X"B000_0019_A000_0019",
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X"B000_001A_A000_001A",
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X"B000_001B_A000_001B",
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X"B000_001C_A000_001C",
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X"B000_001D_A000_001D",
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X"B000_001E_A000_001E",
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X"B000_001F_A000_001F",
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X"B000_0020_A000_0020",
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X"B000_0021_A000_0021",
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X"B000_0022_A000_0022",
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X"B000_0023_A000_0023",
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X"B000_0024_A000_0024",
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X"B000_0025_A000_0025",
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X"B000_0026_A000_0026",
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X"B000_0027_A000_0027",
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X"B000_0028_A000_0028",
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X"B000_0029_A000_0029",
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X"B000_002A_A000_002A",
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X"B000_002B_A000_002B",
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X"B000_002C_A000_002C",
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X"B000_002D_A000_002D",
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X"B000_002E_A000_002E",
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X"B000_002F_A000_002F",
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X"B000_0030_A000_0030",
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X"B000_0031_A000_0031",
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X"B000_0032_A000_0032",
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X"B000_0033_A000_0033",
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X"B000_0034_A000_0034",
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X"B000_0035_A000_0035",
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X"B000_0036_A000_0036",
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X"B000_0037_A000_0037",
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X"B000_0038_A000_0038",
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X"B000_0039_A000_0039",
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X"B000_003A_A000_003A",
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X"B000_003B_A000_003B",
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X"B000_003C_A000_003C",
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X"B000_003D_A000_003D",
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X"B000_003E_A000_003E",
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X"B000_003F_A000_003F",
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X"B000_0040_A000_0040",
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X"B000_0041_A000_0041",
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X"B000_0042_A000_0042",
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X"B000_0043_A000_0043",
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X"B000_0044_A000_0044",
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X"B000_0045_A000_0045",
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X"B000_0046_A000_0046",
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X"B000_0047_A000_0047",
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X"B000_0048_A000_0048",
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X"B000_0049_A000_0049",
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X"B000_004A_A000_004A",
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X"B000_004B_A000_004B",
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X"B000_004C_A000_004C",
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X"B000_004D_A000_004D",
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X"B000_004E_A000_004E",
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X"B000_004F_A000_004F",
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X"B000_0050_A000_0050",
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X"B000_0051_A000_0051",
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X"B000_0052_A000_0052",
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X"B000_0053_A000_0053",
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X"B000_0054_A000_0054",
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X"B000_0055_A000_0055",
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X"B000_0056_A000_0056",
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X"B000_0057_A000_0057",
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X"B000_0058_A000_0058",
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X"B000_0059_A000_0059",
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X"B000_005A_A000_005A",
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X"B000_005B_A000_005B",
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X"B000_005C_A000_005C",
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X"B000_005D_A000_005D",
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X"B000_005E_A000_005E",
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X"B000_005F_A000_005F",
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X"B000_0060_A000_0060",
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X"B000_0061_A000_0061",
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X"B000_0062_A000_0062",
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X"B000_0063_A000_0063",
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X"B000_0064_A000_0064",
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X"B000_0065_A000_0065",
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X"B000_0066_A000_0066",
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X"B000_0067_A000_0067",
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X"B000_0068_A000_0068",
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X"B000_0069_A000_0069",
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X"B000_006A_A000_006A",
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X"B000_006B_A000_006B",
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X"B000_006C_A000_006C",
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X"B000_006D_A000_006D",
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X"B000_006E_A000_006E",
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X"B000_006F_A000_006F",
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X"B000_0070_A000_0070",
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X"B000_0071_A000_0071",
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X"B000_0072_A000_0072",
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X"B000_0073_A000_0073",
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X"B000_0074_A000_0074",
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X"B000_0075_A000_0075",
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X"B000_0076_A000_0076",
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X"B000_0077_A000_0077",
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X"B000_0078_A000_0078",
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X"B000_0079_A000_0079",
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X"B000_007A_A000_007A",
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X"B000_007B_A000_007B",
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X"B000_007C_A000_007C",
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X"B000_007D_A000_007D",
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X"B000_007E_A000_007E",
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X"B000_007F_A000_007F"
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);
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signal ram_dst : ram_t :=
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(
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000"
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);
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BEGIN
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inst_vga_frontend64 : entity work.vga_frontend64
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GENERIC MAP
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(
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fifo_depth => 2048,
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fifo_almost_full_thresh => 2048-128,
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fifo_almost_empty_thresh => 512,
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BLIT_CHUNK_SIZE => 512,
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fifo_depth => 64,
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fifo_almost_full_thresh => 48,
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fifo_almost_empty_thresh => 16,
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BLIT_CHUNK_SIZE => 16,
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tsvga => tsvga
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)
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PORT MAP
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@@ -168,31 +453,66 @@ VGA_CLK_GEN: process
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variable dat_v : arr64_t;
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variable res: unsigned(63 downto 0);
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variable scan_count: unsigned(31 downto 0);
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variable blit_count: unsigned(31 downto 0);
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variable ram_data : unsigned(63 downto 0);
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begin
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if rising_edge(CLK_O) then
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if RST_O = '1' then
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scan_count := X"00000000";
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blit_count := X"00000000";
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for i in 0 to 11 loop
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dat_v(i) := X"FFFFFFFF_FFFFFFFF";
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ack_v(i) := '0';
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end loop;
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else
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if (CYC_I and STB_I) = '1' and rdy = '1' and WE_I = '0' then
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if ADDR_I(24) = '0' then
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res := ADDR_I & scan_count;
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scan_count := scan_count + 8;
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else
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res := ADDR_I & blit_count;
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blit_count := blit_count + 8;
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if blit_count_rst = '1' then
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for i in 0 to 127 loop
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-- ram_dst(i) <= X"DEADBEEF" & X"DEADBEEF";
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ram_dst(i) <= (others => '-');
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end loop;
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end if;
|
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if (CYC_I and STB_I) = '1' and rdy = '1' then
|
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if WE_I = '0' then
|
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if ADDR_I(30) = '1' then
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if ADDR_I(2) = '0' then
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res := ADDR_I & scan_count;
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else
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res := scan_count & ADDR_I;
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end if;
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scan_count := scan_count + 8;
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else
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ram_data := ram_src(to_integer(ADDR_I(31 downto 3)));
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if ADDR_I(2) = '0' then
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res := ram_data;
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else
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res := ram_data(31 downto 0) & ram_data(63 downto 32);
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end if;
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end if;
|
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dat_v := dat_v(10 downto 0) & res;
|
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ack_v := ack_v(10 downto 0) & '1';
|
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else -- WE=1
|
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ram_data := ram_dst(to_integer(ADDR_I(31 downto 3)));
|
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if ADDR_I(2) = '0' then
|
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if SEL_I = "11111111" then
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ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I;
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elsif SEL_I = "00001111" then
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ram_dst(to_integer(ADDR_I(31 downto 3))) <= ram_data(63 downto 32) & MDAT_I(31 downto 0);
|
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elsif SEL_I = "11110000" then
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ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I(63 downto 32) & ram_data(31 downto 0);
|
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end if;
|
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else
|
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if SEL_I = "11111111" then
|
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ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I(31 downto 0) & MDAT_I(63 downto 32);
|
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elsif SEL_I = "00001111" then
|
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ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I(31 downto 0) & ram_data(31 downto 0);
|
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elsif SEL_I = "11110000" then
|
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ram_dst(to_integer(ADDR_I(31 downto 3))) <= ram_data(63 downto 32) & MDAT_I(63 downto 32);
|
||||
end if;
|
||||
end if;
|
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end if;
|
||||
dat_v := dat_v(10 downto 0) & res;
|
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ack_v := ack_v(10 downto 0) & '1';
|
||||
else
|
||||
dat_v := dat_v(10 downto 0) & X"FFFFFFFF_FFFFFFFF";
|
||||
ack_v := ack_v(10 downto 0) & '0';
|
||||
end if;
|
||||
|
||||
MDAT_O <= dat_v(dat_v'left);
|
||||
ACK_O <= ack_v(ack_v'left);
|
||||
end if;
|
||||
@@ -393,6 +713,7 @@ STIMULUS: process
|
||||
|
||||
for i in 0 to blit_size_array_t'length-1 loop
|
||||
|
||||
wait for 600*CLK_PERIOD;
|
||||
|
||||
-------------------------------------------------
|
||||
-- BLIT aligned => aligned test
|
||||
@@ -403,21 +724,26 @@ STIMULUS: process
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
state <= LA_SA;
|
||||
|
||||
blit_count_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
blit_count_rst <= '0';
|
||||
|
||||
-- set source start address
|
||||
reg_write(X"0000_0020", X"4100_0000");
|
||||
reg_write(X"0000_0020", X"0000_0000");
|
||||
|
||||
-- set src dim-x
|
||||
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0028", to_unsigned(4*32, 32));
|
||||
|
||||
-- set destination start address
|
||||
reg_write(X"0000_0050", X"4200_0000");
|
||||
reg_write(X"0000_0050", X"0000_0000");
|
||||
|
||||
-- set constant color
|
||||
reg_write(X"0000_0054", const_color);
|
||||
|
||||
-- set dst dim-x
|
||||
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0058", to_unsigned(4*32, 32));
|
||||
|
||||
-- set nx
|
||||
reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32));
|
||||
@@ -428,8 +754,8 @@ STIMULUS: process
|
||||
-- set blit request
|
||||
reg_read(X"0000_0000");
|
||||
reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
|
||||
|
||||
|
||||
wait for 600*CLK_PERIOD;
|
||||
-------------------------------------------------
|
||||
-- BLIT unaligned => aligned test
|
||||
-------------------------------------------------
|
||||
@@ -439,21 +765,25 @@ STIMULUS: process
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
blit_count_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
blit_count_rst <= '0';
|
||||
state <= LU_SA;
|
||||
|
||||
-- set source start address
|
||||
reg_write(X"0000_0020", X"4100_0004");
|
||||
reg_write(X"0000_0020", X"0000_0004");
|
||||
|
||||
-- set src dim-x
|
||||
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0028", to_unsigned(4*32, 32));
|
||||
|
||||
-- set destination start address
|
||||
reg_write(X"0000_0050", X"4200_0000");
|
||||
reg_write(X"0000_0050", X"0000_0000");
|
||||
|
||||
-- set constant color
|
||||
reg_write(X"0000_0054", const_color);
|
||||
|
||||
-- set dst dim-x
|
||||
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0058", to_unsigned(4*32, 32));
|
||||
|
||||
-- set nx
|
||||
reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32));
|
||||
@@ -465,6 +795,7 @@ STIMULUS: process
|
||||
reg_read(X"0000_0000");
|
||||
reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
|
||||
|
||||
wait for 600*CLK_PERIOD;
|
||||
|
||||
-------------------------------------------------
|
||||
-- BLIT aligned => unaligned test
|
||||
@@ -475,21 +806,25 @@ STIMULUS: process
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
blit_count_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
blit_count_rst <= '0';
|
||||
state <= LA_SU;
|
||||
|
||||
-- set source start address
|
||||
reg_write(X"0000_0020", X"4100_0000");
|
||||
reg_write(X"0000_0020", X"0000_0000");
|
||||
|
||||
-- set src dim-x
|
||||
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0028", to_unsigned(4*32, 32));
|
||||
|
||||
-- set destination start address
|
||||
reg_write(X"0000_0050", X"4200_0004");
|
||||
reg_write(X"0000_0050", X"0000_0004");
|
||||
|
||||
-- set constant color
|
||||
reg_write(X"0000_0054", const_color);
|
||||
|
||||
-- set dst dim-x
|
||||
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0058", to_unsigned(4*32, 32));
|
||||
|
||||
-- set nx
|
||||
reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32));
|
||||
@@ -501,7 +836,7 @@ STIMULUS: process
|
||||
reg_read(X"0000_0000");
|
||||
reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
|
||||
|
||||
|
||||
wait for 600*CLK_PERIOD;
|
||||
-------------------------------------------------
|
||||
-- BLIT unaligned => unaligned test
|
||||
-------------------------------------------------
|
||||
@@ -511,21 +846,25 @@ STIMULUS: process
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
blit_count_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
blit_count_rst <= '0';
|
||||
state <= LU_SU;
|
||||
|
||||
-- set source start address
|
||||
reg_write(X"0000_0020", X"4100_0004");
|
||||
reg_write(X"0000_0020", X"0000_0004");
|
||||
|
||||
-- set src dim-x
|
||||
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0028", to_unsigned(4*32, 32));
|
||||
|
||||
-- set destination start address
|
||||
reg_write(X"0000_0050", X"4200_0004");
|
||||
reg_write(X"0000_0050", X"0000_0004");
|
||||
|
||||
-- set constant color
|
||||
reg_write(X"0000_0054", const_color);
|
||||
|
||||
-- set dst dim-x
|
||||
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0058", to_unsigned(4*32, 32));
|
||||
|
||||
-- set nx
|
||||
reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32));
|
||||
@@ -537,6 +876,7 @@ STIMULUS: process
|
||||
reg_read(X"0000_0000");
|
||||
reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
|
||||
|
||||
wait for 600*CLK_PERIOD;
|
||||
-------------------------------------------------
|
||||
-- BLIT const => aligned test
|
||||
-------------------------------------------------
|
||||
@@ -546,21 +886,27 @@ STIMULUS: process
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
blit_count_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
blit_count_rst <= '0';
|
||||
state <= CC_SA;
|
||||
|
||||
const_color <= const_color + X"1111_1111";
|
||||
|
||||
-- set source start address
|
||||
reg_write(X"0000_0020", X"4100_0000");
|
||||
reg_write(X"0000_0020", X"0000_0000");
|
||||
|
||||
-- set src dim-x
|
||||
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0028", to_unsigned(4*32, 32));
|
||||
|
||||
-- set destination start address
|
||||
reg_write(X"0000_0050", X"4200_0000");
|
||||
reg_write(X"0000_0050", X"0000_0000");
|
||||
|
||||
-- set constant color
|
||||
reg_write(X"0000_0054", const_color);
|
||||
|
||||
-- set dst dim-x
|
||||
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0058", to_unsigned(4*32, 32));
|
||||
|
||||
-- set nx
|
||||
reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32));
|
||||
@@ -572,6 +918,7 @@ STIMULUS: process
|
||||
reg_read(X"0000_0000");
|
||||
reg_write(X"0000_0000", result or X"0001_0100");
|
||||
|
||||
wait for 600*CLK_PERIOD;
|
||||
-------------------------------------------------
|
||||
-- BLIT const => unaligned test
|
||||
-------------------------------------------------
|
||||
@@ -581,21 +928,27 @@ STIMULUS: process
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
blit_count_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
blit_count_rst <= '0';
|
||||
state <= CC_SU;
|
||||
|
||||
const_color <= const_color + X"1111_1111";
|
||||
|
||||
-- set source start address
|
||||
reg_write(X"0000_0020", X"4100_0000");
|
||||
reg_write(X"0000_0020", X"0000_0000");
|
||||
|
||||
-- set src dim-x
|
||||
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0028", to_unsigned(4*32, 32));
|
||||
|
||||
-- set destination start address
|
||||
reg_write(X"0000_0050", X"4200_0004");
|
||||
reg_write(X"0000_0050", X"0000_0004");
|
||||
|
||||
-- set constant color
|
||||
reg_write(X"0000_0054", const_color);
|
||||
|
||||
-- set dst dim-x
|
||||
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
|
||||
reg_write(X"0000_0058", to_unsigned(4*32, 32));
|
||||
|
||||
-- set nx
|
||||
reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32));
|
||||
@@ -607,10 +960,10 @@ STIMULUS: process
|
||||
reg_read(X"0000_0000");
|
||||
reg_write(X"0000_0000", result or X"0001_0100");
|
||||
|
||||
wait for 60000*CLK_PERIOD;
|
||||
const_color <= const_color + X"1111_1111";
|
||||
|
||||
wait for 600*CLK_PERIOD;
|
||||
|
||||
end loop;
|
||||
state <= IDLE;
|
||||
|
||||
wait;
|
||||
|
||||
|
||||
+351
-290
@@ -22,15 +22,14 @@ use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.utils_pkg.all;
|
||||
use work.align_types.all;
|
||||
use work.vga_types.all;
|
||||
|
||||
entity vga_frontend64 is
|
||||
Generic
|
||||
(
|
||||
fifo_depth : integer := 2048;
|
||||
fifo_almost_full_thresh : natural := 2000;
|
||||
fifo_almost_empty_thresh : natural := 48;
|
||||
fifo_depth : integer := 4096;
|
||||
fifo_almost_full_thresh : natural := 4000;
|
||||
fifo_almost_empty_thresh : natural := 800;
|
||||
BLIT_CHUNK_SIZE : natural := 512;
|
||||
tsvga : vga_timespec_t := ts_vga_800_600_72
|
||||
);
|
||||
@@ -171,59 +170,58 @@ architecture Behavioral of vga_frontend64 is
|
||||
|
||||
-- Blitter vars
|
||||
signal blit_chunk_cnt : natural range 0 to BLIT_CHUNK_SIZE-1;
|
||||
signal blit_chunk_cnt_rst : std_logic;
|
||||
signal blit_chunk_cnt_en : std_logic;
|
||||
signal blit_chunk_full : std_logic;
|
||||
|
||||
-- Blitter FIFO signals
|
||||
signal blitfifo_dout_vld : std_logic;
|
||||
signal blitfifo_write_en : std_logic;
|
||||
signal blitfifo_read_en : std_logic;
|
||||
signal blitfifo_full : unsigned(1 downto 0);
|
||||
signal blitfifo_empty : unsigned(1 downto 0);
|
||||
signal blitfifo_we : unsigned(1 downto 0);
|
||||
signal blitfifo_re : unsigned(1 downto 0);
|
||||
signal blitfifo_din : unsigned(63 downto 0);
|
||||
signal blitfifo_dout_0 : unsigned(31 downto 0);
|
||||
signal blitfifo_dout_1 : unsigned(31 downto 0);
|
||||
|
||||
-- Source Blitter FIFO signals
|
||||
signal blitfifo_src_full : std_logic;
|
||||
signal blitfifo_src_empty : std_logic;
|
||||
signal blitfifo_src_re : std_logic;
|
||||
signal blitfifo_src_we : std_logic;
|
||||
signal blitfifo_src_out : unsigned(63 downto 0);
|
||||
signal blitfifo_src_in : unsigned(63 downto 0);
|
||||
|
||||
-- Source alignment register
|
||||
signal blit_src_addr : unsigned(2 downto 0);
|
||||
signal blit_src_reg_vld : std_logic;
|
||||
signal blit_src_reg : unsigned(63 downto 0);
|
||||
signal blit_src_rdy : std_logic;
|
||||
signal blit_src_we : std_logic;
|
||||
signal blit_src_re : std_logic;
|
||||
signal blit_src_unaligned : std_logic;
|
||||
signal blit_src_do_extra : std_logic;
|
||||
signal blit_src_do_extra2 : std_logic;
|
||||
|
||||
signal blit_src_row_cnt : unsigned(31 downto 0);
|
||||
signal blit_src_first : std_logic;
|
||||
signal blit_src_last : std_logic;
|
||||
-- BLIT Source register
|
||||
signal blit_src_cnt_x_next : unsigned(32 downto 0);
|
||||
signal blit_src_cnt_x : unsigned(31 downto 0);
|
||||
signal blit_src_cnt_y : unsigned(31 downto 0);
|
||||
signal blit_src_off_y : unsigned(31 downto 0);
|
||||
signal blit_src_offset : unsigned(31 downto 0);
|
||||
signal blit_src_addr_next : unsigned(31 downto 0);
|
||||
signal blit_src_finish : std_logic;
|
||||
signal blit_src_START_U : std_logic;
|
||||
signal blit_src_START_A : std_logic;
|
||||
signal blit_src_STOP_U : std_logic;
|
||||
signal blit_src_STOP_A : std_logic;
|
||||
|
||||
signal CYC_O_blit_src : std_logic;
|
||||
signal STB_O_blit_src : std_logic;
|
||||
signal ADDR_O_blit_src : unsigned(31 downto 0);
|
||||
signal blit_src_nx : unsigned(31 downto 0);
|
||||
|
||||
-- Destination alignment register
|
||||
signal blit_dst_cmd_rdy : std_logic;
|
||||
signal blit_dst_cmd_vld : std_logic;
|
||||
signal blit_dst_din_rdy : std_logic;
|
||||
signal blit_dst_din_vld : std_logic;
|
||||
signal blit_dst_dout_re : std_logic;
|
||||
signal blit_dst_dout_be : unsigned(7 downto 0);
|
||||
signal blit_dst_dout_vld : std_logic;
|
||||
-- BLIT Destination register
|
||||
signal blit_dst_cnt_x_next : unsigned(32 downto 0);
|
||||
signal blit_dst_cnt_x : unsigned(31 downto 0);
|
||||
signal blit_dst_cnt_y : unsigned(31 downto 0);
|
||||
signal blit_dst_offset : unsigned(31 downto 0);
|
||||
signal blit_dst_dout : unsigned(63 downto 0);
|
||||
signal blit_dst_addr_next : unsigned(31 downto 0);
|
||||
signal blit_dst_finish : std_logic;
|
||||
signal blit_dst_cmd : align_cmd_in_t;
|
||||
signal blitfifo_empty_read : std_logic;
|
||||
signal blit_dst_suspend : std_logic;
|
||||
signal blit_dst_be : unsigned(7 downto 0);
|
||||
|
||||
-- BLIT Source Tracker
|
||||
signal blit_fill_cnt_x_next : unsigned(32 downto 0);
|
||||
signal blit_fill_cnt_x : unsigned(31 downto 0);
|
||||
signal blit_fill_cnt_y : unsigned(31 downto 0);
|
||||
signal blit_fill_offset : unsigned(2 downto 0);
|
||||
signal blit_fill_finish : std_logic;
|
||||
signal blit_fill_addr : unsigned(2 downto 0);
|
||||
|
||||
signal blit_const_color : unsigned(31 downto 0);
|
||||
signal blit_const_color_en : std_logic;
|
||||
signal blit_const_color_vld : std_logic;
|
||||
|
||||
|
||||
signal CYC_O_blit_dst : std_logic;
|
||||
signal STB_O_blit_dst : std_logic;
|
||||
@@ -231,6 +229,7 @@ architecture Behavioral of vga_frontend64 is
|
||||
|
||||
signal odd_pixel : unsigned(NextExpBaseTwo(tsvga.ts_h.ncyc_scan)-1 downto 0);
|
||||
|
||||
|
||||
-- Bus output FIFO
|
||||
signal busout_fifo_din : unsigned(104 downto 0);
|
||||
signal busout_fifo_dout : unsigned(104 downto 0);
|
||||
@@ -260,9 +259,23 @@ architecture Behavioral of vga_frontend64 is
|
||||
signal busin_fifo_rdy : std_logic;
|
||||
signal busin_fifo_dout_vld : std_logic;
|
||||
|
||||
type vm_state_t is (init, rdy, scan_bus_request, scan_bus_read, blit_src_bus_request, blit_src_bus_read, blit_dst_prime_pipe, blit_dst_bus_request, bus_fin);
|
||||
type vm_state_t is (init, rdy, scan_bus_request, scan_bus_read, blit_src_bus_request, blit_src_bus_read, blit_dst_bus_request, const_dst_bus_request, bus_fin);
|
||||
signal s, sn : vm_state_t;
|
||||
|
||||
type debug_t is
|
||||
record
|
||||
FIRST : std_logic;
|
||||
LAST : std_logic;
|
||||
UNALIGNED : std_logic;
|
||||
PARTIAL : std_logic;
|
||||
N_ODD : std_logic;
|
||||
re : unsigned(1 downto 0);
|
||||
end record debug_t;
|
||||
|
||||
signal src_dbg : debug_t;
|
||||
signal fill_dbg : debug_t;
|
||||
signal dst_dbg : debug_t;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
@@ -406,6 +419,7 @@ inst_linefifo: entity work.fifo_async
|
||||
fifo_color_re <= stat_scan and odd_pixel(0);
|
||||
fifo_color_we <= busin_fifo_dout_vld and CYC_O_scan; -- TODO:
|
||||
|
||||
|
||||
-- Bus input FIFO
|
||||
inst_busin_fifo: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
@@ -431,7 +445,7 @@ inst_busin_fifo: entity work.fifo_sync
|
||||
busin_fifo_din <= MDAT_I;
|
||||
busin_fifo_we <= ACK_I and bus_cycle_en and bus_read_en;
|
||||
busin_fifo_dout_vld <= not busin_fifo_empty;
|
||||
busin_fifo_re <= not fifo_full when CYC_O_scan = '1' else blit_src_we;
|
||||
busin_fifo_re <= not fifo_full when CYC_O_scan = '1' else CYC_O_blit_src;
|
||||
|
||||
-- Bus output FIFO
|
||||
inst_busout_fifo: entity work.fifo_sync
|
||||
@@ -457,14 +471,40 @@ inst_busout_fifo: entity work.fifo_sync
|
||||
busout_fifo_rdy <= not busout_fifo_full;
|
||||
busout_fifo_re <= not busout_fifo_empty and SRDY_I;
|
||||
busout_fifo_we <= bus_cycle_en and (STB_O_scan or STB_O_blit_src or STB_O_blit_dst);
|
||||
busout_fifo_data_in <= blit_dst_dout;
|
||||
busout_fifo_data_in <= (blitfifo_dout_1 & blitfifo_dout_0) when blit_const_color_en = '0' else (blit_const_color & blit_const_color);
|
||||
busout_fifo_addr_in <= ADDR_O_blit_src when CYC_O_blit_src = '1' else
|
||||
ADDR_O_blit_dst when CYC_O_blit_dst = '1' else
|
||||
ADDR_O_scan;
|
||||
busout_fifo_sel_in <= blit_dst_dout_be when CYC_O_blit_dst = '1' else (others => '1');
|
||||
busout_fifo_sel_in <= blit_dst_be;
|
||||
busout_fifo_we_in <= CYC_O_blit_dst;
|
||||
request_en <= bus_cycle_en and busout_fifo_we and busout_fifo_rdy;
|
||||
CYC_O <= bus_cycle_en;
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
ADDR_O_scan <= front + (to_unsigned(pixel_cnt, 29) & "000");
|
||||
|
||||
proc_scan_addr:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
bufchg <= '0';
|
||||
if vga_scan_dma_en2 = '0' then
|
||||
pixel_cnt <= 0;
|
||||
front <= host_fb_front;
|
||||
elsif STB_O_scan = '1' and busout_fifo_rdy = '1' then
|
||||
if pixel_cnt /= MAX_REQUEST_CNT/2-1 then
|
||||
pixel_cnt <= pixel_cnt + 1;
|
||||
else
|
||||
pixel_cnt <= 0;
|
||||
front <= host_fb_back;
|
||||
bufchg <= '1';
|
||||
end if;
|
||||
end if;
|
||||
vga_fb_front <= front;
|
||||
vga_fb_back <= back;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
-- VGA master FSM
|
||||
vga_master_next:
|
||||
@@ -480,7 +520,7 @@ vga_master_next:
|
||||
end process;
|
||||
|
||||
vga_master:
|
||||
process(s, stat_vga_rdy, vga_scan_dma_en2, fifo_almost_empty, fifo_almost_full, bus_read_fin, busout_fifo_rdy, busout_fifo_empty, blit_chunk_cnt, blitfifo_src_empty, blit_dst_dout_vld, blit_src_finish, blit_const_color_en)
|
||||
process(s, stat_vga_rdy, vga_scan_dma_en2, fifo_almost_empty, fifo_almost_full, bus_read_fin, busout_fifo_empty, blit_request, blit_dst_suspend, blit_chunk_full, blitfifo_dout_vld, blit_src_finish, blitfifo_empty_read, blit_dst_finish, blit_const_color_en)
|
||||
begin
|
||||
|
||||
CYC_O_scan <= '0';
|
||||
@@ -490,12 +530,8 @@ vga_master:
|
||||
CYC_O_blit_dst <= '0';
|
||||
STB_O_blit_dst <= '0';
|
||||
request_cnt_rst <= '0';
|
||||
request_en <= '0';
|
||||
bus_read_en <= '0';
|
||||
|
||||
bus_cycle_en <= '0';
|
||||
blit_chunk_cnt_rst <= '0';
|
||||
blit_chunk_cnt_en <= '0';
|
||||
|
||||
sn <= s;
|
||||
case s is
|
||||
@@ -506,14 +542,15 @@ vga_master:
|
||||
|
||||
when rdy =>
|
||||
request_cnt_rst <= '1';
|
||||
blit_chunk_cnt_rst <= '1';
|
||||
if fifo_almost_empty = '1' and vga_scan_dma_en2 = '1' then
|
||||
sn <= scan_bus_request;
|
||||
elsif blit_request = '1' then -- ToDo: richtig prüfen anhand eines states wer dran ist. Nicht auf FIFO state prüfen
|
||||
if blit_dst_dout_vld = '1' then
|
||||
sn <= blit_dst_bus_request;
|
||||
elsif blit_const_color_en = '0' then
|
||||
sn <= blit_dst_bus_request;
|
||||
if blitfifo_dout_vld = '0' or blit_dst_suspend = '1' then
|
||||
sn <= blit_src_bus_request;
|
||||
if blit_const_color_en = '1' then
|
||||
sn <= const_dst_bus_request;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
@@ -521,7 +558,6 @@ vga_master:
|
||||
bus_cycle_en <= '1';
|
||||
CYC_O_scan <= '1';
|
||||
STB_O_scan <= '1';
|
||||
request_en <= '1';
|
||||
bus_read_en <= '1';
|
||||
if fifo_almost_full = '1' then
|
||||
sn <= scan_bus_read;
|
||||
@@ -537,39 +573,38 @@ vga_master:
|
||||
|
||||
when blit_src_bus_request =>
|
||||
bus_cycle_en <= '1';
|
||||
bus_read_en <= '1';
|
||||
CYC_O_blit_src <= '1';
|
||||
STB_O_blit_src <= '1';
|
||||
request_en <= '1';
|
||||
bus_read_en <= '1';
|
||||
blit_chunk_cnt_en <= '1';
|
||||
if blit_chunk_cnt = 0 or blit_src_finish = '1' then
|
||||
if blit_chunk_full = '1' or blit_src_finish = '1' then
|
||||
STB_O_blit_src <= '0';
|
||||
sn <= blit_src_bus_read;
|
||||
end if;
|
||||
|
||||
when blit_src_bus_read =>
|
||||
bus_cycle_en <= '1';
|
||||
CYC_O_blit_src <= '1';
|
||||
bus_read_en <= '1';
|
||||
CYC_O_blit_src <= '1';
|
||||
if bus_read_fin = '1' then
|
||||
sn <= rdy;
|
||||
end if;
|
||||
|
||||
-- when blit_dst_prime_pipe =>
|
||||
-- bus_cycle_en <= '1';
|
||||
-- CYC_O_blit_dst <= '1';
|
||||
-- STB_O_blit_dst <= blit_dst_dout_vld;
|
||||
-- blit_chunk_cnt_en <= blit_dst_dout_vld;
|
||||
-- if blit_dst_dout_vld = '1' then
|
||||
-- sn <= blit_dst_bus_request;
|
||||
-- end if;
|
||||
|
||||
when blit_dst_bus_request =>
|
||||
bus_cycle_en <= '1';
|
||||
CYC_O_blit_dst <= '1';
|
||||
STB_O_blit_dst <= blit_dst_dout_vld;
|
||||
blit_chunk_cnt_en <= blit_dst_dout_vld;
|
||||
if blit_chunk_cnt = 0 or blit_dst_dout_vld = '0' then
|
||||
sn <= bus_fin;
|
||||
STB_O_blit_dst <= '1';
|
||||
if blitfifo_empty_read = '1' or blitfifo_dout_vld = '0' or blit_dst_finish = '1' then
|
||||
STB_O_blit_dst <= '0';
|
||||
sn <= bus_fin;
|
||||
end if;
|
||||
|
||||
when const_dst_bus_request =>
|
||||
bus_cycle_en <= '1';
|
||||
CYC_O_blit_dst <= '1';
|
||||
STB_O_blit_dst <= '1';
|
||||
if blit_chunk_full = '1' or blit_dst_finish = '1' then
|
||||
STB_O_blit_dst <= '0';
|
||||
sn <= bus_fin;
|
||||
end if;
|
||||
|
||||
when bus_fin =>
|
||||
@@ -591,7 +626,7 @@ proc_bus_request_counter:
|
||||
if rising_edge(CLK_I) then
|
||||
if request_cnt_rst = '1' then
|
||||
request_cnt <= (others => '0');
|
||||
elsif request_en = '1' and busout_fifo_rdy = '1' then
|
||||
elsif request_en = '1' then
|
||||
request_cnt <= request_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
@@ -624,259 +659,285 @@ proc_blit_chunk_counter:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if blit_chunk_cnt_rst = '1' then
|
||||
blit_chunk_cnt <= BLIT_CHUNK_SIZE-1;
|
||||
elsif blit_chunk_cnt_en = '1' and busout_fifo_rdy = '1' then
|
||||
if blit_chunk_cnt /= 0 then
|
||||
if request_cnt_rst = '1' then
|
||||
blit_chunk_full <= '0';
|
||||
blit_chunk_cnt <= BLIT_CHUNK_SIZE-2;
|
||||
elsif request_en = '1' then
|
||||
if blit_chunk_cnt = 0 then
|
||||
blit_chunk_full <= '1';
|
||||
else
|
||||
blit_chunk_cnt <= blit_chunk_cnt - 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
blit_reset <= RST_I or (blit_request_set and not blit_request);
|
||||
|
||||
ADDR_O_scan <= front + (to_unsigned(pixel_cnt, 29) & "000");
|
||||
|
||||
proc_scan_addr:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
bufchg <= '0';
|
||||
if vga_scan_dma_en2 = '0' then
|
||||
pixel_cnt <= 0;
|
||||
front <= host_fb_front;
|
||||
elsif STB_O_scan = '1' and busout_fifo_rdy = '1' then
|
||||
if pixel_cnt /= MAX_REQUEST_CNT/2-1 then
|
||||
pixel_cnt <= pixel_cnt + 1;
|
||||
else
|
||||
pixel_cnt <= 0;
|
||||
front <= host_fb_back;
|
||||
bufchg <= '1';
|
||||
end if;
|
||||
end if;
|
||||
vga_fb_front <= front;
|
||||
vga_fb_back <= back;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
inst_align_src : entity work.align
|
||||
GENERIC MAP
|
||||
(
|
||||
data_width => 64,
|
||||
aggregate_size => 8
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => blit_reset,
|
||||
clk => CLK_I,
|
||||
ce => blit_src_re,
|
||||
eb => '1',
|
||||
offset => blit_src_addr,
|
||||
din_vld => blit_src_we,
|
||||
din => busin_fifo_dout,
|
||||
dout_vld => blit_src_reg_vld,
|
||||
dout => blit_src_reg,
|
||||
byte_en => open
|
||||
|
||||
);
|
||||
|
||||
blit_src_we <= busin_fifo_dout_vld and CYC_O_blit_src; -- TODO:
|
||||
blit_src_re <= not blitfifo_src_full; -- TODO:
|
||||
|
||||
proc_blit_src_counter:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if blit_reset = '1' then
|
||||
blit_src_row_cnt <= to_unsigned(1, 32);
|
||||
blit_src_unaligned <= '0';
|
||||
blit_src_first <= '0';
|
||||
blit_src_last <= '0';
|
||||
blit_src_do_extra2 <= '0';
|
||||
if blit_src_addr (2 downto 0) /= "000" then
|
||||
blit_src_unaligned <= not blit_const_color_en;
|
||||
blit_src_first <= not blit_const_color_en;
|
||||
blit_src_do_extra2 <= not blit_const_color_en;
|
||||
end if;
|
||||
blit_src_nx <= '0' & blit_nx(blit_nx'left downto 1);
|
||||
elsif blit_src_re = '1' then
|
||||
if blit_src_reg_vld = '1' then
|
||||
blit_src_first <= '0';
|
||||
if blit_src_row_cnt /= blit_src_nx then
|
||||
blit_src_row_cnt <= blit_src_row_cnt + 1;
|
||||
elsif blit_src_do_extra2 = '1' then
|
||||
blit_src_do_extra2 <= '0';
|
||||
else
|
||||
if blit_src_unaligned = '1' then
|
||||
blit_src_do_extra2 <= '1';
|
||||
end if;
|
||||
blit_src_row_cnt <= to_unsigned(1, 32);
|
||||
blit_src_first <= blit_src_unaligned;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_blitfifo_src: entity work.fifo_sync
|
||||
inst_blitfifo_src0: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(BLIT_CHUNK_SIZE),
|
||||
data_width => blitfifo_src_in'length
|
||||
data_width => 32,
|
||||
|
||||
do_last_read_update => false
|
||||
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => blit_reset,
|
||||
clk => CLK_I,
|
||||
we => blitfifo_src_we,
|
||||
re => blitfifo_src_re,
|
||||
data_w => blitfifo_src_in,
|
||||
data_r => blitfifo_src_out,
|
||||
fifo_full => blitfifo_src_full,
|
||||
fifo_empty => blitfifo_src_empty,
|
||||
we => blitfifo_we(0),
|
||||
re => blitfifo_re(0),
|
||||
data_w => blitfifo_din(31 downto 0),
|
||||
data_r => blitfifo_dout_0,
|
||||
fifo_full => blitfifo_full(0),
|
||||
fifo_empty => blitfifo_empty(0),
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open
|
||||
|
||||
);
|
||||
|
||||
blitfifo_src_we <= (blit_src_reg_vld and not blit_src_first) when blit_const_color_en = '0' else (blit_request and not blit_src_finish);
|
||||
blitfifo_src_in <= blit_src_reg when blit_const_color_en = '0' else (blit_const_color & blit_const_color);
|
||||
blitfifo_src_re <= blit_dst_din_rdy;
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
ADDR_O_blit_src <= blit_addr_src_0(31 downto 3) & "000" + blit_src_offset;
|
||||
blit_src_addr <= blit_addr_src_0(2 downto 0);
|
||||
|
||||
proc_blit_addr_src:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if blit_reset = '1' then
|
||||
blit_src_cnt_x <= to_unsigned(1, 32);
|
||||
blit_src_cnt_y <= to_unsigned(1, 32);
|
||||
blit_src_offset <= (others => '0');
|
||||
blit_src_off_y <= blit_dimx_src_0;
|
||||
blit_src_finish <= '0';
|
||||
blit_src_do_extra <= '0';
|
||||
if blit_src_addr (2 downto 0) /= "000" then
|
||||
blit_src_do_extra <= not blit_const_color_en;
|
||||
end if;
|
||||
elsif blit_src_finish = '0' and ((STB_O_blit_src = '1' and busout_fifo_rdy = '1') or (blit_const_color_en = '1' and blitfifo_src_full = '0')) then
|
||||
blit_src_offset <= blit_src_offset + 8;
|
||||
if blit_src_cnt_x /= blit_src_nx then
|
||||
blit_src_cnt_x <= blit_src_cnt_x + 1;
|
||||
elsif blit_src_do_extra = '1' then
|
||||
blit_src_do_extra <= '0';
|
||||
else
|
||||
if blit_src_unaligned = '1' then
|
||||
blit_src_do_extra <= '1';
|
||||
end if;
|
||||
if blit_src_cnt_y /= blit_ny then
|
||||
blit_src_cnt_x <= to_unsigned(1, 32);
|
||||
blit_src_offset <= blit_src_off_y;
|
||||
blit_src_cnt_y <= blit_src_cnt_y + 1;
|
||||
blit_src_off_y <= blit_src_off_y + blit_dimx_src_0;
|
||||
else
|
||||
blit_src_finish <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
inst_align_out : entity work.align_out
|
||||
GENERIC MAP
|
||||
inst_blitfifo_src1: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
data_width => 64,
|
||||
addr_width => 32,
|
||||
byte_size => 8
|
||||
addr_width => NextExpBaseTwo(BLIT_CHUNK_SIZE),
|
||||
data_width => 32,
|
||||
|
||||
do_last_read_update => false
|
||||
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => blit_reset,
|
||||
clk => CLK_I,
|
||||
cmd_rdy => blit_dst_cmd_rdy,
|
||||
cmd_vld => blit_dst_cmd_vld,
|
||||
cmd_in => blit_dst_cmd,
|
||||
din_rdy => blit_dst_din_rdy,
|
||||
din_vld => blit_dst_din_vld,
|
||||
din => blitfifo_src_out,
|
||||
dout_vld => blit_dst_dout_vld,
|
||||
dout => blit_dst_dout,
|
||||
dout_be => blit_dst_dout_be,
|
||||
dout_re => blit_dst_dout_re,
|
||||
addr_out => ADDR_O_blit_dst
|
||||
rst => blit_reset,
|
||||
clk => CLK_I,
|
||||
we => blitfifo_we(1),
|
||||
re => blitfifo_re(1),
|
||||
data_w => blitfifo_din(63 downto 32),
|
||||
data_r => blitfifo_dout_1,
|
||||
fifo_full => blitfifo_full(1),
|
||||
fifo_empty => blitfifo_empty(1),
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open
|
||||
|
||||
);
|
||||
blit_dst_din_vld <= not blitfifo_src_empty;
|
||||
blit_dst_dout_re <= CYC_O_blit_dst and busout_fifo_rdy;
|
||||
|
||||
-- inst_align_dst : entity work.align
|
||||
-- GENERIC MAP
|
||||
-- (
|
||||
-- data_width => 64,
|
||||
-- aggregate_size => 8
|
||||
-- )
|
||||
-- PORT MAP
|
||||
-- (
|
||||
-- rst => blit_reset,
|
||||
-- clk => CLK_I,
|
||||
-- eb => '1',
|
||||
-- ce => blit_dst_re,
|
||||
-- offset => blit_addr_dst(2 downto 0),
|
||||
-- din_vld => blit_dst_we,
|
||||
-- din => blitfifo_src_out,
|
||||
-- dout_vld => blit_dst_reg_vld,
|
||||
-- dout => blit_dst_reg,
|
||||
-- byte_en => blit_dst_reg_be
|
||||
--
|
||||
-- );
|
||||
|
||||
-- blit_dst_be <= blit_dst_reg_be when blit_dst_first = '1' else
|
||||
-- not blit_dst_reg_be when blit_dst_last = '1' else
|
||||
-- (others => '1');
|
||||
|
||||
|
||||
-- blit_dst_we <= not blitfifo_src_empty;
|
||||
-- blit_dst_re <= CYC_O_blit_dst and busout_fifo_rdy and not blit_dst_last;
|
||||
-- blit_dst_vld <= blit_dst_reg_vld or blit_dst_last;
|
||||
blitfifo_din <= busin_fifo_dout;
|
||||
blitfifo_write_en <= busin_fifo_dout_vld and CYC_O_blit_src;
|
||||
blitfifo_read_en <= busout_fifo_rdy and CYC_O_blit_dst;
|
||||
blitfifo_dout_vld <= not (blitfifo_empty(0) and blitfifo_empty(1));
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
blit_reset <= RST_I or (blit_request_set and not blit_request);
|
||||
|
||||
proc_blit_addr_dst:
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
blit_dst_be_gen:
|
||||
process(dst_dbg)
|
||||
begin
|
||||
blit_dst_be <= "11111111";
|
||||
if dst_dbg.UNALIGNED = '1' then
|
||||
if dst_dbg.FIRST = '1' then
|
||||
blit_dst_be <= "00001111";
|
||||
elsif dst_dbg.LAST = '1' then
|
||||
if dst_dbg.PARTIAL = '1' then
|
||||
blit_dst_be <= "11110000";
|
||||
end if;
|
||||
end if;
|
||||
elsif dst_dbg.LAST = '1' then
|
||||
if dst_dbg.PARTIAL = '1' then
|
||||
blit_dst_be <= "00001111";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
blitfifo_we_gen:
|
||||
process(fill_dbg, blitfifo_write_en)
|
||||
begin
|
||||
blitfifo_we <= (blitfifo_write_en & blitfifo_write_en);
|
||||
if fill_dbg.UNALIGNED = '1' then
|
||||
if fill_dbg.FIRST = '1' then
|
||||
blitfifo_we <= ('0' & blitfifo_write_en);
|
||||
elsif fill_dbg.LAST = '1' then
|
||||
if fill_dbg.PARTIAL = '1' then
|
||||
blitfifo_we <= (blitfifo_write_en & '0');
|
||||
end if;
|
||||
end if;
|
||||
elsif fill_dbg.LAST = '1' then
|
||||
if fill_dbg.PARTIAL = '1' then
|
||||
blitfifo_we <= ('0' & blitfifo_write_en);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
blitfifo_re_gen:
|
||||
process(dst_dbg, blitfifo_empty, blitfifo_read_en)
|
||||
variable fifo_re : unsigned(1 downto 0);
|
||||
variable empty_read : std_logic;
|
||||
begin
|
||||
fifo_re := (blitfifo_read_en & blitfifo_read_en);
|
||||
if dst_dbg.UNALIGNED = '1' then
|
||||
if dst_dbg.FIRST = '1' then
|
||||
fifo_re := ('0' & blitfifo_read_en);
|
||||
elsif dst_dbg.LAST = '1' then
|
||||
if dst_dbg.PARTIAL = '1' then
|
||||
fifo_re := (blitfifo_read_en & '0');
|
||||
end if;
|
||||
end if;
|
||||
elsif dst_dbg.LAST = '1' then
|
||||
if dst_dbg.PARTIAL = '1' then
|
||||
fifo_re := ('0' & blitfifo_read_en);
|
||||
end if;
|
||||
end if;
|
||||
empty_read := (blitfifo_empty(0) and fifo_re(0)) or (blitfifo_empty(1) and fifo_re(1));
|
||||
blitfifo_re <= fifo_re and not (empty_read & empty_read);
|
||||
blitfifo_empty_read <= empty_read;
|
||||
dst_dbg.re <= fifo_re;
|
||||
end process;
|
||||
|
||||
blit_dst_suspend_gen:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
blit_dst_finish <= '1';
|
||||
blit_dst_cmd_vld <= '0';
|
||||
elsif blit_reset = '1' then
|
||||
blit_dst_cmd.num_bytes <= blit_nx(blit_nx'left-2 downto 0) & "00";
|
||||
blit_dst_cmd.num_bytes_per_word <= 4;
|
||||
blit_dst_cmd.addr_start <= blit_addr_dst;
|
||||
blit_dst_cmd.eb <= '1';
|
||||
blit_dst_cnt_y <= to_unsigned(1, 32);
|
||||
blit_dst_offset <= blit_addr_dst;
|
||||
blit_dst_cmd_vld <= '1';
|
||||
blit_dst_finish <= '0';
|
||||
elsif blit_dst_finish = '0' then
|
||||
if blit_dst_cnt_y /= blit_ny then
|
||||
if blit_dst_cmd_rdy = '1' then
|
||||
blit_dst_cmd.addr_start <= blit_dst_cmd.addr_start + blit_dimx_dst;
|
||||
blit_dst_cnt_y <= blit_dst_cnt_y + 1;
|
||||
end if;
|
||||
else
|
||||
blit_dst_cmd_vld <= '0';
|
||||
blit_dst_finish <= '1';
|
||||
if blit_reset = '1' or CYC_O_blit_src = '1' then
|
||||
blit_dst_suspend <= '0';
|
||||
elsif blitfifo_read_en = '1' and blitfifo_empty_read = '1' then
|
||||
blit_dst_suspend <= not (blitfifo_empty(0) and blitfifo_empty(1));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
fill_dbg.LAST <= '1' when blit_fill_cnt_x_next = '0' & X"0000_0000" or blit_fill_cnt_x_next(32) = '1' else '0';
|
||||
fill_dbg.PARTIAL <= blit_fill_cnt_x_next(32);
|
||||
fill_dbg.N_ODD <= blit_nx(1);
|
||||
|
||||
blit_fill_cnt_x_next <= ('0' & blit_fill_cnt_x - 1) when fill_dbg.FIRST = '1' and fill_dbg.UNALIGNED = '1' else ('0' & blit_fill_cnt_x - 2);
|
||||
|
||||
blitfifo_fill_src_0:
|
||||
process(CLK_I)
|
||||
variable addr_next : unsigned(31 downto 0);
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if blit_reset = '1' then
|
||||
blit_fill_addr <= blit_addr_src_0(2) & "00";
|
||||
blit_fill_cnt_x <= blit_nx;
|
||||
blit_fill_cnt_y <= blit_ny;
|
||||
blit_fill_offset <= blit_dimx_src_0(2 downto 0);
|
||||
blit_fill_finish <= blit_const_color_en;
|
||||
fill_dbg.FIRST <= not blit_const_color_en;
|
||||
fill_dbg.UNALIGNED <= blit_addr_src_0(2);
|
||||
elsif blit_request = '1' then
|
||||
if blit_fill_finish = '0' and blitfifo_write_en = '1' then
|
||||
fill_dbg.FIRST <= '0';
|
||||
if blit_fill_cnt_x_next = '0' & X"0000_0000" or blit_fill_cnt_x_next(32) = '1' then
|
||||
if blit_fill_cnt_y < X"0000_0002" then
|
||||
blit_fill_finish <= '1';
|
||||
else
|
||||
addr_next := (blit_addr_src_0(31 downto 2) & "00") + blit_fill_offset;
|
||||
blit_fill_addr <= addr_next(2 downto 0);
|
||||
blit_fill_offset <= blit_fill_offset + blit_dimx_src_0(2 downto 0);
|
||||
blit_fill_cnt_x <= blit_nx;
|
||||
blit_fill_cnt_y <= blit_fill_cnt_y - 1;
|
||||
fill_dbg.FIRST <= '1';
|
||||
fill_dbg.UNALIGNED <= addr_next(2);
|
||||
end if;
|
||||
else
|
||||
blit_fill_cnt_x <= blit_fill_cnt_x_next(31 downto 0);
|
||||
blit_fill_addr <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
src_dbg.LAST <= '1' when blit_src_cnt_x_next = '0' & X"0000_0000" or blit_src_cnt_x_next(32) = '1' else '0';
|
||||
src_dbg.PARTIAL <= blit_src_cnt_x_next(32);
|
||||
src_dbg.N_ODD <= blit_nx(1);
|
||||
|
||||
blit_src_addr_next <= ADDR_O_blit_src + 8;
|
||||
blit_src_cnt_x_next <= ('0' & blit_src_cnt_x - 1) when src_dbg.FIRST = '1' and src_dbg.UNALIGNED = '1' else ('0' & blit_src_cnt_x - 2);
|
||||
|
||||
blit_request_addr_src:
|
||||
process(CLK_I)
|
||||
variable addr_next : unsigned(31 downto 0);
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if blit_reset = '1' then
|
||||
ADDR_O_blit_src <= blit_addr_src_0(31 downto 2) & "00";
|
||||
blit_src_cnt_x <= blit_nx;
|
||||
blit_src_cnt_y <= blit_ny;
|
||||
blit_src_offset <= blit_dimx_src_0;
|
||||
blit_src_finish <= blit_const_color_en;
|
||||
src_dbg.FIRST <= not blit_const_color_en;
|
||||
src_dbg.UNALIGNED <= blit_addr_src_0(2);
|
||||
elsif blit_request = '1' then
|
||||
if blit_src_finish = '0' and (STB_O_blit_src = '1' and busout_fifo_rdy = '1') then
|
||||
src_dbg.FIRST <= '0';
|
||||
if blit_src_cnt_x_next = '0' & X"0000_0000" or blit_src_cnt_x_next(32) = '1' then
|
||||
if blit_src_cnt_y < X"0000_0002" then
|
||||
blit_src_finish <= '1';
|
||||
else
|
||||
addr_next := (blit_addr_src_0(31 downto 2) & "00") + blit_src_offset;
|
||||
ADDR_O_blit_src <= addr_next;
|
||||
blit_src_offset <= blit_src_offset + blit_dimx_src_0;
|
||||
blit_src_cnt_x <= blit_nx;
|
||||
blit_src_cnt_y <= blit_src_cnt_y - 1;
|
||||
src_dbg.FIRST <= '1';
|
||||
src_dbg.UNALIGNED <= addr_next(2);
|
||||
end if;
|
||||
else
|
||||
ADDR_O_blit_src <= blit_src_addr_next;
|
||||
blit_src_cnt_x <= blit_src_cnt_x_next(31 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
dst_dbg.LAST <= '1' when blit_dst_cnt_x_next = '0' & X"0000_0000" or blit_dst_cnt_x_next(32) = '1' else '0';
|
||||
dst_dbg.PARTIAL <= blit_dst_cnt_x_next(32);
|
||||
dst_dbg.N_ODD <= blit_nx(1);
|
||||
|
||||
blit_dst_addr_next <= ADDR_O_blit_dst + 8;
|
||||
blit_dst_cnt_x_next <= ('0' & blit_dst_cnt_x - 1) when dst_dbg.FIRST = '1' and dst_dbg.UNALIGNED = '1' else ('0' & blit_dst_cnt_x - 2);
|
||||
|
||||
blit_request_addr_dst:
|
||||
process(CLK_I)
|
||||
variable addr_next : unsigned(31 downto 0);
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if blit_reset = '1' then
|
||||
ADDR_O_blit_dst <= blit_addr_dst(31 downto 2) & "00";
|
||||
blit_dst_cnt_x <= blit_nx;
|
||||
blit_dst_cnt_y <= blit_ny;
|
||||
blit_dst_offset <= blit_dimx_dst;
|
||||
blit_dst_finish <= '0';
|
||||
dst_dbg.FIRST <= '1';
|
||||
dst_dbg.UNALIGNED <= blit_addr_dst(2);
|
||||
elsif blit_request = '1' then
|
||||
if blit_dst_finish = '0' and (STB_O_blit_dst = '1' and busout_fifo_rdy = '1') then
|
||||
dst_dbg.FIRST <= '0';
|
||||
if blit_dst_cnt_x_next = '0' & X"0000_0000" or blit_dst_cnt_x_next(32) = '1' then
|
||||
if blit_dst_cnt_y < X"0000_0002" then
|
||||
blit_dst_finish <= '1';
|
||||
else
|
||||
addr_next := (blit_addr_dst(31 downto 2) & "00") + blit_dst_offset;
|
||||
ADDR_O_blit_dst <= addr_next;
|
||||
blit_dst_offset <= blit_dst_offset + blit_dimx_dst;
|
||||
blit_dst_cnt_x <= blit_nx;
|
||||
blit_dst_cnt_y <= blit_dst_cnt_y - 1;
|
||||
dst_dbg.FIRST <= '1';
|
||||
dst_dbg.UNALIGNED <= addr_next(2);
|
||||
end if;
|
||||
else
|
||||
ADDR_O_blit_dst <= blit_dst_addr_next;
|
||||
blit_dst_cnt_x <= blit_dst_cnt_x_next(31 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
inst_char_gen : entity work.char_gen
|
||||
GENERIC MAP
|
||||
|
||||
Reference in New Issue
Block a user