From 05a24f5fda67f63bf58461114058761d0059ca96 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Wed, 4 Nov 2009 10:39:14 +0000 Subject: [PATCH] - added BUFG for clk_out Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@597 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/VGA_ctrl/src/clkgen_virtex4.vhd | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/lib/VGA_ctrl/src/clkgen_virtex4.vhd b/lib/VGA_ctrl/src/clkgen_virtex4.vhd index c6510f2..d56bd66 100644 --- a/lib/VGA_ctrl/src/clkgen_virtex4.vhd +++ b/lib/VGA_ctrl/src/clkgen_virtex4.vhd @@ -48,6 +48,7 @@ architecture tech of clkgen is signal dcm_clk0 : std_logic; signal dcm_clk_fb : std_logic; + signal clk_out0 : std_logic; begin @@ -71,7 +72,8 @@ architecture tech of clkgen is FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023 STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( + port map + ( CLK0 => dcm_clk0, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => open, -- 270 degree DCM CLK output @@ -79,7 +81,7 @@ architecture tech of clkgen is CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => clk_out, -- DCM CLK synthesis out (M/D) + CLKFX => clk_out0, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => locked, -- DCM LOCK status output CLKFB => dcm_clk_fb, -- DCM clock feedback @@ -94,4 +96,11 @@ architecture tech of clkgen is I => dcm_clk0 -- Clock buffer input ); + BUFG_clk_out : BUFG + port map + ( + O => clk_out, -- Clock buffer output + I => clk_out0 -- Clock buffer input + ); + end tech;