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- added clkgen for vga

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git-svn-id: http://moon:8086/svn/vhdl/trunk@589 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-03 22:50:04 +00:00
parent b4be8c7433
commit 054d232b6c
1 changed files with 124 additions and 86 deletions
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projects/mips_sys/src/mips_sys.vhd
+124 -86
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@@ -44,7 +44,9 @@ GENERIC
(
sys_freq : integer := 100E6;
ddr_phaseshift : integer := 0;
ddr_frequency_hz : integer := 100E6
ddr_frequency_hz : integer := 100E6;
tsvga : vga_timespec_t := ts_vga_800_600_72
);
PORT
(
@@ -263,7 +265,6 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT vga_frontend64
GENERIC
(
sys_freq : integer;
fifo_depth : integer;
fifo_almost_full_thresh : natural;
fifo_almost_empty_thresh : natural;
@@ -300,7 +301,8 @@ ARCHITECTURE behavior OF mips_sys IS
SDAT_O : out unsigned(31 downto 0);
-- VGA signals
vga_clk_out : out std_logic;
vga_clk_in : in std_logic;
vga_clk_ce : in std_logic;
vga_red : out unsigned(7 downto 0);
vga_green : out unsigned(7 downto 0);
vga_blue : out unsigned(7 downto 0);
@@ -312,18 +314,20 @@ ARCHITECTURE behavior OF mips_sys IS
END COMPONENT;
signal nmi : std_logic;
signal rst : std_logic;
signal clk : std_logic;
signal eb : std_logic;
signal clk270 : std_logic;
signal clk270var : std_logic;
signal sdram_clk0 : std_logic;
signal sdram_clk270 : std_logic;
signal sdram_clk270var : std_logic;
signal vga_clk : std_logic;
signal vga_clk_prebuf : std_logic;
signal vga_clk_lock : std_logic;
signal rst_in : std_logic;
signal int_timer : std_logic;
signal int_uart0 : std_logic;
signal int_uart1 : std_logic;
signal uart1_tx : std_logic;
signal uart1_rx : std_logic;
signal locked : std_logic;
signal sdram_clk_lock : std_logic;
signal usb_addr : unsigned(31 downto 0);
signal ac97_rstn : std_logic;
signal mem_mapped_io : std_logic;
@@ -338,6 +342,8 @@ ARCHITECTURE behavior OF mips_sys IS
signal arb_gnt : unsigned (ARB_MAX_MASTER-1 downto 0);
-- J-Bus signals
signal CLK_O : std_logic;
signal RST_O : std_logic;
signal INT : unsigned(5 downto 0);
signal MDAT_I : word_t;
signal MDAT_O : word_t;
@@ -440,6 +446,10 @@ ARCHITECTURE behavior OF mips_sys IS
type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_gpio, mem_uart0, mem_uart1, mem_sdram, mem_vga, mem_ac97);
signal mem_area : mem_area_t;
attribute KEEP : string;
attribute KEEP of vga_clk : signal is "TRUE";
attribute KEEP of sdram_clk0 : signal is "TRUE";
BEGIN
------------------------------------
@@ -456,13 +466,15 @@ BEGIN
sys_error <= debug;
nmi <= not sys_rst_n_in;
rst_in <= not sys_rst_n_in and sys_btn(0) and sys_btn(2);
rst <= not locked;
sys_usb_rstn <= not gpo1(0);
sys_flash_byten <= '1';
usb_addr <= X"0000000" & "00" & ADDR_O(3 downto 2);
sys_flash_a <= '0' & flash_addr(24 downto 2) & '0';
flash_page_mode_en <= not mem_mapped_io;
CLK_O <= sys_clk_in;
RST_O <= not (sdram_clk_lock and vga_clk_lock);
SDAT_I_sdram <= MDAT_O & MDAT_O;
SEL_I_sdram <= "0000" & SEL_O;
@@ -472,6 +484,8 @@ BEGIN
uart1_rx <= sys_uart1_rx and sys_uart2_rx;
sys_uart3_tx <= sys_uart3_rx;
sys_vga_clk <= vga_clk;
---------------------------------------------------------------
-- Arbiter
MRDY_O <= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0';
@@ -492,10 +506,10 @@ BEGIN
MDAT_I_vga <= SDAT_O_sdram(63 downto 32) & MDAT_I;
arbiter_proc:
process(clk)
process(CLK_O)
begin
if rising_edge(clk) then
if rst = '1' then
if rising_edge(CLK_O) then
if RST_O = '1' then
arb_gnt <= (others => '0');
arb_idx <= 0;
elsif arb_req(arb_idx) = '0' then
@@ -512,9 +526,9 @@ arbiter_proc:
end process;
int_sample:
process(clk)
process(CLK_O)
begin
if rising_edge(clk) then
if rising_edge(CLK_O) then
INT <= int_timer & '0' & (gpo1(2) and INT_O_ac97) & (gpo1(1) and sys_usb_int) & (int_uart0 or int_uart1) & sys_btn(4);
end if;
end process;
@@ -623,8 +637,8 @@ inst_mips_top: mips_top
debug => debug,
eb => eb,
nmi => nmi,
RST_I => rst,
CLK_I => clk,
RST_I => RST_O,
CLK_I => CLK_O,
ACK_I => ACK_I_cpu,
SRDY_I => SRDY_I_cpu,
MRDY_O => MRDY_O_cpu,
@@ -641,8 +655,8 @@ inst_mips_top: mips_top
inst_rom_wb : rom_wb
PORT MAP
(
CLK_I => clk,
RST_I => rst,
CLK_I => CLK_O,
RST_I => RST_O,
CYC_I => CYC_I_rom,
STB_I => STB_O,
ACK_O => ACK_O_rom,
@@ -656,8 +670,8 @@ inst_rom_wb : rom_wb
inst_lcd_port: lcd_port
PORT MAP
(
clk => clk,
rst => rst,
clk => CLK_O,
rst => RST_O,
we => '0',
din => X"00",
dout => open,
@@ -670,8 +684,8 @@ inst_lcd_port: lcd_port
inst_gpio_wb : gpio_wb
PORT MAP
(
CLK_I => clk,
RST_I => rst,
CLK_I => CLK_O,
RST_I => RST_O,
CYC_I => CYC_I_gpio,
STB_I => STB_O,
SEL_I => SEL_O,
@@ -700,8 +714,8 @@ inst_flash_port : async_port_wb
)
PORT MAP
(
CLK_I => clk,
RST_I => rst,
CLK_I => CLK_O,
RST_I => RST_O,
CYC_I => CYC_I_flash,
STB_I => STB_O,
WE_I => WE_O,
@@ -732,8 +746,8 @@ inst_usb_port : async_port_wb
)
PORT MAP
(
CLK_I => clk,
RST_I => rst,
CLK_I => CLK_O,
RST_I => RST_O,
CYC_I => CYC_I_usb,
STB_I => STB_O,
WE_I => WE_O,
@@ -757,8 +771,8 @@ inst_usb_port : async_port_wb
inst_uart_wb_0 : uart_wb
PORT MAP
(
CLK_I => clk,
RST_I => rst,
CLK_I => CLK_O,
RST_I => RST_O,
CYC_I => CYC_I_uart0,
STB_I => STB_O,
SEL_I => SEL_O,
@@ -777,8 +791,8 @@ inst_uart_wb_0 : uart_wb
inst_uart_wb_1 : uart_wb
PORT MAP
(
CLK_I => clk,
RST_I => rst,
CLK_I => CLK_O,
RST_I => RST_O,
CYC_I => CYC_I_uart1,
STB_I => STB_O,
SEL_I => SEL_O,
@@ -795,81 +809,104 @@ inst_uart_wb_1 : uart_wb
);
inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk => ddr_frequency_hz,
fifo_depth => 5
)
PORT MAP
(
RST_I => rst,
CLK_I => clk,
CLK270_I => clk270,
CLK270VAR_I => clk270var,
CYC_I => CYC_I_sdram,
STB_I => STB_O,
SEL_I => SEL_I_sdram,
WE_I => WE_O,
ACK_O => ACK_O_sdram,
MRDY_I => MRDY_O,
SRDY_O => SRDY_O_sdram,
ADDR_I => ADDR_O,
DAT_I => SDAT_I_sdram,
DAT_O => SDAT_O_sdram,
-- SDRAM signals
sd_clk_p => sys_sdr_clk_p,
sd_clk_n => sys_sdr_clk_n,
sd_cke => sys_sdr_cke_q,
sd_cs_n => sys_sdr_cs_qn,
sd_cas_n => sys_sdr_cas_qn,
sd_ras_n => sys_sdr_ras_qn,
sd_we_n => sys_sdr_we_qn,
sd_addr => sys_sdr_a_q,
sd_ba => sys_sdr_ba_q,
sd_dm => sys_sdr_dm_q,
sd_dqs => sys_sdr_dqs_q,
sd_data => sys_sdr_data
);
inst_clockgen : entity work.clockgen
GENERIC MAP
(
sys1_phaseshift => 0,
frequency_hz => 100E6
clk_in_freq_hz => 100E6,
clk0_out_phaseshift => 0,
clk1_out_phaseshift => 0
)
PORT MAP
(
-- Clocks and Reset
rst => rst_in, -- external async reset, low active
clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board
clk_in => CLK_O, -- system clock (e.g. 100MHz), from board
clk_fb_in => sys_sdr_clk_fb, -- feedback clock
sys1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sys1_clk270_out => clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
sys0_clk0_out => clk, -- System clock #0, dcm#0 output 0°
sys0_clk270_out => clk270, -- System clock #0, dcm#0 output 270°
locked_out => locked, -- DCM locked status
clk0_0_out => sdram_clk0, -- System clock #0, dcm#0 output 0°
clk0_270_out => sdram_clk270, -- System clock #0, dcm#0 output 270°
clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
clk1_270_out => sdram_clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
locked_out => sdram_clk_lock, -- DCM locked status
error_out => open
);
inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk => ddr_frequency_hz,
fifo_depth => 5
)
PORT MAP
(
RST_I => RST_O,
CLK_I => CLK_O,
SDRAM_CLK0_I => sdram_clk0,
SDRAM_CLK270_I => sdram_clk270,
SDRAM_CLK270VAR_I => sdram_clk270var,
CYC_I => CYC_I_sdram,
STB_I => STB_O,
SEL_I => SEL_I_sdram,
WE_I => WE_O,
ACK_O => ACK_O_sdram,
MRDY_I => MRDY_O,
SRDY_O => SRDY_O_sdram,
ADDR_I => ADDR_O,
DAT_I => SDAT_I_sdram,
DAT_O => SDAT_O_sdram,
-- SDRAM signals
sd_clk_p => sys_sdr_clk_p,
sd_clk_n => sys_sdr_clk_n,
sd_cke => sys_sdr_cke_q,
sd_cs_n => sys_sdr_cs_qn,
sd_cas_n => sys_sdr_cas_qn,
sd_ras_n => sys_sdr_ras_qn,
sd_we_n => sys_sdr_we_qn,
sd_addr => sys_sdr_a_q,
sd_ba => sys_sdr_ba_q,
sd_dm => sys_sdr_dm_q,
sd_dqs => sys_sdr_dqs_q,
sd_data => sys_sdr_data
);
inst_clkgen: entity work.clkgen
GENERIC MAP
(
clk_in_freq_hz => sys_freq,
clk_out_freq_hz => tsvga.f_pxl_clk
)
PORT MAP
(
rst => rst_in,
clk_in => CLK_O,
clk_out => vga_clk_prebuf,
locked => vga_clk_lock
);
BUFG_out_clk : BUFG
port map
(
O => vga_clk, -- Clock buffer output
I => vga_clk_prebuf -- Clock buffer input
);
inst_vga_frontend : vga_frontend64
GENERIC MAP
(
sys_freq => 100E6,
fifo_depth => 2048,
fifo_almost_full_thresh => 1860,
fifo_almost_empty_thresh => 256,
tsvga => ts_vga_800_600_72
tsvga => tsvga
)
PORT MAP
(
-- System signals
RST_I => rst,
CLK_I => clk,
RST_I => RST_O,
CLK_I => CLK_O,
-- JBUS Master signals
CYC_O => CYC_O_vga,
@@ -896,7 +933,8 @@ inst_vga_frontend : vga_frontend64
SDAT_O => SDAT_O_vga,
-- VGA signals
vga_clk_out => sys_vga_clk,
vga_clk_in => vga_clk,
vga_clk_ce => vga_clk_lock,
vga_red => sys_vga_red,
vga_green => sys_vga_green,
vga_blue => sys_vga_blue,
@@ -914,8 +952,8 @@ inst_ac97_wb : entity work.ac97_wb
PORT MAP
(
-- J-Bus domain
CLK_I => clk,
RST_I => rst,
CLK_I => CLK_O,
RST_I => RST_O,
CYC_I => CYC_I_ac97,
STB_I => STB_O,
WE_I => WE_O,