From 03f21b37d47e3167b6b62366e6602796b8ed591c Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 25 Aug 2013 18:37:51 +0000 Subject: [PATCH] - added tlb_query results to pipe-stages ID and EX Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/branches/BRANCH_MIPS_TLB@1027 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/src/core/mips_pipeline.vhd | 28 +++++++++++++++++++----- lib/CPUs/MIPS/src/core/mips_types.vhd | 2 ++ 2 files changed, 24 insertions(+), 6 deletions(-) diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd index edfb737..af8382d 100644 --- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd +++ b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd @@ -439,15 +439,23 @@ proc_stage_branch_not_taken_alt: ID_stage.nop <= sdu.ID_nop; ID_stage.va <= ID_stage.reg_a + extract_simm32(ID_stage.IR); +ID_stage_tlb_query_results: + process(clk_1) + begin + if rising_edge(clk_1) then + ID_stage.itlb_qry <= itlb_qry_in; + end if; + end process; + proc_ID_except: process(ID_stage, ctrl_in, pc) begin ID_stage.events <= events_clr; ID_stage.events.inst_load_err <= not ctrl_in.exc_pending and (ID_stage.pcn(1) or ID_stage.pcn(0)); ID_stage.events.inst_priv_addr <= not ctrl_in.exc_pending and (ID_stage.pcn(word_t'left) and ctrl_in.user_mode); - ID_stage.events.ITLB_LOAD <= itlb_qry_in.vld and itlb_qry_in.miss and not itlb_qry_in.write; - ID_stage.events.ITLB_STORE <= itlb_qry_in.vld and itlb_qry_in.miss and itlb_qry_in.write; - ID_stage.events.ITLB_MOD <= itlb_qry_in.vld and itlb_qry_in.dirty; + ID_stage.events.ITLB_LOAD <= ID_stage.itlb_qry.vld and ID_stage.itlb_qry.miss and not ID_stage.itlb_qry.write; + ID_stage.events.ITLB_STORE <= ID_stage.itlb_qry.vld and ID_stage.itlb_qry.miss and ID_stage.itlb_qry.write; + ID_stage.events.ITLB_MOD <= ID_stage.itlb_qry.vld and ID_stage.itlb_qry.dirty; end process; proc_stage_hdu: @@ -563,6 +571,14 @@ inst_reg_dual: reg_dual EX_stage.reg_b_rptr <= extract_rt(EX_stage.IR); EX_stage.result <= alu_result when EX_stage.ctrl.mul_access = '0' else mul_result; +EX_stage_tlb_query_results: + process(clk_1) + begin + if rising_edge(clk_1) then + EX_stage.dtlb_qry <= dtlb_qry_in; + end if; + end process; + proc_stage_ID_EX_1: process(clk_1) begin @@ -881,9 +897,9 @@ proc_stage_MEM_except: MEM_stage.events <= MEM_stage.events_in; MEM_stage.events.Int <= ctrl_in.int; MEM_stage.events.NMI <= ctrl_in.NMI; - MEM_stage.events.DTLB_LOAD <= dtlb_qry_in.vld and dtlb_qry_in.miss and not dtlb_qry_in.write; - MEM_stage.events.DTLB_STORE <= dtlb_qry_in.vld and dtlb_qry_in.miss and dtlb_qry_in.write; - MEM_stage.events.DTLB_MOD <= dtlb_qry_in.vld and dtlb_qry_in.dirty; + MEM_stage.events.DTLB_LOAD <= EX_stage.dtlb_qry.vld and EX_stage.dtlb_qry.miss and not EX_stage.dtlb_qry.write; + MEM_stage.events.DTLB_STORE <= EX_stage.dtlb_qry.vld and EX_stage.dtlb_qry.miss and EX_stage.dtlb_qry.write; + MEM_stage.events.DTLB_MOD <= EX_stage.dtlb_qry.vld and EX_stage.dtlb_qry.dirty; end process; MEM_stage.exc <= event_is_active(MEM_stage.events); diff --git a/lib/CPUs/MIPS/src/core/mips_types.vhd b/lib/CPUs/MIPS/src/core/mips_types.vhd index 8b4a70f..e9859b7 100644 --- a/lib/CPUs/MIPS/src/core/mips_types.vhd +++ b/lib/CPUs/MIPS/src/core/mips_types.vhd @@ -489,6 +489,7 @@ package mips_types is reg_b : word_t; events : event_t; bcu_flags : bcu_flags_t; + itlb_qry : tlb_query_out_t; end record; type EX_t is record @@ -519,6 +520,7 @@ package mips_types is events : event_t; bcu_flags : bcu_flags_t; branch_not_taken : std_logic; + dtlb_qry : tlb_query_out_t; end record; type MEM_t is record