diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd index fffcd93..1c4090a 100644 --- a/projects/mips_sys/src/mips_sys.vhd +++ b/projects/mips_sys/src/mips_sys.vhd @@ -36,7 +36,8 @@ use work.mips_types.all; use work.sdram_config.all; use work.sdram_types.all; use work.vga_types.all; -use work.sys_types.all; +use work.async_types.all; +use work.async_defs.all; ENTITY mips_sys IS @@ -197,6 +198,7 @@ ARCHITECTURE behavior OF mips_sys IS ( addr_width : natural := 32; data_width : natural := 32; + byte_sel_width : natural := 4; async_timespec : async_timespec_t ); PORT @@ -209,13 +211,14 @@ ARCHITECTURE behavior OF mips_sys IS ACK_O : out STD_LOGIC; SRDY_O : out STD_LOGIC; MRDY_I : in STD_LOGIC; + SEL_I : in unsigned(3 downto 0); ADDR_I : in unsigned(31 downto 0); DAT_I : in unsigned(31 downto 0); DAT_O : out unsigned(31 downto 0); async_a : out unsigned(addr_width-1 downto 0); async_d : inout unsigned(data_width-1 downto 0); async_cs : out std_logic; - async_wr : out std_logic; + async_wr : out unsigned(byte_sel_width-1 downto 0); async_rd : out std_logic; async_rst : out std_logic ); @@ -328,6 +331,8 @@ ARCHITECTURE behavior OF mips_sys IS signal flash_addr : unsigned(31 downto 0); signal ac97_rstn : std_logic; signal flash_rstn : std_logic; + signal usb_wrn : unsigned(0 downto 0); + signal flash_wrn : unsigned(0 downto 0); -- Arbiter constant ARB_MAX_MASTER : natural := 2; @@ -456,6 +461,9 @@ BEGIN SEL_I_sdram <= "0000" & SEL_O; sys_flash_ac97_rstn <= ac97_rstn and flash_rstn; + sys_usb_wrn <= usb_wrn(0); + sys_flash_wrn <= flash_wrn(0); + --------------------------------------------------------------- -- Arbiter MRDY_O <= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0'; @@ -512,19 +520,19 @@ mem_mux: if ADDR_O(31 downto 28) = X"A" then if ADDR_O(27 downto 26) = "00" then if ADDR_O(18 downto 16) = "000" then - mem_area <= mem_gpio; - elsif ADDR_O(18 downto 16) = "001" then - mem_area <= mem_uart; - elsif ADDR_O(18 downto 16) = "010" then - mem_area <= mem_usb; - elsif ADDR_O(18 downto 16) = "011" then - mem_area <= mem_vga; - elsif ADDR_O(18 downto 16) = "100" then - mem_area <= mem_ac97; + mem_area <= mem_gpio; + elsif ADDR_O(18 downto 16) = "001" then + mem_area <= mem_uart; + elsif ADDR_O(18 downto 16) = "010" then + mem_area <= mem_usb; + elsif ADDR_O(18 downto 16) = "011" then + mem_area <= mem_vga; + elsif ADDR_O(18 downto 16) = "100" then + mem_area <= mem_ac97; + end if; + elsif ADDR_O(27 downto 26) = "01" then + mem_area <= mem_flash; end if; - elsif ADDR_O(27 downto 26) = "01" then - mem_area <= mem_flash; - end if; elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then mem_area <= mem_rom; elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then @@ -689,6 +697,7 @@ inst_flash_port : async_port_wb ( addr_width => 25, data_width => 32, + byte_sel_width => 1, async_timespec => ts_flash ) PORT MAP @@ -701,13 +710,14 @@ inst_flash_port : async_port_wb ACK_O => ACK_O_flash, SRDY_O => SRDY_O_flash, MRDY_I => MRDY_O, + SEL_I => SEL_O, ADDR_I => flash_addr, DAT_I => MDAT_O, DAT_O => SDAT_O_flash, async_a => sys_flash_a, async_d => sys_flash_d, async_cs => sys_flash_ce, - async_wr => sys_flash_wrn, + async_wr => flash_wrn, async_rd => sys_flash_rdn, async_rst => flash_rstn ); @@ -717,6 +727,7 @@ inst_usb_port : async_port_wb ( addr_width => 2, data_width => 16, + byte_sel_width => 1, async_timespec => ts_usb ) PORT MAP @@ -729,13 +740,14 @@ inst_usb_port : async_port_wb ACK_O => ACK_O_usb, SRDY_O => SRDY_O_usb, MRDY_I => MRDY_O, + SEL_I => SEL_O, ADDR_I => usb_addr, DAT_I => MDAT_O, DAT_O => SDAT_O_usb, async_a => sys_usb_a, async_d => sys_usb_d, async_cs => sys_usb_csn, - async_wr => sys_usb_wrn, + async_wr => usb_wrn, async_rd => sys_usb_rdn, async_rst => open ); @@ -876,7 +888,7 @@ inst_vga_frontend : vga_frontend64 inst_ac97_wb : entity work.ac97_wb GENERIC MAP ( - fifo_depth => 4 + fifo_depth => 8 ) PORT MAP ( diff --git a/projects/mips_sys/src/mips_sys_sim.vhd b/projects/mips_sys/src/mips_sys_sim.vhd index 1bc1348..e856264 100644 --- a/projects/mips_sys/src/mips_sys_sim.vhd +++ b/projects/mips_sys/src/mips_sys_sim.vhd @@ -36,7 +36,8 @@ use work.mips_types.all; use work.sdram_config.all; use work.sdram_types.all; use work.vga_types.all; -use work.sys_types.all; +use work.async_types.all; +use work.async_defs.all; ENTITY mips_sys IS @@ -207,6 +208,7 @@ ARCHITECTURE behavior OF mips_sys IS ( addr_width : natural := 32; data_width : natural := 32; + byte_sel_width : natural := 4; async_timespec : async_timespec_t ); PORT @@ -219,13 +221,14 @@ ARCHITECTURE behavior OF mips_sys IS ACK_O : out STD_LOGIC; SRDY_O : out STD_LOGIC; MRDY_I : in STD_LOGIC; + SEL_I : in unsigned(3 downto 0); ADDR_I : in unsigned(31 downto 0); DAT_I : in unsigned(31 downto 0); DAT_O : out unsigned(31 downto 0); async_a : out unsigned(addr_width-1 downto 0); async_d : inout unsigned(data_width-1 downto 0); async_cs : out std_logic; - async_wr : out std_logic; + async_wr : out unsigned(byte_sel_width-1 downto 0); async_rd : out std_logic; async_rst : out std_logic ); @@ -385,6 +388,7 @@ ARCHITECTURE behavior OF mips_sys IS signal flash_we_n : std_logic; signal flash_d_drv : std_logic; signal flash_bsy : std_logic; + signal usb_wrn : unsigned(0 downto 0); -- Arbiter constant ARB_MAX_MASTER : natural := 2; @@ -511,6 +515,7 @@ BEGIN rst_in <= not sys_rst_n_in; rst <= not locked; sys_usb_rstn <= not gpo1(0); + sys_usb_wrn <= usb_wrn(0); sys_flash_byten <= '1'; ADDR_I_usb <= X"0000000" & "00" & ADDR_O(3 downto 2); ADDR_I_flash <= "0000000" & ADDR_O(25 downto 2) & '0'; @@ -819,6 +824,7 @@ inst_usb_port : async_port_wb ( addr_width => 2, data_width => 16, + byte_sel_width => 1, async_timespec => ts_usb ) PORT MAP @@ -831,13 +837,14 @@ inst_usb_port : async_port_wb ACK_O => ACK_O_usb, SRDY_O => SRDY_O_usb, MRDY_I => MRDY_O, + SEL_I => SEL_O, ADDR_I => ADDR_I_usb, DAT_I => MDAT_O, DAT_O => SDAT_O_usb, async_a => sys_usb_a, async_d => sys_usb_d, async_cs => sys_usb_csn, - async_wr => sys_usb_wrn, + async_wr => usb_wrn, async_rd => sys_usb_rdn, async_rst => open );