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- added DMA_START and DMA_END strobe signals

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git-svn-id: http://moon:8086/svn/vhdl/trunk@977 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-05-28 11:23:23 +00:00
parent 27021a571d
commit 0253fc426d
4 changed files with 28 additions and 9 deletions
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lib/JBUS/src/tb_dmac.vhd
+5 -2
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@@ -1,5 +1,5 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_dmac.vhd,v 1.1 2013-05-28 10:18:02 jens Exp $
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_dmac.vhd,v 1.2 2013-05-28 11:23:15 jens Exp $
-----------------------------------------------------------------------
LIBRARY ieee;
@@ -25,7 +25,6 @@ ARCHITECTURE behavior OF tb_dmac IS
signal RST_O : std_logic := '1';
-- Master
signal INT_O : std_logic;
signal CYC_O : std_logic;
signal STB_O : std_logic;
signal WE_O : std_logic;
@@ -53,7 +52,9 @@ ARCHITECTURE behavior OF tb_dmac IS
signal dma_req_complete : unsigned(DMA_NUM_CHANNEL-1 downto 0);
signal dma_req_complete_ack : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
signal dma_start : unsigned(DMA_NUM_CHANNEL-1 downto 0);
signal dma_active : unsigned(DMA_NUM_CHANNEL-1 downto 0);
signal dma_end : unsigned(DMA_NUM_CHANNEL-1 downto 0);
signal dma_bus_cmd_cycle_finished : unsigned(DMA_NUM_CHANNEL-1 downto 0);
signal dma_bus_cmd_cycle_en : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
signal dma_bus_cmd_rdy : unsigned(DMA_NUM_CHANNEL-1 downto 0);
@@ -317,7 +318,9 @@ for i in 0 to DMA_NUM_CHANNEL-1 generate
req_complete => dma_req_complete(i),
req_complete_ack => dma_req_complete_ack(i),
dma_start => dma_start(i),
dma_active => dma_active(i),
dma_end => dma_end(i),
-- busmaster control
bus_cyc_complete => dma_bus_cmd_cycle_finished(i),