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- added DMA_START and DMA_END strobe signals

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git-svn-id: http://moon:8086/svn/vhdl/trunk@977 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-05-28 11:23:23 +00:00
parent 27021a571d
commit 0253fc426d
4 changed files with 28 additions and 9 deletions
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lib/JBUS/src/dmac.vhd
+17 -5
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@@ -1,5 +1,5 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/dmac.vhd,v 1.1 2013-05-28 10:18:02 jens Exp $
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/dmac.vhd,v 1.2 2013-05-28 11:23:15 jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
@@ -23,7 +23,9 @@ entity dmac is
master_req : out std_logic;
master_gnt : in std_logic;
dma_start : out std_logic;
dma_active : out std_logic;
dma_end : out std_logic;
req_rdy : out std_logic;
req_en : in std_logic;
@@ -66,7 +68,7 @@ architecture Behavioral of dmac is
signal chunk_count_next : unsigned(32 downto 0);
signal chunk_count_rdy : std_logic;
type state_t is (INIT, READY, SETUP, XFER, FINISH);
type state_t is (INIT, READY, START, SETUP, XFER, FINISH, DONE);
signal s, sn : state_t;
begin
@@ -101,7 +103,9 @@ state:
chunk_count_rst <= '0';
chunk_count_en <= '0';
master_req <= '0';
dma_start <= '0';
dma_active <= '0';
dma_end <= '0';
sn <= s;
case s is
@@ -113,9 +117,13 @@ state:
if req_en = '1' then
start_en <= '1';
sn <= SETUP;
end if;
end if;
when SETUP =>
dma_start <= '1';
sn <= START;
when START =>
master_req <= '1';
chunk_count_rst <= '1';
if req_count_rdy = '1' then
@@ -134,16 +142,20 @@ state:
if req_count_rdy = '1' then
sn <= FINISH;
elsif chunk_count_rdy = '1' then
sn <= SETUP;
sn <= START;
end if;
when FINISH =>
master_req <= '1';
if bus_cyc_complete = '1' then
sn <= READY;
sn <= DONE;
finish_en <= '1';
end if;
when DONE =>
dma_end <= '1';
sn <= READY;
when others =>
sn <= READY;