From 01739e1519d219d3662878641ff76a7b1d4bcf3b Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 22 Nov 2009 15:36:07 +0000 Subject: [PATCH] - bugfix blitter reset Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@674 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/VGA_ctrl/src/vga_frontend64.vhd | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/lib/VGA_ctrl/src/vga_frontend64.vhd b/lib/VGA_ctrl/src/vga_frontend64.vhd index 04e999b..021e3d6 100644 --- a/lib/VGA_ctrl/src/vga_frontend64.vhd +++ b/lib/VGA_ctrl/src/vga_frontend64.vhd @@ -145,7 +145,6 @@ architecture Behavioral of vga_frontend64 is signal blit_comb_sel : unsigned(3 downto 0); signal blit_request : std_logic; signal blit_request_set : std_logic; - signal blit_request_clr : std_logic; signal blit_complete : std_logic; signal blit_complete_ack : std_logic; signal blit_complete_inten : std_logic; @@ -180,7 +179,6 @@ architecture Behavioral of vga_frontend64 is signal blitfifo_color_out : unsigned(63 downto 0); signal blitfifo_color_in : unsigned(63 downto 0); - signal blit_reset : std_logic; signal blit_src_cnt_x : unsigned(31 downto 0); signal blit_src_cnt_y : unsigned(31 downto 0); signal blit_src_off_y : unsigned(31 downto 0); @@ -243,14 +241,11 @@ proc_blit_request_flags: process(CLK_I) begin if rising_edge(CLK_I) then - blit_reset <= '0'; if pixel_cnt_rst = '1' then blit_request <= '0'; - blit_reset <= '1'; elsif blit_request = '0' then if blit_request_set = '1' then blit_request <= '1'; - blit_reset <= '1'; end if; elsif blit_dst_finish = '1' and blitfifo_empty = '1' then blit_request <= '0'; @@ -264,10 +259,10 @@ proc_blit_complete_flag: if rising_edge(CLK_I) then if RST_I = '1' then blit_complete <= '0'; - elsif blit_dst_finish = '1' and blitfifo_empty = '1' then - blit_complete <= '1'; elsif blit_complete_ack = '1' then blit_complete <= '0'; + elsif blit_dst_finish = '1' and blitfifo_empty = '1' then + blit_complete <= '1'; end if; end if; end process; @@ -602,7 +597,7 @@ proc_blit_addr_src: process(CLK_I) begin if rising_edge(CLK_I) then - if blit_reset = '1' then + if RST_I = '1' or (blit_request_set and not blit_request) = '1' then blit_src_cnt_x <= (others => '0'); blit_src_cnt_y <= (others => '0'); blit_src_offset <= (others => '0'); @@ -632,7 +627,7 @@ proc_blit_addr_dst: process(CLK_I) begin if rising_edge(CLK_I) then - if blit_reset = '1' then + if RST_I = '1' or (blit_request_set and not blit_request) = '1' then blit_dst_cnt_x <= (others => '0'); blit_dst_cnt_y <= (others => '0'); blit_dst_offset <= (others => '0');