LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY ram_wb IS
	Port
	(
		CLK_I		: in  STD_LOGIC;
		RST_I		: in  STD_LOGIC;
		CYC_I		: in  STD_LOGIC;
		STB_I		: in  STD_LOGIC;
		SEL_I		: in  unsigned(3 downto 0);
		WE_I		: in  STD_LOGIC;
		ACK_O		: out STD_LOGIC;
		SRDY_O		: out STD_LOGIC;
		MRDY_I		: in  STD_LOGIC;
		ADDR_I		: in  unsigned(31 downto 0);
		DAT_I		: in  unsigned(31 downto 0);
		DAT_O		: out unsigned(31 downto 0)
	);
END ram_wb;

ARCHITECTURE behavior OF ram_wb IS

	COMPONENT ram
	GENERIC 
	(
		word_addr_width 	: integer
	);
	PORT 
	(
		clk			: in  STD_LOGIC;
		ce			: in  STD_LOGIC;
		we			: in  unsigned(3 downto 0);
		addr		: in  unsigned(31 downto 0);
		din			: in  unsigned(31 downto 0);
		dout		: out unsigned(31 downto 0)
	);
	END COMPONENT;

	signal data_en : std_logic;
	signal we : unsigned(3 downto 0);

begin

	we <= SEL_I and (3 downto 0 => WE_I);
	
	data_en	<= CYC_I and STB_I and MRDY_I;
	SRDY_O	<= CYC_I;
	
data_valid_register:
	process(CLK_I)
	begin
		if rising_edge(CLK_I) then
			if RST_I = '1' then
				ACK_O	<= '0';
			else
				ACK_O	<= data_en and not WE_I;
			end if;
		end if;
	end process;

inst_ram : ram
	GENERIC MAP 
	(
		word_addr_width	=> 6
	)
	PORT MAP 
	(
		clk		=> CLK_I,
		ce		=> data_en,
		we		=> we,
		addr	=> ADDR_I,
		din		=> DAT_I,
		dout	=> DAT_O
	);



end behavior;
