-- ============================================================================
--
-- Design unit		:	dual_sbox_virtex2 (dual AES S-box)
--
-- File Name		:	dual_sbox_virtex2.vhd
--
-- Purpose			:	The module provides dual (dual-port memory) AES S-box
--						on Virtex2 family
--
--
-- Depends on 		:
--
--	- Package(s)	:	Xilinx/unisim
--
--	- Module(s)		:	-
--
--
-- Dev. Platform	:	Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
--
--	- Simulator(s)	:	Modelsim XE III 6.0d
--
--	- Synthesis		:	Xilinx XST
--
--	- Place & Route	:	Xilinx PAR
--
--
-- Errors			:	None known
--
--
-- Limitations		:	None known
--
--
-- Notes			:	-
--
--
-- Author(s)		:	A. Freund (af) <a.freund@dsi-it.de>
--						Digitale Signalverabeitung & Informationstechnik GmbH,
--						Bremen, Germany
--
--
-- ============================================================================
--
-- Revision List:
-- Version		Author(s)		Date		Changes
--
-- v0.00		af				2006-11-15	initial version
--
-- see SVN logs
--
-- ============================================================================
--
-- Naming conventions:
--
-- 	- active-low signals are indicated by appending "_n"
--	- constants are in UPPERCASE
--	- name parts are separated by "_"
--
-- ============================================================================


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library unisim;
use unisim.vcomponents.all;


entity dual_sbox_virtex2 is
    port (
    	clk		:	in std_logic;						-- clock (rising)
    	enca	:	in std_logic;						-- encryption (0) / decryption (1) mode
    	encb	:	in std_logic;						-- encryption (0) / decryption (1) mode
    	posa	:	in std_logic_vector(7 downto 0);	-- position
    	posb	:	in std_logic_vector(7 downto 0);	-- position
    	dina	:	in std_logic_vector(7 downto 0);	-- write data
    	dinb	:	in std_logic_vector(7 downto 0);	-- write data
    	wea		:	in std_logic;						-- write enable
    	web		:	in std_logic;    					-- write enable
    	douta	:	out std_logic_vector(7 downto 0);	-- read data
    	doutb	:	out std_logic_vector(7 downto 0);	-- read data
    	is_init	:	out std_logic						-- pre-initialised memory
	);
end dual_sbox_virtex2;


architecture behavioral of dual_sbox_virtex2 is

	signal s_addra : std_logic_vector(10 downto 0);
	signal s_addrb : std_logic_vector(10 downto 0);

begin

	s_addra <= "00" & enca & posa;

	s_addrb <= "00" & encb & posb;


   -- RAMB16_S9_S9: Virtex-II/II-Pro 2k x 8 + 1 Parity bit Dual-Port RAM
   -- Xilinx  HDL Language Template version 7.1i

	sboxd: RAMB16_S9_S9
		generic map (
			WRITE_MODE_A => "READ_FIRST",	--  WRITE_FIRST, READ_FIRST or NO_CHANGE
			WRITE_MODE_B => "READ_FIRST",	--  WRITE_FIRST, READ_FIRST or NO_CHANGE
			SIM_COLLISION_CHECK => "NONE",	-- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
				INIT_00 => X"C072A49CAFA2D4ADF04759FA7DC982CA76ABD7FE2B670130C56F6BF27B777C63",
				INIT_01 => X"75B227EBE28012079A059618C323C7041531D871F1E5A534CCF73F362693FDB7",
				INIT_02 => X"CF584C4A39BECB6A5BB1FC20ED00D153842FE329B3D63B52A05A6E1B1A2C8309",
				INIT_03 => X"D2F3FF1021DAB6BCF5389D928F40A351A89F3C507F02F94585334D43FBAAEFD0",
				INIT_04 => X"DB0B5EDE14B8EE4688902A22DC4F816073195D643D7EA7C41744975FEC130CCD",
				INIT_05 => X"08AE7A65EAF4566CA94ED58D6D37C8E779E4959162ACD3C25C2406490A3A32E0",
				INIT_06 => X"9E1DC186B95735610EF6034866B53E708A8BBD4B1F74DDE8C6B4A61C2E2578BA",
				INIT_07 => X"16BB54B00F2D99416842E6BF0D89A18CDF2855CEE9871E9B948ED9691198F8E1",
				INIT_08 => X"CBE9DEC444438E3487FF2F9B8239E37CFBD7F3819EA340BF38A53630D56A0952",
				INIT_09 => X"25D18B6D49A25B76B224D92866A12E084EC3FA420B954CEE3D23C2A632947B54",
				INIT_0A => X"849D8DA75746155EDAB9EDFD5048706C92B6655DCC5CA4D41698688664F6F872",
				INIT_0B => X"6B8A130103BDAFC1020F3FCA8F1E2CD00645B3B80558E4F70AD3BC8C00ABD890",
				INIT_0C => X"6EDF751CE837F9E28535ADE72274AC9673E6B4F0CECFF297EADC674F4111913A",
				INIT_0D => X"F45ACD78FEC0DB9A2079D2C64B3E56FC1BBE18AA0E62B76F89C5291D711AF147",
				INIT_0E => X"EF9CC9939F7AE52D0D4AB519A97F51605FEC8027591012B131C7078833A8DD1F",
				INIT_0F => X"7D0C2155631469E126D677BA7E042B17619953833CBBEBC8B0F52AAE4D3BE0A0"
		)
		port map (
			DOA		=> douta(7 downto 0),	-- Port A 8-bit Data Output
			DOB		=> doutb(7 downto 0),	-- Port B 8-bit Data Output
			DOPA	=> open,				-- Port A 1-bit Parity Output
			DOPB	=> open,				-- Port B 1-bit Parity Output
			ADDRA	=> s_addra,				-- Port A 11-bit Address Input
			ADDRB	=> s_addrb,				-- Port B 11-bit Address Input
			CLKA	=> clk,					-- Port A Clock
			CLKB	=> clk,					-- Port B Clock
			DIA		=> dina(7 downto 0),	-- Port A 8-bit Data Input
			DIB		=> dinb(7 downto 0),	-- Port B 8-bit Data Input
			DIPA	=> "0",					-- Port A 1-bit parity Input
			DIPB	=> "0",					-- Port-B 1-bit parity Input
			ENA		=> '1',					-- Port A RAM Enable Input
			ENB		=> '1',					-- Port B RAM Enable Input
			SSRA	=> '0',					-- Port A Synchronous Set/Reset Input
			SSRB	=> '0',					-- Port B Synchronous Set/Reset Input
			WEA		=> wea,					-- Port A Write Enable Input
			WEB		=> web					-- Port B Write Enable Input
		);


	is_init <= '1';


end behavioral;
