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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:01:32 07/10/2006 
-- Design Name: 
-- Module Name:    fix_top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

package my_pkg is
	type my_t is array (integer range <>) of std_logic;
end package;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

use work.my_pkg.all;

entity top is
    Port ( rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           din : in  my_t (0 downto -15);
           dout : out  my_t (0 downto -15));

end top;

architecture Behavioral of top is

begin

process(clk, rst, din)
variable var1 : my_t (0 downto -15) := (others => '0');

begin
	if (rst = '1') then
		var1 := (others => '0');
--		dout <= (others => '0'); -- Commented out due to HDL Advisior's advice
	elsif rising_edge(clk) then
		dout <= var1;
		var1 := din;
	end if;
	
end process;

end Behavioral;

