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-- Company: 
-- Engineer:
--
-- Create Date:    12:33:39 10/08/05
-- Design Name:    
-- Module Name:    eval_synch_top - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity eval_synch_top is
	 Generic (N : integer := 8);
    Port ( rst : in std_logic;
           clk : in std_logic;
           din : in std_logic;
           dout : out std_logic_vector(0 to N-1));
end eval_synch_top;

architecture Behavioral of eval_synch_top is

	COMPONENT d_ff
	GENERIC(tpd : time);
	PORT(
		rst : IN std_logic;
		clk : IN std_logic;
		din : IN std_logic;          
		dout : OUT std_logic
		);
	END COMPONENT;

-------------------------------------------------
signal d_i : std_logic_vector(0 to N);

begin

d_i(0) <= din;
dout <= d_i(1 to N);

inst_shift_reg : for i in 1 to N generate 

		Inst_d_ff: d_ff 
		GENERIC MAP(tpd => 2.5 ns)
		PORT MAP(
			rst => rst,
			clk => clk,
			din => d_i(i-1),
			dout => d_i(i)
		);

end generate;

end Behavioral;
