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Changes in release 13
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- mips_biu.vhd: added asynchronous BUS-FIFOs to support different clocks for CPU and BUS
- mips_dcache.vhd: improved instant-RAW stall behavior (faster execution)
- uart_WB.vhd: added simulate_TX generic for plain TX output in simulation log

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Changes in release 12
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- reworked GCC-toolchain: Valid mips*-elf-binaries are now compiled and linked
  using a single mips*-elf-gcc command.
  To use: Copy $THIS_RELEASE/bsp/toolchain/specs to $MIPS_GCC_PREFIX/lib/gcc/mipsel-elf/$GCC_VERSION/,
  and see bsp/examples/Makefile gcc usage
  GCC-provided crt*-functions are now called without problems.
  In summary: The toolchain is now more compliant to the intentional use of GCC.
- mips_biu.vhd: Addresses 0xA0000000..0xBFFFFFFF are now un-dcached for memory-mapped I/O,
  which is now compliant to literature. 
- gpio_wb.vhd: Timer hard-reset is now removed. This helps to keep current time in case of CPU hard-reset.
- new bsp-example source: gunzip
- updated drawing 'mips_jbus_timing.pdf'
- added drawing 'memory_map.pdf' 
- moved COP0 from mips_pipeline.vhd to mips_top.vhd. Created new cop-interface for later COPz connection.
- added I/D-cache info (size and linesize) to upper 16 bits of PrID-Register.
  Example of reading cache info is done in bsp/examples/testbench::PrintCPUinfo()
- simplified instruction decoder in mips_instr.vhd. Now there are less warnings during synthesis.
  Removed idecode_rom.vhd from project as consequence.
- added cop0 instructions to invalidate I-cache and D-Cache
- added copz instructions lwcz and swcz
- gpio_wb.vhd: added 32 bit timer with interrupt and auto reload
- added debugger in libsys. New files are mipsdis.c/h and dbg.c/h
- exception handlers can now be registered to any exception type 
- bugfix mips_pipeline/mips_cop: cop0 registers were not written during exception commit. Cop registers now behave like general registers.
- added pin 'eb' to mips_top.vhd to select CPU-endianess at reset time (eb = 0 : little-endian, eb = 1 : big-endian)
- Status register bit 'RE'= 1 (bit 25) reverses endianess in user-mode
- Status register bit 'TS' (TLB Shutdown, bit 21) is tied high to indicate the absence of an MMU.
- uart_wb.vhd: added interrupt enable
- Interrupt pending flags (IP) are not anymore masked by Interrupt mask flags (IM) in H/W. 
  Masking has to be done in S/W. H/W masking was removed because it isn't MIPS-compliant. 
- added NMI/RST pin (more MIPS compliant). Transition Asserting/Deasserting causes exception. 
  Exception vector is reset (0xBFC00000). It's a soft-reset, which can help debugging. NMI/RST is not maskable.
  Using NMI/RST as reset is dangerous because periphery may not be reseted. Has to be done in S/W.
  Drawback of using NMI/RST: Unitialized/unreseted periphery may cause trouble (e.g. firing unwanted interrupts), but I think you know that already.
- Bootloader: Startup.S now invalidates I/D-Caches at boot.
- uart_wb.vhd: fixed crappy tx-empty interrupt, Added Tx-IRQ acknowledge.
- Bugfix in mips_pipeline: register bypass with same target register, used for unaligned loads (LWL, LWR), was incorrect.
  Newlib's MIPS-optimized version of memcpy() uses this for unaligned copy which revealed the bug.  
  Symptom: Consecutive load instructions without nops using same target register (which is legal) like
   lw $1, 0(mem)
   lwl $1, 1(mem)
  or
   lwl $1, 0(mem)
   lwr $1, 1(mem)
  or similar, lead to incorrect result. Now it's fixed.
- Bugfix mips_biu: instructions uncached LW => cached LW (with cache-miss) was buggy.
  Symptom:
  ...
  1.: lw     $a0, 32($s0)  # Uncached load from memory mapped I/O
  2.: lw     $a2, 4($v0)   # Cached load and cache-miss.
                           # $a0 receives same value as $a2.
                           # CPU skips writing $a0 due to busy flag of D-Cache,
                           # which is already active in the previous cycle
  ...

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Changes in release 11
-----------------------------------------------------------------
- bugfix in mips_pipeline: pc_is_branch is now initialized at reset
  (fixes CPU unrecoverable state after reset)
- reverted "optimization" in mips_dcache, which behaved buggy during exceptions
- new example source: test_exception
- minor changes in libsys
- added async_port_timing in doc
- examples/testbench: date set now really works

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Changes in release 10b
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- bugfix: fixed compiler bug (missing nop after lw) in bootloader,
  which caused exception during boot

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Changes in release 10a
-----------------------------------------------------------------
async_port_wb:
- added byte enable for async_port

bootloader.c
- bugfix: fixed compiler bug (missing nop after lw)

mips-core
- bugfix: SEL_O lines are also asserted correctly during reads

tools/romgen
- TCL-Jtag now compatible with Chipscope 10.1

mips_sys.c
- use byte enable for sram and flash


