-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: cpu_embedded using cpu_core and rom

-- Copyright (C) 2007 J. Ahrensfeld

-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.

-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-- Lesser General Public License for more details.

-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA

-- For questions and ideas, please contact the author at jens@jayfield.org

-----------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

use work.cpu_pkg.all;

entity cpu_embedded is
	Port (
		rst			: in  STD_LOGIC;
		clk			: in  STD_LOGIC;
		ce			: in  STD_LOGIC;
		int_in		: in  STD_LOGIC;
		int_ack		: out STD_LOGIC;
		xmem_we		: out STD_LOGIC;
		xmem_re		: out STD_LOGIC;
		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
		xmem_addr	: out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
		io_sel		: out STD_LOGIC
	);
end cpu_embedded;

architecture rtl of cpu_embedded is

	signal rom_data	: unsigned (IMEM_DATA_WIDTH-1 downto 0);
	signal rom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0);

	COMPONENT cpu
	Port (
		rst			: in  STD_LOGIC;
		clk			: in  STD_LOGIC;
		ce			: in  STD_LOGIC;
		int_in		: in  STD_LOGIC;
		int_ack		: out  STD_LOGIC;
		xmem_wait	: in  STD_LOGIC;
		xmem_we		: out  STD_LOGIC;
		xmem_re		: out  STD_LOGIC;
		instr_din	: in  unsigned (IMEM_DATA_WIDTH-1 downto 0);
		instr_addr	: out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
		xmem_addr	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
		io_sel		: out STD_LOGIC
	);
	END COMPONENT;


	COMPONENT irom
		Port (
			clk			: in  STD_LOGIC;
			ce			: in  STD_LOGIC;
			addr		: in  inst_addr_t;
			dout		: out inst_t
		);
	END COMPONENT;

begin

inst_cpu: cpu
	PORT MAP(
		rst => rst,
		clk => clk,
		ce => ce,
		int_in => int_in,
		int_ack => int_ack,
		xmem_wait => '0',
		xmem_we => xmem_we,
		xmem_re => xmem_re,
		instr_din => rom_data,
		instr_addr => rom_addr,
		xmem_din => xmem_din,
		xmem_dout => xmem_dout,
		xmem_addr => xmem_addr,
		io_sel => io_sel
	);

inst_irom: irom
	PORT MAP(
		clk			=> clk,
		ce			=> ce,
		addr		=> rom_addr,
		dout 		=> rom_data
	);

end rtl;
