
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   17:33:47 06/05/2007
-- Design Name:   eval_ac
-- Module Name:   E:/work/VHDL/eval_ac/tb_eval_ac.vhd
-- Project Name:  ac_out
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ac_out
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY tb_ac_io IS
END tb_ac_io;

ARCHITECTURE behavior OF tb_ac_io IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT ac_io
    Port (
			rst				: in  std_logic;
			clk				: in  std_logic;
			ready			: out std_logic;
			sync_strobe		: out unsigned(0 to 2);
			slot_valid		: out unsigned(0 to 12);
			stat_addr		: out unsigned (19 downto 0);
			stat_data		: out unsigned (19 downto 0);
			rx_pcm_addr		: in  unsigned (3 downto 0);
			rx_pcm_data		: out unsigned (19 downto 0);
			cmd_addr 		: in  unsigned(19 downto 0);
			cmd_data		: in  unsigned(19 downto 0);
			cmd_we			: in  std_logic;
			tx_pcm_addr		: in  unsigned(3 downto 0);
			tx_pcm_data		: in  unsigned(19 downto 0);
			tx_pcm_we		: in  std_logic;
			ac_sdata_in		: in std_logic;
			ac_bit_clk		: in  std_logic;          
			ac_reset_n		: out std_logic;
			ac_sdata_out	: out std_logic;
			ac_ssync		: out std_logic
			);
	END COMPONENT;

	constant SYS_CLK_PERIOD : time := 10 ns;
	CONSTANT BIT_CLK_PERIOD : time := 100 ns;
--	constant BIT_CLK_PERIOD : time := 81.38 ns;
	
	--Inputs
	SIGNAL rst : std_logic := '1';
	SIGNAL clk : std_logic := '0';
	SIGNAL acio_ready  : std_logic;
	SIGNAL cmd_we   :  std_logic := '0';
	SIGNAL tx_pcm_we   :  std_logic := '0';
	SIGNAL ac_bit_clk  :  std_logic := '0';
	SIGNAL cmd_addr :  unsigned(19 downto 0) := (others=>'0');
	SIGNAL cmd_data :  unsigned(19 downto 0) := (others=>'0');
	SIGNAL tx_pcm_addr :  unsigned(3 downto 0) := "0011";
	SIGNAL tx_pcm_data :  unsigned(19 downto 0) := (others=>'0');
	SIGNAL ac_sdata_in :  std_logic;
	SIGNAL rx_pcm_addr :  unsigned(3 downto 0) := "0101";

	--Outputs
	SIGNAL slot_valid :  unsigned(0 to 12);
	SIGNAL sync_strobe :  unsigned(0 to 2);
	SIGNAL ac_reset_n :  std_logic;
	SIGNAL ac_sdata_out :  std_logic;
	SIGNAL ac_ssync :  std_logic;
	SIGNAL stat_addr :  unsigned(19 downto 0);
	SIGNAL stat_data :  unsigned(19 downto 0);
	SIGNAL rx_pcm_data :  unsigned(19 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: ac_io PORT MAP(
		rst				=> rst,				
		clk				=> clk,				
		ready			=> acio_ready,				
		sync_strobe		=> sync_strobe,	
		slot_valid		=> slot_valid,	
		stat_addr		=> stat_addr,			
		stat_data		=> stat_data,			
		rx_pcm_addr		=> rx_pcm_addr,		
		rx_pcm_data		=> rx_pcm_data,		
		cmd_addr 		=> cmd_addr, 	
		cmd_data		=> cmd_data,		
		cmd_we			=> cmd_we,	
		tx_pcm_addr		=> tx_pcm_addr,		
		tx_pcm_data		=> tx_pcm_data,		
		tx_pcm_we		=> tx_pcm_we,	
		ac_sdata_in		=> ac_sdata_in,		
		ac_bit_clk		=> ac_bit_clk,		
		ac_reset_n		=> ac_reset_n,		
		ac_sdata_out	=> ac_sdata_out,	
		ac_ssync		=> ac_ssync		
	);
	
	ac_sdata_in <= ac_sdata_out;
	
	sys_clk_gen :
	PROCESS
	BEGIN
		wait for SYS_CLK_PERIOD;
		clk <= not clk;
	END PROCESS;

	bit_clk_gen : PROCESS
	begin
		if (ac_reset_n = '0') then
			ac_bit_clk <= '0';
			wait until ac_reset_n = '1';
			wait for 150 us;
		end if;	
		wait for BIT_CLK_PERIOD/2;
		ac_bit_clk <= not ac_bit_clk;
	END PROCESS;

	tb_out : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 100*SYS_CLK_PERIOD;
		rst <= '0';
		
		wait until (ac_reset_n = '1');
		
		wait until rising_edge(clk) and sync_strobe(2) = '1';
		wait for 100*SYS_CLK_PERIOD;
		cmd_data <= X"12340";
		cmd_addr <= X"8B930";

		wait until rising_edge(clk);
		cmd_we <= '1';
		wait until rising_edge(clk);
		cmd_we <= '0';

		for k in 1 to 10 loop
			tx_pcm_we <= '0';
			wait until rising_edge(clk) and sync_strobe(2) = '1';
			wait for 10*BIT_CLK_PERIOD;
			for i in 3 to 12 loop
				tx_pcm_addr <= to_unsigned(i, 4);
				tx_pcm_data <= to_unsigned(2048*k + integer(i), 20);
				tx_pcm_we <= '1';
				wait until rising_edge(clk);
			end loop;
		end loop;
		tx_pcm_we <= '0';

		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

	tb_in : PROCESS(clk, rx_pcm_addr, sync_strobe)
	BEGIN
		if rising_edge(clk) then
			if sync_strobe(1) = '1' then
				rx_pcm_addr <= "0011";
			elsif rx_pcm_addr /= "1100" then
				rx_pcm_addr <= rx_pcm_addr + 1;
			end if;	
		end if;
	END PROCESS;

END;
