
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   17:33:47 06/05/2007
-- Design Name:   eval_ac
-- Module Name:   E:/work/VHDL/eval_ac/tb_eval_ac.vhd
-- Project Name:  ac_out
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ac_out
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY tb_ac_out IS
END tb_ac_out;

ARCHITECTURE behavior OF tb_ac_out IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT ac_out
	PORT(
		rst				: IN  std_logic;
		clk				: IN  std_logic;
		sync_tx			: OUT std_logic;
		cmd_addr 		: IN  unsigned(19 downto 0);
		cmd_data		: IN  unsigned(19 downto 0);
		cmd_we			: IN  std_logic;
		pcm_in_addr		: IN  unsigned(3 downto 0);
		pcm_in_data		: IN  unsigned(19 downto 0);
		pcm_in_we		: IN  std_logic;
		ac_bit_clk		: IN  std_logic;          
		ac_reset		: in std_logic;
		ac_sdata_out	: OUT std_logic;
		ac_ssync		: OUT std_logic
		);
	END COMPONENT;

	constant SYS_CLK_PERIOD : time := 10 ns;
	constant BIT_CLK_PERIOD : time := 81.38 ns;
	
	--Inputs
	SIGNAL rst :  std_logic := '1';
	SIGNAL clk :  std_logic := '0';
	SIGNAL ce :  std_logic := '0';
	SIGNAL cmd_we :  std_logic := '0';
	SIGNAL pcm_in_we :  std_logic := '0';
	SIGNAL ac_bit_clk :  std_logic := '0';
	SIGNAL cmd_addr :  unsigned(19 downto 0) := (others=>'0');
	SIGNAL cmd_data :  unsigned(19 downto 0) := (others=>'0');
	SIGNAL pcm_in_addr :  unsigned(3 downto 0) := (others=>'0');
	SIGNAL pcm_in_data :  unsigned(19 downto 0) := (others=>'0');

	--Outputs
	SIGNAL sync_tx :  std_logic;
	SIGNAL ac_reset :  std_logic;
	SIGNAL ac_sdata_out :  std_logic;
	SIGNAL ac_ssync :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: ac_out PORT MAP(
		rst => rst,
		clk => clk,
		sync_tx => sync_tx,
		cmd_addr => cmd_addr,
		cmd_data => cmd_data,
		cmd_we => cmd_we,
		pcm_in_addr => pcm_in_addr,
		pcm_in_data => pcm_in_data,
		pcm_in_we => pcm_in_we,
		ac_reset => ac_reset,
		ac_bit_clk => ac_bit_clk,
		ac_sdata_out => ac_sdata_out,
		ac_ssync => ac_ssync
	);

	sys_clk_gen :
	PROCESS
	BEGIN
		wait for SYS_CLK_PERIOD;
		clk <= not clk;
	END PROCESS;

	bit_clk_gen :
	PROCESS
	BEGIN
		wait for BIT_CLK_PERIOD;
		ac_bit_clk <= not ac_bit_clk;
	END PROCESS;

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 100*SYS_CLK_PERIOD;
		rst <= '0';
		
		wait for 100*SYS_CLK_PERIOD;
		ac_reset <= '0';
		
		wait until rising_edge(clk) and sync_tx = '1';
		wait for 100*SYS_CLK_PERIOD;
		cmd_data <= X"aaaa0";
		cmd_addr <= X"1DFC0";

		wait until rising_edge(clk);
		cmd_we <= '1';
		wait until rising_edge(clk);
		cmd_we <= '0';

		for k in 1 to 10 loop
			pcm_in_we <= '0';
			wait until rising_edge(clk) and sync_tx = '1';
			wait for 100*SYS_CLK_PERIOD;
			for i in 3 to 12 loop
				pcm_in_addr <= to_unsigned(i, 4);
				pcm_in_data <= to_unsigned(2048*k + integer(i), 20);
				pcm_in_we <= '1';
				wait until rising_edge(clk);
			end loop;
		end loop;
		pcm_in_we <= '0';

		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

END;
