
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   17:08:52 04/08/2007
-- Design Name:   piso
-- Module Name:   tb_piso.vhd
-- Project Name:  piso_sipo
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: piso
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

ENTITY tb_sipo_vhd IS
GENERIC ( width : integer := 8);
END tb_sipo_vhd;

ARCHITECTURE behavior OF tb_sipo_vhd IS 

	-- Component Declaration for PISO
	COMPONENT piso
	GENERIC ( width : integer );
	PORT(
		rst		: in  STD_LOGIC;
		clk		: in  STD_LOGIC;
		pdi		: in  UNSIGNED (width-1 downto 0);
		pvi		: in  STD_LOGIC;
		prdyo	: out STD_LOGIC;
		sdo		: out STD_LOGIC;
		sso		: out STD_LOGIC;
		srdyi	: in  STD_LOGIC
		);
	END COMPONENT;

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT sipo
	GENERIC ( width : integer );
	PORT(
		rst		: in  STD_LOGIC;
		clk		: in  STD_LOGIC;
		srdyo	: out STD_LOGIC;
		sdi		: in  STD_LOGIC;
		ssi		: in  STD_LOGIC;
		prdyi	: in  STD_LOGIC;
		pvo		: out STD_LOGIC;
		pdo		: out UNSIGNED (width-1 downto 0)
		);
	END COMPONENT;

	CONSTANT CLK_PERIOD : time := 10 ns;
	
	--Inputs
	SIGNAL rst :  std_logic := '1';
	SIGNAL clk :  std_logic := '1';
	SIGNAL sdi :  std_logic := '0';
	SIGNAL ssi :  std_logic := '0';
	SIGNAL pvi :  std_logic := '0';
	SIGNAL srdyi :  std_logic := '1';
	SIGNAL prdyi :  std_logic := '1';
	SIGNAL pdi :  UNSIGNED(width-1 downto 0) := (others=>'0');

	--Outputs
	SIGNAL srdyo :  std_logic;
	SIGNAL prdyo :  std_logic;
	SIGNAL sdo :  std_logic;
	SIGNAL sso :  std_logic;
	SIGNAL pvo :  std_logic;
	SIGNAL pdo :  UNSIGNED(width-1 downto 0);
	SIGNAL data : integer := 0;
	SIGNAL data_out :  UNSIGNED(width-1 downto 0);
	
BEGIN

	clk_gen:
	PROCESS
	BEGIN
		wait for CLK_PERIOD/2;
		clk <= not clk;
	END PROCESS;
		
	-- Instantiate the Unit Under Test (UUT)
	inst_piso: piso 
	GENERIC MAP( width => width )
	PORT MAP(
		rst => rst,
		clk => clk,
		pdi => pdi,
		pvi => pvi,
		prdyo => prdyo,
		sdo => sdo,
		sso => sso,
		srdyi => srdyi
	);

	uut: sipo
	GENERIC MAP( width => width )
	PORT MAP(
		rst => rst,
		clk => clk,
		srdyo => srdyo,
		sdi => sdi,
		ssi => ssi,
		pvo => pvo,
		pdo => pdo,
		prdyi => prdyi
	);

	tb_prdy : process (rst, clk, pvo)
	variable count : integer := 0;
	begin
		if rst = '1' then
			prdyi <= '0';
			count := 10;
		elsif rising_edge(clk) then
			if pvo = '1' then
				prdyi <= pdi(0);
			end if;	
			if count /= 0 then
				count := count - 1;
			else
				count := 53;
				prdyi <= '1';
			end if;
		end if;	
	end process;
	
	sdi <= sdo;
	ssi <= sso;
	srdyi <= srdyo;

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 100 ns;
		rst <= '0';
		
	
		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

	tb_sig : process (rst, clk, prdyo)
	begin
		if rst = '1' then
			data <= 85;
		elsif rising_edge(clk) then
			if prdyo = '1' then
				data <= data + 1;
			end if;
		end if;	
		pdi <= to_unsigned(data, pdi'length);
		pvi <= prdyo;
	end process;
			
	tb_data : process (rst, clk, pvo)
	begin
		if rst = '1' then
			data_out <= (others => '0');
		elsif rising_edge(clk) then
			if pvo = '1' then
				data_out <= pdo;
			end if;
		end if;	
	end process;
			
END;
