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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:44:00 03/07/2007 
-- Design Name: 
-- Module Name:    jtag_test - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity jtag_test is
    Port (
		sys_rstn_in	: in  STD_LOGIC;	
        sys_led     : out unsigned(8 downto 0)
	);
end jtag_test;

architecture Behavioral of jtag_test is

	signal rst, bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
	signal user_regi, user_rego : unsigned (7 downto 0);
	constant id : unsigned (7 downto 0) := "11010101";
begin

   BSCAN_VIRTEX4_inst : BSCAN_VIRTEX4 
   generic map (
      JTAG_CHAIN => 2) -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
   port map (
      CAPTURE => bs_capture, -- CAPTURE output from TAP controller
      DRCK => bs_clk0,       -- Data register output for USER functions
      RESET => bs_rst,       -- Reset output from TAP controller
      SEL => bs_sel,         -- USER active output
      SHIFT => bs_shift,     -- SHIFT output from TAP controller
      TDI => bs_tdi,        -- TDI output from TAP controller
      UPDATE => bs_update0,   -- UPDATE output from TAP controller
      TDO => bs_tdo         -- Data input for USER function
   );

   i00_BUFG : BUFG
	port map (
		O => bs_clk1,
        I => bs_clk0
	);
   i01_BUFG : BUFG
	port map (
		O => bs_update1,
        I => bs_update0
	);

	rst <= not sys_rstn_in;

led_out:
	process (rst, bs_clk1, bs_update1, user_regi)
	begin
		if rst = '1' then
			sys_led(7 downto 0) <= (others => '0');
		elsif rising_edge(bs_update1) then
			if bs_sel = '1' then
				sys_led(7 downto 0) <= user_regi;
			end if;
		end if;
	end process;	

cled_out:
	process (rst, bs_clk1, bs_update1, user_regi)
	begin
		if rst = '1' then
			sys_led(8) <= '0';
		elsif rising_edge(bs_update1) then
			sys_led(8) <= bs_sel; 
		end if;
	end process;	
	
sipo:
	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
	begin
		if bs_rst = '1' then
			user_regi <= (others => '0');
		elsif rising_edge(bs_clk1) then
			if bs_shift = '1' then
				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
			end if;
		end if;
	end process;	

piso:
	process (rst, bs_clk1, bs_shift, user_rego)
	begin
		bs_tdo <= user_rego(0);
		if rst = '1' then
			user_rego <= (others => '0');
		elsif rising_edge(bs_clk1) then
			if bs_shift = '1' then
				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
			else
				user_rego <= id;	
			end if;
		end if;
	end process;	

	
end Behavioral;

