--------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: The arithmetic logic unit
--
-- Copyright (C) 2008 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

use work.mips_types.all;

entity bcu is
	Generic 
	(
		data_width : integer := 8
	);
	Port 
	(
		op1_in		: in  unsigned (data_width-1 downto 0);
		op2_in		: in  unsigned (data_width-1 downto 0);
		flags		: out bcu_flags_t
	);
end bcu;

architecture Behavioral of bcu is

--------------------------------------------------------------------------
begin

	flags.eq	<= '1' when op1_in = op2_in else '0';
	flags.ltz	<= op1_in(op1_in'left);

--------------------------------------------------------------------------
end Behavioral;
