-------------------------------------------------------------------------
-- Project: SDRAM controller
-- This file: User SDRAM component adjustments
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------

library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

use work.sdram_const.all;

package sdram_config is

	constant DATA_RATE_FACTOR		: positive := 2;	-- DDR => twice part data width
	constant PART_DATA_WIDTH 		: positive := 32;  -- External DDR-SDRAM Module data bus width
	constant PART_ADDR_WIDTH 		: positive := 13;  -- number of address lines to DDR-SDRAM Device/Module
	constant PART_BANK_WIDTH 		: positive := 2;   -- Number of BANK address lines of external DDR-SDRAM
	constant PART_ROW_ADDR_WIDTH	: positive := 13;  -- 
	constant PART_COL_ADDR_WIDTH	: positive := 9;  -- 
	
	constant PART_DQS_WIDTH  		: positive := PART_DATA_WIDTH / 8; -- Number of data strobe lines
	constant PART_DM_WIDTH   		: positive := PART_DATA_WIDTH / 8; -- Number of Data Mask Lines
	constant BUS_DATA_WIDTH 		: positive := 2*PART_DATA_WIDTH;  -- DDR => twice part data width
	constant BUS_DM_WIDTH			: positive := 2*PART_DM_WIDTH;    -- DDR => twice part data width

	-- DDR SDRAM Hardware defined constants
	constant BIT_AUTO_PRE		: positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
	constant BIT_PRE_ALL		: positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
	constant ENABLE_PRE_ALL		: std_logic := '1';
	constant ENABLE_AUTO_PRE	: std_logic := '0';
	constant LMR_BL_CURR		: natural := LMR_BL2;
	
	-- DDR-SDR TIMING constants ------------------------------------------------------------------
	-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh 
	constant REFRESH_INTERVAL	: real := 7.8125E3; -- [ns]

	-- These values are for your SDRAM part (see datasheet) 
	constant TCAS : positive	:= 2;   		-- CAS latency [clocks]
	constant TRP  : real		:= 20.0;		-- precharge command period [ns]
	constant TRAS : real		:= 45.0;		-- active to precharge delay [ns]
	constant TRFC : real		:= 75.0;		-- auto refresh command period [ns]
	constant TMRD : positive	:= 2;			-- load mode register command cylce time [clocks]
	constant TRCD : real		:= 20.0;		-- active to read or write delay [ns]
	constant TWR  : real		:= 15.0;		-- write recovery time [ns]

	constant PWR_UP_WAIT		: real := 22.0E3; -- [ns]

	subtype user_tag_t is unsigned(3 downto 0);

	----------------------------------------------------------------------------------------------
	
end sdram_config;
