-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: cpu_embedded using cpu_core and rom
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

use work.fifo_ctrl_pkg.all;
use work.sdram_config.all;
use work.sdram_types.all;

entity ctrl_ddr_wb32 is
	Generic
	(
		F_SYSCLK		: real		:= 100.0;
		F_SDRCLK	 	: real		:= 100.0;
		FIFO_DEPTH		: integer	:= 4;
		TPD_BOARD_SIM	: time		:= 0 ns
	);
	Port
	(
		RST_I				: in  STD_LOGIC;
		CLK_I				: in  STD_LOGIC;
		SDRAM_CLK_I			: in  STD_LOGIC;
		SDRAM_CLK_FB_I		: in  STD_LOGIC;
		
		CYC_I				: in  STD_LOGIC;
		STB_I				: in  STD_LOGIC;
		SEL_I				: in  unsigned(3 downto 0);
		WE_I				: in  STD_LOGIC;
		ACK_O				: out STD_LOGIC;
		MRDY_I				: in  STD_LOGIC;
		SRDY_O				: out STD_LOGIC;
		ADDR_I				: in  unsigned(31 downto 0);
		DAT_I				: in  unsigned(31 downto 0);
		DAT_O				: out unsigned(31 downto 0);

		-- SDRAM signals
		sd_clk_p			: out  STD_LOGIC;
		sd_clk_n			: out  STD_LOGIC;
		sd_cke				: out  STD_LOGIC;
		sd_cs_n				: out  STD_LOGIC;
		sd_cas_n			: out  STD_LOGIC;
		sd_ras_n			: out  STD_LOGIC;
		sd_we_n				: out  STD_LOGIC;
		sd_addr				: out  sdr_addr_t;
		sd_ba				: out  sdr_ba_t;
		sd_dm				: out unsigned(PART_DM_WIDTH-1 downto 0);
		sd_dqs				: inout unsigned(PART_DQS_WIDTH-1 downto 0);
		sd_data				: inout unsigned(PART_DATA_WIDTH-1 downto 0)
		
	);
end ctrl_ddr_wb32;

architecture struct of ctrl_ddr_wb32 is

	signal sdram_clk0		: std_logic;
	signal sdram_rst0		: std_logic;

	signal phy_ctrl			: phy_ctrl_t;	
	signal phy_in			: phy_in_t;	
	signal phy_out			: phy_out_t;	
begin

	-- DDR SDRAM Controller Core
	sdram_ctrl_frontend_wb32 : entity work.sdram_ctrl_frontend_wb32
	GENERIC MAP
	(
		F_SYSCLK	 	=> F_SYSCLK,
		F_SDRCLK	 	=> F_SDRCLK,
		FIFO_DEPTH		=> FIFO_DEPTH
	)
	PORT MAP
	(
		RST_I				=> RST_I,
		CLK_I				=> CLK_I,
		SDRAM_RST0			=> sdram_rst0,
		SDRAM_CLK0			=> sdram_clk0,
		
		CYC_I				=> CYC_I,
		STB_I				=> STB_I,
		SEL_I				=> SEL_I,
		WE_I				=> WE_I,
		ACK_O				=> ACK_O,
		SRDY_O				=> SRDY_O,
		MRDY_I				=> MRDY_I,
		ADDR_I				=> ADDR_I,
		DAT_I				=> DAT_I,
		DAT_O				=> DAT_O,

		-- PHY signals
		phy_in				=> phy_in,
		phy_out				=> phy_out,
		phy_ctrl			=> phy_ctrl
	
	);

	-- DDR phy
	inst_sdram_phy : entity work.sdram_phy
	Generic map
	(
		F_SDRCLK		=> F_SDRCLK,
		TPD_BOARD_SIM	=> TPD_BOARD_SIM
	)
	Port map
	(
		-- Clock interface
		rst				=> RST_I,
		clk				=> SDRAM_CLK_I,
		clk_fb			=> SDRAM_CLK_FB_I,
		clk0_out		=> sdram_clk0,
		rst0_out		=> sdram_rst0,
		
		-- PHY interface
		phy_in			=> phy_in,
		phy_out			=> phy_out,
		phy_ctrl		=> phy_ctrl,
		
		-- SDRAM part interface
		part_clk_p		=> sd_clk_p,
		part_clk_n		=> sd_clk_n,
		part_addr		=> sd_addr,
		part_ba			=> sd_ba,
		part_dm			=> sd_dm,
		part_dqs		=> sd_dqs,
		part_data		=> sd_data,
		part_cs_n		=> sd_cs_n,
		part_we_n		=> sd_we_n,
		part_cas_n		=> sd_cas_n,
		part_ras_n		=> sd_ras_n,
		part_cke		=> sd_cke
	);

end architecture struct;
