-- UART Transmitter with integral 16 byte FIFO buffer
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
--
------------------------------------------------------------------------------------
--
-- Main Entity for UART_TX
--
entity uart_tx is
	Generic 
	(
		fifo_depth_bits	: integer := 4
	);
    Port
	(
		rst				: in std_logic;
		clk				: in std_logic;
		we				: in std_logic;
		din				: in unsigned(7 downto 0);
		full			: out std_logic;
		half_full		: out std_logic;
		ser_out			: out std_logic;
		tx_complete		: out std_logic;
		tx_empty		: out std_logic;
		en_16_x_baud	: in std_logic
	);
end uart_tx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for UART_TX
--	 
architecture rtl of uart_tx is
--
------------------------------------------------------------------------------------
--
-- Components used in UART_TX and defined in subsequent entities.
--	
------------------------------------------------------------------------------------
--
-- Constant (K) Compact UART Transmitter
--
component juart_tx 
	Port
	(
		rst				: in std_logic;
		clk				: in std_logic;
		din				: in unsigned(7 downto 0);
		we				: in std_logic;
		en_16_x_baud	: in std_logic;
		ser_out			: out std_logic;
		Tx_complete		: out std_logic
	);
end component;
--
-- 'Bucket Brigade' FIFO 
--
component bbfifo 
	Generic 
	(
		depth_bits	: integer := 4;
		data_width	: integer := 8
	);
    Port
	( 
		rst			: in std_logic;
		clk			: in std_logic;
		we			: in std_logic;
		din			: in unsigned(7 downto 0);
		full		: out std_logic;
		half_full	: out std_logic;
		re			: in std_logic;
		dout		: out unsigned(7 downto 0);
		dout_vld	: out std_logic
	);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used in UART_TX
--
------------------------------------------------------------------------------------
--
signal fifo_data_out		: unsigned(7 downto 0);
signal fifo_data_present	: std_logic;
signal fifo_read			: std_logic;
--
------------------------------------------------------------------------------------
--
-- Start of UART_TX circuit description
--
------------------------------------------------------------------------------------
--	
begin

  tx_complete	<= fifo_read;
  tx_empty		<= not fifo_data_present;
  
juart: juart_tx
port map
(
	rst				=> rst,
	clk				=> clk,
	din				=> fifo_data_out,
	we				=> fifo_data_present,
	en_16_x_baud	=> en_16_x_baud,
	ser_out			=> ser_out,
	Tx_complete		=> fifo_read
);


buf: bbfifo 
GENERIC MAP 
(
	depth_bits	=> fifo_depth_bits,
	data_width	=> 8
)
port map
(
	clk			=> clk,
	rst			=> rst,
	din			=> din,
	dout		=> fifo_data_out,
	we			=> we,
	re			=> fifo_read,
	full		=> full,
	half_full	=> half_full,
	dout_vld	=> fifo_data_present
);

end rtl;

------------------------------------------------------------------------------------
--
-- END OF FILE UART_TX.VHD
--
------------------------------------------------------------------------------------

