--------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: On-chip RAM
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

use work.cpu_pkg.all;

entity chipram is
	Generic (
		addr_width : integer := 3;
		data_width : integer := 8
	);
	Port (
		clka		: in  STD_LOGIC;
		clkb		: in  STD_LOGIC;
		en_a		: in  STD_LOGIC;
		en_b		: in  STD_LOGIC;
		we_a		: in  STD_LOGIC;
		we_b		: in  STD_LOGIC;
		addr_a		: in  unsigned (addr_width-1 downto 0);
		addr_b		: in  unsigned (addr_width-1 downto 0);
		din_a		: in  unsigned (data_width-1 downto 0);
		din_b		: in  unsigned (data_width-1 downto 0);
		dout_a		: out unsigned (data_width-1 downto 0);
		dout_b		: out unsigned (data_width-1 downto 0)
	);
end chipram;

architecture Behavioral of chipram is

	constant depth : integer := 2**addr_width;
	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
	shared variable RAM : RAMtype;
	
begin

process (clka)
begin
if clka'event and clka = '1' then
	if en_a = '1' then
		if we_a = '1' then
			RAM(to_integer(addr_a)) := din_a;
		end if;
		dout_a <= RAM(to_integer(addr_a));
	end if;
end if;
end process;

process (clkb)
begin
if clkb'event and clkb = '1' then
	if en_b = '1' then
		if we_b = '1' then
			RAM(to_integer(addr_b)) := din_b;
		end if;
		dout_b <= RAM(to_integer(addr_b));
	end if;
end if;
end process;


end Behavioral;

