-- ============================================================================
--
-- Design unit      :   tech_iface
--
-- File Name        :   tech_iface_virtex2.vhd
--
-- Purpose          :   The package collects type declarations for all non-
--                      trivial interfaces of used entities. Record types
--                      are used extensively to group related signals (e.g.
--                      data / control & status, physical attachment etc.).
--
--
-- Depends on       :
--
--  - Package(s)    :   aes_definitions
--
--  - Module(s)     :   -
--
--
-- Dev. Platform    :   Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
--
--  - Simulator(s)  :   Modelsim XE III 6.0d
--
--  - Synthesis     :   Xilinx XST
--
--  - Place & Route :   Xilinx PAR
--
--
-- Errors           :   None known
--
--
-- Limitations      :   None known
--
--
-- Notes            :   -
--
--
-- Author(s)        :   A. Freund (af) <a.freund@dsi-it.de>
--                      Digitale Signalverabeitung & Informationstechnik GmbH,
--                      Bremen, Germany
--
--
-- ============================================================================
--
-- Revision List:
-- Version      Author(s)       Date        Changes
--
-- v0.00        af              2006-11-15  initial version
--
-- see SVN logs
--
-- ============================================================================
--
-- Naming conventions:
--
--  - coding style: record-signals for related purposes (Gaisler-style)
--  - active-low signals are indicated by appending "_n"
--  - constants are in UPPERCASE
--  - name parts are separated by "_"
--
-- ============================================================================


library ieee;
use ieee.std_logic_1164.all;


use work.aes_definitions.all;


package tech_iface is


	-- architecture-dependent key-id size (matching Virtex-II BlockRAM size)
	subtype key_id_t is std_logic_vector(2 downto 0);


	-- number of 32-bit slice within subkey
	subtype part_no_t is std_logic_vector(1 downto 0);

	-- 32-bit slice of 128-bit data block
	subtype part_data_t is std_logic_vector(31 downto 0);

	-- 32-bit slice of 128-bit subkey
	subtype part_subkey_t is std_logic_vector(31 downto 0);


--
-- S-box stage interface definition (32-bit version, 2x7-bit + 2x9-bit, mapping as required by KS-128)
--


	-- s-box stage input signals
	type sbox_stage_in_type is record
		act		:	std_logic;			-- read-enable control (to suppress simulation warnings)
		din		:	part_data_t;		-- S-box input data
		ed_mode	:	std_logic;			-- encryption (0) / decryption (1) mode
	end record;


	-- s-box stage load input signals
	type sbox_stage_load_in_type is record
		act		:	std_logic;			-- activate load I/F
		ed_mode	:	std_logic;			-- encryption (0) / decryption (1) mode
		pos		:	aes_sbox_8_t;		-- position
		din		:	aes_sbox_8_t;		-- new value
		wen		:	std_logic;			-- write enable
		done	:	std_logic;			-- S-box loading done
	end record;


	-- s-box stage outputs signals
	type sbox_stage_out_type is record
		dout	:	part_data_t;		-- S-box output data
		ready	:	std_logic;			-- S-box stage is ready
	end record;


--
-- subkey memory interface definition (32-bit version)
--


	-- key-schedule - side input signals
	type subkey_memory_ks_in_type is record
		write_en	:	std_logic;			-- write enable
		key_id		:	key_id_t;			-- key id to use
		subkey_no	:	aes_round_no_t;	-- subkey number
		part_no		:	part_no_t;			-- 32-bit slice number
		subkey		:	part_subkey_t;		-- subkey
		rounds		:	aes_round_no_t;	-- number of rounds
	end record;


	-- key-schedule - side output signals
	type subkey_memory_ks_out_type is record
		dummy	:	std_logic;
	end record;


	-- encryption/decryption - side input signals
	type subkey_memory_ed_in_type is record
		rd_en		:	std_logic;			-- read-enable control (to suppress simulation warnings)
		subkey_no	:	aes_round_no_t;	-- subkey number
		part_no		:	part_no_t;			-- 32-bit slice number
		key_id		:	key_id_t;			-- key id to use
	end record;


	-- encryption/decryption - side output signals
	type subkey_memory_ed_out_type is record
		subkey		:	part_subkey_t;		-- subkey
		rounds		:	aes_round_no_t;	-- number of rounds
	end record;


--
--
-- Component declarations
--
--


	-- S-Box stage
	component tech_sbox_stage is
		port (
			rst		: 	in	std_logic;						-- reset
			clk		:	in	std_logic;						-- clock
			data_i	:	in	sbox_stage_in_type;				-- see package tech_iface
			data_o	:	out	sbox_stage_out_type;			-- see package tech_iface
			load_i	:	in	sbox_stage_load_in_type			-- see package tech_iface
		);
	end component;


	-- subkey memory
	component tech_subkey_memory is
		port (
			clk			:	in	std_logic;					-- clock
			key_sched_i	:	in	subkey_memory_ks_in_type;	-- see package tech_iface
			enc_dec_i	:	in	subkey_memory_ed_in_type;	-- see package tech_iface
			enc_dec_o	:	out	subkey_memory_ed_out_type	-- see package tech_iface
		);
	end component;


	-- S-box loader (mainly for simulation)
	component sbox_loader is
		port (
			rst		: 	in	std_logic;					-- reset
			clk		:	in	std_logic;					-- clock
			load_o	:	out	sbox_stage_load_in_type		-- see package tech_iface
		);
	end component;


end tech_iface;
