
entity dpram_1w1r2c_ra is
	Generic (
		addr_width : integer := 3;
		data_width : integer := 8
	);
	Port (
		clk_a		: in  STD_LOGIC;
		clk_b		: in  STD_LOGIC;
		en_a		: in  STD_LOGIC;
		en_b		: in  STD_LOGIC;
		we_a		: in  STD_LOGIC;
		addr_a		: in  unsigned (addr_width-1 downto 0);
		addr_b		: in  unsigned (addr_width-1 downto 0);
		din_a		: in  unsigned (data_width-1 downto 0);
		dout_b		: out unsigned (data_width-1 downto 0)
	);
end dpram_1w1r2c_ra;





-------------------------------------------
-- to_component
-------------------------------------------
-- case insensitive
-- regexp
-- text

GENERIC
GENERIC

PORT
PORT

^ENTITY
COMPONENT

 +IS
{empty}


^.*END.*
END COMPONENT;

-------------------------------------------
-- to_portmap
-------------------------------------------
-- case insensitive
-- regexp
-- text

GENERIC
GENERIC MAP

PORT
PORT MAP

: +.*;
=>,

: +.*
=>

\(\<.*[^ \t]*.*\>\)[ \t,]*=>
\1\t=>\t\1

^ENTITY[ \t]+\([^ ].*[^ ]\) .*IS
inst_\1: \1

^END +.*$
{empty}
