-- ============================================================================
--
-- Design unit      :   ecb_mode_encryption (ECB-mode encryption)
--
-- File Name        :   ecb_mode_encryption.vhd
--
-- Purpose          :   The module provides ECB-mode encryption (there is no
--                      internal logic, it's just a placeholder to hold up with
--                      common infrastructure used for more complex modes)
--
--
-- Depends on       :
--
--  - Package(s)    :   engine_iface, ecb_mode_iface
--
--  - Module(s)     :   -
--
--
-- Dev. Platform    :   Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
--
--  - Simulator(s)  :   Modelsim XE III 6.0d
--
--  - Synthesis     :   Xilinx XST
--
--  - Place & Route :   Xilinx PAR
--
--
-- Errors           :   None known
--
--
-- Limitations      :   None known
--
--
-- Notes            :   Version for implementation using 32-bit datapath
--
--
-- Author(s)        :   A. Freund (af) <a.freund@dsi-it.de>
--                      Digitale Signalverabeitung & Informationstechnik GmbH,
--                      Bremen, Germany
--
--
-- ============================================================================
--
-- Revision List:
-- Version      Author(s)       Date        Changes
--
-- v0.00        af              2006-11-02  initial version
--
-- see SVN logs
--
-- ============================================================================
--
-- Naming conventions:
--
--  - coding style: two-process method (Gaisler-style)
--  - active-low signals are indicated by appending "_n"
--  - constants are in UPPERCASE
--  - name parts are separated by "_"
--
-- ============================================================================


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


use work.engine_iface.all;
use work.ecb_mode_iface.all;


entity ecb_mode_encryption is
	port (
		rst		: 	in	std_logic;						-- reset
		clk		:	in	std_logic;						-- clock
		mode_i	:	in	ecb_mode_encryption_in_type;	-- see package ecb_mode_iface
		mode_o	:	out	ecb_mode_encryption_out_type;	-- see package ecb_mode_iface
		enc_i	:	in	encryption_engine_out_type;		-- see package engine_iface
		enc_o	:	out	encryption_engine_in_type		-- see package engine_iface
	);
end ecb_mode_encryption;


architecture behavioural of ecb_mode_encryption is


	type registers is record
		dummy		:	std_logic;
	end record;


	type variables is record
		dummy		:	std_logic;
	end record;


	signal	r, rin : registers;


begin


	-- combinatorial logic
	comb: process (rst, r, mode_i, enc_i)
		variable v : registers;
		variable t : variables;
	begin

		-- assign default values
		v := r;
--
--
--



--
--
--
		-- reset handling
		if (rst = '1')
			then
		end if;
--
--
--
		-- update registers
		rin <= v;
--
--
--
		-- drive outputs
		enc_o.start		<=	mode_i.start;
		enc_o.plain		<=	mode_i.plain;
		enc_o.key_id	<=	mode_i.key_id;

		mode_o.valid	<=	enc_i.valid;
		mode_o.busy		<=	enc_i.busy;
		mode_o.cipher	<=	enc_i.cipher;


	end process;


	-- registers
	regs: process (clk, rst)
	begin
		if rising_edge(clk)
			then
				r <= rin;
		end if;

		-- async. reset
		if (rst = '1')
			then
		end if;
	end process;


end behavioural;
