-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------

LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;

library work;
use work.cpu_pkg.all;

-- JASM_ROM_INSERT_HERE
ENTITY irom IS
	Port (
	clk			: in  STD_LOGIC;
	ce			: in  STD_LOGIC;
	addr		: in  inst_addr_t;
	dout		: out inst_t
	);
END irom;

ARCHITECTURE dctest OF irom IS 

	type imem_rom_t is array (0 to 17) of inst_t;

	-- Assembled from dctest.jsm
	constant imem_rom : imem_rom_t :=
	(
		"110000" & X"010", -- 0x000: JMP 0x010
		"110000" & X"011", -- 0x001: JMP 0x011
		"000000" & X"000", -- 0x002:
		"000000" & X"000", -- 0x003:
		"000000" & X"000", -- 0x004:
		"000000" & X"000", -- 0x005:
		"000000" & X"000", -- 0x006:
		"000000" & X"000", -- 0x007:
		"000000" & X"000", -- 0x008:
		"000000" & X"000", -- 0x009:
		"000000" & X"000", -- 0x00A:
		"000000" & X"000", -- 0x00B:
		"000000" & X"000", -- 0x00C:
		"000000" & X"000", -- 0x00D:
		"000000" & X"000", -- 0x00E:
		"000000" & X"000", -- 0x00F:
		"110000" & X"010", -- 0x010: JMP 0x010
		"111111" & X"000"  -- 0x011: RETI
	);

begin

PROM_READ:
	process(clk, ce)
	begin
		if rising_edge(clk) and ce = '1' then
			dout <= imem_rom(to_integer(addr));
		end if;
	end process;

end dctest;

