-------------------------------------------------------------------------
-- Project: SDRAM controller
-- This file: Type definitions
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------

library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.MATH_REAL.ALL;

use work.sdram_const.all;
use work.sdram_config.all;

package sdram_types is

	-----------------------------------------------------------------------------------------
	-- Table of Timing Parameters as a function of operation

	-- Derived constants from sdram_config

	type sdr_state_t is (PWR_DOWN, PRECHARGE, MODE, IDLE_WAIT, IDLE, ROW_ACT, WRITE, WRITE_A, READ, READ_A, BURST_STOP, SELF_REF, AUTO_REF, PRE_PWR_DOWN, ACT_PWR_DOWN);
	subtype user_addr_t is unsigned(PART_BANK_WIDTH+PART_ROW_ADDR_WIDTH+PART_COL_ADDR_WIDTH-1 downto 0);
	subtype sdr_addr_t is unsigned(PART_ADDR_WIDTH-1 downto 0);
	subtype sdr_ba_t is unsigned(PART_BANK_WIDTH-1 downto 0);
	subtype mode_word_t is unsigned(PART_ADDR_WIDTH+PART_BANK_WIDTH-1 downto 0);

	subtype bank_addr_t is unsigned(PART_BANK_WIDTH-1 downto 0);
	subtype row_addr_t is unsigned(PART_ADDR_WIDTH-1 downto 0);
	subtype col_addr_t is unsigned(8 downto 0);
	
	type sdr_cmd_lines_t is
	record
         cs_n    : std_logic;
         ras_n   : std_logic;
         cas_n   : std_logic;
         we_n    : std_logic;
	end record sdr_cmd_lines_t;

	type part_ctrl_t is
	record
		cmd		: sdr_cmd_lines_t;
		ba	 	: unsigned(PART_BANK_WIDTH-1 downto 0);
		addr	: unsigned(PART_ADDR_WIDTH-1 downto 0);
		cke		: std_logic;
	end record part_ctrl_t;
	
	type phy_ctrl_t is
	record
		re				: std_logic;
		we				: std_logic;
		utag_we			: std_logic;
		part			: part_ctrl_t;
		u_tag			: user_tag_t;
	end record phy_ctrl_t;

	type phy_in_t is
	record
		wr_dm			: unsigned(BUS_DM_WIDTH-1 downto 0);
		wr_data			: unsigned(BUS_DATA_WIDTH-1 downto 0);
	end record phy_in_t;

	type phy_out_t is
	record
		rd_data			: unsigned(BUS_DATA_WIDTH-1 downto 0);
		rd_data_we		: STD_LOGIC;
		wr_data_re		: STD_LOGIC;
		tag_rd			: user_tag_t;
		tag_wr			: user_tag_t;
	end record phy_out_t;

	type part_cmd_array_t is array (sdr_cmd_t) of sdr_cmd_lines_t;
	constant COMMAND : part_cmd_array_t :=
	--	 command                 cs_n     ras_qn      cas_qn      we_qn
	(	SD_DESELECT         =>   (   '1',      '1',        '1',        '1'),
		SD_NOP              =>   (   '0',      '1',        '1',        '1'),
		SD_LMR              =>   (   '0',      '0',        '0',        '0'),
		SD_ACT              =>   (   '0',      '0',        '1',        '1'),
		SD_READ             =>   (   '0',      '1',        '0',        '1'),
		SD_WRITE            =>   (   '0',      '1',        '0',        '0'),
		SD_PRE              =>   (   '0',      '0',        '1',        '0'),
		SD_BST              =>   (   '0',      '1',        '1',        '0'),
		SD_AR               =>   (   '0',      '0',        '0',        '1'),
		SD_SR               =>   (   '0',      '0',        '0',        '1')
	);

	type init_seq_t is 
	record
		cmd			: sdr_cmd_t;
		mode_word	: mode_word_t;
		wait_cycle	: natural;
	end record init_seq_t;	
	
	function to_cycles(T_ns : real; f_Mhz : real) return natural;
	
end sdram_types;

package body sdram_types is

	function to_cycles(T_ns : real; f_Mhz : real) return natural is
	begin
		
		return natural(ceil(1.0E-3*T_ns*f_Mhz));

	end to_cycles;	

end sdram_types;
