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Date (DD/MM/YYYY)  - 16.11.2009

Model name         - S25FL256S

Vendor             - Spansion (www.spansion.com)

Publication ID     - S25FL128 256 512 01GS MRS Rev0 98

VITAL model author -  Vesna Mancev
                      v-mancev@hdl-dh.com
                      Ranko Prokopovic
                      r-prokopovic@hdl-dh.com
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INITIAL RELEASE

# Release Label             => vital-amd-serial-s25fl-REL-s25fl512s-2009-11-16-1.tar.gz
# Release Date (DD/MM/YYYY) => 16/11/2009
# Release Version           => 1.0

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VITAL model author -  Vesna Mancev
                      v-mancev@hdl-dh.com
                      Ranko Prokopovic
                      r-prokopovic@hdl-dh.com
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# Release Label             => vital-amd-serial-s25fl-REL-s25fl512s-2009-11-19-2.tar.gz
# Release Date (DD/MM/YYYY) => 19/11/2009
# Release Version           => 1.1

# Corrections:
#	1.Negative tests which show how model behaves when reset pulse
#         width is less than specified and when write and erase operations are interrupted .
#         with reset signal are interrupted with reset signal are added.
#       2.Implementation of Continuous Read Mode
#       3.After 8 clock cycles for instruction, first address bit is latched on the next
#         rising edge of clock.

# Files modified
-s25fl512s.vhd
-testbench_s25fl512s_vhdl.vhd
-spansion_tc_pkg.vhd
-s25fl512s.ftm
-s25fl512s_vhdl.sdf
-s25fl512s.v
-testbench_s25fl512s_verilog.vhd
-s25fl512s.ftmv
-s25fl512s_verilog.sdf
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VITAL model author -  Vesna Mancev
                      v-mancev@hdl-dh.com
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# Release Label             => vital-amd-serial-s25fl-REL-s25fl512s-2010-03-04-1.tar.gz
# Release Date (DD/MM/YYYY) => 04/03/2010
# Release Version           => 1.2

# Corrections:
#	1.Array variable WByte in sensitivity list is replaced with signal WB_flag to enable
#         compilation in NCSim
#       2.addr_cnt for second read in high performance read continuous mode can change its
#         value only when CSNeg = '0'

# Files modified
-s25fl512s.v
-s25fl512s.vhd
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VITAL model author -  Vesna Mancev
                      v-mancev@hdl-dh.com
##########################################
# Release Label             => vital-amd-serial-s25fl-REL-s25fl512s-2010-04-15-1.tar.gz
# Release Date (DD/MM/YYYY) => 15/04/2010
# Release Version           => 1.3

# Corrections:
#	1.HOLD mode corrected
#       2.Condition for PP operation corrected

# Files modified
-s25fl512s.v
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VITAL model author -  Vesna Mancev
                      v-mancev@hdl-dh.com
##########################################
# Release Label             => vital-amd-serial-s25fl-REL-s25fl512s-2010-05-21-1.tar.gz
# Release Date (DD/MM/YYYY) => 21/05/2010
# Release Version           => 1.4

# Corrections:
#       1.SRWD bit assignment is corrected
#       2.Condition for WRR command in write_cycle_decode section is corrected
#       3.Blocking assignments for signals WSTART and PSTART are replaced with
#         nonblocking assignments
#       4.Conditions in Page Program section are fixed
#

# Files modified
-s25fl512s.v
-s25fl512s.vhd
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VITAL model author -  Vesna Mancev
                      v-mancev@hdl-dh.com
##########################################
# Release Label             => vital-amd-serial-s25fl-REL-s25fl512s-2010-05-25-1.tar.gz
# Release Date (DD/MM/YYYY) => 25/05/2010
# Release Version           => 1.5

# Corrections:
#       1. Timing control sections for Program and Erase operation are changed
#       2. Conditions in Page Program section are fixed
#

# Files modified
-s25fl512s.v
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VITAL model author -  Vesna Mancev
                      v-mancev@hdl-dh.com
##########################################
# Release Label             => vital-amd-serial-s25fl-REL-s25fl512s-2010-06-03-2.tar.gz
# Release Date (DD/MM/YYYY) => 03/06/2010
# Release Version           => 1.6

# Corrections:
#       1. bus_cycle_state section for PGSP command is fixed
#

# Files modified
-s25fl512s.v
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VITAL model author -  Vesna Mancev
                      v-mancev@hdl-dh.com
##########################################
# Release Label             => vital-amd-serial-s25fl-REL-s25fl512s-2010-07-28-1.tar.gz
# Release Date (DD/MM/YYYY) => 28/07/2010
# Release Version           => 1.7

# Corrections:
#       1. During the QUAD mode HOLD# input is not monitored for its normal function
#       2. Internal pull-up resistors for HOLD# and WP# inputs are implemented

# Files modified
-s25fl512s.v
-s25fl512s.vhd
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# Release Label             => vital-amd-serial-s25fl-REL-s25fl512s-2010-08-24-1.tar.gz
# Release Date (DD/MM/YYYY) => 24/08/2010
# Release Version           => 1.8

# Corrections:
#       1. All redundant signals are removed from BusCycle process

# Files modified
-s25fl512s.v
-s25fl512s.vhd
##########################################
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VITAL model author -  Vesna Mancev
                      v-mancev@hdl-dh.com
                      Branislav Colakovic
                      b-colakovic@hdl-dh.com
##########################################
# Release Label             => vital-amd-serial-s25fl-REL-s25fl512s-2010-10-14-1.tar.gz
# Release Date (DD/MM/YYYY) => 14/10/2010
# Release Version           => 1.9

# Corrections:
#       1. Latest datasheet aligned (VERILOG files only)

# Files modified
-spansion_tc_pkg.vhd
-s25fl512s.v
-testbench_s25fl512s_verilog.vhd
-s25fl512s.ftmv
-s25fl512s_verilog.sdf
##########################################
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VITAL model author -  Vesna Mancev
                      v-mancev@hdl-dh.com
                      Branislav Colakovic
                      b-colakovic@hdl-dh.com
##########################################
# Release Label             => vital-amd-serial-s25fl-REL-s25fl512s-2010-10-20-1.tar.gz
# Release Date (DD/MM/YYYY) => 20/10/2010
# Release Version           => 2.0

# Corrections:
#       1. Latest datasheet aligned (VHDL files added)

# Files modified
-s25fl512s.vhd
-testbench_s25fl512s_vhdl.vhd
-s25fl512s.ftm
-s25fl512s_vhdl.sdf
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# Release Label             => vital-amd-serial-s25fl-REL-s25fl512s-2010-10-22-2.tar.gz
# Release Date (DD/MM/YYYY) => 22/10/2010
# Release Version           => 2.1

# Corrections:
#       1. Latest datasheet aligned (VHDL files added)

# Files modified
-s25fl512s.vhd
-testbench_s25fl512s_vhdl.vhd
-s25fl512s.ftm
-s25fl512s_verilog.sdf
-s25fl512s.v
-s25fl512s.sv
-testbench_s25fl512s_verilog.vhd
-s25fl512s.ftmv
-s25fl512s_vhdl.sdf
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# Release Label             => vital-amd-serial-s25fl-REL-s25fl512s-2010-11-05-1.tar.gz
# Release Date (DD/MM/YYYY) => 05/11/2010
# Release Version           => 2.2

# Corrections:
#       1. Latest datasheet aligned

# Files modified
-spansion_tc_pkg.vhd
-s25fl512s.vhd
-testbench_s25fl512s_vhdl.vhd
-s25fl512s.v
-s25fl512s.sv
-testbench_s25fl512s_verilog.vhd
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VITAL model author -  Vesna Mancev
                      v-mancev@hdl-dh.com
                      Ranko Prokopovic
                      r-prokopovic@hdl-dh.com
                      Hana Dimitrijevic
                      h-dimitrijevic@hdl-dh.com
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# Release Label             => vital-amd-serial-s25fl-REL-s25fl512s-2010-11-15-1.tar.gz
# Release Date (DD/MM/YYYY) => 15/11/2010
# Release Version           => 2.3

# Corrections:
#       1. QUAD Program operation during Erase Suspend is added
#       2. Warning for Resume to Suspend time is added
#       3. During Erase Suspend, after Program operation is completed, WEL bit is cleared
#       4. Implementation of Software Reset is Changed
#       5. ADDRHILO_PG procedure corrected

# Files modified
-spansion_tc_pkg.vhd
-s25fl512s.v
-s25fl512s.vhd
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VITAL model author -  Snezana Petrovic
                      s-petrovic@hdl-dh.com
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# Release Label             => vital-amd-serial-s25fl-REL-s25fl512s-2011-04-18-1.tar.gz
# Release Date (DD/MM/YYYY) => 18/04/2011
# Release Version           => 2.4

# Corrections:
- corrected timing for internal signal rising_edge_CSNeg_ipd

# Files modified
-s25fl512s.v
-s25fl512s.sv
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VITAL model author -  Vesna Mancev
                      v-mancev@hdl-dh.com
                      Branislav Colakovic
                      b-colakovic@hdl-dh.com
##########################################
# Release Label             => vital-amd-serial-s25fl-REL-s25fl512s-2011-07-11-1.tar.gz
# Release Date (DD/MM/YYYY) => 11/07/2011
# Release Version           => 2.5

# Corrections:
- Latest Datasheet Aligned

# Files modified
-s25fl512s.v
-s25fl512s.vhd
-testbench_s25fl512s_verilog.vhd
-testbench_s25fl512s_vhdl.vhd
-spansion_tc_pkg.vhd
-s25fl512s.ftmv
-s25fl512s.ftm
-s25fl512s_verilog.sdf
-s25fl512s_vhdl.sdf
##########################################
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VITAL model author -  Vesna Mancev
                      v-mancev@hdl-dh.com
                      Branislav Colakovic
                      b-colakovic@hdl-dh.com
##########################################
# Release Label             => vital-amd-serial-s25fl-REL-s25fl512s-2011-07-15-2.tar.gz
# Release Date (DD/MM/YYYY) => 15/07/2011
# Release Version           => 2.6

# Corrections:
- Optimization issue is fixed
- Timingmodel is corrected

# Files modified
-s25fl512s.v
-s25fl512s.sv
-testbench_s25fl512s_vhdl.vhd
-testbench_s25fl512s_verilog.vhd
##########################################
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VITAL model author -  Vesna Mancev
                      v-mancev@hdl-dh.com
                      Branislav Colakovic
                      b-colakovic@hdl-dh.com
##########################################
# Release Label             => vital-amd-serial-s25fl-REL-s25fl512s-2011-07-22-1.tar.gz
# Release Date (DD/MM/YYYY) => 22/07/2011
# Release Version           => 2.7

# Corrections:
- Timing check issue is fixed
- Correction for P4E and P4E4 instructions

# Files modified
-s25fl512s.v
-s25fl512s.sv
-s25fl512s.vhd
##########################################
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VITAL model author -  Vesna Mancev
                      v-mancev@hdl-dh.com
##########################################
# Release Label             => vital-amd-serial-s25fl-REL-s25fl512s-2011-11-18-1.tar.gz
# Release Date (DD/MM/YYYY) => 18/11/2011
# Release Version           => 2.8

# Corrections:
- Time tHO is changed to 1 ns (customer's request)
- Setting of Device protection mode is modified (customer's request)
- BRWR instruction is corrected

# Files modified
-s25fl512s.v
-s25fl512s.vhd
-testbench_s25fl512s_verilog.vhd
-testbench_s25fl512s_vhdl.vhd
-s25fl512s.ftmv
-s25fl512s.ftm
-s25fl512s_verilog.sdf
-s25fl512s_vhdl.sdf
##########################################
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VITAL model author -  Snezana Petrovic
                      s-petrovic@hdl-dh.com
##########################################
# Release Label             => vital-amd-serial-s25fl-REL-s25fl512s-2012-06-02-1.tar.gz
# Release Date (DD/MM/YYYY) => 02/06/2012
# Release Version           => 2.9

# Corrections:
- OPP instruction is allowed in previously programmed page

# Files modified
-s25fl512s.v
-s25fl512s.sv
-s25fl512s.vhd
-testbench_s25fl512s_verilog.vhd
-testbench_s25fl512s_vhdl.vhd
-spansion_tc_pkg.vhd

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