----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:22:40 01/17/2009 
-- Design Name: 
-- Module Name:    scopetest - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity scopetest is
    Port ( sys_clk : in  STD_LOGIC;
           sys_rst_n : in  STD_LOGIC;
           clk_out_bus : out  STD_LOGIC_VECTOR (7 downto 0);
           clk_out_sma : out  STD_LOGIC_VECTOR (3 downto 0)
			  );
end scopetest;

architecture Behavioral of scopetest is

signal count : STD_LOGIC_VECTOR (6 downto 0);

begin

clk_out_bus <= count & sys_clk;
clk_out_sma <= count(3 downto 1) & sys_clk;

process (sys_clk) 
begin
   if sys_clk='1' and sys_clk'event then
      if sys_rst_n='0' then 
         count <= (others => '0');
      else
         count <= count + 1;
      end if;
   end if;
end process; 

end Behavioral;

