-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and2.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-input AND Gate
-- /___/   /\     Filename : AND2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:12 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND2 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic
    );
end AND2;

architecture AND2_V of AND2 is
begin
  O <= I0 and I1;
end AND2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and2b1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-input AND Gate
-- /___/   /\     Filename : AND2B1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:12 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND2B1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND2B1 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic
    );
end AND2B1;

architecture AND2B1_V of AND2B1 is
begin
  O <= (not I0) and I1;
end AND2B1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and2b2.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-input AND Gate
-- /___/   /\     Filename : AND2B2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:12 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND2B2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND2B2 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic
    );
end AND2B2;

architecture AND2B2_V of AND2B2 is
begin
  O <= (not I0) and (not I1);
end AND2B2_V;



-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and3.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-input AND Gate
-- /___/   /\     Filename : AND3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:12 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND3 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic
    );
end AND3;

architecture AND3_V of AND3 is
begin
  O <= I0 and I1 and I2;
end AND3_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and3b1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-input AND Gate
-- /___/   /\     Filename : AND3B1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:12 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND3B1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND3B1 is
  port(
    O : out std_ulogic;

    I0     : in std_ulogic;
    I1     : in std_ulogic;
    I2     : in std_ulogic
    );
end AND3B1;

architecture AND3B1_V of AND3B1 is
begin
  O <= (not I0) and I1 and I2;
end AND3B1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and3b2.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-input AND Gate
-- /___/   /\     Filename : AND3B2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:13 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND3B2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND3B2 is
  port(
    O : out std_ulogic;

    I0     : in std_ulogic;
    I1     : in std_ulogic;
    I2     : in std_ulogic
    );
end AND3B2;

architecture AND3B2_V of AND3B2 is
begin
  O <= (not I0) and (not I1) and I2;
end AND3B2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and3b3.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-input AND Gate
-- /___/   /\     Filename : AND3B3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:13 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND3B3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND3B3 is
  port(
    O : out std_ulogic;

    I0     : in std_ulogic;
    I1     : in std_ulogic;
    I2     : in std_ulogic
    );
end AND3B3;

architecture AND3B3_V of AND3B3 is
begin
  O <= (not I0) and (not I1) and (not I2);
end AND3B3_V;



-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and4.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input AND Gate
-- /___/   /\     Filename : AND4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:13 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND4 is
  port(
    O : out std_ulogic;

    I0   : in std_ulogic;
    I1   : in std_ulogic;
    I2   : in std_ulogic;
    I3   : in std_ulogic
    );
end AND4;

architecture AND4_V of AND4 is
begin
  O <= I0 and I1 and I2 and I3;
end AND4_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and4b1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input AND Gate
-- /___/   /\     Filename : AND4B1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:13 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND4B1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND4B1 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic
    );
end AND4B1;

architecture AND4B1_V of AND4B1 is
begin
  O <= (not I0) and I1 and I2 and I3;
end AND4B1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and4b2.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input AND Gate
-- /___/   /\     Filename : AND4B2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:13 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND4B2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND4B2 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic
    );
end AND4B2;

architecture AND4B2_V of AND4B2 is
begin
  O <= (not I1) and (not I0) and I2 and I3;
end AND4B2_V;



-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and4b3.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input AND Gate
-- /___/   /\     Filename : AND4B3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:13 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND4B3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND4B3 is
  port(
    O : out std_ulogic;

    I0     : in std_ulogic;
    I1     : in std_ulogic;
    I2     : in std_ulogic;
    I3     : in std_ulogic
    );
end AND4B3;

architecture AND4B3_V of AND4B3 is
begin
  O <= (not I1) and (not I0) and (not I2) and I3;
end AND4B3_V;



-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and4b4.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input AND Gate
-- /___/   /\     Filename : AND4B4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:13 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND4B4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND4B4 is
  port(
    O : out std_ulogic;

    I0     : in std_ulogic;
    I1     : in std_ulogic;
    I2     : in std_ulogic;
    I3     : in std_ulogic
    );
end AND4B4;

architecture AND4B4_V of AND4B4 is
begin
  O <= (not I1) and (not I0) and (not I2) and (not I3);
end AND4B4_V;



-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and5.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input AND Gate
-- /___/   /\     Filename : AND5.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:13 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND5 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end AND5;

architecture AND5_V of AND5 is
begin
  O <= I0 and I1 and I2 and I3 and I4;
end AND5_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and5b1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input AND Gate
-- /___/   /\     Filename : AND5B1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:13 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND5B1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND5B1 is
  port(
    O : out std_ulogic;

    I0     : in std_ulogic;
    I1     : in std_ulogic;
    I2     : in std_ulogic;
    I3     : in std_ulogic;
    I4     : in std_ulogic
    );
end AND5B1;

architecture AND5B1_V of AND5B1 is
begin
  O <= (not I0) and I1 and I2 and I3 and I4;
end AND5B1_V;




-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and5b2.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input AND Gate
-- /___/   /\     Filename : AND5B2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:14 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND5B2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND5B2 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end AND5B2;

architecture AND5B2_V of AND5B2 is
begin
  O <= (not I0) and (not I1) and I2 and I3 and I4;
end AND5B2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and5b3.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input AND Gate
-- /___/   /\     Filename : AND5B3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:14 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND5B3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND5B3 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end AND5B3;

architecture AND5B3_V of AND5B3 is
begin
  O <= (not I0) and (not I1) and (not I2) and I3 and I4;
end AND5B3_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and5b4.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input AND Gate
-- /___/   /\     Filename : AND5B4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:14 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND5B4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND5B4 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end AND5B4;

architecture AND5B4_V of AND5B4 is
begin
  O <= (not I0) and (not I1) and (not I2) and (not I3) and I4;
end AND5B4_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and5b5.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input AND Gate
-- /___/   /\     Filename : AND5B5.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:14 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND5B5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND5B5 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end AND5B5;

architecture AND5B5_V of AND5B5 is
begin
  O <= (not I0) and (not I1) and (not I2) and (not I3) and (not I4);
end AND5B5_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bscan_fpgacore.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Boundary Scan Logic Control Circuit for FPGACORE
-- /___/   /\     Filename : BSCAN_FPGACORE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:14 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL BSCAN_FPGACORE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BSCAN_FPGACORE is
  port(
    CAPTURE : out std_ulogic := 'H';
    DRCK1   : out std_ulogic := 'H';
    DRCK2   : out std_ulogic := 'H';
    RESET   : out std_ulogic := 'H';
    SEL1    : out std_ulogic := 'L';
    SEL2    : out std_ulogic := 'L';
    SHIFT   : out std_ulogic := 'L';
    TDI     : out std_ulogic := 'L';
    UPDATE  : out std_ulogic := 'L';

    TDO1 : in std_ulogic := 'X';
    TDO2 : in std_ulogic := 'X'
    );
end BSCAN_FPGACORE;

architecture BSCAN_FPGACORE_V of BSCAN_FPGACORE is
begin
  CAPTURE <= 'H';
  RESET   <= 'H';
  UPDATE  <= 'L';
  SHIFT   <= 'L';
  DRCK1   <= 'H';
  DRCK2   <= 'H';
  SEL1    <= 'L';
  SEL2    <= 'L';
  TDI     <= 'L';
end BSCAN_FPGACORE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bscan_spartan2.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Boundary Scan Logic Control Circuit for SPARTAN2
-- /___/   /\     Filename : BSCAN_SPARTAN2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:14 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL BSCAN_SPARTAN2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BSCAN_SPARTAN2 is
  port(
    DRCK1  : out std_ulogic := 'H';
    DRCK2  : out std_ulogic := 'H';
    RESET  : out std_ulogic := 'H';
    SEL1   : out std_ulogic := 'L';
    SEL2   : out std_ulogic := 'L';
    SHIFT  : out std_ulogic := 'L';
    TDI    : out std_ulogic := 'L';
    UPDATE : out std_ulogic := 'L';

    TDO1 : in std_ulogic := 'X';
    TDO2 : in std_ulogic := 'X'
    );
end BSCAN_SPARTAN2;

architecture BSCAN_SPARTAN2_V of BSCAN_SPARTAN2 is
begin
  RESET  <= 'H';
  UPDATE <= 'L';
  SHIFT  <= 'L';
  DRCK1  <= 'H';
  DRCK2  <= 'H';
  SEL1   <= 'L';
  SEL2   <= 'L';
  TDI    <= 'L';
end BSCAN_SPARTAN2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bscan_spartan3.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Boundary Scan Logic Control Circuit for SPARTAN3
-- /___/   /\     Filename : BSCAN_SPARTAN3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:14 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL BSCAN_SPARTAN3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BSCAN_SPARTAN3 is
  port(
    CAPTURE : out std_ulogic := 'H';
    DRCK1   : out std_ulogic := 'L';
    DRCK2   : out std_ulogic := 'L';
    RESET   : out std_ulogic := 'L';
    SEL1    : out std_ulogic := 'L';
    SEL2    : out std_ulogic := 'L';
    SHIFT   : out std_ulogic := 'L';
    TDI     : out std_ulogic := 'L';
    UPDATE  : out std_ulogic := 'L';

    TDO1 : in std_ulogic := 'X';
    TDO2 : in std_ulogic := 'X'
    );
end BSCAN_SPARTAN3;

architecture BSCAN_SPARTAN3_V of BSCAN_SPARTAN3 is
begin
  CAPTURE <= 'H';
  RESET   <= 'L';
  UPDATE  <= 'L';
  SHIFT   <= 'L';
  DRCK1   <= 'L';
  DRCK2   <= 'L';
  SEL1    <= 'L';
  SEL2    <= 'L';
  TDI     <= 'L';
end BSCAN_SPARTAN3_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bscan_virtex.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Boundary Scan Logic Control Circuit for VIRTEX
-- /___/   /\     Filename : BSCAN_VIRTEX.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:15 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL BSCAN_VIRTEX -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BSCAN_VIRTEX is
  port(
    DRCK1  : out std_ulogic := 'H';
    DRCK2  : out std_ulogic := 'H';
    RESET  : out std_ulogic := 'H';
    SEL1   : out std_ulogic := 'L';
    SEL2   : out std_ulogic := 'L';
    SHIFT  : out std_ulogic := 'L';
    TDI    : out std_ulogic := 'L';
    UPDATE : out std_ulogic := 'L';

    TDO1 : in std_ulogic := 'X';
    TDO2 : in std_ulogic := 'X'
    );
end BSCAN_VIRTEX;

architecture BSCAN_VIRTEX_V of BSCAN_VIRTEX is
begin
  RESET  <= 'H';
  UPDATE <= 'L';
  SHIFT  <= 'L';
  DRCK1  <= 'H';
  DRCK2  <= 'H';
  SEL1   <= 'L';
  SEL2   <= 'L';
  TDI    <= 'L';
end BSCAN_VIRTEX_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bscan_virtex2.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Boundary Scan Logic Control Circuit for VIRTEX2
-- /___/   /\     Filename : BSCAN_VIRTEX2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:15 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL BSCAN_VIRTEX2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BSCAN_VIRTEX2 is
  port(
    CAPTURE : out std_ulogic := 'H';
    DRCK1   : out std_ulogic := 'H';
    DRCK2   : out std_ulogic := 'H';
    RESET   : out std_ulogic := 'H';
    SEL1    : out std_ulogic := 'L';
    SEL2    : out std_ulogic := 'L';
    SHIFT   : out std_ulogic := 'L';
    TDI     : out std_ulogic := 'L';
    UPDATE  : out std_ulogic := 'L';

    TDO1 : in std_ulogic := 'X';
    TDO2 : in std_ulogic := 'X'
    );
end BSCAN_VIRTEX2;

architecture BSCAN_VIRTEX2_V of BSCAN_VIRTEX2 is
begin
  CAPTURE <= 'H';
  RESET   <= 'H';
  UPDATE  <= 'L';
  SHIFT   <= 'L';
  DRCK1   <= 'H';
  DRCK2   <= 'H';
  SEL1    <= 'L';
  SEL2    <= 'L';
  TDI     <= 'L';
end BSCAN_VIRTEX2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/buf.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  General Purpose Buffer
-- /___/   /\     Filename : BUF.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:15 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL BUF -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BUF is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end BUF;

architecture BUF_V of BUF is
begin
  O <= TO_X01(I);
end BUF_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bufcf.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Fast Connect Buffer
-- /___/   /\     Filename : BUFCF.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:15 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL BUFCF -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BUFCF is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end BUFCF;

architecture BUFCF_V of BUFCF is
begin
  O <= TO_X01(I);
end BUFCF_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bufe.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Internal 3-State Buffer with Active High Enable
-- /___/   /\     Filename : BUFE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:15 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL BUFE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BUFE is
  port(
    O : out std_ulogic;

    E : in std_ulogic;
    I : in std_ulogic
    );
end BUFE;

architecture BUFE_V of BUFE is
begin
  VITALBehavior : process(E, I)
    begin
      if ((E = '0') or (E = 'L')) then
        O <= 'Z';
      elsif ((E = '1') or (E = 'H')) then
        if ((I = '1') or (I = 'H')) then
          O <= '1';
        elsif ((I = '0') or (I = 'L')) then
          O <= '0';
        elsif (I = 'U') then
          O <= 'U';
        else
          O <= 'X';  
        end if;
      elsif (E = 'U') then
        O <= 'U';          
      else                                      
        O <= 'X';  
      end if;
  end process;  
end BUFE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bufg.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Buffer
-- /___/   /\     Filename : BUFG.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:15 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL BUFG -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BUFG is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end BUFG;

architecture BUFG_V of BUFG is
begin
  O <= TO_X01(I);
end BUFG_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bufgce.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Mux Buffer with Clock Enable and Output State 0
-- /___/   /\     Filename : BUFGCE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:15 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL BUFGCE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity BUFGCE is
     port(
	 O : out STD_ULOGIC;
         
	 CE: in STD_ULOGIC;
	 I : in STD_ULOGIC
         );
end BUFGCE;

architecture BUFGCE_V of BUFGCE is

    signal NCE : STD_ULOGIC := 'X';
    signal GND : STD_ULOGIC := '0';

begin
    B1 : BUFGMUX 
	port map (
	I0 => I,
	I1 => GND,
	O =>O,
	s =>NCE);

    I1 : INV
	port map (
	I => CE,
	O => NCE);

end BUFGCE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bufgce_1.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Mux Buffer with Clock Enable and Output State 1
-- /___/   /\     Filename : BUFGCE_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:15 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL BUFGCE_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity BUFGCE_1 is
	port(
	O : out STD_ULOGIC;
        
	CE: in STD_ULOGIC;
	I : in STD_ULOGIC
        );
end BUFGCE_1;
architecture BUFGCE_1_V of BUFGCE_1 is

    signal NCE : STD_ULOGIC := 'X';
    signal VCC : STD_ULOGIC := '1';

begin
    B1 : BUFGMUX_1 
	port map (
	I0 => I,
	I1 => VCC,
	O => O,
	s => NCE);

    I1 : INV 
	port map (
	I => CE,
	O => NCE);

end BUFGCE_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bufgdll.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Clock Delay Locked Loop Buffer
-- /___/   /\     Filename : BUFGDLL.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:16 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL BUFGDLL -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity BUFGDLL is
  generic(
    DUTY_CYCLE_CORRECTION :     boolean := true
    );
  port(
    O                     : out std_ulogic;

    I : in std_ulogic
    );
end BUFGDLL;

architecture BUFGDLL_V of BUFGDLL is

  signal clkin_int, clkout                           : std_ulogic;
  signal clk0_out, clk180_out, clk270_out, clk90_out : std_ulogic;
  signal clk2x_out, clkdv_out, locked_out            : std_ulogic := '0';
  signal gnd                                         : std_ulogic := '0';
begin
  IBUFG_inst                                         : IBUFG
    port map (
      O => clkin_int,

      I => I
      );

  CLKDLL_inst : CLKDLL
    generic map (
      DUTY_CYCLE_CORRECTION => DUTY_CYCLE_CORRECTION
      )

    port map(
      CLK0   => clk0_out,
      CLK180 => clk180_out,
      CLK270 => clk270_out,
      CLK2X  => clk2x_out,
      CLK90  => clk90_out,
      CLKDV  => clkdv_out,
      LOCKED => locked_out,

      CLKFB => clkout,
      CLKIN => clkin_int,
      RST   => gnd
      );

  BUFG_inst : BUFG
    port map (
      O => clkout,

      I => clk0_out
      );

  O <= clkout;
end BUFGDLL_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bufgmux.vhd,v 1.6.228.1 2008/02/29 00:12:09 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Mux Buffer with Output State 0
-- /___/   /\     Filename : BUFGMUX.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:16 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    02/07/08 - Recoding same as verilog model. (CR467336)
-- End Revision


----- CELL BUFGMUX -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BUFGMUX is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic := '0';
    I1 : in std_ulogic := '0';
    S  : in std_ulogic 
    );

end BUFGMUX;

architecture BUFGMUX_V of BUFGMUX is
  signal q0 : std_ulogic := '1';
  signal q0_enable : std_ulogic := '1';
  signal q1 : std_ulogic := '0';
  signal q1_enable : std_ulogic := '0';
begin

  O <= I0 when (q0 = '1') else I1 when (q1 = '1') else 'X' when ( q0 = 'X' or q1 = 'X') else 'L';

  q0_p : process(I0, S, q0_enable) 
  begin
     if (I0 /= '1') then
        q0 <= (not S) and q0_enable;
     end if;
  end process;

  q1_p : process(I1, S, q1_enable)
  begin
     if (I1 /= '1') then
        q1 <= S and q1_enable;
     end if;
  end process;

  q0_en_p : process(q1, I0)
  begin
      if (q1 = '1') then
          q0_enable <= '0';
      elsif (I0 /= '0') then
          q0_enable <=  not q1;
      end if;
  end process;

  q1_en_p : process(q0, I1)
  begin
      if (q0 = '1') then
          q1_enable <= '0';
      elsif (I1 /= '0') then
          q1_enable <=  not q0;
      end if;
  end process;

end BUFGMUX_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bufgmux_1.vhd,v 1.6.228.1 2008/02/29 00:15:22 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Mux Buffer with Output State 1
-- /___/   /\     Filename : BUFGMUX_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:16 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    02/07/08 - Recoding same as verilog model. (CR467336)
-- End Revision

----- CELL BUFGMUX_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BUFGMUX_1 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic := '1';
    I1 : in std_ulogic := '1';
    S  : in std_ulogic
    );
end BUFGMUX_1;

architecture BUFGMUX_1_V of BUFGMUX_1 is
  signal q0 : std_ulogic := '1';
  signal q0_enable : std_ulogic := '1';
  signal q1 : std_ulogic := '0';
  signal q1_enable : std_ulogic := '0';
begin

  O <= I0 when (q0 = '1') else I1 when (q1 = '1') else 'X' when ( q0 = 'X' or q1 = 'X') else 'H';

  q0_p : process(I0, S, q0_enable) 
  begin
     if (I0 /= '0') then
        q0 <= (not S) and q0_enable;
     end if;
  end process;

  q1_p : process(I1, S, q1_enable)
  begin
     if (I1 /= '0') then
        q1 <= S and q1_enable;
     end if;
  end process;

  q0_en_p : process(q1, I0)
  begin
      if (q1 = '1') then
          q0_enable <= '0';
      elsif (I0 /= '1') then
          q0_enable <=  not q1;
      end if;
  end process;

  q1_en_p : process(q0, I1)
  begin
      if (q0 = '1') then
          q1_enable <= '0';
      elsif (I1 /= '1') then
          q1_enable <=  not q0;
      end if;
  end process;


end BUFGMUX_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bufgp.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Primary Global Buffer for Driving Clocks or Long Lines
-- /___/   /\     Filename : BUFGP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:16 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL BUFGP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BUFGP is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end BUFGP;

architecture BUFGP_V of BUFGP is
begin
  O <= TO_X01(I);
end BUFGP_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/buft.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Internal 3-State Buffers with Active Low Enable
-- /___/   /\     Filename : BUFT.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:16 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL BUFT -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BUFT is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );
end BUFT;

architecture BUFT_V of BUFT is
begin
  VITALBehavior : process(I, T)
    begin
      if ((T = '1') or (T = 'H')) then
        O <= 'Z';
      elsif ((T = '0') or (T = 'L')) then
        if ((I = '1') or (I = 'H')) then
          O <= '1';
        elsif ((I = '0') or (I = 'L')) then
          O <= '0';
        elsif (I = 'U') then
          O <= 'U';
        else
          O <= 'X';  
        end if;
      elsif (T = 'U') then
        O <= 'U';          
      else                                      
        O <= 'X';  
      end if;
  end process;        
end BUFT_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/capture_fpgacore.vhd,v 1.8 2006/01/10 08:24:56 fphillip Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Register State Capture for Bitstream Readback for FPGACORE
-- /___/   /\     Filename : CAPTURE_FPGACORE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:16 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    07/23/05 - Added ONESHOT to all CAPUTURE comps; CR # 212645
--    01/10/06 - made ONESHOT false; CR # 220151
-- End Revision


----- CELL CAPTURE_FPGACORE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CAPTURE_FPGACORE is
  generic(
    ONESHOT : boolean := false
    );
  port(
    CAP : in std_ulogic;
    CLK : in std_ulogic
    );
end CAPTURE_FPGACORE;

architecture CAPTURE_FPGACORE_V of CAPTURE_FPGACORE is
begin
end CAPTURE_FPGACORE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/capture_spartan2.vhd,v 1.8 2006/01/10 08:24:56 fphillip Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Register State Capture for Bitstream Readback for SPARTAN2
-- /___/   /\     Filename : CAPTURE_SPARTAN2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:16 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    07/23/05 - Added ONESHOT to all CAPUTURE comps; CR # 212645
--    01/10/06 - made ONESHOT false; CR # 220151
-- End Revision

----- CELL CAPTURE_SPARTAN2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CAPTURE_SPARTAN2 is
  generic(
    ONESHOT : boolean := false
    );  
  port(
    CAP : in std_ulogic;
    CLK : in std_ulogic
    );
end CAPTURE_SPARTAN2;

architecture CAPTURE_SPARTAN2_V of CAPTURE_SPARTAN2 is
begin
end CAPTURE_SPARTAN2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/capture_spartan3.vhd,v 1.8 2006/01/10 08:24:56 fphillip Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Register State Capture for Bitstream Readback for SPARTAN3
-- /___/   /\     Filename : CAPTURE_SPARTAN3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:17 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    07/23/05 - Added ONESHOT to all CAPUTURE comps; CR # 212645
--    01/10/06 - made ONESHOT false; CR # 220151
-- End Revision

----- CELL CAPTURE_SPARTAN3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CAPTURE_SPARTAN3 is
  generic(
    ONESHOT : boolean := false
    );  
  port(
    CAP : in std_ulogic;
    CLK : in std_ulogic
    );
end CAPTURE_SPARTAN3;

architecture CAPTURE_SPARTAN3_V of CAPTURE_SPARTAN3 is
begin
end CAPTURE_SPARTAN3_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/capture_virtex.vhd,v 1.8 2006/01/10 08:24:56 fphillip Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Register State Capture for Bitstream Readback for VIRTEX
-- /___/   /\     Filename : CAPTURE_VIRTEX.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:17 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    07/23/05 - Added ONESHOT to all CAPUTURE comps; CR # 212645
--    01/10/06 - made ONESHOT false; CR # 220151
-- End Revision


----- CELL CAPTURE_VIRTEX -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CAPTURE_VIRTEX is
  generic(
    ONESHOT : boolean := false
    );  
  port(
    CAP : in std_ulogic;
    CLK : in std_ulogic
    );
end CAPTURE_VIRTEX;

architecture CAPTURE_VIRTEX_V of CAPTURE_VIRTEX is
begin
end CAPTURE_VIRTEX_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/capture_virtex2.vhd,v 1.8 2006/01/10 08:24:56 fphillip Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Register State Capture for Bitstream Readback for VIRTEX2
-- /___/   /\     Filename : CAPTURE_VIRTEX2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:17 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    07/23/05 - Added ONESHOT to all CAPUTURE comps; CR # 212645
--    01/10/06 - made ONESHOT false; CR # 220151
-- End Revision


----- CELL CAPTURE_VIRTEX2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CAPTURE_VIRTEX2 is
  generic(
    ONESHOT : boolean := false
    );
  port(
    CAP : in std_ulogic;
    CLK : in std_ulogic
    );
end CAPTURE_VIRTEX2;

architecture CAPTURE_VIRTEX2_V of CAPTURE_VIRTEX2 is
begin
end CAPTURE_VIRTEX2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/clkdll.vhd,v 1.15 2007/06/01 23:01:22 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Clock Delay Locked Loop
-- /___/   /\     Filename : CLKDLL.vhd
-- \   \  /  \    Timestamp : Fri Jun 18 10:55:21 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    05/09/05 - Change RST check from 3 clkin cycles to 2 ns (CR200477).
--     05/25/06 - Remove GSR (232012).
--     05/10/07 - Remove vital timing.
-- End Revision

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library STD;
use STD.TEXTIO.all;



entity clkdll_maximum_period_check is
  generic (
    clock_name : string := "";
    maximum_period : time);
  port(
    clock : in std_ulogic;
    rst : in std_ulogic
    );
end clkdll_maximum_period_check;

architecture clkdll_maximum_period_check_V of clkdll_maximum_period_check is
begin

  MAX_PERIOD_CHECKER : process
    variable clock_edge_previous : time := 0 ps;
    variable clock_edge_current : time := 0 ps;
    variable clock_period : time := 0 ps;
    variable Message : line;
  begin
    if (rising_edge(clock)) then
      clock_edge_previous := clock_edge_current;
      clock_edge_current := NOW;

      if (clock_edge_previous > 0 ps) then
        clock_period := clock_edge_current - clock_edge_previous;
      end if;

      if ((clock_period > maximum_period) and (rst = '0')) then
        Write ( Message, string'(" Error : Input Clock Period of"));
        Write ( Message, clock_period/1000.0 );
        Write ( Message, string'(" on the ") );
        Write ( Message, clock_name );
        Write ( Message, string'(" port ") );
        Write ( Message, string'(" of CLKDLL ") );
        Write ( Message, string'(" exceeds allotted value of ") );
        Write ( Message, maximum_period/1000.0 );
        Write ( Message, string'(" at simulation time ") );
        Write ( Message, clock_edge_current/1000.0 );
        Write ( Message, '.' & LF );
        assert false report Message.all severity warning;
        DEALLOCATE (Message);
      end if;
    end if;    
    wait on clock;
  end process MAX_PERIOD_CHECKER;
end clkdll_maximum_period_check_V;

----- CELL CLKDLL -----
library IEEE;
use IEEE.std_logic_1164.all;

library STD;
use STD.TEXTIO.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;


entity CLKDLL is
  generic (
    CLKDV_DIVIDE : real := 2.0;
    DUTY_CYCLE_CORRECTION : boolean := true;
    FACTORY_JF : bit_vector := X"C080";  --non-simulatable
    STARTUP_WAIT : boolean := false  --non-simulatable
    );

  port (
    CLK0 : out std_ulogic := '0';
    CLK180 : out std_ulogic := '0';
    CLK270 : out std_ulogic := '0';
    CLK2X : out std_ulogic := '0';
    CLK90 : out std_ulogic := '0';
    CLKDV : out std_ulogic := '0';
    LOCKED : out std_ulogic := '0';

    CLKFB : in std_ulogic := '0';
    CLKIN : in std_ulogic := '0';
    RST : in std_ulogic := '0'
    );

end CLKDLL;

architecture CLKDLL_V of CLKDLL is

  component clkdll_maximum_period_check
    generic (
      clock_name : string := "";
      maximum_period : time);
    port(
      clock : in std_ulogic;
      rst : in std_ulogic
      );
  end component;

  constant MAXPERCLKIN : time := 40000 ps;  
  constant SIM_CLKIN_CYCLE_JITTER : time := 300 ps;  
  constant SIM_CLKIN_PERIOD_JITTER : time := 1000 ps;  

  signal CLKFB_ipd, CLKIN_ipd, RST_ipd : std_ulogic;
  signal clk0_out : std_ulogic;
  signal clk2x_out, clkdv_out, locked_out : std_ulogic := '0';

  signal clkfb_type : integer;
  signal divide_type : integer;
  signal clk1x_type : integer;

  signal lock_period, lock_delay, lock_clkin, lock_clkfb : std_ulogic := '0';
  signal lock_out : std_logic_vector(1 downto 0) := "00";

  signal lock_fb : std_ulogic := '0';
  signal fb_delay_found : std_ulogic := '0';

  signal clkin_ps : std_ulogic;
  signal clkin_fb, clkin_fb0, clkin_fb1, clkin_fb2 : std_ulogic;
  type   real_array_usr is array (2 downto 0) of time;
  signal clkin_period_real : real_array_usr := (0.000 ns, 0.000 ns, 0.000 ns);
  signal period : time := 0 ps;
  signal period_orig : time := 0 ps;
  signal period_ps : time := 0 ps;
  signal clkout_delay : time := 0 ps;
  signal fb_delay : time := 0 ps;
  signal period_dv_high, period_dv_low : time := 0 ps;
  signal cycle_jitter, period_jitter : time := 0 ps;

  signal clkin_window, clkfb_window : std_ulogic := '0';
  signal clkin_5050 : std_ulogic := '0';
  signal rst_reg : std_logic_vector(2 downto 0) := "000";

  signal clkin_period_real0_temp : time := 0 ps;
  signal ps_lock_temp : std_ulogic := '0';

  signal clk0_temp : std_ulogic := '0';
  signal clk2x_temp : std_ulogic := '0';

  signal no_stop : boolean := false;

begin
  INITPROC : process
  begin
    detect_resolution
      (model_name => "CLKDLL"
       );
    if (CLKDV_DIVIDE = 1.5) then
      divide_type <= 3;
    elsif (CLKDV_DIVIDE = 2.0) then
      divide_type <= 4;
    elsif (CLKDV_DIVIDE = 2.5) then
      divide_type <= 5;
    elsif (CLKDV_DIVIDE = 3.0) then
      divide_type <= 6;
    elsif (CLKDV_DIVIDE = 4.0) then
      divide_type <= 8;
    elsif (CLKDV_DIVIDE = 5.0) then
      divide_type <= 10;
    elsif (CLKDV_DIVIDE = 8.0) then
      divide_type <= 16;
    elsif (CLKDV_DIVIDE = 16.0) then
      divide_type <= 32;
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLKDV_DIVIDE",
         EntityName => "CLKDLL",
         GenericValue => CLKDV_DIVIDE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    clkfb_type <= 2;

    period_jitter <= SIM_CLKIN_PERIOD_JITTER;
    cycle_jitter <= SIM_CLKIN_CYCLE_JITTER;

    case DUTY_CYCLE_CORRECTION is
      when false => clk1x_type <= 0;
      when true => clk1x_type <= 1;
      when others =>
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "DUTY_CYCLE_CORRECTION",
           EntityName => "CLKDLL",
           GenericValue => DUTY_CYCLE_CORRECTION,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
    end case;

    case STARTUP_WAIT is
      when false => null;
      when true => null;
      when others =>
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "STARTUP_WAIT",
           EntityName => "CLKDLL",
           GenericValue => STARTUP_WAIT,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
    end case;
    wait;
  end process INITPROC;

--
-- input wire delays
--

  CLKIN_ipd <= CLKIN;
  CLKFB_ipd <= CLKFB;
  RST_ipd <= RST;


  i_max_clkin : clkdll_maximum_period_check
    generic map (
      clock_name => "CLKIN",
      maximum_period => MAXPERCLKIN)

    port map (
      clock => clkin_ipd,
      rst => rst_ipd);

  assign_clkin_ps : process
  begin
    if (rst_ipd = '0') then
      clkin_ps <= clkin_ipd;
    elsif (rst_ipd = '1') then
      clkin_ps <= '0';      
      wait until (falling_edge(rst_reg(2)));
    end if;
    wait on clkin_ipd, rst_ipd;
  end process assign_clkin_ps;

  clkin_fb0 <= transport (clkin_ps and lock_fb) after period_ps/4;
  clkin_fb1 <= transport clkin_fb0 after period_ps/4;
  clkin_fb2 <= transport clkin_fb1 after period_ps/4;
  clkin_fb <= transport clkin_fb2 after period_ps/4;

  determine_period_ps : process
    variable clkin_ps_edge_previous : time := 0 ps;
    variable clkin_ps_edge_current : time := 0 ps;
  begin
    if (rst_ipd'event) then
      clkin_ps_edge_previous := 0 ps;
      clkin_ps_edge_current := 0 ps;
      period_ps <= 0 ps;
    else
      if (rising_edge(clkin_ps)) then
        clkin_ps_edge_previous := clkin_ps_edge_current;
        clkin_ps_edge_current := NOW;
        wait for 0 ps;
        if ((clkin_ps_edge_current - clkin_ps_edge_previous) <= (1.5 * period_ps)) then
          period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous;
        elsif ((period_ps = 0 ps) and (clkin_ps_edge_previous /= 0 ps)) then
          period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous;
        end if;
      end if;
    end if;
    wait on clkin_ps, rst_ipd;
  end process determine_period_ps;

  assign_lock_fb : process
  begin
    if (rising_edge(clkin_ps)) then
      lock_fb <= lock_period;
    end if;
    wait on clkin_ps;
  end process assign_lock_fb;

  calculate_clkout_delay : process
  begin
    if (rst_ipd'event) then
      clkout_delay <= 0 ps;            
    elsif (period'event or fb_delay'event) then
      clkout_delay <= period - fb_delay;
    end if;
    wait on period, fb_delay, rst_ipd;
  end process calculate_clkout_delay;

--
--generate master reset signal
--

  gen_master_rst : process
  begin
    if (rising_edge(clkin_ipd)) then
      rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst_ipd;
      rst_reg(1) <= rst_reg(0) and rst_ipd;
      rst_reg(0) <= rst_ipd;
    end if;
    wait on clkin_ipd;
  end process gen_master_rst;

  check_rst_width : process
    variable Message : line;
    variable rst_tmp1, rst_tmp2 : time := 0 ps;
  begin
    if ((rising_edge(rst_ipd)) or (falling_edge(rst_ipd))) then
      if (rst_ipd = '1') then
        rst_tmp1 := NOW;
      elsif (rst_ipd = '1') then
        rst_tmp2 := NOW - rst_tmp1;
      end if;
      if ((rst_tmp2 < 2000 ps) and (rst_tmp2 /= 0 ps)) then
        Write ( Message, string'(" Error : RST "));
        Write ( Message, string'(" must be asserted atleast for 2 ns. "));
        assert false report Message.all severity error;
        DEALLOCATE (Message);        
      end if;  
    end if;
    wait on rst_ipd;
  end process check_rst_width;

--
--determine clock period
--
  determine_clock_period : process
    variable clkin_edge_previous : time := 0 ps;
    variable clkin_edge_current : time := 0 ps;
  begin
    if (rst_ipd'event) then
      clkin_period_real(0) <= 0 ps;
      clkin_period_real(1) <= 0 ps;
      clkin_period_real(2) <= 0 ps;    
    elsif (rising_edge(clkin_ps)) then
      clkin_edge_previous := clkin_edge_current;
      clkin_edge_current := NOW;
      clkin_period_real(2) <= clkin_period_real(1);
      clkin_period_real(1) <= clkin_period_real(0);
      if (clkin_edge_previous /= 0 ps) then
        clkin_period_real(0) <= clkin_edge_current - clkin_edge_previous;
      end if;
    end if;
    if (no_stop'event) then
      clkin_period_real(0) <= clkin_period_real0_temp;
    end if;
    wait on clkin_ps, no_stop, rst_ipd;
  end process determine_clock_period;

  evaluate_clock_period : process
    variable clock_stopped : std_ulogic := '1';    
    variable Message : line;
  begin
    if (rst_ipd'event) then
      lock_period <= '0';
      clock_stopped := '1';
      clkin_period_real0_temp <= 0 ps;                        
    else
      if (falling_edge(clkin_ps)) then
        if (lock_period = '0') then
          if ((clkin_period_real(0) /= 0 ps ) and (clkin_period_real(0) - cycle_jitter <= clkin_period_real(1)) and (clkin_period_real(1) <= clkin_period_real(0) + cycle_jitter) and (clkin_period_real(1) - cycle_jitter <= clkin_period_real(2)) and (clkin_period_real(2) <= clkin_period_real(1) + cycle_jitter)) then
            lock_period <= '1';
            period_orig <= (clkin_period_real(0) + clkin_period_real(1) + clkin_period_real(2)) / 3;
            period <= clkin_period_real(0);
          end if;
        elsif (lock_period = '1') then
          if (100000000 ps < clkin_period_real(0)/1000) then
            Write ( Message, string'(" Error : CLKIN stopped toggling "));
            Write ( Message, string'(" exceeds "));
            Write ( Message, string'(" 10000 "));
            Write ( Message, string'(" Current CLKIN Period = "));
            Write ( Message, string'(" clkin_period(0) / 10000.0 "));
            Write ( Message, string'(" ns "));
            assert false report Message.all severity warning;
            DEALLOCATE (Message);
            lock_period <= '0';
            wait until (falling_edge(rst_reg(2)));
          elsif ((period_orig * 2 < clkin_period_real(0)) and (clock_stopped = '0')) then
            clkin_period_real0_temp <= clkin_period_real(1);
            no_stop <= not no_stop;
            clock_stopped := '1';            
          elsif ((clkin_period_real(0) < period_orig - period_jitter) or (period_orig + period_jitter < clkin_period_real(0))) then
            Write ( Message, string'(" Error : Input Clock Period Jitter "));
            Write ( Message, string'(" exceeds "));
            Write ( Message, period_jitter / 1000.0 );
            Write ( Message, string'(" Locked CLKIN Period = "));
            Write ( Message, period_orig / 1000.0 );
            Write ( Message, string'(" Current CLKIN Period = "));
            Write ( Message, clkin_period_real(0) / 1000.0 );
            assert false report Message.all severity warning;
            DEALLOCATE (Message);
            lock_period <= '0';
            wait until (falling_edge(rst_reg(2)));
          elsif ((clkin_period_real(0) < clkin_period_real(1) - cycle_jitter) or (clkin_period_real(1) + cycle_jitter < clkin_period_real(0))) then
            Write ( Message, string'(" Error : Input Clock Cycle Jitter  "));
            Write ( Message, string'(" exceeds "));
            Write ( Message, cycle_jitter / 1000.0 );
            Write ( Message, string'(" Previous CLKIN Period = "));
            Write ( Message, clkin_period_real(1) / 1000.0 );
            Write ( Message, string'(" Current CLKIN Period = "));
            Write ( Message, clkin_period_real(0) / 1000.0 );
            assert false report Message.all severity warning;
            DEALLOCATE (Message);
            lock_period <= '0';
            wait until (falling_edge(rst_reg(2)));
          else
            period <= clkin_period_real(0);
            clock_stopped := '0';            
          end if;
        end if;
      end if;
    end if;
    wait on clkin_ps, rst_ipd;
  end process evaluate_clock_period;

--
--determine clock delay
--

  determine_clock_delay : process
    variable delay_edge : time := 0 ps;
    variable temp1 : integer := 0;
    variable temp2 : integer := 0;
    variable temp : integer := 0;
    variable delay_edge_current : time := 0 ps;
  begin
    if (rst_ipd'event) then
      fb_delay <= 0 ps;      
      fb_delay_found <= '0';
    else
      if (rising_edge(lock_period)) then
        if ((lock_period = '1') and (clkfb_type /= 0)) then
          if (clkfb_type = 1) then
            wait until ((rising_edge(clk0_temp)) or (rst_ipd'event));                                
            delay_edge := NOW;
          elsif (clkfb_type = 2) then
            wait until ((rising_edge(clk2x_temp)) or (rst_ipd'event));            
            delay_edge := NOW;
          end if;
          wait until ((rising_edge(clkfb_ipd)) or (rst_ipd'event));          
          temp1 := ((NOW*1) - (delay_edge*1))/ (1 ps);
          temp2 := (period_orig * 1)/ (1 ps);
          temp := temp1 mod temp2;
          fb_delay <= temp * 1 ps;
        end if;
      end if;
      fb_delay_found <= '1';
    end if;
    wait on lock_period, rst_ipd;
  end process determine_clock_delay;
--
-- determine feedback lock
--
  GEN_CLKFB_WINDOW : process
  begin
    if (rst_ipd'event) then
      clkfb_window <= '0';
    else
      if (rising_edge(CLKFB_ipd)) then
        wait for 0 ps;
        clkfb_window <= '1';
        wait for cycle_jitter;
        clkfb_window <= '0';
      end if;
    end if;
    wait on clkfb_ipd, rst_ipd;
  end process GEN_CLKFB_WINDOW;

  GEN_CLKIN_WINDOW : process
  begin
    if (rst_ipd'event) then
      clkin_window <= '0';
    else
      if (rising_edge(clkin_fb)) then
        wait for 0 ps;
        clkin_window <= '1';
        wait for cycle_jitter;
        clkin_window <= '0';
      end if;
    end if;
    wait on clkin_fb, rst_ipd;
  end process GEN_CLKIN_WINDOW;

  set_reset_lock_clkin : process
  begin
    if (rst_ipd'event) then
      lock_clkin <= '0';
    else
      if (rising_edge(clkin_fb)) then
        wait for 1 ps;
        if ((clkfb_window = '1') and (fb_delay_found = '1')) then
          lock_clkin <= '1';
        else
          lock_clkin <= '0';
        end if;
      end if;
    end if;
    wait on clkin_fb, rst_ipd;
  end process set_reset_lock_clkin;

  set_reset_lock_clkfb : process
  begin
    if (rst_ipd'event) then
      lock_clkfb <= '0';
    else
      if (rising_edge(clkfb_ipd)) then
        wait for 1 ps;
        if ((clkin_window = '1') and (fb_delay_found = '1')) then
          lock_clkfb <= '1';
        else
          lock_clkfb <= '0';
        end if;
      end if;
    end if;
    wait on clkfb_ipd, rst_ipd;
  end process set_reset_lock_clkfb;

  assign_lock_delay : process
  begin
    if (rst_ipd'event) then
      lock_delay <= '0';
    else
      if (falling_edge(clkin_fb)) then
        lock_delay <= lock_clkin or lock_clkfb;
      end if;
    end if;
    wait on clkin_fb, rst_ipd;
  end process;

--
--generate lock signal
--

  generate_lock : process
  begin
    if (rst_ipd'event) then
      lock_out <= "00";
      locked_out <= '0';
    else
      if (rising_edge(clkin_ps)) then
        if (clkfb_type = 0) then
          lock_out(0) <= lock_period;
        else
          lock_out(0) <= lock_period and lock_delay and lock_fb;
        end if;
        lock_out(1) <= lock_out(0);
        locked_out <= lock_out(1);

      end if;
    end if;
    wait on clkin_ps, rst_ipd;
  end process generate_lock;

--
--generate the clk1x_out
--

  gen_clk1x : process
  begin
    if (rst_ipd'event) then
      clkin_5050 <= '0';
    else
      if (rising_edge(clkin_ps)) then
        clkin_5050 <= '1';
        wait for (period/2);
        clkin_5050 <= '0';
      end if;
    end if;
    wait on clkin_ps, rst_ipd;
  end process gen_clk1x;

  clk0_out <= clkin_5050 when (clk1x_type = 1) else clkin_ps;

--
--generate the clk2x_out
--

  gen_clk2x : process
  begin

    if (rising_edge(clkin_ps)) then
      clk2x_out <= '1';
      wait for (period / 4);
      clk2x_out <= '0';
      if (lock_out(0) = '1') then
        wait for (period / 4);
        clk2x_out <= '1';
        wait for (period / 4);
        clk2x_out <= '0';
      else
        wait for (period / 2);
      end if;
    end if;
    wait on clkin_ps;
  end process gen_clk2x;

--
--generate the clkdv_out
--

  determine_clkdv_period : process
  begin
    if (period'event) then
--      period_dv_high <= (period / 2) * (divide_type / 2);
--      period_dv_low <= (period / 2) * (divide_type / 2 + divide_type mod 2);
      period_dv_high <= (period * divide_type) / 4;
      period_dv_low <= (period * divide_type) / 4;      
    end if;
    wait on period;
  end process determine_clkdv_period;


  gen_clkdv : process
  begin
    if (rising_edge(clkin_ps)) then
      if (lock_out(0) = '1') then
        clkdv_out <= '1';
        wait for (period_dv_high);
        clkdv_out <= '0';
        wait for (period_dv_low);
        clkdv_out <= '1';
        wait for (period_dv_high);
        clkdv_out <= '0';
        wait for (period_dv_low - period/2);
      end if;
    end if;
    wait on clkin_ps;
  end process gen_clkdv;


--
--generate all output signal
--
  schedule_outputs : process
  begin
    if (CLK0_out'event) then
      CLK0 <= transport CLK0_out after clkout_delay;
      clk0_temp <= transport CLK0_out after clkout_delay;
      CLK90 <= transport clk0_out after (clkout_delay + period / 4);
      CLK180 <= transport clk0_out after (clkout_delay + period / 2);
      CLK270 <= transport clk0_out after (clkout_delay + (3 * period) / 4);
    end if;

    if (clk2x_out'event) then
      CLK2X <= transport clk2x_out after clkout_delay;
      clk2x_temp <= transport clk2x_out after clkout_delay;
    end if;

    if (clkdv_out'event) then
      CLKDV <= transport clkdv_out after clkout_delay;
    end if;

    LOCKED <= locked_out after 100 ps;
    wait on clk0_out, clk2x_out, clkdv_out, locked_out;
  end process schedule_outputs;

end CLKDLL_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/clkdlle.vhd,v 1.15 2007/06/01 23:01:22 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Clock Delay Locked Loop for Virtex-E
-- /___/   /\     Filename : CLKDLLE.vhd
-- \   \  /  \    Timestamp : Fri Jun 18 10:55:21 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    05/09/05 - Change RST check from 3 clkin cycles to 2 ns (CR200477).
--    05/25/06 - Remove GSR (232012).
--    05/10/07 - Remove Vital timing.
-- End Revision

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library STD;
use STD.TEXTIO.all;



entity clkdlle_maximum_period_check is
  generic (
    clock_name : string := "";
    maximum_period : time);
  port(
    clock : in std_ulogic;
    rst : in std_ulogic
    );
end clkdlle_maximum_period_check;

architecture clkdlle_maximum_period_check_V of clkdlle_maximum_period_check is
begin

  MAX_PERIOD_CHECKER : process
    variable clock_edge_previous : time := 0 ps;
    variable clock_edge_current : time := 0 ps;
    variable clock_period : time := 0 ps;
    variable Message : line;
  begin
    if (rising_edge(clock)) then
      clock_edge_previous := clock_edge_current;
      clock_edge_current := NOW;

      if (clock_edge_previous > 0 ps) then
        clock_period := clock_edge_current - clock_edge_previous;
      end if;

      if ((clock_period > maximum_period) and (rst = '0')) then
        Write ( Message, string'(" Error : Input Clock Period of"));
        Write ( Message, clock_period/1000.0 );
        Write ( Message, string'(" on the ") );
        Write ( Message, clock_name );
        Write ( Message, string'(" port ") );
        Write ( Message, string'(" of CLKDLLE  ") );
        Write ( Message, string'(" exceeds allotted value of ") );
        Write ( Message, maximum_period/1000.0 );
        Write ( Message, string'(" at simulation time ") );
        Write ( Message, clock_edge_current/1000.0 );
        Write ( Message, '.' & LF );
        assert false report Message.all severity warning;
        DEALLOCATE (Message);
      end if;
    end if;
    wait on clock;
  end process MAX_PERIOD_CHECKER;
end clkdlle_maximum_period_check_V;

----- CELL CLKDLLE -----
library IEEE;
use IEEE.std_logic_1164.all;

library STD;
use STD.TEXTIO.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity CLKDLLE is
  generic (

    CLKDV_DIVIDE : real := 2.0;
    DUTY_CYCLE_CORRECTION : boolean := true;
    FACTORY_JF : bit_vector := X"C080";  --non-simulatable
    STARTUP_WAIT : boolean := false  --non-simulatable
    );

  port (
    CLK0 : out std_ulogic := '0';
    CLK180 : out std_ulogic := '0';
    CLK270 : out std_ulogic := '0';
    CLK2X : out std_ulogic := '0';
    CLK2X180 : out std_ulogic := '0';
    CLK90 : out std_ulogic := '0';
    CLKDV : out std_ulogic := '0';
    LOCKED : out std_ulogic := '0';

    CLKFB : in std_ulogic := '0';
    CLKIN : in std_ulogic := '0';
    RST : in std_ulogic := '0'
    );

end CLKDLLE;

architecture CLKDLLE_V of CLKDLLE is

  component clkdlle_maximum_period_check
    generic (
      clock_name : string := "";
      maximum_period : time);
    port(
      clock : in std_ulogic;
      rst : in std_ulogic
      );
  end component;

  constant MAXPERCLKIN : time := 40000 ps;
  constant SIM_CLKIN_CYCLE_JITTER : time := 300 ps;
  constant SIM_CLKIN_PERIOD_JITTER : time := 1000 ps;

  signal CLKFB_ipd, CLKIN_ipd, RST_ipd : std_ulogic;
  signal clk0_out : std_ulogic;
  signal clk2x_out, clkdv_out, locked_out : std_ulogic := '0';

  signal clkfb_type : integer;
  signal divide_type : integer;
  signal clk1x_type : integer;

  signal lock_period, lock_delay, lock_clkin, lock_clkfb : std_ulogic := '0';
  signal lock_out : std_logic_vector(1 downto 0) := "00";

  signal lock_fb : std_ulogic := '0';
  signal fb_delay_found : std_ulogic := '0';

  signal clkin_ps : std_ulogic;
  signal clkin_fb, clkin_fb0, clkin_fb1, clkin_fb2 : std_ulogic;
  type   real_array_usr is array (2 downto 0) of time;
  signal clkin_period_real : real_array_usr := (0.000 ns, 0.000 ns, 0.000 ns);
  signal period : time := 0 ps;
  signal period_orig : time := 0 ps;
  signal period_ps : time := 0 ps;
  signal clkout_delay : time := 0 ps;
  signal fb_delay : time := 0 ps;
  signal period_dv_high, period_dv_low : time := 0 ps;
  signal cycle_jitter, period_jitter : time := 0 ps;

  signal clkin_window, clkfb_window : std_ulogic := '0';
  signal clkin_5050 : std_ulogic := '0';
  signal rst_reg : std_logic_vector(2 downto 0) := "000";

  signal clkin_period_real0_temp : time := 0 ps;
  signal ps_lock_temp : std_ulogic := '0';

  signal clk0_temp : std_ulogic := '0';
  signal clk2x_temp : std_ulogic := '0';

  signal no_stop : boolean := false;

begin
  INITPROC : process
  begin
    detect_resolution
      (model_name => "CLKDLLE"
       );    
    if (CLKDV_DIVIDE = 1.5) then
      divide_type <= 3;
    elsif (CLKDV_DIVIDE = 2.0) then
      divide_type <= 4;
    elsif (CLKDV_DIVIDE = 2.5) then
      divide_type <= 5;
    elsif (CLKDV_DIVIDE = 3.0) then
      divide_type <= 6;
    elsif (CLKDV_DIVIDE = 3.5) then
      divide_type <= 7;
    elsif (CLKDV_DIVIDE = 4.0) then
      divide_type <= 8;
    elsif (CLKDV_DIVIDE = 4.5) then
      divide_type <= 9;
    elsif (CLKDV_DIVIDE = 5.0) then
      divide_type <= 10;
    elsif (CLKDV_DIVIDE = 5.5) then
      divide_type <= 11;
    elsif (CLKDV_DIVIDE = 6.0) then
      divide_type <= 12;
    elsif (CLKDV_DIVIDE = 6.5) then
      divide_type <= 13;
    elsif (CLKDV_DIVIDE = 7.0) then
      divide_type <= 14;
    elsif (CLKDV_DIVIDE = 7.5) then
      divide_type <= 15;
    elsif (CLKDV_DIVIDE = 8.0) then
      divide_type <= 16;
    elsif (CLKDV_DIVIDE = 9.0) then
      divide_type <= 18;
    elsif (CLKDV_DIVIDE = 10.0) then
      divide_type <= 20;
    elsif (CLKDV_DIVIDE = 11.0) then
      divide_type <= 22;
    elsif (CLKDV_DIVIDE = 12.0) then
      divide_type <= 24;
    elsif (CLKDV_DIVIDE = 13.0) then
      divide_type <= 26;
    elsif (CLKDV_DIVIDE = 14.0) then
      divide_type <= 28;
    elsif (CLKDV_DIVIDE = 15.0) then
      divide_type <= 30;
    elsif (CLKDV_DIVIDE = 16.0) then
      divide_type <= 32;
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLKDV_DIVIDE",
         EntityName => "CLKDLLE",
         GenericValue => CLKDV_DIVIDE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    clkfb_type <= 2;

    period_jitter <= SIM_CLKIN_PERIOD_JITTER;
    cycle_jitter <= SIM_CLKIN_CYCLE_JITTER;

    case DUTY_CYCLE_CORRECTION is
      when false => clk1x_type <= 0;
      when true => clk1x_type <= 1;
      when others =>
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "DUTY_CYCLE_CORRECTION",
           EntityName => "CLKDLLE",
           GenericValue => DUTY_CYCLE_CORRECTION,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
    end case;

    case STARTUP_WAIT is
      when false => null;
      when true => null;
      when others =>
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "STARTUP_WAIT",
           EntityName => "CLKDLLE",
           GenericValue => STARTUP_WAIT,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
    end case;
    wait;
  end process INITPROC;

--
-- input wire delays
--

  CLKIN_ipd <= CLKIN;
  CLKFB_ipd <= CLKFB;
  RST_ipd <= RST;
  
  i_max_clkin : clkdlle_maximum_period_check
    generic map (
      clock_name => "CLKIN",
      maximum_period => MAXPERCLKIN)

    port map (
      clock => clkin_ipd,
      rst => rst_ipd);

  assign_clkin_ps : process
  begin
    if (rst_ipd = '0') then
      clkin_ps <= clkin_ipd;
    elsif (rst_ipd = '1') then
      clkin_ps <= '0';      
      wait until (falling_edge(rst_reg(2)));
    end if;
    wait on clkin_ipd, rst_ipd;
  end process assign_clkin_ps;

  clkin_fb0 <= transport (clkin_ps and lock_fb) after period_ps/4;
  clkin_fb1 <= transport clkin_fb0 after period_ps/4;
  clkin_fb2 <= transport clkin_fb1 after period_ps/4;
  clkin_fb <= transport clkin_fb2 after period_ps/4;

  determine_period_ps : process
    variable clkin_ps_edge_previous : time := 0 ps;
    variable clkin_ps_edge_current : time := 0 ps;
  begin
    if (rst_ipd'event) then
      clkin_ps_edge_previous := 0 ps;
      clkin_ps_edge_current := 0 ps;
      period_ps <= 0 ps;
    else
      if (rising_edge(clkin_ps)) then
        clkin_ps_edge_previous := clkin_ps_edge_current;
        clkin_ps_edge_current := NOW;
        wait for 0 ps;
        if ((clkin_ps_edge_current - clkin_ps_edge_previous) <= (1.5 * period_ps)) then
          period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous;
        elsif ((period_ps = 0 ps) and (clkin_ps_edge_previous /= 0 ps)) then
          period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous;
        end if;
      end if;
    end if;
    wait on clkin_ps, rst_ipd;
  end process determine_period_ps;

  assign_lock_fb : process
  begin
    if (rising_edge(clkin_ps)) then
      lock_fb <= lock_period;
    end if;
    wait on clkin_ps;
  end process assign_lock_fb;

  calculate_clkout_delay : process
  begin
    if (rst_ipd'event) then
      clkout_delay <= 0 ps;        
    elsif (period'event or fb_delay'event) then
      clkout_delay <= period - fb_delay;
    end if;
    wait on period, fb_delay, rst_ipd;
  end process calculate_clkout_delay;

--
--generate master reset signal
--

  gen_master_rst : process
  begin
    if (rising_edge(clkin_ipd)) then
      rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst_ipd;
      rst_reg(1) <= rst_reg(0) and rst_ipd;
      rst_reg(0) <= rst_ipd;
    end if;
    wait on clkin_ipd;
  end process gen_master_rst;

  check_rst_width : process
    variable Message : line;
    variable rst_tmp1, rst_tmp2 : time := 0 ps;
  begin
    if ((rising_edge(rst_ipd)) or (falling_edge(rst_ipd))) then
      if (rst_ipd = '1') then
        rst_tmp1 := NOW;
      elsif (rst_ipd = '1') then
        rst_tmp2 := NOW - rst_tmp1;
      end if;
      if ((rst_tmp2 < 2000 ps) and (rst_tmp2 /= 0 ps)) then
        Write ( Message, string'(" Error : RST "));
        Write ( Message, string'(" must be asserted atleast for 2 ns. "));
        assert false report Message.all severity error;
        DEALLOCATE (Message);        
      end if;  
    end if;
    wait on rst_ipd;
  end process check_rst_width;

--
--determine clock period
--
  determine_clock_period : process
    variable clkin_edge_previous : time := 0 ps;
    variable clkin_edge_current : time := 0 ps;
  begin
    if (rst_ipd'event) then
      clkin_period_real(0) <= 0 ps;
      clkin_period_real(1) <= 0 ps;
      clkin_period_real(2) <= 0 ps;
    elsif (rising_edge(clkin_ps)) then
      clkin_edge_previous := clkin_edge_current;
      clkin_edge_current := NOW;
      clkin_period_real(2) <= clkin_period_real(1);
      clkin_period_real(1) <= clkin_period_real(0);
      if (clkin_edge_previous /= 0 ps) then
        clkin_period_real(0) <= clkin_edge_current - clkin_edge_previous;
      end if;
    end if;
    if (no_stop'event) then
      clkin_period_real(0) <= clkin_period_real0_temp;
    end if;
    wait on clkin_ps, no_stop, rst_ipd;
  end process determine_clock_period;

  evaluate_clock_period : process
    variable clock_stopped : std_ulogic := '1';    
    variable Message : line;
  begin
    if (rst_ipd'event) then
      lock_period <= '0';
      clock_stopped := '1';
      clkin_period_real0_temp <= 0 ps;                        
    else
      if (falling_edge(clkin_ps)) then
        if (lock_period = '0') then
          if ((clkin_period_real(0) /= 0 ps ) and (clkin_period_real(0) - cycle_jitter <= clkin_period_real(1)) and (clkin_period_real(1) <= clkin_period_real(0) + cycle_jitter) and (clkin_period_real(1) - cycle_jitter <= clkin_period_real(2)) and (clkin_period_real(2) <= clkin_period_real(1) + cycle_jitter)) then
            lock_period <= '1';
            period_orig <= (clkin_period_real(0) + clkin_period_real(1) + clkin_period_real(2)) / 3;
            period <= clkin_period_real(0);
          end if;
        elsif (lock_period = '1') then
          if (100000000 ps < clkin_period_real(0)/1000) then
            Write ( Message, string'(" Error : CLKIN stopped toggling "));
            Write ( Message, string'(" exceeds "));
            Write ( Message, string'(" 10000 "));
            Write ( Message, string'(" Current CLKIN Period = "));
            Write ( Message, string'(" clkin_period(0) / 10000.0 "));
            Write ( Message, string'(" ns "));
            assert false report Message.all severity warning;
            DEALLOCATE (Message);
            lock_period <= '0';
            wait until (falling_edge(rst_reg(2)));
          elsif ((period_orig * 2 < clkin_period_real(0)) and (clock_stopped = '0')) then
            clkin_period_real0_temp <= clkin_period_real(1);
            no_stop <= not no_stop;
              clock_stopped := '1';            
          elsif ((clkin_period_real(0) < period_orig - period_jitter) or (period_orig + period_jitter < clkin_period_real(0))) then
            Write ( Message, string'(" Error : Input Clock Period Jitter  "));
            Write ( Message, string'(" exceeds "));
            Write ( Message, period_jitter / 1000.0 );
            Write ( Message, string'(" Locked CLKIN Period = "));
            Write ( Message, period_orig / 1000.0 );
            Write ( Message, string'(" Current CLKIN Period = "));
            Write ( Message, clkin_period_real(0) / 1000.0 );
            assert false report Message.all severity warning;
            DEALLOCATE (Message);
            lock_period <= '0';
            wait until (falling_edge(rst_reg(2)));
          elsif ((clkin_period_real(0) < clkin_period_real(1) - cycle_jitter) or (clkin_period_real(1) + cycle_jitter < clkin_period_real(0))) then
            Write ( Message, string'(" Error : Input Clock Cycle Jitter  "));
            Write ( Message, string'(" exceeds "));
            Write ( Message, cycle_jitter / 1000.0 );
            Write ( Message, string'(" Previous CLKIN Period = "));
            Write ( Message, clkin_period_real(1) / 1000.0 );
            Write ( Message, string'(" Current CLKIN Period = "));
            Write ( Message, clkin_period_real(0) / 1000.0 );
            assert false report Message.all severity warning;
            DEALLOCATE (Message);
            lock_period <= '0';
            wait until (falling_edge(rst_reg(2)));
          end if;
        else
          period <= clkin_period_real(0);
          clock_stopped := '0';          
        end if;
      end if;
    end if;
    wait on clkin_ps, rst_ipd;
  end process evaluate_clock_period;

--
--determine clock delay
--

  determine_clock_delay : process
    variable delay_edge : time := 0 ps;
    variable temp1 : integer := 0;
    variable temp2 : integer := 0;
    variable temp : integer := 0;
    variable delay_edge_current : time := 0 ps;
  begin
    if (rst_ipd'event) then
      fb_delay <= 0 ps;      
      fb_delay_found <= '0';
    else
      if (rising_edge(lock_period)) then
        if ((lock_period = '1') and (clkfb_type /= 0)) then
          if (clkfb_type = 1) then
            wait until ((rising_edge(clk0_temp)) or (rst_ipd'event));                                
            delay_edge := NOW;
          elsif (clkfb_type = 2) then
            wait until ((rising_edge(clk2x_temp)) or (rst_ipd'event));            
            delay_edge := NOW;
          end if;
          wait until ((rising_edge(clkfb_ipd)) or (rst_ipd'event));          
          temp1 := ((NOW*1) - (delay_edge*1))/ (1 ps);
          temp2 := (period_orig * 1)/ (1 ps);
          temp := temp1 mod temp2;
          fb_delay <= temp * 1 ps;
        end if;
      end if;
      fb_delay_found <= '1';
    end if;
    wait on lock_period, rst_ipd;
  end process determine_clock_delay;
--
-- determine feedback lock
--
  GEN_CLKFB_WINDOW : process
  begin
    if (rst_ipd'event) then
      clkfb_window <= '0';
    else
      if (rising_edge(CLKFB_ipd)) then
        wait for 0 ps;
        clkfb_window <= '1';
        wait for cycle_jitter;
        clkfb_window <= '0';
      end if;
    end if;
    wait on clkfb_ipd, rst_ipd;
  end process GEN_CLKFB_WINDOW;

  GEN_CLKIN_WINDOW : process
  begin
    if (rst_ipd'event) then
      clkin_window <= '0';
    else
      if (rising_edge(clkin_fb)) then
        wait for 0 ps;
        clkin_window <= '1';
        wait for cycle_jitter;
        clkin_window <= '0';
      end if;
    end if;
    wait on clkin_fb, rst_ipd;
  end process GEN_CLKIN_WINDOW;

  set_reset_lock_clkin : process
  begin
    if (rst_ipd'event) then
      lock_clkin <= '0';
    else
      if (rising_edge(clkin_fb)) then
        wait for 1 ps;
        if ((clkfb_window = '1') and (fb_delay_found = '1')) then
          lock_clkin <= '1';
        else
          lock_clkin <= '0';
        end if;
      end if;
    end if;
    wait on clkin_fb, rst_ipd;
  end process set_reset_lock_clkin;

  set_reset_lock_clkfb : process
  begin
    if (rst_ipd'event) then
      lock_clkfb <= '0';
    else
      if (rising_edge(clkfb_ipd)) then
        wait for 1 ps;
        if ((clkin_window = '1') and (fb_delay_found = '1')) then
          lock_clkfb <= '1';
        else
          lock_clkfb <= '0';
        end if;
      end if;
    end if;
    wait on clkfb_ipd, rst_ipd;
  end process set_reset_lock_clkfb;

  assign_lock_delay : process
  begin
    if (rst_ipd'event) then
      lock_delay <= '0';
    else
      if (falling_edge(clkin_fb)) then
        lock_delay <= lock_clkin or lock_clkfb;
      end if;
    end if;
    wait on clkin_fb, rst_ipd;
  end process;

--
--generate lock signal
--

  generate_lock : process
  begin
    if (rst_ipd'event) then
      lock_out <= "00";
      locked_out <= '0';
    else
      if (rising_edge(clkin_ps)) then
        if (clkfb_type = 0) then
          lock_out(0) <= lock_period;
        else
          lock_out(0) <= lock_period and lock_delay and lock_fb;
        end if;
        lock_out(1) <= lock_out(0);
        locked_out <= lock_out(1);

      end if;
    end if;
    wait on clkin_ps, rst_ipd;
  end process generate_lock;

--
--generate the clk1x_out
--

  gen_clk1x : process
  begin
    if (rst_ipd'event) then
      clkin_5050 <= '0';
    else
      if (rising_edge(clkin_ps)) then
        clkin_5050 <= '1';
        wait for (period/2);
        clkin_5050 <= '0';
      end if;
    end if;
    wait on clkin_ps, rst_ipd;
  end process gen_clk1x;

  clk0_out <= clkin_5050 when (clk1x_type = 1) else clkin_ps;

--
--generate the clk2x_out
--

  gen_clk2x : process
  begin

    if (rising_edge(clkin_ps)) then
      clk2x_out <= '1';
      wait for (period / 4);
      clk2x_out <= '0';
      if (lock_out(0) = '1') then
        wait for (period / 4);
        clk2x_out <= '1';
        wait for (period / 4);
        clk2x_out <= '0';
      else
        wait for (period / 2);
      end if;
    end if;
    wait on clkin_ps;
  end process gen_clk2x;

--
--generate the clkdv_out
--

  determine_clkdv_period : process
  begin
    if (period'event) then
--      period_dv_high <= (period / 2) * (divide_type / 2);
--      period_dv_low <= (period / 2) * (divide_type / 2 + divide_type mod 2);
      period_dv_high <= (period * divide_type)/4;
      period_dv_low <= (period * divide_type)/4;      
    end if;
    wait on period;
  end process determine_clkdv_period;


  gen_clkdv : process
  begin
    if (rising_edge(clkin_ps)) then
      if (lock_out(0) = '1') then
        clkdv_out <= '1';
        wait for (period_dv_high);
        clkdv_out <= '0';
        wait for (period_dv_low);
        clkdv_out <= '1';
        wait for (period_dv_high);
        clkdv_out <= '0';
        wait for (period_dv_low - period/2);
      end if;
    end if;
    wait on clkin_ps;
  end process gen_clkdv;


--
--generate all output signal
--
  schedule_outputs : process
  begin
    if (CLK0_out'event) then
      CLK0 <= transport CLK0_out after clkout_delay;
      clk0_temp <= transport CLK0_out after clkout_delay;
      CLK90 <= transport clk0_out after (clkout_delay + period / 4);
      CLK180 <= transport clk0_out after (clkout_delay + period / 2);
      CLK270 <= transport clk0_out after (clkout_delay + (3 * period) / 4);
    end if;

    if (clk2x_out'event) then
      CLK2X <= transport clk2x_out after clkout_delay;
      clk2x_temp <= transport clk2x_out after clkout_delay;
      CLK2X180 <= transport clk2x_out after (clkout_delay + period/4);
    end if;

    if (clkdv_out'event) then
      CLKDV <= transport clkdv_out after clkout_delay;
    end if;

    LOCKED <= locked_out after 100 ps;
    wait on clk0_out, clk2x_out, clkdv_out, locked_out;
  end process schedule_outputs;

end CLKDLLE_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/clkdllhf.vhd,v 1.14 2007/06/01 23:01:22 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  High Frequency Clcok Delay Locked Loop
-- /___/   /\     Filename : CLKDLLHF.vhd
-- \   \  /  \    Timestamp : Fri Jun 18 10:55:21 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    05/09/05 - Change RST check from 3 clkin cycles to 2 ns (CR200477).
--    05/25/06 - Remove GSR (232012).
--    05/10/07 - Remove vital timing.
-- End Revision

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library STD;
use STD.TEXTIO.all;



entity clkdllhf_maximum_period_check is
  generic (
    clock_name : string := "";
    maximum_period : time);
  port(
    clock : in std_ulogic;
    rst : in std_ulogic
    );
end clkdllhf_maximum_period_check;

architecture clkdllhf_maximum_period_check_V of clkdllhf_maximum_period_check is
begin

  MAX_PERIOD_CHECKER : process
    variable clock_edge_previous : time := 0 ps;
    variable clock_edge_current : time := 0 ps;
    variable clock_period : time := 0 ps;
    variable Message : line;
  begin
    if (rising_edge(clock)) then
      clock_edge_previous := clock_edge_current;
      clock_edge_current := NOW;

      if (clock_edge_previous > 0 ps) then
        clock_period := clock_edge_current - clock_edge_previous;
      end if;

      if ((clock_period > maximum_period) and (rst = '0')) then
        Write ( Message, string'(" Error : Input Clock Period of"));
        Write ( Message, clock_period/1000.0 );
        Write ( Message, string'(" on the ") );
        Write ( Message, clock_name );
        Write ( Message, string'(" port ") );
        Write ( Message, string'(" of CLKDLLHF ") );
        Write ( Message, string'(" exceeds allotted value of ") );
        Write ( Message, maximum_period/1000.0 );
        Write ( Message, string'(" at simulation time ") );
        Write ( Message, clock_edge_current/1000.0 );
        Write ( Message, '.' & LF );
        assert false report Message.all severity warning;
        DEALLOCATE (Message);
      end if;
    end if;
    wait on clock;
  end process MAX_PERIOD_CHECKER;
end clkdllhf_maximum_period_check_V;

----- CELL CLKDLLHF -----
library IEEE;
use IEEE.std_logic_1164.all;

library STD;
use STD.TEXTIO.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity CLKDLLHF is
  generic (
    CLKDV_DIVIDE : real := 2.0;
    DUTY_CYCLE_CORRECTION : boolean := true;
    FACTORY_JF : bit_vector := X"FFF0";  --non-simulatable
    STARTUP_WAIT : boolean := false  --non-simulatable
    );

  port (
    CLK0 : out std_ulogic := '0';
    CLK180 : out std_ulogic := '0';
    CLKDV : out std_ulogic := '0';
    LOCKED : out std_ulogic := '0';

    CLKFB : in std_ulogic := '0';
    CLKIN : in std_ulogic := '0';
    RST : in std_ulogic := '0'
    );

end CLKDLLHF;

architecture CLKDLLHF_V of CLKDLLHF is

  component clkdllhf_maximum_period_check
    generic (
      clock_name : string := "";
      maximum_period : time);
    port(
      clock : in std_ulogic;
      rst : in std_ulogic      
      );
  end component;

  constant MAXPERCLKIN : time := 40000 ps;
  constant SIM_CLKIN_CYCLE_JITTER : time := 300 ps;
  constant SIM_CLKIN_PERIOD_JITTER : time := 1000 ps;

  signal CLKFB_ipd, CLKIN_ipd, RST_ipd : std_ulogic;
  signal clk0_out : std_ulogic;
  signal clkdv_out, locked_out : std_ulogic := '0';

  signal clkfb_type : integer;
  signal divide_type : integer;
  signal clk1x_type : integer;

  signal lock_period, lock_delay, lock_clkin, lock_clkfb : std_ulogic := '0';
  signal lock_out : std_logic_vector(1 downto 0) := "00";

  signal lock_fb : std_ulogic := '0';
  signal fb_delay_found : std_ulogic := '0';

  signal clkin_ps : std_ulogic;
  signal clkin_fb, clkin_fb0, clkin_fb1, clkin_fb2 : std_ulogic;
  type   real_array_usr is array (2 downto 0) of time;
  signal clkin_period_real : real_array_usr := (0.000 ns, 0.000 ns, 0.000 ns);
  signal period : time := 0 ps;
  signal period_orig : time := 0 ps;
  signal period_ps : time := 0 ps;
  signal clkout_delay : time := 0 ps;
  signal fb_delay : time := 0 ps;
  signal period_dv_high, period_dv_low : time := 0 ps;
  signal cycle_jitter, period_jitter : time := 0 ps;

  signal clkin_window, clkfb_window : std_ulogic := '0';
  signal clkin_5050 : std_ulogic := '0';
  signal rst_reg : std_logic_vector(2 downto 0) := "000";

  signal clkin_period_real0_temp : time := 0 ps;
  signal ps_lock_temp : std_ulogic := '0';

  signal clk0_temp : std_ulogic := '0';
  signal clk2X_temp : std_ulogic := '0';

  signal no_stop : boolean := false;

begin
  INITPROC : process
  begin
    detect_resolution
      (model_name => "CLKDLLHF"
       );    

    if (CLKDV_DIVIDE = 1.5) then
      divide_type <= 3;
    elsif (CLKDV_DIVIDE = 2.0) then
      divide_type <= 4;
    elsif (CLKDV_DIVIDE = 2.5) then
      divide_type <= 5;
    elsif (CLKDV_DIVIDE = 3.0) then
      divide_type <= 6;
    elsif (CLKDV_DIVIDE = 4.0) then
      divide_type <= 8;
    elsif (CLKDV_DIVIDE = 5.0) then
      divide_type <= 10;
    elsif (CLKDV_DIVIDE = 8.0) then
      divide_type <= 16;
    elsif (CLKDV_DIVIDE = 16.0) then
      divide_type <= 32;
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLKDV_DIVIDE",
         EntityName => "CLKDLLHF",
         GenericValue => CLKDV_DIVIDE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    clkfb_type <= 1;

    period_jitter <= SIM_CLKIN_PERIOD_JITTER;
    cycle_jitter <= SIM_CLKIN_CYCLE_JITTER;

    case DUTY_CYCLE_CORRECTION is
      when false => clk1x_type <= 0;
      when true => clk1x_type <= 1;
      when others =>
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "DUTY_CYCLE_CORRECTION",
           EntityName => "CLKDLLHF",
           GenericValue => DUTY_CYCLE_CORRECTION,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
    end case;

    case STARTUP_WAIT is
      when false => null;
      when true => null;
      when others =>
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "STARTUP_WAIT",
           EntityName => "CLKDLLHF",
           GenericValue => STARTUP_WAIT,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
    end case;
    wait;
  end process INITPROC;

--
-- input wire delays
--

   CLKIN_ipd<= CLKIN;
   CLKFB_ipd <= CLKFB;
   RST_ipd <= RST;

  
  i_max_clkin : clkdllhf_maximum_period_check
    generic map (
      clock_name => "CLKIN",
      maximum_period => MAXPERCLKIN)

    port map (
      clock => clkin_ipd,
      rst => rst_ipd);

  assign_clkin_ps : process
  begin
    if (rst_ipd = '0') then
      clkin_ps <= clkin_ipd;
    elsif (rst_ipd = '1') then
      clkin_ps <= '0';
      wait until (falling_edge(rst_reg(2)));
    end if;
    wait on clkin_ipd, rst_ipd;
  end process assign_clkin_ps;

  clkin_fb0 <= transport (clkin_ps and lock_fb) after period_ps/4;
  clkin_fb1 <= transport clkin_fb0 after period_ps/4;
  clkin_fb2 <= transport clkin_fb1 after period_ps/4;
  clkin_fb <= transport clkin_fb2 after period_ps/4;

  determine_period_ps : process
    variable clkin_ps_edge_previous : time := 0 ps;
    variable clkin_ps_edge_current : time := 0 ps;
  begin
    if (rst_ipd'event) then
      clkin_ps_edge_previous := 0 ps;
      clkin_ps_edge_current := 0 ps;
      period_ps <= 0 ps;
    else
      if (rising_edge(clkin_ps)) then
        clkin_ps_edge_previous := clkin_ps_edge_current;
        clkin_ps_edge_current := NOW;
        wait for 0 ps;
        if ((clkin_ps_edge_current - clkin_ps_edge_previous) <= (1.5 * period_ps)) then
          period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous;
        elsif ((period_ps = 0 ps) and (clkin_ps_edge_previous /= 0 ps)) then
          period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous;
        end if;
      end if;
    end if;
    wait on clkin_ps, rst_ipd;
  end process determine_period_ps;

  assign_lock_fb : process
  begin
    if (rising_edge(clkin_ps)) then
      lock_fb <= lock_period;
    end if;
    wait on clkin_ps;
  end process assign_lock_fb;

  calculate_clkout_delay : process
  begin
    if (rst_ipd'event) then
      clkout_delay <= 0 ps;        
    elsif (period'event or fb_delay'event) then
      clkout_delay <= period - fb_delay;
    end if;
    wait on period, fb_delay, rst_ipd;
  end process calculate_clkout_delay;

--
--generate master reset signal
--

  gen_master_rst : process
  begin
    if (rising_edge(clkin_ipd)) then
      rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst_ipd;
      rst_reg(1) <= rst_reg(0) and rst_ipd;
      rst_reg(0) <= rst_ipd;
    end if;
    wait on clkin_ipd;
  end process gen_master_rst;

  check_rst_width : process
    variable Message : line;
    variable rst_tmp1, rst_tmp2 : time := 0 ps;
  begin
    if ((rising_edge(rst_ipd)) or (falling_edge(rst_ipd))) then
      if (rst_ipd = '1') then
        rst_tmp1 := NOW;
      elsif (rst_ipd = '1') then
        rst_tmp2 := NOW - rst_tmp1;
      end if;
      if ((rst_tmp2 < 2000 ps) and (rst_tmp2 /= 0 ps)) then
        Write ( Message, string'(" Error : RST "));
        Write ( Message, string'(" must be asserted atleast for 2 ns. "));
        assert false report Message.all severity error;
        DEALLOCATE (Message);        
      end if;  
    end if;
    wait on rst_ipd;
  end process check_rst_width;

--
--determine clock period
--
  determine_clock_period : process
    variable clkin_edge_previous : time := 0 ps;
    variable clkin_edge_current : time := 0 ps;
  begin
    if (rst_ipd'event) then
      clkin_period_real(0) <= 0 ps;
      clkin_period_real(1) <= 0 ps;
      clkin_period_real(2) <= 0 ps;
    elsif (rising_edge(clkin_ps)) then
      clkin_edge_previous := clkin_edge_current;
      clkin_edge_current := NOW;
      clkin_period_real(2) <= clkin_period_real(1);
      clkin_period_real(1) <= clkin_period_real(0);
      if (clkin_edge_previous /= 0 ps) then
        clkin_period_real(0) <= clkin_edge_current - clkin_edge_previous;
      end if;
    end if;
    if (no_stop'event) then
      clkin_period_real(0) <= clkin_period_real0_temp;
    end if;
    wait on clkin_ps, no_stop, rst_ipd;
  end process determine_clock_period;

  evaluate_clock_period : process
    variable clock_stopped : std_ulogic := '1';    
    variable Message : line;
  begin
    if (rst_ipd'event) then
      lock_period <= '0';
      clock_stopped := '1';
      clkin_period_real0_temp <= 0 ps;                        
    else
      if (falling_edge(clkin_ps)) then
        if (lock_period = '0') then
          if ((clkin_period_real(0) /= 0 ps ) and (clkin_period_real(0) - cycle_jitter <= clkin_period_real(1)) and (clkin_period_real(1) <= clkin_period_real(0) + cycle_jitter) and (clkin_period_real(1) - cycle_jitter <= clkin_period_real(2)) and (clkin_period_real(2) <= clkin_period_real(1) + cycle_jitter)) then
            lock_period <= '1';
            period_orig <= (clkin_period_real(0) + clkin_period_real(1) + clkin_period_real(2)) / 3;
            period <= clkin_period_real(0);
          end if;
        elsif (lock_period = '1') then
          if (100000000 ps < clkin_period_real(0)/1000) then
            Write ( Message, string'(" Error : CLKIN stopped toggling "));
            Write ( Message, string'(" exceeds "));
            Write ( Message, string'(" 10000 "));
            Write ( Message, string'(" Current CLKIN Period = "));
            Write ( Message, string'(" clkin_period(0) / 10000.0 "));
            Write ( Message, string'(" ns "));
            assert false report Message.all severity warning;
            DEALLOCATE (Message);
            lock_period <= '0';
            wait until (falling_edge(rst_reg(2)));
          elsif ((period_orig * 2 < clkin_period_real(0)) and (clock_stopped = '0')) then
            clkin_period_real0_temp <= clkin_period_real(1);
            no_stop <= not no_stop;
            clock_stopped := '1';            
          elsif ((clkin_period_real(0) < period_orig - period_jitter) or (period_orig + period_jitter < clkin_period_real(0))) then
            Write ( Message, string'(" Error : Input Clock Period Jitter "));
            Write ( Message, string'(" exceeds "));
            Write ( Message, period_jitter / 1000.0 );
            Write ( Message, string'(" Locked CLKIN Period = "));
            Write ( Message, period_orig / 1000.0 );
            Write ( Message, string'(" Current CLKIN Period = "));
            Write ( Message, clkin_period_real(0) / 1000.0 );
            assert false report Message.all severity warning;
            DEALLOCATE (Message);
            lock_period <= '0';
            wait until (falling_edge(rst_reg(2)));
          elsif ((clkin_period_real(0) < clkin_period_real(1) - cycle_jitter) or (clkin_period_real(1) + cycle_jitter < clkin_period_real(0))) then
            Write ( Message, string'(" Error : Input Clock Cycle Jitter "));
            Write ( Message, string'(" exceeds "));
            Write ( Message, cycle_jitter / 1000.0 );
            Write ( Message, string'(" Previous CLKIN Period = "));
            Write ( Message, clkin_period_real(1) / 1000.0 );
            Write ( Message, string'(" Current CLKIN Period = "));
            Write ( Message, clkin_period_real(0) / 1000.0 );
            assert false report Message.all severity warning;
            DEALLOCATE (Message);
            lock_period <= '0';
            wait until (falling_edge(rst_reg(2)));
          end if;
        else
          period <= clkin_period_real(0);
          clock_stopped := '0';          
        end if;
      end if;
    end if;
    wait on clkin_ps, rst_ipd;
  end process evaluate_clock_period;

  determine_clock_delay : process
    variable delay_edge : time := 0 ps;
    variable temp1 : integer := 0;
    variable temp2 : integer := 0;
    variable temp : integer := 0;
    variable delay_edge_current : time := 0 ps;
  begin
    if (rst_ipd'event) then
      fb_delay <= 0 ps;      
      fb_delay_found <= '0';
    else
      if (rising_edge(lock_period)) then
        if ((lock_period = '1') and (clkfb_type /= 0)) then
          if (clkfb_type = 1) then
            wait until ((rising_edge(clk0_temp)) or (rst_ipd'event));                                
            delay_edge := NOW;
          elsif (clkfb_type = 2) then
            wait until ((rising_edge(clk2x_temp)) or (rst_ipd'event));            
            delay_edge := NOW;
          end if;
          wait until ((rising_edge(clkfb_ipd)) or (rst_ipd'event));          
          temp1 := ((NOW*1) - (delay_edge*1))/ (1 ps);
          temp2 := (period_orig * 1)/ (1 ps);
          temp := temp1 mod temp2;
          fb_delay <= temp * 1 ps;
        end if;
      end if;
      fb_delay_found <= '1';
    end if;
    wait on lock_period, rst_ipd;
  end process determine_clock_delay;
--
-- determine feedback lock
--
  GEN_CLKFB_WINDOW : process
  begin
    if (rst_ipd'event) then
      clkfb_window <= '0';
    else
      if (rising_edge(CLKFB_ipd)) then
        wait for 0 ps;
        clkfb_window <= '1';
        wait for cycle_jitter;
        clkfb_window <= '0';
      end if;
    end if;
    wait on clkfb_ipd, rst_ipd;
  end process GEN_CLKFB_WINDOW;

  GEN_CLKIN_WINDOW : process
  begin
    if (rst_ipd'event) then
      clkin_window <= '0';
    else
      if (rising_edge(clkin_fb)) then
        wait for 0 ps;
        clkin_window <= '1';
        wait for cycle_jitter;
        clkin_window <= '0';
      end if;
    end if;
    wait on clkin_fb, rst_ipd;
  end process GEN_CLKIN_WINDOW;

  set_reset_lock_clkin : process
  begin
    if (rst_ipd'event) then
      lock_clkin <= '0';
    else
      if (rising_edge(clkin_fb)) then
        wait for 1 ps;
        if ((clkfb_window = '1') and (fb_delay_found = '1')) then
          lock_clkin <= '1';
        else
          lock_clkin <= '0';
        end if;
      end if;
    end if;
    wait on clkin_fb, rst_ipd;
  end process set_reset_lock_clkin;

  set_reset_lock_clkfb : process
  begin
    if (rst_ipd'event) then
      lock_clkfb <= '0';
    else
      if (rising_edge(clkfb_ipd)) then
        wait for 1 ps;
        if ((clkin_window = '1') and (fb_delay_found = '1')) then
          lock_clkfb <= '1';
        else
          lock_clkfb <= '0';
        end if;
      end if;
    end if;
    wait on clkfb_ipd, rst_ipd;
  end process set_reset_lock_clkfb;

  assign_lock_delay : process
  begin
    if (rst_ipd'event) then
      lock_delay <= '0';
    else
      if (falling_edge(clkin_fb)) then
        lock_delay <= lock_clkin or lock_clkfb;
      end if;
    end if;
    wait on clkin_fb, rst_ipd;
  end process;

--
--generate lock signal
--

  generate_lock : process
  begin
    if (rst_ipd'event) then
      lock_out <= "00";
      locked_out <= '0';
    else
      if (rising_edge(clkin_ps)) then
        if (clkfb_type = 0) then
          lock_out(0) <= lock_period;
        else
          lock_out(0) <= lock_period and lock_delay and lock_fb;
        end if;
        lock_out(1) <= lock_out(0);
        locked_out <= lock_out(1);

      end if;
    end if;
    wait on clkin_ps, rst_ipd;
  end process generate_lock;

--
--generate the clk1x_out
--

  gen_clk1x : process
  begin
    if (rst_ipd'event) then
      clkin_5050 <= '0';
    else
      if (rising_edge(clkin_ps)) then
        clkin_5050 <= '1';
        wait for (period/2);
        clkin_5050 <= '0';
      end if;
    end if;
    wait on clkin_ps, rst_ipd;
  end process gen_clk1x;

  clk0_out <= clkin_5050 when (clk1x_type = 1) else clkin_ps;

--
--generate the clkdv_out
--

  determine_clkdv_period : process
  begin
    if (period'event) then
      period_dv_high <= (period / 2) * (divide_type / 2);
      period_dv_low <= (period / 2) * (divide_type / 2 + divide_type mod 2);
    end if;
    wait on period;
  end process determine_clkdv_period;


  gen_clkdv : process
  begin
    if (rising_edge(clkin_ps)) then
      if (lock_out(0) = '1') then
        clkdv_out <= '1';
        wait for (period_dv_high);
        clkdv_out <= '0';
        wait for (period_dv_low);
        clkdv_out <= '1';
        wait for (period_dv_high);
        clkdv_out <= '0';
        wait for (period_dv_low - period/2);
      end if;
    end if;
    wait on clkin_ps;
  end process gen_clkdv;


--
--generate all output signal
--
  schedule_outputs : process
  begin
    if (CLK0_out'event) then
      CLK0 <= transport CLK0_out after clkout_delay;
      clk0_temp <= transport CLK0_out after clkout_delay;
      CLK180 <= transport clk0_out after (clkout_delay + period / 2);
    end if;


    if (clkdv_out'event) then
      CLKDV <= transport clkdv_out after clkout_delay;
    end if;

    LOCKED <= locked_out after 100 ps;
    wait on clk0_out, clkdv_out, locked_out;
  end process schedule_outputs;

end CLKDLLHF_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/config.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  
-- /___/   /\     Filename : CONFIG.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:21 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CONFIG -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CONFIG is
end CONFIG;

architecture CONFIG_V of CONFIG is
begin
end CONFIG_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/dcm.vhd,v 1.28.16.2 2008/03/18 22:25:55 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Digital Clock Manager
-- /___/   /\     Filename : DCM.vhd
-- \   \  /  \    Timestamp : Fri Jun 18 10:57:08 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    05/11/05 - Add clkin alignment check control to remove the glitch when
--               clkin stopped. (CR207409).
--    05/25/05 - Seperate clock_second_pos and neg to another process due to
--               wait caused unreset. Set fb_delay_found after fb_delay computed.
--               Enable clkfb_div after lock_fb high (CR 208771)
--    06/03/05 - Use after instead wait for clk0_out(CR209283).
--               Update error message (CR 209076).
--    07/06/05 - Add lock_fb_dly to alignment check. (CR210755).
--               Use counter to generate clkdv_out to align with clk0_out. (CR211465).
--    07/25/05 - Set CLKIN_PERIOD default to 10.0ns to (CR 213190).
--    08/30/05 - Change reset for CLK270, CLK180 (CR 213641).
--    09/08/05 - Add positive edge trig to dcm_maximum_period_check_v. (CR 216828).
--    12/22/05 - LOCKED = x when RST less than 3 clock cycles (CR 222795)
--    02/28/06 - Remove 1 ps in clkfx_out block to support fs resolution (CR222390)
--    09/22/06 - Add lock_period and lock_fb to clkfb_div block (CR418722).
--    12/19/06 - Add clkfb_div_en for clkfb2x divider (CR431210).
--    04/06/07 - Enable the clock out in clock low time after reset in model 
--               clock_divide_by_2  (CR 437471).
--    06/11/07 - Add SIM_MODE and fast unisim model (SLIB_M2.1)
--    08/29/07 - Change delay of lock_fb_dly to 0.75*period, same as verilog (CR447628).
--    02/21/08 - Align clk2x to both clk0 pos and neg edges. (CR467858).
--    03/01/08 - Disable alignment of clkfb and clkin_fb check when ps_lock high (CR468893).
-- End Revision


----- dcm_clock_divide_by_2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity dcm_clock_divide_by_2 is
  port(
    clock_out : out std_ulogic := '0';

    clock : in std_ulogic;
    clock_type : in integer;
    rst : in std_ulogic
    );
end dcm_clock_divide_by_2;

architecture dcm_clock_divide_by_2_V of dcm_clock_divide_by_2 is
  signal clock_div2 : std_ulogic := '0';
  signal rst_reg : std_logic_vector(2 downto 0);
  signal clk_src : std_ulogic;
begin

  CLKIN_DIVIDER : process
  begin
    if (rising_edge(clock)) then
      clock_div2 <= not clock_div2;
    end if;
    wait on clock;
  end process CLKIN_DIVIDER;

  gen_reset : process
  begin
    if (rising_edge(clock)) then      
      rst_reg(0) <= rst;
      rst_reg(1) <= rst_reg(0) and rst;
      rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst;
    end if;      
    wait on clock;    
  end process gen_reset;

  clk_src <= clock_div2 when (clock_type = 1) else clock;

  assign_clkout : process
  begin
    if (rst = '0') then
      clock_out <= clk_src;
    elsif (rst = '1') then
      clock_out <= '0';
      wait until falling_edge(rst_reg(2));
      if (clk_src = '1') then
         wait until falling_edge(clk_src);
      end if;
    end if;
    wait on clk_src, rst, rst_reg;
  end process assign_clkout;
end dcm_clock_divide_by_2_V;

----- dcm_maximum_period_check  -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;

library STD;
use STD.TEXTIO.all;

entity dcm_maximum_period_check is
  generic (
--    InstancePath : string := "*";

    clock_name : string := "";
    maximum_period : time);
  port(
    clock : in std_ulogic;
    rst : in std_ulogic
    );
end dcm_maximum_period_check;

architecture dcm_maximum_period_check_V of dcm_maximum_period_check is
begin

  MAX_PERIOD_CHECKER : process
    variable clock_edge_previous : time := 0 ps;
    variable clock_edge_current : time := 0 ps;
    variable clock_period : time := 0 ps;
    variable Message : line;
  begin

   if (rising_edge(clock)) then
    clock_edge_previous := clock_edge_current;
    clock_edge_current := NOW;

    if (clock_edge_previous > 0 ps) then
      clock_period := clock_edge_current - clock_edge_previous;
    end if;

    if (clock_period > maximum_period and  rst = '0') then
      Write ( Message, string'(" Warning : Input Clock Period of "));
      Write ( Message, clock_period );
      Write ( Message, string'(" on the ") );
      Write ( Message, clock_name );      
      Write ( Message, string'(" port ") );      
      Write ( Message, string'(" of DCM instance ") );
      Write ( Message, string'(" exceeds allowed value of ") );
      Write ( Message, maximum_period );
      Write ( Message, string'(" at simulation time ") );
      Write ( Message, clock_edge_current );
      Write ( Message, '.' & LF );
      assert false report Message.all severity warning;
      DEALLOCATE (Message);
    end if;
   end if;
    wait on clock;
  end process MAX_PERIOD_CHECKER;
end dcm_maximum_period_check_V;

----- dcm_clock_lost  -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity dcm_clock_lost is
  port(
    lost : out std_ulogic := '0';

    clock : in std_ulogic;
    enable : in boolean := false;
    rst :  in std_ulogic    
    );
end dcm_clock_lost;

architecture dcm_clock_lost_V of dcm_clock_lost is
  signal period : time := 0 ps;
  signal lost_r : std_ulogic := '0';
  signal lost_f : std_ulogic := '0';
  signal lost_sig : std_ulogic := '0';  
  signal clock_negedge, clock_posedge : std_ulogic;
  signal clock_low, clock_high : std_ulogic := '0';
  signal clock_second_pos, clock_second_neg : std_ulogic := '0';
begin
  determine_period : process
    variable clock_edge_previous : time := 0 ps;
    variable clock_edge_current : time := 0 ps;    
  begin
      if (rst = '1') then
        period <= 0 ps;
      elsif (rising_edge(clock)) then
        clock_edge_previous := clock_edge_current;
        clock_edge_current := NOW;
        if (period /= 0 ps and ((clock_edge_current - clock_edge_previous) <= (1.5 * period))) then
          period <= NOW - clock_edge_previous;
        elsif (period /= 0 ps and ((NOW - clock_edge_previous) > (1.5 * period))) then
          period <= 0 ps;
        elsif ((period = 0 ps) and (clock_edge_previous /= 0 ps) and (clock_second_pos = '1')) then
          period <= NOW - clock_edge_previous;
        end if;
      end if;      
    wait on clock, rst;
  end process determine_period;

  CLOCK_LOST_CHECKER : process

  begin
      if (rst = '1') then
        clock_low <= '0';
        clock_high <= '0';
        clock_posedge <= '0';              
        clock_negedge <= '0';
      else
        if (rising_edge(clock)) then
          clock_low <= '0';
          clock_high <= '1';
          clock_posedge <= '0';              
          clock_negedge <= '1';
        end if;

        if (falling_edge(clock)) then
          clock_high <= '0';
          clock_low <= '1';
          clock_posedge <= '1';
          clock_negedge <= '0';
        end if;
      end if;

    wait on clock, rst;
  end process CLOCK_LOST_CHECKER;    

  CLOCK_SECOND_P : process
    begin
      if (rst = '1') then
        clock_second_pos <= '0';
        clock_second_neg <= '0';
    else
      if (rising_edge(clock)) then
        clock_second_pos <= '1';
      end if;
      if (falling_edge(clock)) then
          clock_second_neg <= '1';
      end if;
    end if;
    wait on clock, rst;
  end process CLOCK_SECOND_P;

  SET_RESET_LOST_R : process
    begin
    if (rst = '1') then
      lost_r <= '0';
    else
      if ((enable = true) and (clock_second_pos = '1'))then
        if (rising_edge(clock)) then
          wait for 1 ps;                      
          if (period /= 0 ps) then
            lost_r <= '0';        
          end if;
          wait for (period * (9.1/10.0));
          if ((clock_low /= '1') and (clock_posedge /= '1') and (rst = '0')) then
            lost_r <= '1';
          end if;
        end if;
      end if;
    end if;
    wait on clock, rst;    
  end process SET_RESET_LOST_R;

  SET_RESET_LOST_F : process
    begin
      if (rst = '1') then
        lost_f <= '0';
      else
        if ((enable = true) and (clock_second_neg = '1'))then
          if (falling_edge(clock)) then
            if (period /= 0 ps) then      
              lost_f <= '0';
            end if;
            wait for (period * (9.1/10.0));
            if ((clock_high /= '1') and (clock_negedge /= '1') and (rst = '0')) then
              lost_f <= '1';
            end if;      
          end if;        
        end if;
      end if;
    wait on clock, rst;    
  end process SET_RESET_LOST_F;      

  assign_lost : process
    begin
      if (enable = true) then
        if (lost_r'event) then
          lost <= lost_r;
        end if;
        if (lost_f'event) then
          lost <= lost_f;
        end if;
      end if;      
      wait on lost_r, lost_f;
    end process assign_lost;
end dcm_clock_lost_V;


----- CELL DCM  -----
library IEEE;
use IEEE.std_logic_1164.all;





library STD;
use STD.TEXTIO.all;

library unisim;
use unisim.VPKG.all;

entity DCM is
  generic (
    CLKDV_DIVIDE : real := 2.0;
    CLKFX_DIVIDE : integer := 1;
    CLKFX_MULTIPLY : integer := 4;
    CLKIN_DIVIDE_BY_2 : boolean := false;
    CLKIN_PERIOD : real := 10.0;                         --non-simulatable
    CLKOUT_PHASE_SHIFT : string := "NONE";
    CLK_FEEDBACK : string := "1X";
    DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";     --non-simulatable
    DFS_FREQUENCY_MODE : string := "LOW";
    DLL_FREQUENCY_MODE : string := "LOW";
    DSS_MODE : string := "NONE";                        --non-simulatable
    DUTY_CYCLE_CORRECTION : boolean := true;
    FACTORY_JF : bit_vector := X"C080";                 --non-simulatable
    PHASE_SHIFT : integer := 0;
    SIM_MODE : string := "SAFE";
    STARTUP_WAIT : boolean := false                     --non-simulatable
    );

  port (
    CLK0 : out std_ulogic := '0';
    CLK180 : out std_ulogic := '0';
    CLK270 : out std_ulogic := '0';
    CLK2X : out std_ulogic := '0';
    CLK2X180 : out std_ulogic := '0';
    CLK90 : out std_ulogic := '0';
    CLKDV : out std_ulogic := '0';
    CLKFX : out std_ulogic := '0';
    CLKFX180 : out std_ulogic := '0';
    LOCKED : out std_ulogic := '0';
    PSDONE : out std_ulogic := '0';
    STATUS : out std_logic_vector(7 downto 0) := "00000000";
    
    CLKFB : in std_ulogic := '0';
    CLKIN : in std_ulogic := '0';
    DSSEN : in std_ulogic := '0';
    PSCLK : in std_ulogic := '0';
    PSEN : in std_ulogic := '0';
    PSINCDEC : in std_ulogic := '0';
    RST : in std_ulogic := '0'
    );

end DCM;

architecture DCM_V of DCM is

  component dcm_clock_divide_by_2
    port(
      clock_out : out std_ulogic;

      clock : in std_ulogic;
      clock_type : in integer;
      rst : in std_ulogic
      );
  end component;

  component dcm_maximum_period_check
    generic (
--      InstancePath : string := "*";

      clock_name : string := "";
      maximum_period : time);
    port(
      clock : in std_ulogic;
      rst : in std_ulogic
      );
  end component;

  component dcm_clock_lost
    port(
      lost : out std_ulogic;

      clock : in std_ulogic;
      enable : in boolean := false;
      rst :  in std_ulogic          
      );    
  end component;

  signal CLKFB_ipd, CLKIN_ipd, DSSEN_ipd : std_ulogic;
  signal PSCLK_ipd, PSEN_ipd, PSINCDEC_ipd, RST_ipd : std_ulogic;
  signal PSCLK_dly ,PSEN_dly, PSINCDEC_dly : std_ulogic := '0';
  
  signal clk0_out : std_ulogic;
  signal clk2x_out, clkdv_out : std_ulogic := '0';
  signal clkfx_out, locked_out, psdone_out, ps_overflow_out, ps_lock : std_ulogic := '0';
  signal clk0_out_o : std_ulogic;
  signal clk2x_out_o, clkdv_out_o : std_ulogic := '0';
  signal clkfx_out_o  : std_ulogic := '0';
  signal clk180_out_o, clk90_out_o, clk270_out_o, clk2x180_out_o : std_ulogic := '0';
  signal clkfx180_out_o : std_ulogic := '0';
  signal clk0_out_ofs : std_ulogic;
  signal clk2x_out_ofs, clkdv_out_ofs : std_ulogic := '0';
  signal clkfx_out_ofs  : std_ulogic := '0';
  signal clk180_out_ofs, clk90_out_ofs, clk270_out_ofs, clk2x180_out_ofs : std_ulogic := '0';
  signal clkfx180_out_ofs : std_ulogic := '0';
  signal locked_out_out : std_ulogic := '0';
  signal LOCKED_sig : std_ulogic := '0';  
  signal LOCKED_sig_fs : std_ulogic := '0';  


  signal clkdv_cnt : integer := 0;
  signal clkfb_type : integer;
  signal divide_type : integer;
  signal clkin_type : integer;
  signal ps_type : integer;
  signal deskew_adjust_mode : integer;
  signal dfs_mode_type : integer;
  signal dll_mode_type : integer;
  signal clk1x_type : integer;


  signal lock_period, lock_delay, lock_clkin, lock_clkfb : std_ulogic := '0';
  signal lock_out : std_logic_vector(1 downto 0) := "00";  
  signal lock_out1_neg : std_ulogic := '0';

  signal lock_fb : std_ulogic := '0';
  signal lock_fb_dly : std_ulogic := '0';
  signal lock_fb_dly_tmp : std_ulogic := '0';
  signal fb_delay_found : std_ulogic := '0';

  signal clkin_div : std_ulogic;
  signal clkin_ps : std_ulogic;
  signal clkin_fb : std_ulogic;


  signal ps_delay : time := 0 ps;
  type   real_array_usr is array (2 downto 0) of time;
  signal clkin_period_real : real_array_usr := (0.000 ns, 0.000 ns, 0.000 ns);
  signal period : time := 0 ps;
  signal period_div : time := 0 ps;
  signal period_orig : time := 0 ps;
  signal period_ps : time := 0 ps;
  signal clkout_delay : time := 0 ps;
  signal fb_delay : time := 0 ps;
  signal period_fx, remain_fx : time := 0 ps;
  signal period_dv_high, period_dv_low : time := 0 ps;
  signal cycle_jitter, period_jitter : time := 0 ps;

  signal clkin_window, clkfb_window : std_ulogic := '0';
  signal rst_reg : std_logic_vector(2 downto 0) := "000";
  signal rst_flag : std_ulogic := '0';
  signal numerator, denominator, gcd : integer := 1;

  signal clkin_lost_out : std_ulogic := '0';
  signal clkfx_lost_out : std_ulogic := '0';

  signal remain_fx_temp : integer := 0;

  signal clkin_period_real0_temp : time := 0 ps;
  signal ps_lock_reg : std_ulogic := '0';

  signal clk0_sig : std_ulogic := '0';
  signal clk2x_sig : std_ulogic := '0';

  signal no_stop : boolean := false;

  signal clkfx180_en : std_ulogic := '0';

  signal status_out  : std_logic_vector(7 downto 0) := "00000000";
  signal status_out_fs  : std_logic_vector(7 downto 0) := "00000000";

  signal first_time_locked : boolean := false;

  signal en_status : boolean := false;

  signal ps_overflow_out_ext : std_ulogic := '0';  
  signal clkin_lost_out_ext : std_ulogic := '0';
  signal clkfx_lost_out_ext : std_ulogic := '0';

  signal clkfb_div : std_ulogic := '0';
  signal clkfb_div_en : std_ulogic := '0';
  signal clkfb_chk : std_ulogic := '0';

  signal lock_period_dly : std_ulogic := '0';
  signal lock_period_pulse : std_ulogic := '0';  

  signal clock_stopped : std_ulogic := '1';

  signal clkin_chkin, clkfb_chkin : std_ulogic := '0';
  signal chk_enable, chk_rst : std_ulogic := '0';

  signal lock_ps : std_ulogic := '0';
  signal lock_ps_dly : std_ulogic := '0';      

  constant MAXPERCLKIN : time := 1000000 ps;                   
  constant MAXPERPSCLK : time := 100000000 ps;                 
  constant SIM_CLKIN_CYCLE_JITTER : time := 300 ps;
  constant SIM_CLKIN_PERIOD_JITTER : time := 1000 ps;
  signal  CLK0_out_fs :  std_ulogic := '0';
  signal  CLK180_out_fs :  std_ulogic := '0';
  signal  CLK270_out_fs :  std_ulogic := '0';
  signal  CLK2X_out_fs :  std_ulogic := '0';
  signal  CLK2X180_out_fs :  std_ulogic := '0';
  signal  CLK90_out_fs :  std_ulogic := '0';
  signal  CLKFX180_out_fs :  std_ulogic := '0';
  signal  CLKFX_out_fs :  std_ulogic := '0';
  signal  CLKDV_out_fs :  std_ulogic := '0';
  signal  PSDONE_out_fs :  std_ulogic := '0';
  signal  LOCKED_out_fs :  std_ulogic := '0';

  signal pos_shift : std_logic_vector (2 downto 0) := "000";
  signal pos_shift_st : std_logic_vector (2 downto 0) := "000";
  signal neg_shift : std_logic_vector (2 downto 0) := "000";
  signal neg_shift_st : std_logic_vector (2 downto 0) := "000";
  signal clkin_cnt : integer := 0;
  signal old_clkin_cnt : integer := 0;

  signal align : std_logic := '0';
  signal clkin_divide : std_logic := '0';
  signal fbsync : std_logic := '0';
  signal clkin_error : std_logic := '0';
  signal period_updated : std_logic := '0';
  signal clkin_cnt_en : std_logic := '0';

  signal clk_period : delay_length; 
  signal clkfx_period : delay_length; 
  signal shift_ammount : delay_length;
  signal clkdv_period : delay_length; 
  signal start_time, delay_time : delay_length;
  signal clkfx_divide_real, clkfx_multiply_real, phase_shift_real : real;
  signal rst_tmp, rst_done_fx, rst_done_dv : std_logic := '0';
  signal sim_mode_type : std_logic := '0';

begin
     sim_mode_type <= '1' when (SIM_MODE="FAST") else '0';
     CLK0 <= CLK0_out_ofs when sim_mode_type = '1' else CLK0_out_o;
     CLK180 <= CLK180_out_ofs when sim_mode_type = '1' else CLK180_out_o;
     CLK270 <= CLK270_out_ofs when sim_mode_type = '1' else CLK270_out_o;
     CLK2X <= CLK2X_out_ofs when sim_mode_type = '1' else CLK2X_out_o;
     CLK2X180 <= CLK2X180_out_ofs when sim_mode_type = '1' else CLK2X180_out_o;
     CLK90 <= CLK90_out_ofs when sim_mode_type = '1' else CLK90_out_o;
     CLKDV <= CLKDV_out_ofs when sim_mode_type = '1' else CLKDV_out_o;
     CLKFX <= CLKFX_out_ofs when sim_mode_type = '1' else CLKFX_out_o;
     CLKFX180 <= CLKFX180_out_ofs when sim_mode_type = '1' else CLKFX180_out_o;
     STATUS <= status_out_fs when sim_mode_type = '1' else status_out;
    LOCKED <= LOCKED_sig_fs after 100 ps when sim_mode_type = '1' else LOCKED_sig after 100 ps;
    PSDONE <= PSDONE_out_fs when sim_mode_type = '1' else PSDONE_out;
    LOCKED_sig <= LOCKED_sig_fs when sim_mode_type = '1' else locked_out_out;

  INITPROC : process
  begin
    detect_resolution
      (model_name => "DCM"
       );
    if (CLKDV_DIVIDE = 1.5) then
      divide_type <= 3;
    elsif (CLKDV_DIVIDE = 2.0) then
      divide_type <= 4;
    elsif (CLKDV_DIVIDE = 2.5) then
      divide_type <= 5;
    elsif (CLKDV_DIVIDE = 3.0) then
      divide_type <= 6;
    elsif (CLKDV_DIVIDE = 3.5) then
      divide_type <= 7;
    elsif (CLKDV_DIVIDE = 4.0) then
      divide_type <= 8;
    elsif (CLKDV_DIVIDE = 4.5) then
      divide_type <= 9;
    elsif (CLKDV_DIVIDE = 5.0) then
      divide_type <= 10;
    elsif (CLKDV_DIVIDE = 5.5) then
      divide_type <= 11;
    elsif (CLKDV_DIVIDE = 6.0) then
      divide_type <= 12;
    elsif (CLKDV_DIVIDE = 6.5) then
      divide_type <= 13;
    elsif (CLKDV_DIVIDE = 7.0) then
      divide_type <= 14;
    elsif (CLKDV_DIVIDE = 7.5) then
      divide_type <= 15;
    elsif (CLKDV_DIVIDE = 8.0) then
      divide_type <= 16;
    elsif (CLKDV_DIVIDE = 9.0) then
      divide_type <= 18;
    elsif (CLKDV_DIVIDE = 10.0) then
      divide_type <= 20;
    elsif (CLKDV_DIVIDE = 11.0) then
      divide_type <= 22;
    elsif (CLKDV_DIVIDE = 12.0) then
      divide_type <= 24;
    elsif (CLKDV_DIVIDE = 13.0) then
      divide_type <= 26;
    elsif (CLKDV_DIVIDE = 14.0) then
      divide_type <= 28;
    elsif (CLKDV_DIVIDE = 15.0) then
      divide_type <= 30;
    elsif (CLKDV_DIVIDE = 16.0) then
      divide_type <= 32;
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLKDV_DIVIDE",
         EntityName => "DCM",
--         InstanceName => InstancePath,
         GenericValue => CLKDV_DIVIDE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    if ((CLKFX_DIVIDE <= 0) or (32 < CLKFX_DIVIDE)) then
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLKFX_DIVIDE",
         EntityName => "DCM",
--         InstanceName => InstancePath,
         GenericValue => CLKFX_DIVIDE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are 1....32",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;
    if ((CLKFX_MULTIPLY <= 1) or (32 < CLKFX_MULTIPLY)) then
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLKFX_MULTIPLY",
         EntityName => "DCM",
--         InstanceName => InstancePath,
         GenericValue => CLKFX_MULTIPLY,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are 2....32",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;
    case CLKIN_DIVIDE_BY_2 is
      when false => clkin_type <= 0;
      when true => clkin_type <= 1;
      when others =>
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "CLKIN_DIVIDE_BY_2",
           EntityName => "DCM",
--           InstanceName => InstancePath,
           GenericValue => CLKIN_DIVIDE_BY_2,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
    end case;


    if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then
      ps_type <= 0;
    elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then
      ps_type <= 1;
    elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then
      ps_type <= 2;
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLKOUT_PHASE_SHIFT",
         EntityName => "DCM",
--         InstanceName => InstancePath,
         GenericValue => CLKOUT_PHASE_SHIFT,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are NONE, FIXED or VARIABLE",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    if ((CLK_FEEDBACK = "none") or (CLK_FEEDBACK = "NONE")) then
      clkfb_type <= 0;
    elsif ((CLK_FEEDBACK = "1x") or (CLK_FEEDBACK = "1X")) then
      clkfb_type <= 1;
    elsif ((CLK_FEEDBACK = "2x") or (CLK_FEEDBACK = "2X")) then
      clkfb_type <= 2;
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLK_FEEDBACK",
         EntityName => "DCM",
--         InstanceName => InstancePath,
         GenericValue => CLK_FEEDBACK,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are NONE, 1X or 2X",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    if ((DESKEW_ADJUST = "source_synchronous") or (DESKEW_ADJUST = "SOURCE_SYNCHRONOUS")) then
      DESKEW_ADJUST_mode <= 8;
    elsif ((DESKEW_ADJUST = "system_synchronous") or (DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS")) then
      DESKEW_ADJUST_mode <= 11;
    elsif ((DESKEW_ADJUST = "0")) then
      DESKEW_ADJUST_mode <= 0;
    elsif ((DESKEW_ADJUST = "1")) then
      DESKEW_ADJUST_mode <= 1;
    elsif ((DESKEW_ADJUST = "2")) then
      DESKEW_ADJUST_mode <= 2;
    elsif ((DESKEW_ADJUST = "3")) then
      DESKEW_ADJUST_mode <= 3;
    elsif ((DESKEW_ADJUST = "4")) then
      DESKEW_ADJUST_mode <= 4;
    elsif ((DESKEW_ADJUST = "5")) then
      DESKEW_ADJUST_mode <= 5;
    elsif ((DESKEW_ADJUST = "6")) then
      DESKEW_ADJUST_mode <= 6;
    elsif ((DESKEW_ADJUST = "7")) then
      DESKEW_ADJUST_mode <= 7;
    elsif ((DESKEW_ADJUST = "8")) then
      DESKEW_ADJUST_mode <= 8;
    elsif ((DESKEW_ADJUST = "9")) then
      DESKEW_ADJUST_mode <= 9;
    elsif ((DESKEW_ADJUST = "10")) then
      DESKEW_ADJUST_mode <= 10;
    elsif ((DESKEW_ADJUST = "11")) then
      DESKEW_ADJUST_mode <= 11;
    elsif ((DESKEW_ADJUST = "12")) then
      DESKEW_ADJUST_mode <= 12;
    elsif ((DESKEW_ADJUST = "13")) then
      DESKEW_ADJUST_mode <= 13;
    elsif ((DESKEW_ADJUST = "14")) then
      DESKEW_ADJUST_mode <= 14;
    elsif ((DESKEW_ADJUST = "15")) then
      DESKEW_ADJUST_mode <= 15;
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "DESKEW_ADJUST_MODE",
         EntityName => "DCM",
--         InstanceName => InstancePath,
         GenericValue => DESKEW_ADJUST_MODE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 1....15",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    if ((DFS_FREQUENCY_MODE = "high") or (DFS_FREQUENCY_MODE = "HIGH")) then
      dfs_mode_type <= 1;
    elsif ((DFS_FREQUENCY_MODE = "low") or (DFS_FREQUENCY_MODE = "LOW")) then
      dfs_mode_type <= 0;
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "DFS_FREQUENCY_MODE",
         EntityName => "DCM",
--         InstanceName => InstancePath,
         GenericValue => DFS_FREQUENCY_MODE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are HIGH or LOW",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    if ((DLL_FREQUENCY_MODE = "high") or (DLL_FREQUENCY_MODE = "HIGH")) then
      dll_mode_type <= 1;
    elsif ((DLL_FREQUENCY_MODE = "low") or (DLL_FREQUENCY_MODE = "LOW")) then
      dll_mode_type <= 0;
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "DLL_FREQUENCY_MODE",
         EntityName => "DCM",
--         InstanceName => InstancePath,
         GenericValue => DLL_FREQUENCY_MODE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are HIGH or LOW",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    if ((DSS_MODE = "none") or (DSS_MODE = "NONE")) then
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "DSS_MODE",
         EntityName => "DCM",
--         InstanceName => InstancePath,
         GenericValue => DSS_MODE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are NONE",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    case DUTY_CYCLE_CORRECTION is
      when false => clk1x_type <= 0;
      when true => clk1x_type <= 1;
      when others =>
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "DUTY_CYCLE_CORRECTION",
           EntityName => "DCM",
--           InstanceName => InstancePath,
           GenericValue => DUTY_CYCLE_CORRECTION,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
    end case;

    if ((PHASE_SHIFT < -255) or (PHASE_SHIFT > 255)) then
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "PHASE_SHIFT",
         EntityName => "DCM",
--         InstanceName => InstancePath,
         GenericValue => PHASE_SHIFT,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are -255 ... 255",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    period_jitter <= SIM_CLKIN_PERIOD_JITTER;
    cycle_jitter <= SIM_CLKIN_CYCLE_JITTER;
    
    case STARTUP_WAIT is
      when false => null;
      when true => null;
      when others =>
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "STARTUP_WAIT",
           EntityName => "DCM",
--           InstanceName => InstancePath,
           GenericValue => STARTUP_WAIT,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
    end case;

--
-- fx parameters
--    
    gcd <= 1;
    for i in 2 to CLKFX_MULTIPLY loop
      if (((CLKFX_MULTIPLY mod i) = 0) and ((CLKFX_DIVIDE mod i) = 0)) then
        gcd <= i;
      end if;
    end loop;    
    numerator <= CLKFX_MULTIPLY / gcd;
    denominator <= CLKFX_DIVIDE / gcd;          
    wait;
  end process INITPROC;

--
-- input wire delays
--  

safe_model : if (SIM_MODE = "SAFE") generate

     CLKFB_ipd <= CLKFB;
     CLKIN_ipd <= CLKIN;
     DSSEN_ipd <= DSSEN;
     PSCLK_dly <= PSCLK;
     PSEN_dly <= PSEN;
     PSINCDEC_dly <= PSINCDEC;
     RST_ipd <= RST;

  i_clock_divide_by_2 : dcm_clock_divide_by_2
    port map (
      clock => clkin_ipd,
      clock_type => clkin_type,
      rst => rst_ipd,
      clock_out => clkin_div);

  i_max_clkin : dcm_maximum_period_check
    generic map (
      clock_name => "CLKIN",
      maximum_period => MAXPERCLKIN)

    port map (
      clock => clkin_ipd,
      rst => rst_ipd);

  i_max_psclk : dcm_maximum_period_check
    generic map (
      clock_name => "PSCLK",
      maximum_period => MAXPERPSCLK)

    port map (
      clock => psclk_dly,
      rst => rst_ipd);

  i_clkin_lost : dcm_clock_lost
    port map (
      lost  => clkin_lost_out,
      clock => clkin_ipd,
      enable => first_time_locked,
      rst => rst_ipd      
      );

  i_clkfx_lost : dcm_clock_lost
    port map (
      lost  => clkfx_lost_out,
      clock => clkfx_out,
      enable => first_time_locked,
      rst => rst_ipd
      );  

  clkin_ps <= transport clkin_div after ps_delay;  
  
  clkin_fb <= transport (clkin_ps and lock_fb);

  detect_first_time_locked : process
    begin
      if (first_time_locked = false) then
        if (rising_edge(locked_out)) then
          first_time_locked <= true;
        end if;        
      end if;
      wait on locked_out;
  end process detect_first_time_locked;

  set_reset_en_status : process
  begin
    if (rst_ipd = '1') then
      en_status <= false;
    elsif (rising_edge(Locked_sig)) then
      en_status <= true;
    end if;
    wait on rst_ipd, Locked_sig;
  end process set_reset_en_status;    

  gen_clkfb_div_en: process
  begin
    if (rst_ipd = '1') then
      clkfb_div_en <= '0';
    elsif (falling_edge(clkfb_ipd)) then
      if (lock_fb_dly='1' and lock_period='1' and lock_fb = '1' and clkin_ps = '0') then
        clkfb_div_en <= '1';
      end if;
    end if;
    wait on clkfb_ipd, rst_ipd;
  end process  gen_clkfb_div_en;

   gen_clkfb_div: process
  begin  
    if (rst_ipd = '1') then
      clkfb_div <= '0';      
    elsif (rising_edge(clkfb_ipd)) then
      if (clkfb_div_en='1') then
        clkfb_div <= not clkfb_div;      
      end if;
    end if;    
    wait on clkfb_ipd, rst_ipd;
  end process  gen_clkfb_div;

  determine_clkfb_chk: process
  begin
    if (clkfb_type = 2) then
      clkfb_chk <= clkfb_div;
    else 
      clkfb_chk <= clkfb_ipd and lock_fb_dly;
    end if;
    wait on clkfb_ipd, clkfb_div;
  end process  determine_clkfb_chk;

  set_reset_clkin_chkin : process
  begin
    if ((rising_edge(clkin_fb)) or (rising_edge(chk_rst))) then
      if (chk_rst = '1') then
        clkin_chkin <= '0';
      else
        clkin_chkin <= '1';
      end if;
    end if;
    wait on clkin_fb, chk_rst;
  end process set_reset_clkin_chkin;

  set_reset_clkfb_chkin : process
  begin
    if ((rising_edge(clkfb_chk)) or (rising_edge(chk_rst))) then
      if (chk_rst = '1') then
        clkfb_chkin <= '0';
      else
        clkfb_chkin <= '1';
      end if;
    end if;
    wait on clkfb_chk, chk_rst;
  end process set_reset_clkfb_chkin;

  
  chk_rst <= '1' when ((rst_ipd = '1') or (clock_stopped = '1')) else '0';  

  chk_enable <= '1' when ((clkin_chkin = '1') and (clkfb_chkin = '1') and (lock_ps = '1') and (lock_fb_dly = '1') and (lock_fb = '1')) else '0';  

  control_status_bits: process
  begin  
    if ((rst_ipd = '1') or (en_status = false)) then
      ps_overflow_out_ext <= '0';
      clkin_lost_out_ext <= '0';
      clkfx_lost_out_ext <= '0';
    else
      ps_overflow_out_ext <= ps_overflow_out;
      clkin_lost_out_ext <= clkin_lost_out;
      clkfx_lost_out_ext <= clkfx_lost_out;
    end if;
    wait on clkfx_lost_out, clkin_lost_out, en_status, ps_overflow_out, rst_ipd;
  end process  control_status_bits;
  
  determine_period_div : process
    variable clkin_div_edge_previous : time := 0 ps; 
    variable clkin_div_edge_current : time := 0 ps;
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      clkin_div_edge_previous := 0 ps; 
      clkin_div_edge_current := 0 ps;
      period_div <= 0 ps;
    else
      if (rising_edge(clkin_div)) then
        clkin_div_edge_previous := clkin_div_edge_current;
        clkin_div_edge_current := NOW;
        if ((clkin_div_edge_current - clkin_div_edge_previous) <= (1.5 * period_div)) then
          period_div <= clkin_div_edge_current - clkin_div_edge_previous;
        elsif ((period_div = 0 ps) and (clkin_div_edge_previous /= 0 ps)) then
          period_div <= clkin_div_edge_current - clkin_div_edge_previous;      
        end if;          
      end if;    
    end if;
    wait on clkin_div, rst_ipd;
  end process determine_period_div;

  determine_period_ps : process
    variable clkin_ps_edge_previous : time := 0 ps; 
    variable clkin_ps_edge_current : time := 0 ps;    
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      clkin_ps_edge_previous := 0 ps; 
      clkin_ps_edge_current := 0 ps;
      period_ps <= 0 ps;
    else    
      if (rising_edge(clkin_ps)) then
        clkin_ps_edge_previous := clkin_ps_edge_current;
        clkin_ps_edge_current := NOW;
        wait for 0 ps;
        if ((clkin_ps_edge_current - clkin_ps_edge_previous) <= (1.5 * period_ps)) then
          period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous;
        elsif ((period_ps = 0 ps) and (clkin_ps_edge_previous /= 0 ps)) then
          period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous;      
        end if;
      end if;
    end if;
    wait on clkin_ps, rst_ipd;    
  end process determine_period_ps;

  assign_lock_ps_fb : process

  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      lock_fb <= '0';
      lock_ps <= '0';
      lock_ps_dly <= '0';                                            
      lock_fb_dly <= '0';
      lock_fb_dly_tmp <= '0';
    else
      if (rising_edge(clkin_ps)) then
        lock_ps <= lock_period;
        lock_ps_dly <= lock_ps;        
        lock_fb <= lock_ps_dly;            
        lock_fb_dly_tmp <= lock_fb;            
      end if;          
      if (falling_edge(clkin_ps)) then
--         lock_fb_dly <= lock_fb_dly_tmp after (period/4);
         lock_fb_dly <= lock_fb_dly_tmp after (period * 0.75);
      end if;
    end if;
    wait on clkin_ps, rst_ipd;
  end process assign_lock_ps_fb;

  calculate_clkout_delay : process
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      clkout_delay <= 0 ps;
    elsif (fb_delay = 0 ps) then
      clkout_delay <= 0 ps;                
    elsif (period'event or fb_delay'event) then
      clkout_delay <= period - fb_delay;        
    end if;
    wait on period, fb_delay, rst_ipd;
  end process calculate_clkout_delay;

--
--generate master reset signal
--  

  gen_master_rst : process
  begin
    if (rising_edge(clkin_ipd)) then    
      rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst_ipd;    
      rst_reg(1) <= rst_reg(0) and rst_ipd;
      rst_reg(0) <= rst_ipd;
    end if;
    wait on clkin_ipd;     
  end process gen_master_rst;

  check_rst_width : process
    variable Message : line;    
    begin
      if (rst_ipd ='1') then
          rst_flag <= '0';
      end if;
      if (falling_edge(rst_ipd)) then
        if ((rst_reg(2) and rst_reg(1) and rst_reg(0)) = '0') then
          rst_flag <= '1';
          Write ( Message, string'(" Input Error : RST on DCM "));
          Write ( Message, string'(" must be asserted for 3 CLKIN clock cycles. "));          
          assert false report Message.all severity error;
          DEALLOCATE (Message);
        end if;        
      end if;

      wait on rst_ipd;
    end process check_rst_width;

--
--phase shift parameters
--  

  determine_phase_shift : process
    variable Message : line;
    variable  FINE_SHIFT_RANGE : time;
    variable first_time : boolean := true;
    variable ps_in : integer;    
  begin
    if (first_time = true) then
      if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then
        ps_in := 256;      
      elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then
        ps_in := 256 + PHASE_SHIFT;
      elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then
        ps_in := 256 + PHASE_SHIFT;
      end if;
      first_time := false;
    end if;    
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then
        ps_in := 256;      
      elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then
        ps_in := 256 + PHASE_SHIFT;
      elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then
        ps_in := 256 + PHASE_SHIFT;
      else
      end if;
      ps_lock <= '0';
      ps_overflow_out <= '0';
      ps_delay <= 0 ps;
    else
      if (rising_edge (lock_period)) then
        if (ps_type = 1) then
          FINE_SHIFT_RANGE := 10000 ps;
        elsif (ps_type = 2) then
          FINE_SHIFT_RANGE := 5000 ps;
        end if;
        if (PHASE_SHIFT > 0) then
          if (((ps_in * period_orig) / 256) > (period_orig + FINE_SHIFT_RANGE)) then
            Write ( Message, string'(" Function Error : "));
--             Write ( Message, Instancepath );          
            Write ( Message, string'(" Requested Phase Shift = "));

            Write ( Message, string'(" PHASE_SHIFT * PERIOD/256 = "));
            Write ( Message, PHASE_SHIFT);
            Write ( Message, string'(" * "));
            Write ( Message, period_orig / 256);
            Write ( Message, string'(" = "));            
            Write ( Message, (PHASE_SHIFT) * period_orig / 256 );                      
            Write ( Message, string'(" This exceeds the FINE_SHIFT_RANGE of "));            
            Write ( Message, FINE_SHIFT_RANGE);                        
            assert false report Message.all severity error;
            DEALLOCATE (Message);          
          end if;
        elsif (PHASE_SHIFT < 0) then
          if ((period_orig > FINE_SHIFT_RANGE) and ((ps_in * period_orig / 256) < period_orig - FINE_SHIFT_RANGE)) then
            Write ( Message, string'(" Function Error : "));
--            Write ( Message, Instancepath );          
            Write ( Message, string'(" Requested Phase Shift = "));

            Write ( Message, string'(" PHASE_SHIFT * PERIOD/256 = "));
            Write ( Message, PHASE_SHIFT);
            Write ( Message, string'(" * "));
            Write ( Message, period_orig / 256);
            Write ( Message, string'(" = "));            
            Write ( Message, (-PHASE_SHIFT) * period_orig / 256 );                      
            Write ( Message, string'(" This exceeds the FINE_SHIFT_RANGE of "));            
            Write ( Message, FINE_SHIFT_RANGE);                      

            assert false report Message.all severity error;
            DEALLOCATE (Message);                  
          end if;
        end if;
      end if;
      if (rising_edge(lock_period_pulse)) then
        ps_delay <= (ps_in * period_div / 256);        
      end if;      
      if (rising_edge(PSCLK_dly)) then
        if (ps_type = 2) then
          if (psen_dly = '1') then
            if (ps_lock = '1') then
              Write ( Message, string'(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift. "));
              assert false report Message.all severity warning;
              DEALLOCATE (Message);              
            else
              if (psincdec_dly = '1') then
                if (ps_in = 511) then
                  ps_overflow_out <= '1';
                elsif (((ps_in + 1) * period_orig / 256) > period_orig + FINE_SHIFT_RANGE) then
                  ps_overflow_out <= '1';
                else
                  ps_in := ps_in + 1;
                  ps_delay <= (ps_in * period_div / 256);
                  ps_overflow_out <= '0';
                end if;
                ps_lock <= '1';                
              elsif (psincdec_dly = '0') then
                if (ps_in = 1) then
                  ps_overflow_out <= '1';
                elsif ((period_orig > FINE_SHIFT_RANGE) and (((ps_in - 1) * period_orig / 256) < period_orig - FINE_SHIFT_RANGE)) then
                  ps_overflow_out <= '1';
                else
                  ps_in := ps_in - 1;
                  ps_delay <= (ps_in * period_div / 256);
                  ps_overflow_out <= '0';
                end if;
                ps_lock <= '1';                                
              end if;
            end if;
          end if;
        end if;
      end if;          
    end if;
    if (ps_lock_reg'event) then
      ps_lock <= ps_lock_reg;
    end if;
    wait on lock_period, lock_period_pulse, psclk_dly, ps_lock_reg, rst_ipd;
  end process determine_phase_shift;

  determine_psdone_out : process
  begin
    if (rising_edge(ps_lock)) then
      ps_lock_reg <= '1';      
      wait until (rising_edge(clkin_ps));
      wait until (rising_edge(psclk_dly));
      wait until (rising_edge(psclk_dly));
      wait until (rising_edge(psclk_dly));
      psdone_out <= '1';
      wait until (rising_edge(psclk_dly));
      psdone_out <= '0';
      ps_lock_reg <= '0';
    end if;
    wait on ps_lock;
  end process determine_psdone_out;      
  
--
--determine clock period
--    
  determine_clock_period : process
    variable clkin_edge_previous : time := 0 ps; 
    variable clkin_edge_current : time := 0 ps;
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      clkin_period_real(0) <= 0 ps;
      clkin_period_real(1) <= 0 ps;
      clkin_period_real(2) <= 0 ps;
      clkin_edge_previous := 0 ps;      
      clkin_edge_current := 0 ps;      
    elsif (rising_edge(clkin_div)) then
      clkin_edge_previous := clkin_edge_current;
      clkin_edge_current := NOW;
      clkin_period_real(2) <= clkin_period_real(1);
      clkin_period_real(1) <= clkin_period_real(0);      
      if (clkin_edge_previous /= 0 ps) then
	clkin_period_real(0) <= clkin_edge_current - clkin_edge_previous;
      end if;
    end if;      
    if (no_stop'event) then
      clkin_period_real(0) <= clkin_period_real0_temp;
    end if;
    wait on clkin_div, no_stop, rst_ipd;
  end process determine_clock_period;
  
  evaluate_clock_period : process
    variable Message : line;
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      lock_period <= '0';
      clock_stopped <= '1';
      clkin_period_real0_temp <= 0 ps;                        
    else
      if (falling_edge(clkin_div)) then
        if (lock_period = '0') then
          if ((clkin_period_real(0) /= 0 ps ) and (clkin_period_real(0) - cycle_jitter <= clkin_period_real(1)) and (clkin_period_real(1) <= clkin_period_real(0) + cycle_jitter) and (clkin_period_real(1) - cycle_jitter <= clkin_period_real(2)) and (clkin_period_real(2) <= clkin_period_real(1) + cycle_jitter)) then
            lock_period <= '1';
            period_orig <= (clkin_period_real(0) + clkin_period_real(1) + clkin_period_real(2)) / 3;
            period <= clkin_period_real(0);
          end if;
        elsif (lock_period = '1') then
          if (100000000 ns < clkin_period_real(0)) then
            Write ( Message, string'(" Warning : CLKIN stopped toggling on "));
--            Write ( Message, Instancepath );          
            Write ( Message, string'(" exceeds "));
            Write ( Message, string'(" 100 ms "));
            Write ( Message, string'(" Current CLKIN Period = "));
            Write ( Message, clkin_period_real(0));
            assert false report Message.all severity warning;
            DEALLOCATE (Message);
            lock_period <= '0';
            wait until (falling_edge(rst_reg(2)));            
          elsif ((period_orig * 2 < clkin_period_real(0)) and (clock_stopped = '0')) then
              clkin_period_real0_temp <= clkin_period_real(1);            
              no_stop <= not no_stop;
              clock_stopped <= '1';              
          elsif ((clkin_period_real(0) < period_orig - period_jitter) or (period_orig + period_jitter < clkin_period_real(0))) then
            Write ( Message, string'(" Warning : DCM Input Clock Period Jitter "));
--            Write ( Message, Instancepath );          
            Write ( Message, string'(" exceeds "));
            Write ( Message, period_jitter );
            Write ( Message, string'(" Locked CLKIN Period =  "));
            Write ( Message, period_orig );
            Write ( Message, string'(" Current CLKIN Period =  "));
            Write ( Message, clkin_period_real(0) );
            assert false report Message.all severity warning;
            DEALLOCATE (Message);
            lock_period <= '0';
            wait until (falling_edge(rst_reg(2)));                                  
          elsif ((clkin_period_real(0) < clkin_period_real(1) - cycle_jitter) or (clkin_period_real(1) + cycle_jitter < clkin_period_real(0))) then
            Write ( Message, string'(" Warning : DCM Input Clock Cycle Jitter "));
--            Write ( Message, Instancepath );
            Write ( Message, string'(" exceeds "));
            Write ( Message, cycle_jitter );
            Write ( Message, string'(" Previous CLKIN Period =  "));
            Write ( Message, clkin_period_real(1) );
            Write ( Message, string'(" Current CLKIN Period =  "));
            Write ( Message, clkin_period_real(0) );                    
            assert false report Message.all severity warning;
            DEALLOCATE (Message);
            lock_period <= '0';
            wait until (falling_edge(rst_reg(2)));
          else           
            period <= clkin_period_real(0);
            clock_stopped <= '0';            
          end if;
        end if;  
      end if;          
    end if;
    wait on clkin_div, rst_ipd;
  end process evaluate_clock_period;    

  lock_period_dly <= transport lock_period after period/2;

  lock_period_pulse <= '1' when ((lock_period = '1') and (lock_period_dly = '0')) else '0';  
  
--
--determine clock delay
--  
  
  determine_clock_delay : process
    variable delay_edge : time := 0 ps;
    variable temp1 : integer := 0;
    variable temp2 : integer := 0;        
    variable temp : integer := 0;
    variable delay_edge_current : time := 0 ps;    
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      fb_delay <= 0 ps;      
      fb_delay_found <= '0';                        
    else
      if (rising_edge(lock_ps_dly)) then
        if  ((lock_period = '1') and (clkfb_type /= 0)) then
          if (clkfb_type = 1) then
            wait until ((rising_edge(clk0_sig)) or (rst_ipd'event));                    
            delay_edge := NOW;
          elsif (clkfb_type = 2) then
            wait until ((rising_edge(clk2x_sig)) or (rst_ipd'event));
            delay_edge := NOW;
          end if;
          wait until ((rising_edge(clkfb_ipd)) or (rst_ipd'event));
          temp1 := ((NOW*1) - (delay_edge*1))/ (1 ps);
          temp2 := (period_orig * 1)/ (1 ps);
          temp := temp1 mod temp2;
          fb_delay <= temp * 1 ps;
          fb_delay_found <= '1';          
        end if;
      end if;
    end if;
    wait on lock_ps_dly, rst_ipd;
  end process determine_clock_delay;
--
--  determine feedback lock
--  
  GEN_CLKFB_WINDOW : process
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      clkfb_window <= '0';  
    else
      if (rising_edge(clkfb_chk)) then
        wait for 0 ps;
        clkfb_window <= '1';
        wait for cycle_jitter;        
        clkfb_window <= '0';
      end if;          
    end if;      
    wait on clkfb_chk, rst_ipd;
  end process GEN_CLKFB_WINDOW;

  GEN_CLKIN_WINDOW : process
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      clkin_window <= '0';
    else
      if (rising_edge(clkin_fb)) then
        wait for 0 ps;
        clkin_window <= '1';
        wait for cycle_jitter;        
        clkin_window <= '0';
      end if;          
    end if;      
    wait on clkin_fb, rst_ipd;
  end process GEN_CLKIN_WINDOW;  

  set_reset_lock_clkin : process
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      lock_clkin <= '0';                  
    else
      if (rising_edge(clkin_fb)) then
        wait for 1 ps;
        if (((clkfb_window = '1') and (fb_delay_found = '1')) or ((clkin_lost_out = '1') and (lock_out(0) = '1'))) then
          lock_clkin <= '1';
        else
          if (chk_enable = '1' and ps_lock = '0') then
            lock_clkin <= '0';
          end if;
        end if;
      end if;          
    end if;
    wait on clkin_fb, rst_ipd;
  end process set_reset_lock_clkin;

  set_reset_lock_clkfb : process
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      lock_clkfb <= '0';                  
    else
      if (rising_edge(clkfb_chk)) then
        wait for 1 ps;
        if (((clkin_window = '1') and (fb_delay_found = '1')) or ((clkin_lost_out = '1') and (lock_out(0) = '1')))then
          lock_clkfb <= '1';
        else
          if (chk_enable = '1' and ps_lock = '0') then          
            lock_clkfb <= '0';
          end if;
        end if;
      end if;          
    end if;
    wait on clkfb_chk, rst_ipd;
  end process set_reset_lock_clkfb;

  assign_lock_delay : process
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      lock_delay <= '0';          
    else
      if (falling_edge(clkin_fb)) then
        lock_delay <= lock_clkin or lock_clkfb;
      end if;
    end if;
    wait on clkin_fb, rst_ipd;    
  end process;

--
--generate lock signal
--  
  
  generate_lock : process(clkin_ps, rst_ipd)
  begin
    if (rst_ipd='1') then
      lock_out <= "00";
      locked_out <= '0';
      lock_out1_neg <= '0';
    elsif (rising_edge(clkin_ps)) then
        if (clkfb_type = 0) then
          lock_out(0) <= lock_period;
        else
          lock_out(0) <= lock_period and lock_delay and lock_fb;
        end if;
        lock_out(1) <= lock_out(0);
        locked_out <= lock_out(1);
    elsif (falling_edge(clkin_ps)) then
        lock_out1_neg <= lock_out(1);
    end if;
  end process generate_lock;

--
--generate the clk1x_out
--  
  
  gen_clk1x : process( clkin_ps, rst_ipd)
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      clk0_out <= '0';
    elsif (clkin_ps'event) then
      if (clkin_ps = '1' ) then
        if ((clk1x_type = 1) and (lock_out(0) = '1')) then
          clk0_out <= '1', '0' after period/2;
        else
          clk0_out <= '1';
        end if;
      else
        if ((clkin_ps = '0') and ((((clk1x_type = 1) and (lock_out(0) = '1')) = false) or ((lock_out(0) = '1') and (lock_out(1) = '0')))) then                
          clk0_out <= '0';
        end if;
      end if;          
    end if;
  end process gen_clk1x;

--
--generate the clk2x_out
--    

  gen_clk2x : process
  begin
    if (rising_edge(rst_ipd) or (rst_ipd = '1')) then
      clk2x_out <= '0';
    else  
      if (rising_edge(clkin_ps) or falling_edge(clkin_ps)) then
        clk2x_out <= '1';
        wait for (period / 4);
        clk2x_out <= '0';
      end if;
    end if;
    wait on clkin_ps, rst_ipd;
  end process gen_clk2x;
  
-- 
--generate the clkdv_out
-- 

  gen_clkdv : process (clkin_ps, rst_ipd)
  begin
    if (rst_ipd='1') then
       clkdv_out <= '0';
       clkdv_cnt <= 0;
    elsif ((rising_edge(clkin_ps)) or (falling_edge(clkin_ps))) then
      if (lock_out1_neg = '1') then
         if (clkdv_cnt >= divide_type -1) then
           clkdv_cnt <= 0;
         else
           clkdv_cnt <= clkdv_cnt + 1;
         end if;

         if (clkdv_cnt < divide_type /2) then
            clkdv_out <= '1';
         else
           if ( ((divide_type rem (2)) > 0) and (dll_mode_type = 0)) then
             clkdv_out <= '0' after (period/4);
           else
            clkdv_out <= '0';
           end if;
         end if;
      end if;
    end if;
  end process;

--
-- generate fx output signal
--
  
  calculate_period_fx : process
  begin
    if (lock_period = '1') then
      period_fx <= (period * denominator) / (numerator * 2);
      remain_fx <= (((period/1 ps) * denominator) mod (numerator * 2)) * 1 ps;        
    end if;
    wait on lock_period, period, denominator, numerator;
  end process calculate_period_fx;

  generate_clkfx : process
    variable temp : integer;
  begin
    if (rst_ipd = '1') then
      clkfx_out <= '0';
    elsif (clkin_lost_out_ext = '1') then
       wait until (rising_edge(rst_ipd));
       clkfx_out <= '0';            
      wait until (falling_edge(rst_reg(2)));              
    elsif (rising_edge(clkin_ps)) then
      if (lock_out(1) = '1') then
        clkfx_out <= '1';
        temp := numerator * 2 - 1 - 1;
        for p in 0 to temp loop
          wait for (period_fx);
          clkfx_out <= not clkfx_out;
        end loop;
        if (period_fx > (period / 2)) then
          wait for (period_fx - (period / 2));
        end if;
      end if;
      if (clkin_lost_out_ext = '1') then
        wait until (rising_edge(rst_ipd));
        clkfx_out <= '0';      
        wait until (falling_edge(rst_reg(2)));
      end if;      
    end if;
    wait on clkin_lost_out_ext, clkin_ps, rst_ipd, rst_reg(2);
  end process generate_clkfx;


--
--generate all output signal
--

  schedule_p1_outputs : process
  begin
    if (CLK0_out'event) then
      if (clkfb_type /= 0) then
        CLK0_out_o <= transport CLK0_out after clkout_delay;
        clk0_sig <= transport CLK0_out after clkout_delay; 
      end if;                 
      if ((dll_mode_type = 0) and (clkfb_type /= 0)) then
        CLK90_out_o <= transport clk0_out after (clkout_delay + period / 4);
      end if;
    end if;

    if (CLK0_out'event or rst_ipd'event)then
      if (rst_ipd = '1') then
        CLK180_out_o <= '0';
        CLK270_out_o <= '0';
      elsif (CLK0_out'event) then 
        if (clkfb_type /= 0) then        
          CLK180_out_o <= transport (not clk0_out) after clkout_delay;
        end if;
        if ((dll_mode_type = 0) and (clkfb_type /= 0)) then        
          CLK270_out_o <= transport (not clk0_out) after (clkout_delay + period/4);
        end if;
      end if;
    end if;

    if (clk2x_out'event) then
      if ((dll_mode_type = 0) and (clkfb_type /= 0)) then
        CLK2X_out_o <= transport clk2x_out after clkout_delay;
        clk2x_sig <= transport clk2x_out after clkout_delay;  
      end if;
    end if;

    if (CLK2X_out'event or rst_ipd'event) then
      if (rst_ipd = '1') then
        CLK2X180_out_o <= '0';
      elsif (CLK2X_out'event) then
        if ((dll_mode_type = 0) and (clkfb_type /= 0)) then
          CLK2X180_out_o <= transport (not CLK2X_out) after clkout_delay;  
        end if;
      end if;
    end if;

    if (clkdv_out'event) then
      if (clkfb_type /= 0) then                
        CLKDV_out_o <= transport clkdv_out after clkout_delay;
      end if;
    end if;

    if (clkfx_out'event or rst_ipd'event) then
      if (rst_ipd = '1') then
        CLKFX_out_o <= '0';
      elsif (clkfx_out'event) then
        CLKFX_out_o <= transport clkfx_out after clkout_delay;                          
      end if;
    end if;

    if (clkfx_out'event or (rising_edge(rst_ipd)) or first_time_locked'event or locked_out'event) then
      if ((rst_ipd = '1') or (not first_time_locked)) then
        CLKFX180_out_o <= '0';
      else
        CLKFX180_out_o <= transport (not clkfx_out) after clkout_delay;  
      end if;
    end if;

   wait on clk0_out, clk2x_out, clkdv_out, clkfx_out, first_time_locked, locked_out, rst_ipd;
   end process;
 
  assign_status_out : process
    begin
      if (rst_ipd = '1') then
        status_out(0) <= '0';
        status_out(1) <= '0';
        status_out(2) <= '0';
      elsif (ps_overflow_out_ext'event) then
        status_out(0) <= ps_overflow_out_ext;
      elsif (clkin_lost_out_ext'event) then
        status_out(1) <= clkin_lost_out_ext;
      elsif (clkfx_lost_out_ext'event) then
        status_out(2) <= clkfx_lost_out_ext;
      end if;
      wait on clkin_lost_out_ext, clkfx_lost_out_ext, ps_overflow_out_ext, rst_ipd;
    end process assign_status_out;

   locked_out_out <= 'X' when rst_flag = '1' else locked_out;




end generate;

fast_model : if (SIM_MODE = "FAST") generate


  CONV_P : process
    variable con_line : line;
    variable tmpvalue : real;
    variable skipspace : character;
  begin
    write (con_line, CLKFX_DIVIDE);
    write (con_line, string'(".0 "));
    write (con_line, CLKFX_MULTIPLY);
    write (con_line, string'(".0 ")); 
    write (con_line, PHASE_SHIFT);

    read (con_line, tmpvalue);
    clkfx_divide_real <= tmpvalue;
    read (con_line, skipspace);
    read (con_line, tmpvalue);
    clkfx_multiply_real <= tmpvalue;
    read (con_line, skipspace);
    read (con_line, tmpvalue);
    phase_shift_real <= tmpvalue;
    wait;
  end process;

   CLK0_out_ofs <= CLK0_out_fs;
   CLK180_out_ofs <= CLK180_out_fs;
   CLK270_out_ofs <= CLK270_out_fs;
   CLK2X_out_ofs <= CLK2X_out_fs;
   CLK2X180_out_ofs <= CLK2X180_out_fs;
   CLK90_out_ofs <= CLK90_out_fs;
   CLKDV_out_ofs <= CLKDV_out_fs;
   CLKFX_out_ofs <= CLKFX_out_fs;
   CLKFX180_out_ofs <= CLKFX180_out_fs;
   LOCKED_sig_fs <= LOCKED_out_fs;

  feedback_dcm : process
  begin
      fbsync <= '0';
      wait until (RST='0');
      wait until (period_updated='1');
      wait until (rising_edge(CLKFB));
      delay_time <= NOW - start_time;
      wait until (rising_edge(CLKIN));
      wait for (((12*clk_period)-(delay_time)));
      fbsync <= '1';
      wait until (RST='1');
   end process;

  main_dcm : process
      variable clkin_time1, clkin_time2 : time;
      variable period_clkin, tmpshift : delay_length;
      variable rst_tmp1 : std_ulogic := '0';
  begin
      pos_shift(0) <= '0';
      neg_shift(0) <= '0';
      align  <= '0';
      LOCKED_out_fs <= '0';
      period_updated <= '0';
      clkin_cnt_en <= '0';
      CLK0_out_fs <= '0';
      CLK90_out_fs <= '0';
      CLK180_out_fs <= '0';
      CLK270_out_fs <= '0';
      CLK2X_out_fs <= '0';
      CLK2X180_out_fs <= '0';
      rst_tmp1 := '1';
      rst_tmp <= rst_tmp1;
      wait until (RST='0' and rst_done_fx='1' and rst_done_dv='1');
      rst_tmp <= '0';
      wait until (rising_edge(CLKIN));
      clkin_time1 := NOW;
      wait until (rising_edge(CLKIN));
      clkin_time2 := NOW;
      period_clkin := clkin_time2 -  clkin_time1;
      
      clk_period <=  period_clkin*0.25;
      clkfx_period <= (period_clkin*clkfx_divide_real)/(2.0*clkfx_multiply_real);
      shift_ammount <= ((period_clkin)/256.0);
      clkdv_period <= ((period_clkin*CLKDV_DIVIDE)/2.0);


      wait until (rising_edge(CLKIN));
      period_updated <= '1';
      start_time <= NOW;
      for i in  1 to 6 loop
         CLK0_out_fs <=  not CLK0_out_fs;
         CLK2X_out_fs <=  not CLK2X_out_fs;
         wait for clk_period;
         CLK2X_out_fs <=  not CLK2X_out_fs;
         wait for clk_period;
      end loop;
      for i in  1 to 6 loop
          CLK0_out_fs <=  not CLK0_out_fs;
         CLK2X_out_fs <=  not CLK2X_out_fs;
         wait for clk_period;
         CLK2X_out_fs <=  not CLK2X_out_fs;
         wait for clk_period;
      end loop;
      if (clkfb_type /= 0) then
         if (fbsync='0') then
            wait until (fbsync='1');
         end if;
      end if;
      if (ps_type /= 0) then
        if (PHASE_SHIFT > 0) then
           tmpshift := (period_clkin*phase_shift_real)/256.0;
          wait for tmpshift;
        elsif (PHASE_SHIFT < 0) then
           tmpshift :=(period_clkin)-((period_clkin*phase_shift_real)/256.0);
          wait for  tmpshift;
        end if;
      end if;
      align <= '1';
      CLK0_out_fs <=  not CLK0_out_fs;
      CLK2X_out_fs <=  not CLK2X_out_fs;
      wait for (clk_period);
      CLK90_out_fs <=  not CLK90_out_fs;
      CLK2X_out_fs <=  not CLK2X_out_fs;
      CLK2X180_out_fs <=  not CLK2X180_out_fs;
      wait for (Clk_period);
      for i in 1 to 7 loop
         CLK0_out_fs <=  not CLK0_out_fs;
         CLK180_out_fs <=  not CLK180_out_fs;
         CLK2X_out_fs <=  not CLK2X_out_fs;
         CLK2X180_out_fs <=  not CLK2X180_out_fs;
         wait for (clk_period);
         CLK90_out_fs <=  not CLK90_out_fs;
         CLK2X_out_fs <=  not CLK2X_out_fs;
         CLK2X180_out_fs <=  not CLK2X180_out_fs;
         CLK270_out_fs <=  not CLK270_out_fs;
         wait for (clk_period);
      end loop;
      LOCKED_out_fs <= '1';
      clkin_cnt_en <= '1';
      while (RST = '0') loop
         CLK0_out_fs <=  not CLK0_out_fs;
         CLK180_out_fs <=  not CLK180_out_fs;
         CLK2X_out_fs <=  not CLK2X_out_fs;
         CLK2X180_out_fs <=  not CLK2X180_out_fs;
         wait for (clk_period);
         CLK90_out_fs <=  not CLK90_out_fs;
         CLK270_out_fs <=  not CLK270_out_fs;
         CLK2X_out_fs <=  not CLK2X_out_fs;
         CLK2X180_out_fs <=  not CLK2X180_out_fs;
         wait for (clk_period);
         CLK0_out_fs <=  not CLK0_out_fs;
         CLK180_out_fs <=  not CLK180_out_fs;
         CLK2X_out_fs <=  not CLK2X_out_fs;
         CLK2X180_out_fs <=  not CLK2X180_out_fs;
         wait for (clk_period);
         CLK90_out_fs <=  not CLK90_out_fs;
         CLK270_out_fs <=  not CLK270_out_fs;
         CLK2X_out_fs <=  not CLK2X_out_fs;
         CLK2X180_out_fs <=  not CLK2X180_out_fs;
         if (pos_shift_st(0)='1' and pos_shift(0)='0') then
           wait for ((clk_period)+shift_ammount);
            pos_shift(0) <= '1';
         elsif (neg_shift_st(0)='1' and neg_shift(0)='0') then
           wait for ((clk_period)-shift_ammount);
            neg_shift(0) <= '1';
         else
           if (pos_shift_st(0)='0') then
               pos_shift(0) <= '0';
           end if;
           if (neg_shift_st(0)='0') then
              neg_shift(0) <= '0';
           end if;
           wait for (clk_period);
         end if;
         if (clkin_error='1') then
           wait until (RST = '1');
         end if;
      end loop;
   end process;

   clkfdcm : process
   begin
      pos_shift(1) <= '0';
      neg_shift(1) <= '0';
      CLKFX_out_fs <= '0';
      CLKFX180_out_fs <= '0';
      rst_done_fx <= '1';
--      wait until (RST='0');
      wait until (rst_tmp = '0');
      wait until (LOCKED_out_fs='1');
      rst_done_fx <= '0';
      CLKFX_out_fs <= '1';
      CLKFX180_out_fs <= '0';
      while (rst_tmp = '0' and RST='0') loop
         wait for (clkfx_period);
         CLKFX_out_fs <=  not CLKFX_out_fs;
         CLKFX180_out_fs <=  not CLKFX180_out_fs;
         if (pos_shift_st(1)='1' and pos_shift(1)='0')  then
           wait for ((clkfx_period) + shift_ammount);
            pos_shift(1) <= '1';
         elsif (neg_shift_st(1)='1' and neg_shift(1)='0')  then
            wait for ((clkfx_period)-shift_ammount);
            neg_shift(1) <= '1';
         else
           if (pos_shift_st(1)='0') then
              pos_shift(1) <= '0';
           end if;
           if (neg_shift_st(1)='0') then
              neg_shift(1) <= '0';
           end if;
           wait for clkfx_period;
         end if;
         CLKFX_out_fs <=  not CLKFX_out_fs;
         CLKFX180_out_fs <=  not CLKFX180_out_fs;
         if (clkin_error='1') then
           wait until (RST = '1');
         end if;
      end loop;
   end process;

   clkdv_dcm : process
   begin
      pos_shift(2) <= '0';
      neg_shift(2) <= '0';
      CLKDV_out_fs <= '0';
      rst_done_dv <= '1';
--      wait until (RST='0');
      wait until (rst_tmp = '0');
      wait until (LOCKED_out_fs='1');
      rst_done_dv <= '0';
      CLKDV_out_fs <=  not CLKDV_out_fs;
      while (rst_tmp = '0' and RST = '0') loop
         if (pos_shift_st(2)='1' and pos_shift(2)='0') then
           wait for (clkdv_period+shift_ammount);
            pos_shift(2) <= '1';
         elsif (neg_shift_st(2)='1' and neg_shift(2)='0') then
           wait for (clkdv_period-shift_ammount);
            neg_shift(2) <= '1';
         else
            if (pos_shift_st(2)='0') then
                pos_shift(2) <= '0';
            end if;
            if (neg_shift_st(2)='0') then
                neg_shift(2) <= '0';
            end if;
            wait for (clkdv_period);
         end if;
         CLKDV_out_fs <=  not CLKDV_out_fs;
         if (clkin_error='1') then
           wait until (RST='1');
         end if;
      end loop;
   end process;

   dps_dcm : process (PSCLK)
      variable shift : integer :=0;
   begin
    if (PSCLK'event and PSCLK='1') then
      PSDONE_out_fs <= '0';
      if (ps_type=2) then
        if (PSEN = '1') then 
           if (pos_shift /= "000" or neg_shift /= "000") then
             assert false report
               "Warning : Please wait for PSDONE signal before adjusting the Phase Shift. "
               severity warning;
           else
              if (PSINCDEC = '1' and pos_shift="000") then 
                pos_shift_st <= "111";
                shift := shift + 1;
                if (shift >256) then
                  STATUS_out_fs(0) <= '1';
                else
                  STATUS_out_fs(0) <= '0';
                end if;
              elsif (PSINCDEC = '0' and neg_shift="000") then 
                neg_shift_st <= "111";
                shift := shift - 1;
                if (shift < -256) then
                   STATUS_out_fs(0) <= '1';
                else
                   STATUS_out_fs(0) <= '0';
                end if;
              end if;
           end if;
        end if;   
        end if;
        if ( pos_shift="111") then
             pos_shift_st <= "000";
             PSDONE_out_fs <= '1';
        else if ( neg_shift="111") then
             neg_shift_st <= "000";
             PSDONE_out_fs <= '1';
        end if;
      end if;
   end if;
   end process; 

--   STATUS(0) <= shift(8);

   process (CLKIN)
   begin
     if (CLKIN'event and CLKIN = '1') then
        if (RST = '1') then
           clkin_cnt <= 0;
        else
           if (clkin_cnt_en ='1') then
               if (clkin_cnt = 3) then
                   clkin_cnt <= 0;
               else
                  clkin_cnt <= clkin_cnt + 1;
               end if;
           end if;
        end if;
     end if;
   end process;
   

   status_dcm : process
   begin
      if (RST='1') then 
         old_clkin_cnt <= 0;
          clkin_error <= '0';
      else
--      elsif (CLK0_out'event and CLK0_out='1') then 
         wait until (rising_edge(CLK0_out));
         if (clkin_cnt_en= '1') then 
              clkin_error <= '0' after 1 ps ;
             wait until (rising_edge(CLK0_out));
             if (clkin_cnt = old_clkin_cnt) then 
           assert FALSE report
         "Error: This DCM simulation does not support the stopping of CLKIN. Please use the standard DCM model to properly view this behavior. All DCM outputs will be suspended until the DCM is reset."
           severity error;
                 clkin_error <= '1';
                 wait until (RST='1');
             else
                old_clkin_cnt <= clkin_cnt;
             end if;
         end if;
     end if;
  end process;


end generate;



end DCM_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/dcm_sp.vhd,v 1.10.16.5 2008/07/17 23:35:09 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Digital Clock Manager
-- /___/   /\     Filename : DCM_SP.vhd
-- \   \  /  \    Timestamp : Fri Jun 18 10:57:08 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/06/06 - Initial version.
--    05/09/06 - Add clkin_ps_mkup and clkin_ps_mkup_win for phase shifting (CR 229789).
--    06/14/06 - Add period_int2 and period_int3 for multiple cycle phase shifting (CR 233283).
--        07/21/06 - Change range of variable phase shifting to +/- integer of 20*(Period-3ns).
--               Give warning not support initial phase shifting for variable phase shifting.
--               (CR 235216).
--    09/22/06 - Add lock_period and lock_fb to clkfb_div block (CR 418722).
--    12/19/06 - Add clkfb_div_en for clkfb2x divider (CR431210).
--    04/06/07 - Enable the clock out in clock low time after reset in model
--               clock_divide_by_2  (CR 437471).
--    07/10/07 - Remove modulaton of ps_delay_md for none and fixed delay type (CR441155)
--    08/29/07 - Change delay of lock_fb_dly to 0.75*period, same as verilog (CR447628).
--    01/22/08 - Add () to ps_in * period_in of ps_delay_md calculation (CR466293)
--    02/21/08 - Align clk2x to both clk0 pos and neg edges. (CR467858).
--    03/01/08 - Disable alignment of clkfb and clkin_fb check when ps_lock high (CR468893).
--    03/20/08 - Not check clock lost when negative edge period smaller than positive
--               edge period in dcm_adv_clock_lost module (CR469499).
--             - always generate clk2x with even duty cycle regardless CLKIN duty cycle.(CR467858).
--             - Remove -- from LOCKED <= for unisim model. (CR470138).
--    05/13/08 - Change min input clock freq from 1.0Mhz to 0.2Mhz (CR467770)
--    07/16/08 - remove condition for lock_out[0] when 2x feedback (CR476637).
-- End Revision


----- dcm_sp_clock_divide_by_2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity dcm_sp_clock_divide_by_2 is
  port(
    clock_out : out std_ulogic := '0';

    clock : in std_ulogic;
    clock_type : in integer;
    rst : in std_ulogic
    );
end dcm_sp_clock_divide_by_2;

architecture dcm_sp_clock_divide_by_2_V of dcm_sp_clock_divide_by_2 is
  signal clock_div2 : std_ulogic := '0';
  signal rst_reg : std_logic_vector(2 downto 0);
  signal clk_src : std_ulogic;
begin

  CLKIN_DIVIDER : process
  begin
    if (rising_edge(clock)) then
      clock_div2 <= not clock_div2;
    end if;
    wait on clock;
  end process CLKIN_DIVIDER;

  gen_reset : process
  begin
    if (rising_edge(clock)) then      
      rst_reg(0) <= rst;
      rst_reg(1) <= rst_reg(0) and rst;
      rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst;
    end if;      
    wait on clock;    
  end process gen_reset;

  clk_src <= clock_div2 when (clock_type = 1) else clock;

  assign_clkout : process
  begin
    if (rst = '0') then
      clock_out <= clk_src;
    elsif (rst = '1') then
      clock_out <= '0';
      wait until falling_edge(rst_reg(2));
      if (clk_src = '1') then
         wait until falling_edge(clk_src);
      end if;
    end if;
    wait on clk_src, rst, rst_reg;
  end process assign_clkout;
end dcm_sp_clock_divide_by_2_V;

----- dcm_sp_maximum_period_check  -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;

library STD;
use STD.TEXTIO.all;

entity dcm_sp_maximum_period_check is
  generic (
    InstancePath : string := "*";

    clock_name : string := "";
    maximum_period : time);
  port(
    clock : in std_ulogic;
    rst : in std_ulogic
    );
end dcm_sp_maximum_period_check;

architecture dcm_sp_maximum_period_check_V of dcm_sp_maximum_period_check is
begin

  MAX_PERIOD_CHECKER : process
    variable clock_edge_previous : time := 0 ps;
    variable clock_edge_current : time := 0 ps;
    variable clock_period : time := 0 ps;
    variable Message : line;
  begin

   if (rising_edge(clock)) then
    clock_edge_previous := clock_edge_current;
    clock_edge_current := NOW;

    if (clock_edge_previous > 0 ps) then
      clock_period := clock_edge_current - clock_edge_previous;
    end if;

    if (clock_period > maximum_period and  rst = '0') then
      Write ( Message, string'(" Warning : Input Clock Period of "));
      Write ( Message, clock_period );
      Write ( Message, string'(" on the ") );
      Write ( Message, clock_name );      
      Write ( Message, string'(" port ") );      
      Write ( Message, string'(" of DCM_SP instance ") );
      Write ( Message, string'(" exceeds allowed value of ") );
      Write ( Message, maximum_period );
      Write ( Message, string'(" at simulation time ") );
      Write ( Message, clock_edge_current );
      Write ( Message, '.' & LF );
      assert false report Message.all severity warning;
      DEALLOCATE (Message);
    end if;
   end if;
    wait on clock;
  end process MAX_PERIOD_CHECKER;
end dcm_sp_maximum_period_check_V;

----- dcm_sp_clock_lost  -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity dcm_sp_clock_lost is
  port(
    lost : out std_ulogic := '0';

    clock : in std_ulogic;
    enable : in boolean := false;
    rst :  in std_ulogic    
    );
end dcm_sp_clock_lost;

architecture dcm_sp_clock_lost_V of dcm_sp_clock_lost is
  signal period : time := 0 ps;
  signal period_neg : time := 0 ps;
  signal period_tmp_win : time := 0 ps;
  signal period_neg_tmp_win : time := 0 ps;
  signal period_chk_win : time := 0 ps;
  signal lost_r : std_ulogic := '0';
  signal lost_f : std_ulogic := '0';
  signal lost_sig : std_ulogic := '0';  
  signal clock_negedge, clock_posedge : integer := 0;
  signal clock_low, clock_high : integer := 0;
  signal clock_second_pos, clock_second_neg : integer := 0;
begin
  determine_period : process(clock,rst)
    variable clock_edge_previous : time := 0 ps;
    variable clock_edge_current : time := 0 ps;
    variable period_tmp : time := 0 ps;
  begin
      if (rst = '1') then
        period <= 0 ps;
      elsif (rising_edge(clock)) then
        clock_edge_previous := clock_edge_current;
        clock_edge_current := NOW;
        period_tmp := clock_edge_current - clock_edge_previous;
        if (period /= 0 ps and (period_tmp <= period_tmp_win)) then
          period <= period_tmp;
        elsif (period /= 0 ps and (period_tmp > period_tmp_win)) then
          period <= 0 ps;
        elsif ((period = 0 ps) and (clock_edge_previous /= 0 ps) and (clock_second_pos = 1)) then
          period <= period_tmp;
        end if;
      end if;
  end process determine_period;
                                                                                  
  period_15_p : process(period) begin
     period_tmp_win <= 1.5 * period;
     period_chk_win <= (period * 9.1) / 10;
  end process;

  determine_period_neg : process(clock,rst)
    variable clock_edge_neg_previous : time := 0 ps;
    variable clock_edge_neg_current : time := 0 ps;
    variable period_neg_tmp : time := 0 ps;
  begin
      if (rst = '1') then
        period_neg <= 0 ps;
      elsif (falling_edge(clock)) then
        clock_edge_neg_previous := clock_edge_neg_current;
        clock_edge_neg_current := NOW;
        period_neg_tmp := clock_edge_neg_current - clock_edge_neg_previous;
        if (period_neg /= 0 ps and (period_neg_tmp <= period_neg_tmp_win)) then
          period_neg <= period_neg_tmp;
        elsif (period_neg /= 0 ps and (period_neg_tmp > period_neg_tmp_win)) then
          period_neg <= 0 ps;
        elsif ((period_neg = 0 ps) and (clock_edge_neg_previous /= 0 ps) and (clock_second_neg = 1)) then
          period_neg <= period_neg_tmp;
        end if;
      end if;
  end process determine_period_neg;
                                                                                  
  period_15_neg_p : process(period_neg) begin
     period_neg_tmp_win <= 1.5 * period_neg;
  end process;


  CLOCK_LOST_CHECKER : process(clock, rst)
  begin
      if (rst = '1') then
        clock_low <= 0;
        clock_high <= 0;
        clock_posedge <= 0;              
        clock_negedge <= 0;
      else
        if (rising_edge(clock)) then
          clock_low <= 0;
          clock_high <= 1;
          clock_posedge <= 0;              
          clock_negedge <= 1;
        end if;
        if (falling_edge(clock)) then
          clock_high <= 0;
          clock_low <= 1;
          clock_posedge <= 1;
          clock_negedge <= 0;
        end if;
      end if;
  end process CLOCK_LOST_CHECKER;    

  CLOCK_SECOND_P : process(clock, rst)
    begin
      if (rst = '1') then
        clock_second_pos <= 0;
        clock_second_neg <= 0;
    else
      if (rising_edge(clock)) then
        clock_second_pos <= 1;
      end if;
      if (falling_edge(clock)) then
          clock_second_neg <= 1;
      end if;
    end if;
  end process CLOCK_SECOND_P;

  SET_RESET_LOST_R : process
    begin
    if (rst = '1') then
      lost_r <= '0';
    else
      if ((enable = true) and (clock_second_pos = 1))then
        if (rising_edge(clock)) then
          wait for 1 ps;                      
          if (period /= 0 ps) then
            lost_r <= '0';        
          end if;
          wait for (period_chk_win);
          if ((clock_low /= 1) and (clock_posedge /= 1) and (rst = '0')) then
            lost_r <= '1';
          end if;
        end if;
      end if;
    end if;
    wait on clock, rst;    
  end process SET_RESET_LOST_R;

  SET_RESET_LOST_F : process
    begin
      if (rst = '1') then
        lost_f <= '0';
      else
        if ((enable = true) and (clock_second_neg = 1))then
          if (falling_edge(clock)) then
            if (period /= 0 ps) then      
              lost_f <= '0';
            end if;
            wait for (period_chk_win);
            if ((clock_high /= 1) and (clock_negedge /= 1) and (rst = '0') and (period <= period_neg) ) then
              lost_f <= '1';
            end if;      
          end if;        
        end if;
      end if;
    wait on clock, rst;    
  end process SET_RESET_LOST_F;      

  assign_lost : process(lost_r, lost_f)
    begin
      if (enable = true) then
        if (lost_r'event) then
          lost <= lost_r;
        end if;
        if (lost_f'event) then
          lost <= lost_f;
        end if;
      end if;      
    end process assign_lost;
end dcm_sp_clock_lost_V;


----- CELL DCM_SP  -----
library IEEE;
use IEEE.std_logic_1164.all;





library STD;
use STD.TEXTIO.all;

library unisim;
use unisim.VPKG.all;

entity DCM_SP is
  generic (
    TimingChecksOn : boolean := true;
    InstancePath : string := "*";
    Xon : boolean := true;
    MsgOn : boolean := false;
    CLKDV_DIVIDE : real := 2.0;
    CLKFX_DIVIDE : integer := 1;
    CLKFX_MULTIPLY : integer := 4;
    CLKIN_DIVIDE_BY_2 : boolean := false;
    CLKIN_PERIOD : real := 10.0;                         --non-simulatable
    CLKOUT_PHASE_SHIFT : string := "NONE";
    CLK_FEEDBACK : string := "1X";
    DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";     --non-simulatable
    DFS_FREQUENCY_MODE : string := "LOW";
    DLL_FREQUENCY_MODE : string := "LOW";
    DSS_MODE : string := "NONE";                        --non-simulatable
    DUTY_CYCLE_CORRECTION : boolean := true;
    FACTORY_JF : bit_vector := X"C080";                 --non-simulatable


    PHASE_SHIFT : integer := 0;


    STARTUP_WAIT : boolean := false                     --non-simulatable
    );

  port (
    CLK0 : out std_ulogic := '0';
    CLK180 : out std_ulogic := '0';
    CLK270 : out std_ulogic := '0';
    CLK2X : out std_ulogic := '0';
    CLK2X180 : out std_ulogic := '0';
    CLK90 : out std_ulogic := '0';
    CLKDV : out std_ulogic := '0';
    CLKFX : out std_ulogic := '0';
    CLKFX180 : out std_ulogic := '0';
    LOCKED : out std_ulogic := '0';
    PSDONE : out std_ulogic := '0';
    STATUS : out std_logic_vector(7 downto 0) := "00000000";
    
    CLKFB : in std_ulogic := '0';
    CLKIN : in std_ulogic := '0';
    DSSEN : in std_ulogic := '0';
    PSCLK : in std_ulogic := '0';
    PSEN : in std_ulogic := '0';
    PSINCDEC : in std_ulogic := '0';
    RST : in std_ulogic := '0'
    );



end DCM_SP;

architecture DCM_SP_V of DCM_SP is
  

  component dcm_sp_clock_divide_by_2
    port(
      clock_out : out std_ulogic;

      clock : in std_ulogic;
      clock_type : in integer;
      rst : in std_ulogic
      );
  end component;

  component dcm_sp_maximum_period_check
    generic (
      InstancePath : string := "*";

      clock_name : string := "";
      maximum_period : time);
    port(
      clock : in std_ulogic;
      rst : in std_ulogic
      );
  end component;

  component dcm_sp_clock_lost
    port(
      lost : out std_ulogic;

      clock : in std_ulogic;
      enable : in boolean := false;
      rst :  in std_ulogic          
      );    
  end component;

  constant MAXPERCLKIN : time := 1000000 ps;                   
  constant MAXPERPSCLK : time := 100000000 ps;                 
  constant SIM_CLKIN_CYCLE_JITTER : time := 300 ps;
  constant SIM_CLKIN_PERIOD_JITTER : time := 1000 ps;

  signal CLKFB_ipd, CLKIN_ipd, DSSEN_ipd : std_ulogic;
  signal PSCLK_ipd, PSEN_ipd, PSINCDEC_ipd, RST_ipd : std_ulogic;
  signal PSCLK_dly ,PSEN_dly, PSINCDEC_dly : std_ulogic := '0';
  
  signal clk0_out : std_ulogic;
  signal clk2x_out, clkdv_out : std_ulogic := '0';
  signal clkfx_out, locked_out, psdone_out, ps_overflow_out, ps_lock : std_ulogic := '0';
  signal locked_out_out : std_ulogic := '0';
  signal LOCKED_sig : std_ulogic := '0';  

  signal clkdv_cnt : integer := 0;
  signal clkfb_type : integer;
  signal divide_type : integer;
  signal clkin_type : integer;
  signal ps_type : integer;
  signal deskew_adjust_mode : integer;
  signal dfs_mode_type : integer;
  signal dll_mode_type : integer;
  signal clk1x_type : integer;


  signal lock_period, lock_delay, lock_clkin, lock_clkfb : std_ulogic := '0';
  signal lock_out : std_logic_vector(1 downto 0) := "00";  
  signal lock_out1_neg : std_ulogic := '0';

  signal lock_fb : std_ulogic := '0';
  signal lock_fb_dly : std_ulogic := '0';
  signal lock_fb_dly_tmp : std_ulogic := '0';
  signal fb_delay_found : std_ulogic := '0';

  signal clkin_div : std_ulogic;
  signal clkin_ps : std_ulogic;
  signal clkin_ps_tmp : std_ulogic;
  signal clkin_ps_mkup : std_ulogic := '0';
  signal clkin_ps_mkup_win : std_ulogic := '0';
  
  signal clkin_fb : std_ulogic;


  signal ps_delay : time := 0 ps;
  signal ps_in_out : integer := 0;
  signal ps_delay_init : time := 0 ps;
  signal ps_delay_md : time := 0 ps;
  signal ps_delay_all : time := 0 ps;
  signal ps_max_range : integer := 0;
  signal ps_acc : integer := 0;
  signal period_int : integer := 0;
  

  type   real_array_usr is array (2 downto 0) of time;
  signal clkin_period_real : real_array_usr := (0.000 ns, 0.000 ns, 0.000 ns);
  signal period : time := 0 ps;
  signal period_25 : time := 0 ps;
  signal period_50 : time := 0 ps;
  signal period_div : time := 0 ps;
  signal period_orig : time := 0 ps;
  signal period_ps : time := 0 ps;
  signal clkout_delay : time := 0 ps;
  signal fb_delay : time := 0 ps;
  signal period_fx, remain_fx : time := 0 ps;
  signal period_dv_high, period_dv_low : time := 0 ps;
  signal cycle_jitter, period_jitter : time := 0 ps;

  signal clkin_window, clkfb_window : std_ulogic := '0';
  signal rst_reg : std_logic_vector(2 downto 0) := "000";
  signal rst_flag : std_ulogic := '0';
  signal numerator, denominator, gcd : integer := 1;

  signal clkin_lost_out : std_ulogic := '0';
  signal clkfx_lost_out : std_ulogic := '0';

  signal remain_fx_temp : integer := 0;

  signal clkin_period_real0_temp : time := 0 ps;
  signal ps_lock_reg : std_ulogic := '0';

  signal clk0_sig : std_ulogic := '0';
  signal clk2x_sig : std_ulogic := '0';

  signal no_stop : boolean := false;

  signal clkfx180_en : std_ulogic := '0';

  signal status_out  : std_logic_vector(7 downto 0) := "00000000";

  signal first_time_locked : boolean := false;

  signal en_status : boolean := false;

  signal ps_overflow_out_ext : std_ulogic := '0';  
  signal clkin_lost_out_ext : std_ulogic := '0';
  signal clkfx_lost_out_ext : std_ulogic := '0';

  signal clkfb_div : std_ulogic := '0';
  signal clkfb_div_en : std_ulogic := '0';
  signal clkfb_chk : std_ulogic := '0';

  signal lock_period_dly : std_ulogic := '0';
  signal lock_period_dly1 : std_ulogic := '0';
  signal lock_period_pulse : std_ulogic := '0';  

  signal clock_stopped : std_ulogic := '1';

  signal clkin_chkin, clkfb_chkin : std_ulogic := '0';
  signal chk_enable, chk_rst : std_ulogic := '0';

  signal lock_ps : std_ulogic := '0';
  signal lock_ps_dly : std_ulogic := '0';      
  
  constant PS_STEP : time := 25 ps;

begin
  INITPROC : process
  begin
    detect_resolution
      (model_name => "DCM_SP"
       );
    if (CLKDV_DIVIDE = 1.5) then
      divide_type <= 3;
    elsif (CLKDV_DIVIDE = 2.0) then
      divide_type <= 4;
    elsif (CLKDV_DIVIDE = 2.5) then
      divide_type <= 5;
    elsif (CLKDV_DIVIDE = 3.0) then
      divide_type <= 6;
    elsif (CLKDV_DIVIDE = 3.5) then
      divide_type <= 7;
    elsif (CLKDV_DIVIDE = 4.0) then
      divide_type <= 8;
    elsif (CLKDV_DIVIDE = 4.5) then
      divide_type <= 9;
    elsif (CLKDV_DIVIDE = 5.0) then
      divide_type <= 10;
    elsif (CLKDV_DIVIDE = 5.5) then
      divide_type <= 11;
    elsif (CLKDV_DIVIDE = 6.0) then
      divide_type <= 12;
    elsif (CLKDV_DIVIDE = 6.5) then
      divide_type <= 13;
    elsif (CLKDV_DIVIDE = 7.0) then
      divide_type <= 14;
    elsif (CLKDV_DIVIDE = 7.5) then
      divide_type <= 15;
    elsif (CLKDV_DIVIDE = 8.0) then
      divide_type <= 16;
    elsif (CLKDV_DIVIDE = 9.0) then
      divide_type <= 18;
    elsif (CLKDV_DIVIDE = 10.0) then
      divide_type <= 20;
    elsif (CLKDV_DIVIDE = 11.0) then
      divide_type <= 22;
    elsif (CLKDV_DIVIDE = 12.0) then
      divide_type <= 24;
    elsif (CLKDV_DIVIDE = 13.0) then
      divide_type <= 26;
    elsif (CLKDV_DIVIDE = 14.0) then
      divide_type <= 28;
    elsif (CLKDV_DIVIDE = 15.0) then
      divide_type <= 30;
    elsif (CLKDV_DIVIDE = 16.0) then
      divide_type <= 32;
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLKDV_DIVIDE",
         EntityName => "DCM_SP",
         InstanceName => InstancePath,
         GenericValue => CLKDV_DIVIDE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    if ((CLKFX_DIVIDE <= 0) or (32 < CLKFX_DIVIDE)) then
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLKFX_DIVIDE",
         EntityName => "DCM_SP",
         InstanceName => InstancePath,
         GenericValue => CLKFX_DIVIDE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are 1....32",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;
    if ((CLKFX_MULTIPLY <= 1) or (32 < CLKFX_MULTIPLY)) then
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLKFX_MULTIPLY",
         EntityName => "DCM_SP",
         InstanceName => InstancePath,
         GenericValue => CLKFX_MULTIPLY,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are 2....32",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;
    case CLKIN_DIVIDE_BY_2 is
      when false => clkin_type <= 0;
      when true => clkin_type <= 1;
      when others =>
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "CLKIN_DIVIDE_BY_2",
           EntityName => "DCM_SP",
           InstanceName => InstancePath,
           GenericValue => CLKIN_DIVIDE_BY_2,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
    end case;


    if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then
      ps_type <= 0;
    elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then
      ps_type <= 1;
    elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then
      ps_type <= 2;
      if (PHASE_SHIFT /= 0) then
       GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Warning",
         GenericName => "PHASE_SHIFT",
         EntityName => "DCM_SP",
         InstanceName => InstancePath,
         GenericValue => PHASE_SHIFT,
         Unit => "",
         ExpectedValueMsg => "The maximum variable phase shift range is only valid when initial phase shift PHASE_SHIFT is zero",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => warning  
         );
      end if;
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLKOUT_PHASE_SHIFT",
         EntityName => "DCM_SP",
         InstanceName => InstancePath,
         GenericValue => CLKOUT_PHASE_SHIFT,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are NONE, FIXED or VARIABLE",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    if ((CLK_FEEDBACK = "none") or (CLK_FEEDBACK = "NONE")) then
      clkfb_type <= 0;
    elsif ((CLK_FEEDBACK = "1x") or (CLK_FEEDBACK = "1X")) then
      clkfb_type <= 1;
    elsif ((CLK_FEEDBACK = "2x") or (CLK_FEEDBACK = "2X")) then
      clkfb_type <= 2;
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLK_FEEDBACK",
         EntityName => "DCM_SP",
         InstanceName => InstancePath,
         GenericValue => CLK_FEEDBACK,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are NONE, 1X or 2X",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;



    if ((DESKEW_ADJUST = "source_synchronous") or (DESKEW_ADJUST = "SOURCE_SYNCHRONOUS")) then
      DESKEW_ADJUST_mode <= 8;
    elsif ((DESKEW_ADJUST = "system_synchronous") or (DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS")) then
      DESKEW_ADJUST_mode <= 11;
    elsif ((DESKEW_ADJUST = "0")) then
      DESKEW_ADJUST_mode <= 0;
    elsif ((DESKEW_ADJUST = "1")) then
      DESKEW_ADJUST_mode <= 1;
    elsif ((DESKEW_ADJUST = "2")) then
      DESKEW_ADJUST_mode <= 2;
    elsif ((DESKEW_ADJUST = "3")) then
      DESKEW_ADJUST_mode <= 3;
    elsif ((DESKEW_ADJUST = "4")) then
      DESKEW_ADJUST_mode <= 4;
    elsif ((DESKEW_ADJUST = "5")) then
      DESKEW_ADJUST_mode <= 5;
    elsif ((DESKEW_ADJUST = "6")) then
      DESKEW_ADJUST_mode <= 6;
    elsif ((DESKEW_ADJUST = "7")) then
      DESKEW_ADJUST_mode <= 7;
    elsif ((DESKEW_ADJUST = "8")) then
      DESKEW_ADJUST_mode <= 8;
    elsif ((DESKEW_ADJUST = "9")) then
      DESKEW_ADJUST_mode <= 9;
    elsif ((DESKEW_ADJUST = "10")) then
      DESKEW_ADJUST_mode <= 10;
    elsif ((DESKEW_ADJUST = "11")) then
      DESKEW_ADJUST_mode <= 11;
    elsif ((DESKEW_ADJUST = "12")) then
      DESKEW_ADJUST_mode <= 12;
    elsif ((DESKEW_ADJUST = "13")) then
      DESKEW_ADJUST_mode <= 13;
    elsif ((DESKEW_ADJUST = "14")) then
      DESKEW_ADJUST_mode <= 14;
    elsif ((DESKEW_ADJUST = "15")) then
      DESKEW_ADJUST_mode <= 15;
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "DESKEW_ADJUST_MODE",
         EntityName => "DCM_SP",
         InstanceName => InstancePath,
         GenericValue => DESKEW_ADJUST_MODE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 1....15",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    if ((DFS_FREQUENCY_MODE = "high") or (DFS_FREQUENCY_MODE = "HIGH")) then
      dfs_mode_type <= 1;
    elsif ((DFS_FREQUENCY_MODE = "low") or (DFS_FREQUENCY_MODE = "LOW")) then
      dfs_mode_type <= 0;
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "DFS_FREQUENCY_MODE",
         EntityName => "DCM_SP",
         InstanceName => InstancePath,
         GenericValue => DFS_FREQUENCY_MODE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are HIGH or LOW",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    if ((DLL_FREQUENCY_MODE = "high") or (DLL_FREQUENCY_MODE = "HIGH")) then
      dll_mode_type <= 1;
    elsif ((DLL_FREQUENCY_MODE = "low") or (DLL_FREQUENCY_MODE = "LOW")) then
      dll_mode_type <= 0;
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "DLL_FREQUENCY_MODE",
         EntityName => "DCM_SP",
         InstanceName => InstancePath,
         GenericValue => DLL_FREQUENCY_MODE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are HIGH or LOW",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    if ((DSS_MODE = "none") or (DSS_MODE = "NONE")) then
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "DSS_MODE",
         EntityName => "DCM_SP",
         InstanceName => InstancePath,
         GenericValue => DSS_MODE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are NONE",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    case DUTY_CYCLE_CORRECTION is
      when false => clk1x_type <= 0;
      when true => clk1x_type <= 1;
      when others =>
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "DUTY_CYCLE_CORRECTION",
           EntityName => "DCM_SP",
           InstanceName => InstancePath,
           GenericValue => DUTY_CYCLE_CORRECTION,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
    end case;

    if ((PHASE_SHIFT < -255) or (PHASE_SHIFT > 255)) then
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "PHASE_SHIFT",
         EntityName => "DCM_SP",
         InstanceName => InstancePath,
         GenericValue => PHASE_SHIFT,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are -255 ... 255",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    period_jitter <= SIM_CLKIN_PERIOD_JITTER;
    cycle_jitter <= SIM_CLKIN_CYCLE_JITTER;
    
    case STARTUP_WAIT is
      when false => null;
      when true => null;
      when others =>
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "STARTUP_WAIT",
           EntityName => "DCM_SP",
           InstanceName => InstancePath,
           GenericValue => STARTUP_WAIT,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
    end case;

--
-- fx parameters
--    
    gcd <= 1;
    for i in 2 to CLKFX_MULTIPLY loop
      if (((CLKFX_MULTIPLY mod i) = 0) and ((CLKFX_DIVIDE mod i) = 0)) then
        gcd <= i;
      end if;
    end loop;    
    numerator <= CLKFX_MULTIPLY / gcd;
    denominator <= CLKFX_DIVIDE / gcd;          
    wait;
  end process INITPROC;

--
-- input wire delays
--  


   CLKFB_ipd <= CLKFB;
   CLKIN_ipd <= CLKIN;
   DSSEN_ipd <= DSSEN;
   PSCLK_dly <= PSCLK;
   PSEN_dly <= PSEN;
   PSINCDEC_dly <= PSINCDEC;
   RST_ipd <= RST;

  i_clock_divide_by_2 : dcm_sp_clock_divide_by_2
    port map (
      clock => clkin_ipd,
      clock_type => clkin_type,
      rst => rst_ipd,
      clock_out => clkin_div);

  i_max_clkin : dcm_sp_maximum_period_check
    generic map (
      clock_name => "CLKIN",
      maximum_period => MAXPERCLKIN)

    port map (
      clock => clkin_ipd,
      rst => rst_ipd);

  i_max_psclk : dcm_sp_maximum_period_check
    generic map (
      clock_name => "PSCLK",
      maximum_period => MAXPERPSCLK)

    port map (
      clock => psclk_dly,
      rst => rst_ipd);

  i_clkin_lost : dcm_sp_clock_lost
    port map (
      lost  => clkin_lost_out,
      clock => clkin_ipd,
      enable => first_time_locked,
      rst => rst_ipd      
      );

  i_clkfx_lost : dcm_sp_clock_lost
    port map (
      lost  => clkfx_lost_out,
      clock => clkfx_out,
      enable => first_time_locked,
      rst => rst_ipd
      );  

  clkin_ps_tmp <= transport clkin_div after ps_delay_md;  

  clkin_ps <= clkin_ps_mkup when clkin_ps_mkup_win = '1' else clkin_ps_tmp;
  
  clkin_fb <= transport (clkin_ps and lock_fb);


  clkin_ps_tmp_p: process
     variable  ps_delay_last : integer := 0;
     variable  ps_delay_int : integer;
     variable  period_int2  : integer := 0;
     variable  period_int3  : integer := 0;
  begin
   if (ps_type = 2) then
      ps_delay_int := (ps_delay /1 ps ) * 1;
      period_int2 := 2 * period_int;
      period_int3 := 3 * period_int;

     if (rising_edge(clkin_div)) then
       if ((ps_delay_last > 0  and ps_delay_int <= 0 ) or 
        (ps_delay_last >= period_int  and ps_delay_int < period_int) or
        (ps_delay_last >= period_int2 and ps_delay_int < period_int2) or 
        (ps_delay_last >= period_int3  and ps_delay_int < period_int3)) then
        clkin_ps_mkup_win <= '1';
        clkin_ps_mkup <= '1';
        wait until falling_edge(clkin_div);
           clkin_ps_mkup_win <= '1';
           clkin_ps_mkup <= '0';
       else
           clkin_ps_mkup_win <= '0';
           clkin_ps_mkup <= '0';
       end if;
     end if;

     if (falling_edge(clkin_div)) then
        if ((ps_delay_last > 0  and ps_delay_int <= 0 ) or
        (ps_delay_last >= period_int  and ps_delay_int < period_int) or
        (ps_delay_last >= period_int2 and ps_delay_int < period_int2) or
        (ps_delay_last >= period_int3  and ps_delay_int < period_int3)) then
          clkin_ps_mkup <= '0';
          clkin_ps_mkup_win <= '0';
        wait until rising_edge(clkin_div);
           clkin_ps_mkup <= '1';
           clkin_ps_mkup_win <= '1';
         wait until falling_edge(clkin_div);
           clkin_ps_mkup <= '0';
           clkin_ps_mkup_win <= '1';
        else
           clkin_ps_mkup <= '0';
           clkin_ps_mkup_win <= '0';
        end if;
     end if;
        ps_delay_last := ps_delay_int;
   end if;
    wait on clkin_div;
  end process;

  detect_first_time_locked : process
    begin
      if (first_time_locked = false) then
        if (rising_edge(locked_out)) then
          first_time_locked <= true;
        end if;        
      end if;
      wait on locked_out;
  end process detect_first_time_locked;

  set_reset_en_status : process
  begin
    if (rst_ipd = '1') then
      en_status <= false;
    elsif (rising_edge(Locked_sig)) then
      en_status <= true;
    end if;
    wait on rst_ipd, Locked_sig;
  end process set_reset_en_status;    

  gen_clkfb_div_en: process
  begin
    if (rst_ipd = '1') then
      clkfb_div_en <= '0';
    elsif (falling_edge(clkfb_ipd)) then
      if (lock_fb_dly='1' and lock_period='1' and lock_fb = '1' and clkin_ps = '0') then
        clkfb_div_en <= '1';
      end if;
    end if;
    wait on clkfb_ipd, rst_ipd;
  end process  gen_clkfb_div_en;

   gen_clkfb_div: process
  begin  
    if (rst_ipd = '1') then
      clkfb_div <= '0';      
    elsif (rising_edge(clkfb_ipd)) then
      if (clkfb_div_en = '1') then
        clkfb_div <= not clkfb_div;      
      end if;
    end if;    
    wait on clkfb_ipd, rst_ipd;
  end process  gen_clkfb_div;

  determine_clkfb_chk: process
  begin
    if (clkfb_type = 2) then
      clkfb_chk <= clkfb_div;
    else 
      clkfb_chk <= clkfb_ipd and lock_fb_dly;
    end if;
    wait on clkfb_ipd, clkfb_div;
  end process  determine_clkfb_chk;

  set_reset_clkin_chkin : process
  begin
    if ((rising_edge(clkin_fb)) or (rising_edge(chk_rst))) then
      if (chk_rst = '1') then
        clkin_chkin <= '0';
      else
        clkin_chkin <= '1';
      end if;
    end if;
    wait on clkin_fb, chk_rst;
  end process set_reset_clkin_chkin;

  set_reset_clkfb_chkin : process
  begin
    if ((rising_edge(clkfb_chk)) or (rising_edge(chk_rst))) then
      if (chk_rst = '1') then
        clkfb_chkin <= '0';
      else
        clkfb_chkin <= '1';
      end if;
    end if;
    wait on clkfb_chk, chk_rst;
  end process set_reset_clkfb_chkin;

  
--   assign_chk_rst: process
--   begin
--     if ((rst_ipd = '1') or (clock_stopped = '1')) then
--       chk_rst <= '1';
--     else
--       chk_rst <= '0';  
--     end if;
--     wait on rst_ipd, clock_stopped;
--   end process assign_chk_rst;

  chk_rst <= '1' when ((rst_ipd = '1') or (clock_stopped = '1')) else '0';  

--   assign_chk_enable: process
--   begin
--     if ((clkin_chkin = '1') and (clkfb_chkin = '1')) then
--       chk_enable <= '1';
--     else
--       chk_enable <= '0';  
--     end if;
--   wait on clkin_chkin, clkfb_chkin;  
--   end process  assign_chk_enable;

  chk_enable <= '1' when ((clkin_chkin = '1') and (clkfb_chkin = '1') and (lock_ps = '1') and (lock_fb_dly = '1') and (lock_fb = '1')) else '0';  




  control_status_bits: process
  begin  
    if ((rst_ipd = '1') or (en_status = false)) then
      ps_overflow_out_ext <= '0';
      clkin_lost_out_ext <= '0';
      clkfx_lost_out_ext <= '0';
    else
      ps_overflow_out_ext <= ps_overflow_out;
      clkin_lost_out_ext <= clkin_lost_out;
      clkfx_lost_out_ext <= clkfx_lost_out;
    end if;
    wait on clkfx_lost_out, clkin_lost_out, en_status, ps_overflow_out, rst_ipd;
  end process  control_status_bits;
  
  determine_period_div : process
    variable clkin_div_edge_previous : time := 0 ps; 
    variable clkin_div_edge_current : time := 0 ps;
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      clkin_div_edge_previous := 0 ps; 
      clkin_div_edge_current := 0 ps;
      period_div <= 0 ps;
    else
      if (rising_edge(clkin_div)) then
        clkin_div_edge_previous := clkin_div_edge_current;
        clkin_div_edge_current := NOW;
        if ((clkin_div_edge_current - clkin_div_edge_previous) <= (1.5 * period_div)) then
          period_div <= clkin_div_edge_current - clkin_div_edge_previous;
        elsif ((period_div = 0 ps) and (clkin_div_edge_previous /= 0 ps)) then
          period_div <= clkin_div_edge_current - clkin_div_edge_previous;      
        end if;          
      end if;    
    end if;
    wait on clkin_div, rst_ipd;
  end process determine_period_div;

  period_cal_p : process(period)
        variable period_25_tmp : time := 0 ps;
  begin
        period_25_tmp := period / 4;
        period_50 <= 2 * period_25_tmp;
        period_25 <= period_25_tmp;
  end process;

  determine_period_ps : process
    variable clkin_ps_edge_previous : time := 0 ps; 
    variable clkin_ps_edge_current : time := 0 ps;    
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      clkin_ps_edge_previous := 0 ps; 
      clkin_ps_edge_current := 0 ps;
      period_ps <= 0 ps;
    else    
      if (rising_edge(clkin_ps)) then
        clkin_ps_edge_previous := clkin_ps_edge_current;
        clkin_ps_edge_current := NOW;
        wait for 0 ps;
        if ((clkin_ps_edge_current - clkin_ps_edge_previous) <= (1.5 * period_ps)) then
          period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous;
        elsif ((period_ps = 0 ps) and (clkin_ps_edge_previous /= 0 ps)) then
          period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous;      
        end if;
      end if;
    end if;
    wait on clkin_ps, rst_ipd;    
  end process determine_period_ps;

  assign_lock_ps_fb : process

  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      lock_fb <= '0';
      lock_ps <= '0';
      lock_ps_dly <= '0';                                            
      lock_fb_dly <= '0';
      lock_fb_dly_tmp <= '0';
    else
      if (rising_edge(clkin_ps)) then
        lock_ps <= lock_period;
        lock_ps_dly <= lock_ps;        
        lock_fb <= lock_ps_dly;            
        lock_fb_dly_tmp <= lock_fb;            
      end if;          
      if (falling_edge(clkin_ps)) then
--         lock_fb_dly <= lock_fb_dly_tmp after (period/4);
         lock_fb_dly <= lock_fb_dly_tmp after (period * 0.75);
      end if;
    end if;
    wait on clkin_ps, rst_ipd;
  end process assign_lock_ps_fb;

  calculate_clkout_delay : process
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      clkout_delay <= 0 ps;
    elsif (fb_delay = 0 ps) then
      clkout_delay <= 0 ps;                
    elsif (period'event or fb_delay'event) then
      clkout_delay <= period - fb_delay;        
    end if;
    wait on period, fb_delay, rst_ipd;
  end process calculate_clkout_delay;

--
--generate master reset signal
--  

  gen_master_rst : process
  begin
    if (rising_edge(clkin_ipd)) then    
      rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst_ipd;    
      rst_reg(1) <= rst_reg(0) and rst_ipd;
      rst_reg(0) <= rst_ipd;
    end if;
    wait on clkin_ipd;     
  end process gen_master_rst;

  check_rst_width : process
    variable Message : line;    
    begin
      if (rst_ipd ='1') then
          rst_flag <= '0';
      end if;
      if (falling_edge(rst_ipd)) then
        if ((rst_reg(2) and rst_reg(1) and rst_reg(0)) = '0') then
          rst_flag <= '1';
          Write ( Message, string'(" Input Error : RST on DCM_SP "));
          Write ( Message, string'(" must be asserted for 3 CLKIN clock cycles. "));          
          assert false report Message.all severity error;
          DEALLOCATE (Message);
        end if;        
      end if;

      wait on rst_ipd;
    end process check_rst_width;

--
--phase shift parameters
--  

  ps_max_range_p : process (period)
    variable period_ps_tmp : integer := 0;
  begin
    period_int <= (period/ 1 ps ) * 1;
    if (clkin_type = 1) then
       period_ps_tmp := 2 * (period/ 1 ns );
    else
       period_ps_tmp := (period/ 1 ns ) * 1;
    end if;
   if (period_ps_tmp > 3) then
     ps_max_range <= 20 * (period_ps_tmp - 3);
   else
     ps_max_range <= 0;
  end if;
  end process;

  ps_delay_md_p : process (period, ps_delay, lock_period, rst_ipd)
      variable tmp_value : integer;
      variable tmp_value1 : integer;
      variable tmp_value2 : integer;
  begin
      if (rst_ipd = '1') then
           ps_delay_md <= 0 ps;
      elsif (lock_period = '1') then
          tmp_value := (ps_delay / 1 ps ) * 1;
          tmp_value1 := (period / 1 ps) * 1;
          tmp_value2 := tmp_value mod tmp_value1;
          if (ps_type = 2) then
             ps_delay_md <= period + tmp_value2 * 1 ps;
          else
             ps_delay_md <= period + (ps_in_out * period) / 256;
          end if;
      end if;
  end process;


  determine_phase_shift : process
    variable Message : line;
    variable first_time : boolean := true;
    variable ps_in : integer;    
    variable ps_acc : integer := 0;
    variable ps_step_int : integer := 0;
  begin
    if (first_time = true) then
      if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then
        ps_in := 256;      
      elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then
        ps_in := 256 + PHASE_SHIFT;
      elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then
        ps_in := 256 + PHASE_SHIFT;
      end if;
      ps_step_int := (PS_STEP / 1 ps ) * 1;
      first_time := false;
    end if;    

    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then
        ps_in := 256;      
      elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then
        ps_in := 256 + PHASE_SHIFT;
      elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then
        ps_in := 256 + PHASE_SHIFT;
      else
      end if;
      ps_in_out <= ps_in;
      ps_lock <= '0';
      ps_overflow_out <= '0';
      ps_delay <= 0 ps;
      ps_acc := 0;
    elsif (rising_edge(lock_period_pulse)) then
        ps_delay <= (ps_in * period_div / 256);        
    elsif (rising_edge(PSCLK_dly)) then
        if (ps_type = 2) then
          if (psen_dly = '1') then
            if (ps_lock = '1') then
              Write ( Message, string'(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift. "));
              assert false report Message.all severity warning;
              DEALLOCATE (Message);              
            else if (lock_ps = '1') then
              if (psincdec_dly = '1') then
                if (ps_acc > ps_max_range) then
                  ps_overflow_out <= '1';
                else
                  ps_delay <= ps_delay  + PS_STEP;
                  ps_acc := ps_acc + 1;
                  ps_overflow_out <= '0';
                end if;
                ps_lock <= '1';                
              elsif (psincdec_dly = '0') then
                if (ps_acc < -ps_max_range) then
                  ps_overflow_out <= '1';
                else
                  ps_delay <= ps_delay - PS_STEP;
                  ps_acc := ps_acc - 1;
                  ps_overflow_out <= '0';
                end if;
                ps_lock <= '1';                                
              end if;
            end if;
          end if;
         end if;
        end if;
      end if;
    if (ps_lock_reg'event) then
      ps_lock <= ps_lock_reg;
    end if;
    wait on lock_period_pulse, psclk_dly, ps_lock_reg, rst_ipd;
  end process determine_phase_shift;

  determine_psdone_out : process
  begin
    if (rising_edge(ps_lock)) then
      ps_lock_reg <= '1';      
      wait until (rising_edge(clkin_ps));
      wait until (rising_edge(psclk_dly));
      wait until (rising_edge(psclk_dly));
      wait until (rising_edge(psclk_dly));
      psdone_out <= '1';
      wait until (rising_edge(psclk_dly));
      psdone_out <= '0';
      ps_lock_reg <= '0';
    end if;
    wait on ps_lock;
  end process determine_psdone_out;      
  
--
--determine clock period
--    
  determine_clock_period : process
    variable clkin_edge_previous : time := 0 ps; 
    variable clkin_edge_current : time := 0 ps;
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      clkin_period_real(0) <= 0 ps;
      clkin_period_real(1) <= 0 ps;
      clkin_period_real(2) <= 0 ps;
      clkin_edge_previous := 0 ps;      
      clkin_edge_current := 0 ps;      
    elsif (rising_edge(clkin_div)) then
      clkin_edge_previous := clkin_edge_current;
      clkin_edge_current := NOW;
      clkin_period_real(2) <= clkin_period_real(1);
      clkin_period_real(1) <= clkin_period_real(0);      
      if (clkin_edge_previous /= 0 ps) then
	clkin_period_real(0) <= clkin_edge_current - clkin_edge_previous;
      end if;
    end if;      
    if (no_stop'event) then
      clkin_period_real(0) <= clkin_period_real0_temp;
    end if;
    wait on clkin_div, no_stop, rst_ipd;
  end process determine_clock_period;
  
  evaluate_clock_period : process
    variable Message : line;
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      lock_period <= '0';
      clock_stopped <= '1';
      clkin_period_real0_temp <= 0 ps;                        
    else
      if (falling_edge(clkin_div)) then
        if (lock_period = '0') then
          if ((clkin_period_real(0) /= 0 ps ) and (clkin_period_real(0) - cycle_jitter <= clkin_period_real(1)) and (clkin_period_real(1) <= clkin_period_real(0) + cycle_jitter) and (clkin_period_real(1) - cycle_jitter <= clkin_period_real(2)) and (clkin_period_real(2) <= clkin_period_real(1) + cycle_jitter)) then
            lock_period <= '1';
            period_orig <= (clkin_period_real(0) + clkin_period_real(1) + clkin_period_real(2)) / 3;
            period <= clkin_period_real(0);
          end if;
        elsif (lock_period = '1') then
          if (100000000 ns < clkin_period_real(0)) then
            Write ( Message, string'(" Warning : CLKIN stopped toggling on instance "));
            Write ( Message, Instancepath );          
            Write ( Message, string'(" exceeds "));
            Write ( Message, string'(" 100 ms "));
            Write ( Message, string'(" Current CLKIN Period = "));
            Write ( Message, clkin_period_real(0));
            assert false report Message.all severity warning;
            DEALLOCATE (Message);
            lock_period <= '0';
            wait until (falling_edge(rst_reg(2)));            
          elsif ((period_orig * 2 < clkin_period_real(0)) and (clock_stopped = '0')) then
              clkin_period_real0_temp <= clkin_period_real(1);            
              no_stop <= not no_stop;
              clock_stopped <= '1';              
          elsif ((clkin_period_real(0) < period_orig - period_jitter) or (period_orig + period_jitter < clkin_period_real(0))) then
            Write ( Message, string'(" Warning : Input Clock Period Jitter on instance "));
            Write ( Message, Instancepath );          
            Write ( Message, string'(" exceeds "));
            Write ( Message, period_jitter );
            Write ( Message, string'(" Locked CLKIN Period =  "));
            Write ( Message, period_orig );
            Write ( Message, string'(" Current CLKIN Period =  "));
            Write ( Message, clkin_period_real(0) );
            assert false report Message.all severity warning;
            DEALLOCATE (Message);
            lock_period <= '0';
            wait until (falling_edge(rst_reg(2)));                                  
          elsif ((clkin_period_real(0) < clkin_period_real(1) - cycle_jitter) or (clkin_period_real(1) + cycle_jitter < clkin_period_real(0))) then
            Write ( Message, string'(" Warning : Input Clock Cycle Jitter on on instance "));
            Write ( Message, Instancepath );
            Write ( Message, string'(" exceeds "));
            Write ( Message, cycle_jitter );
            Write ( Message, string'(" Previous CLKIN Period =  "));
            Write ( Message, clkin_period_real(1) );
            Write ( Message, string'(" Current CLKIN Period =  "));
            Write ( Message, clkin_period_real(0) );                    
            assert false report Message.all severity warning;
            DEALLOCATE (Message);
            lock_period <= '0';
            wait until (falling_edge(rst_reg(2)));
          else           
            period <= clkin_period_real(0);
            clock_stopped <= '0';            
          end if;
        end if;  
      end if;          
    end if;
    wait on clkin_div, rst_ipd;
  end process evaluate_clock_period;    

  lock_period_dly1 <= transport lock_period after 1 ps;
  lock_period_dly <= transport lock_period_dly1 after period_50;

  lock_period_pulse <= '1' when ((lock_period = '1') and (lock_period_dly = '0')) else '0';  
  
--
--determine clock delay
--  
  
  determine_clock_delay : process
    variable delay_edge : time := 0 ps;
    variable temp1 : integer := 0;
    variable temp2 : integer := 0;        
    variable temp : integer := 0;
    variable delay_edge_current : time := 0 ps;    
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      fb_delay <= 0 ps;      
      fb_delay_found <= '0';                        
    else
      if (rising_edge(lock_ps_dly)) then
        if  ((lock_period = '1') and (clkfb_type /= 0)) then
          if (clkfb_type = 1) then
            wait until ((rising_edge(clk0_sig)) or (rst_ipd'event));                    
            delay_edge := NOW;
          elsif (clkfb_type = 2) then
            wait until ((rising_edge(clk2x_sig)) or (rst_ipd'event));
            delay_edge := NOW;
          end if;
          wait until ((rising_edge(clkfb_ipd)) or (rst_ipd'event));
          temp1 := ((NOW*1) - (delay_edge*1))/ (1 ps);
          temp2 := (period_orig * 1)/ (1 ps);
          temp := temp1 mod temp2;
          fb_delay <= temp * 1 ps;
          fb_delay_found <= '1';          
        end if;
      end if;
    end if;
    wait on lock_ps_dly, rst_ipd;
  end process determine_clock_delay;
--
--  determine feedback lock
--  
  GEN_CLKFB_WINDOW : process
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      clkfb_window <= '0';  
    else
      if (rising_edge(clkfb_chk)) then
        wait for 0 ps;
        clkfb_window <= '1';
        wait for cycle_jitter;        
        clkfb_window <= '0';
      end if;          
    end if;      
    wait on clkfb_chk, rst_ipd;
  end process GEN_CLKFB_WINDOW;

  GEN_CLKIN_WINDOW : process
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      clkin_window <= '0';
    else
      if (rising_edge(clkin_fb)) then
        wait for 0 ps;
        clkin_window <= '1';
        wait for cycle_jitter;        
        clkin_window <= '0';
      end if;          
    end if;      
    wait on clkin_fb, rst_ipd;
  end process GEN_CLKIN_WINDOW;  

  set_reset_lock_clkin : process
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      lock_clkin <= '0';                  
    else
      if (rising_edge(clkin_fb)) then
        wait for 1 ps;
        if (((clkfb_window = '1') and (fb_delay_found = '1')) or ((clkin_lost_out = '1') and (lock_out(0) = '1'))) then
          lock_clkin <= '1';
        else
          if (chk_enable = '1' and ps_lock = '0') then
            lock_clkin <= '0';
          end if;
        end if;
      end if;          
    end if;
    wait on clkin_fb, rst_ipd;
  end process set_reset_lock_clkin;

  set_reset_lock_clkfb : process
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      lock_clkfb <= '0';                  
    else
      if (rising_edge(clkfb_chk)) then
        wait for 1 ps;
        if (((clkin_window = '1') and (fb_delay_found = '1')) or ((clkin_lost_out = '1') and (lock_out(0) = '1')))then
          lock_clkfb <= '1';
        else
          if (chk_enable = '1' and ps_lock = '0') then          
            lock_clkfb <= '0';
          end if;
        end if;
      end if;          
    end if;
    wait on clkfb_chk, rst_ipd;
  end process set_reset_lock_clkfb;

  assign_lock_delay : process
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      lock_delay <= '0';          
    else
      if (falling_edge(clkin_fb)) then
        lock_delay <= lock_clkin or lock_clkfb;
      end if;
    end if;
    wait on clkin_fb, rst_ipd;    
  end process;

--
--generate lock signal
--  
  
  generate_lock : process(clkin_ps, rst_ipd)
  begin
    if (rst_ipd='1') then
      lock_out <= "00";
      locked_out <= '0';
      lock_out1_neg <= '0';
    elsif (rising_edge(clkin_ps)) then
--        if (clkfb_type = 0) then
          lock_out(0) <= lock_period;
--        else
--          lock_out(0) <= lock_period and lock_delay and lock_fb;
--        end if;
        lock_out(1) <= lock_out(0);
        locked_out <= lock_out(1);
    elsif (falling_edge(clkin_ps)) then
        lock_out1_neg <= lock_out(1);
    end if;
  end process generate_lock;

--
--generate the clk1x_out
--  
  
  gen_clk1x : process( clkin_ps, rst_ipd)
  begin
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      clk0_out <= '0';
    elsif (clkin_ps'event) then
      if (clkin_ps = '1' ) then
        if ((clk1x_type = 1) and (lock_out(0) = '1')) then
          clk0_out <= '1', '0' after period_50;
        else
          clk0_out <= '1';
        end if;
      else
        if ((clkin_ps = '0') and ((((clk1x_type = 1) and (lock_out(0) = '1')) = false) or ((lock_out(0) = '1') and (lock_out(1) = '0')))) then                
          clk0_out <= '0';
        end if;
      end if;          
    end if;
  end process gen_clk1x;




  
--
--generate the clk2x_out
--    

                                                                                  
  gen_clk2x : process
  begin
    if (rst_ipd='1') then
       clk2x_out <= '0';
    elsif (rising_edge(clkin_ps)) then
      clk2x_out <= '1';
      wait for period_25;
      clk2x_out <= '0';
      if (lock_out(0) = '1') then
        wait for period_25;
        clk2x_out <= '1';
        wait for period_25;
        clk2x_out <= '0';
      else
        wait for period_50;
      end if;
    end if;
    wait on clkin_ps, rst_ipd;
  end process gen_clk2x;

-- 
--generate the clkdv_out
-- 

  gen_clkdv : process (clkin_ps, rst_ipd)
  begin
    if (rst_ipd='1') then
       clkdv_out <= '0';
       clkdv_cnt <= 0;
    elsif ((rising_edge(clkin_ps)) or (falling_edge(clkin_ps))) then
      if (lock_out1_neg = '1') then
         if (clkdv_cnt >= divide_type -1) then
           clkdv_cnt <= 0;
         else
           clkdv_cnt <= clkdv_cnt + 1;
         end if;

         if (clkdv_cnt < divide_type /2) then
            clkdv_out <= '1';
         else
           if ( ((divide_type rem (2)) > 0) and (dll_mode_type = 0)) then
             clkdv_out <= '0' after (period_25);
           else
            clkdv_out <= '0';
           end if;
         end if;
      end if;
    end if;
  end process;

--
-- generate fx output signal
--
  
  calculate_period_fx : process
  begin
    if (lock_period = '1') then
      period_fx <= (period * denominator) / (numerator * 2);
      remain_fx <= (((period/1 ps) * denominator) mod (numerator * 2)) * 1 ps;        
    end if;
    wait on lock_period, period, denominator, numerator;
  end process calculate_period_fx;

  generate_clkfx : process
    variable temp : integer;
  begin
    if (rst_ipd = '1') then
      clkfx_out <= '0';
    elsif (clkin_lost_out_ext = '1') then
       wait until (rising_edge(rst_ipd));
       clkfx_out <= '0';            
      wait until (falling_edge(rst_reg(2)));              
    elsif (rising_edge(clkin_ps)) then
      if (lock_out(1) = '1') then
        clkfx_out <= '1';
        temp := numerator * 2 - 1 - 1;
        for p in 0 to temp loop
          wait for (period_fx);
          clkfx_out <= not clkfx_out;
        end loop;
        if (period_fx > (period_50)) then
          wait for (period_fx - (period_50));
        end if;
      end if;
      if (clkin_lost_out_ext = '1') then
        wait until (rising_edge(rst_ipd));
        clkfx_out <= '0';      
        wait until (falling_edge(rst_reg(2)));
      end if;      
    end if;
    wait on clkin_lost_out_ext, clkin_ps, rst_ipd, rst_reg(2);
  end process generate_clkfx;


--
--generate all output signal
--

  schedule_p1_outputs : process
  begin
    if (CLK0_out'event) then
      if (clkfb_type /= 0) then
        CLK0 <= transport CLK0_out after clkout_delay;
        clk0_sig <= transport CLK0_out after clkout_delay; 
      end if;                 
      if ((dll_mode_type = 0) and (clkfb_type /= 0)) then
        CLK90 <= transport clk0_out after (clkout_delay + period_25);
      end if;
    end if;

    if (CLK0_out'event or rst_ipd'event)then
      if (rst_ipd = '1') then
        CLK180 <= '0';
        CLK270 <= '0';
      elsif (CLK0_out'event) then 
        if (clkfb_type /= 0) then        
          CLK180 <= transport (not clk0_out) after clkout_delay;
        end if;
        if ((dll_mode_type = 0) and (clkfb_type /= 0)) then        
          CLK270 <= transport (not clk0_out) after (clkout_delay + period_25);
        end if;
      end if;
    end if;

    if (clk2x_out'event) then
      if ((dll_mode_type = 0) and (clkfb_type /= 0)) then
        CLK2X <= transport clk2x_out after clkout_delay;
        clk2x_sig <= transport clk2x_out after clkout_delay;  
      end if;
    end if;

    if (CLK2X_out'event or rst_ipd'event) then
      if (rst_ipd = '1') then
        CLK2X180 <= '0';
      elsif (CLK2X_out'event) then
        if ((dll_mode_type = 0) and (clkfb_type /= 0)) then
          CLK2X180 <= transport (not CLK2X_out) after clkout_delay;  
        end if;
      end if;
    end if;
      

    if (clkdv_out'event) then
      if (clkfb_type /= 0) then                
        CLKDV <= transport clkdv_out after clkout_delay;
      end if;
    end if;

    if (clkfx_out'event or rst_ipd'event) then
      if (rst_ipd = '1') then
        CLKFX <= '0';
      elsif (clkfx_out'event) then
        CLKFX <= transport clkfx_out after clkout_delay;                          
      end if;
    end if;

    if (clkfx_out'event or (rising_edge(rst_ipd)) or first_time_locked'event or locked_out'event) then
      if ((rst_ipd = '1') or (not first_time_locked)) then
        CLKFX180 <= '0';
      else
        CLKFX180 <= transport (not clkfx_out) after clkout_delay;  
      end if;
    end if;

    if (status_out(0)'event) then
      status(0) <= status_out(0);
    end if;

    if (status_out(1)'event) then
      status(1) <= status_out(1);
    end if;

    if (status_out(2)'event) then
      status(2) <= status_out(2);
    end if;    
   
   wait on clk0_out, clk2x_out, clkdv_out, clkfx_out, first_time_locked, locked_out, rst_ipd, status_out;
   end process;
 
  assign_status_out : process
    begin
      if (rst_ipd = '1') then
        status_out(0) <= '0';
        status_out(1) <= '0';
        status_out(2) <= '0';
      elsif (ps_overflow_out_ext'event) then
        status_out(0) <= ps_overflow_out_ext;
      elsif (clkin_lost_out_ext'event) then
        status_out(1) <= clkin_lost_out_ext;
      elsif (clkfx_lost_out_ext'event) then
        status_out(2) <= clkfx_lost_out_ext;
      end if;
      wait on clkin_lost_out_ext, clkfx_lost_out_ext, ps_overflow_out_ext, rst_ipd;
    end process assign_status_out;

   locked_out_out <= 'X' when rst_flag = '1' else locked_out;

   LOCKED <= locked_out_out after 100 ps;
   PSDONE <= psdone_out;
   LOCKED_sig <= locked_out_out after 100 ps;    

end DCM_SP_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fd.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop
-- /___/   /\     Filename : FD.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:21 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FD is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C : in std_ulogic;
    D : in std_ulogic
    );
end FD;

architecture FD_V of FD is
begin

  VITALBehavior : process(C)
    variable FIRST_TIME : boolean := true ;    
  begin
    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;
    
    if (rising_edge(C)) then
      Q <= D after 100 ps;
    end if;
  end process;
end FD_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fd_1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Negative-Edge Clock
-- /___/   /\     Filename : FD_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:21 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FD_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FD_1 is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;
    
    C : in  std_ulogic;
    D : in  std_ulogic
    );
end FD_1;

architecture FD_1_V of FD_1 is
begin
  VITALBehavior : process(C)
    variable FIRST_TIME : boolean := true ;        
  begin
    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;
    if (falling_edge(C)) then
      Q <= D after 100 ps;
    end if;
  end process;
end FD_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdc.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Asynchronous Clear
-- /___/   /\     Filename : FDC.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:21 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDC -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDC is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C   : in std_ulogic;
    CLR : in std_ulogic;
    D   : in std_ulogic
    );
end FDC;

architecture FDC_V of FDC is
begin
  VITALBehavior         : process(CLR, C)
    variable FIRST_TIME : boolean := true;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;
    
    if (CLR = '1') then
      Q <= '0';
    elsif (rising_edge(C)) then
      Q <= D after 100 ps;
    end if;
end process;
end FDC_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdc_1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Asynchronous Clear and Negative-Edge Clock
-- /___/   /\     Filename : FDC_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:21 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDC_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDC_1 is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C   : in std_ulogic;
    CLR : in std_ulogic;
    D   : in std_ulogic
    );
end FDC_1;

architecture FDC_1_V of FDC_1 is
begin
  VITALBehavior         : process(C, CLR)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (CLR = '1') then
      Q <= '0';
    elsif (falling_edge(C)) then
      Q <= D after 100 ps;
    end if;
  end process;
end FDC_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdce.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Asynchronous Clear and Clock Enable
-- /___/   /\     Filename : FDCE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:22 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDCE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDCE is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C   : in std_ulogic;
    CE  : in std_ulogic;
    CLR : in std_ulogic;
    D   : in std_ulogic
    );
end FDCE;

architecture FDCE_V of FDCE is
begin
  VITALBehavior         : process(C, CLR)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (CLR = '1') then
      Q   <= '0';
    elsif (rising_edge(C)) then
      if (CE = '1') then
        Q <= D after 100 ps;
      end if;
    end if;
  end process;
end FDCE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdce_1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Asynchronous Clear, Clock Enable and Negative-Edge Clock
-- /___/   /\     Filename : FDCE_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:22 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDCE_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDCE_1 is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C   : in std_ulogic;
    CE  : in std_ulogic;
    CLR : in std_ulogic;
    D   : in std_ulogic
    );
end FDCE_1;

architecture FDCE_1_V of FDCE_1 is
begin
  VITALBehavior         : process(C, CLR)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (CLR = '1') then
      Q   <= '0';
    elsif (falling_edge(C)) then
      if (CE = '1') then
        Q <= D after 100 ps;
      end if;
    end if;
  end process;
end FDCE_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdcp.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Asynchronous Clear and Preset
-- /___/   /\     Filename : FDCP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:22 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDCP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDCP is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C   : in std_ulogic;
    CLR : in std_ulogic;
    D   : in std_ulogic;
    PRE : in std_ulogic
    );
end FDCP;

architecture FDCP_V of FDCP is
begin
  VITALBehavior         : process(C, CLR, PRE)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (CLR = '1') then
      Q <= '0';
    elsif (PRE = '1') then
      Q <= '1';
    elsif (rising_edge(C)) then
      Q <= D after 100 ps;
    end if;
  end process;
end FDCP_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdcp_1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Asynchronous Clear and Preset and Negative-Edge Clock
-- /___/   /\     Filename : FDCP_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:22 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDCP_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDCP_1 is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C   : in std_ulogic;
    CLR : in std_ulogic;
    D   : in std_ulogic;
    PRE : in std_ulogic
    );

end FDCP_1;

architecture FDCP_1_V of FDCP_1 is
begin
  VITALBehavior         : process(C, CLR, PRE)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (CLR = '1') then
      Q <= '0';
    elsif (PRE = '1') then
      Q <= '1';
    elsif (falling_edge(C)) then
      Q <= D after 100 ps;
    end if;
  end process;
end FDCP_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdcpe.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Asynchronous Clear and Preset and Clock Enable
-- /___/   /\     Filename : FDCPE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:22 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDCPE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDCPE is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C   : in std_ulogic;
    CE  : in std_ulogic;
    CLR : in std_ulogic;
    D   : in std_ulogic;
    PRE : in std_ulogic
    );
end FDCPE;

architecture FDCPE_V of FDCPE is
begin
  VITALBehavior         : process(C, CLR, PRE)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (CLR = '1') then
      Q   <= '0';
    elsif (PRE = '1') then
      Q   <= '1';
    elsif (rising_edge(C)) then
      if (CE = '1') then
        Q <= D after 100 ps;
      end if;
    end if;
  end process;
end FDCPE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdcpe_1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Asynchronous Clear and Preset, Clock Enable and Negative-Edge Clock
-- /___/   /\     Filename : FDCPE_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:22 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDCPE_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDCPE_1 is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C   : in std_ulogic;
    CE  : in std_ulogic;
    CLR : in std_ulogic;
    D   : in std_ulogic;
    PRE : in std_ulogic
    );
end FDCPE_1;

architecture FDCPE_1_V of FDCPE_1 is
begin
  VITALBehavior         : process(C, CLR, PRE)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (CLR = '1') then
      Q   <= '0';
    elsif (PRE = '1') then
      Q   <= '1';
    elsif (falling_edge(C)) then
      if (CE = '1') then
        Q <= D after 100 ps;
      end if;
    end if;
  end process;

end FDCPE_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fddrcpe.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Dual Data Rate D Flip-Flop with Asynchronous Clear and Preset and Clock Enable
-- /___/   /\     Filename : FDDRCPE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:23 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDDRCPE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDDRCPE is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C0  : in std_ulogic;
    C1  : in std_ulogic;
    CE  : in std_ulogic;
    CLR : in std_ulogic;
    D0  : in std_ulogic;
    D1  : in std_ulogic;
    PRE : in std_ulogic
    );
end FDDRCPE;

architecture FDDRCPE_V of FDDRCPE is
begin

  VITALBehavior         : process(C0, C1, CLR, PRE)
    variable FIRST_TIME : boolean := true;
  begin

    if (FIRST_TIME) then
      Q <= TO_X01(INIT);
      FIRST_TIME                  := false ;
    end if;

    if (CLR = '1') then
      Q   <= '0';
    elsif (PRE = '1' ) then
      Q   <= '1';
    elsif ( rising_edge(C0) = true) then
      if (CE = '1' ) then
        Q <= D0 after 100 ps;
      end if;
    elsif (rising_edge(C1) = true ) then
      if (CE = '1') then
        Q <= D1 after 100 ps;
      end if;
    end if;
  end process VITALBehavior;
end FDDRCPE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fddrrse.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Dual Data Rate D Flip-Flop with Synchronous Reset and Set and Clock Enable
-- /___/   /\     Filename : FDDRRSE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:23 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDDRRSE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDDRRSE is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C0 : in std_ulogic;
    C1 : in std_ulogic;
    CE : in std_ulogic;
    D0 : in std_ulogic;
    D1 : in std_ulogic;
    R  : in std_ulogic;
    S  : in std_ulogic
    );
end FDDRRSE;

architecture FDDRRSE_V of FDDRRSE is
begin

  VITALBehavior         : process(C0, C1)
    variable FIRST_TIME : boolean := true;
  begin

    if (FIRST_TIME) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false ;
    end if;

    if ( rising_edge(C0) = true) then
      if (R = '1') then
        Q <= '0' after 100 ps;
      elsif (S = '1' ) then
        Q <= '1' after 100 ps;
      elsif (CE = '1' ) then
        Q <= D0 after 100 ps;
      end if;
    elsif (rising_edge(C1) = true ) then
      if (R = '1') then
        Q <= '0' after 100 ps;
      elsif (S = '1' ) then
        Q <= '1' after 100 ps;
      elsif (CE = '1') then
        Q <= D1 after 100 ps;
      end if;
    end if;
  end process VITALBehavior;
end FDDRRSE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fde.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Clock Enable
-- /___/   /\     Filename : FDE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:23 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDE is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C  : in std_ulogic;
    CE : in std_ulogic;
    D  : in std_ulogic
    );
end FDE;

architecture FDE_V of FDE is
begin
  VITALBehavior         : process(C)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (rising_edge(C)) then
      if (CE = '1') then
        Q <= D after 100 ps;
      end if;
    end if;
  end process;
end FDE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fde_1.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Clock Enable and Negative-Edge Clock
-- /___/   /\     Filename : FDE_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:24 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDE_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDE_1 is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C  : in std_ulogic;
    CE : in std_ulogic;
    D  : in std_ulogic
    );
end FDE_1;

architecture FDE_1_V of FDE_1 is
begin
  VITALBehavior         : process(C)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (falling_edge(C)) then
      if (CE = '1') then
        Q <= D after 100 ps;
      end if;
    end if;
  end process;
end FDE_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdp.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Asynchronous Preset
-- /___/   /\     Filename : FDP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:24 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDP is
  generic(
    INIT : bit := '1'
    );

  port(
    Q : out std_ulogic;

    C   : in std_ulogic;
    D   : in std_ulogic;
    PRE : in std_ulogic
    );
end FDP;

architecture FDP_V of FDP is
begin
  VITALBehavior         : process(C, PRE)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (PRE = '1') then
      Q <= '1';
    elsif (C' event and C = '1') then
      Q <= D after 100 ps;
    end if;
  end process;
end FDP_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdp_1.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Asynchronous Preset and Negative-Edge Clock
-- /___/   /\     Filename : FDP_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:24 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDP_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDP_1 is
  generic(
    INIT : bit := '1'
    );

  port(
    Q : out std_ulogic;

    C   : in std_ulogic;
    D   : in std_ulogic;
    PRE : in std_ulogic
    );
end FDP_1;

architecture FDP_1_V of FDP_1 is
begin
  VITALBehavior         : process(C, PRE)
    variable FIRST_TIME : boolean := true ;
  begin
    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME                  := false;
    end if;

    if (PRE = '1') then
      Q <= '1';
    elsif (C' event and C = '0') then
      Q <= D after 100 ps;
    end if;
  end process;

end FDP_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdpe.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Asynchronous Preset and Clock Enable
-- /___/   /\     Filename : FDPE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:24 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDPE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDPE is
  generic(
    INIT : bit := '1'
    );

  port(
    Q : out std_ulogic;

    C   : in std_ulogic;
    CE  : in std_ulogic;
    D   : in std_ulogic;
    PRE : in std_ulogic
    );
end FDPE;

architecture FDPE_V of FDPE is
begin
  VITALBehavior         : process(C, PRE)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (PRE = '1') then
      Q   <= '1';
    elsif (rising_edge(C)) then
      if (CE = '1') then
        Q <= D after 100 ps;
      end if;
    end if;
  end process;
end FDPE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdpe_1.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Asynchronous Preset, Clock Enable and Negative-Edge Clock
-- /___/   /\     Filename : FDPE_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:24 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDPE_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDPE_1 is
  generic(
    INIT : bit := '1'
    );

  port(
    Q : out std_ulogic;

    C   : in std_ulogic;
    CE  : in std_ulogic;
    D   : in std_ulogic;
    PRE : in std_ulogic
    );
end FDPE_1;

architecture FDPE_1_V of FDPE_1 is
begin
  VITALBehavior         : process(C, PRE)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (PRE = '1') then
      Q   <= '1';
    elsif (falling_edge(C)) then
      if (CE = '1') then
        Q <= D after 100 ps;
      end if;
    end if;
  end process;
end FDPE_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdr.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Synchronous Reset
-- /___/   /\     Filename : FDR.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:24 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDR -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDR is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C : in std_ulogic;
    D : in std_ulogic;
    R : in std_ulogic
    );
end FDR;

architecture FDR_V of FDR is
begin
  VITALBehavior         : process(C)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (rising_edge(C)) then
      if (R = '1') then
        Q <= '0' after 100 ps;
      else
        Q <= D after 100 ps;
      end if;
    end if;
  end process;
end FDR_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdr_1.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Synchronous Reset and Negative-Edge Clock
-- /___/   /\     Filename : FDR_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:24 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDR_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDR_1 is
   generic(
      INIT                           :  bit := '0'  
);
   
      port(
      Q                              :	out   STD_ULOGIC;
      
      C                              :	in    STD_ULOGIC;      
      D                              :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC
      );
end FDR_1;

architecture FDR_1_V of FDR_1 is
begin
   VITALBehavior : process(C) 
   VARIABLE FIRST_TIME : boolean := True ;
   begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (falling_edge(C)) then
      if (R = '1') then
        Q <= '0' after 100 ps;
      else
        Q <= D after 100 ps;
      end if;
    end if;     
end process;
end FDR_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdre.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Synchronous Reset and Clock Enable
-- /___/   /\     Filename : FDRE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:24 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDRE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDRE is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C  : in std_ulogic;
    CE : in std_ulogic;
    D  : in std_ulogic;
    R  : in std_ulogic
    );
end FDRE;

architecture FDRE_V of FDRE is
begin
  VITALBehavior         : process(C)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (rising_edge(C)) then
      if (R = '1') then
        Q <= '0' after 100 ps;
      elsif (CE = '1') then
        Q <= D after 100 ps;
      end if;
    end if;
  end process;
end FDRE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdre_1.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Synchronous Reset, Clock Enable and Negative-Edge Clock
-- /___/   /\     Filename : FDRE_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:24 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDRE_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDRE_1 is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C  : in std_ulogic;
    CE : in std_ulogic;
    D  : in std_ulogic;
    R  : in std_ulogic
    );
end FDRE_1;

architecture FDRE_1_V of FDRE_1 is
begin
  VITALBehavior         : process(C)
    variable FIRST_TIME : boolean := true ;
  begin
    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME                  := false;
    end if;

    if (falling_edge(C)) then
      if (R = '1') then
        Q <= '0' after 100 ps;
      elsif (CE = '1') then
        Q <= D after 100 ps;
      end if;
    end if;
  end process;

end FDRE_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdrs.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Synchronous Reset and Set
-- /___/   /\     Filename : FDRS.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:25 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDRS -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDRS is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C : in std_ulogic;
    D : in std_ulogic;
    R : in std_ulogic;
    S : in std_ulogic
    );
end FDRS;

architecture FDRS_V of FDRS is
begin
  VITALBehavior         : process(C)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (rising_edge(C)) then
      if (R = '1') then
        Q <= '0' after 100 ps;
      elsif (S = '1') then
        Q <= '1' after 100 ps;
      else
        Q <= D after 100 ps;
      end if;
    end if;
  end process;
end FDRS_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdrs_1.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Synchronous Reset and Set and Negative-Edge Clock
-- /___/   /\     Filename : FDRS_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:25 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDRS_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDRS_1 is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C : in std_ulogic;
    D : in std_ulogic;
    R : in std_ulogic;
    S : in std_ulogic
    );
end FDRS_1;

architecture FDRS_1_V of FDRS_1 is
begin
  VITALBehavior         : process(C)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (falling_edge(C)) then
      if (R = '1') then
        Q <= '0' after 100 ps;
      elsif (S = '1') then
        Q <= '1' after 100 ps;
      else
        Q <= D after 100 ps;
      end if;
    end if;
  end process;
end FDRS_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdrse.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Synchronous Reset and Set and Clock Enable
-- /___/   /\     Filename : FDRSE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:25 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDRSE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDRSE is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C  : in std_ulogic;
    CE : in std_ulogic;
    D  : in std_ulogic;
    R  : in std_ulogic;
    S  : in std_ulogic
    );
end FDRSE;

architecture FDRSE_V of FDRSE is
begin
  VITALBehavior         : process(C)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (rising_edge(C)) then
      if (R = '1') then
        Q <= '0' after 100 ps;
      elsif (S = '1') then
        Q <= '1' after 100 ps;
      elsif (CE = '1') then
        Q <= D after 100 ps;
      end if;
    end if;
  end process;
end FDRSE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdrse_1.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Synchronous Reset and Set, Clock Enable and Negative-Edge Clock
-- /___/   /\     Filename : FDRSE_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:25 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDRSE_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDRSE_1 is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C  : in std_ulogic;
    CE : in std_ulogic;
    D  : in std_ulogic;
    R  : in std_ulogic;
    S  : in std_ulogic
    );
end FDRSE_1;

architecture FDRSE_1_V of FDRSE_1 is
begin
  VITALBehavior         : process(C)
    variable FIRST_TIME : boolean := true ;
  begin
    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME                  := false;
    end if;

    if (falling_edge(C)) then
      if (R = '1') then
        Q <= '0' after 100 ps;
      elsif (S = '1') then
        Q <= '1' after 100 ps;
      elsif (CE = '1') then
        Q <= D after 100 ps;
      end if;
    end if;
  end process;
end FDRSE_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fds.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Synchronous Set
-- /___/   /\     Filename : FDS.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:25 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDS -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDS is
  generic(
    INIT : bit := '1'
    );

  port(
    Q : out std_ulogic;

    C : in std_ulogic;
    D : in std_ulogic;
    S : in std_ulogic
    );
end FDS;

architecture FDS_V of FDS is
begin
  VITALBehavior         : process(C)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (rising_edge(C)) then
      if (S = '1') then
        Q <= '1' after 100 ps;
      else
        Q <= D after 100 ps;
      end if;
    end if;
  end process;
end FDS_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fds_1.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Synchronous Set and Negative-Edge Clock
-- /___/   /\     Filename : FDS_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:25 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDS_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDS_1 is
  generic(
    INIT : bit := '1'
    );

  port(
    Q : out std_ulogic;

    C : in std_ulogic;
    D : in std_ulogic;
    S : in std_ulogic
    );
end FDS_1;

architecture FDS_1_V of FDS_1 is
begin
  VITALBehavior         : process(C)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (falling_edge(C)) then
      if (S = '1') then
        Q <= '1' after 100 ps;
      else
        Q <= D after 100 ps;
      end if;
    end if;
  end process;
end FDS_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdse.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Synchronous Set and Clock Enable
-- /___/   /\     Filename : FDSE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:25 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDSE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDSE is
  generic(
    INIT : bit := '1'
    );

  port(
    Q : out std_ulogic;

    C  : in std_ulogic;
    CE : in std_ulogic;
    D  : in std_ulogic;
    S  : in std_ulogic
    );
end FDSE;

architecture FDSE_V of FDSE is
begin
  VITALBehavior         : process(C)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (rising_edge(C)) then
      if (S = '1') then
        Q <= '1' after 100 ps;
      elsif (CE = '1') then
        Q <= D after 100 ps;
      end if;
    end if;
  end process;
end FDSE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdse_1.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Synchronous Set, Clock Enable and Negative-Edge Clock
-- /___/   /\     Filename : FDSE_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:25 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDSE_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDSE_1 is
  generic(
    INIT : bit := '1'
    );

  port(
    Q : out std_ulogic;

    C  : in std_ulogic;
    CE : in std_ulogic;
    D  : in std_ulogic;
    S  : in std_ulogic
    );
end FDSE_1;

architecture FDSE_1_V of FDSE_1 is
begin
  VITALBehavior         : process(C)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (falling_edge(C)) then
      if (S = '1') then
        Q <= '1' after 100 ps;
      elsif (CE = '1') then
        Q <= D after 100 ps;
      end if;
    end if;
  end process;
end FDSE_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fmap.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  F Function Generator Partitioning Control Symbol
-- /___/   /\     Filename : FMAP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:25 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FMAP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FMAP is
  port(
    O : in std_ulogic := 'X';

    I1 : in std_ulogic := 'X';
    I2 : in std_ulogic := 'X';
    I3 : in std_ulogic := 'X';
    I4 : in std_ulogic := 'X'
    );
end FMAP;

architecture FMAP_V of FMAP is
begin
end FMAP_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/gnd.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  GND Connection
-- /___/   /\     Filename : GND.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:26 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL GND -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity GND is
  port(
    G : out std_ulogic := '0'
    );
end GND;

architecture GND_V of GND is
begin

  G <= '0';
end GND_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf.vhd,v 1.10 2005/03/10 22:45:34 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer
-- /___/   /\     Filename : IBUF.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:26 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
----- CELL IBUF                         -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

entity IBUF is
  generic(
    CAPACITANCE : string := "DONT_CARE";
    IBUF_DELAY_VALUE : string := "0";
    IFD_DELAY_VALUE  : string := "AUTO";
    IOSTANDARD  : string := "DEFAULT"
    );

  port(
    O : out std_ulogic;

    I : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    IBUF : entity is true;
end IBUF;

architecture IBUF_V of IBUF is
begin

  prcs_init : process
  variable FIRST_TIME        : boolean    := TRUE;
  begin
     
     If(FIRST_TIME = true) then
        if((CAPACITANCE = "LOW") or
           (CAPACITANCE = "NORMAL") or 
           (CAPACITANCE = "DONT_CARE")) then 
           FIRST_TIME := false;
        else  
           assert false
           report "Attribute Syntax Error: The allowed values for CAPACITANCE are LOW, NORMAL or DONT_CARE"
           severity Failure;
        end if;

--  
        if((IBUF_DELAY_VALUE = "0") or (IBUF_DELAY_VALUE = "1") or
          (IBUF_DELAY_VALUE = "2")  or (IBUF_DELAY_VALUE = "3") or
          (IBUF_DELAY_VALUE = "4")  or (IBUF_DELAY_VALUE = "5") or
          (IBUF_DELAY_VALUE = "6")  or (IBUF_DELAY_VALUE = "7") or
          (IBUF_DELAY_VALUE = "8")  or (IBUF_DELAY_VALUE = "9") or
          (IBUF_DELAY_VALUE = "10") or (IBUF_DELAY_VALUE = "11") or
          (IBUF_DELAY_VALUE = "12") or (IBUF_DELAY_VALUE = "13") or
          (IBUF_DELAY_VALUE = "14") or (IBUF_DELAY_VALUE = "15") or
          (IBUF_DELAY_VALUE = "16")) then
              FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The Legal values for IBUF_DELAY_VALUE are 0, 1, 2, ... , or 16. "
           severity Failure;
        end if;

--  
        if((IFD_DELAY_VALUE = "AUTO") or (IFD_DELAY_VALUE = "auto") or
          (IFD_DELAY_VALUE = "0")     or (IFD_DELAY_VALUE = "1") or
          (IFD_DELAY_VALUE = "2")     or (IFD_DELAY_VALUE = "3") or
          (IFD_DELAY_VALUE = "4")     or (IFD_DELAY_VALUE = "5") or
          (IFD_DELAY_VALUE = "6")     or (IFD_DELAY_VALUE = "7") or
          (IFD_DELAY_VALUE = "8")) then
              FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The Legal values for IFD_DELAY_VALUE are AUTO, 0, 1, ... , or 8"
           severity Failure;
        end if;

     end if;
     wait; 
  end process prcs_init;
    

  O <= TO_X01(I) after 0 ps;
end IBUF_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_agp.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with AGP I/O Standard
-- /___/   /\     Filename : IBUF_AGP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:26 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_AGP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_AGP is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_AGP;

architecture IBUF_AGP_V of IBUF_AGP is
begin
  O <= TO_X01(I);
end IBUF_AGP_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_ctt.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with CTT I/O Standard
-- /___/   /\     Filename : IBUF_CTT.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:26 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_CTT -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_CTT is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_CTT;

architecture IBUF_CTT_V of IBUF_CTT is
begin
  O <= TO_X01(I);
end IBUF_CTT_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_gtl.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with GTL I/O Standard
-- /___/   /\     Filename : IBUF_GTL.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:26 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_GTL -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_GTL is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_GTL;

architecture IBUF_GTL_V of IBUF_GTL is
begin
  O <= TO_X01(I);
end IBUF_GTL_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_gtl_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with GTL_DCI I/O Standard
-- /___/   /\     Filename : IBUF_GTL_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:26 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_GTL_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_GTL_DCI is
   port(
      O : out std_ulogic;

      I : in std_ulogic
      );
end IBUF_GTL_DCI;

architecture IBUF_GTL_DCI_V of IBUF_GTL_DCI is
begin
  O <= TO_X01(I);
end IBUF_GTL_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_gtlp.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with GTLP I/O Standard
-- /___/   /\     Filename : IBUF_GTLP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:27 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_GTLP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_GTLP is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_GTLP;

architecture IBUF_GTLP_V of IBUF_GTLP is
begin
  O <= TO_X01(I);
end IBUF_GTLP_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_gtlp_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with GTLP_DCI I/O Standard
-- /___/   /\     Filename : IBUF_GTLP_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:27 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_GTLP_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_GTLP_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_GTLP_DCI;

architecture IBUF_GTLP_DCI_V of IBUF_GTLP_DCI is
begin
  O <= TO_X01(I);
end IBUF_GTLP_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_i.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with HSTL_I I/O Standard
-- /___/   /\     Filename : IBUF_HSTL_I.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:27 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_HSTL_I -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_HSTL_I is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_HSTL_I;

architecture IBUF_HSTL_I_V of IBUF_HSTL_I is
begin
  O <= TO_X01(I);
end IBUF_HSTL_I_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_i_18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with HSTL_I_18 I/O Standard
-- /___/   /\     Filename : IBUF_HSTL_I_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:27 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_HSTL_I_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_HSTL_I_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_HSTL_I_18;

architecture IBUF_HSTL_I_18_V of IBUF_HSTL_I_18 is
begin
  O <= TO_X01(I);
end IBUF_HSTL_I_18_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_i_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with HSTL_I_DCI I/O Standard
-- /___/   /\     Filename : IBUF_HSTL_I_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:27 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_HSTL_I_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_HSTL_I_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_HSTL_I_DCI;

architecture IBUF_HSTL_I_DCI_V of IBUF_HSTL_I_DCI is
begin
  O <= TO_X01(I);
end IBUF_HSTL_I_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_i_dci_18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with HSTL_I_DCI_18 I/O Standard
-- /___/   /\     Filename : IBUF_HSTL_I_DCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:27 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_HSTL_I_DCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_HSTL_I_DCI_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_HSTL_I_DCI_18;

architecture IBUF_HSTL_I_DCI_18_V of IBUF_HSTL_I_DCI_18 is
begin
  O <= TO_X01(I);
end IBUF_HSTL_I_DCI_18_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_ii.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with HSTL_II I/O Standard
-- /___/   /\     Filename : IBUF_HSTL_II.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:27 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_HSTL_II -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_HSTL_II is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_HSTL_II;

architecture IBUF_HSTL_II_V of IBUF_HSTL_II is
begin
  O <= TO_X01(I);
end IBUF_HSTL_II_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_ii_18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with HSTL_II_18 I/O Standard
-- /___/   /\     Filename : IBUF_HSTL_II_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:27 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_HSTL_II_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_HSTL_II_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_HSTL_II_18;

architecture IBUF_HSTL_II_18_V of IBUF_HSTL_II_18 is
begin
  O <= TO_X01(I);
end IBUF_HSTL_II_18_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_ii_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with HSTL_II_DCI I/O Standard
-- /___/   /\     Filename : IBUF_HSTL_II_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:27 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_HSTL_II_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_HSTL_II_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_HSTL_II_DCI;

architecture IBUF_HSTL_II_DCI_V of IBUF_HSTL_II_DCI is
begin
  O <= TO_X01(I);
end IBUF_HSTL_II_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_ii_dci_18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with HSTL_II_DCI_18 I/O Standard
-- /___/   /\     Filename : IBUF_HSTL_II_DCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:28 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_HSTL_II_DCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_HSTL_II_DCI_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_HSTL_II_DCI_18;

architecture IBUF_HSTL_II_DCI_18_V of IBUF_HSTL_II_DCI_18 is
begin
  O <= TO_X01(I);
end IBUF_HSTL_II_DCI_18_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_iii.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with HSTL_III I/O Standard
-- /___/   /\     Filename : IBUF_HSTL_III.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:28 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_HSTL_III -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_HSTL_III is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_HSTL_III;

architecture IBUF_HSTL_III_V of IBUF_HSTL_III is
begin
  O <= TO_X01(I);
end IBUF_HSTL_III_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_iii_18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with HSTL_III_18 I/O Standard
-- /___/   /\     Filename : IBUF_HSTL_III_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:28 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_HSTL_III_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_HSTL_III_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_HSTL_III_18;

architecture IBUF_HSTL_III_18_V of IBUF_HSTL_III_18 is
begin
  O <= TO_X01(I);
end IBUF_HSTL_III_18_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_iii_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with HSTL_III_DCI I/O Standard
-- /___/   /\     Filename : IBUF_HSTL_III_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:28 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_HSTL_III_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_HSTL_III_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_HSTL_III_DCI;

architecture IBUF_HSTL_III_DCI_V of IBUF_HSTL_III_DCI is
begin
  O <= TO_X01(I);
end IBUF_HSTL_III_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_iii_dci_18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with HSTL_III_DCI_18 I/O Standard
-- /___/   /\     Filename : IBUF_HSTL_III_DCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:28 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_HSTL_III_DCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_HSTL_III_DCI_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_HSTL_III_DCI_18;

architecture IBUF_HSTL_III_DCI_18_V of IBUF_HSTL_III_DCI_18 is
begin
  O <= TO_X01(I);
end IBUF_HSTL_III_DCI_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_iv.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with HSTL_IV I/O Standard
-- /___/   /\     Filename : IBUF_HSTL_IV.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:28 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_HSTL_IV -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_HSTL_IV is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_HSTL_IV;

architecture IBUF_HSTL_IV_V of IBUF_HSTL_IV is
begin
  O <= TO_X01(I);
end IBUF_HSTL_IV_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_iv_18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with HSTL_IV_18 I/O Standard
-- /___/   /\     Filename : IBUF_HSTL_IV_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:28 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_HSTL_IV_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_HSTL_IV_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_HSTL_IV_18;

architecture IBUF_HSTL_IV_18_V of IBUF_HSTL_IV_18 is
begin
  O <= TO_X01(I);
end IBUF_HSTL_IV_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_iv_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with HSTL_IV_DCI I/O Standard
-- /___/   /\     Filename : IBUF_HSTL_IV_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:28 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_HSTL_IV_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_HSTL_IV_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_HSTL_IV_DCI;

architecture IBUF_HSTL_IV_DCI_V of IBUF_HSTL_IV_DCI is
begin
  O <= TO_X01(I);
end IBUF_HSTL_IV_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_iv_dci_18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with HSTL_IV_DCI_18 I/O Standard
-- /___/   /\     Filename : IBUF_HSTL_IV_DCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:28 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_HSTL_IV_DCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_HSTL_IV_DCI_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_HSTL_IV_DCI_18;

architecture IBUF_HSTL_IV_DCI_18_V of IBUF_HSTL_IV_DCI_18 is
begin
  O <= TO_X01(I);
end IBUF_HSTL_IV_DCI_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvcmos12.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with LVCMOS12 I/O Standard
-- /___/   /\     Filename : IBUF_LVCMOS12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:28 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_LVCMOS12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_LVCMOS12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_LVCMOS12;

architecture IBUF_LVCMOS12_V of IBUF_LVCMOS12 is
begin
  O <= TO_X01(I);
end IBUF_LVCMOS12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvcmos15.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with LVCMOS15 I/O Standard
-- /___/   /\     Filename : IBUF_LVCMOS15.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:29 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_LVCMOS15 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_LVCMOS15 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_LVCMOS15;

architecture IBUF_LVCMOS15_V of IBUF_LVCMOS15 is
begin
  O <= TO_X01(I);
end IBUF_LVCMOS15_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvcmos18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with LVCMOS18 I/O Standard
-- /___/   /\     Filename : IBUF_LVCMOS18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:29 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_LVCMOS18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_LVCMOS18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_LVCMOS18;

architecture IBUF_LVCMOS18_V of IBUF_LVCMOS18 is
begin
  O <= TO_X01(I);
end IBUF_LVCMOS18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvcmos2.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with LVCMOS2 I/O Standard
-- /___/   /\     Filename : IBUF_LVCMOS2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:29 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_LVCMOS2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_LVCMOS2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_LVCMOS2;

architecture IBUF_LVCMOS2_V of IBUF_LVCMOS2 is
begin
  O <= TO_X01(I);
end IBUF_LVCMOS2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvcmos25.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with LVCMOS25 I/O Standard
-- /___/   /\     Filename : IBUF_LVCMOS25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:29 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_LVCMOS25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_LVCMOS25 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_LVCMOS25;

architecture IBUF_LVCMOS25_V of IBUF_LVCMOS25 is
begin
  O <= TO_X01(I);
end IBUF_LVCMOS25_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvcmos33.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with LVCMOS33 I/O Standard
-- /___/   /\     Filename : IBUF_LVCMOS33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:29 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_LVCMOS33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_LVCMOS33 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_LVCMOS33;

architecture IBUF_LVCMOS33_V of IBUF_LVCMOS33 is
begin
  O <= TO_X01(I);
end IBUF_LVCMOS33_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvdci_15.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with LVDCI_15 I/O Standard
-- /___/   /\     Filename : IBUF_LVDCI_15.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:29 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_LVDCI_15 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_LVDCI_15 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_LVDCI_15;

architecture IBUF_LVDCI_15_V of IBUF_LVDCI_15 is
begin
  O <= TO_X01(I);
end IBUF_LVDCI_15_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvdci_18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with LVDCI_18 I/O Standard
-- /___/   /\     Filename : IBUF_LVDCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:29 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_LVDCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_LVDCI_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_LVDCI_18;

architecture IBUF_LVDCI_18_V of IBUF_LVDCI_18 is
begin
  O <= TO_X01(I);
end IBUF_LVDCI_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvdci_25.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with LVDCI_25 I/O Standard
-- /___/   /\     Filename : IBUF_LVDCI_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:29 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_LVDCI_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_LVDCI_25 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_LVDCI_25;

architecture IBUF_LVDCI_25_V of IBUF_LVDCI_25 is
begin
  O <= TO_X01(I);
end IBUF_LVDCI_25_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvdci_33.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with LVDCI_33 I/O Standard
-- /___/   /\     Filename : IBUF_LVDCI_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:29 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_LVDCI_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_LVDCI_33 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_LVDCI_33;

architecture IBUF_LVDCI_33_V of IBUF_LVDCI_33 is
begin
  O <= TO_X01(I);
end IBUF_LVDCI_33_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvdci_dv2_15.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with LVDCI_DV2_15 I/O Standard
-- /___/   /\     Filename : IBUF_LVDCI_DV2_15.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:30 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_LVDCI_DV2_15 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_LVDCI_DV2_15 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_LVDCI_DV2_15;

architecture IBUF_LVDCI_DV2_15_V of IBUF_LVDCI_DV2_15 is
begin
  O <= TO_X01(I);
end IBUF_LVDCI_DV2_15_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvdci_dv2_18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with LVDCI_DV2_18 I/O Standard
-- /___/   /\     Filename : IBUF_LVDCI_DV2_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:30 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_LVDCI_DV2_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_LVDCI_DV2_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_LVDCI_DV2_18;

architecture IBUF_LVDCI_DV2_18_V of IBUF_LVDCI_DV2_18 is
begin
  O <= TO_X01(I);
end IBUF_LVDCI_DV2_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvdci_dv2_25.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with LVDCI_DV2_25 I/O Standard
-- /___/   /\     Filename : IBUF_LVDCI_DV2_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:30 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_LVDCI_DV2_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_LVDCI_DV2_25 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_LVDCI_DV2_25;

architecture IBUF_LVDCI_DV2_25_V of IBUF_LVDCI_DV2_25 is
begin
  O <= TO_X01(I);
end IBUF_LVDCI_DV2_25_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvdci_dv2_33.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with LVDCI_DV2_33 I/O Standard
-- /___/   /\     Filename : IBUF_LVDCI_DV2_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:30 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_LVDCI_DV2_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_LVDCI_DV2_33 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_LVDCI_DV2_33;

architecture IBUF_LVDCI_DV2_33_V of IBUF_LVDCI_DV2_33 is
begin
  O <= TO_X01(I);
end IBUF_LVDCI_DV2_33_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvds.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with LVDS I/O Standard
-- /___/   /\     Filename : IBUF_LVDS.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:30 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_LVDS -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_LVDS is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_LVDS;

architecture IBUF_LVDS_V of IBUF_LVDS is
begin
  O <= TO_X01(I);
end IBUF_LVDS_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvpecl.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with LVPECL I/O Standard
-- /___/   /\     Filename : IBUF_LVPECL.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:30 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_LVPECL -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_LVPECL is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_LVPECL;

architecture IBUF_LVPECL_V of IBUF_LVPECL is
begin
  O <= TO_X01(I);
end IBUF_LVPECL_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvttl.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with LVTTL I/O Standard
-- /___/   /\     Filename : IBUF_LVTTL.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:30 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_LVTTL -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_LVTTL is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_LVTTL;

architecture IBUF_LVTTL_V of IBUF_LVTTL is
begin
  O <= TO_X01(I);
end IBUF_LVTTL_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_pci33_3.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with PCI33_3 I/O Standard
-- /___/   /\     Filename : IBUF_PCI33_3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:30 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_PCI33_3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_PCI33_3 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_PCI33_3;

architecture IBUF_PCI33_3_V of IBUF_PCI33_3 is
begin
  O <= TO_X01(I);
end IBUF_PCI33_3_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_pci33_5.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with PCI33_5 I/O Standard
-- /___/   /\     Filename : IBUF_PCI33_5.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:30 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_PCI33_5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_PCI33_5 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_PCI33_5;

architecture IBUF_PCI33_5_V of IBUF_PCI33_5 is
begin
  O <= TO_X01(I);
end IBUF_PCI33_5_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_pci66_3.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with PCI66_3 I/O Standard
-- /___/   /\     Filename : IBUF_PCI66_3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:31 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_PCI66_3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_PCI66_3 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_PCI66_3;

architecture IBUF_PCI66_3_V of IBUF_PCI66_3 is
begin
  O <= TO_X01(I);
end IBUF_PCI66_3_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_pcix.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with PCIX I/O Standard
-- /___/   /\     Filename : IBUF_PCIX.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:31 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_PCIX -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_PCIX is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_PCIX;

architecture IBUF_PCIX_V of IBUF_PCIX is
begin
  O <= TO_X01(I);
end IBUF_PCIX_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_pcix66_3.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with PCIX66_3 I/O Standard
-- /___/   /\     Filename : IBUF_PCIX66_3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:31 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_PCIX66_3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_PCIX66_3 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_PCIX66_3;

architecture IBUF_PCIX66_3_V of IBUF_PCIX66_3 is
begin
  O <= TO_X01(I);
end IBUF_PCIX66_3_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl18_i.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with SSTL18_I I/O Standard
-- /___/   /\     Filename : IBUF_SSTL18_I.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:31 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_SSTL18_I -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_SSTL18_I is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_SSTL18_I;

architecture IBUF_SSTL18_I_V of IBUF_SSTL18_I is
begin
  O <= TO_X01(I);
end IBUF_SSTL18_I_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl18_i_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with SSTL18_I_DCI I/O Standard
-- /___/   /\     Filename : IBUF_SSTL18_I_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:31 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_SSTL18_I_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_SSTL18_I_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_SSTL18_I_DCI;

architecture IBUF_SSTL18_I_DCI_V of IBUF_SSTL18_I_DCI is
begin
  O <= TO_X01(I);
end IBUF_SSTL18_I_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl18_ii.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with SSTL18_II I/O Standard
-- /___/   /\     Filename : IBUF_SSTL18_II.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:31 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_SSTL18_II -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_SSTL18_II is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_SSTL18_II;

architecture IBUF_SSTL18_II_V of IBUF_SSTL18_II is
begin
  O <= TO_X01(I);
end IBUF_SSTL18_II_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl18_ii_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with SSTL18_II_DCI I/O Standard
-- /___/   /\     Filename : IBUF_SSTL18_II_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:31 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_SSTL18_II_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_SSTL18_II_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_SSTL18_II_DCI;

architecture IBUF_SSTL18_II_DCI_V of IBUF_SSTL18_II_DCI is
begin
  O <= TO_X01(I);
end IBUF_SSTL18_II_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl2_i.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with SSTL2_I I/O Standard
-- /___/   /\     Filename : IBUF_SSTL2_I.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:31 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_SSTL2_I -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_SSTL2_I is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_SSTL2_I;

architecture IBUF_SSTL2_I_V of IBUF_SSTL2_I is
begin
  O <= TO_X01(I);
end IBUF_SSTL2_I_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl2_i_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with SSTL2_I_DCI I/O Standard
-- /___/   /\     Filename : IBUF_SSTL2_I_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:32 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_SSTL2_I_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_SSTL2_I_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_SSTL2_I_DCI;

architecture IBUF_SSTL2_I_DCI_V of IBUF_SSTL2_I_DCI is
begin
  O <= TO_X01(I);
end IBUF_SSTL2_I_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl2_ii.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with SSTL2_II I/O Standard
-- /___/   /\     Filename : IBUF_SSTL2_II.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:32 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_SSTL2_II -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_SSTL2_II is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_SSTL2_II;

architecture IBUF_SSTL2_II_V of IBUF_SSTL2_II is
begin
  O <= TO_X01(I);
end IBUF_SSTL2_II_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl2_ii_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with SSTL2_II_DCI I/O Standard
-- /___/   /\     Filename : IBUF_SSTL2_II_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:32 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_SSTL2_II_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_SSTL2_II_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_SSTL2_II_DCI;

architecture IBUF_SSTL2_II_DCI_V of IBUF_SSTL2_II_DCI is
begin
  O <= TO_X01(I);
end IBUF_SSTL2_II_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl3_i.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with SSTL3_I I/O Standard
-- /___/   /\     Filename : IBUF_SSTL3_I.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:32 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_SSTL3_I -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_SSTL3_I is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_SSTL3_I;

architecture IBUF_SSTL3_I_V of IBUF_SSTL3_I is
begin
  O <= TO_X01(I);
end IBUF_SSTL3_I_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl3_i_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with SSTL3_I_DCI I/O Standard
-- /___/   /\     Filename : IBUF_SSTL3_I_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:32 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_SSTL3_I_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_SSTL3_I_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_SSTL3_I_DCI;

architecture IBUF_SSTL3_I_DCI_V of IBUF_SSTL3_I_DCI is
begin
  O <= TO_X01(I);
end IBUF_SSTL3_I_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl3_ii.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with SSTL3_II I/O Standard
-- /___/   /\     Filename : IBUF_SSTL3_II.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:32 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_SSTL3_II -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_SSTL3_II is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_SSTL3_II;

architecture IBUF_SSTL3_II_V of IBUF_SSTL3_II is
begin
  O <= TO_X01(I);
end IBUF_SSTL3_II_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl3_ii_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Buffer with SSTL3_II_DCI I/O Standard
-- /___/   /\     Filename : IBUF_SSTL3_II_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:32 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUF_SSTL3_II_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUF_SSTL3_II_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUF_SSTL3_II_DCI;

architecture IBUF_SSTL3_II_DCI_V of IBUF_SSTL3_II_DCI is
begin
  O <= TO_X01(I);
end IBUF_SSTL3_II_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds.vhd,v 1.10 2006/07/21 20:50:05 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Buffer
-- /___/   /\     Filename : IBUFDS.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:32 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/10/06 - CR 222428 -- added H(pullup) and L(pulldown) usage
--    07/19/06 - Add else to handle x case for o_out (CR 234718).
-- End Revision


----- CELL IBUFDS -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFDS is
  generic(
      CAPACITANCE : string  := "DONT_CARE";
      DIFF_TERM   : boolean :=  FALSE;
      IBUF_DELAY_VALUE : string := "0";
      IFD_DELAY_VALUE  : string := "AUTO";
      IOSTANDARD  : string  := "DEFAULT"
    );

  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFDS;

architecture IBUFDS_V of IBUFDS is
begin
  prcs_init : process
  variable FIRST_TIME        : boolean    := TRUE;
  begin

     If(FIRST_TIME = true) then

        if((CAPACITANCE = "LOW") or
           (CAPACITANCE = "NORMAL") or
           (CAPACITANCE = "DONT_CARE")) then
           FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The Legal values for CAPACITANCE are LOW, NORMAL or DONT_CARE"
           severity Failure;
        end if;

        if((DIFF_TERM = TRUE) or
           (DIFF_TERM = FALSE)) then
           FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The Legal values for DIFF_TERM are TRUE or FALSE"
           severity Failure;
        end if;

--   
        if((IBUF_DELAY_VALUE = "0") or (IBUF_DELAY_VALUE = "1") or 
          (IBUF_DELAY_VALUE = "2")  or (IBUF_DELAY_VALUE = "3") or
          (IBUF_DELAY_VALUE = "4")  or (IBUF_DELAY_VALUE = "5") or
          (IBUF_DELAY_VALUE = "6")  or (IBUF_DELAY_VALUE = "7") or
          (IBUF_DELAY_VALUE = "8")  or (IBUF_DELAY_VALUE = "9") or
          (IBUF_DELAY_VALUE = "10") or (IBUF_DELAY_VALUE = "11") or
          (IBUF_DELAY_VALUE = "12") or (IBUF_DELAY_VALUE = "13") or
          (IBUF_DELAY_VALUE = "14") or (IBUF_DELAY_VALUE = "15") or
          (IBUF_DELAY_VALUE = "16")) then 
              FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The Legal values for IBUF_DELAY_VALUE are 0, 1, 2, ... , or 16. "
           severity Failure;
        end if;        

--   
        if((IFD_DELAY_VALUE = "AUTO") or (IFD_DELAY_VALUE = "auto") or 
          (IFD_DELAY_VALUE = "0")     or (IFD_DELAY_VALUE = "1") or 
          (IFD_DELAY_VALUE = "2")     or (IFD_DELAY_VALUE = "3") or
          (IFD_DELAY_VALUE = "4")     or (IFD_DELAY_VALUE = "5") or
          (IFD_DELAY_VALUE = "6")     or (IFD_DELAY_VALUE = "7") or
          (IFD_DELAY_VALUE = "8")) then
              FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The Legal values for IFD_DELAY_VALUE are AUTO, 0, 1, ... , or 8"
           severity Failure;
        end if;        

     end if;

     wait;
  end process prcs_init;

  VitalBehavior : process (I, IB)
  begin
--    if ((I = '1') and (IB = '0')) then
--      O <= TO_X01(I);
--    elsif ((I = '0') and (IB = '1')) then
--      O <= TO_X01(I);
--    end if;
    if ( (((I = '1') or (I = 'H')) and ((IB = '0') or (IB = 'L'))) or
         (((I = '0') or (I = 'L')) and ((IB = '1') or (IB = 'H'))) ) then
      O <= TO_X01(I);
    elsif (I = 'Z' or I = 'X' or IB = 'Z' or IB ='X') then
        O <= 'X';
    end if;

  end process;
end IBUFDS_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_blvds_25.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Buffer with BLVDS_25 I/O Standard
-- /___/   /\     Filename : IBUFDS_BLVDS_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:32 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFDS_BLVDS_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFDS_BLVDS_25 is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFDS_BLVDS_25;

architecture IBUFDS_BLVDS_25_V of IBUFDS_BLVDS_25 is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFDS_BLVDS_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_diff_out.vhd,v 1.5 2005/07/23 00:24:21 fphillip Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Buffer with Differential Outputs
-- /___/   /\     Filename : IBUFDS_DIFF_OUT.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:33 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFDS_DIFF_OUT -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFDS_DIFF_OUT is
  generic(
    IOSTANDARD                     : string := "LVDS_25"          
    );

   port(
      O                              :	out   STD_ULOGIC;
      OB                              :	out   STD_ULOGIC;      
      
      I                              :	in    STD_ULOGIC;
      IB                              :	in    STD_ULOGIC      
      );
end IBUFDS_DIFF_OUT;

architecture IBUFDS_DIFF_OUT_V of IBUFDS_DIFF_OUT is
begin
   VITALBehavior : process (I, IB)
   begin
      if (I /= IB ) then
        O  <= TO_X01(I);
        OB <= TO_X01(NOT I);
      end if;
end process;
end IBUFDS_DIFF_OUT_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_ldt_25.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Buffer with LDT_25 I/O Standard
-- /___/   /\     Filename : IBUFDS_LDT_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:33 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFDS_LDT_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFDS_LDT_25 is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFDS_LDT_25;

architecture IBUFDS_LDT_25_V of IBUFDS_LDT_25 is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFDS_LDT_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_lvds_25.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Buffer with LVDS_25 I/O Standard
-- /___/   /\     Filename : IBUFDS_LVDS_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:33 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFDS_LVDS_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFDS_LVDS_25 is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFDS_LVDS_25;

architecture IBUFDS_LVDS_25_V of IBUFDS_LVDS_25 is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFDS_LVDS_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_lvds_25_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Buffer with LVDS_25_DCI I/O Standard
-- /___/   /\     Filename : IBUFDS_LVDS_25_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:33 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFDS_LVDS_25_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFDS_LVDS_25_DCI is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFDS_LVDS_25_DCI;

architecture IBUFDS_LVDS_25_DCI_V of IBUFDS_LVDS_25_DCI is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFDS_LVDS_25_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_lvds_33.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Buffer with LVDS_33 I/O Standard
-- /___/   /\     Filename : IBUFDS_LVDS_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:33 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFDS_LVDS_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFDS_LVDS_33 is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFDS_LVDS_33;

architecture IBUFDS_LVDS_33_V of IBUFDS_LVDS_33 is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFDS_LVDS_33_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_lvds_33_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Buffer with LVDS_33_DCI I/O Standard
-- /___/   /\     Filename : IBUFDS_LVDS_33_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:33 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFDS_LVDS_33_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFDS_LVDS_33_DCI is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFDS_LVDS_33_DCI;

architecture IBUFDS_LVDS_33_DCI_V of IBUFDS_LVDS_33_DCI is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFDS_LVDS_33_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_lvdsext_25.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Buffer with LVDSEXT_25 I/O Standard
-- /___/   /\     Filename : IBUFDS_LVDSEXT_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:33 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFDS_LVDSEXT_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFDS_LVDSEXT_25 is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFDS_LVDSEXT_25;

architecture IBUFDS_LVDSEXT_25_V of IBUFDS_LVDSEXT_25 is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFDS_LVDSEXT_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_lvdsext_25_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Buffer with LVDSEXT_25_DCI I/O Standard
-- /___/   /\     Filename : IBUFDS_LVDSEXT_25_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:33 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFDS_LVDSEXT_25_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFDS_LVDSEXT_25_DCI is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFDS_LVDSEXT_25_DCI;

architecture IBUFDS_LVDSEXT_25_DCI_V of IBUFDS_LVDSEXT_25_DCI is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFDS_LVDSEXT_25_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_lvdsext_33.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Buffer with LVDSEXT_33 I/O Standard
-- /___/   /\     Filename : IBUFDS_LVDSEXT_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:33 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFDS_LVDSEXT_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFDS_LVDSEXT_33 is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFDS_LVDSEXT_33;

architecture IBUFDS_LVDSEXT_33_V of IBUFDS_LVDSEXT_33 is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFDS_LVDSEXT_33_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_lvdsext_33_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Buffer with LVDSEXT_33_DCI I/O Standard
-- /___/   /\     Filename : IBUFDS_LVDSEXT_33_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:33 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFDS_LVDSEXT_33_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFDS_LVDSEXT_33_DCI is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFDS_LVDSEXT_33_DCI;

architecture IBUFDS_LVDSEXT_33_DCI_V of IBUFDS_LVDSEXT_33_DCI is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFDS_LVDSEXT_33_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_lvpecl_25.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Buffer with LVPECL_25 I/O Standard
-- /___/   /\     Filename : IBUFDS_LVPECL_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:34 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFDS_LVPECL_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFDS_LVPECL_25 is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFDS_LVPECL_25;

architecture IBUFDS_LVPECL_25_V of IBUFDS_LVPECL_25 is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFDS_LVPECL_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_lvpecl_33.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Buffer with LVPECL_33 I/O Standard
-- /___/   /\     Filename : IBUFDS_LVPECL_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:34 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFDS_LVPECL_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFDS_LVPECL_33 is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFDS_LVPECL_33;

architecture IBUFDS_LVPECL_33_V of IBUFDS_LVPECL_33 is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFDS_LVPECL_33_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_ulvds_25.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Buffer with ULVDS_25 I/O Standard
-- /___/   /\     Filename : IBUFDS_ULVDS_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:34 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFDS_ULVDS_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFDS_ULVDS_25 is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFDS_ULVDS_25;

architecture IBUFDS_ULVDS_25_V of IBUFDS_ULVDS_25 is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFDS_ULVDS_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg.vhd,v 1.8 2005/03/10 22:45:34 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer
-- /___/   /\     Filename : IBUFG.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:34 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG is
  generic(
    CAPACITANCE : string := "DONT_CARE";
    IBUF_DELAY_VALUE : string := "0";        
    IOSTANDARD  : string := "DEFAULT"
    );

  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG;

architecture IBUFG_V of IBUFG is
begin
  prcs_init : process
  variable FIRST_TIME        : boolean    := TRUE;
  begin

     If(FIRST_TIME = true) then
        if((CAPACITANCE = "LOW") or
           (CAPACITANCE = "NORMAL") or
           (CAPACITANCE = "DONT_CARE")) then
           FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The Legal values for CAPACITANCE are LOW, NORMAL or DONT_CARE"
           severity Failure;
        end if;
--   
        if((IBUF_DELAY_VALUE = "0") or (IBUF_DELAY_VALUE = "1") or 
          (IBUF_DELAY_VALUE = "2")  or (IBUF_DELAY_VALUE = "3") or
          (IBUF_DELAY_VALUE = "4")  or (IBUF_DELAY_VALUE = "5") or
          (IBUF_DELAY_VALUE = "6")  or (IBUF_DELAY_VALUE = "7") or
          (IBUF_DELAY_VALUE = "8")  or (IBUF_DELAY_VALUE = "9") or
          (IBUF_DELAY_VALUE = "10") or (IBUF_DELAY_VALUE = "11") or
          (IBUF_DELAY_VALUE = "12") or (IBUF_DELAY_VALUE = "13") or
          (IBUF_DELAY_VALUE = "14") or (IBUF_DELAY_VALUE = "15") or
          (IBUF_DELAY_VALUE = "16")) then 
              FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The Legal values for IBUF_DELAY_VALUE are 0, 1, 2, ... , or 16. "
           severity Failure;
        end if;        

     end if;
     wait;
  end process prcs_init;

  O <= TO_X01(I);
end IBUFG_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_agp.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with AGP I/O Standard
-- /___/   /\     Filename : IBUFG_AGP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:34 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_AGP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_AGP is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_AGP;

architecture IBUFG_AGP_V of IBUFG_AGP is
begin
  O <= TO_X01(I);
end IBUFG_AGP_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_ctt.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with CTT I/O Standard
-- /___/   /\     Filename : IBUFG_CTT.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:34 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_CTT -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_CTT is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_CTT;

architecture IBUFG_CTT_V of IBUFG_CTT is
begin
  O <= TO_X01(I);
end IBUFG_CTT_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_gtl.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with GTL I/O Standard
-- /___/   /\     Filename : IBUFG_GTL.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:34 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_GTL -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_GTL is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_GTL;

architecture IBUFG_GTL_V of IBUFG_GTL is
begin
  O <= TO_X01(I);
end IBUFG_GTL_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_gtl_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with GTL_DCI I/O Standard
-- /___/   /\     Filename : IBUFG_GTL_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:34 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_GTL_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_GTL_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_GTL_DCI;

architecture IBUFG_GTL_DCI_V of IBUFG_GTL_DCI is
begin
  O <= TO_X01(I);
end IBUFG_GTL_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_gtlp.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with GTLP I/O Standard
-- /___/   /\     Filename : IBUFG_GTLP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:34 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_GTLP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_GTLP is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_GTLP;

architecture IBUFG_GTLP_V of IBUFG_GTLP is
begin
  O <= TO_X01(I);
end IBUFG_GTLP_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_gtlp_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with GTLP_DCI I/O Standard
-- /___/   /\     Filename : IBUFG_GTLP_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:35 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_GTLP_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_GTLP_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_GTLP_DCI;

architecture IBUFG_GTLP_DCI_V of IBUFG_GTLP_DCI is
begin
  O <= TO_X01(I);
end IBUFG_GTLP_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_i.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with HSTL_I I/O Standard
-- /___/   /\     Filename : IBUFG_HSTL_I.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:35 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_HSTL_I -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_HSTL_I is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_HSTL_I;

architecture IBUFG_HSTL_I_V of IBUFG_HSTL_I is
begin
  O <= TO_X01(I);
end IBUFG_HSTL_I_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_i_18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with HSTL_I_18 I/O Standard
-- /___/   /\     Filename : IBUFG_HSTL_I_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:35 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_HSTL_I_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_HSTL_I_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_HSTL_I_18;

architecture IBUFG_HSTL_I_18_V of IBUFG_HSTL_I_18 is
begin
  O <= TO_X01(I);
end IBUFG_HSTL_I_18_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_i_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with HSTL_I_DCI I/O Standard
-- /___/   /\     Filename : IBUFG_HSTL_I_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:35 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_HSTL_I_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_HSTL_I_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_HSTL_I_DCI;

architecture IBUFG_HSTL_I_DCI_V of IBUFG_HSTL_I_DCI is
begin
  O <= TO_X01(I);
end IBUFG_HSTL_I_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_i_dci_18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with HSTL_I_DCI_18 I/O Standard
-- /___/   /\     Filename : IBUFG_HSTL_I_DCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:35 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_HSTL_I_DCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_HSTL_I_DCI_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_HSTL_I_DCI_18;

architecture IBUFG_HSTL_I_DCI_18_V of IBUFG_HSTL_I_DCI_18 is
begin
  O <= TO_X01(I);
end IBUFG_HSTL_I_DCI_18_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_ii.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with HSTL_II I/O Standard
-- /___/   /\     Filename : IBUFG_HSTL_II.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:35 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_HSTL_II -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_HSTL_II is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_HSTL_II;

architecture IBUFG_HSTL_II_V of IBUFG_HSTL_II is
begin
  O <= TO_X01(I);
end IBUFG_HSTL_II_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_ii_18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with HSTL_II_18 I/O Standard
-- /___/   /\     Filename : IBUFG_HSTL_II_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:35 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_HSTL_II_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_HSTL_II_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_HSTL_II_18;

architecture IBUFG_HSTL_II_18_V of IBUFG_HSTL_II_18 is
begin
  O <= TO_X01(I);
end IBUFG_HSTL_II_18_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_ii_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with HSTL_II_DCI I/O Standard
-- /___/   /\     Filename : IBUFG_HSTL_II_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:35 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_HSTL_II_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_HSTL_II_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_HSTL_II_DCI;

architecture IBUFG_HSTL_II_DCI_V of IBUFG_HSTL_II_DCI is
begin
  O <= TO_X01(I);
end IBUFG_HSTL_II_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_ii_dci_18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with HSTL_II_DCI_18 I/O Standard
-- /___/   /\     Filename : IBUFG_HSTL_II_DCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:35 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_HSTL_II_DCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_HSTL_II_DCI_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_HSTL_II_DCI_18;

architecture IBUFG_HSTL_II_DCI_18_V of IBUFG_HSTL_II_DCI_18 is
begin
  O <= TO_X01(I);
end IBUFG_HSTL_II_DCI_18_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_iii.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with HSTL_III I/O Standard
-- /___/   /\     Filename : IBUFG_HSTL_III.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:36 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_HSTL_III -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_HSTL_III is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_HSTL_III;

architecture IBUFG_HSTL_III_V of IBUFG_HSTL_III is
begin
  O <= TO_X01(I);
end IBUFG_HSTL_III_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_iii_18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with HSTL_III_18 I/O Standard
-- /___/   /\     Filename : IBUFG_HSTL_III_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:36 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_HSTL_III_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_HSTL_III_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_HSTL_III_18;

architecture IBUFG_HSTL_III_18_V of IBUFG_HSTL_III_18 is
begin
  O <= TO_X01(I);
end IBUFG_HSTL_III_18_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_iii_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with HSTL_III_DCI I/O Standard
-- /___/   /\     Filename : IBUFG_HSTL_III_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:36 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_HSTL_III_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_HSTL_III_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_HSTL_III_DCI;

architecture IBUFG_HSTL_III_DCI_V of IBUFG_HSTL_III_DCI is
begin
  O <= TO_X01(I);
end IBUFG_HSTL_III_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_iii_dci_18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with HSTL_III_DCI_18 I/O Standard
-- /___/   /\     Filename : IBUFG_HSTL_III_DCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:36 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_HSTL_III_DCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_HSTL_III_DCI_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_HSTL_III_DCI_18;

architecture IBUFG_HSTL_III_DCI_18_V of IBUFG_HSTL_III_DCI_18 is
begin
  O <= TO_X01(I);
end IBUFG_HSTL_III_DCI_18_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_iv.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with HSTL_IV I/O Standard
-- /___/   /\     Filename : IBUFG_HSTL_IV.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:36 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_HSTL_IV -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_HSTL_IV is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_HSTL_IV;

architecture IBUFG_HSTL_IV_V of IBUFG_HSTL_IV is
begin
  O <= TO_X01(I);
end IBUFG_HSTL_IV_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_iv_18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with HSTL_IV_18 I/O Standard
-- /___/   /\     Filename : IBUFG_HSTL_IV_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:36 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_HSTL_IV_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_HSTL_IV_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_HSTL_IV_18;

architecture IBUFG_HSTL_IV_18_V of IBUFG_HSTL_IV_18 is
begin
  O <= TO_X01(I);
end IBUFG_HSTL_IV_18_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_iv_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with HSTL_IV_DCI I/O Standard
-- /___/   /\     Filename : IBUFG_HSTL_IV_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:36 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_HSTL_IV_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_HSTL_IV_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_HSTL_IV_DCI;

architecture IBUFG_HSTL_IV_DCI_V of IBUFG_HSTL_IV_DCI is
begin
  O <= TO_X01(I);
end IBUFG_HSTL_IV_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_iv_dci_18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with HSTL_IV_DCI_18 I/O Standard
-- /___/   /\     Filename : IBUFG_HSTL_IV_DCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:36 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_HSTL_IV_DCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_HSTL_IV_DCI_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_HSTL_IV_DCI_18;

architecture IBUFG_HSTL_IV_DCI_18_V of IBUFG_HSTL_IV_DCI_18 is
begin
  O <= TO_X01(I);
end IBUFG_HSTL_IV_DCI_18_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvcmos12.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with LVCMOS12 I/O Standard
-- /___/   /\     Filename : IBUFG_LVCMOS12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:36 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_LVCMOS12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_LVCMOS12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_LVCMOS12;

architecture IBUFG_LVCMOS12_V of IBUFG_LVCMOS12 is
begin
  O <= TO_X01(I);
end IBUFG_LVCMOS12_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvcmos15.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with LVCMOS15 I/O Standard
-- /___/   /\     Filename : IBUFG_LVCMOS15.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:37 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_LVCMOS15 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_LVCMOS15 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_LVCMOS15;

architecture IBUFG_LVCMOS15_V of IBUFG_LVCMOS15 is
begin
  O <= TO_X01(I);
end IBUFG_LVCMOS15_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvcmos18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with LVCMOS18 I/O Standard
-- /___/   /\     Filename : IBUFG_LVCMOS18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:37 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_LVCMOS18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_LVCMOS18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_LVCMOS18;

architecture IBUFG_LVCMOS18_V of IBUFG_LVCMOS18 is
begin
  O <= TO_X01(I);
end IBUFG_LVCMOS18_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvcmos2.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with LVCMOS2 I/O Standard
-- /___/   /\     Filename : IBUFG_LVCMOS2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:37 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_LVCMOS2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_LVCMOS2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_LVCMOS2;

architecture IBUFG_LVCMOS2_V of IBUFG_LVCMOS2 is
begin
  O <= TO_X01(I);
end IBUFG_LVCMOS2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvcmos25.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with LVCMOS25 I/O Standard
-- /___/   /\     Filename : IBUFG_LVCMOS25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:37 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_LVCMOS25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_LVCMOS25 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_LVCMOS25;

architecture IBUFG_LVCMOS25_V of IBUFG_LVCMOS25 is
begin
  O <= TO_X01(I);
end IBUFG_LVCMOS25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvcmos33.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with LVCMOS33 I/O Standard
-- /___/   /\     Filename : IBUFG_LVCMOS33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:37 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_LVCMOS33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_LVCMOS33 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_LVCMOS33;

architecture IBUFG_LVCMOS33_V of IBUFG_LVCMOS33 is
begin
  O <= TO_X01(I);
end IBUFG_LVCMOS33_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvdci_15.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with LVDCI_15 I/O Standard
-- /___/   /\     Filename : IBUFG_LVDCI_15.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:37 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_LVDCI_15 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_LVDCI_15 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_LVDCI_15;

architecture IBUFG_LVDCI_15_V of IBUFG_LVDCI_15 is
begin
  O <= TO_X01(I);
end IBUFG_LVDCI_15_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvdci_18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with LVDCI_18 I/O Standard
-- /___/   /\     Filename : IBUFG_LVDCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:37 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_LVDCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_LVDCI_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_LVDCI_18;

architecture IBUFG_LVDCI_18_V of IBUFG_LVDCI_18 is
begin
  O <= TO_X01(I);
end IBUFG_LVDCI_18_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvdci_25.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with LVDCI_25 I/O Standard
-- /___/   /\     Filename : IBUFG_LVDCI_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:37 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_LVDCI_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_LVDCI_25 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_LVDCI_25;

architecture IBUFG_LVDCI_25_V of IBUFG_LVDCI_25 is
begin
  O <= TO_X01(I);
end IBUFG_LVDCI_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvdci_33.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with LVDCI_33 I/O Standard
-- /___/   /\     Filename : IBUFG_LVDCI_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:37 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_LVDCI_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_LVDCI_33 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_LVDCI_33;

architecture IBUFG_LVDCI_33_V of IBUFG_LVDCI_33 is
begin
  O <= TO_X01(I);
end IBUFG_LVDCI_33_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvdci_dv2_15.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with LVDCI_DV2_15 I/O Standard
-- /___/   /\     Filename : IBUFG_LVDCI_DV2_15.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:38 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_LVDCI_DV2_15 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_LVDCI_DV2_15 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_LVDCI_DV2_15;

architecture IBUFG_LVDCI_DV2_15_V of IBUFG_LVDCI_DV2_15 is
begin
  O <= TO_X01(I);
end IBUFG_LVDCI_DV2_15_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvdci_dv2_18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with LVDCI_DV2_18 I/O Standard
-- /___/   /\     Filename : IBUFG_LVDCI_DV2_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:38 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_LVDCI_DV2_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_LVDCI_DV2_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_LVDCI_DV2_18;

architecture IBUFG_LVDCI_DV2_18_V of IBUFG_LVDCI_DV2_18 is
begin
  O <= TO_X01(I);
end IBUFG_LVDCI_DV2_18_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvdci_dv2_25.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with LVDCI_DV2_25 I/O Standard
-- /___/   /\     Filename : IBUFG_LVDCI_DV2_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:38 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_LVDCI_DV2_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_LVDCI_DV2_25 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_LVDCI_DV2_25;

architecture IBUFG_LVDCI_DV2_25_V of IBUFG_LVDCI_DV2_25 is
begin
  O <= TO_X01(I);
end IBUFG_LVDCI_DV2_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvdci_dv2_33.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with LVDCI_DV2_33 I/O Standard
-- /___/   /\     Filename : IBUFG_LVDCI_DV2_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:38 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_LVDCI_DV2_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_LVDCI_DV2_33 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_LVDCI_DV2_33;

architecture IBUFG_LVDCI_DV2_33_V of IBUFG_LVDCI_DV2_33 is
begin
  O <= TO_X01(I);
end IBUFG_LVDCI_DV2_33_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvds.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with LVDS I/O Standard
-- /___/   /\     Filename : IBUFG_LVDS.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:38 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_LVDS -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_LVDS is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_LVDS;

architecture IBUFG_LVDS_V of IBUFG_LVDS is
begin
  O <= TO_X01(I);
end IBUFG_LVDS_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvpecl.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with LVPECL I/O Standard
-- /___/   /\     Filename : IBUFG_LVPECL.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:38 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_LVPECL -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_LVPECL is
  port(
    O : out STD_ULOGIC;

    I : in STD_ULOGIC
    );
end IBUFG_LVPECL;

architecture IBUFG_LVPECL_V of IBUFG_LVPECL is
begin
  O <= TO_X01(I);
end IBUFG_LVPECL_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvttl.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with LVTTL I/O Standard
-- /___/   /\     Filename : IBUFG_LVTTL.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:38 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_LVTTL -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_LVTTL is
  port(
    O : out STD_ULOGIC;

    I : in STD_ULOGIC
    );
end IBUFG_LVTTL;

architecture IBUFG_LVTTL_V of IBUFG_LVTTL is
begin
  O <= TO_X01(I);
end IBUFG_LVTTL_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_pci33_3.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with PCI33_3 I/O Standard
-- /___/   /\     Filename : IBUFG_PCI33_3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:38 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_PCI33_3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_PCI33_3 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_PCI33_3;

architecture IBUFG_PCI33_3_V of IBUFG_PCI33_3 is
begin
  O <= TO_X01(I);
end IBUFG_PCI33_3_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_pci33_5.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with PCI33_5 I/O Standard
-- /___/   /\     Filename : IBUFG_PCI33_5.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:38 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_PCI33_5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_PCI33_5 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_PCI33_5;

architecture IBUFG_PCI33_5_V of IBUFG_PCI33_5 is
begin
  O <= TO_X01(I);
end IBUFG_PCI33_5_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_pci66_3.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with PCI66_3 I/O Standard
-- /___/   /\     Filename : IBUFG_PCI66_3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:39 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_PCI66_3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_PCI66_3 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_PCI66_3;

architecture IBUFG_PCI66_3_V of IBUFG_PCI66_3 is
begin
  O <= TO_X01(I);
end IBUFG_PCI66_3_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_pcix.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with PCIX I/O Standard
-- /___/   /\     Filename : IBUFG_PCIX.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:39 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_PCIX -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_PCIX is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_PCIX;

architecture IBUFG_PCIX_V of IBUFG_PCIX is
begin
  O <= TO_X01(I);
end IBUFG_PCIX_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_pcix66_3.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with PCIX66_3 I/O Standard
-- /___/   /\     Filename : IBUFG_PCIX66_3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:39 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_PCIX66_3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_PCIX66_3 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_PCIX66_3;

architecture IBUFG_PCIX66_3_V of IBUFG_PCIX66_3 is
begin
  O <= TO_X01(I);
end IBUFG_PCIX66_3_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl18_i.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with SSTL18_I I/O Standard
-- /___/   /\     Filename : IBUFG_SSTL18_I.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:39 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_SSTL18_I -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_SSTL18_I is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_SSTL18_I;

architecture IBUFG_SSTL18_I_V of IBUFG_SSTL18_I is
begin
  O <= TO_X01(I);
end IBUFG_SSTL18_I_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl18_i_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with SSTL18_I_DCI I/O Standard
-- /___/   /\     Filename : IBUFG_SSTL18_I_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:39 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_SSTL18_I_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_SSTL18_I_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_SSTL18_I_DCI;

architecture IBUFG_SSTL18_I_DCI_V of IBUFG_SSTL18_I_DCI is
begin
  O <= TO_X01(I);
end IBUFG_SSTL18_I_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl18_ii.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with SSTL18_II I/O Standard
-- /___/   /\     Filename : IBUFG_SSTL18_II.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:39 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_SSTL18_II -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_SSTL18_II is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_SSTL18_II;

architecture IBUFG_SSTL18_II_V of IBUFG_SSTL18_II is
begin
  O <= TO_X01(I);
end IBUFG_SSTL18_II_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl18_ii_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with SSTL18_II_DCI I/O Standard
-- /___/   /\     Filename : IBUFG_SSTL18_II_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:39 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_SSTL18_II_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_SSTL18_II_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_SSTL18_II_DCI;

architecture IBUFG_SSTL18_II_DCI_V of IBUFG_SSTL18_II_DCI is
begin
  O <= TO_X01(I);
end IBUFG_SSTL18_II_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl2_i.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with SSTL2_I I/O Standard
-- /___/   /\     Filename : IBUFG_SSTL2_I.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:39 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_SSTL2_I -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_SSTL2_I is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_SSTL2_I;

architecture IBUFG_SSTL2_I_V of IBUFG_SSTL2_I is
begin
  O <= TO_X01(I);
end IBUFG_SSTL2_I_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl2_i_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with SSTL2_I_DCI I/O Standard
-- /___/   /\     Filename : IBUFG_SSTL2_I_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:39 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_SSTL2_I_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_SSTL2_I_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_SSTL2_I_DCI;

architecture IBUFG_SSTL2_I_DCI_V of IBUFG_SSTL2_I_DCI is
begin
  O <= TO_X01(I);
end IBUFG_SSTL2_I_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl2_ii.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with SSTL2_II I/O Standard
-- /___/   /\     Filename : IBUFG_SSTL2_II.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:40 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_SSTL2_II -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_SSTL2_II is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_SSTL2_II;

architecture IBUFG_SSTL2_II_V of IBUFG_SSTL2_II is
begin
  O <= TO_X01(I);
end IBUFG_SSTL2_II_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl2_ii_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with SSTL2_II_DCI I/O Standard
-- /___/   /\     Filename : IBUFG_SSTL2_II_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:40 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_SSTL2_II_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_SSTL2_II_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_SSTL2_II_DCI;

architecture IBUFG_SSTL2_II_DCI_V of IBUFG_SSTL2_II_DCI is
begin
  O <= TO_X01(I);
end IBUFG_SSTL2_II_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl3_i.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with SSTL3_I I/O Standard
-- /___/   /\     Filename : IBUFG_SSTL3_I.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:40 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_SSTL3_I -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_SSTL3_I is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_SSTL3_I;

architecture IBUFG_SSTL3_I_V of IBUFG_SSTL3_I is
begin
  O <= TO_X01(I);
end IBUFG_SSTL3_I_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl3_i_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with SSTL3_I_DCI I/O Standard
-- /___/   /\     Filename : IBUFG_SSTL3_I_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:40 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_SSTL3_I_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_SSTL3_I_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_SSTL3_I_DCI;

architecture IBUFG_SSTL3_I_DCI_V of IBUFG_SSTL3_I_DCI is
begin
  O <= TO_X01(I);
end IBUFG_SSTL3_I_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl3_ii.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with SSTL3_II I/O Standard
-- /___/   /\     Filename : IBUFG_SSTL3_II.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:40 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_SSTL3_II -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_SSTL3_II is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_SSTL3_II;

architecture IBUFG_SSTL3_II_V of IBUFG_SSTL3_II is
begin
  O <= TO_X01(I);
end IBUFG_SSTL3_II_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl3_ii_dci.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Input Clock Buffer with SSTL3_II_DCI I/O Standard
-- /___/   /\     Filename : IBUFG_SSTL3_II_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:40 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFG_SSTL3_II_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFG_SSTL3_II_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end IBUFG_SSTL3_II_DCI;

architecture IBUFG_SSTL3_II_DCI_V of IBUFG_SSTL3_II_DCI is
begin
  O <= TO_X01(I);
end IBUFG_SSTL3_II_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds.vhd,v 1.9 2007/07/26 23:51:52 fphillip Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Clock Buffer
-- /___/   /\     Filename : IBUFGDS.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:40 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    07/26/07 - Add else to handle x case for output (CR 424214).
-- End Revision

----- CELL IBUFGDS -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFGDS is
  generic(
      CAPACITANCE : string  := "DONT_CARE";
      DIFF_TERM   : boolean :=  FALSE;
      IBUF_DELAY_VALUE : string := "0";          
      IOSTANDARD  : string  := "DEFAULT"
    );

  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFGDS;

architecture IBUFGDS_V of IBUFGDS is
begin
  prcs_init : process
  variable FIRST_TIME        : boolean    := TRUE;
  begin

     If(FIRST_TIME = true) then

        if((CAPACITANCE = "LOW") or
           (CAPACITANCE = "NORMAL") or
           (CAPACITANCE = "DONT_CARE")) then
           FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The Legal values for CAPACITANCE are LOW, NORMAL or DONT_CARE"
           severity Failure;
        end if;

        if((DIFF_TERM = TRUE) or
           (DIFF_TERM = FALSE)) then
           FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The Legal values for DIFF_TERM are TRUE or FALSE"
           severity Failure;
        end if;

--   
        if((IBUF_DELAY_VALUE = "0") or (IBUF_DELAY_VALUE = "1") or 
          (IBUF_DELAY_VALUE = "2")  or (IBUF_DELAY_VALUE = "3") or
          (IBUF_DELAY_VALUE = "4")  or (IBUF_DELAY_VALUE = "5") or
          (IBUF_DELAY_VALUE = "6")  or (IBUF_DELAY_VALUE = "7") or
          (IBUF_DELAY_VALUE = "8")  or (IBUF_DELAY_VALUE = "9") or
          (IBUF_DELAY_VALUE = "10") or (IBUF_DELAY_VALUE = "11") or
          (IBUF_DELAY_VALUE = "12") or (IBUF_DELAY_VALUE = "13") or
          (IBUF_DELAY_VALUE = "14") or (IBUF_DELAY_VALUE = "15") or
          (IBUF_DELAY_VALUE = "16")) then 
              FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The Legal values for IBUF_DELAY_VALUE are 0, 1, 2, ... , or 16. "
           severity Failure;
        end if;        

     end if;
     wait;
  end process prcs_init;

  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    elsif (I = 'Z' or I = 'X' or IB = 'Z' or IB ='X') then
        O <= 'X';
    end if;
  end process;
end IBUFGDS_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_blvds_25.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Clock Buffer with BLVDS_25 I/O Standard
-- /___/   /\     Filename : IBUFGDS_BLVDS_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:40 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFGDS_BLVDS_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFGDS_BLVDS_25 is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFGDS_BLVDS_25;

architecture IBUFGDS_BLVDS_25_V of IBUFGDS_BLVDS_25 is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFGDS_BLVDS_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_diff_out.vhd,v 1.5 2005/07/23 00:24:21 fphillip Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Clock Buffer with Differential Outputs
-- /___/   /\     Filename : IBUFGDS_DIFF_OUT.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:40 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFGDS_DIFF_OUT -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFGDS_DIFF_OUT is
  generic(
    IOSTANDARD                     : string := "LVDS_25"          
    );

   port(
      O                              :	out   STD_ULOGIC;
      OB                              :	out   STD_ULOGIC;      
      
      I                              :	in    STD_ULOGIC;
      IB                              :	in    STD_ULOGIC      
      );
end IBUFGDS_DIFF_OUT;

architecture IBUFGDS_DIFF_OUT_V of IBUFGDS_DIFF_OUT is
begin
   VITALBehavior : process (I, IB)
   begin
      if (I /= IB ) then
        O  <= TO_X01(I);
        OB <= TO_X01(NOT I);
      end if;
end process;
end IBUFGDS_DIFF_OUT_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_ldt_25.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Clock Buffer with LDT_25 I/O Standard
-- /___/   /\     Filename : IBUFGDS_LDT_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:41 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFGDS_LDT_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFGDS_LDT_25 is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFGDS_LDT_25;

architecture IBUFGDS_LDT_25_V of IBUFGDS_LDT_25 is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFGDS_LDT_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_lvds_25.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Clock Buffer with LVDS_25 I/O Standard
-- /___/   /\     Filename : IBUFGDS_LVDS_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:41 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFGDS_LVDS_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFGDS_LVDS_25 is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFGDS_LVDS_25;

architecture IBUFGDS_LVDS_25_V of IBUFGDS_LVDS_25 is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFGDS_LVDS_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_lvds_25_dci.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Clock Buffer with LVDS_25_DCI I/O Standard
-- /___/   /\     Filename : IBUFGDS_LVDS_25_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:41 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFGDS_LVDS_25_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFGDS_LVDS_25_DCI is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFGDS_LVDS_25_DCI;

architecture IBUFGDS_LVDS_25_DCI_V of IBUFGDS_LVDS_25_DCI is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFGDS_LVDS_25_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_lvds_33.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Clock Buffer with LVDS_33 I/O Standard
-- /___/   /\     Filename : IBUFGDS_LVDS_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:41 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFGDS_LVDS_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFGDS_LVDS_33 is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFGDS_LVDS_33;

architecture IBUFGDS_LVDS_33_V of IBUFGDS_LVDS_33 is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFGDS_LVDS_33_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_lvds_33_dci.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Clock Buffer with LVDS_33_DCI I/O Standard
-- /___/   /\     Filename : IBUFGDS_LVDS_33_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:41 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFGDS_LVDS_33_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFGDS_LVDS_33_DCI is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFGDS_LVDS_33_DCI;

architecture IBUFGDS_LVDS_33_DCI_V of IBUFGDS_LVDS_33_DCI is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFGDS_LVDS_33_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_lvdsext_25.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Clock Buffer with LVDSEXT_25 I/O Standard
-- /___/   /\     Filename : IBUFGDS_LVDSEXT_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:41 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFGDS_LVDSEXT_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFGDS_LVDSEXT_25 is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFGDS_LVDSEXT_25;

architecture IBUFGDS_LVDSEXT_25_V of IBUFGDS_LVDSEXT_25 is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFGDS_LVDSEXT_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_lvdsext_25_dci.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Clock Buffer with LVDSEXT_25_DCI I/O Standard
-- /___/   /\     Filename : IBUFGDS_LVDSEXT_25_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:41 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFGDS_LVDSEXT_25_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFGDS_LVDSEXT_25_DCI is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFGDS_LVDSEXT_25_DCI;

architecture IBUFGDS_LVDSEXT_25_DCI_V of IBUFGDS_LVDSEXT_25_DCI is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFGDS_LVDSEXT_25_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_lvdsext_33.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Clock Buffer with LVDSEXT_33 I/O Standard
-- /___/   /\     Filename : IBUFGDS_LVDSEXT_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:41 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFGDS_LVDSEXT_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFGDS_LVDSEXT_33 is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFGDS_LVDSEXT_33;

architecture IBUFGDS_LVDSEXT_33_V of IBUFGDS_LVDSEXT_33 is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFGDS_LVDSEXT_33_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_lvdsext_33_dci.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Clock Buffer with LVDSEXT_33_DCI I/O Standard
-- /___/   /\     Filename : IBUFGDS_LVDSEXT_33_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:41 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFGDS_LVDSEXT_33_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFGDS_LVDSEXT_33_DCI is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFGDS_LVDSEXT_33_DCI;

architecture IBUFGDS_LVDSEXT_33_DCI_V of IBUFGDS_LVDSEXT_33_DCI is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFGDS_LVDSEXT_33_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_lvpecl_25.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Clock Buffer with LVPECL_25 I/O Standard
-- /___/   /\     Filename : IBUFGDS_LVPECL_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:42 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFGDS_LVPECL_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFGDS_LVPECL_25 is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFGDS_LVPECL_25;

architecture IBUFGDS_LVPECL_25_V of IBUFGDS_LVPECL_25 is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFGDS_LVPECL_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_lvpecl_33.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Clock Buffer with LVPECL_33 I/O Standard
-- /___/   /\     Filename : IBUFGDS_LVPECL_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:42 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFGDS_LVPECL_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFGDS_LVPECL_33 is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFGDS_LVPECL_33;

architecture IBUFGDS_LVPECL_33_V of IBUFGDS_LVPECL_33 is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFGDS_LVPECL_33_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_ulvds_25.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Input Clock Buffer with ULVDS_25 I/O Standard
-- /___/   /\     Filename : IBUFGDS_ULVDS_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:42 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IBUFGDS_ULVDS_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IBUFGDS_ULVDS_25 is
  port(
    O : out std_ulogic;

    I  : in std_ulogic;
    IB : in std_ulogic
    );
end IBUFGDS_ULVDS_25;

architecture IBUFGDS_ULVDS_25_V of IBUFGDS_ULVDS_25 is
begin
  VitalBehavior : process (I, IB)
  begin
    if ((I = '1') and (IB = '0')) then
      O <= TO_X01(I);
    elsif ((I = '0') and (IB = '1')) then
      O <= TO_X01(I);
    end if;
  end process;
end IBUFGDS_ULVDS_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/icap_virtex2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Internal Configuration Access Port for Virtex2
-- /___/   /\     Filename : ICAP_VIRTEX2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:42 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL ICAP_VIRTEX2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity ICAP_VIRTEX2 is
  port(
    BUSY : out std_ulogic;
    O    : out std_logic_vector(7 downto 0);

    CE    : in std_ulogic;
    CLK   : in std_ulogic;
    I     : in std_logic_vector(7 downto 0);
    WRITE : in std_ulogic
    );
end ICAP_VIRTEX2;

architecture ICAP_VIRTEX2_V of ICAP_VIRTEX2 is
begin
end ICAP_VIRTEX2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ifddrcpe.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Dual Data Rate Input D Flip-Flop with Asynchronous Clear and Preset and Clock Enable
-- /___/   /\     Filename : IFDDRCPE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:42 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IFDDRCPE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity IFDDRCPE is
  port(
    Q0 : out std_ulogic;
    Q1 : out std_ulogic;

    C0  : in std_ulogic;
    C1  : in std_ulogic;
    CE  : in std_ulogic;
    CLR : in std_ulogic;
    D   : in std_ulogic;
    PRE : in std_ulogic
    );
end IFDDRCPE;

architecture IFDDRCPE_V of IFDDRCPE is
  signal D_in : std_ulogic := 'X';
begin

  I1 : IBUF
    port map (
      I => D,
      O => D_in
      );

  F0 : FDCPE
    generic map (
      INIT => '0' )
    port map (
      C    => C0,
      CE   => CE,
      CLR  => CLR,
      D    => D_in,
      PRE  => PRE,
      Q    => Q0
      );

  F1 : FDCPE
    generic map (
      INIT => '0' )
    port map (
      C    => C1,
      CE   => CE,
      CLR  => CLR,
      D    => D_in,
      PRE  => PRE,
      Q    => Q1
      );
end IFDDRCPE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ifddrrse.vhd,v 1.5 2006/08/09 01:01:48 fphillip Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Dual Data Rate Input D Flip-Flop with Synchronous Reset and SET and Clock Enable
-- /___/   /\     Filename : IFDDRRSE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:42 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    08/08/06 - CR 227386 fix
-- End Revision

----- CELL IFDDRRSE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity IFDDRRSE is
  port(
    Q0 : out std_ulogic;
    Q1 : out std_ulogic;

    C0 : in std_ulogic;
    C1 : in std_ulogic;
    CE : in std_ulogic;
    D  : in std_ulogic;
    R  : in std_ulogic;
    S  : in std_ulogic
    );
end IFDDRRSE;

architecture IFDDRRSE_V of IFDDRRSE is
  signal D_in : std_ulogic := 'X';
begin
  I1          : IBUF
    port map (
      I => D,
      O => D_in
      );

  F0 : FDRSE
    generic map (
      INIT => '0')
    port map (
      C    => C0,
      CE   => CE,
      R    => R,
      D    => D_in,
      S    => S,
      Q    => Q0
      );

  F1 : FDRSE
    generic map (
      INIT => '0')
    port map (
      C    => C1,
      CE   => CE,
      R    => R,
      D    => D_in,
      S    => S,
      Q    => Q1
      );
end IFDDRRSE_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/inv.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Inverter
-- /___/   /\     Filename : INV.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:42 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL INV -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity INV is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end INV;

architecture INV_V of INV is
begin
  O <= (not TO_X01(I));
end INV_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf.vhd,v 1.8 2005/03/10 22:45:34 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer
-- /___/   /\     Filename : IOBUF.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:43 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF is
  generic(
      CAPACITANCE : string     := "DONT_CARE";
      DRIVE       : integer    := 12;
      IBUF_DELAY_VALUE : string := "0";
      IFD_DELAY_VALUE  : string := "AUTO";
      IOSTANDARD  : string     := "DEFAULT";
      SLEW        : string     := "SLOW"
    );

  port(
    O  : out   std_ulogic;
    IO : inout std_ulogic;
    I  : in    std_ulogic;
    T  : in    std_ulogic
    );
end IOBUF;

architecture IOBUF_V of IOBUF is
begin
  prcs_init : process
  variable FIRST_TIME        : boolean    := TRUE;
  begin

     If(FIRST_TIME = true) then
        if((CAPACITANCE = "LOW") or
           (CAPACITANCE = "NORMAL") or
           (CAPACITANCE = "DONT_CARE")) then
           FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The Legal values for CAPACITANCE are LOW, NORMAL or DONT_CARE"
           severity Failure;
        end if;
--   
        if((IBUF_DELAY_VALUE = "0") or (IBUF_DELAY_VALUE = "1") or 
          (IBUF_DELAY_VALUE = "2")  or (IBUF_DELAY_VALUE = "3") or
          (IBUF_DELAY_VALUE = "4")  or (IBUF_DELAY_VALUE = "5") or
          (IBUF_DELAY_VALUE = "6")  or (IBUF_DELAY_VALUE = "7") or
          (IBUF_DELAY_VALUE = "8")  or (IBUF_DELAY_VALUE = "9") or
          (IBUF_DELAY_VALUE = "10") or (IBUF_DELAY_VALUE = "11") or
          (IBUF_DELAY_VALUE = "12") or (IBUF_DELAY_VALUE = "13") or
          (IBUF_DELAY_VALUE = "14") or (IBUF_DELAY_VALUE = "15") or
          (IBUF_DELAY_VALUE = "16")) then 
              FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The Legal values for IBUF_DELAY_VALUE are 0, 1, 2, ... , or 16. "
           severity Failure;
        end if;        

--   
        if((IFD_DELAY_VALUE = "AUTO") or (IFD_DELAY_VALUE = "auto") or 
          (IFD_DELAY_VALUE = "0")     or (IFD_DELAY_VALUE = "1") or 
          (IFD_DELAY_VALUE = "2")     or (IFD_DELAY_VALUE = "3") or
          (IFD_DELAY_VALUE = "4")     or (IFD_DELAY_VALUE = "5") or
          (IFD_DELAY_VALUE = "6")     or (IFD_DELAY_VALUE = "7") or
          (IFD_DELAY_VALUE = "8")) then
              FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The Legal values for IFD_DELAY_VALUE are AUTO, 0, 1, ... , or 8"
           severity Failure;
        end if;        

     end if;
     wait;
  end process prcs_init;

  VPKGBehavior     : process (IO, I, T)

  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_agp.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with AGP I/O Standard
-- /___/   /\     Filename : IOBUF_AGP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:43 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_AGP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_AGP is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );
end IOBUF_AGP;

architecture IOBUF_AGP_V of IOBUF_AGP is

begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_AGP_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_ctt.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with CTT I/O Standard
-- /___/   /\     Filename : IOBUF_CTT.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:43 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_CTT -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_CTT is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );
end IOBUF_CTT;

architecture IOBUF_CTT_V of IOBUF_CTT is
begin
  VPKGBehavior     : process (IO, I, T)
    variable IO_zd : std_ulogic;
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_CTT_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_f_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with Fast Slew 12 mA Drive
-- /___/   /\     Filename : IOBUF_F_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:43 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_F_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_F_12 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_F_12;

architecture IOBUF_F_12_V of IOBUF_F_12 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_F_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_f_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with Fast Slew 16 mA Drive
-- /___/   /\     Filename : IOBUF_F_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:43 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_F_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_F_16 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_F_16;

architecture IOBUF_F_16_V of IOBUF_F_16 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_F_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_f_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with Fast Slew 2 mA Drive
-- /___/   /\     Filename : IOBUF_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:43 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_F_2 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_F_2;

architecture IOBUF_F_2_V of IOBUF_F_2 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_F_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_f_24.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with Fast Slew 24 mA Drive
-- /___/   /\     Filename : IOBUF_F_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:43 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_F_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_F_24 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_F_24;

architecture IOBUF_F_24_V of IOBUF_F_24 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_F_24_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_f_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with Fast Slew 4 mA Drive
-- /___/   /\     Filename : IOBUF_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:43 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_F_4 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_F_4;

architecture IOBUF_F_4_V of IOBUF_F_4 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_F_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_f_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with Fast Slew 6 mA Drive
-- /___/   /\     Filename : IOBUF_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:43 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_F_6 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_F_6;

architecture IOBUF_F_6_V of IOBUF_F_6 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_F_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_f_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with Fast Slew 8 mA Drive
-- /___/   /\     Filename : IOBUF_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:44 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_F_8 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_F_8;

architecture IOBUF_F_8_V of IOBUF_F_8 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_F_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_gtl.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with GTL I/O Standard
-- /___/   /\     Filename : IOBUF_GTL.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:44 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_GTL -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_GTL is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_GTL;

architecture IOBUF_GTL_V of IOBUF_GTL is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_GTL_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_gtl_dci.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with GTL_DCI I/O Standard
-- /___/   /\     Filename : IOBUF_GTL_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:44 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_GTL_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_GTL_DCI is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_GTL_DCI;

architecture IOBUF_GTL_DCI_V of IOBUF_GTL_DCI is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_GTL_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_gtlp.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with GTLP I/O Standard
-- /___/   /\     Filename : IOBUF_GTLP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:44 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_GTLP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_GTLP is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_GTLP;

architecture IOBUF_GTLP_V of IOBUF_GTLP is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_GTLP_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_gtlp_dci.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with GTLP_DCI I/O Standard
-- /___/   /\     Filename : IOBUF_GTLP_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:44 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_GTLP_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_GTLP_DCI is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_GTLP_DCI;

architecture IOBUF_GTLP_DCI_V of IOBUF_GTLP_DCI is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_GTLP_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_i.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with HSTL_I I/O Standard
-- /___/   /\     Filename : IOBUF_HSTL_I.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:44 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_HSTL_I -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_HSTL_I is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_HSTL_I;

architecture IOBUF_HSTL_I_V of IOBUF_HSTL_I is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_HSTL_I_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_i_18.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with HSTL_I_18 I/O Standard
-- /___/   /\     Filename : IOBUF_HSTL_I_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:44 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_HSTL_I_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_HSTL_I_18 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_HSTL_I_18;

architecture IOBUF_HSTL_I_18_V of IOBUF_HSTL_I_18 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_HSTL_I_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_ii.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with HSTL_II I/O Standard
-- /___/   /\     Filename : IOBUF_HSTL_II.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:44 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_HSTL_II -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_HSTL_II is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_HSTL_II;

architecture IOBUF_HSTL_II_V of IOBUF_HSTL_II is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_HSTL_II_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_ii_18.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with HSTL_II_18 I/O Standard
-- /___/   /\     Filename : IOBUF_HSTL_II_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:44 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_HSTL_II_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_HSTL_II_18 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_HSTL_II_18;

architecture IOBUF_HSTL_II_18_V of IOBUF_HSTL_II_18 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_HSTL_II_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_ii_dci.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with HSTL_II_DCI I/O Standard
-- /___/   /\     Filename : IOBUF_HSTL_II_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:45 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_HSTL_II_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_HSTL_II_DCI is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_HSTL_II_DCI;

architecture IOBUF_HSTL_II_DCI_V of IOBUF_HSTL_II_DCI is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_HSTL_II_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_ii_dci_18.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with HSTL_II_DCI_18 I/O Standard
-- /___/   /\     Filename : IOBUF_HSTL_II_DCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:45 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_HSTL_II_DCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_HSTL_II_DCI_18 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_HSTL_II_DCI_18;

architecture IOBUF_HSTL_II_DCI_18_V of IOBUF_HSTL_II_DCI_18 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_HSTL_II_DCI_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_iii.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with HSTL_III I/O Standard
-- /___/   /\     Filename : IOBUF_HSTL_III.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:45 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_HSTL_III -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_HSTL_III is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_HSTL_III;

architecture IOBUF_HSTL_III_V of IOBUF_HSTL_III is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_HSTL_III_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_iii_18.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with HSTL_III_18 I/O Standard
-- /___/   /\     Filename : IOBUF_HSTL_III_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:45 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_HSTL_III_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_HSTL_III_18 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_HSTL_III_18;

architecture IOBUF_HSTL_III_18_V of IOBUF_HSTL_III_18 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_HSTL_III_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_iv.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with HSTL_IV I/O Standard
-- /___/   /\     Filename : IOBUF_HSTL_IV.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:45 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_HSTL_IV -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_HSTL_IV is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_HSTL_IV;

architecture IOBUF_HSTL_IV_V of IOBUF_HSTL_IV is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_HSTL_IV_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_iv_18.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with HSTL_IV_18 I/O Standard
-- /___/   /\     Filename : IOBUF_HSTL_IV_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:45 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_HSTL_IV_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_HSTL_IV_18 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_HSTL_IV_18;

architecture IOBUF_HSTL_IV_18_V of IOBUF_HSTL_IV_18 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_HSTL_IV_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_iv_dci.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with HSTL_IV_DCI I/O Standard
-- /___/   /\     Filename : IOBUF_HSTL_IV_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:45 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_HSTL_IV_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_HSTL_IV_DCI is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_HSTL_IV_DCI;

architecture IOBUF_HSTL_IV_DCI_V of IOBUF_HSTL_IV_DCI is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_HSTL_IV_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_iv_dci_18.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with HSTL_IV_DCI_18 I/O Standard
-- /___/   /\     Filename : IOBUF_HSTL_IV_DCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:45 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_HSTL_IV_DCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_HSTL_IV_DCI_18 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_HSTL_IV_DCI_18;

architecture IOBUF_HSTL_IV_DCI_18_V of IOBUF_HSTL_IV_DCI_18 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_HSTL_IV_DCI_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS12 I/O Standard
-- /___/   /\     Filename : IOBUF_LVCMOS12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:45 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS12 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS12;

architecture IOBUF_LVCMOS12_V of IOBUF_LVCMOS12 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos12_f_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS12 I/O Standard Fast Slew 2 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS12_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:46 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS12_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS12_F_2 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS12_F_2;

architecture IOBUF_LVCMOS12_F_2_V of IOBUF_LVCMOS12_F_2 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS12_F_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos12_f_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS12 I/O Standard Fast Slew 4 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS12_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:46 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS12_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS12_F_4 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS12_F_4;

architecture IOBUF_LVCMOS12_F_4_V of IOBUF_LVCMOS12_F_4 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS12_F_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos12_f_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS12 I/O Standard Fast Slew 6 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS12_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:46 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS12_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS12_F_6 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS12_F_6;

architecture IOBUF_LVCMOS12_F_6_V of IOBUF_LVCMOS12_F_6 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS12_F_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos12_f_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS12 I/O Standard Fast Slew 8 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS12_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:46 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS12_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS12_F_8 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS12_F_8;

architecture IOBUF_LVCMOS12_F_8_V of IOBUF_LVCMOS12_F_8 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS12_F_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos12_s_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS12 I/O Standard Slow Slew 2 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS12_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:46 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS12_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS12_S_2 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS12_S_2;

architecture IOBUF_LVCMOS12_S_2_V of IOBUF_LVCMOS12_S_2 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS12_S_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos12_s_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS12 I/O Standard Slow Slew 4 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS12_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:46 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS12_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS12_S_4 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS12_S_4;

architecture IOBUF_LVCMOS12_S_4_V of IOBUF_LVCMOS12_S_4 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS12_S_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos12_s_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS12 I/O Standard Slow Slew 6 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS12_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:46 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS12_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS12_S_6 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS12_S_6;

architecture IOBUF_LVCMOS12_S_6_V of IOBUF_LVCMOS12_S_6 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS12_S_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos12_s_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS12 I/O Standard Slow Slew 8 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS12_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:46 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS12_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS12_S_8 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS12_S_8;

architecture IOBUF_LVCMOS12_S_8_V of IOBUF_LVCMOS12_S_8 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS12_S_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS15 I/O Standard
-- /___/   /\     Filename : IOBUF_LVCMOS15.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:46 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS15 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS15 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS15;

architecture IOBUF_LVCMOS15_V of IOBUF_LVCMOS15 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS15_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_f_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS15 I/O Standard Fast Slew 12 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS15_F_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:47 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS15_F_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS15_F_12 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS15_F_12;

architecture IOBUF_LVCMOS15_F_12_V of IOBUF_LVCMOS15_F_12 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS15_F_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_f_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS15 I/O Standard Fast Slew 16 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS15_F_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:47 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS15_F_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS15_F_16 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS15_F_16;

architecture IOBUF_LVCMOS15_F_16_V of IOBUF_LVCMOS15_F_16 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS15_F_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_f_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS15 I/O Standard Fast Slew 2 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS15_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:47 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS15_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS15_F_2 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS15_F_2;

architecture IOBUF_LVCMOS15_F_2_V of IOBUF_LVCMOS15_F_2 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS15_F_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_f_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS15 I/O Standard Fast Slew 4 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS15_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:47 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS15_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS15_F_4 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS15_F_4;

architecture IOBUF_LVCMOS15_F_4_V of IOBUF_LVCMOS15_F_4 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS15_F_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_f_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS15 I/O Standard Fast Slew 6 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS15_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:47 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS15_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS15_F_6 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS15_F_6;

architecture IOBUF_LVCMOS15_F_6_V of IOBUF_LVCMOS15_F_6 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS15_F_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_f_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS15 I/O Standard Fast Slew 8 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS15_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:47 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS15_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS15_F_8 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS15_F_8;

architecture IOBUF_LVCMOS15_F_8_V of IOBUF_LVCMOS15_F_8 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS15_F_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_s_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS15 I/O Standard Slow Slew 12 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS15_S_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:47 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS15_S_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS15_S_12 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS15_S_12;

architecture IOBUF_LVCMOS15_S_12_V of IOBUF_LVCMOS15_S_12 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS15_S_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_s_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS15 I/O Standard Slow Slew 16 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS15_S_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:47 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS15_S_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS15_S_16 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS15_S_16;

architecture IOBUF_LVCMOS15_S_16_V of IOBUF_LVCMOS15_S_16 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS15_S_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_s_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS15 I/O Standard Slow Slew 2 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS15_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:47 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS15_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS15_S_2 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS15_S_2;

architecture IOBUF_LVCMOS15_S_2_V of IOBUF_LVCMOS15_S_2 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS15_S_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_s_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS15 I/O Standard Slow Slew 4 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS15_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:48 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS15_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS15_S_4 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS15_S_4;

architecture IOBUF_LVCMOS15_S_4_V of IOBUF_LVCMOS15_S_4 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS15_S_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_s_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS15 I/O Standard Slow Slew 6 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS15_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:48 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS15_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS15_S_6 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS15_S_6;

architecture IOBUF_LVCMOS15_S_6_V of IOBUF_LVCMOS15_S_6 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS15_S_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_s_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS15 I/O Standard Slow Slew 8 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS15_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:48 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS15_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS15_S_8 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS15_S_8;

architecture IOBUF_LVCMOS15_S_8_V of IOBUF_LVCMOS15_S_8 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS15_S_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS18 I/O Standard
-- /___/   /\     Filename : IOBUF_LVCMOS18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:48 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS18 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS18;

architecture IOBUF_LVCMOS18_V of IOBUF_LVCMOS18 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_f_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS18 I/O Standard Fast Slew 12 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS18_F_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:48 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS18_F_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS18_F_12 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS18_F_12;

architecture IOBUF_LVCMOS18_F_12_V of IOBUF_LVCMOS18_F_12 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS18_F_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_f_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS18 I/O Standard Fast Slew 16 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS18_F_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:48 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS18_F_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS18_F_16 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS18_F_16;

architecture IOBUF_LVCMOS18_F_16_V of IOBUF_LVCMOS18_F_16 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS18_F_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_f_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS18 I/O Standard Fast Slew 2 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS18_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:48 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS18_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS18_F_2 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS18_F_2;

architecture IOBUF_LVCMOS18_F_2_V of IOBUF_LVCMOS18_F_2 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS18_F_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_f_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS18 I/O Standard Fast Slew 4 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS18_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:48 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS18_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS18_F_4 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS18_F_4;

architecture IOBUF_LVCMOS18_F_4_V of IOBUF_LVCMOS18_F_4 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS18_F_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_f_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS18 I/O Standard Fast Slew 6 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS18_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:48 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS18_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS18_F_6 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS18_F_6;

architecture IOBUF_LVCMOS18_F_6_V of IOBUF_LVCMOS18_F_6 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS18_F_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_f_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS18 I/O Standard Fast Slew 8 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS18_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:49 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS18_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS18_F_8 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS18_F_8;

architecture IOBUF_LVCMOS18_F_8_V of IOBUF_LVCMOS18_F_8 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS18_F_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_s_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS18 I/O Standard Slow Slew 12 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS18_S_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:49 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS18_S_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS18_S_12 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS18_S_12;

architecture IOBUF_LVCMOS18_S_12_V of IOBUF_LVCMOS18_S_12 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS18_S_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_s_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS18 I/O Standard Slow Slew 16 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS18_S_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:49 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS18_S_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS18_S_16 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS18_S_16;

architecture IOBUF_LVCMOS18_S_16_V of IOBUF_LVCMOS18_S_16 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS18_S_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_s_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS18 I/O Standard Slow Slew 2 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS18_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:49 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS18_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS18_S_2 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS18_S_2;

architecture IOBUF_LVCMOS18_S_2_V of IOBUF_LVCMOS18_S_2 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS18_S_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_s_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS18 I/O Standard Slow Slew 4 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS18_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:49 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS18_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS18_S_4 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS18_S_4;

architecture IOBUF_LVCMOS18_S_4_V of IOBUF_LVCMOS18_S_4 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS18_S_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_s_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS18 I/O Standard Slow Slew 6 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS18_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:49 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS18_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS18_S_6 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS18_S_6;

architecture IOBUF_LVCMOS18_S_6_V of IOBUF_LVCMOS18_S_6 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS18_S_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_s_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS18 I/O Standard Slow Slew 8 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS18_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:49 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS18_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS18_S_8 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS18_S_8;

architecture IOBUF_LVCMOS18_S_8_V of IOBUF_LVCMOS18_S_8 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS18_S_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS2 I/O Standard
-- /___/   /\     Filename : IOBUF_LVCMOS2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:49 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS2 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS2;

architecture IOBUF_LVCMOS2_V of IOBUF_LVCMOS2 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS25 I/O Standard
-- /___/   /\     Filename : IOBUF_LVCMOS25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:50 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS25 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS25;

architecture IOBUF_LVCMOS25_V of IOBUF_LVCMOS25 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS25_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_f_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 12 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS25_F_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:50 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS25_F_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS25_F_12 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS25_F_12;

architecture IOBUF_LVCMOS25_F_12_V of IOBUF_LVCMOS25_F_12 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS25_F_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_f_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 16 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS25_F_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:50 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS25_F_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS25_F_16 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS25_F_16;

architecture IOBUF_LVCMOS25_F_16_V of IOBUF_LVCMOS25_F_16 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS25_F_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_f_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 2 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS25_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:50 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS25_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS25_F_2 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS25_F_2;

architecture IOBUF_LVCMOS25_F_2_V of IOBUF_LVCMOS25_F_2 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS25_F_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_f_24.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 24 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS25_F_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:50 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS25_F_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS25_F_24 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS25_F_24;

architecture IOBUF_LVCMOS25_F_24_V of IOBUF_LVCMOS25_F_24 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS25_F_24_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_f_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 4 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS25_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:50 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS25_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS25_F_4 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS25_F_4;

architecture IOBUF_LVCMOS25_F_4_V of IOBUF_LVCMOS25_F_4 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS25_F_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_f_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 6 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS25_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:50 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS25_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS25_F_6 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS25_F_6;

architecture IOBUF_LVCMOS25_F_6_V of IOBUF_LVCMOS25_F_6 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS25_F_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_f_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 8 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS25_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:51 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS25_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS25_F_8 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS25_F_8;

architecture IOBUF_LVCMOS25_F_8_V of IOBUF_LVCMOS25_F_8 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS25_F_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_s_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 12 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS25_S_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:51 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS25_S_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS25_S_12 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS25_S_12;

architecture IOBUF_LVCMOS25_S_12_V of IOBUF_LVCMOS25_S_12 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS25_S_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_s_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 16 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS25_S_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:51 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS25_S_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS25_S_16 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS25_S_16;

architecture IOBUF_LVCMOS25_S_16_V of IOBUF_LVCMOS25_S_16 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS25_S_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_s_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 2 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS25_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:51 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS25_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS25_S_2 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS25_S_2;

architecture IOBUF_LVCMOS25_S_2_V of IOBUF_LVCMOS25_S_2 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS25_S_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_s_24.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 24 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS25_S_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:51 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS25_S_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS25_S_24 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS25_S_24;

architecture IOBUF_LVCMOS25_S_24_V of IOBUF_LVCMOS25_S_24 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS25_S_24_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_s_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 4 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS25_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:51 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS25_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS25_S_4 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS25_S_4;

architecture IOBUF_LVCMOS25_S_4_V of IOBUF_LVCMOS25_S_4 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS25_S_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_s_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 6 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS25_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:51 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS25_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS25_S_6 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS25_S_6;

architecture IOBUF_LVCMOS25_S_6_V of IOBUF_LVCMOS25_S_6 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS25_S_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_s_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 8 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS25_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:51 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS25_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS25_S_8 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS25_S_8;

architecture IOBUF_LVCMOS25_S_8_V of IOBUF_LVCMOS25_S_8 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS25_S_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS33 I/O Standard
-- /___/   /\     Filename : IOBUF_LVCMOS33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:51 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS33 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS33;

architecture IOBUF_LVCMOS33_V of IOBUF_LVCMOS33 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS33_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_f_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 12 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS33_F_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:52 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS33_F_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS33_F_12 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS33_F_12;

architecture IOBUF_LVCMOS33_F_12_V of IOBUF_LVCMOS33_F_12 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS33_F_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_f_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 16 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS33_F_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:52 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS33_F_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS33_F_16 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS33_F_16;

architecture IOBUF_LVCMOS33_F_16_V of IOBUF_LVCMOS33_F_16 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS33_F_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_f_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 2 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS33_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:52 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS33_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS33_F_2 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS33_F_2;

architecture IOBUF_LVCMOS33_F_2_V of IOBUF_LVCMOS33_F_2 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS33_F_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_f_24.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 24 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS33_F_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:52 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS33_F_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS33_F_24 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS33_F_24;

architecture IOBUF_LVCMOS33_F_24_V of IOBUF_LVCMOS33_F_24 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS33_F_24_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_f_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 4 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS33_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:52 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS33_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS33_F_4 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS33_F_4;

architecture IOBUF_LVCMOS33_F_4_V of IOBUF_LVCMOS33_F_4 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS33_F_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_f_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 6 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS33_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:52 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS33_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS33_F_6 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS33_F_6;

architecture IOBUF_LVCMOS33_F_6_V of IOBUF_LVCMOS33_F_6 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS33_F_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_f_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 8 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS33_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:52 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS33_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS33_F_8 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS33_F_8;

architecture IOBUF_LVCMOS33_F_8_V of IOBUF_LVCMOS33_F_8 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS33_F_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_s_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 12 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS33_S_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:52 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS33_S_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS33_S_12 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS33_S_12;

architecture IOBUF_LVCMOS33_S_12_V of IOBUF_LVCMOS33_S_12 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS33_S_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_s_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 16 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS33_S_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:52 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS33_S_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS33_S_16 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS33_S_16;

architecture IOBUF_LVCMOS33_S_16_V of IOBUF_LVCMOS33_S_16 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS33_S_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_s_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 2 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS33_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:53 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS33_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS33_S_2 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS33_S_2;

architecture IOBUF_LVCMOS33_S_2_V of IOBUF_LVCMOS33_S_2 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS33_S_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_s_24.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 24 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS33_S_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:53 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS33_S_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS33_S_24 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS33_S_24;

architecture IOBUF_LVCMOS33_S_24_V of IOBUF_LVCMOS33_S_24 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS33_S_24_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_s_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 4 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS33_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:53 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS33_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS33_S_4 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS33_S_4;

architecture IOBUF_LVCMOS33_S_4_V of IOBUF_LVCMOS33_S_4 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS33_S_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_s_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 6 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS33_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:53 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS33_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS33_S_6 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS33_S_6;

architecture IOBUF_LVCMOS33_S_6_V of IOBUF_LVCMOS33_S_6 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS33_S_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_s_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 8 mA Drive
-- /___/   /\     Filename : IOBUF_LVCMOS33_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:53 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVCMOS33_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVCMOS33_S_8 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVCMOS33_S_8;

architecture IOBUF_LVCMOS33_S_8_V of IOBUF_LVCMOS33_S_8 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVCMOS33_S_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvdci_15.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVDCI_15 I/O Standard
-- /___/   /\     Filename : IOBUF_LVDCI_15.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:53 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVDCI_15 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVDCI_15 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVDCI_15;

architecture IOBUF_LVDCI_15_V of IOBUF_LVDCI_15 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVDCI_15_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvdci_18.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVDCI_18 I/O Standard
-- /___/   /\     Filename : IOBUF_LVDCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:53 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVDCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVDCI_18 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVDCI_18;

architecture IOBUF_LVDCI_18_V of IOBUF_LVDCI_18 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVDCI_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvdci_25.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVDCI_25 I/O Standard
-- /___/   /\     Filename : IOBUF_LVDCI_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:53 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVDCI_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVDCI_25 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVDCI_25;

architecture IOBUF_LVDCI_25_V of IOBUF_LVDCI_25 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVDCI_25_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvdci_33.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVDCI_33 I/O Standard
-- /___/   /\     Filename : IOBUF_LVDCI_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:53 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVDCI_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVDCI_33 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVDCI_33;

architecture IOBUF_LVDCI_33_V of IOBUF_LVDCI_33 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVDCI_33_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvdci_dv2_15.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVDCI_DV2_15 I/O Standard
-- /___/   /\     Filename : IOBUF_LVDCI_DV2_15.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:54 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVDCI_DV2_15 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVDCI_DV2_15 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVDCI_DV2_15;

architecture IOBUF_LVDCI_DV2_15_V of IOBUF_LVDCI_DV2_15 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVDCI_DV2_15_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvdci_dv2_18.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVDCI_DV2_18 I/O Standard
-- /___/   /\     Filename : IOBUF_LVDCI_DV2_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:54 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVDCI_DV2_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVDCI_DV2_18 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVDCI_DV2_18;

architecture IOBUF_LVDCI_DV2_18_V of IOBUF_LVDCI_DV2_18 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVDCI_DV2_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvdci_dv2_25.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVDCI_DV2_25 I/O Standard
-- /___/   /\     Filename : IOBUF_LVDCI_DV2_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:54 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVDCI_DV2_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVDCI_DV2_25 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVDCI_DV2_25;

architecture IOBUF_LVDCI_DV2_25_V of IOBUF_LVDCI_DV2_25 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVDCI_DV2_25_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvdci_dv2_33.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVDCI_DV2_33 I/O Standard
-- /___/   /\     Filename : IOBUF_LVDCI_DV2_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:54 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVDCI_DV2_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVDCI_DV2_33 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVDCI_DV2_33;

architecture IOBUF_LVDCI_DV2_33_V of IOBUF_LVDCI_DV2_33 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVDCI_DV2_33_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvds.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVDS I/O Standard
-- /___/   /\     Filename : IOBUF_LVDS.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:54 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVDS -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVDS is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVDS;

architecture IOBUF_LVDS_V of IOBUF_LVDS is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVDS_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvpecl.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVPECL I/O Standard
-- /___/   /\     Filename : IOBUF_LVPECL.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:54 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVPECL -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVPECL is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVPECL;

architecture IOBUF_LVPECL_V of IOBUF_LVPECL is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVPECL_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVTTL I/O Standard
-- /___/   /\     Filename : IOBUF_LVTTL.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:54 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVTTL -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVTTL is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVTTL;

architecture IOBUF_LVTTL_V of IOBUF_LVTTL is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVTTL_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_f_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 12 mA Drive
-- /___/   /\     Filename : IOBUF_LVTTL_F_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:54 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVTTL_F_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVTTL_F_12 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVTTL_F_12;

architecture IOBUF_LVTTL_F_12_V of IOBUF_LVTTL_F_12 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVTTL_F_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_f_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 16 mA Drive
-- /___/   /\     Filename : IOBUF_LVTTL_F_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:54 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVTTL_F_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVTTL_F_16 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVTTL_F_16;

architecture IOBUF_LVTTL_F_16_V of IOBUF_LVTTL_F_16 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVTTL_F_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_f_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 2 mA Drive
-- /___/   /\     Filename : IOBUF_LVTTL_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:55 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVTTL_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVTTL_F_2 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVTTL_F_2;

architecture IOBUF_LVTTL_F_2_V of IOBUF_LVTTL_F_2 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVTTL_F_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_f_24.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 24 mA Drive
-- /___/   /\     Filename : IOBUF_LVTTL_F_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:55 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVTTL_F_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVTTL_F_24 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVTTL_F_24;

architecture IOBUF_LVTTL_F_24_V of IOBUF_LVTTL_F_24 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVTTL_F_24_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_f_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 4 mA Drive
-- /___/   /\     Filename : IOBUF_LVTTL_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:55 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVTTL_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVTTL_F_4 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVTTL_F_4;

architecture IOBUF_LVTTL_F_4_V of IOBUF_LVTTL_F_4 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVTTL_F_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_f_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 6 mA Drive
-- /___/   /\     Filename : IOBUF_LVTTL_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:55 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVTTL_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVTTL_F_6 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVTTL_F_6;

architecture IOBUF_LVTTL_F_6_V of IOBUF_LVTTL_F_6 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVTTL_F_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_f_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 8 mA Drive
-- /___/   /\     Filename : IOBUF_LVTTL_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:55 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVTTL_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVTTL_F_8 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVTTL_F_8;

architecture IOBUF_LVTTL_F_8_V of IOBUF_LVTTL_F_8 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVTTL_F_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_s_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 12 mA Drive
-- /___/   /\     Filename : IOBUF_LVTTL_S_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:55 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVTTL_S_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVTTL_S_12 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVTTL_S_12;

architecture IOBUF_LVTTL_S_12_V of IOBUF_LVTTL_S_12 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVTTL_S_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_s_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 16 mA Drive
-- /___/   /\     Filename : IOBUF_LVTTL_S_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:55 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVTTL_S_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVTTL_S_16 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVTTL_S_16;

architecture IOBUF_LVTTL_S_16_V of IOBUF_LVTTL_S_16 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVTTL_S_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_s_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 2 mA Drive
-- /___/   /\     Filename : IOBUF_LVTTL_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:55 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVTTL_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVTTL_S_2 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVTTL_S_2;

architecture IOBUF_LVTTL_S_2_V of IOBUF_LVTTL_S_2 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVTTL_S_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_s_24.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 24 mA Drive
-- /___/   /\     Filename : IOBUF_LVTTL_S_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVTTL_S_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVTTL_S_24 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVTTL_S_24;

architecture IOBUF_LVTTL_S_24_V of IOBUF_LVTTL_S_24 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVTTL_S_24_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_s_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 4 mA Drive
-- /___/   /\     Filename : IOBUF_LVTTL_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVTTL_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVTTL_S_4 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVTTL_S_4;

architecture IOBUF_LVTTL_S_4_V of IOBUF_LVTTL_S_4 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVTTL_S_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_s_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 6 mA Drive
-- /___/   /\     Filename : IOBUF_LVTTL_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVTTL_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVTTL_S_6 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVTTL_S_6;

architecture IOBUF_LVTTL_S_6_V of IOBUF_LVTTL_S_6 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVTTL_S_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_s_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 8 mA Drive
-- /___/   /\     Filename : IOBUF_LVTTL_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_LVTTL_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_LVTTL_S_8 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_LVTTL_S_8;

architecture IOBUF_LVTTL_S_8_V of IOBUF_LVTTL_S_8 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_LVTTL_S_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_pci33_3.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with PCI33_3 I/O Standard
-- /___/   /\     Filename : IOBUF_PCI33_3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_PCI33_3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_PCI33_3 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_PCI33_3;

architecture IOBUF_PCI33_3_V of IOBUF_PCI33_3 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_PCI33_3_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_pci33_5.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with PCI33_5 I/O Standard
-- /___/   /\     Filename : IOBUF_PCI33_5.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_PCI33_5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_PCI33_5 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_PCI33_5;

architecture IOBUF_PCI33_5_V of IOBUF_PCI33_5 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_PCI33_5_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_pci66_3.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with PCI66_3 I/O Standard
-- /___/   /\     Filename : IOBUF_PCI66_3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_PCI66_3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_PCI66_3 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_PCI66_3;

architecture IOBUF_PCI66_3_V of IOBUF_PCI66_3 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_PCI66_3_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_pcix.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with PCIX I/O Standard
-- /___/   /\     Filename : IOBUF_PCIX.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_PCIX -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_PCIX is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_PCIX;

architecture IOBUF_PCIX_V of IOBUF_PCIX is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_PCIX_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_pcix66_3.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with PCIX66_3 I/O Standard
-- /___/   /\     Filename : IOBUF_PCIX66_3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_PCIX66_3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_PCIX66_3 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_PCIX66_3;

architecture IOBUF_PCIX66_3_V of IOBUF_PCIX66_3 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_PCIX66_3_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_s_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with Slow Slew 12 mA Drive
-- /___/   /\     Filename : IOBUF_S_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:57 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_S_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_S_12 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_S_12;

architecture IOBUF_S_12_V of IOBUF_S_12 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_S_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_s_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with Slow Slew 16 mA Drive
-- /___/   /\     Filename : IOBUF_S_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:57 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_S_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_S_16 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_S_16;

architecture IOBUF_S_16_V of IOBUF_S_16 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_S_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_s_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with Slow Slew 2 mA Drive
-- /___/   /\     Filename : IOBUF_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:57 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_S_2 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_S_2;

architecture IOBUF_S_2_V of IOBUF_S_2 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_S_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_s_24.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with Slow Slew 24 mA Drive
-- /___/   /\     Filename : IOBUF_S_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:57 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_S_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_S_24 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_S_24;

architecture IOBUF_S_24_V of IOBUF_S_24 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_S_24_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_s_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with Slow Slew 4 mA Drive
-- /___/   /\     Filename : IOBUF_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:57 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_S_4 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_S_4;

architecture IOBUF_S_4_V of IOBUF_S_4 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_S_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_s_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with Slow Slew 6 mA Drive
-- /___/   /\     Filename : IOBUF_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:57 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_S_6 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_S_6;

architecture IOBUF_S_6_V of IOBUF_S_6 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_S_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_s_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with Slow Slew 8 mA Drive
-- /___/   /\     Filename : IOBUF_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:57 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_S_8 is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_S_8;

architecture IOBUF_S_8_V of IOBUF_S_8 is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_S_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_sstl18_i.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with SSTL18_I I/O Standard
-- /___/   /\     Filename : IOBUF_SSTL18_I.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:57 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_SSTL18_I -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_SSTL18_I is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_SSTL18_I;

architecture IOBUF_SSTL18_I_V of IOBUF_SSTL18_I is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_SSTL18_I_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_sstl18_ii.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with SSTL18_II I/O Standard
-- /___/   /\     Filename : IOBUF_SSTL18_II.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:57 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_SSTL18_II -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_SSTL18_II is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_SSTL18_II;

architecture IOBUF_SSTL18_II_V of IOBUF_SSTL18_II is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_SSTL18_II_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_sstl18_ii_dci.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with SSTL18_II_DCI I/O Standard
-- /___/   /\     Filename : IOBUF_SSTL18_II_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:58 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_SSTL18_II_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_SSTL18_II_DCI is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_SSTL18_II_DCI;

architecture IOBUF_SSTL18_II_DCI_V of IOBUF_SSTL18_II_DCI is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_SSTL18_II_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_sstl2_i.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with SSTL2_I I/O Standard
-- /___/   /\     Filename : IOBUF_SSTL2_I.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:58 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_SSTL2_I -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_SSTL2_I is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_SSTL2_I;

architecture IOBUF_SSTL2_I_V of IOBUF_SSTL2_I is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_SSTL2_I_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_sstl2_ii.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with SSTL2_II I/O Standard
-- /___/   /\     Filename : IOBUF_SSTL2_II.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:58 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_SSTL2_II -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_SSTL2_II is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_SSTL2_II;

architecture IOBUF_SSTL2_II_V of IOBUF_SSTL2_II is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_SSTL2_II_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_sstl2_ii_dci.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with SSTL2_II_DCI I/O Standard
-- /___/   /\     Filename : IOBUF_SSTL2_II_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:58 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_SSTL2_II_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_SSTL2_II_DCI is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_SSTL2_II_DCI;

architecture IOBUF_SSTL2_II_DCI_V of IOBUF_SSTL2_II_DCI is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_SSTL2_II_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_sstl3_i.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with SSTL3_I I/O Standard
-- /___/   /\     Filename : IOBUF_SSTL3_I.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:58 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_SSTL3_I -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_SSTL3_I is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_SSTL3_I;

architecture IOBUF_SSTL3_I_V of IOBUF_SSTL3_I is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_SSTL3_I_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_sstl3_ii.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with SSTL3_II I/O Standard
-- /___/   /\     Filename : IOBUF_SSTL3_II.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:58 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_SSTL3_II -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_SSTL3_II is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_SSTL3_II;

architecture IOBUF_SSTL3_II_V of IOBUF_SSTL3_II is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_SSTL3_II_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_sstl3_ii_dci.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer with SSTL3_II_DCI I/O Standard
-- /___/   /\     Filename : IOBUF_SSTL3_II_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:58 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUF_SSTL3_II_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUF_SSTL3_II_DCI is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end IOBUF_SSTL3_II_DCI;

architecture IOBUF_SSTL3_II_DCI_V of IOBUF_SSTL3_II_DCI is
begin
  VPKGBehavior     : process (IO, I, T)
  begin
    O  <= TO_X01(IO);
    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;
  end process;
end IOBUF_SSTL3_II_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobufds.vhd,v 1.7 2007/07/26 23:51:52 fphillip Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Diffential Signaling I/O Buffer
-- /___/   /\     Filename : IOBUFDS.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:58 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    07/26/07 - Add else to handle x case for output (CR 424214).
-- End Revision


----- CELL IOBUFDS -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUFDS is
  generic(
    CAPACITANCE : string  := "DONT_CARE";
    IBUF_DELAY_VALUE : string := "0";
    IFD_DELAY_VALUE  : string := "AUTO";
    IOSTANDARD  : string  := "DEFAULT"
    );

  port(
    O : out std_ulogic;

    IO  : inout std_ulogic;
    IOB : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );
end IOBUFDS;

architecture IOBUFDS_V of IOBUFDS is
begin

  prcs_init             : process
    variable FIRST_TIME : boolean := true;
  begin

    if(FIRST_TIME = true) then
      if((CAPACITANCE = "LOW") or
         (CAPACITANCE = "NORMAL") or
         (CAPACITANCE = "DONT_CARE")) then
        FIRST_TIME := false;
      else
        assert false
          report "Attribute Syntax Error : The allowed values for CAPACITANCE are LOW, NORMAL or DONT_CARE"
          severity failure;
      end if;
    end if;

--   
        if((IBUF_DELAY_VALUE = "0") or (IBUF_DELAY_VALUE = "1") or 
          (IBUF_DELAY_VALUE = "2")  or (IBUF_DELAY_VALUE = "3") or
          (IBUF_DELAY_VALUE = "4")  or (IBUF_DELAY_VALUE = "5") or
          (IBUF_DELAY_VALUE = "6")  or (IBUF_DELAY_VALUE = "7") or
          (IBUF_DELAY_VALUE = "8")  or (IBUF_DELAY_VALUE = "9") or
          (IBUF_DELAY_VALUE = "10") or (IBUF_DELAY_VALUE = "11") or
          (IBUF_DELAY_VALUE = "12") or (IBUF_DELAY_VALUE = "13") or
          (IBUF_DELAY_VALUE = "14") or (IBUF_DELAY_VALUE = "15") or
          (IBUF_DELAY_VALUE = "16")) then 
              FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The Legal values for IBUF_DELAY_VALUE are 0, 1, 2, ... , or 16. "
           severity Failure;
        end if;        

--   
        if((IFD_DELAY_VALUE = "AUTO") or (IFD_DELAY_VALUE = "auto") or 
          (IFD_DELAY_VALUE = "0")     or (IFD_DELAY_VALUE = "1") or 
          (IFD_DELAY_VALUE = "2")     or (IFD_DELAY_VALUE = "3") or
          (IFD_DELAY_VALUE = "4")     or (IFD_DELAY_VALUE = "5") or
          (IFD_DELAY_VALUE = "6")     or (IFD_DELAY_VALUE = "7") or
          (IFD_DELAY_VALUE = "8")) then
              FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The Legal values for IFD_DELAY_VALUE are AUTO, 0, 1, ... , or 8"
           severity Failure;
        end if;        

    wait;
  end process prcs_init;

  VPKGBehavior : process (IO, IOB, I, T)
  begin

--    if (IO /= IOB ) then
--      O <= TO_X01(IO);
--    else
--      O <= 'X';
--    end if;
    
    if (IO = 'X' or IOB = 'X' ) then
       O <= 'X';  
    elsif (IO /= IOB ) then
      O <= TO_X01(IO);
    else
      O <= 'X';
    end if;

    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;

    if ((T = '1') or (T = 'H')) then
      IOB <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if (((not I) = '1') or ((not I) = 'H')) then
        IOB <= '1';
      elsif (((not I) = '0') or ((not I) = 'L')) then
        IOB <= '0';
      elsif ((not I) = 'U') then
        IOB <= 'U';
      else
        IOB <= 'X';  
      end if;
    elsif (T = 'U') then
      IOB <= 'U';          
    else                                      
      IOB <= 'X';  
    end if;        
  end process;


end IOBUFDS_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobufds_blvds_25.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Differential Signaling I/O Buffer with BLVDS_25 I/O Standard
-- /___/   /\     Filename : IOBUFDS_BLVDS_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:58 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUFDS_BLVDS_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUFDS_BLVDS_25 is

  port(
    O : out std_ulogic;

    IO  : inout std_ulogic;
    IOB : inout std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );
end IOBUFDS_BLVDS_25;

architecture IOBUFDS_BLVDS_25_V of IOBUFDS_BLVDS_25 is
begin

  VPKGBehavior : process (IO, IOB, I, T)
  begin
    if (IO /= IOB ) then
      O <= TO_X01(IO);
    else
      O <= 'X';
    end if;

    if ((T = '1') or (T = 'H')) then
      IO <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (T = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;

    if ((T = '1') or (T = 'H')) then
      IOB <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if (((not I) = '1') or ((not I) = 'H')) then
        IOB <= '1';
      elsif (((not I) = '0') or ((not I) = 'L')) then
        IOB <= '0';
      elsif ((not I) = 'U') then
        IOB <= 'U';
      else
        IOB <= 'X';  
      end if;
    elsif (T = 'U') then
      IOB <= 'U';          
    else                                      
      IOB <= 'X';  
    end if;            
  end process;

end IOBUFDS_BLVDS_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/keeper.vhd,v 1.7 2005/05/06 19:55:07 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Weak Keeper
-- /___/   /\     Filename : KEEPER.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:59 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    05/09/05 - Fixed CR#198911

----- CELL KEEPER -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity KEEPER is
  port(
    O : inout std_ulogic := 'W'
    );
end KEEPER;

architecture KEEPER_V of KEEPER is
begin
  process (O)
  begin
    if (O'event) then
      if (O = '1') then
        O <= 'H';
      elsif (O = '0') then
        O <= 'L';
      elsif (O = 'X') then
        O <= 'W';        
      end if;
    end if;
  end process;
end KEEPER_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ld.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Transparent Data Latch
-- /___/   /\     Filename : LD.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:59 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL LD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LD is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic := '0';

    D : in std_ulogic;
    G : in std_ulogic
    );
end LD;

architecture LD_V of LD is
begin
  VITALBehavior : process(D, G)
    begin
    if (G = '1') then
        Q <= D after 100 ps;        
    end if;
  end process;
end LD_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ld_1.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Transparent Data Latch with Inverted Gate
-- /___/   /\     Filename : LD_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:59 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL LD_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LD_1 is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic := '0';

    D : in std_ulogic;
    G : in std_ulogic
    );
end LD_1;

architecture LD_1_V of LD_1 is
begin
  VITALBehavior : process(D, G)
   begin
     if (G = '0') then
       Q <= D after 100 ps;        
     end if;          
  end process;
end LD_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldc.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Transparent Data Latch with Asynchronous Clear
-- /___/   /\     Filename : LDC.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:59 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL LDC -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LDC is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    CLR : in std_ulogic;
    D   : in std_ulogic;
    G   : in std_ulogic
    );
end LDC;

architecture LDC_V of LDC is
begin
  VITALBehavior : process(CLR, D, G)
  begin
    if (CLR = '1') then
      Q <= '0';
    elsif (G = '1') then
      Q <= D after 100 ps;        
    end if;
  end process;
end LDC_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldc_1.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Transparent Data Latch with Asynchronous Clear and Inverted Gate
-- /___/   /\     Filename : LDC_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:59 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL LDC_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LDC_1 is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    CLR : in std_ulogic;
    D   : in std_ulogic;
    G   : in std_ulogic
    );
end LDC_1;

architecture LDC_1_V of LDC_1 is
begin
  VITALBehavior : process(CLR, D, G)
  begin
    if (CLR = '1') then
      Q <= '0';
    elsif (G = '0') then
      Q <= D after 100 ps;        
    end if;
  end process;
end LDC_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldce.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Transparent Data Latch with Asynchronous Clear and Gate Enable
-- /___/   /\     Filename : LDCE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:00 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL LDCE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LDCE is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    CLR : in std_ulogic;
    D   : in std_ulogic;
    G   : in std_ulogic;
    GE  : in std_ulogic
    );
end LDCE;

architecture LDCE_V of LDCE is
begin

  VITALBehavior : process(CLR, D, G, GE)
  begin
    if (CLR = '1') then
      Q   <= '0';
    elsif ((GE = '1')  and (G = '1')) then
      Q <= D after 100 ps;        
    end if;
  end process;
end LDCE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldce_1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Transparent Data Latch with Asynchronous Clear, Gate Enable and Inverted Gate
-- /___/   /\     Filename : LDCE_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:00 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL LDCE_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LDCE_1 is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    CLR : in std_ulogic;
    D   : in std_ulogic;
    G   : in std_ulogic;
    GE  : in std_ulogic
    );
end LDCE_1;

architecture LDCE_1_V of LDCE_1 is
begin
  VITALBehavior : process(CLR, D, G, GE)
  begin
    if (CLR = '1') then
      Q   <= '0';
    elsif ((GE = '1') and (G = '0')) then
      Q <= D after 100 ps;        
    end if;
  end process;
end LDCE_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldcp.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Transparent Data Latch with Asynchronous Clear and Preset
-- /___/   /\     Filename : LDCP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:00 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL LDCP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LDCP is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    CLR : in std_ulogic;
    D   : in std_ulogic;
    G   : in std_ulogic;
    PRE : in std_ulogic
    );
end LDCP;

architecture LDCP_V of LDCP is
begin
  VITALBehavior : process(CLR, D, G, PRE)
  begin
    if (CLR = '1') then
      Q <= '0';
    elsif (PRE = '1') then
      Q <= '1';
    elsif (G = '1') then
      Q <= D after 100 ps;        
    end if;
  end process;
end LDCP_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldcp_1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Transparent Data Latch with Asynchronous Clear and Preset and Inverted Gate
-- /___/   /\     Filename : LDCP_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:00 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL LDCP_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LDCP_1 is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    CLR : in std_ulogic;
    D   : in std_ulogic;
    G   : in std_ulogic;
    PRE : in std_ulogic
    );
end LDCP_1;

architecture LDCP_1_V of LDCP_1 is
begin
  VITALBehavior : process(CLR, D, G, PRE)
  begin
    if (CLR = '1') then
      Q <= '0';
    elsif (PRE = '1') then
      Q <= '1';
    elsif (G = '0') then
      Q <= D after 100 ps;        
    end if;
  end process;
end LDCP_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldcpe.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Transparent Data Latch with Asynchronous Clear and Preset and Gate Enable
-- /___/   /\     Filename : LDCPE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:00 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL LDCPE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LDCPE is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    CLR : in std_ulogic;
    D   : in std_ulogic;
    G   : in std_ulogic;
    GE  : in std_ulogic;
    PRE : in std_ulogic
    );
end LDCPE;

architecture LDCPE_V of LDCPE is
begin
  VITALBehavior : process(CLR, D, G, GE, PRE)
    begin
    if (CLR = '1') then
      Q   <= '0';
    elsif (PRE = '1') then
      Q   <= '1';
    elsif ((GE = '1') and (G = '1'))then
      Q <= D after 100 ps;        
    end if;
  end process;
end LDCPE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldcpe_1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Transparent Data Latch with Asynchronous Clear and Preset, Gate Enable and Inverted Gate
-- /___/   /\     Filename : LDCPE_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:00 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL LDCPE_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LDCPE_1 is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    CLR : in std_ulogic;
    D   : in std_ulogic;
    G   : in std_ulogic;
    GE  : in std_ulogic;
    PRE : in std_ulogic
    );
end LDCPE_1;

architecture LDCPE_1_V of LDCPE_1 is
begin
  VITALBehavior : process(CLR, D, G, GE, PRE)
  begin
    if (CLR = '1') then
      Q   <= '0';
    elsif (PRE = '1') then
      Q   <= '1';
    elsif ((GE = '1') and (G = '0')) then
      Q <= D after 100 ps;        
    end if;
  end process;
end LDCPE_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lde.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Transparent Data Latch with Gate Enable
-- /___/   /\     Filename : LDE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:00 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL LDE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LDE is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic := '0';

    D  : in std_ulogic;
    G  : in std_ulogic;
    GE : in std_ulogic
    );
end LDE;

architecture LDE_V of LDE is
begin
  VITALBehavior : process(D, G, GE)
  begin
    if (GE = '1' and G = '1') then
        Q <= D after 100 ps;        
    end if;
  end process;
end LDE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lde_1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Transparent Data Latch with Gate Enable and Inverted Gate
-- /___/   /\     Filename : LDE_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:00 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL LDE_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LDE_1 is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic := '0';

    D  : in std_ulogic;
    G  : in std_ulogic;
    GE : in std_ulogic
    );
end LDE_1;

architecture LDE_1_V of LDE_1 is
begin
  VITALBehavior : process(D, G, GE)
  begin
    if (GE = '1' and G = '0') then
      Q <= D after 100 ps;        
    end if;
  end process;
end LDE_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldp.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Transparent Data Latch with Asynchronous Preset
-- /___/   /\     Filename : LDP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:01 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL LDP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LDP is
  generic(
    INIT : bit := '1'
    );

  port(
    Q : out std_ulogic;

    D   : in std_ulogic;
    G   : in std_ulogic;
    PRE : in std_ulogic
    );
end LDP;

architecture LDP_V of LDP is
begin
  VITALBehavior : process(D, G, PRE)
  begin
    if (PRE = '1') then
      Q <= '1';
    elsif (G = '1') then
      Q <= D after 100 ps;        
    end if;
  end process;
end LDP_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldp_1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Transparent Data Latch with Asynchronous Preset and Inverted Gate
-- /___/   /\     Filename : LDP_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:01 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL LDP_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LDP_1 is
  generic(
    INIT : bit := '1'
    );

  port(
    Q : out std_ulogic;

    D   : in std_ulogic;
    G   : in std_ulogic;
    PRE : in std_ulogic
    );
end LDP_1;

architecture LDP_1_V of LDP_1 is
begin
  VITALBehavior : process(D, G, PRE)
  begin
    if (PRE = '1') then
      Q <= '1';
    elsif (G = '0') then
      Q <= D after 100 ps;        
    end if;
  end process;
end LDP_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldpe.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Transparent Data Latch with Asynchronous Preset and Gate Enable
-- /___/   /\     Filename : LDPE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:01 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL LDPE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LDPE is
  generic(
    INIT : bit := '1'
    );

  port(
    Q : out std_ulogic;

    D   : in std_ulogic;
    G   : in std_ulogic;
    GE  : in std_ulogic;
    PRE : in std_ulogic
    );
end LDPE;

architecture LDPE_V of LDPE is
begin
  VITALBehavior : process(D, G, GE, PRE)
  begin
    if (PRE = '1') then
      Q   <= '1';
    elsif ((GE = '1') and (G = '1'))then
      Q <= D after 100 ps;        
    end if;
  end process;
end LDPE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldpe_1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Transparent Data Latch with Asynchronous Preset, Gate Enable and Inverted Gate
-- /___/   /\     Filename : LDPE_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:01 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL LDPE_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LDPE_1 is
  generic(
    INIT : bit := '1'
    );

  port(
    Q : out std_ulogic;

    D   : in std_ulogic;
    G   : in std_ulogic;
    GE  : in std_ulogic;
    PRE : in std_ulogic
    );
end LDPE_1;

architecture LDPE_1_V of LDPE_1 is
begin
  VITALBehavior : process(D, G, GE, PRE)
  begin
    if (PRE = '1') then
      Q   <= '1';
    elsif ((GE = '1') and (G = '0'))then
      Q <= D after 100 ps;        
    end if;
  end process;
end LDPE_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut1.vhd,v 1.6 2005/03/10 22:45:34 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  1-input Look-Up-Table with General Output
-- /___/   /\     Filename : LUT1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:01 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL LUT1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LUT1 is
  generic(
    INIT : bit_vector := X"0"
    );

  port(
    O : out std_ulogic;

    I0 : in std_ulogic
    );
end LUT1;

architecture LUT1_V of LUT1 is

begin
  VITALBehavior   : process (I0)
    variable INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT); 
  begin
    if (INIT_reg(0) = INIT_reg(1)) then
      O <= INIT_reg(0);
    elsif (I0 = '0') then
      O <= INIT_reg(0);
    elsif (I0 = '1') then
      O <= INIT_reg(1);      
    else
      O <= 'X';
    end if;
  end process;
end LUT1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut1_d.vhd,v 1.6 2005/03/10 22:45:34 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  1-input Look-Up-Table with Dual Output
-- /___/   /\     Filename : LUT1_D.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:01 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL LUT1_D -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LUT1_D is
  generic(
    INIT : bit_vector := X"0"
    );

  port(
    LO : out std_ulogic;
    O  : out std_ulogic;

    I0 : in std_ulogic
    );
end LUT1_D;

architecture LUT1_D_V of LUT1_D is
begin
  VITALBehavior     : process (I0)
    variable INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT);
  begin
    if (I0 = '0') then
      O <= INIT_reg(0);
      LO <= INIT_reg(0);      
    elsif (I0 = '1') then
      O <= INIT_reg(1);
      LO <= INIT_reg(1);      
    elsif (INIT_reg(0) = INIT_reg(1)) then
      O <= INIT_reg(0);
      LO <= INIT_reg(0);
    else
      O <= 'X';
      LO <= 'X';
    end if;    
  end process;
end LUT1_D_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut1_l.vhd,v 1.6 2005/03/10 22:45:34 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  1-input Look-Up-Table with Local Output
-- /___/   /\     Filename : LUT1_L.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:01 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL LUT1_L -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LUT1_L is
  generic(
    INIT : bit_vector := X"0"
    );

  port(
    LO : out std_ulogic;

    I0 : in std_ulogic
    );
end LUT1_L;

architecture LUT1_L_V of LUT1_L is
begin
  VITALBehavior    : process (I0)
    variable INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT);
  begin
    if (I0 = '0') then
      LO <= INIT_reg(0);
    elsif (I0 = '1') then
      LO <= INIT_reg(1);      
    elsif (INIT_reg(0) = INIT_reg(1)) then
      LO <= INIT_reg(0);
    else
      LO <= 'X';
    end if;    
  end process;
end LUT1_L_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut2.vhd,v 1.9 2006/04/21 23:39:47 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-input Look-Up-Table with General Output
-- /___/   /\     Filename : LUT2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:01 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    03/15/05 - Modified to handle the address unknown case.
--    03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842)
--    04/13/06 - Add address declaration. (CR229735)
-- End Revision

----- CELL LUT2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity LUT2 is
  generic(
    INIT : bit_vector := X"0"
    );

  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic
    );
end LUT2;

architecture LUT2_V of LUT2 is
begin
  VITALBehavior   : process (I0, I1)
    variable INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT);
    variable address : std_logic_vector(1 downto 0);
    variable address_int : integer := 0;
  begin
     address := I1 & I0;
     address_int := SLV_TO_INT(address(1 downto 0));

     if ((I1 xor I0) = '1' or (I1 xor I0) = '0') then
       O <= INIT_reg(address_int);
    else 
      if ((INIT_reg(0) = INIT_reg(1)) and (INIT_reg(2) = INIT_reg(3)) and 
                              (INIT_reg(0) = INIT_reg(2)))  then
        O <= INIT_reg(0);      
      elsif ((I1 = '0') and (INIT_reg(0) = INIT_reg(1)))  then
        O <= INIT_reg(0);      
        O <= INIT_reg(0);      
      elsif ((I1 = '1') and (INIT_reg(2) = INIT_reg(3)))  then
        O <= INIT_reg(2);      
      elsif ((I0 = '0') and (INIT_reg(0) = INIT_reg(2)))  then
        O <= INIT_reg(0);      
      elsif ((I0 = '1') and (INIT_reg(1)  = INIT_reg(3)))  then
        O <= INIT_reg(1);      
      else
        O <= 'X';
      end if;
    end if;
  end process;
end LUT2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut2_d.vhd,v 1.9 2006/04/21 23:39:47 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-input Look-Up-Table with Dual Output
-- /___/   /\     Filename : LUT2_D.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:01 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    03/15/05 - Modified to handle the address unknown case.
--    03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842)
--    04/13/06 - Add address declaration. (CR229735)
-- End Revision

----- CELL LUT2_D -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity LUT2_D is
  generic(
    INIT : bit_vector := X"0"
    );

  port(
    LO : out std_ulogic;
    O  : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic
    );
end LUT2_D;

architecture LUT2_D_V of LUT2_D is
    constant INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT);
begin
  VITALBehavior    : process (I0, I1)
    variable address : std_logic_vector(1 downto 0);
    variable address_int : integer := 0;
    variable tmp_o : std_ulogic;
  begin
     address := I1 & I0;
     address_int := SLV_TO_INT(address(1 downto 0));

     if ((I1 xor I0) = '1' or (I1 xor I0) = '0') then
       tmp_o := INIT_reg(address_int);
    else 
      if ((INIT_reg(0) = INIT_reg(1)) and (INIT_reg(2) = INIT_reg(3)) and 
                              (INIT_reg(0) = INIT_reg(2)))  then
        tmp_o := INIT_reg(0);
      elsif ((I1 = '0') and (INIT_reg(0) = INIT_reg(1)))  then
        tmp_o := INIT_reg(0);      
      elsif ((I1 = '1') and (INIT_reg(2) = INIT_reg(3)))  then
        tmp_o := INIT_reg(2);      
      elsif ((I0 = '0') and (INIT_reg(0) = INIT_reg(2)))  then
       tmp_o  := INIT_reg(0);      
      elsif ((I0 = '1') and (INIT_reg(1)  = INIT_reg(3)))  then
       tmp_o  := INIT_reg(1);      
      else
        tmp_o := 'X';
      end if;
     end if;
     O <=tmp_o; 
     LO <=tmp_o; 

  end process;
end LUT2_D_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut2_l.vhd,v 1.9 2006/04/21 23:39:47 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-input Look-Up-Table with Local Output
-- /___/   /\     Filename : LUT2_L.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:02 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    03/15/05 - Modified to handle the address unknown case.
--    03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842)
--    04/13/06 - Add address declaration. (CR229735)
-- End Revision

----- CELL LUT2_L -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity LUT2_L is
  generic(
    INIT : bit_vector := X"0"
    );

  port(
    LO : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic
    );
end LUT2_L;

architecture LUT2_L_V of LUT2_L is
begin
  VITALBehavior    : process (I0, I1)
    variable INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT);
    variable address : std_logic_vector(1 downto 0);
    variable address_int : integer := 0;
  begin
     address := I1 & I0;
     address_int := SLV_TO_INT(address(1 downto 0));

     if ((I1 xor I0) = '1' or (I1 xor I0) = '0') then
       LO <= INIT_reg(address_int);
    else 
        if ((INIT_reg(0) = INIT_reg(1)) and (INIT_reg(2) = INIT_reg(3)) and 
                              (INIT_reg(0) = INIT_reg(2)))  then
        LO <= INIT_reg(0);
      elsif ((I1 = '0') and (INIT_reg(0) = INIT_reg(1)))  then
        LO <= INIT_reg(0);      
      elsif ((I1 = '1') and (INIT_reg(2) = INIT_reg(3)))  then
        LO <= INIT_reg(2);      
      elsif ((I0 = '0') and (INIT_reg(0) = INIT_reg(2)))  then
        LO <= INIT_reg(0);      
      elsif ((I0 = '1') and (INIT_reg(1)  = INIT_reg(3)))  then
        LO <= INIT_reg(1);      
      else
        LO <= 'X';
      end if;
    end if;
  end process;
end LUT2_L_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut3.vhd,v 1.7 2006/03/11 00:58:14 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-input Look-Up-Table with General Output
-- /___/   /\     Filename : LUT3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:02 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    03/15/05 - Modified to handle the address unknown case.
--    03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842)
-- End Revision

----- CELL LUT3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity LUT3 is
  generic(
    INIT : bit_vector := X"00"
    );

  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic
    );
end LUT3;

architecture LUT3_V of LUT3 is

function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0))
                    return std_logic is
       variable lut4_mux4_o : std_logic;
  begin

       if (((s(1) xor s(0)) = '1')  or  ((s(1) xor s(0)) = '0')) then
           lut4_mux4_o := d(SLV_TO_INT(s));
       elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0'
                    and (d(0) xor d(2)) = '0') then
           lut4_mux4_o := d(0);
       elsif ((s(1) = '0') and (d(0) = d(1))) then
           lut4_mux4_o := d(0);
       elsif ((s(1) = '1') and (d(2) = d(3))) then
           lut4_mux4_o := d(2);
       elsif ((s(0) = '0') and (d(0) = d(2))) then
           lut4_mux4_o := d(0);
       elsif ((s(0) = '1') and (d(1) = d(3))) then
           lut4_mux4_o := d(1);
       else
           lut4_mux4_o := 'X';
      end if;

      return (lut4_mux4_o);
    
  end function lut4_mux4;
    constant INIT_reg : std_logic_vector(7 downto 0) := To_StdLogicVector(INIT);
begin
  VITALBehavior   : process (I0, I1, I2)
    variable I_reg    : std_logic_vector(2 downto 0);
  begin

    I_reg := TO_STDLOGICVECTOR( I2 & I1 & I0);

    if ((I2 xor I1 xor I0) = '1' or (I2 xor I1 xor I0) = '0') then
       O <= INIT_reg(SLV_TO_INT(I_reg));
    else
       O <= lut4_mux4(('0' & '0' & lut4_mux4(INIT_reg(7 downto 4), I_reg(1 downto 0)) &
            lut4_mux4(INIT_reg(3 downto 0), I_reg(1 downto 0))), ('0' & I_reg(2)));
    end if;
  end process;
end LUT3_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut3_d.vhd,v 1.7 2006/03/11 00:58:14 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-input Look-Up-Table with Dual Output
-- /___/   /\     Filename : LUT3_D.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:02 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    03/15/05 - Modified to handle the address unknown case.
--    03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842)
-- End Revision

----- CELL LUT3_D -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity LUT3_D is
  generic(
    INIT : bit_vector := X"00"
    );

  port(
    LO : out std_ulogic;
    O  : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic
    );
end LUT3_D;

architecture LUT3_D_V of LUT3_D is

function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0))
                    return std_logic is
       variable lut4_mux4_o : std_logic;
  begin

       if (((s(1) xor s(0)) = '1')  or  ((s(1) xor s(0)) = '0')) then
           lut4_mux4_o := d(SLV_TO_INT(s));
       elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0'
                    and (d(0) xor d(2)) = '0') then
           lut4_mux4_o := d(0);
       elsif ((s(1) = '0') and (d(0) = d(1))) then
           lut4_mux4_o := d(0);
       elsif ((s(1) = '1') and (d(2) = d(3))) then
           lut4_mux4_o := d(2);
       elsif ((s(0) = '0') and (d(0) = d(2))) then
           lut4_mux4_o := d(0);
       elsif ((s(0) = '1') and (d(1) = d(3))) then
           lut4_mux4_o := d(1);
       else
           lut4_mux4_o := 'X';
      end if;

      return (lut4_mux4_o);
    
  end function lut4_mux4;

    constant INIT_reg : std_logic_vector(7 downto 0) := To_StdLogicVector(INIT);
begin

  VITALBehavior    : process (I0, I1, I2)
    variable I_reg    : std_logic_vector(2 downto 0);
    variable tmp_o    : std_ulogic;
  begin

    I_reg := TO_STDLOGICVECTOR( I2 & I1 & I0);

    if ((I2 xor I1 xor I0) = '1' or (I2 xor I1 xor I0) = '0') then
       tmp_o := INIT_reg(SLV_TO_INT(I_reg));
    else
       tmp_o := lut4_mux4(('0' & '0' & lut4_mux4(INIT_reg(7 downto 4), I_reg(1 downto 0)) &
            lut4_mux4(INIT_reg(3 downto 0), I_reg(1 downto 0))), ('0' & I_reg(2)));
    end if;
    
    O <= tmp_o;
    LO <= tmp_o;

  end process;
end LUT3_D_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut3_l.vhd,v 1.7 2006/03/11 00:58:14 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-input Look-Up-Table with Local Output
-- /___/   /\     Filename : LUT3_L.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:02 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    03/15/05 - Modified to handle the address unknown case.
--    03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842)
-- End Revision

----- CELL LUT3_L -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity LUT3_L is
  generic(
    INIT : bit_vector := X"00"
    );

  port(
    LO : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic
    );
end LUT3_L;

architecture LUT3_L_V of LUT3_L is

function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0))
                    return std_logic is
       variable lut4_mux4_o : std_logic;
  begin

       if (((s(1) xor s(0)) = '1')  or  ((s(1) xor s(0)) = '0')) then
           lut4_mux4_o := d(SLV_TO_INT(s));
       elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0'
                    and (d(0) xor d(2)) = '0') then
           lut4_mux4_o := d(0);
       elsif ((s(1) = '0') and (d(0) = d(1))) then
           lut4_mux4_o := d(0);
       elsif ((s(1) = '1') and (d(2) = d(3))) then
           lut4_mux4_o := d(2);
       elsif ((s(0) = '0') and (d(0) = d(2))) then
           lut4_mux4_o := d(0);
       elsif ((s(0) = '1') and (d(1) = d(3))) then
           lut4_mux4_o := d(1);
       else
           lut4_mux4_o := 'X';
      end if;

      return (lut4_mux4_o);
    
  end function lut4_mux4;

    constant INIT_reg : std_logic_vector(7 downto 0) := To_StdLogicVector(INIT);
begin
  VITALBehavior    : process (I0, I1, I2)
    variable I_reg    : std_logic_vector(2 downto 0);
  begin

    I_reg := TO_STDLOGICVECTOR( I2 & I1 & I0);

    if ((I2 xor I1 xor I0) = '1' or (I2 xor I1 xor I0) = '0') then
       LO <= INIT_reg(SLV_TO_INT(I_reg));
    else
       LO <= lut4_mux4(('0' & '0' & lut4_mux4(INIT_reg(7 downto 4), I_reg(1 downto 0)) &
            lut4_mux4(INIT_reg(3 downto 0), I_reg(1 downto 0))), ('0' & I_reg(2)));
    end if;

  end process;
end LUT3_L_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut4.vhd,v 1.7 2006/03/11 00:58:14 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input Look-Up-Table with General Output
-- /___/   /\     Filename : LUT4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:02 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    03/15/05 - Modified to handle the address unknown case.
--    03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842)
-- End Revision

----- CELL LUT4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity LUT4 is
  generic(
    INIT : bit_vector := X"0000"
    );

  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic
    );
end LUT4;

architecture LUT4_V of LUT4 is

function lut4_mux4 (d :  std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) )
                    return std_logic is

       variable lut4_mux4_o : std_logic;
  begin
       
       if (((s(1) xor s(0)) = '1')  or  ((s(1) xor s(0)) = '0')) then
           lut4_mux4_o := d(SLV_TO_INT(s));
       elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0'
                    and (d(0) xor d(2)) = '0') then
           lut4_mux4_o := d(0);
       elsif ((s(1) = '0') and (d(0) = d(1))) then
           lut4_mux4_o := d(0);
       elsif ((s(1) = '1') and (d(2) = d(3))) then
           lut4_mux4_o := d(2);
       elsif ((s(0) = '0') and (d(0) = d(2))) then
           lut4_mux4_o := d(0);
       elsif ((s(0) = '1') and (d(1) = d(3))) then
           lut4_mux4_o := d(1);
       else
           lut4_mux4_o := 'X';
      end if;

      return (lut4_mux4_o);
     
  end function lut4_mux4;

    constant INIT_reg : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT);    
begin

  lut_p   : process (I0, I1, I2, I3)
--    variable INIT_reg : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT);    
    variable I_reg    : std_logic_vector(3 downto 0);
  begin

    I_reg := TO_STDLOGICVECTOR(I3 &  I2 & I1 & I0);

    if ((I3 xor I2 xor I1 xor I0) = '1' or (I3 xor I2 xor I1 xor I0) = '0') then
       O <= INIT_reg(SLV_TO_INT(I_reg));
    else 

       O <= lut4_mux4 ( 
            (lut4_mux4 ( INIT_reg(15 downto 12), I_reg(1 downto 0)) &
            lut4_mux4 ( INIT_reg(11 downto 8), I_reg(1 downto 0)) &
            lut4_mux4 ( INIT_reg(7 downto 4), I_reg(1 downto 0)) &
            lut4_mux4 ( INIT_reg(3 downto 0), I_reg(1 downto 0))), I_reg(3 downto 2));
 
    end if;
  end process;
end LUT4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut4_d.vhd,v 1.7 2006/03/11 00:58:14 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input Look-Up-Table with Dual Output
-- /___/   /\     Filename : LUT4_D.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:02 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    03/15/05 - Modified to handle the address unknown case.
--    03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842)
-- End Revision

----- CELL LUT4_D -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity LUT4_D is
  generic(
    INIT : bit_vector := X"0000"
    );

  port(
    LO : out std_ulogic;
    O  : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic
    );
end LUT4_D;

architecture LUT4_D_V of LUT4_D is

function lut4_mux4 (d :  std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) )
                    return std_logic is

       variable lut4_mux4_o : std_logic;
  begin
       
       if (((s(1) xor s(0)) = '1')  or  ((s(1) xor s(0)) = '0')) then
           lut4_mux4_o := d(SLV_TO_INT(s));
       elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0'
                    and (d(0) xor d(2)) = '0') then
           lut4_mux4_o := d(0);
       elsif ((s(1) = '0') and (d(0) = d(1))) then
           lut4_mux4_o := d(0);
       elsif ((s(1) = '1') and (d(2) = d(3))) then
           lut4_mux4_o := d(2);
       elsif ((s(0) = '0') and (d(0) = d(2))) then
           lut4_mux4_o := d(0);
       elsif ((s(0) = '1') and (d(1) = d(3))) then
           lut4_mux4_o := d(1);
       else
           lut4_mux4_o := 'X';
      end if;

      return (lut4_mux4_o);
     
  end function lut4_mux4;

    constant INIT_reg : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT);    
begin

  lut_p   : process (I0, I1, I2, I3)
    variable I_reg    : std_logic_vector(3 downto 0);
    variable tmp_o    : std_ulogic;
  begin

    I_reg := TO_STDLOGICVECTOR(I3 &  I2 & I1 & I0);

    if ((I3 xor I2 xor I1 xor I0) = '1' or (I3 xor I2 xor I1 xor I0) = '0') then
       tmp_o := INIT_reg(SLV_TO_INT(I_reg));
    else 
       tmp_o := lut4_mux4 ( 
            (lut4_mux4 ( INIT_reg(15 downto 12), I_reg(1 downto 0)) &
            lut4_mux4 ( INIT_reg(11 downto 8), I_reg(1 downto 0)) &
            lut4_mux4 ( INIT_reg(7 downto 4), I_reg(1 downto 0)) &
            lut4_mux4 ( INIT_reg(3 downto 0), I_reg(1 downto 0))), I_reg(3 downto 2));
    end if;
    O <= tmp_o;
    LO <= tmp_o;

  end process;
end LUT4_D_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut4_l.vhd,v 1.7 2006/03/11 00:58:14 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input Look-Up-Table with Local Output
-- /___/   /\     Filename : LUT4_L.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:02 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    03/15/05 - Modified to handle the address unknown case.
--    03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842)
-- End Revision

----- CELL LUT4_L -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity LUT4_L is
   generic(
      INIT : bit_vector := X"0000"
      );

   port(
      LO : out std_ulogic;

      I0 : in std_ulogic;
      I1 : in std_ulogic;
      I2 : in std_ulogic;
      I3 : in std_ulogic
      );
end LUT4_L;

architecture LUT4_L_V of LUT4_L is

function lut4_mux4 (d :  std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) )
                    return std_logic is

       variable lut4_mux4_o : std_logic;
  begin
       
       if (((s(1) xor s(0)) = '1')  or  ((s(1) xor s(0)) = '0')) then
           lut4_mux4_o := d(SLV_TO_INT(s));
       elsif ((d(0) = d(1)) and (d(2) = d(3)) and (d(0) = d(2))) then
           lut4_mux4_o := d(0);
       elsif ((s(1) = '0') and (d(0) = d(1))) then
           lut4_mux4_o := d(0);
       elsif ((s(1) = '1') and (d(2) = d(3))) then
           lut4_mux4_o := d(2);
       elsif ((s(0) = '0') and (d(0) = d(2))) then
           lut4_mux4_o := d(0);
       elsif ((s(0) = '1') and (d(1) = d(3))) then
           lut4_mux4_o := d(1);
       else
           lut4_mux4_o := 'X';
      end if;

      return (lut4_mux4_o);
     
  end function lut4_mux4;

    constant INIT_reg : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT);    
begin

  lut_p   : process (I0, I1, I2, I3)
    variable I_reg    : std_logic_vector(3 downto 0);
  begin

    I_reg := TO_STDLOGICVECTOR(I3 &  I2 & I1 & I0);

    if ((I3 xor I2 xor I1 xor I0) = '1' or (I3 xor I2 xor I1 xor I0) = '0') then
       LO <= INIT_reg(SLV_TO_INT(I_reg));
    else 
       LO <= lut4_mux4 ( 
            (lut4_mux4 ( INIT_reg(15 downto 12), I_reg(1 downto 0)) &
            lut4_mux4 ( INIT_reg(11 downto 8), I_reg(1 downto 0)) &
            lut4_mux4 ( INIT_reg(7 downto 4), I_reg(1 downto 0)) &
            lut4_mux4 ( INIT_reg(3 downto 0), I_reg(1 downto 0))), I_reg(3 downto 2));
    end if;
end process;
end LUT4_L_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/mult18x18.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  18X18 Signed Multiplier
-- /___/   /\     Filename : MULT18X18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:03 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL MULT18X18 -----

library IEEE;
use IEEE.std_logic_1164.all;

library unisim;
use unisim.Vpkg.all;

entity MULT18X18 is
    port (
	  P	: out std_logic_vector (35 downto 0);
          
          A	: in std_logic_vector (17 downto 0);
          B	: in std_logic_vector (17 downto 0)
          );
    
end MULT18X18;

architecture MULT18X18_V of MULT18X18 is

function INT_TO_SLV(ARG: integer; SIZE: integer) return std_logic_vector is

	variable result : std_logic_vector (SIZE-1 downto 0);
        variable temp : integer := ARG;
begin
	temp := ARG;
	for i in 0 to SIZE-1 loop
		if (temp mod 2) = 1 then
			result(i) := '1';
		else
			result(i) := '0';
		end if;
		if temp > 0 then
			temp := temp /2 ;
		elsif (temp > integer'low) then
			temp := (temp-1) / 2;
		else
			temp := temp / 2;
		end if;
	end loop;
	return result;
end;

function COMPLEMENT(ARG: std_logic_vector ) return std_logic_vector is

	variable 	RESULT : std_logic_vector (ARG'left downto 0);
	variable	found1 : std_ulogic := '0';
begin
		for i in  0 to ARG'left  loop
			if (found1 = '0') then
				RESULT(i) := ARG(i);
				if (ARG(i) = '1' ) then
					found1 := '1';
				end if;
			else
				RESULT(i) := not ARG(i);
			end if;
                end loop;
		return result;
end;

function VECPLUS(A, B: std_logic_vector ) return std_logic_vector is

	variable carry: std_ulogic;
        variable BV, sum: std_logic_vector(A'left downto 0);

begin

	if (A(A'left) = 'X' or B(B'left) = 'X') then
            sum := (others => 'X');
            return(sum);
        end if;
        carry := '0';
        BV := B;

        for i in 0 to A'left loop
            sum(i) := A(i) xor BV(i) xor carry;
            carry := (A(i) and BV(i)) or
                    (A(i) and carry) or
                    (carry and BV(i));
        end loop;
        return sum;
end;
 
begin

  VITALBehaviour : process (A, B)
    variable O_zd,O1_zd, O2_zd : std_logic_vector( A'length+B'length-1 downto 0);
    variable IA, IB1,IB2  : integer ;
    variable sign : std_ulogic := '0';
    variable A_i : std_logic_vector(A'left downto 0);
    variable B_i : std_logic_vector(B'left downto 0);

  begin

    if (Is_X(A) or Is_X(B) ) then
            O_zd := (others => 'X');
    else
       if (A(A'left) = '1' ) then
         A_i :=  complement(A);
       else 
         A_i := A;
       end if;

       if (B(B'left)  = '1') then
         B_i := complement(B);
       else
         B_i := B;
       end if;

        IA := SLV_TO_INT(A_i);
        IB1 := SLV_TO_INT(B_i (17 downto 9));
        IB2 := SLV_TO_INT(B_i (8 downto 0));


       O1_zd := INT_TO_SLV((IA * IB1), A'length+B'length);
	-- shift I1_zd 9 to the left
           for j in 0 to 8 loop
            O1_zd(A'length+B'length-1 downto 0) := O1_zd(A'length+B'length-2 downto 0) & '0';
           end loop;
       O2_zd := INT_TO_SLV((IA * IB2), A'length+B'length);
       O_zd  := VECPLUS(O1_zd, O2_zd);

       sign := A(A'left) xor B(B'left);
       if (sign = '1' ) then
              O_zd := complement(O_zd);
       end if;
    end if;
    P <= O_zd;
  end process VITALBehaviour;

end MULT18X18_V ;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/mult18x18s.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  18X18 Signed Registered Multiplier
-- /___/   /\     Filename : MULT18X18S.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:03 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL MULT18X18S -----

library IEEE;
use IEEE.std_logic_1164.all;

library unisim;
use unisim.Vpkg.all;

entity MULT18X18S is

  port (
    P  : out std_logic_vector (35 downto 0);

    A  : in std_logic_vector (17 downto 0);
    B  : in std_logic_vector (17 downto 0);
    C  : in std_ulogic;
    CE : in std_ulogic;
    R  : in std_ulogic
    );
end MULT18X18S;

architecture MULT18X18S_V of MULT18X18S is

  function INT_TO_SLV(ARG : integer; SIZE : integer) return std_logic_vector is

    variable result : std_logic_vector (SIZE-1 downto 0);
    variable temp   : integer := ARG;
  begin
    temp                      := ARG;
    for i in 0 to SIZE-1 loop
      if (temp mod 2) = 1 then
        result(i)             := '1';
      else
        result(i)             := '0';
      end if;
      if temp > 0 then
        temp                  := temp /2;
      elsif (temp > integer'low) then
        temp                  := (temp-1) / 2;
      else
        temp                  := temp / 2;
      end if;
    end loop;
    return result;
  end;

  function COMPLEMENT(ARG : std_logic_vector ) return std_logic_vector is

    variable RESULT : std_logic_vector (ARG'left downto 0);
    variable found1 : std_ulogic := '0';
  begin
    for i in 0 to ARG'left loop
      if (found1 = '0') then
        RESULT(i)                := ARG(i);
        if (ARG(i) = '1' ) then
          found1                 := '1';
        end if;
      else
        RESULT(i)                := not ARG(i);
      end if;
    end loop;
    return result;
  end;

  function VECPLUS(A, B : std_logic_vector ) return std_logic_vector is

    variable carry   : std_ulogic;
    variable BV, sum : std_logic_vector(A'left downto 0);

  begin

    if (A(A'left) = 'X' or B(B'left) = 'X') then
      sum := (others => 'X');
      return(sum);
    end if;
    carry := '0';
    BV    := B;

    for i in 0 to A'left loop
      sum(i) := A(i) xor BV(i) xor carry;
      carry  := (A(i) and BV(i)) or
                (A(i) and carry) or
                (carry and BV(i));
    end loop;
    return sum;
  end;

begin

  VITALBehaviour                : process (C)
    variable O_zd, O1_zd, O2_zd : std_logic_vector( A'length+B'length-1 downto 0);
    variable B1_zd, B2_zd       : bit_vector(A'length+B'length-1 downto 0);
    variable IA, IB1, Ib2       : integer;
    variable sign               : std_ulogic := '0';
    variable A_i                : std_logic_vector(A'left downto 0);
    variable B_i                : std_logic_vector(B'left downto 0);

  begin

    if (rising_edge(C)) then
      if (R = '1' ) then
        O_zd    := (others => '0');
      elsif (CE = '1' ) then
        if (Is_X(A) or Is_X(B) ) then
          O_zd  := (others => 'X');
        else
          if (A(A'left) = '1' ) then
            A_i := complement(A);
          else
            A_i := A;
          end if;

          if (B(B'left) = '1') then
            B_i := complement(B);
          else
            B_i := B;
          end if;

          IA  := SLV_TO_INT(A_i);
          IB1 := SLV_TO_INT(B_i (17 downto 9));
          IB2 := SLV_TO_INT(B_i (8 downto 0));


          O1_zd                                 := INT_TO_SLV((IA * IB1), A'length+B'length);
          for j in 0 to 8 loop
            O1_zd(A'length+B'length-1 downto 0) := O1_zd(A'length+B'length-2 downto 0) & '0';
          end loop;
          O2_zd                                 := INT_TO_SLV((IA * IB2), A'length+B'length);
          O_zd                                  := VECPLUS(O1_zd, O2_zd);

          sign   := A(A'left) xor B(B'left);
          if (sign = '1' ) then
            O_zd := complement(O_zd);
          end if;
        end if;
      end if;
    end if;
    P <= O_zd after 100 ps;
  end process VITALBehaviour;

end MULT18X18S_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/mult_and.vhd,v 1.5 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Fast Multiplier AND
-- /___/   /\     Filename : MULT_AND.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:03 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL MULT_AND -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MULT_AND is
  port(
    LO : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic
    );

end MULT_AND;

architecture MULT_AND_V of MULT_AND is
begin
  VITALBehavior : process (I1, I0)
  begin
    LO <= (I0 and I1) after 0 ps;
  end process;
end MULT_AND_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxcy.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-to-1 Multiplexer for Carry Logic with General Output
-- /___/   /\     Filename : MUXCY.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:03 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

--    08/23/07 - Handle S= X case. CR434611 
----- CELL MUXCY -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUXCY is
  port(
    O : out std_ulogic;

    CI : in std_ulogic;
    DI : in std_ulogic;
    S  : in std_ulogic
    );
end MUXCY;

architecture MUXCY_V of MUXCY is
begin
  VITALBehavior   : process (CI, DI, S)
  begin
    if (S = '0') then
      O <= DI;
    else
      O <= CI;      
    end if;
  end process;
end MUXCY_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxcy_d.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-to-1 Multiplexer for Carry Logic with Dual Output
-- /___/   /\     Filename : MUXCY_D.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:03 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

--    08/23/07 - Handle S= X case. CR434611 
----- CELL MUXCY_D -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUXCY_D is
  port(
    LO : out std_ulogic;
    O  : out std_ulogic;

    CI : in std_ulogic;
    DI : in std_ulogic;
    S  : in std_ulogic
    );
end MUXCY_D;

architecture MUXCY_D_V of MUXCY_D is
begin
  VITALBehavior    : process (CI, DI, S)
  begin
    if (S = '0') then
      O <= DI;
      LO <= DI;      
    else
      O <= CI;
      LO <= CI;            
    end if;    
  end process;
end MUXCY_D_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxcy_l.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-to-1 Multiplexer for Carry Logic with Local Output
-- /___/   /\     Filename : MUXCY_L.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:03 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

--    08/23/07 - Handle S= X case. CR434611 
----- CELL MUXCY_L -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUXCY_L is
  port(
    LO : out std_ulogic;

    CI : in std_ulogic;
    DI : in std_ulogic;
    S  : in std_ulogic
    );
end MUXCY_L;

architecture MUXCY_L_V of MUXCY_L is
begin
  VITALBehavior    : process (CI, DI, S)
  begin
    if (S = '0') then
      LO <= DI;
    else
      LO <= CI;      
    end if;    
  end process;
end MUXCY_L_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf5.vhd,v 1.6 2007/08/23 23:28:36 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-to-1 Lookup Table Multiplexer with General Output
-- /___/   /\     Filename : MUXF5.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:03 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    02/10/07 - When input same, output same for any sel value. (CR433761).
--    08/23/07 - Handle S= X case. CR434611 

----- CELL MUXF5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUXF5 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    S  : in std_ulogic
    );
end MUXF5;

architecture MUXF5_V of MUXF5 is
begin
  VITALBehavior   : process (I0, I1, S)
  begin
    if ( S = '1') then
      O <= I1;
    else
      O <= I0;      
    end if;    
  end process;
end MUXF5_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf5_d.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-to-1 Lookup Table Multiplexer with Dual Output
-- /___/   /\     Filename : MUXF5_D.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:03 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

--    08/23/07 - Handle S= X case. CR434611 
----- CELL MUXF5_D -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUXF5_D is
  port(
    LO : out std_ulogic;
    O  : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    S  : in std_ulogic
    );
end MUXF5_D;

architecture MUXF5_D_V of MUXF5_D is
begin
  VITALBehavior    : process (I0, I1, S)
  begin
    if (S = '0') then
      O <= I0;
      LO <= I0;      
    else
      O <= I1;
      LO <= I1;            
    end if;        
  end process;
end MUXF5_D_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf5_l.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-to-1 Lookup Table Multiplexer with Local Output
-- /___/   /\     Filename : MUXF5_L.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:03 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

--    08/23/07 - Handle S= X case. CR434611 
----- CELL MUXF5_L -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUXF5_L is
  port(
    LO : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    S  : in std_ulogic
    );
end MUXF5_L;

architecture MUXF5_L_V of MUXF5_L is
begin
  VITALBehavior    : process (I0, I1, S)
  begin
    if (S = '0') then
      LO <= I0;
    else
      LO <= I1;      
    end if;        
  end process;
end MUXF5_L_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf6.vhd,v 1.6 2007/08/23 23:28:36 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-to-1 Lookup Table Multiplexer with General Output
-- /___/   /\     Filename : MUXF6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:04 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

--    08/23/07 - Handle S= X case. CR434611 
----- CELL MUXF6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUXF6 is

  port(
    O  : out std_ulogic;
    
    I0 : in  std_ulogic;
    I1 : in  std_ulogic;
    S  : in  std_ulogic
    );
end MUXF6;

architecture MUXF6_V of MUXF6 is
begin
  VITALBehavior   : process (I0, I1, S)
  begin
    if (S = '0') then
      O <= I0;
    else
      O <= I1;      
    end if;        
  end process;
end MUXF6_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf6_d.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-to-1 Lookup Table Multiplexer with Dual Output
-- /___/   /\     Filename : MUXF6_D.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:04 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

--    08/23/07 - Handle S= X case. CR434611 
----- CELL MUXF6_D -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUXF6_D is
  port(
    LO : out std_ulogic;
    O  : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    S  : in std_ulogic
    );
end MUXF6_D;

architecture MUXF6_D_V of MUXF6_D is
begin
  VITALBehavior    : process (I0, I1, S)
  begin
    if (S = '0') then
      O <= I0;
      LO <= I0;      
    else
      O <= I1;
      LO <= I1;            
    end if;            
  end process;
end MUXF6_D_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf6_l.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-to-1 Lookup Table Multiplexer with Local Output
-- /___/   /\     Filename : MUXF6_L.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:04 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

--    08/23/07 - Handle S= X case. CR434611 
----- CELL MUXF6_L -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUXF6_L is
  port(
    LO : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    S  : in std_ulogic
    );
end MUXF6_L;

architecture MUXF6_L_V of MUXF6_L is
begin
  VITALBehavior    : process (I0, I1, S)
  begin
    if (S = '0') then
      LO <= I0;      
    else
      LO <= I1;            
    end if;                
  end process;
end MUXF6_L_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf7.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-to-1 Lookup Table Multiplexer with General Output
-- /___/   /\     Filename : MUXF7.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:04 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

--    08/23/07 - Handle S= X case. CR434611 
----- CELL MUXF7 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUXF7 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    S  : in std_ulogic
    );
end MUXF7;

architecture MUXF7_V of MUXF7 is
begin
  VITALBehavior   : process (I0, I1, S)
  begin
    if (S = '0') then
      O <= I0;      
    else
      O <= I1;            
    end if;                    
  end process;
end MUXF7_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf7_d.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-to-1 Lookup Table Multiplexer with Dual Output
-- /___/   /\     Filename : MUXF7_D.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:04 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

--    08/23/07 - Handle S= X case. CR434611 
----- CELL MUXF7_D -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUXF7_D is
  port(
    LO : out std_ulogic;
    O  : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    S  : in std_ulogic
    );
end MUXF7_D;

architecture MUXF7_D_V of MUXF7_D is
begin
  VITALBehavior    : process (I0, I1, S)
  begin
    if (S = '0') then
      O <= I0;
      LO <= I0;            
    else
      O <= I1;
      LO <= I1;                  
    end if;                    
  end process;
end MUXF7_D_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf7_l.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-to-1 Lookup Table Multiplexer with Local Output
-- /___/   /\     Filename : MUXF7_L.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:04 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

--    08/23/07 - Handle S= X case. CR434611 
----- CELL MUXF7_L -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUXF7_L is
  port(
    LO : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    S  : in std_ulogic
    );
end MUXF7_L;

architecture MUXF7_L_V of MUXF7_L is
begin
  VITALBehavior    : process (I0, I1, S)
    variable LO_zd : std_ulogic;
  begin
    if (S = '0') then
      LO <= I0;            
    else
      LO <= I1;                  
    end if;                        
  end process;
end MUXF7_L_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf8.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-to-1 Lookup Table Multiplexer with General Output
-- /___/   /\     Filename : MUXF8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:04 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

--    08/23/07 - Handle S= X case. CR434611 
----- CELL MUXF8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUXF8 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    S  : in std_ulogic
    );
end MUXF8;

architecture MUXF8_V of MUXF8 is
begin
  VITALBehavior   : process (I0, I1, S)
  begin
    if (S = '0') then
      O <= I0;            
    else
      O <= I1;                  
    end if;                            
  end process;
end MUXF8_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf8_d.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-to-1 Lookup Table Multiplexer with Dual Output
-- /___/   /\     Filename : MUXF8_D.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:04 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

--    08/23/07 - Handle S= X case. CR434611 
----- CELL MUXF8_D -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUXF8_D is
  port(
    LO : out std_ulogic;
    O  : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    S  : in std_ulogic
    );
end MUXF8_D;

architecture MUXF8_D_V of MUXF8_D is
begin
  VITALBehavior    : process (I0, I1, S)
  begin
    if (S = '0') then
      O <= I0;                  
      LO <= I0;            
    else
      O <= I1;                        
      LO <= I1;                  
    end if;                                
  end process;
end MUXF8_D_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf8_l.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-to-1 Lookup Table Multiplexer with Local Output
-- /___/   /\     Filename : MUXF8_L.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:04 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

--    08/23/07 - Handle S= X case. CR434611 
----- CELL MUXF8_L -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUXF8_L is
  port(
    LO : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    S  : in std_ulogic
    );
end MUXF8_L;

architecture MUXF8_L_V of MUXF8_L is
begin
  VITALBehavior    : process (I0, I1, S)
  begin
    if (S = '0') then
      LO <= I0;            
    else
      LO <= I1;                  
    end if;                                    
  end process;
end MUXF8_L_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-input NAND Gate
-- /___/   /\     Filename : NAND2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:05 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NAND2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NAND2 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic
    );
end NAND2;

architecture NAND2_V of NAND2 is
begin
  O <= not (I0 and I1);
end NAND2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand2b1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-input NAND Gate
-- /___/   /\     Filename : NAND2B1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:05 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NAND2B1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NAND2B1 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic
    );
end NAND2B1;

architecture NAND2B1_V of NAND2B1 is
begin
  O <= not ((not I0) and I1);
end NAND2B1_V;



-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand2b2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-input NAND Gate
-- /___/   /\     Filename : NAND2B2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:05 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NAND2B2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NAND2B2 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic
    );
end NAND2B2;

architecture NAND2B2_V of NAND2B2 is
begin
  O <= not ((not I0) and (not I1));
end NAND2B2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand3.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-input NAND Gate
-- /___/   /\     Filename : NAND3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:05 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NAND3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NAND3 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic
    );
end NAND3;

architecture NAND3_V of NAND3 is
begin
  O <= not (I0 and I1 and I2);
end NAND3_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand3b1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-input NAND Gate
-- /___/   /\     Filename : NAND3B1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:05 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NAND3B1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NAND3B1 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic
    );
end NAND3B1;

architecture NAND3B1_V of NAND3B1 is
begin
  O <= not ((not I0) and I1 and I2);
end NAND3B1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand3b2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-input NAND Gate
-- /___/   /\     Filename : NAND3B2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:05 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NAND3B2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NAND3B2 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic
    );
end NAND3B2;

architecture NAND3B2_V of NAND3B2 is
begin
  O <= not ((not I0) and (not I1) and I2);
end NAND3B2_V;



-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand3b3.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-input NAND Gate
-- /___/   /\     Filename : NAND3B3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:05 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NAND3B3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NAND3B3 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic
    );
end NAND3B3;

architecture NAND3B3_V of NAND3B3 is
begin
  O <= not ((not I0) and (not I1) and (not I2));
end NAND3B3_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand4.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input NAND Gate
-- /___/   /\     Filename : NAND4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:05 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NAND4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NAND4 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic
    );
end NAND4;

architecture NAND4_V of NAND4 is
begin
  O <= not (I0 and I1 and I2 and I3);
end NAND4_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand4b1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input NAND Gate
-- /___/   /\     Filename : NAND4B1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:05 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NAND4B1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NAND4B1 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic
    );
end NAND4B1;

architecture NAND4B1_V of NAND4B1 is
begin
  O <= not ((not I0) and I1 and I2 and I3);
end NAND4B1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand4b2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input NAND Gate
-- /___/   /\     Filename : NAND4B2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:06 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NAND4B2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NAND4B2 is
  port(
    O : out std_ulogic;

    I0      : in std_ulogic;
    I1      : in std_ulogic;
    I2      : in std_ulogic;
    I3      : in std_ulogic
    );
end NAND4B2;

architecture NAND4B2_V of NAND4B2 is
begin
  O <= not ((not I0) and (not I1) and I2 and I3);
end NAND4B2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand4b3.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input NAND Gate
-- /___/   /\     Filename : NAND4B3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:06 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NAND4B3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NAND4B3 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic
    );
end NAND4B3;

architecture NAND4B3_V of NAND4B3 is
begin
  O <= not ((not I0) and (not I1) and (not I2) and I3);
end NAND4B3_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand4b4.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input NAND Gate
-- /___/   /\     Filename : NAND4B4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:06 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NAND4B4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NAND4B4 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic
    );
end NAND4B4;

architecture NAND4B4_V of NAND4B4 is
begin
  O <= not ((not I0) and (not I1) and (not I2) and (not I3));
end NAND4B4_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand5.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input NAND Gate
-- /___/   /\     Filename : NAND5.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:06 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NAND5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NAND5 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end NAND5;

architecture NAND5_V of NAND5 is
begin
  O <= not (I0 and I1 and I2 and I3 and I4);
end NAND5_V;



-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand5b1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input NAND Gate
-- /___/   /\     Filename : NAND5B1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:06 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NAND5B1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NAND5B1 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end NAND5B1;

architecture NAND5B1_V of NAND5B1 is
begin
  O <= not ((not I0) and I1 and I2 and I3 and I4);
end NAND5B1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand5b2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input NAND Gate
-- /___/   /\     Filename : NAND5B2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:06 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NAND5B2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NAND5B2 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end NAND5B2;

architecture NAND5B2_V of NAND5B2 is
begin
  O <= not ((not I0) and (not I1) and I2 and I3 and I4);
end NAND5B2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand5b3.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input NAND Gate
-- /___/   /\     Filename : NAND5B3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:06 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NAND5B3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NAND5B3 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end NAND5B3;

architecture NAND5B3_V of NAND5B3 is
begin
  O <= not ((not I0) and (not I1) and (not I2) and I3 and I4);
end NAND5B3_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand5b4.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input NAND Gate
-- /___/   /\     Filename : NAND5B4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:06 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NAND5B4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NAND5B4 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end NAND5B4;

architecture NAND5B4_V of NAND5B4 is
begin
  O <= not ((not I0) and (not I1) and (not I2) and (not I3) and I4);
end NAND5B4_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand5b5.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input NAND Gate
-- /___/   /\     Filename : NAND5B5.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:07 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NAND5B5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NAND5B5 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end NAND5B5;

architecture NAND5B5_V of NAND5B5 is
begin
  O <= not ((not I0) and (not I1) and (not I2) and (not I3) and (not I4));
end NAND5B5_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-input NOR Gate
-- /___/   /\     Filename : NOR2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:07 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NOR2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NOR2 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic
    );
end NOR2;

architecture NOR2_V of NOR2 is
begin
  O <= (not (I0 or I1));
end NOR2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor2b1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-input NOR Gate
-- /___/   /\     Filename : NOR2B1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:07 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NOR2B1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NOR2B1 is
  port(
    O : out STD_ULOGIC;

    I0 : in STD_ULOGIC;
    I1 : in STD_ULOGIC
    );
end NOR2B1;

architecture NOR2B1_V of NOR2B1 is
begin
  O <= (NOT ((NOT I0) OR I1));
end NOR2B1_V;



-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor2b2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-input NOR Gate
-- /___/   /\     Filename : NOR2B2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:07 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NOR2B2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NOR2B2 is
   port(
      O                              :	out   STD_ULOGIC;
      
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC
      );
end NOR2B2;

architecture NOR2B2_V of NOR2B2 is
begin
  O <= (NOT ((NOT I0) OR (not I1)));  
end NOR2B2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor3.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-input NOR Gate
-- /___/   /\     Filename : NOR3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:07 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NOR3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NOR3 is
   port(
      O                              :	out   STD_ULOGIC;
      
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC
      );
end NOR3;

architecture NOR3_V of NOR3 is
begin
      O <= (NOT (I0 OR I1 OR I2));
end NOR3_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor3b1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-input NOR Gate
-- /___/   /\     Filename : NOR3B1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:07 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NOR3B1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NOR3B1 is
   port(
      O                              :	out   STD_ULOGIC;
      
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC
      );
end NOR3B1;

architecture NOR3B1_V of NOR3B1 is
begin
      O <= (NOT ((NOT I0) or I1 OR I2));
end NOR3B1_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor3b2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-input NOR Gate
-- /___/   /\     Filename : NOR3B2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:07 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NOR3B2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NOR3B2 is
   port(
      O                              :	out   STD_ULOGIC;
      
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC
      );
end NOR3B2;

architecture NOR3B2_V of NOR3B2 is
begin
      O <= (NOT ((NOT I0) or (not I1) OR I2));
end NOR3B2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor3b3.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-input NOR Gate
-- /___/   /\     Filename : NOR3B3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:07 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NOR3B3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NOR3B3 is
   port(
      O                              :	out   STD_ULOGIC;
      
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC
      );
end NOR3B3;

architecture NOR3B3_V of NOR3B3 is
begin
      O <= (NOT ((NOT I0) or (not I1) OR (not I2)));
end NOR3B3_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor4.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input NOR Gate
-- /___/   /\     Filename : NOR4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:07 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NOR4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NOR4 is
   port(
      O                              :	out   STD_ULOGIC;
      
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC
      );
end NOR4;

architecture NOR4_V of NOR4 is
begin
      O <= (NOT (I0 or I1 OR I2 or I3));
end NOR4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor4b1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input NOR Gate
-- /___/   /\     Filename : NOR4B1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:08 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NOR4B1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NOR4B1 is
   port(
      O                              :	out   STD_ULOGIC;
      
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC
      );
end NOR4B1;

architecture NOR4B1_V of NOR4B1 is
begin
      O <= (NOT ((not I0) or I1 OR I2 or I3));
end NOR4B1_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor4b2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input NOR Gate
-- /___/   /\     Filename : NOR4B2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:08 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NOR4B2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NOR4B2 is
   port(
      O                              :	out   STD_ULOGIC;
      
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC
      );
end NOR4B2;

architecture NOR4B2_V of NOR4B2 is
begin
      O <= (NOT ((not I0) or (not I1) OR I2 or I3));
end NOR4B2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor4b3.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input NOR Gate
-- /___/   /\     Filename : NOR4B3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:08 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NOR4B3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NOR4B3 is
   port(
      O                              :	out   STD_ULOGIC;
      
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC
      );
end NOR4B3;

architecture NOR4B3_V of NOR4B3 is
begin
      O <= (NOT ((not I0) or (not I1) OR (not I2) or I3));
end NOR4B3_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor4b4.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input NOR Gate
-- /___/   /\     Filename : NOR4B4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:08 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NOR4B4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NOR4B4 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic
    );
end NOR4B4;

architecture NOR4B4_V of NOR4B4 is
begin
  O <= (not ((not I0) or (not I1) or (not I2) or (not I3)));
end NOR4B4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor5.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input NOR Gate
-- /___/   /\     Filename : NOR5.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:08 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NOR5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NOR5 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end NOR5;

architecture NOR5_V of NOR5 is
begin
  O <= (not (I0 or I1 or I2 or I3 or I4));
end NOR5_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor5b1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input NOR Gate
-- /___/   /\     Filename : NOR5B1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:08 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NOR5B1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NOR5B1 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end NOR5B1;

architecture NOR5B1_V of NOR5B1 is
begin
  O <= (not ((not I0) or I1 or I2 or I3 or I4));
end NOR5B1_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor5b2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input NOR Gate
-- /___/   /\     Filename : NOR5B2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:08 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NOR5B2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NOR5B2 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end NOR5B2;

architecture NOR5B2_V of NOR5B2 is
begin
  O <= (not ((not I0) or (not I1) or I2 or I3 or I4));
end NOR5B2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor5b3.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input NOR Gate
-- /___/   /\     Filename : NOR5B3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:08 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NOR5B3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NOR5B3 is
   port(
      O                              :	out   STD_ULOGIC;
      
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC
      );
end NOR5B3;

architecture NOR5B3_V of NOR5B3 is
begin
      O <= (NOT ((not I0) or (not I1) OR (not I2) or I3 or I4));
end NOR5B3_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor5b4.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input NOR Gate
-- /___/   /\     Filename : NOR5B4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:08 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NOR5B4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NOR5B4 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end NOR5B4;

architecture NOR5B4_V of NOR5B4 is
begin
  O <= (not ((not I0) or (not I1) or (not I2) or (not I3) or I4));
end NOR5B4_V;






-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor5b5.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input NOR Gate
-- /___/   /\     Filename : NOR5B5.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:09 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL NOR5B5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NOR5B5 is
  port(
    O : out STD_ULOGIC;

    I0 : in STD_ULOGIC;
    I1 : in STD_ULOGIC;
    I2 : in STD_ULOGIC;
    I3 : in STD_ULOGIC;
    I4 : in STD_ULOGIC
    );
end NOR5B5;

architecture NOR5B5_V of NOR5B5 is
begin
  O <= (NOT ((not I0) or (not I1) OR (not I2) or (not I3) or (not I4)));
end NOR5B5_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf.vhd,v 1.5 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer
-- /___/   /\     Filename : OBUF.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:09 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF is
  generic(
      CAPACITANCE : string     := "DONT_CARE";
      DRIVE       : integer    := 12;
      IOSTANDARD  : string     := "DEFAULT";
      SLEW        : string     := "SLOW"
    );  
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF;

architecture OBUF_V of OBUF is
begin
  prcs_init : process
  variable FIRST_TIME        : boolean    := TRUE;
  begin

     If(FIRST_TIME = true) then
        if((CAPACITANCE = "LOW") or
           (CAPACITANCE = "NORMAL") or
           (CAPACITANCE = "DONT_CARE")) then
           FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The allowed values for CAPACITANCE are LOW, NORMAL or DONT_CARE"
           severity Failure;
        end if;
     end if;
     wait;
  end process prcs_init;

  O <= TO_X01(I);
end OBUF_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_agp.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with AGP I/O Standard
-- /___/   /\     Filename : OBUF_AGP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:09 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_AGP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_AGP is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_AGP;

architecture OBUF_AGP_V of OBUF_AGP is
begin
  O <= TO_X01(I);
end OBUF_AGP_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_ctt.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with CTT I/O Standard
-- /___/   /\     Filename : OBUF_CTT.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:09 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_CTT -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_CTT is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_CTT;

architecture OBUF_CTT_V of OBUF_CTT is
begin
  O <= TO_X01(I);
end OBUF_CTT_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_f_12.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with Fast Slew 12 mA Drive
-- /___/   /\     Filename : OBUF_F_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:09 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_F_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_F_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_F_12;

architecture OBUF_F_12_V of OBUF_F_12 is
begin
  O <= TO_X01(I);
end OBUF_F_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_f_16.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with Fast Slew 16 mA Drive
-- /___/   /\     Filename : OBUF_F_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:09 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_F_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_F_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_F_16;

architecture OBUF_F_16_V of OBUF_F_16 is
begin
  O <= TO_X01(I);
end OBUF_F_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_f_2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with Fast Slew 2 mA Drive
-- /___/   /\     Filename : OBUF_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:09 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_F_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_F_2;

architecture OBUF_F_2_V of OBUF_F_2 is
begin
  O <= TO_X01(I);
end OBUF_F_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_f_24.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with Fast Slew 24 mA Drive
-- /___/   /\     Filename : OBUF_F_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:09 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_F_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_F_24 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_F_24;

architecture OBUF_F_24_V of OBUF_F_24 is
begin
  O <= TO_X01(I);
end OBUF_F_24_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_f_4.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with Fast Slew 4 mA Drive
-- /___/   /\     Filename : OBUF_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:09 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_F_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_F_4;

architecture OBUF_F_4_V of OBUF_F_4 is
begin
  O <= TO_X01(I);
end OBUF_F_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_f_6.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with Fast Slew 6 mA Drive
-- /___/   /\     Filename : OBUF_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:10 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_F_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_F_6;

architecture OBUF_F_6_V of OBUF_F_6 is
begin
  O <= TO_X01(I);
end OBUF_F_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_f_8.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with Fast Slew 8 mA Drive
-- /___/   /\     Filename : OBUF_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:10 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_F_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_F_8;

architecture OBUF_F_8_V of OBUF_F_8 is
begin
  O <= TO_X01(I);
end OBUF_F_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_gtl.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with GTL I/O Standard
-- /___/   /\     Filename : OBUF_GTL.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:10 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_GTL -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_GTL is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_GTL;

architecture OBUF_GTL_V of OBUF_GTL is
begin
  O <= TO_X01(I);
end OBUF_GTL_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_gtl_dci.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with GTL_DCI I/O Standard
-- /___/   /\     Filename : OBUF_GTL_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:10 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_GTL_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_GTL_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_GTL_DCI;

architecture OBUF_GTL_DCI_V of OBUF_GTL_DCI is
begin
  O <= TO_X01(I);
end OBUF_GTL_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_gtlp.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with GTLP I/O Standard
-- /___/   /\     Filename : OBUF_GTLP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:10 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_GTLP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_GTLP is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_GTLP;

architecture OBUF_GTLP_V of OBUF_GTLP is
begin
  O <= TO_X01(I);
end OBUF_GTLP_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_gtlp_dci.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with GTLP_DCI I/O Standard
-- /___/   /\     Filename : OBUF_GTLP_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:10 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_GTLP_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_GTLP_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_GTLP_DCI;

architecture OBUF_GTLP_DCI_V of OBUF_GTLP_DCI is
begin
  O <= TO_X01(I);
end OBUF_GTLP_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_i.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with HSTL_I I/O Standard
-- /___/   /\     Filename : OBUF_HSTL_I.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:10 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_HSTL_I -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_HSTL_I is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_HSTL_I;

architecture OBUF_HSTL_I_V of OBUF_HSTL_I is
begin
  O <= TO_X01(I);
end OBUF_HSTL_I_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_i_18.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with HSTL_I_18 I/O Standard
-- /___/   /\     Filename : OBUF_HSTL_I_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:10 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_HSTL_I_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_HSTL_I_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_HSTL_I_18;

architecture OBUF_HSTL_I_18_V of OBUF_HSTL_I_18 is
begin
  O <= TO_X01(I);
end OBUF_HSTL_I_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_i_dci.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with HSTL_I_DCI I/O Standard
-- /___/   /\     Filename : OBUF_HSTL_I_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:10 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_HSTL_I_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_HSTL_I_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_HSTL_I_DCI;

architecture OBUF_HSTL_I_DCI_V of OBUF_HSTL_I_DCI is
begin
  O <= TO_X01(I);
end OBUF_HSTL_I_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_i_dci_18.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with HSTL_I_DCI_18 I/O Standard
-- /___/   /\     Filename : OBUF_HSTL_I_DCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:10 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_HSTL_I_DCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_HSTL_I_DCI_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_HSTL_I_DCI_18;

architecture OBUF_HSTL_I_DCI_18_V of OBUF_HSTL_I_DCI_18 is
begin
  O <= TO_X01(I);
end OBUF_HSTL_I_DCI_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_ii.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with HSTL_II I/O Standard
-- /___/   /\     Filename : OBUF_HSTL_II.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:11 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_HSTL_II -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_HSTL_II is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_HSTL_II;

architecture OBUF_HSTL_II_V of OBUF_HSTL_II is
begin
  O <= TO_X01(I);
end OBUF_HSTL_II_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_ii_18.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with HSTL_II_18 I/O Standard
-- /___/   /\     Filename : OBUF_HSTL_II_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:11 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_HSTL_II_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_HSTL_II_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_HSTL_II_18;

architecture OBUF_HSTL_II_18_V of OBUF_HSTL_II_18 is
begin
  O <= TO_X01(I);
end OBUF_HSTL_II_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_ii_dci.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with HSTL_II_DCI I/O Standard
-- /___/   /\     Filename : OBUF_HSTL_II_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:11 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_HSTL_II_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_HSTL_II_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_HSTL_II_DCI;

architecture OBUF_HSTL_II_DCI_V of OBUF_HSTL_II_DCI is
begin
  O <= TO_X01(I);
end OBUF_HSTL_II_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_ii_dci_18.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with HSTL_II_DCI_18 I/O Standard
-- /___/   /\     Filename : OBUF_HSTL_II_DCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:11 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_HSTL_II_DCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_HSTL_II_DCI_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_HSTL_II_DCI_18;

architecture OBUF_HSTL_II_DCI_18_V of OBUF_HSTL_II_DCI_18 is
begin
  O <= TO_X01(I);
end OBUF_HSTL_II_DCI_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_iii.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with HSTL_III I/O Standard
-- /___/   /\     Filename : OBUF_HSTL_III.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:11 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_HSTL_III -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_HSTL_III is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_HSTL_III;

architecture OBUF_HSTL_III_V of OBUF_HSTL_III is
begin
  O <= TO_X01(I);
end OBUF_HSTL_III_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_iii_18.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with HSTL_III_18 I/O Standard
-- /___/   /\     Filename : OBUF_HSTL_III_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:11 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_HSTL_III_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_HSTL_III_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_HSTL_III_18;

architecture OBUF_HSTL_III_18_V of OBUF_HSTL_III_18 is
begin
  O <= TO_X01(I);
end OBUF_HSTL_III_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_iii_dci.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with HSTL_III_DCI I/O Standard
-- /___/   /\     Filename : OBUF_HSTL_III_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:11 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_HSTL_III_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_HSTL_III_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_HSTL_III_DCI;

architecture OBUF_HSTL_III_DCI_V of OBUF_HSTL_III_DCI is
begin
  O <= TO_X01(I);
end OBUF_HSTL_III_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_iii_dci_18.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with HSTL_III_DCI_18 I/O Standard
-- /___/   /\     Filename : OBUF_HSTL_III_DCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:11 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_HSTL_III_DCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_HSTL_III_DCI_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_HSTL_III_DCI_18;

architecture OBUF_HSTL_III_DCI_18_V of OBUF_HSTL_III_DCI_18 is
begin
  O <= TO_X01(I);
end OBUF_HSTL_III_DCI_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_iv.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with HSTL_IV I/O Standard
-- /___/   /\     Filename : OBUF_HSTL_IV.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:11 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_HSTL_IV -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_HSTL_IV is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_HSTL_IV;

architecture OBUF_HSTL_IV_V of OBUF_HSTL_IV is
begin
  O <= TO_X01(I);
end OBUF_HSTL_IV_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_iv_18.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with HSTL_IV_18 I/O Standard
-- /___/   /\     Filename : OBUF_HSTL_IV_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:12 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_HSTL_IV_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_HSTL_IV_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_HSTL_IV_18;

architecture OBUF_HSTL_IV_18_V of OBUF_HSTL_IV_18 is
begin
  O <= TO_X01(I);
end OBUF_HSTL_IV_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_iv_dci.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with HSTL_IV_DCI I/O Standard
-- /___/   /\     Filename : OBUF_HSTL_IV_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:12 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_HSTL_IV_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_HSTL_IV_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_HSTL_IV_DCI;

architecture OBUF_HSTL_IV_DCI_V of OBUF_HSTL_IV_DCI is
begin
  O <= TO_X01(I);
end OBUF_HSTL_IV_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_iv_dci_18.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with HSTL_IV_DCI_18 I/O Standard
-- /___/   /\     Filename : OBUF_HSTL_IV_DCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:12 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_HSTL_IV_DCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_HSTL_IV_DCI_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_HSTL_IV_DCI_18;

architecture OBUF_HSTL_IV_DCI_18_V of OBUF_HSTL_IV_DCI_18 is
begin
  O <= TO_X01(I);
end OBUF_HSTL_IV_DCI_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos12.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS12 I/O Standard
-- /___/   /\     Filename : OBUF_LVCMOS12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:12 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS12;

architecture OBUF_LVCMOS12_V of OBUF_LVCMOS12 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos12_f_2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS12 I/O Standard Fast Slew 2 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS12_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:12 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS12_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS12_F_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS12_F_2;

architecture OBUF_LVCMOS12_F_2_V of OBUF_LVCMOS12_F_2 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS12_F_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos12_f_4.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS12 I/O Standard Fast Slew 4 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS12_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:12 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS12_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS12_F_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS12_F_4;

architecture OBUF_LVCMOS12_F_4_V of OBUF_LVCMOS12_F_4 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS12_F_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos12_f_6.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS12 I/O Standard Fast Slew 6 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS12_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:12 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS12_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS12_F_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS12_F_6;

architecture OBUF_LVCMOS12_F_6_V of OBUF_LVCMOS12_F_6 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS12_F_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos12_f_8.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS12 I/O Standard Fast Slew 8 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS12_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:12 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS12_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS12_F_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS12_F_8;

architecture OBUF_LVCMOS12_F_8_V of OBUF_LVCMOS12_F_8 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS12_F_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos12_s_2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS12 I/O Standard Slow Slew 2 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS12_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:12 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS12_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS12_S_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS12_S_2;

architecture OBUF_LVCMOS12_S_2_V of OBUF_LVCMOS12_S_2 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS12_S_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos12_s_4.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS12 I/O Standard Slow Slew 4 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS12_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:13 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS12_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS12_S_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS12_S_4;

architecture OBUF_LVCMOS12_S_4_V of OBUF_LVCMOS12_S_4 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS12_S_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos12_s_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS12 I/O Standard Slow Slew 6 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS12_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:13 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS12_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS12_S_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS12_S_6;

architecture OBUF_LVCMOS12_S_6_V of OBUF_LVCMOS12_S_6 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS12_S_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos12_s_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS12 I/O Standard Slow Slew 8 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS12_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:13 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS12_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS12_S_8 is
   port(
      O : out std_ulogic;

      I : in std_ulogic
      );
end OBUF_LVCMOS12_S_8;

architecture OBUF_LVCMOS12_S_8_V of OBUF_LVCMOS12_S_8 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS12_S_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS15 I/O Standard
-- /___/   /\     Filename : OBUF_LVCMOS15.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:13 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS15 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS15 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS15;

architecture OBUF_LVCMOS15_V of OBUF_LVCMOS15 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS15_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_f_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS15 I/O Standard Fast Slew 12 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS15_F_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:13 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS15_F_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS15_F_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS15_F_12;

architecture OBUF_LVCMOS15_F_12_V of OBUF_LVCMOS15_F_12 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS15_F_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_f_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS15 I/O Standard Fast Slew 16 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS15_F_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:13 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS15_F_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS15_F_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS15_F_16;

architecture OBUF_LVCMOS15_F_16_V of OBUF_LVCMOS15_F_16 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS15_F_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_f_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS15 I/O Standard Fast Slew 2 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS15_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:13 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS15_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS15_F_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS15_F_2;

architecture OBUF_LVCMOS15_F_2_V of OBUF_LVCMOS15_F_2 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS15_F_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_f_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS15 I/O Standard Fast Slew 4 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS15_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:13 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS15_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS15_F_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS15_F_4;

architecture OBUF_LVCMOS15_F_4_V of OBUF_LVCMOS15_F_4 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS15_F_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_f_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS15 I/O Standard Fast Slew 6 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS15_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:13 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS15_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS15_F_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS15_F_6;

architecture OBUF_LVCMOS15_F_6_V of OBUF_LVCMOS15_F_6 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS15_F_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_f_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS15 I/O Standard Fast Slew 8 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS15_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:14 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS15_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS15_F_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS15_F_8;

architecture OBUF_LVCMOS15_F_8_V of OBUF_LVCMOS15_F_8 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS15_F_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_s_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS15 I/O Standard Slow Slew 12 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS15_S_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:14 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS15_S_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS15_S_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS15_S_12;

architecture OBUF_LVCMOS15_S_12_V of OBUF_LVCMOS15_S_12 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS15_S_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_s_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS15 I/O Standard Slow Slew 16 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS15_S_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:14 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS15_S_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS15_S_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS15_S_16;

architecture OBUF_LVCMOS15_S_16_V of OBUF_LVCMOS15_S_16 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS15_S_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_s_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS15 I/O Standard Slow Slew 2 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS15_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:14 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS15_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS15_S_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS15_S_2;

architecture OBUF_LVCMOS15_S_2_V of OBUF_LVCMOS15_S_2 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS15_S_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_s_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS15 I/O Standard Slow Slew 4 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS15_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:14 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS15_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS15_S_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS15_S_4;

architecture OBUF_LVCMOS15_S_4_V of OBUF_LVCMOS15_S_4 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS15_S_4_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_s_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS15 I/O Standard Slow Slew 6 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS15_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:14 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS15_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS15_S_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS15_S_6;

architecture OBUF_LVCMOS15_S_6_V of OBUF_LVCMOS15_S_6 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS15_S_6_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_s_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS15 I/O Standard Slow Slew 8 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS15_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:14 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS15_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS15_S_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS15_S_8;

architecture OBUF_LVCMOS15_S_8_V of OBUF_LVCMOS15_S_8 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS15_S_8_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS18 I/O Standard
-- /___/   /\     Filename : OBUF_LVCMOS18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:14 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS18;

architecture OBUF_LVCMOS18_V of OBUF_LVCMOS18 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS18_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_f_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS18 I/O Standard Fast Slew 12 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS18_F_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:14 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS18_F_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS18_F_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS18_F_12;

architecture OBUF_LVCMOS18_F_12_V of OBUF_LVCMOS18_F_12 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS18_F_12_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_f_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS18 I/O Standard Fast Slew 16 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS18_F_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:15 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS18_F_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS18_F_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS18_F_16;

architecture OBUF_LVCMOS18_F_16_V of OBUF_LVCMOS18_F_16 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS18_F_16_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_f_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS18 I/O Standard Fast Slew 2 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS18_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:15 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS18_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS18_F_2 is
  port(
    O : out STD_ULOGIC;

    I : in STD_ULOGIC
    );
end OBUF_LVCMOS18_F_2;

architecture OBUF_LVCMOS18_F_2_V of OBUF_LVCMOS18_F_2 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS18_F_2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_f_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS18 I/O Standard Fast Slew 4 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS18_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:15 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS18_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS18_F_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS18_F_4;

architecture OBUF_LVCMOS18_F_4_V of OBUF_LVCMOS18_F_4 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS18_F_4_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_f_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS18 I/O Standard Fast Slew 6 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS18_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:15 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS18_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS18_F_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS18_F_6;

architecture OBUF_LVCMOS18_F_6_V of OBUF_LVCMOS18_F_6 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS18_F_6_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_f_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS18 I/O Standard Fast Slew 8 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS18_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:15 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS18_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS18_F_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS18_F_8;

architecture OBUF_LVCMOS18_F_8_V of OBUF_LVCMOS18_F_8 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS18_F_8_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_s_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS18 I/O Standard Slow Slew 12 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS18_S_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:15 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS18_S_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS18_S_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS18_S_12;

architecture OBUF_LVCMOS18_S_12_V of OBUF_LVCMOS18_S_12 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS18_S_12_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_s_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS18 I/O Standard Slow Slew 16 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS18_S_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:15 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS18_S_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS18_S_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS18_S_16;

architecture OBUF_LVCMOS18_S_16_V of OBUF_LVCMOS18_S_16 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS18_S_16_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_s_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS18 I/O Standard Slow Slew 2 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS18_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:15 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS18_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS18_S_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS18_S_2;

architecture OBUF_LVCMOS18_S_2_V of OBUF_LVCMOS18_S_2 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS18_S_2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_s_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS18 I/O Standard Slow Slew 4 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS18_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:16 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS18_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS18_S_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS18_S_4;

architecture OBUF_LVCMOS18_S_4_V of OBUF_LVCMOS18_S_4 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS18_S_4_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_s_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS18 I/O Standard Slow Slew 6 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS18_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:16 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS18_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS18_S_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS18_S_6;

architecture OBUF_LVCMOS18_S_6_V of OBUF_LVCMOS18_S_6 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS18_S_6_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_s_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS18 I/O Standard Slow Slew 8 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS18_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:16 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS18_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS18_S_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS18_S_8;

architecture OBUF_LVCMOS18_S_8_V of OBUF_LVCMOS18_S_8 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS18_S_8_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS2 I/O Standard
-- /___/   /\     Filename : OBUF_LVCMOS2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:16 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS2;

architecture OBUF_LVCMOS2_V of OBUF_LVCMOS2 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS25 I/O Standard
-- /___/   /\     Filename : OBUF_LVCMOS25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:16 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS25 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS25;

architecture OBUF_LVCMOS25_V of OBUF_LVCMOS25 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_f_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS25 I/O Standard Fast Slew 12 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS25_F_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:16 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS25_F_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS25_F_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS25_F_12;

architecture OBUF_LVCMOS25_F_12_V of OBUF_LVCMOS25_F_12 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS25_F_12_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_f_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS25 I/O Standard Fast Slew 16 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS25_F_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:16 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS25_F_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS25_F_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS25_F_16;

architecture OBUF_LVCMOS25_F_16_V of OBUF_LVCMOS25_F_16 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS25_F_16_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_f_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS25 I/O Standard Fast Slew 2 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS25_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:16 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS25_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS25_F_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS25_F_2;

architecture OBUF_LVCMOS25_F_2_V of OBUF_LVCMOS25_F_2 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS25_F_2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_f_24.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS25 I/O Standard Fast Slew 24 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS25_F_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:16 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS25_F_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS25_F_24 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS25_F_24;

architecture OBUF_LVCMOS25_F_24_V of OBUF_LVCMOS25_F_24 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS25_F_24_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_f_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS25 I/O Standard Fast Slew 4 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS25_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:17 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS25_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS25_F_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS25_F_4;

architecture OBUF_LVCMOS25_F_4_V of OBUF_LVCMOS25_F_4 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS25_F_4_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_f_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS25 I/O Standard Fast Slew 6 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS25_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:17 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS25_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS25_F_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS25_F_6;

architecture OBUF_LVCMOS25_F_6_V of OBUF_LVCMOS25_F_6 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS25_F_6_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_f_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS25 I/O Standard Fast Slew 8 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS25_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:17 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS25_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS25_F_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS25_F_8;

architecture OBUF_LVCMOS25_F_8_V of OBUF_LVCMOS25_F_8 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS25_F_8_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_s_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS25 I/O Standard Slow Slew 12 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS25_S_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:17 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS25_S_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS25_S_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS25_S_12;

architecture OBUF_LVCMOS25_S_12_V of OBUF_LVCMOS25_S_12 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS25_S_12_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_s_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS25 I/O Standard Slow Slew 16 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS25_S_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:17 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS25_S_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS25_S_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS25_S_16;

architecture OBUF_LVCMOS25_S_16_V of OBUF_LVCMOS25_S_16 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS25_S_16_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_s_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS25 I/O Standard Slow Slew 2 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS25_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:17 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS25_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS25_S_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS25_S_2;

architecture OBUF_LVCMOS25_S_2_V of OBUF_LVCMOS25_S_2 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS25_S_2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_s_24.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS25 I/O Standard Slow Slew 24 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS25_S_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:17 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS25_S_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS25_S_24 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS25_S_24;

architecture OBUF_LVCMOS25_S_24_V of OBUF_LVCMOS25_S_24 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS25_S_24_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_s_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS25 I/O Standard Slow Slew 4 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS25_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:17 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS25_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS25_S_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS25_S_4;

architecture OBUF_LVCMOS25_S_4_V of OBUF_LVCMOS25_S_4 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS25_S_4_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_s_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS25 I/O Standard Slow Slew 6 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS25_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:17 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS25_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS25_S_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS25_S_6;

architecture OBUF_LVCMOS25_S_6_V of OBUF_LVCMOS25_S_6 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS25_S_6_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_s_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS25 I/O Standard Slow Slew 8 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS25_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:18 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS25_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS25_S_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS25_S_8;

architecture OBUF_LVCMOS25_S_8_V of OBUF_LVCMOS25_S_8 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS25_S_8_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS33 I/O Standard
-- /___/   /\     Filename : OBUF_LVCMOS33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:18 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS33 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS33;

architecture OBUF_LVCMOS33_V of OBUF_LVCMOS33 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS33_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_f_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS33 I/O Standard Fast Slew 12 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS33_F_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:18 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS33_F_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS33_F_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS33_F_12;

architecture OBUF_LVCMOS33_F_12_V of OBUF_LVCMOS33_F_12 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS33_F_12_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_f_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS33 I/O Standard Fast Slew 16 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS33_F_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:18 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS33_F_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS33_F_16 is
  port(
    O : out STD_ULOGIC;

    I : in STD_ULOGIC
    );
end OBUF_LVCMOS33_F_16;

architecture OBUF_LVCMOS33_F_16_V of OBUF_LVCMOS33_F_16 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS33_F_16_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_f_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS33 I/O Standard Fast Slew 2 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS33_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:18 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS33_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS33_F_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS33_F_2;

architecture OBUF_LVCMOS33_F_2_V of OBUF_LVCMOS33_F_2 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS33_F_2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_f_24.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS33 I/O Standard Fast Slew 24 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS33_F_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:18 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS33_F_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS33_F_24 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS33_F_24;

architecture OBUF_LVCMOS33_F_24_V of OBUF_LVCMOS33_F_24 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS33_F_24_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_f_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS33 I/O Standard Fast Slew 4 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS33_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:18 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS33_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS33_F_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS33_F_4;

architecture OBUF_LVCMOS33_F_4_V of OBUF_LVCMOS33_F_4 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS33_F_4_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_f_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS33 I/O Standard Fast Slew 6 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS33_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:18 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS33_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS33_F_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS33_F_6;

architecture OBUF_LVCMOS33_F_6_V of OBUF_LVCMOS33_F_6 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS33_F_6_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_f_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS33 I/O Standard Fast Slew 8 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS33_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:18 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS33_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS33_F_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS33_F_8;

architecture OBUF_LVCMOS33_F_8_V of OBUF_LVCMOS33_F_8 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS33_F_8_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_s_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS33 I/O Standard Slow Slew 12 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS33_S_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:19 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS33_S_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS33_S_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS33_S_12;

architecture OBUF_LVCMOS33_S_12_V of OBUF_LVCMOS33_S_12 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS33_S_12_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_s_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS33 I/O Standard Slow Slew 16 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS33_S_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:19 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS33_S_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS33_S_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS33_S_16;

architecture OBUF_LVCMOS33_S_16_V of OBUF_LVCMOS33_S_16 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS33_S_16_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_s_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS33 I/O Standard Slow Slew 2 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS33_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:19 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS33_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS33_S_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS33_S_2;

architecture OBUF_LVCMOS33_S_2_V of OBUF_LVCMOS33_S_2 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS33_S_2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_s_24.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS33 I/O Standard Slow Slew 24 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS33_S_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:19 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS33_S_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS33_S_24 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS33_S_24;

architecture OBUF_LVCMOS33_S_24_V of OBUF_LVCMOS33_S_24 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS33_S_24_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_s_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS33 I/O Standard Slow Slew 4 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS33_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:19 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS33_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS33_S_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS33_S_4;

architecture OBUF_LVCMOS33_S_4_V of OBUF_LVCMOS33_S_4 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS33_S_4_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_s_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS33 I/O Standard Slow Slew 6 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS33_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:19 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS33_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS33_S_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS33_S_6;

architecture OBUF_LVCMOS33_S_6_V of OBUF_LVCMOS33_S_6 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS33_S_6_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_s_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVCMOS33 I/O Standard Slow Slew 8 mA Drive
-- /___/   /\     Filename : OBUF_LVCMOS33_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:19 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVCMOS33_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVCMOS33_S_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVCMOS33_S_8;

architecture OBUF_LVCMOS33_S_8_V of OBUF_LVCMOS33_S_8 is
begin
  O <= TO_X01(I);
end OBUF_LVCMOS33_S_8_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvdci_15.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVDCI_15 I/O Standard
-- /___/   /\     Filename : OBUF_LVDCI_15.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:19 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVDCI_15 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVDCI_15 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVDCI_15;

architecture OBUF_LVDCI_15_V of OBUF_LVDCI_15 is
begin
  O <= TO_X01(I);
end OBUF_LVDCI_15_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvdci_18.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVDCI_18 I/O Standard
-- /___/   /\     Filename : OBUF_LVDCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:19 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVDCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVDCI_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVDCI_18;

architecture OBUF_LVDCI_18_V of OBUF_LVDCI_18 is
begin
  O <= TO_X01(I);
end OBUF_LVDCI_18_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvdci_25.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVDCI_25 I/O Standard
-- /___/   /\     Filename : OBUF_LVDCI_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:20 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVDCI_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVDCI_25 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVDCI_25;

architecture OBUF_LVDCI_25_V of OBUF_LVDCI_25 is
begin
  O <= TO_X01(I);
end OBUF_LVDCI_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvdci_33.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVDCI_33 I/O Standard
-- /___/   /\     Filename : OBUF_LVDCI_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:20 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVDCI_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVDCI_33 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVDCI_33;

architecture OBUF_LVDCI_33_V of OBUF_LVDCI_33 is
begin
  O <= TO_X01(I);
end OBUF_LVDCI_33_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvdci_dv2_15.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVDCI_DV2_15 I/O Standard
-- /___/   /\     Filename : OBUF_LVDCI_DV2_15.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:20 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVDCI_DV2_15 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVDCI_DV2_15 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVDCI_DV2_15;

architecture OBUF_LVDCI_DV2_15_V of OBUF_LVDCI_DV2_15 is
begin
  O <= TO_X01(I);
end OBUF_LVDCI_DV2_15_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvdci_dv2_18.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVDCI_DV2_18 I/O Standard
-- /___/   /\     Filename : OBUF_LVDCI_DV2_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:20 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVDCI_DV2_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVDCI_DV2_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVDCI_DV2_18;

architecture OBUF_LVDCI_DV2_18_V of OBUF_LVDCI_DV2_18 is
begin
  O <= TO_X01(I);
end OBUF_LVDCI_DV2_18_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvdci_dv2_25.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVDCI_DV2_25 I/O Standard
-- /___/   /\     Filename : OBUF_LVDCI_DV2_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:20 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVDCI_DV2_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVDCI_DV2_25 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVDCI_DV2_25;

architecture OBUF_LVDCI_DV2_25_V of OBUF_LVDCI_DV2_25 is
begin
  O <= TO_X01(I);
end OBUF_LVDCI_DV2_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvdci_dv2_33.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVDCI_DV2_33 I/O Standard
-- /___/   /\     Filename : OBUF_LVDCI_DV2_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:20 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVDCI_DV2_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVDCI_DV2_33 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVDCI_DV2_33;

architecture OBUF_LVDCI_DV2_33_V of OBUF_LVDCI_DV2_33 is
begin
  O <= TO_X01(I);
end OBUF_LVDCI_DV2_33_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvds.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVDS I/O Standard
-- /___/   /\     Filename : OBUF_LVDS.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:20 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVDS -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVDS is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVDS;

architecture OBUF_LVDS_V of OBUF_LVDS is
begin
  O <= TO_X01(I);
end OBUF_LVDS_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvpecl.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVPECL I/O Standard
-- /___/   /\     Filename : OBUF_LVPECL.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:20 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVPECL -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVPECL is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVPECL;

architecture OBUF_LVPECL_V of OBUF_LVPECL is
begin
  O <= TO_X01(I);
end OBUF_LVPECL_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVTTL I/O Standard
-- /___/   /\     Filename : OBUF_LVTTL.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:20 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVTTL -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVTTL is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVTTL;

architecture OBUF_LVTTL_V of OBUF_LVTTL is
begin
  O <= TO_X01(I);
end OBUF_LVTTL_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_f_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVTTL I/O Standard Fast Slew 12 mA Drive
-- /___/   /\     Filename : OBUF_LVTTL_F_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:21 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVTTL_F_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVTTL_F_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVTTL_F_12;

architecture OBUF_LVTTL_F_12_V of OBUF_LVTTL_F_12 is
begin
  O <= TO_X01(I);
end OBUF_LVTTL_F_12_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_f_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVTTL I/O Standard Fast Slew 16 mA Drive
-- /___/   /\     Filename : OBUF_LVTTL_F_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:21 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVTTL_F_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVTTL_F_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVTTL_F_16;

architecture OBUF_LVTTL_F_16_V of OBUF_LVTTL_F_16 is
begin
  O <= TO_X01(I);
end OBUF_LVTTL_F_16_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_f_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVTTL I/O Standard Fast Slew 2 mA Drive
-- /___/   /\     Filename : OBUF_LVTTL_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:21 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVTTL_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVTTL_F_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVTTL_F_2;

architecture OBUF_LVTTL_F_2_V of OBUF_LVTTL_F_2 is
begin
  O <= TO_X01(I);
end OBUF_LVTTL_F_2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_f_24.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVTTL I/O Standard Fast Slew 24 mA Drive
-- /___/   /\     Filename : OBUF_LVTTL_F_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:21 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVTTL_F_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVTTL_F_24 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVTTL_F_24;

architecture OBUF_LVTTL_F_24_V of OBUF_LVTTL_F_24 is
begin
  O <= TO_X01(I);
end OBUF_LVTTL_F_24_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_f_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVTTL I/O Standard Fast Slew 4 mA Drive
-- /___/   /\     Filename : OBUF_LVTTL_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:21 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVTTL_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVTTL_F_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVTTL_F_4;

architecture OBUF_LVTTL_F_4_V of OBUF_LVTTL_F_4 is
begin
  O <= TO_X01(I);
end OBUF_LVTTL_F_4_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_f_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVTTL I/O Standard Fast Slew 6 mA Drive
-- /___/   /\     Filename : OBUF_LVTTL_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:21 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVTTL_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVTTL_F_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVTTL_F_6;

architecture OBUF_LVTTL_F_6_V of OBUF_LVTTL_F_6 is
begin
  O <= TO_X01(I);
end OBUF_LVTTL_F_6_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_f_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVTTL I/O Standard Fast Slew 8 mA Drive
-- /___/   /\     Filename : OBUF_LVTTL_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:21 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVTTL_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVTTL_F_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVTTL_F_8;

architecture OBUF_LVTTL_F_8_V of OBUF_LVTTL_F_8 is
begin
  O <= TO_X01(I);
end OBUF_LVTTL_F_8_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_s_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVTTL I/O Standard Slow Slew 12 mA Drive
-- /___/   /\     Filename : OBUF_LVTTL_S_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:21 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVTTL_S_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVTTL_S_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVTTL_S_12;

architecture OBUF_LVTTL_S_12_V of OBUF_LVTTL_S_12 is
begin
  O <= TO_X01(I);
end OBUF_LVTTL_S_12_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_s_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVTTL I/O Standard Slow Slew 16 mA Drive
-- /___/   /\     Filename : OBUF_LVTTL_S_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:21 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVTTL_S_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVTTL_S_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVTTL_S_16;

architecture OBUF_LVTTL_S_16_V of OBUF_LVTTL_S_16 is
begin
  O <= TO_X01(I);
end OBUF_LVTTL_S_16_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_s_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVTTL I/O Standard Slow Slew 2 mA Drive
-- /___/   /\     Filename : OBUF_LVTTL_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:22 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVTTL_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVTTL_S_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVTTL_S_2;

architecture OBUF_LVTTL_S_2_V of OBUF_LVTTL_S_2 is
begin
  O <= TO_X01(I);
end OBUF_LVTTL_S_2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_s_24.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVTTL I/O Standard Slow Slew 24 mA Drive
-- /___/   /\     Filename : OBUF_LVTTL_S_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:22 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVTTL_S_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVTTL_S_24 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVTTL_S_24;

architecture OBUF_LVTTL_S_24_V of OBUF_LVTTL_S_24 is
begin
  O <= TO_X01(I);
end OBUF_LVTTL_S_24_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_s_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVTTL I/O Standard Slow Slew 4 mA Drive
-- /___/   /\     Filename : OBUF_LVTTL_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:22 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVTTL_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVTTL_S_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVTTL_S_4;

architecture OBUF_LVTTL_S_4_V of OBUF_LVTTL_S_4 is
begin
  O <= TO_X01(I);
end OBUF_LVTTL_S_4_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_s_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVTTL I/O Standard Slow Slew 6 mA Drive
-- /___/   /\     Filename : OBUF_LVTTL_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:22 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVTTL_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVTTL_S_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVTTL_S_6;

architecture OBUF_LVTTL_S_6_V of OBUF_LVTTL_S_6 is
begin
  O <= TO_X01(I);
end OBUF_LVTTL_S_6_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_s_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with LVTTL I/O Standard Slow Slew 8 mA Drive
-- /___/   /\     Filename : OBUF_LVTTL_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:22 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_LVTTL_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_LVTTL_S_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_LVTTL_S_8;

architecture OBUF_LVTTL_S_8_V of OBUF_LVTTL_S_8 is
begin
  O <= TO_X01(I);
end OBUF_LVTTL_S_8_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_pci33_3.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with PCI33_3 I/O Standard
-- /___/   /\     Filename : OBUF_PCI33_3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:22 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_PCI33_3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_PCI33_3 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_PCI33_3;

architecture OBUF_PCI33_3_V of OBUF_PCI33_3 is
begin
  O <= TO_X01(I);
end OBUF_PCI33_3_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_pci33_5.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with PCI33_5 I/O Standard
-- /___/   /\     Filename : OBUF_PCI33_5.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:22 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_PCI33_5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_PCI33_5 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_PCI33_5;

architecture OBUF_PCI33_5_V of OBUF_PCI33_5 is
begin
  O <= TO_X01(I);
end OBUF_PCI33_5_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_pci66_3.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with PCI66_3 I/O Standard
-- /___/   /\     Filename : OBUF_PCI66_3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:22 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_PCI66_3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_PCI66_3 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_PCI66_3;

architecture OBUF_PCI66_3_V of OBUF_PCI66_3 is
begin
  O <= TO_X01(I);
end OBUF_PCI66_3_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_pcix.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with PCIX I/O Standard
-- /___/   /\     Filename : OBUF_PCIX.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:22 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_PCIX -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_PCIX is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_PCIX;

architecture OBUF_PCIX_V of OBUF_PCIX is
begin
  O <= TO_X01(I);
end OBUF_PCIX_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_pcix66_3.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with PCIX66_3 I/O Standard
-- /___/   /\     Filename : OBUF_PCIX66_3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:22 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_PCIX66_3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_PCIX66_3 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_PCIX66_3;

architecture OBUF_PCIX66_3_V of OBUF_PCIX66_3 is
begin
  O <= TO_X01(I);
end OBUF_PCIX66_3_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_s_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with Slow Slew 12 mA Drive
-- /___/   /\     Filename : OBUF_S_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:23 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_S_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_S_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_S_12;

architecture OBUF_S_12_V of OBUF_S_12 is
begin
  O <= TO_X01(I);
end OBUF_S_12_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_s_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with Slow Slew 16 mA Drive
-- /___/   /\     Filename : OBUF_S_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:23 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_S_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_S_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_S_16;

architecture OBUF_S_16_V of OBUF_S_16 is
begin
  O <= TO_X01(I);
end OBUF_S_16_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_s_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with Slow Slew 2 mA Drive
-- /___/   /\     Filename : OBUF_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:23 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_S_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_S_2;

architecture OBUF_S_2_V of OBUF_S_2 is
begin
  O <= TO_X01(I);
end OBUF_S_2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_s_24.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with Slow Slew 24 mA Drive
-- /___/   /\     Filename : OBUF_S_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:23 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_S_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_S_24 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_S_24;

architecture OBUF_S_24_V of OBUF_S_24 is
begin
  O <= TO_X01(I);
end OBUF_S_24_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_s_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with Slow Slew 4 mA Drive
-- /___/   /\     Filename : OBUF_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:23 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_S_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_S_4;

architecture OBUF_S_4_V of OBUF_S_4 is
begin
  O <= TO_X01(I);
end OBUF_S_4_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_s_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with Slow Slew 6 mA Drive
-- /___/   /\     Filename : OBUF_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:23 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_S_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_S_6;

architecture OBUF_S_6_V of OBUF_S_6 is
begin
  O <= TO_X01(I);
end OBUF_S_6_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_s_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with Slow Slew 8 mA Drive
-- /___/   /\     Filename : OBUF_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:23 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_S_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_S_8;

architecture OBUF_S_8_V of OBUF_S_8 is
begin
  O <= TO_X01(I);
end OBUF_S_8_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl18_i.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with SSTL18_I I/O Standard
-- /___/   /\     Filename : OBUF_SSTL18_I.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:23 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_SSTL18_I -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_SSTL18_I is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_SSTL18_I;

architecture OBUF_SSTL18_I_V of OBUF_SSTL18_I is
begin
  O <= TO_X01(I);
end OBUF_SSTL18_I_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl18_i_dci.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with SSTL18_I_DCI I/O Standard
-- /___/   /\     Filename : OBUF_SSTL18_I_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:23 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_SSTL18_I_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_SSTL18_I_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_SSTL18_I_DCI;

architecture OBUF_SSTL18_I_DCI_V of OBUF_SSTL18_I_DCI is
begin
  O <= TO_X01(I);
end OBUF_SSTL18_I_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl18_ii.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with SSTL18_II I/O Standard
-- /___/   /\     Filename : OBUF_SSTL18_II.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:24 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_SSTL18_II -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_SSTL18_II is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_SSTL18_II;

architecture OBUF_SSTL18_II_V of OBUF_SSTL18_II is
begin
  O <= TO_X01(I);
end OBUF_SSTL18_II_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl18_ii_dci.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with SSTL18_II_DCI I/O Standard
-- /___/   /\     Filename : OBUF_SSTL18_II_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:24 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_SSTL18_II_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_SSTL18_II_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_SSTL18_II_DCI;

architecture OBUF_SSTL18_II_DCI_V of OBUF_SSTL18_II_DCI is
begin
  O <= TO_X01(I);
end OBUF_SSTL18_II_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl2_i.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with SSTL2_I I/O Standard
-- /___/   /\     Filename : OBUF_SSTL2_I.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:24 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_SSTL2_I -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_SSTL2_I is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_SSTL2_I;

architecture OBUF_SSTL2_I_V of OBUF_SSTL2_I is
begin
  O <= TO_X01(I);
end OBUF_SSTL2_I_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl2_i_dci.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with SSTL2_I_DCI I/O Standard
-- /___/   /\     Filename : OBUF_SSTL2_I_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:24 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_SSTL2_I_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_SSTL2_I_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_SSTL2_I_DCI;

architecture OBUF_SSTL2_I_DCI_V of OBUF_SSTL2_I_DCI is
begin
  O <= TO_X01(I);
end OBUF_SSTL2_I_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl2_ii.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with SSTL2_II I/O Standard
-- /___/   /\     Filename : OBUF_SSTL2_II.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:24 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_SSTL2_II -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_SSTL2_II is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_SSTL2_II;

architecture OBUF_SSTL2_II_V of OBUF_SSTL2_II is
begin
  O <= TO_X01(I);
end OBUF_SSTL2_II_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl2_ii_dci.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with SSTL2_II_DCI I/O Standard
-- /___/   /\     Filename : OBUF_SSTL2_II_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:24 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_SSTL2_II_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_SSTL2_II_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_SSTL2_II_DCI;

architecture OBUF_SSTL2_II_DCI_V of OBUF_SSTL2_II_DCI is
begin
  O <= TO_X01(I);
end OBUF_SSTL2_II_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl3_i.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with SSTL3_I I/O Standard
-- /___/   /\     Filename : OBUF_SSTL3_I.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:24 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_SSTL3_I -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_SSTL3_I is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_SSTL3_I;

architecture OBUF_SSTL3_I_V of OBUF_SSTL3_I is
begin
  O <= TO_X01(I);
end OBUF_SSTL3_I_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl3_i_dci.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with SSTL3_I_DCI I/O Standard
-- /___/   /\     Filename : OBUF_SSTL3_I_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:24 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_SSTL3_I_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_SSTL3_I_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_SSTL3_I_DCI;

architecture OBUF_SSTL3_I_DCI_V of OBUF_SSTL3_I_DCI is
begin
  O <= TO_X01(I);
end OBUF_SSTL3_I_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl3_ii.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with SSTL3_II I/O Standard
-- /___/   /\     Filename : OBUF_SSTL3_II.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:24 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_SSTL3_II -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_SSTL3_II is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_SSTL3_II;

architecture OBUF_SSTL3_II_V of OBUF_SSTL3_II is
begin
  O <= TO_X01(I);
end OBUF_SSTL3_II_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl3_ii_dci.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Output Buffer with SSTL3_II_DCI I/O Standard
-- /___/   /\     Filename : OBUF_SSTL3_II_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:25 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUF_SSTL3_II_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUF_SSTL3_II_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end OBUF_SSTL3_II_DCI;

architecture OBUF_SSTL3_II_DCI_V of OBUF_SSTL3_II_DCI is
begin
  O <= TO_X01(I);
end OBUF_SSTL3_II_DCI_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obufds.vhd,v 1.6 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Output Buffer
-- /___/   /\     Filename : OBUFDS.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:25 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFDS -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFDS is
  generic(
      CAPACITANCE : string     := "DONT_CARE";
      IOSTANDARD  : string     := "DEFAULT"
    );

  port(
    O  : out std_ulogic;
    OB : out std_ulogic;

    I : in std_ulogic
    );
end OBUFDS;

architecture OBUFDS_V of OBUFDS is
begin
  VitalBehavior    : process (I)
    variable O_zd  : std_logic;
    variable OB_zd : std_logic;
  begin
    O_zd  := TO_X01(I);
    OB_zd := (not O_zd);
    O  <= O_zd;
    OB <= OB_zd;
  end process;
end OBUFDS_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obufds_blvds_25.vhd,v 1.5 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Output Buffer with BLVDS_25 I/O Standard
-- /___/   /\     Filename : OBUFDS_BLVDS_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:25 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFDS_BLVDS_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFDS_BLVDS_25 is
  port(
    O  : out std_ulogic;
    OB : out std_ulogic;

    I : in std_ulogic
    );
end OBUFDS_BLVDS_25;

architecture OBUFDS_BLVDS_25_V of OBUFDS_BLVDS_25 is
begin
  VITALBehavior    : process (I)
    variable O_zd  : std_ulogic;
    variable OB_zd : std_ulogic;

  begin
    O_zd  := TO_X01(I);
    OB_zd := (not O_zd);
    O  <= O_zd;
    OB <= OB_zd;
  end process;
end OBUFDS_BLVDS_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obufds_ldt_25.vhd,v 1.5 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Output Buffer with LDT_25 I/O Standard
-- /___/   /\     Filename : OBUFDS_LDT_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:25 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFDS_LDT_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFDS_LDT_25 is
  port(
    O  : out std_ulogic;
    OB : out std_ulogic;

    I : in std_ulogic
    );
end OBUFDS_LDT_25;

architecture OBUFDS_LDT_25_V of OBUFDS_LDT_25 is
begin
  VITALBehavior    : process (I)
    variable O_zd  : std_ulogic;
    variable OB_zd : std_ulogic;

  begin
    O_zd  := TO_X01(I);
    OB_zd := (not O_zd);
    O  <= O_zd;
    OB <= OB_zd;
  end process;
end OBUFDS_LDT_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obufds_lvds_25.vhd,v 1.5 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Output Buffer with LVDS_25 I/O Standard
-- /___/   /\     Filename : OBUFDS_LVDS_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:25 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFDS_LVDS_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFDS_LVDS_25 is
  port(
    O  : out std_ulogic;
    OB : out std_ulogic;

    I : in std_ulogic
    );
end OBUFDS_LVDS_25;

architecture OBUFDS_LVDS_25_V of OBUFDS_LVDS_25 is
begin
  VITALBehavior    : process (I)
    variable O_zd  : std_ulogic;
    variable OB_zd : std_ulogic;

  begin
    O_zd  := TO_X01(I);
    OB_zd := (not O_zd);
    O  <= O_zd;
    OB <= OB_zd;
  end process;
end OBUFDS_LVDS_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obufds_lvds_33.vhd,v 1.5 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Output Buffer with LVDS_33 I/O Standard
-- /___/   /\     Filename : OBUFDS_LVDS_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:25 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFDS_LVDS_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFDS_LVDS_33 is
  port(
    O  : out std_ulogic;
    OB : out std_ulogic;

    I : in std_ulogic
    );
end OBUFDS_LVDS_33;

architecture OBUFDS_LVDS_33_V of OBUFDS_LVDS_33 is
begin
  VITALBehavior    : process (I)
    variable O_zd  : std_ulogic;
    variable OB_zd : std_ulogic;

  begin
    O_zd  := TO_X01(I);
    OB_zd := (not O_zd);
    O  <= O_zd;
    OB <= OB_zd;
  end process;
end OBUFDS_LVDS_33_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obufds_lvdsext_25.vhd,v 1.5 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Output Buffer with LVDSEXT_25 I/O Standard
-- /___/   /\     Filename : OBUFDS_LVDSEXT_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:25 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFDS_LVDSEXT_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFDS_LVDSEXT_25 is
  port(
    O  : out std_ulogic;
    OB : out std_ulogic;

    I : in std_ulogic
    );
end OBUFDS_LVDSEXT_25;

architecture OBUFDS_LVDSEXT_25_V of OBUFDS_LVDSEXT_25 is
begin
  VITALBehavior    : process (I)
    variable O_zd  : std_ulogic;
    variable OB_zd : std_ulogic;

  begin
    O_zd  := TO_X01(I);
    OB_zd := (not O_zd);
    O  <= O_zd;
    OB <= OB_zd;
  end process;
end OBUFDS_LVDSEXT_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obufds_lvdsext_33.vhd,v 1.5 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Output Buffer with LVDSEXT_33 I/O Standard
-- /___/   /\     Filename : OBUFDS_LVDSEXT_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:25 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFDS_LVDSEXT_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFDS_LVDSEXT_33 is
  port(
    O  : out std_ulogic;
    OB : out std_ulogic;

    I : in std_ulogic
    );
end OBUFDS_LVDSEXT_33;

architecture OBUFDS_LVDSEXT_33_V of OBUFDS_LVDSEXT_33 is
begin
  VITALBehavior    : process (I)
    variable O_zd  : std_ulogic;
    variable OB_zd : std_ulogic;

  begin
    O_zd  := TO_X01(I);
    OB_zd := (not O_zd);
    O  <= O_zd;
    OB <= OB_zd;
  end process;
end OBUFDS_LVDSEXT_33_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obufds_lvpecl_25.vhd,v 1.5 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Output Buffer with LVPECL_25 I/O Standard
-- /___/   /\     Filename : OBUFDS_LVPECL_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:25 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFDS_LVPECL_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFDS_LVPECL_25 is
  port(
    O  : out std_ulogic;
    OB : out std_ulogic;

    I : in std_ulogic
    );
end OBUFDS_LVPECL_25;

architecture OBUFDS_LVPECL_25_V of OBUFDS_LVPECL_25 is
begin
  VITALBehavior    : process (I)
    variable O_zd  : std_ulogic;
    variable OB_zd : std_ulogic;

  begin
    O_zd  := TO_X01(I);
    OB_zd := (not O_zd);
    O  <= O_zd;
    OB <= OB_zd;
  end process;
end OBUFDS_LVPECL_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obufds_lvpecl_33.vhd,v 1.5 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Output Buffer with LVPECL_33 I/O Standard
-- /___/   /\     Filename : OBUFDS_LVPECL_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:26 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFDS_LVPECL_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFDS_LVPECL_33 is
  port(
    O  : out std_ulogic;
    OB : out std_ulogic;

    I : in std_ulogic
    );
end OBUFDS_LVPECL_33;

architecture OBUFDS_LVPECL_33_V of OBUFDS_LVPECL_33 is
begin
  VITALBehavior    : process (I)
    variable O_zd  : std_ulogic;
    variable OB_zd : std_ulogic;

  begin
    O_zd  := TO_X01(I);
    OB_zd := (not O_zd);
    O  <= O_zd;
    OB <= OB_zd;
  end process;
end OBUFDS_LVPECL_33_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obufds_ulvds_25.vhd,v 1.5 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Differential Signaling Output Buffer with ULVDS_25 I/O Standard
-- /___/   /\     Filename : OBUFDS_ULVDS_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:26 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFDS_ULVDS_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFDS_ULVDS_25 is
  port(
    O  : out std_ulogic;
    OB : out std_ulogic;

    I : in std_ulogic
    );
end OBUFDS_ULVDS_25;

architecture OBUFDS_ULVDS_25_V of OBUFDS_ULVDS_25 is
begin
  VITALBehavior    : process (I)
    variable O_zd  : std_ulogic;
    variable OB_zd : std_ulogic;

  begin
    O_zd  := TO_X01(I);
    OB_zd := (not O_zd);
    O  <= O_zd;
    OB <= OB_zd;
  end process;
end OBUFDS_ULVDS_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft.vhd,v 1.5 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer
-- /___/   /\     Filename : OBUFT.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:26 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT is
  generic(
      CAPACITANCE : string     := "DONT_CARE";
      DRIVE       : integer    := 12;
      IOSTANDARD  : string     := "DEFAULT";
      SLEW        : string     := "SLOW"
    );

  port(
    O : out std_ulogic;
    I : in  std_ulogic;
    T : in  std_ulogic
    );

end OBUFT;

architecture OBUFT_V of OBUFT is
begin
  prcs_init : process
  variable FIRST_TIME        : boolean    := TRUE;
  begin

     If(FIRST_TIME = true) then
        if((CAPACITANCE = "LOW") or
           (CAPACITANCE = "NORMAL") or
           (CAPACITANCE = "DONT_CARE")) then
           FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The allowed values for CAPACITANCE are LOW, NORMAL or DONT_CARE"
           severity Failure;
        end if;
     end if;
     wait;
  end process prcs_init;

  VITALBehavior   : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_agp.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with AGP I/O Standard
-- /___/   /\     Filename : OBUFT_AGP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:26 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_AGP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_AGP is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_AGP;

architecture OBUFT_AGP_V of OBUFT_AGP is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_AGP_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_ctt.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with CTT I/O Standard
-- /___/   /\     Filename : OBUFT_CTT.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:26 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_CTT -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_CTT is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_CTT;

architecture OBUFT_CTT_V of OBUFT_CTT is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_CTT_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_f_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with Fast Slew 12 mA Drive
-- /___/   /\     Filename : OBUFT_F_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:26 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_F_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_F_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_F_12;

architecture OBUFT_F_12_V of OBUFT_F_12 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_F_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_f_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with Fast Slew 16 mA Drive
-- /___/   /\     Filename : OBUFT_F_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:26 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_F_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_F_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_F_16;

architecture OBUFT_F_16_V of OBUFT_F_16 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_F_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_f_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with Fast Slew 2 mA Drive
-- /___/   /\     Filename : OBUFT_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:27 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_F_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_F_2;

architecture OBUFT_F_2_V of OBUFT_F_2 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_F_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_f_24.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with Fast Slew 24 mA Drive
-- /___/   /\     Filename : OBUFT_F_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:27 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_F_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_F_24 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_F_24;

architecture OBUFT_F_24_V of OBUFT_F_24 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_F_24_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_f_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with Fast Slew 4 mA Drive
-- /___/   /\     Filename : OBUFT_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:27 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_F_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_F_4;

architecture OBUFT_F_4_V of OBUFT_F_4 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_F_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_f_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with Fast Slew 6 mA Drive
-- /___/   /\     Filename : OBUFT_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:27 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_F_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_F_6;

architecture OBUFT_F_6_V of OBUFT_F_6 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_F_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_f_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with Fast Slew 8 mA Drive
-- /___/   /\     Filename : OBUFT_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:27 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_F_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_F_8;

architecture OBUFT_F_8_V of OBUFT_F_8 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_F_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_gtl.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with GTL I/O Standard
-- /___/   /\     Filename : OBUFT_GTL.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:27 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_GTL -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_GTL is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_GTL;

architecture OBUFT_GTL_V of OBUFT_GTL is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_GTL_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_gtl_dci.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with GTL_DCI I/O Standard
-- /___/   /\     Filename : OBUFT_GTL_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:27 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_GTL_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_GTL_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_GTL_DCI;

architecture OBUFT_GTL_DCI_V of OBUFT_GTL_DCI is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_GTL_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_gtlp.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with GTLP I/O Standard
-- /___/   /\     Filename : OBUFT_GTLP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:27 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_GTLP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_GTLP is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_GTLP;

architecture OBUFT_GTLP_V of OBUFT_GTLP is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_GTLP_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_gtlp_dci.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with GTLP_DCI I/O Standard
-- /___/   /\     Filename : OBUFT_GTLP_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:27 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_GTLP_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_GTLP_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_GTLP_DCI;

architecture OBUFT_GTLP_DCI_V of OBUFT_GTLP_DCI is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_GTLP_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_i.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with HSTL_I I/O Standard
-- /___/   /\     Filename : OBUFT_HSTL_I.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:28 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_HSTL_I -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_HSTL_I is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_HSTL_I;

architecture OBUFT_HSTL_I_V of OBUFT_HSTL_I is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_HSTL_I_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_i_18.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with HSTL_I_18 I/O Standard
-- /___/   /\     Filename : OBUFT_HSTL_I_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:28 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_HSTL_I_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_HSTL_I_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_HSTL_I_18;

architecture OBUFT_HSTL_I_18_V of OBUFT_HSTL_I_18 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_HSTL_I_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_i_dci.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with HSTL_I_DCI I/O Standard
-- /___/   /\     Filename : OBUFT_HSTL_I_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:28 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_HSTL_I_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_HSTL_I_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_HSTL_I_DCI;

architecture OBUFT_HSTL_I_DCI_V of OBUFT_HSTL_I_DCI is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_HSTL_I_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_i_dci_18.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with HSTL_I_DCI_18 I/O Standard
-- /___/   /\     Filename : OBUFT_HSTL_I_DCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:28 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_HSTL_I_DCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_HSTL_I_DCI_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_HSTL_I_DCI_18;

architecture OBUFT_HSTL_I_DCI_18_V of OBUFT_HSTL_I_DCI_18 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_HSTL_I_DCI_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_ii.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with HSTL_II I/O Standard
-- /___/   /\     Filename : OBUFT_HSTL_II.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:28 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_HSTL_II -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_HSTL_II is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_HSTL_II;

architecture OBUFT_HSTL_II_V of OBUFT_HSTL_II is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_HSTL_II_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_ii_18.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with HSTL_II_18 I/O Standard
-- /___/   /\     Filename : OBUFT_HSTL_II_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:28 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_HSTL_II_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_HSTL_II_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_HSTL_II_18;

architecture OBUFT_HSTL_II_18_V of OBUFT_HSTL_II_18 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_HSTL_II_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_ii_dci.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with HSTL_II_DCI I/O Standard
-- /___/   /\     Filename : OBUFT_HSTL_II_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:28 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_HSTL_II_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_HSTL_II_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_HSTL_II_DCI;

architecture OBUFT_HSTL_II_DCI_V of OBUFT_HSTL_II_DCI is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_HSTL_II_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_ii_dci_18.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with HSTL_II_DCI_18 I/O Standard
-- /___/   /\     Filename : OBUFT_HSTL_II_DCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:28 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_HSTL_II_DCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_HSTL_II_DCI_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_HSTL_II_DCI_18;

architecture OBUFT_HSTL_II_DCI_18_V of OBUFT_HSTL_II_DCI_18 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_HSTL_II_DCI_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_iii.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with HSTL_III I/O Standard
-- /___/   /\     Filename : OBUFT_HSTL_III.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:28 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_HSTL_III -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_HSTL_III is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_HSTL_III;

architecture OBUFT_HSTL_III_V of OBUFT_HSTL_III is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_HSTL_III_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_iii_18.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with HSTL_III_18 I/O Standard
-- /___/   /\     Filename : OBUFT_HSTL_III_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:29 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_HSTL_III_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_HSTL_III_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_HSTL_III_18;

architecture OBUFT_HSTL_III_18_V of OBUFT_HSTL_III_18 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_HSTL_III_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_iii_dci.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with HSTL_III_DCI I/O Standard
-- /___/   /\     Filename : OBUFT_HSTL_III_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:29 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_HSTL_III_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_HSTL_III_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_HSTL_III_DCI;

architecture OBUFT_HSTL_III_DCI_V of OBUFT_HSTL_III_DCI is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_HSTL_III_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_iii_dci_18.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with HSTL_III_DCI_18 I/O Standard
-- /___/   /\     Filename : OBUFT_HSTL_III_DCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:29 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_HSTL_III_DCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_HSTL_III_DCI_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_HSTL_III_DCI_18;

architecture OBUFT_HSTL_III_DCI_18_V of OBUFT_HSTL_III_DCI_18 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_HSTL_III_DCI_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_iv.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with HSTL_IV I/O Standard
-- /___/   /\     Filename : OBUFT_HSTL_IV.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:29 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_HSTL_IV -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_HSTL_IV is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_HSTL_IV;

architecture OBUFT_HSTL_IV_V of OBUFT_HSTL_IV is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_HSTL_IV_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_iv_18.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with HSTL_IV_18 I/O Standard
-- /___/   /\     Filename : OBUFT_HSTL_IV_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:29 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_HSTL_IV_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_HSTL_IV_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_HSTL_IV_18;

architecture OBUFT_HSTL_IV_18_V of OBUFT_HSTL_IV_18 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_HSTL_IV_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_iv_dci.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with HSTL_IV_DCI I/O Standard
-- /___/   /\     Filename : OBUFT_HSTL_IV_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:29 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_HSTL_IV_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_HSTL_IV_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_HSTL_IV_DCI;

architecture OBUFT_HSTL_IV_DCI_V of OBUFT_HSTL_IV_DCI is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_HSTL_IV_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_iv_dci_18.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with HSTL_IV_DCI_18 I/O Standard
-- /___/   /\     Filename : OBUFT_HSTL_IV_DCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:29 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_HSTL_IV_DCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_HSTL_IV_DCI_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_HSTL_IV_DCI_18;

architecture OBUFT_HSTL_IV_DCI_18_V of OBUFT_HSTL_IV_DCI_18 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_HSTL_IV_DCI_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS12 I/O Standard
-- /___/   /\     Filename : OBUFT_LVCMOS12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:29 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS12;

architecture OBUFT_LVCMOS12_V of OBUFT_LVCMOS12 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos12_f_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS12 I/O Standard Fast Slew 2 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS12_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:29 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS12_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS12_F_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS12_F_2;

architecture OBUFT_LVCMOS12_F_2_V of OBUFT_LVCMOS12_F_2 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS12_F_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos12_f_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS12 I/O Standard Fast Slew 4 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS12_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:30 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS12_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS12_F_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS12_F_4;

architecture OBUFT_LVCMOS12_F_4_V of OBUFT_LVCMOS12_F_4 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS12_F_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos12_f_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS12 I/O Standard Fast Slew 6 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS12_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:30 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS12_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS12_F_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS12_F_6;

architecture OBUFT_LVCMOS12_F_6_V of OBUFT_LVCMOS12_F_6 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS12_F_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos12_f_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS12 I/O Standard Fast Slew 8 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS12_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:30 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS12_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS12_F_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS12_F_8;

architecture OBUFT_LVCMOS12_F_8_V of OBUFT_LVCMOS12_F_8 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS12_F_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos12_s_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS12 I/O Standard Slow Slew 2 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS12_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:30 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS12_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS12_S_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS12_S_2;

architecture OBUFT_LVCMOS12_S_2_V of OBUFT_LVCMOS12_S_2 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS12_S_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos12_s_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS12 I/O Standard Slow Slew 4 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS12_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:30 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS12_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS12_S_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS12_S_4;

architecture OBUFT_LVCMOS12_S_4_V of OBUFT_LVCMOS12_S_4 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS12_S_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos12_s_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS12 I/O Standard Slow Slew 6 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS12_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:30 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS12_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS12_S_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS12_S_6;

architecture OBUFT_LVCMOS12_S_6_V of OBUFT_LVCMOS12_S_6 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS12_S_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos12_s_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS12 I/O Standard Slow Slew 8 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS12_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:30 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS12_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS12_S_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS12_S_8;

architecture OBUFT_LVCMOS12_S_8_V of OBUFT_LVCMOS12_S_8 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS12_S_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS15 I/O Standard
-- /___/   /\     Filename : OBUFT_LVCMOS15.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:30 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS15 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS15 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS15;

architecture OBUFT_LVCMOS15_V of OBUFT_LVCMOS15 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS15_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_f_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS15 I/O Standard Fast Slew 12 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS15_F_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:30 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS15_F_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS15_F_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS15_F_12;

architecture OBUFT_LVCMOS15_F_12_V of OBUFT_LVCMOS15_F_12 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS15_F_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_f_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS15 I/O Standard Fast Slew 16 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS15_F_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:31 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS15_F_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS15_F_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS15_F_16;

architecture OBUFT_LVCMOS15_F_16_V of OBUFT_LVCMOS15_F_16 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS15_F_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_f_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS15 I/O Standard Fast Slew 2 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS15_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:31 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS15_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS15_F_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS15_F_2;

architecture OBUFT_LVCMOS15_F_2_V of OBUFT_LVCMOS15_F_2 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS15_F_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_f_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS15 I/O Standard Fast Slew 4 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS15_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:31 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS15_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS15_F_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS15_F_4;

architecture OBUFT_LVCMOS15_F_4_V of OBUFT_LVCMOS15_F_4 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS15_F_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_f_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS15 I/O Standard Fast Slew 6 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS15_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:31 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS15_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS15_F_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS15_F_6;

architecture OBUFT_LVCMOS15_F_6_V of OBUFT_LVCMOS15_F_6 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS15_F_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_f_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS15 I/O Standard Fast Slew 8 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS15_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:31 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS15_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS15_F_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS15_F_8;

architecture OBUFT_LVCMOS15_F_8_V of OBUFT_LVCMOS15_F_8 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS15_F_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_s_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS15 I/O Standard Slow Slew 12 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS15_S_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:31 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS15_S_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS15_S_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS15_S_12;

architecture OBUFT_LVCMOS15_S_12_V of OBUFT_LVCMOS15_S_12 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS15_S_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_s_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS15 I/O Standard Slow Slew 16 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS15_S_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:31 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS15_S_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS15_S_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS15_S_16;

architecture OBUFT_LVCMOS15_S_16_V of OBUFT_LVCMOS15_S_16 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS15_S_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_s_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS15 I/O Standard Slow Slew 2 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS15_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:31 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS15_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS15_S_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS15_S_2;

architecture OBUFT_LVCMOS15_S_2_V of OBUFT_LVCMOS15_S_2 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS15_S_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_s_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS15 I/O Standard Slow Slew 4 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS15_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:31 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS15_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS15_S_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS15_S_4;

architecture OBUFT_LVCMOS15_S_4_V of OBUFT_LVCMOS15_S_4 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS15_S_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_s_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS15 I/O Standard Slow Slew 6 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS15_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:32 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS15_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS15_S_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS15_S_6;

architecture OBUFT_LVCMOS15_S_6_V of OBUFT_LVCMOS15_S_6 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS15_S_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_s_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS15 I/O Standard Slow Slew 8 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS15_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:32 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS15_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS15_S_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS15_S_8;

architecture OBUFT_LVCMOS15_S_8_V of OBUFT_LVCMOS15_S_8 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS15_S_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS18 I/O Standard
-- /___/   /\     Filename : OBUFT_LVCMOS18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:32 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS18;

architecture OBUFT_LVCMOS18_V of OBUFT_LVCMOS18 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_f_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS18 I/O Standard Fast Slew 12 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS18_F_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:32 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS18_F_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS18_F_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS18_F_12;

architecture OBUFT_LVCMOS18_F_12_V of OBUFT_LVCMOS18_F_12 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS18_F_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_f_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS18 I/O Standard Fast Slew 16 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS18_F_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:32 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS18_F_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS18_F_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS18_F_16;

architecture OBUFT_LVCMOS18_F_16_V of OBUFT_LVCMOS18_F_16 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS18_F_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_f_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS18 I/O Standard Fast Slew 2 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS18_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:32 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS18_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS18_F_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS18_F_2;

architecture OBUFT_LVCMOS18_F_2_V of OBUFT_LVCMOS18_F_2 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS18_F_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_f_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS18 I/O Standard Fast Slew 4 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS18_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:32 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS18_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS18_F_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS18_F_4;

architecture OBUFT_LVCMOS18_F_4_V of OBUFT_LVCMOS18_F_4 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS18_F_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_f_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS18 I/O Standard Fast Slew 6 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS18_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:32 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS18_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS18_F_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS18_F_6;

architecture OBUFT_LVCMOS18_F_6_V of OBUFT_LVCMOS18_F_6 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS18_F_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_f_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS18 I/O Standard Fast Slew 8 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS18_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:32 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS18_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS18_F_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS18_F_8;

architecture OBUFT_LVCMOS18_F_8_V of OBUFT_LVCMOS18_F_8 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS18_F_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_s_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS18 I/O Standard Slow Slew 12 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS18_S_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:33 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS18_S_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS18_S_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS18_S_12;

architecture OBUFT_LVCMOS18_S_12_V of OBUFT_LVCMOS18_S_12 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS18_S_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_s_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS18 I/O Standard Slow Slew 16 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS18_S_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:33 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS18_S_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS18_S_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS18_S_16;

architecture OBUFT_LVCMOS18_S_16_V of OBUFT_LVCMOS18_S_16 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS18_S_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_s_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS18 I/O Standard Slow Slew 2 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS18_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:33 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS18_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS18_S_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS18_S_2;

architecture OBUFT_LVCMOS18_S_2_V of OBUFT_LVCMOS18_S_2 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS18_S_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_s_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS18 I/O Standard Slow Slew 4 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS18_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:33 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS18_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS18_S_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS18_S_4;

architecture OBUFT_LVCMOS18_S_4_V of OBUFT_LVCMOS18_S_4 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS18_S_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_s_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS18 I/O Standard Slow Slew 6 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS18_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:33 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS18_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS18_S_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS18_S_6;

architecture OBUFT_LVCMOS18_S_6_V of OBUFT_LVCMOS18_S_6 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS18_S_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_s_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS18 I/O Standard Slow Slew 8 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS18_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:33 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS18_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS18_S_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS18_S_8;

architecture OBUFT_LVCMOS18_S_8_V of OBUFT_LVCMOS18_S_8 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS18_S_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS2 I/O Standard
-- /___/   /\     Filename : OBUFT_LVCMOS2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:33 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS2;

architecture OBUFT_LVCMOS2_V of OBUFT_LVCMOS2 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS25 I/O Standard
-- /___/   /\     Filename : OBUFT_LVCMOS25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:33 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS25 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS25;

architecture OBUFT_LVCMOS25_V of OBUFT_LVCMOS25 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS25_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_f_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 12 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS25_F_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:33 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS25_F_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS25_F_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS25_F_12;

architecture OBUFT_LVCMOS25_F_12_V of OBUFT_LVCMOS25_F_12 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS25_F_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_f_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 16 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS25_F_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:34 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS25_F_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS25_F_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS25_F_16;

architecture OBUFT_LVCMOS25_F_16_V of OBUFT_LVCMOS25_F_16 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS25_F_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_f_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 2 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS25_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:34 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS25_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS25_F_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS25_F_2;

architecture OBUFT_LVCMOS25_F_2_V of OBUFT_LVCMOS25_F_2 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS25_F_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_f_24.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 24 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS25_F_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:34 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS25_F_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS25_F_24 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS25_F_24;

architecture OBUFT_LVCMOS25_F_24_V of OBUFT_LVCMOS25_F_24 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS25_F_24_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_f_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 4 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS25_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:34 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS25_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS25_F_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS25_F_4;

architecture OBUFT_LVCMOS25_F_4_V of OBUFT_LVCMOS25_F_4 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS25_F_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_f_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 6 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS25_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:34 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS25_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS25_F_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS25_F_6;

architecture OBUFT_LVCMOS25_F_6_V of OBUFT_LVCMOS25_F_6 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS25_F_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_f_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 8 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS25_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:34 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS25_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS25_F_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS25_F_8;

architecture OBUFT_LVCMOS25_F_8_V of OBUFT_LVCMOS25_F_8 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS25_F_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_s_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 12 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS25_S_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:34 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS25_S_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS25_S_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS25_S_12;

architecture OBUFT_LVCMOS25_S_12_V of OBUFT_LVCMOS25_S_12 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS25_S_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_s_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 16 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS25_S_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:34 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS25_S_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS25_S_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS25_S_16;

architecture OBUFT_LVCMOS25_S_16_V of OBUFT_LVCMOS25_S_16 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS25_S_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_s_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 2 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS25_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:34 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS25_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS25_S_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS25_S_2;

architecture OBUFT_LVCMOS25_S_2_V of OBUFT_LVCMOS25_S_2 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS25_S_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_s_24.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 24 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS25_S_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:35 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS25_S_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS25_S_24 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS25_S_24;

architecture OBUFT_LVCMOS25_S_24_V of OBUFT_LVCMOS25_S_24 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS25_S_24_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_s_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 4 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS25_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:35 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS25_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS25_S_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS25_S_4;

architecture OBUFT_LVCMOS25_S_4_V of OBUFT_LVCMOS25_S_4 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS25_S_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_s_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 6 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS25_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:35 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS25_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS25_S_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS25_S_6;

architecture OBUFT_LVCMOS25_S_6_V of OBUFT_LVCMOS25_S_6 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS25_S_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_s_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 8 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS25_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:35 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS25_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS25_S_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS25_S_8;

architecture OBUFT_LVCMOS25_S_8_V of OBUFT_LVCMOS25_S_8 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS25_S_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS33 I/O Standard
-- /___/   /\     Filename : OBUFT_LVCMOS33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:35 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS33 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS33;

architecture OBUFT_LVCMOS33_V of OBUFT_LVCMOS33 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS33_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_f_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 12 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS33_F_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:35 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS33_F_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS33_F_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS33_F_12;

architecture OBUFT_LVCMOS33_F_12_V of OBUFT_LVCMOS33_F_12 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS33_F_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_f_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 16 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS33_F_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:35 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS33_F_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS33_F_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS33_F_16;

architecture OBUFT_LVCMOS33_F_16_V of OBUFT_LVCMOS33_F_16 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS33_F_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_f_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 2 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS33_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:35 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS33_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS33_F_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS33_F_2;

architecture OBUFT_LVCMOS33_F_2_V of OBUFT_LVCMOS33_F_2 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS33_F_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_f_24.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 24 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS33_F_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:35 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS33_F_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS33_F_24 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS33_F_24;

architecture OBUFT_LVCMOS33_F_24_V of OBUFT_LVCMOS33_F_24 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS33_F_24_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_f_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 4 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS33_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:36 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS33_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS33_F_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS33_F_4;

architecture OBUFT_LVCMOS33_F_4_V of OBUFT_LVCMOS33_F_4 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS33_F_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_f_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 6 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS33_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:36 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS33_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS33_F_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS33_F_6;

architecture OBUFT_LVCMOS33_F_6_V of OBUFT_LVCMOS33_F_6 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS33_F_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_f_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 8 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS33_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:36 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS33_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS33_F_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS33_F_8;

architecture OBUFT_LVCMOS33_F_8_V of OBUFT_LVCMOS33_F_8 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS33_F_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_s_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 12 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS33_S_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:36 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS33_S_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS33_S_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS33_S_12;

architecture OBUFT_LVCMOS33_S_12_V of OBUFT_LVCMOS33_S_12 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS33_S_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_s_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 16 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS33_S_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:36 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS33_S_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS33_S_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS33_S_16;

architecture OBUFT_LVCMOS33_S_16_V of OBUFT_LVCMOS33_S_16 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS33_S_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_s_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 2 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS33_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:36 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS33_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS33_S_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS33_S_2;

architecture OBUFT_LVCMOS33_S_2_V of OBUFT_LVCMOS33_S_2 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS33_S_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_s_24.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 24 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS33_S_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:36 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS33_S_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS33_S_24 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS33_S_24;

architecture OBUFT_LVCMOS33_S_24_V of OBUFT_LVCMOS33_S_24 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS33_S_24_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_s_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 4 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS33_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:36 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS33_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS33_S_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS33_S_4;

architecture OBUFT_LVCMOS33_S_4_V of OBUFT_LVCMOS33_S_4 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS33_S_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_s_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 6 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS33_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:36 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS33_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS33_S_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS33_S_6;

architecture OBUFT_LVCMOS33_S_6_V of OBUFT_LVCMOS33_S_6 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS33_S_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_s_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 8 mA Drive
-- /___/   /\     Filename : OBUFT_LVCMOS33_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:37 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVCMOS33_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVCMOS33_S_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVCMOS33_S_8;

architecture OBUFT_LVCMOS33_S_8_V of OBUFT_LVCMOS33_S_8 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVCMOS33_S_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvdci_15.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVDCI_15 I/O Standard
-- /___/   /\     Filename : OBUFT_LVDCI_15.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:37 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVDCI_15 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVDCI_15 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVDCI_15;

architecture OBUFT_LVDCI_15_V of OBUFT_LVDCI_15 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVDCI_15_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvdci_18.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVDCI_18 I/O Standard
-- /___/   /\     Filename : OBUFT_LVDCI_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:37 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVDCI_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVDCI_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVDCI_18;

architecture OBUFT_LVDCI_18_V of OBUFT_LVDCI_18 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVDCI_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvdci_25.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVDCI_25 I/O Standard
-- /___/   /\     Filename : OBUFT_LVDCI_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:37 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVDCI_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVDCI_25 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVDCI_25;

architecture OBUFT_LVDCI_25_V of OBUFT_LVDCI_25 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVDCI_25_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvdci_33.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVDCI_33 I/O Standard
-- /___/   /\     Filename : OBUFT_LVDCI_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:37 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVDCI_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVDCI_33 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVDCI_33;

architecture OBUFT_LVDCI_33_V of OBUFT_LVDCI_33 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVDCI_33_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvdci_dv2_15.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVDCI_DV2_15 I/O Standard
-- /___/   /\     Filename : OBUFT_LVDCI_DV2_15.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:37 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVDCI_DV2_15 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVDCI_DV2_15 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVDCI_DV2_15;

architecture OBUFT_LVDCI_DV2_15_V of OBUFT_LVDCI_DV2_15 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVDCI_DV2_15_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvdci_dv2_18.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVDCI_DV2_18 I/O Standard
-- /___/   /\     Filename : OBUFT_LVDCI_DV2_18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:37 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVDCI_DV2_18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVDCI_DV2_18 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVDCI_DV2_18;

architecture OBUFT_LVDCI_DV2_18_V of OBUFT_LVDCI_DV2_18 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVDCI_DV2_18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvdci_dv2_25.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVDCI_DV2_25 I/O Standard
-- /___/   /\     Filename : OBUFT_LVDCI_DV2_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:37 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVDCI_DV2_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVDCI_DV2_25 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVDCI_DV2_25;

architecture OBUFT_LVDCI_DV2_25_V of OBUFT_LVDCI_DV2_25 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVDCI_DV2_25_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvdci_dv2_33.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVDCI_DV2_33 I/O Standard
-- /___/   /\     Filename : OBUFT_LVDCI_DV2_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:37 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVDCI_DV2_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVDCI_DV2_33 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVDCI_DV2_33;

architecture OBUFT_LVDCI_DV2_33_V of OBUFT_LVDCI_DV2_33 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVDCI_DV2_33_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvds.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVDS I/O Standard
-- /___/   /\     Filename : OBUFT_LVDS.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:38 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVDS -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVDS is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVDS;

architecture OBUFT_LVDS_V of OBUFT_LVDS is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVDS_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvpecl.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVPECL I/O Standard
-- /___/   /\     Filename : OBUFT_LVPECL.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:38 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVPECL -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVPECL is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVPECL;

architecture OBUFT_LVPECL_V of OBUFT_LVPECL is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVPECL_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVTTL I/O Standard
-- /___/   /\     Filename : OBUFT_LVTTL.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:38 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVTTL -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVTTL is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVTTL;

architecture OBUFT_LVTTL_V of OBUFT_LVTTL is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVTTL_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_f_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVTTL I/O Standard Fast Slew 12 mA Drive
-- /___/   /\     Filename : OBUFT_LVTTL_F_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:38 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVTTL_F_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVTTL_F_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVTTL_F_12;

architecture OBUFT_LVTTL_F_12_V of OBUFT_LVTTL_F_12 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVTTL_F_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_f_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVTTL I/O Standard Fast Slew 16 mA Drive
-- /___/   /\     Filename : OBUFT_LVTTL_F_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:38 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVTTL_F_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVTTL_F_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVTTL_F_16;

architecture OBUFT_LVTTL_F_16_V of OBUFT_LVTTL_F_16 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVTTL_F_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_f_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVTTL I/O Standard Fast Slew 2 mA Drive
-- /___/   /\     Filename : OBUFT_LVTTL_F_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:38 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVTTL_F_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVTTL_F_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVTTL_F_2;

architecture OBUFT_LVTTL_F_2_V of OBUFT_LVTTL_F_2 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVTTL_F_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_f_24.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVTTL I/O Standard Fast Slew 24 mA Drive
-- /___/   /\     Filename : OBUFT_LVTTL_F_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:38 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVTTL_F_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVTTL_F_24 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVTTL_F_24;

architecture OBUFT_LVTTL_F_24_V of OBUFT_LVTTL_F_24 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVTTL_F_24_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_f_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVTTL I/O Standard Fast Slew 4 mA Drive
-- /___/   /\     Filename : OBUFT_LVTTL_F_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:38 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVTTL_F_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVTTL_F_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVTTL_F_4;

architecture OBUFT_LVTTL_F_4_V of OBUFT_LVTTL_F_4 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVTTL_F_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_f_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVTTL I/O Standard Fast Slew 6 mA Drive
-- /___/   /\     Filename : OBUFT_LVTTL_F_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:39 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVTTL_F_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVTTL_F_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVTTL_F_6;

architecture OBUFT_LVTTL_F_6_V of OBUFT_LVTTL_F_6 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVTTL_F_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_f_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVTTL I/O Standard Fast Slew 8 mA Drive
-- /___/   /\     Filename : OBUFT_LVTTL_F_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:39 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVTTL_F_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVTTL_F_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVTTL_F_8;

architecture OBUFT_LVTTL_F_8_V of OBUFT_LVTTL_F_8 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVTTL_F_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_s_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVTTL I/O Standard Slow Slew 12 mA Drive
-- /___/   /\     Filename : OBUFT_LVTTL_S_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:39 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVTTL_S_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVTTL_S_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVTTL_S_12;

architecture OBUFT_LVTTL_S_12_V of OBUFT_LVTTL_S_12 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVTTL_S_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_s_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVTTL I/O Standard Slow Slew 16 mA Drive
-- /___/   /\     Filename : OBUFT_LVTTL_S_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:39 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVTTL_S_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVTTL_S_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVTTL_S_16;

architecture OBUFT_LVTTL_S_16_V of OBUFT_LVTTL_S_16 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVTTL_S_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_s_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVTTL I/O Standard Slow Slew 2 mA Drive
-- /___/   /\     Filename : OBUFT_LVTTL_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:39 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVTTL_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVTTL_S_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVTTL_S_2;

architecture OBUFT_LVTTL_S_2_V of OBUFT_LVTTL_S_2 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVTTL_S_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_s_24.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVTTL I/O Standard Slow Slew 24 mA Drive
-- /___/   /\     Filename : OBUFT_LVTTL_S_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:39 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVTTL_S_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVTTL_S_24 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVTTL_S_24;

architecture OBUFT_LVTTL_S_24_V of OBUFT_LVTTL_S_24 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVTTL_S_24_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_s_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVTTL I/O Standard Slow Slew 4 mA Drive
-- /___/   /\     Filename : OBUFT_LVTTL_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:39 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVTTL_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVTTL_S_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVTTL_S_4;

architecture OBUFT_LVTTL_S_4_V of OBUFT_LVTTL_S_4 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVTTL_S_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_s_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVTTL I/O Standard Slow Slew 6 mA Drive
-- /___/   /\     Filename : OBUFT_LVTTL_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:39 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVTTL_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVTTL_S_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVTTL_S_6;

architecture OBUFT_LVTTL_S_6_V of OBUFT_LVTTL_S_6 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVTTL_S_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_s_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with LVTTL I/O Standard Slow Slew 8 mA Drive
-- /___/   /\     Filename : OBUFT_LVTTL_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:39 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_LVTTL_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_LVTTL_S_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_LVTTL_S_8;

architecture OBUFT_LVTTL_S_8_V of OBUFT_LVTTL_S_8 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_LVTTL_S_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_pci33_3.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with PCI33_3 I/O Standard
-- /___/   /\     Filename : OBUFT_PCI33_3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:40 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_PCI33_3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_PCI33_3 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_PCI33_3;

architecture OBUFT_PCI33_3_V of OBUFT_PCI33_3 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_PCI33_3_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_pci33_5.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with PCI33_5 I/O Standard
-- /___/   /\     Filename : OBUFT_PCI33_5.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:40 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_PCI33_5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_PCI33_5 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_PCI33_5;

architecture OBUFT_PCI33_5_V of OBUFT_PCI33_5 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_PCI33_5_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_pci66_3.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with PCI66_3 I/O Standard
-- /___/   /\     Filename : OBUFT_PCI66_3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:40 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_PCI66_3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_PCI66_3 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_PCI66_3;

architecture OBUFT_PCI66_3_V of OBUFT_PCI66_3 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_PCI66_3_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_pcix.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with PCIX I/O Standard
-- /___/   /\     Filename : OBUFT_PCIX.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:40 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_PCIX -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_PCIX is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_PCIX;

architecture OBUFT_PCIX_V of OBUFT_PCIX is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_PCIX_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_pcix66_3.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with PCIX66_3 I/O Standard
-- /___/   /\     Filename : OBUFT_PCIX66_3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:40 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_PCIX66_3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_PCIX66_3 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_PCIX66_3;

architecture OBUFT_PCIX66_3_V of OBUFT_PCIX66_3 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_PCIX66_3_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_s_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with Slow Slew 12 mA Drive
-- /___/   /\     Filename : OBUFT_S_12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:40 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_S_12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_S_12 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_S_12;

architecture OBUFT_S_12_V of OBUFT_S_12 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_S_12_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_s_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with Slow Slew 16 mA Drive
-- /___/   /\     Filename : OBUFT_S_16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:40 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_S_16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_S_16 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_S_16;

architecture OBUFT_S_16_V of OBUFT_S_16 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_S_16_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_s_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with Slow Slew 2 mA Drive
-- /___/   /\     Filename : OBUFT_S_2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:40 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_S_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_S_2 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_S_2;

architecture OBUFT_S_2_V of OBUFT_S_2 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_S_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_s_24.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with Slow Slew 24 mA Drive
-- /___/   /\     Filename : OBUFT_S_24.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:41 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_S_24 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_S_24 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_S_24;

architecture OBUFT_S_24_V of OBUFT_S_24 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_S_24_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_s_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with Slow Slew 4 mA Drive
-- /___/   /\     Filename : OBUFT_S_4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:41 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_S_4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_S_4 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_S_4;

architecture OBUFT_S_4_V of OBUFT_S_4 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_S_4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_s_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with Slow Slew 6 mA Drive
-- /___/   /\     Filename : OBUFT_S_6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:41 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_S_6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_S_6 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_S_6;

architecture OBUFT_S_6_V of OBUFT_S_6 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_S_6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_s_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with Slow Slew 8 mA Drive
-- /___/   /\     Filename : OBUFT_S_8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:41 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_S_8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_S_8 is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_S_8;

architecture OBUFT_S_8_V of OBUFT_S_8 is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_S_8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl18_i.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with SSTL18_I I/O Standard
-- /___/   /\     Filename : OBUFT_SSTL18_I.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:41 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_SSTL18_I -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_SSTL18_I is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_SSTL18_I;

architecture OBUFT_SSTL18_I_V of OBUFT_SSTL18_I is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_SSTL18_I_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl18_i_dci.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with SSTL18_I_DCI I/O Standard
-- /___/   /\     Filename : OBUFT_SSTL18_I_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:41 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_SSTL18_I_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_SSTL18_I_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_SSTL18_I_DCI;

architecture OBUFT_SSTL18_I_DCI_V of OBUFT_SSTL18_I_DCI is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_SSTL18_I_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl18_ii.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with SSTL18_II I/O Standard
-- /___/   /\     Filename : OBUFT_SSTL18_II.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:41 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_SSTL18_II -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_SSTL18_II is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_SSTL18_II;

architecture OBUFT_SSTL18_II_V of OBUFT_SSTL18_II is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_SSTL18_II_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl18_ii_dci.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with SSTL18_II_DCI I/O Standard
-- /___/   /\     Filename : OBUFT_SSTL18_II_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:41 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_SSTL18_II_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_SSTL18_II_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_SSTL18_II_DCI;

architecture OBUFT_SSTL18_II_DCI_V of OBUFT_SSTL18_II_DCI is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_SSTL18_II_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl2_i.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with SSTL2_I I/O Standard
-- /___/   /\     Filename : OBUFT_SSTL2_I.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:42 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_SSTL2_I -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_SSTL2_I is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_SSTL2_I;

architecture OBUFT_SSTL2_I_V of OBUFT_SSTL2_I is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_SSTL2_I_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl2_i_dci.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with SSTL2_I_DCI I/O Standard
-- /___/   /\     Filename : OBUFT_SSTL2_I_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:42 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_SSTL2_I_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_SSTL2_I_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_SSTL2_I_DCI;

architecture OBUFT_SSTL2_I_DCI_V of OBUFT_SSTL2_I_DCI is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_SSTL2_I_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl2_ii.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with SSTL2_II I/O Standard
-- /___/   /\     Filename : OBUFT_SSTL2_II.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:42 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_SSTL2_II -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_SSTL2_II is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_SSTL2_II;

architecture OBUFT_SSTL2_II_V of OBUFT_SSTL2_II is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_SSTL2_II_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl2_ii_dci.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with SSTL2_II_DCI I/O Standard
-- /___/   /\     Filename : OBUFT_SSTL2_II_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:42 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_SSTL2_II_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_SSTL2_II_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_SSTL2_II_DCI;

architecture OBUFT_SSTL2_II_DCI_V of OBUFT_SSTL2_II_DCI is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_SSTL2_II_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl3_i.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with SSTL3_I I/O Standard
-- /___/   /\     Filename : OBUFT_SSTL3_I.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:42 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_SSTL3_I -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_SSTL3_I is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_SSTL3_I;

architecture OBUFT_SSTL3_I_V of OBUFT_SSTL3_I is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_SSTL3_I_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl3_i_dci.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with SSTL3_I_DCI I/O Standard
-- /___/   /\     Filename : OBUFT_SSTL3_I_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:42 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_SSTL3_I_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_SSTL3_I_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_SSTL3_I_DCI;

architecture OBUFT_SSTL3_I_DCI_V of OBUFT_SSTL3_I_DCI is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_SSTL3_I_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl3_ii.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with SSTL3_II I/O Standard
-- /___/   /\     Filename : OBUFT_SSTL3_II.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:42 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_SSTL3_II -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_SSTL3_II is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_SSTL3_II;

architecture OBUFT_SSTL3_II_V of OBUFT_SSTL3_II is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_SSTL3_II_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl3_ii_dci.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer with SSTL3_II_DCI I/O Standard
-- /___/   /\     Filename : OBUFT_SSTL3_II_DCI.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:42 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFT_SSTL3_II_DCI -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFT_SSTL3_II_DCI is
  port(
    O : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );

end OBUFT_SSTL3_II_DCI;

architecture OBUFT_SSTL3_II_DCI_V of OBUFT_SSTL3_II_DCI is
begin
  VITALBehavior    : process (I, T)
  begin
    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;
  end process;
end OBUFT_SSTL3_II_DCI_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuftds.vhd,v 1.5 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Differential Signaling Output Buffer
-- /___/   /\     Filename : OBUFTDS.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:42 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFTDS -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFTDS is
  generic(
      CAPACITANCE : string     := "DONT_CARE";
      IOSTANDARD  : string     := "DEFAULT"
    );

  port(
    O  : out std_ulogic;
    OB : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );
end OBUFTDS;

architecture OBUFTDS_V of OBUFTDS is
begin
  prcs_init : process
  variable FIRST_TIME        : boolean    := TRUE;
  begin

     If(FIRST_TIME = true) then
        if((CAPACITANCE = "LOW") or
           (CAPACITANCE = "NORMAL") or
           (CAPACITANCE = "DONT_CARE")) then
           FIRST_TIME := false;
        else
           assert false
           report "Attribute Syntax Error: The allowed values for CAPACITANCE are LOW, NORMAL or DONT_CARE"
           severity Failure;
        end if;
     end if;
     wait;
  end process prcs_init;

  VITALBehavior    : process (I, T)
  begin

    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;

    if ((T = '1') or (T = 'H')) then
      OB <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if (((not I) = '1') or ((not I) = 'H')) then
        OB <= '1';
      elsif (((not I) = '0') or ((not I) = 'L')) then
        OB <= '0';
      elsif ((not I) = 'U') then
        OB <= 'U';
      else
        OB <= 'X';  
      end if;
    elsif (T = 'U') then
      OB <= 'U';          
    else                                      
      OB <= 'X';  
    end if;        
  end process;
end OBUFTDS_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuftds_blvds_25.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Differential Signaling Output Buffer with BLVDS_25 I/O Standard
-- /___/   /\     Filename : OBUFTDS_BLVDS_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:43 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFTDS_BLVDS_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFTDS_BLVDS_25 is
  port(
    O  : out std_ulogic;
    OB : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );
end OBUFTDS_BLVDS_25;

architecture OBUFTDS_BLVDS_25_V of OBUFTDS_BLVDS_25 is
begin
  VITALBehavior    : process (I, T)
    variable O_zd  : std_ulogic;
    variable OB_zd : std_ulogic;
  begin

    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;

    if ((T = '1') or (T = 'H')) then
      OB <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if (((not I) = '1') or ((not I) = 'H')) then
        OB <= '1';
      elsif (((not I) = '0') or ((not I) = 'L')) then
        OB <= '0';
      elsif ((not I) = 'U') then
        OB <= 'U';
      else
        OB <= 'X';  
      end if;
    elsif (T = 'U') then
      OB <= 'U';          
    else                                      
      OB <= 'X';  
    end if;            
  end process;
end OBUFTDS_BLVDS_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuftds_ldt_25.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Differential Signaling Output Buffer with LDT_25 I/O Standard
-- /___/   /\     Filename : OBUFTDS_LDT_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:43 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFTDS_LDT_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFTDS_LDT_25 is
  port(
    O  : out std_ulogic;
    OB : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );
end OBUFTDS_LDT_25;

architecture OBUFTDS_LDT_25_V of OBUFTDS_LDT_25 is
begin
  VITALBehavior    : process (I, T)
    variable O_zd  : std_ulogic;
    variable OB_zd : std_ulogic;
  begin

    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;

    if ((T = '1') or (T = 'H')) then
      OB <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if (((not I) = '1') or ((not I) = 'H')) then
        OB <= '1';
      elsif (((not I) = '0') or ((not I) = 'L')) then
        OB <= '0';
      elsif ((not I) = 'U') then
        OB <= 'U';
      else
        OB <= 'X';  
      end if;
    elsif (T = 'U') then
      OB <= 'U';          
    else                                      
      OB <= 'X';  
    end if;            
  end process;
end OBUFTDS_LDT_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuftds_lvds_25.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Differential Signaling Output Buffer with LVDS_25 I/O Standard
-- /___/   /\     Filename : OBUFTDS_LVDS_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:43 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFTDS_LVDS_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFTDS_LVDS_25 is
  port(
    O  : out std_ulogic;
    OB : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );
end OBUFTDS_LVDS_25;

architecture OBUFTDS_LVDS_25_V of OBUFTDS_LVDS_25 is
begin
  VITALBehavior    : process (I, T)
    variable O_zd  : std_ulogic;
    variable OB_zd : std_ulogic;
  begin

    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;

    if ((T = '1') or (T = 'H')) then
      OB <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if (((not I) = '1') or ((not I) = 'H')) then
        OB <= '1';
      elsif (((not I) = '0') or ((not I) = 'L')) then
        OB <= '0';
      elsif ((not I) = 'U') then
        OB <= 'U';
      else
        OB <= 'X';  
      end if;
    elsif (T = 'U') then
      OB <= 'U';          
    else                                      
      OB <= 'X';  
    end if;            
  end process;
end OBUFTDS_LVDS_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuftds_lvds_33.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Differential Signaling Output Buffer with LVDS_33 I/O Standard
-- /___/   /\     Filename : OBUFTDS_LVDS_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:43 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFTDS_LVDS_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFTDS_LVDS_33 is
  port(
    O  : out std_ulogic;
    OB : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );
end OBUFTDS_LVDS_33;

architecture OBUFTDS_LVDS_33_V of OBUFTDS_LVDS_33 is
begin
  VITALBehavior    : process (I, T)
  begin

    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;

    if ((T = '1') or (T = 'H')) then
      OB <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if (((not I) = '1') or ((not I) = 'H')) then
        OB <= '1';
      elsif (((not I) = '0') or ((not I) = 'L')) then
        OB <= '0';
      elsif ((not I) = 'U') then
        OB <= 'U';
      else
        OB <= 'X';  
      end if;
    elsif (T = 'U') then
      OB <= 'U';          
    else                                      
      OB <= 'X';  
    end if;            
  end process;
end OBUFTDS_LVDS_33_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuftds_lvdsext_25.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Differential Signaling Output Buffer with LVDSEXT_25 I/O Standard
-- /___/   /\     Filename : OBUFTDS_LVDSEXT_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:43 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFTDS_LVDSEXT_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFTDS_LVDSEXT_25 is
  port(
    O  : out std_ulogic;
    OB : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );
end OBUFTDS_LVDSEXT_25;

architecture OBUFTDS_LVDSEXT_25_V of OBUFTDS_LVDSEXT_25 is
begin
  VITALBehavior    : process (I, T)
  begin

    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;

    if ((T = '1') or (T = 'H')) then
      OB <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if (((not I) = '1') or ((not I) = 'H')) then
        OB <= '1';
      elsif (((not I) = '0') or ((not I) = 'L')) then
        OB <= '0';
      elsif ((not I) = 'U') then
        OB <= 'U';
      else
        OB <= 'X';  
      end if;
    elsif (T = 'U') then
      OB <= 'U';          
    else                                      
      OB <= 'X';  
    end if;            
  end process;
end OBUFTDS_LVDSEXT_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuftds_lvdsext_33.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Differential Signaling Output Buffer with LVDSEXT_33 I/O Standard
-- /___/   /\     Filename : OBUFTDS_LVDSEXT_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:43 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFTDS_LVDSEXT_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFTDS_LVDSEXT_33 is
  port(
    O  : out std_ulogic;
    OB : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );
end OBUFTDS_LVDSEXT_33;

architecture OBUFTDS_LVDSEXT_33_V of OBUFTDS_LVDSEXT_33 is
begin
  VITALBehavior    : process (I, T)
  begin

    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;

    if ((T = '1') or (T = 'H')) then
      OB <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if (((not I) = '1') or ((not I) = 'H')) then
        OB <= '1';
      elsif (((not I) = '0') or ((not I) = 'L')) then
        OB <= '0';
      elsif ((not I) = 'U') then
        OB <= 'U';
      else
        OB <= 'X';  
      end if;
    elsif (T = 'U') then
      OB <= 'U';          
    else                                      
      OB <= 'X';  
    end if;            
  end process;
end OBUFTDS_LVDSEXT_33_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuftds_lvpecl_25.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Differential Signaling Output Buffer with LVPECL_25 I/O Standard
-- /___/   /\     Filename : OBUFTDS_LVPECL_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:43 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFTDS_LVPECL_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFTDS_LVPECL_25 is
  port(
    O  : out std_ulogic;
    OB : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );
end OBUFTDS_LVPECL_25;

architecture OBUFTDS_LVPECL_25_V of OBUFTDS_LVPECL_25 is
begin
  VITALBehavior    : process (I, T)
  begin

    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;

    if ((T = '1') or (T = 'H')) then
      OB <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if (((not I) = '1') or ((not I) = 'H')) then
        OB <= '1';
      elsif (((not I) = '0') or ((not I) = 'L')) then
        OB <= '0';
      elsif ((not I) = 'U') then
        OB <= 'U';
      else
        OB <= 'X';  
      end if;
    elsif (T = 'U') then
      OB <= 'U';          
    else                                      
      OB <= 'X';  
    end if;            
  end process;
end OBUFTDS_LVPECL_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuftds_lvpecl_33.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Differential Signaling Output Buffer with LVPECL_33 I/O Standard
-- /___/   /\     Filename : OBUFTDS_LVPECL_33.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:43 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFTDS_LVPECL_33 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFTDS_LVPECL_33 is
  port(
    O  : out std_ulogic;
    OB : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );
end OBUFTDS_LVPECL_33;

architecture OBUFTDS_LVPECL_33_V of OBUFTDS_LVPECL_33 is
begin
  VITALBehavior    : process (I, T)
  begin

    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;

    if ((T = '1') or (T = 'H')) then
      OB <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if (((not I) = '1') or ((not I) = 'H')) then
        OB <= '1';
      elsif (((not I) = '0') or ((not I) = 'L')) then
        OB <= '0';
      elsif ((not I) = 'U') then
        OB <= 'U';
      else
        OB <= 'X';  
      end if;
    elsif (T = 'U') then
      OB <= 'U';          
    else                                      
      OB <= 'X';  
    end if;            
  end process;
end OBUFTDS_LVPECL_33_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuftds_ulvds_25.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Differential Signaling Output Buffer with ULVDS_25 I/O Standard
-- /___/   /\     Filename : OBUFTDS_ULVDS_25.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:43 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFTDS_ULVDS_25 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFTDS_ULVDS_25 is
  port(
    O  : out std_ulogic;
    OB : out std_ulogic;

    I : in std_ulogic;
    T : in std_ulogic
    );
end OBUFTDS_ULVDS_25;

architecture OBUFTDS_ULVDS_25_V of OBUFTDS_ULVDS_25 is
begin
  VITALBehavior    : process (I, T)
  begin

    if ((T = '1') or (T = 'H')) then
      O <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if ((I = '1') or (I = 'H')) then
        O <= '1';
      elsif ((I = '0') or (I = 'L')) then
        O <= '0';
      elsif (I = 'U') then
        O <= 'U';
      else
        O <= 'X';  
      end if;
    elsif (T = 'U') then
      O <= 'U';          
    else                                      
      O <= 'X';  
    end if;

    if ((T = '1') or (T = 'H')) then
      OB <= 'Z';
    elsif ((T = '0') or (T = 'L')) then
      if (((not I) = '1') or ((not I) = 'H')) then
        OB <= '1';
      elsif (((not I) = '0') or ((not I) = 'L')) then
        OB <= '0';
      elsif ((not I) = 'U') then
        OB <= 'U';
      else
        OB <= 'X';  
      end if;
    elsif (T = 'U') then
      OB <= 'U';          
    else                                      
      OB <= 'X';  
    end if;            
  end process;
end OBUFTDS_ULVDS_25_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ofddrcpe.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Dual Data Rate Output D Flip-Flop with Asynchronous Clear and Preset and Clock Enable
-- /___/   /\     Filename : OFDDRCPE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:44 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OFDDRCPE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity OFDDRCPE is
  port(
    Q : out std_ulogic;

    C0  : in std_ulogic;
    C1  : in std_ulogic;
    CE  : in std_ulogic;
    CLR : in std_ulogic;
    D0  : in std_ulogic;
    D1  : in std_ulogic;
    PRE : in std_ulogic
    );
end OFDDRCPE;

architecture OFDDRCPE_V of OFDDRCPE is
   SIGNAL Q_out : STD_ULOGIC := 'X';
   
begin
  F0 : FDDRCPE
    generic map (
      INIT => '0' )
    port map (
      C0   => C0,
      C1   => C1,
      CE   => CE,
      CLR  => CLR,
      D0   => D0,
      D1   => D1,
      PRE  => PRE,
      Q    => Q_out
      );

  O1 : OBUF
    port map (
      I => Q_out,
      O => Q
      );
end OFDDRCPE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ofddrrse.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Dual Data Rate Output D Flip-Flop with Synchronous Reset and Set and Clock Enable
-- /___/   /\     Filename : OFDDRRSE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:44 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OFDDRRSE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity OFDDRRSE is
  port(
    Q : out std_ulogic;

    C0 : in std_ulogic;
    C1 : in std_ulogic;
    CE : in std_ulogic;
    D0 : in std_ulogic;
    D1 : in std_ulogic;
    R  : in std_ulogic;
    S  : in std_ulogic
    );
end OFDDRRSE;

architecture OFDDRRSE_V of OFDDRRSE is

  signal Q_out : std_ulogic := 'X';

begin
  O1 : OBUF
    port map (
      I => Q_out,
      O => Q
      );

  F0 : FDDRRSE
    generic map (INIT => '0'
                 )

    port map (
      C0 => C0,
      C1 => C1,
      CE => CE,
      R  => R,
      D0 => D0,
      D1 => D1,
      S  => S,
      Q  => Q_out
      );
end OFDDRRSE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ofddrtcpe.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Dual Data Rate Output D Flip-Flop with 3-State Output, Asynchronous Clear and Preset and Clock Enable
-- /___/   /\     Filename : OFDDRTCPE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:44 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OFDDRTCPE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity OFDDRTCPE is
  port(
    O : out std_ulogic;

    C0  : in std_ulogic;
    C1  : in std_ulogic;
    CE  : in std_ulogic;
    CLR : in std_ulogic;
    D0  : in std_ulogic;
    D1  : in std_ulogic;
    PRE : in std_ulogic;
    T   : in std_ulogic
    );
end OFDDRTCPE;

architecture OFDDRTCPE_V of OFDDRTCPE is

  signal Q_out : std_ulogic := 'X';

begin
  F0 : FDDRCPE
    generic map (
      INIT => '0' )
    port map (
      C0   => C0,
      C1   => C1,
      CE   => CE,
      CLR  => CLR,
      D0   => D0,
      D1   => D1,
      PRE  => PRE,
      Q    => Q_out
      );

  O1 : OBUFT
    port map (
      I => Q_out,
      T => T,
      O => O
      );
end OFDDRTCPE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ofddrtrse.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Dual Data Rate Output D Flip-Flop with 3-State Output, Synchronous Reset and Set and Clock Enable
-- /___/   /\     Filename : OFDDRTRSE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:44 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OFDDRTRSE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity OFDDRTRSE is
  port(
    O : out std_ulogic;

    C0 : in std_ulogic;
    C1 : in std_ulogic;
    CE : in std_ulogic;
    D0 : in std_ulogic;
    D1 : in std_ulogic;
    R  : in std_ulogic;
    S  : in std_ulogic;
    T  : in std_ulogic
    );
end OFDDRTRSE;

architecture OFDDRTRSE_V of OFDDRTRSE is
  signal Q_out : std_ulogic := 'X';

begin
  F0 : FDDRRSE
    generic map (
      INIT => '0'
      )
    port map (
      C0   => C0,
      C1   => C1,
      CE   => CE,
      R    => R,
      D0   => D0,
      D1   => D1,
      S    => S,
      Q    => Q_out
      );

  O1 : OBUFT
    port map (
      I => Q_out,
      T => T,
      O => O
      );
end OFDDRTRSE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-input OR Gate
-- /___/   /\     Filename : OR2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:44 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR2 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic
    );
end OR2;

architecture OR2_V of OR2 is
begin
  O <= (I0 or I1);
end OR2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or2b1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-input OR Gate
-- /___/   /\     Filename : OR2B1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:44 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR2B1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR2B1 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic
    );
end OR2B1;

architecture OR2B1_V of OR2B1 is
begin
  O <= ((not I0) or I1);
end OR2B1_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or2b2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-input OR Gate
-- /___/   /\     Filename : OR2B2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:45 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR2B2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR2B2 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic
    );
end OR2B2;

architecture OR2B2_V of OR2B2 is
begin
  O <= ((not I0) or (not I1));
end OR2B2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or3.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-input OR Gate
-- /___/   /\     Filename : OR3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:45 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR3 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic
    );
end OR3;

architecture OR3_V of OR3 is
begin
  O <= (I0 or I1 or I2);
end OR3_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or3b1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-input OR Gate
-- /___/   /\     Filename : OR3B1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:45 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR3B1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR3B1 is
  port(
    O  : out std_ulogic;
    I0 : in  std_ulogic;
    I1 : in  std_ulogic;
    I2 : in  std_ulogic
    );
end OR3B1;

architecture OR3B1_V of OR3B1 is
begin
  O <= ((not I0) or I1 or I2);
end OR3B1_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or3b2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-input OR Gate
-- /___/   /\     Filename : OR3B2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:45 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR3B2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR3B2 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic
    );
end OR3B2;

architecture OR3B2_V of OR3B2 is
begin
  O <= ((not I0) or (not I1) or I2);
end OR3B2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or3b3.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input OR Gate
-- /___/   /\     Filename : OR3B3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:45 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR3B3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR3B3 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic
    );
end OR3B3;

architecture OR3B3_V of OR3B3 is
begin
  O <= ((not I0) or (not I1) or (not I2));
end OR3B3_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input OR Gate
-- /___/   /\     Filename : OR4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:45 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR4 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic
    );
end OR4;

architecture OR4_V of OR4 is
begin
  O <= (I0 or I1 or I2 or I3);
end OR4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or4b1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input OR Gate
-- /___/   /\     Filename : OR4B1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:45 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR4B1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR4B1 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic
    );
end OR4B1;

architecture OR4B1_V of OR4B1 is
begin
  O <= ((not I0) or I1 or I2 or I3);
end OR4B1_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or4b2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input OR Gate
-- /___/   /\     Filename : OR4B2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:45 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR4B2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR4B2 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic
    );
end OR4B2;

architecture OR4B2_V of OR4B2 is
begin
  O <= ((not I0) or (not I1) or I2 or I3);
end OR4B2_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or4b3.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input OR Gate
-- /___/   /\     Filename : OR4B3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:45 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR4B3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR4B3 is
  port(
    O : out std_ulogic;

    I0    : in std_ulogic;
    I1    : in std_ulogic;
    I2    : in std_ulogic;
    I3    : in std_ulogic
    );
end OR4B3;

architecture OR4B3_V of OR4B3 is
begin
  O <= ((not I2)) or (I3) or ((not I1)) or ((not I0));
end OR4B3_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or4b4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input OR Gate
-- /___/   /\     Filename : OR4B4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:46 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR4B4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR4B4 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic
    );
end OR4B4;

architecture OR4B4_V of OR4B4 is
begin
  O <= ((not I0) or (not I1) or (not I2) or (not I3));
end OR4B4_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or5.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input OR Gate
-- /___/   /\     Filename : OR5.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:46 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR5 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end OR5;

architecture OR5_V of OR5 is
begin
  O <= (I0 or I1 or I2 or I3 or I4);
end OR5_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or5b1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input OR Gate
-- /___/   /\     Filename : OR5B1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:46 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR5B1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR5B1 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end OR5B1;

architecture OR5B1_V of OR5B1 is
begin
  O <= ((not I0) or I1 or I2 or I3 or I4);
end OR5B1_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or5b2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input OR Gate
-- /___/   /\     Filename : OR5B2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:46 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR5B2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR5B2 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end OR5B2;

architecture OR5B2_V of OR5B2 is
begin
  O <= ((not I0) or (not I1) or I2 or I3 or I4);
end OR5B2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or5b3.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input OR Gate
-- /___/   /\     Filename : OR5B3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:46 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR5B3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR5B3 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end OR5B3;

architecture OR5B3_V of OR5B3 is
begin
  O <= ((not I0) or (not I1) or (not I2) or I3 or I4);
end OR5B3_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or5b4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input OR Gate
-- /___/   /\     Filename : OR5B4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:46 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR5B4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR5B4 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end OR5B4;

architecture OR5B4_V of OR5B4 is
begin
  O <= ((not I0) or (not I1) or (not I2) or (not I3) or I4);
end OR5B4_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or5b5.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input OR Gate
-- /___/   /\     Filename : OR5B5.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:46 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR5B5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR5B5 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end OR5B5;

architecture OR5B5_V of OR5B5 is
begin
  O <= ((not I0) or (not I1) or (not I2) or (not I3) or (not I4));
end OR5B5_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/orcy.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  OR with Carry Logic
-- /___/   /\     Filename : ORCY.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:47 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL ORCY -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity ORCY is
   port(
      O : out std_ulogic;

      CI : in std_ulogic;
      I  : in std_ulogic
      );
end ORCY;

architecture ORCY_V of ORCY is
begin
      O <= (CI or I);
end ORCY_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/pulldown.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Resistor to GND
-- /___/   /\     Filename : PULLDOWN.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:47 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL PULLDOWN -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity PULLDOWN is
  port(
    O : out std_ulogic := 'L'
    );
end PULLDOWN;

architecture PULLDOWN_V of PULLDOWN is
begin
  O <= 'L';
end PULLDOWN_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/pullup.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Resistor to VCC
-- /___/   /\     Filename : PULLUP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:47 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL PULLUP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity PULLUP is
  port(
    O : out std_ulogic := 'H'
    );
end PULLUP;

architecture PULLUP_V of PULLUP is
begin
  O <= 'H';
end PULLUP_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram128x1s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Synchronous RAM 128-Deep by 1-Wide
-- /___/   /\     Filename : RAM128X1S.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:47 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM128X1S -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM128X1S is

  generic (
    INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000"
    );

  port (
    O : out std_ulogic;

    A0   : in std_ulogic;
    A1   : in std_ulogic;
    A2   : in std_ulogic;
    A3   : in std_ulogic;
    A4   : in std_ulogic;
    A5   : in std_ulogic;
    A6   : in std_ulogic;
    D    : in std_ulogic;
    WCLK : in std_ulogic;
    WE   : in std_ulogic
    );
end RAM128X1S;

architecture RAM128X1S_V of RAM128X1S is
  signal MEM : std_logic_vector( 128 downto 0 ) := ('X' & To_StdLogicVector(INIT) );

begin
  VITALReadBehavior  : process(A0, A1, A2, A3, A4, A5, A6, MEM)
    Variable Index   : integer    := 128;
    variable Address : std_logic_vector( 6 downto 0);

  begin
    Address := (A6, A5, A4, A3, A2, A1, A0);
    Index   := SLV_TO_INT(SLV => Address);
    O <= MEM(Index);      

  end process VITALReadBehavior;

  VITALWriteBehavior : process(WCLK)
    Variable Index   : integer := 128;
    variable Address : std_logic_vector (6 downto 0);

  begin
    if (rising_edge(WCLK)) then
      if (WE = '1') then
        Address := (A6, A5, A4, A3, A2, A1, A0);
        Index   := SLV_TO_INT(SLV => Address);
        MEM(Index) <= D after 100 ps;
      end if;
    end if;
  end process VITALWriteBehavior;
end RAM128X1S_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram128x1s_1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Synchronous RAM 128-Deep by 1-Wide
-- /___/   /\     Filename : RAM128X1S_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:47 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM128X1S_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM128X1S_1 is

  generic (
    INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000"
    );

  port (
    O : out std_ulogic;

    A0   : in std_ulogic;
    A1   : in std_ulogic;
    A2   : in std_ulogic;
    A3   : in std_ulogic;
    A4   : in std_ulogic;
    A5   : in std_ulogic;
    A6   : in std_ulogic;
    D    : in std_ulogic;
    WCLK : in std_ulogic;
    WE   : in std_ulogic
    );
end RAM128X1S_1;

architecture RAM128X1S_1_V of RAM128X1S_1 is
  signal MEM : std_logic_vector( 128 downto 0 ) := ('X' & To_StdLogicVector(INIT) );

begin
  VITALReadBehavior  : process(A0, A1, A2, A3, A4, A5, A6, MEM)
    Variable Index   : integer    := 128;
    variable Address : std_logic_vector( 6 downto 0);

  begin
    Address := (A6, A5, A4, A3, A2, A1, A0);
    Index   := SLV_TO_INT(SLV => Address);
    O <= MEM(Index);      
  end process VITALReadBehavior;

  VITALWriteBehavior : process(WCLK)
    Variable Index   : integer := 128;
    variable Address : std_logic_vector (6 downto 0);

  begin
    if (falling_edge(WCLK)) then
      if (WE = '1') then
        Address := (A6, A5, A4, A3, A2, A1, A0);
        Index   := SLV_TO_INT(SLV => Address);
        MEM(Index) <= D after 100 ps;
      end if;
    end if;
  end process VITALWriteBehavior;
end RAM128X1S_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram16x1d.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Dual Port Synchronous RAM 16-Deep by 1-Wide
-- /___/   /\     Filename : RAM16X1D.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:47 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM16X1D -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM16X1D is

  generic (
       INIT : bit_vector(15 downto 0) := X"0000"
  );

  port (
        DPO   : out std_ulogic;        
        SPO   : out std_ulogic;
        
        A0    : in std_ulogic;
        A1    : in std_ulogic;
        A2    : in std_ulogic;
        A3    : in std_ulogic;
        D     : in std_ulogic;        
        DPRA0 : in std_ulogic;
        DPRA1 : in std_ulogic;
        DPRA2 : in std_ulogic;
        DPRA3 : in std_ulogic;        
        WCLK  : in std_ulogic;
        WE    : in std_ulogic
       );
end RAM16X1D;

architecture RAM16X1D_V of RAM16X1D is
  signal MEM       : std_logic_vector( 16 downto 0 ) := ('X' & To_StdLogicVector(INIT) );

begin
 VITALReadBehavior : process(A0, A1, A2, A3, DPRA3, DPRA2, DPRA1, DPRA0, MEM)
       Variable Index_SP   : integer  := 16 ;
       Variable Index_DP   : integer  := 16 ;

  begin 
    Index_SP := DECODE_ADDR4(ADDRESS => (A3, A2, A1, A0));
    Index_DP := DECODE_ADDR4(ADDRESS => (DPRA3, DPRA2, DPRA1, DPRA0));
    SPO <= MEM(Index_SP);
    DPO <= MEM(Index_DP);

  end process VITALReadBehavior;

 VITALWriteBehavior : process(WCLK)
    variable Index_SP  : integer := 16;
    variable Index_DP  : integer := 16;
  begin
    Index_SP := DECODE_ADDR4(ADDRESS => (A3, A2, A1, A0));
    if ((WE = '1') and (wclk'event) and (wclk'last_value = '0') and (wclk = '1')) then
      MEM(Index_SP) <= D after 100 ps;      
    end if;
  end process VITALWriteBehavior;
end RAM16X1D_V;
 

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram16x1d_1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Dual Port Synchronous RAM 16-Deep by 1-Wide
-- /___/   /\     Filename : RAM16X1D_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:47 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM16X1D_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM16X1D_1 is

  generic (
    INIT : bit_vector(15 downto 0) := X"0000"
    );

  port (
    DPO : out std_ulogic;
    SPO : out std_ulogic;

    A0    : in std_ulogic;
    A1    : in std_ulogic;
    A2    : in std_ulogic;
    A3    : in std_ulogic;
    D     : in std_ulogic;
    DPRA0 : in std_ulogic;
    DPRA1 : in std_ulogic;
    DPRA2 : in std_ulogic;
    DPRA3 : in std_ulogic;
    WCLK  : in std_ulogic;
    WE    : in std_ulogic
    );
end RAM16X1D_1;

architecture RAM16X1D_1_V of RAM16X1D_1 is
  signal MEM : std_logic_vector( 16 downto 0 ) := ('X' & To_StdLogicVector(INIT) );

begin
  VITALReadBehavior   : process(A0, A1, A2, A3, DPRA3, DPRA2, DPRA1, DPRA0, MEM)
    variable Index_SP : integer := 16;
    variable Index_DP : integer := 16;

  begin
    Index_SP := DECODE_ADDR4(ADDRESS => (A3, A2, A1, A0));
    Index_DP := DECODE_ADDR4(ADDRESS => (DPRA3, DPRA2, DPRA1, DPRA0));
    SPO <= MEM(Index_SP);
    DPO <= MEM(Index_DP);
  end process VITALReadBehavior;

  VITALWriteBehavior  : process(WCLK)
    variable Index_SP : integer := 16;
    variable Index_DP : integer := 16;
  begin
    Index_SP                    := DECODE_ADDR4(ADDRESS => (A3, A2, A1, A0));
    if ((WE = '1') and (wclk'event) and (wclk'last_value = '1') and (wclk = '0')) then
      MEM(Index_SP) <= D after 100 ps;
    end if;

  end process VITALWriteBehavior;
end RAM16X1D_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram16x1s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Synchronous RAM 16-Deep by 1-Wide
-- /___/   /\     Filename : RAM16X1S.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:47 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM16X1S -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM16X1S is

  generic (
    INIT : bit_vector(15 downto 0) := X"0000"
    );

  port (
    O : out std_ulogic;

    A0   : in std_ulogic;
    A1   : in std_ulogic;
    A2   : in std_ulogic;
    A3   : in std_ulogic;
    D    : in std_ulogic;
    WCLK : in std_ulogic;
    WE   : in std_ulogic
    );
end RAM16X1S;

architecture RAM16X1S_V of RAM16X1S is
  signal MEM : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT));

begin
  VITALReadBehavior  : process(A0, A1, A2, A3, MEM)
    variable Index   : integer := 16;
    variable Address : std_logic_vector(3 downto 0);
  begin
    Address                    := (A3, A2, A1, A0);
    Index                      := SLV_TO_INT(SLV => Address);
    O <= MEM(Index);      
  end process VITALReadBehavior;

  VITALWriteBehavior : process(WCLK)
    variable Index   : integer := 16;
    variable Address : std_logic_vector (3 downto 0);
  begin
    if (rising_edge(WCLK)) then
      if (WE = '1') then
        Address                := (A3, A2, A1, A0);
        Index                  := SLV_TO_INT(SLV => Address);
        MEM(Index) <= D after 100 ps;
      end if;
    end if;
  end process VITALWriteBehavior;
end RAM16X1S_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram16x1s_1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Synchronous RAM 16-Deep by 1 -Wide
-- /___/   /\     Filename : RAM16X1S_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:48 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM16X1S_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM16X1S_1 is

  generic (
    INIT : bit_vector(15 downto 0) := X"0000"
    );

  port (
    O : out std_ulogic;

    A0   : in std_ulogic;
    A1   : in std_ulogic;
    A2   : in std_ulogic;
    A3   : in std_ulogic;
    D    : in std_ulogic;
    WCLK : in std_ulogic;
    WE   : in std_ulogic
    );
end RAM16X1S_1;

architecture RAM16X1S_1_V of RAM16X1S_1 is
  signal MEM : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT));

begin
  VITALReadBehavior  : process(A0, A1, A2, A3, MEM)
    variable Index   : integer := 16;
    variable Address : std_logic_vector(3 downto 0);
  begin
    Address                    := (A3, A2, A1, A0);
    Index                      := SLV_TO_INT(SLV => Address);
    O <= MEM(Index);      
  end process VITALReadBehavior;

  VITALWriteBehavior : process(WCLK)
    variable Index   : integer := 16;
    variable Address : std_logic_vector (3 downto 0);
  begin
    if (falling_edge(WCLK)) then
      if (WE = '1') then
        Address                := (A3, A2, A1, A0);
        Index                  := SLV_TO_INT(SLV => Address);
        MEM(Index) <= D after 100 ps;
      end if;
    end if;
  end process VITALWriteBehavior;
end RAM16X1S_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram16x2s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Synchronous RAM 16-Deep by 2-Wide
-- /___/   /\     Filename : RAM16X2S.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:48 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM16X2S -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM16X2S is

  generic (
    INIT_00 : bit_vector(15 downto 0) := X"0000";
    INIT_01 : bit_vector(15 downto 0) := X"0000"
    );

  port (
    O0 : out std_ulogic;
    O1 : out std_ulogic;

    A0   : in std_ulogic;
    A1   : in std_ulogic;
    A2   : in std_ulogic;
    A3   : in std_ulogic;
    D0   : in std_ulogic;
    D1   : in std_ulogic;
    WCLK : in std_ulogic;
    WE   : in std_ulogic
    );
end RAM16X2S;

architecture RAM16X2S_V of RAM16X2S is
  signal MEM0 : std_logic_vector( 16 downto 0 ) := ('X' & To_StdLogicVector(INIT_00) );
  signal MEM1 : std_logic_vector( 16 downto 0 ) := ('X' & To_StdLogicVector(INIT_01) );

begin
  VITALReadBehavior  : process(A0, A1, A2, A3, MEM0, MEM1)
    variable Index   : integer := 16;
    variable Address : std_logic_vector(3 downto 0);

  begin
    Address := (A3, A2, A1, A0);
    Index   := SLV_TO_INT(SLV => Address);
    O0 <= MEM0(Index);      
    O1 <= MEM1(Index);      
  end process VITALReadBehavior;

  VITALWriteBehavior : process(WCLK)
    variable Index   : integer := 16;
    variable Address : std_logic_vector(3 downto 0);
  begin
    if (rising_edge(WCLK)) then
      if (WE = '1') then
        Address                := (A3, A2, A1, A0);
        Index                  := SLV_TO_INT(SLV => Address);
        MEM0(Index) <= D0 after 100 ps;
        MEM1(Index) <= D1 after 100 ps;
      end if;
    end if;
  end process VITALWriteBehavior;
end RAM16X2S_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram16x4s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Synchronous RAM 16-Deep by 4-Wide
-- /___/   /\     Filename : RAM16X4S.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:48 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM16X4S -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM16X4S is

  generic (
    INIT_00 : bit_vector(15 downto 0) := X"0000";
    INIT_01 : bit_vector(15 downto 0) := X"0000";
    INIT_02 : bit_vector(15 downto 0) := X"0000";
    INIT_03 : bit_vector(15 downto 0) := X"0000"
    );

  port (
    O0 : out std_ulogic;
    O1 : out std_ulogic;
    O2 : out std_ulogic;
    O3 : out std_ulogic;

    A0   : in std_ulogic;
    A1   : in std_ulogic;
    A2   : in std_ulogic;
    A3   : in std_ulogic;
    D0   : in std_ulogic;
    D1   : in std_ulogic;
    D2   : in std_ulogic;
    D3   : in std_ulogic;
    WCLK : in std_ulogic;
    WE   : in std_ulogic
    );
end RAM16X4S;

architecture RAM16X4S_V of RAM16X4S is
  signal MEM0 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_00));
  signal MEM1 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_01));
  signal MEM2 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_02));
  signal MEM3 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_03));

begin
  VITALReadBehavior  : process(A0, A1, A2, A3, MEM0, MEM1, MEM2, MEM3)
    variable Index   : integer := 16;
    variable Address : std_logic_vector(3 downto 0);
  begin
    Address                    := (A3, A2, A1, A0);
    Index                      := SLV_TO_INT(SLV => Address);
    O0 <= MEM0(Index);      
    O1 <= MEM1(Index);      
    O2 <= MEM2(Index);      
    O3 <= MEM3(Index);      
  end process VITALReadBehavior;

  VITALWriteBehavior : process(WCLK)
    variable Index   : integer := 16;
    variable Address : std_logic_vector(3 downto 0);
  begin
    if (rising_edge(WCLK)) then
      if (WE = '1') then
        Address                := (A3, A2, A1, A0);
        Index                  := SLV_TO_INT(SLV => Address);
        MEM0(Index) <= D0 after 100 ps;
        MEM1(Index) <= D1 after 100 ps;
        MEM2(Index) <= D2 after 100 ps;
        MEM3(Index) <= D3 after 100 ps;
      end if;
    end if;
  end process VITALWriteBehavior;
end RAM16X4S_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram16x8s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Synchronous RAM 16-Deep by 8-Wide
-- /___/   /\     Filename : RAM16X8S.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:48 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM16X8S -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM16X8S is
  generic (
    INIT_00 : bit_vector(15 downto 0) := X"0000";
    INIT_01 : bit_vector(15 downto 0) := X"0000";
    INIT_02 : bit_vector(15 downto 0) := X"0000";
    INIT_03 : bit_vector(15 downto 0) := X"0000";
    INIT_04 : bit_vector(15 downto 0) := X"0000";
    INIT_05 : bit_vector(15 downto 0) := X"0000";
    INIT_06 : bit_vector(15 downto 0) := X"0000";
    INIT_07 : bit_vector(15 downto 0) := X"0000"
    );

  port (
    O : out std_logic_vector ( 7 downto 0);

    A0   : in std_ulogic;
    A1   : in std_ulogic;
    A2   : in std_ulogic;
    A3   : in std_ulogic;
    D    : in std_logic_vector ( 7 downto 0);
    WCLK : in std_ulogic;
    WE   : in std_ulogic
    );
end RAM16X8S;

architecture RAM16X8S_V of RAM16X8S is
  signal MEM0 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_00));
  signal MEM1 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_01));
  signal MEM2 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_02));
  signal MEM3 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_03));
  signal MEM4 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_04));
  signal MEM5 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_05));
  signal MEM6 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_06));
  signal MEM7 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_07));

begin
  VITALReadBehavior  : process(A0, A1, A2, A3, MEM0, MEM1, MEM2, MEM3, MEM4, MEM5, MEM6, MEM7)
    variable Index   : integer := 16;
    variable Address : std_logic_vector(3 downto 0);
  begin
    Address                    := (A3, A2, A1, A0);
    Index                      := SLV_TO_INT(SLV => Address);
    O(0) <= MEM0(Index);      
    O(1) <= MEM1(Index);      
    O(2) <= MEM2(Index);      
    O(3) <= MEM3(Index);      
    O(4) <= MEM4(Index);      
    O(5) <= MEM5(Index);      
    O(6) <= MEM6(Index);      
    O(7) <= MEM7(Index);      
  end process VITALReadBehavior;

  VITALWriteBehavior : process(WCLK)
    variable Index   : integer := 16;
    variable Address : std_logic_vector(3 downto 0);
  begin
    if (rising_edge(WCLK)) then
      if (WE = '1') then
        Address                := (A3, A2, A1, A0);
        Index                  := SLV_TO_INT(SLV => Address);
        MEM0(Index) <= D(0) after 100 ps;
        MEM1(Index) <= D(1) after 100 ps;
        MEM2(Index) <= D(2) after 100 ps;
        MEM3(Index) <= D(3) after 100 ps;
        MEM4(Index) <= D(4) after 100 ps;
        MEM5(Index) <= D(5) after 100 ps;
        MEM6(Index) <= D(6) after 100 ps;
        MEM7(Index) <= D(7) after 100 ps;
      end if;
    end if;
  end process VITALWriteBehavior;
end RAM16X8S_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram32x1d.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Dual Port Synchronous RAM 32-Deep by 1-Wide
-- /___/   /\     Filename : RAM32X1D.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:48 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM32X1D -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM32X1D is

  generic (
       INIT : bit_vector(31 downto 0) := X"00000000"
  );

  port (
        DPO   : out std_ulogic;        
        SPO   : out std_ulogic;

        A0    : in std_ulogic;
        A1    : in std_ulogic;
        A2    : in std_ulogic;
        A3    : in std_ulogic;
        A4    : in std_ulogic;
        D     : in std_ulogic;
        DPRA0 : in std_ulogic;
        DPRA1 : in std_ulogic;
        DPRA2 : in std_ulogic;
        DPRA3 : in std_ulogic;
        DPRA4 : in std_ulogic;
        WCLK  : in std_ulogic;        
        WE    : in std_ulogic
       );
end RAM32X1D;
architecture RAM32X1D_V of RAM32X1D is
  signal MEM       : std_logic_vector( 32 downto 0 ) := ('X' & To_StdLogicVector(INIT) );

begin
 VITALReadBehavior : process(A0, A1, A2, A3, A4, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0, MEM)
       Variable Index_SP   : integer  := 32 ;
       Variable Index_DP   : integer  := 32 ;
    variable Raddress : std_logic_vector (4 downto 0);
    variable Waddress : std_logic_vector (4 downto 0);

  begin 
    Waddress := (A4, A3, A2, A1, A0);
    Raddress := (DPRA4, DPRA3, DPRA2, DPRA1, DPRA0);
    Index_SP := SLV_TO_INT(SLV => Waddress);
    Index_DP := SLV_TO_INT(SLV => Raddress);
    SPO <= MEM(Index_SP);
    DPO <= MEM(Index_DP);      

  end process VITALReadBehavior;

 VITALWriteBehavior : process(WCLK)
    variable Index_SP  : integer := 32;
    variable Index_DP  : integer := 32;
    variable Address   : std_logic_vector( 4 downto 0);

  begin 
    Address := (A4, A3, A2, A1, A0);
    Index_SP := SLV_TO_INT(SLV => Address );
    if ((WE = '1') and (wclk'event) and (wclk'last_value = '0') and (wclk = '1')) then
      MEM(Index_SP) <= D after 100 ps;            
    end if;
  end process VITALWriteBehavior;
end RAM32X1D_V;
 

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram32x1d_1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Dual Port Synchronous RAM 32-Deep by 1-Wide
-- /___/   /\     Filename : RAM32X1D_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:48 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM32X1D_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM32X1D_1 is

  generic (
    INIT : bit_vector(31 downto 0) := X"00000000"
    );

  port (
    DPO : out std_ulogic;
    SPO : out std_ulogic;

    A0    : in std_ulogic;
    A1    : in std_ulogic;
    A2    : in std_ulogic;
    A3    : in std_ulogic;
    A4    : in std_ulogic;
    D     : in std_ulogic;
    DPRA0 : in std_ulogic;
    DPRA1 : in std_ulogic;
    DPRA2 : in std_ulogic;
    DPRA3 : in std_ulogic;
    DPRA4 : in std_ulogic;
    WCLK  : in std_ulogic;
    WE    : in std_ulogic
    );
end RAM32X1D_1;

architecture RAM32X1D_1_V of RAM32X1D_1 is
  signal MEM : std_logic_vector( 32 downto 0 ) := ('X' & To_StdLogicVector(INIT) );

begin
  VITALReadBehavior   : process(A0, A1, A2, A3, A4, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0, MEM)
    variable Index_SP : integer := 32;
    variable Index_DP : integer := 32;
    variable Raddress : std_logic_vector (4 downto 0);
    variable Waddress : std_logic_vector (4 downto 0);

  begin
    Raddress := (A4, A3, A2, A1, A0);
    Waddress := (DPRA4, DPRA3, DPRA2, DPRA1, DPRA0);
    Index_SP := SLV_TO_INT(SLV => Raddress);
    Index_DP := SLV_TO_INT(SLV => Waddress);
    SPO <= MEM(Index_SP);
    DPO <= MEM(Index_DP);
  end process VITALReadBehavior;

  VITALWriteBehavior  : process(WCLK)
    variable Index_SP : integer := 32;
    variable Index_DP : integer := 32;
    variable Address  : std_logic_vector( 4 downto 0);

  begin
    Address  := (A4, A3, A2, A1, A0);
    Index_SP := SLV_TO_INT(SLV => Address );
    if ((WE = '1') and (wclk'event) and (wclk'last_value = '1') and (wclk = '0')) then
      MEM(Index_SP) <= D after 100 ps;      
    end if;
  end process VITALWriteBehavior;
end RAM32X1D_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram32x1s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Synchronous RAM 32-Deep by 1-Wide
-- /___/   /\     Filename : RAM32X1S.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:48 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM32X1S -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM32X1S is
  generic (
    INIT : bit_vector(31 downto 0) := X"00000000"
    );

  port (
    O : out std_ulogic;

    A0   : in std_ulogic;
    A1   : in std_ulogic;
    A2   : in std_ulogic;
    A3   : in std_ulogic;
    A4   : in std_ulogic;
    D    : in std_ulogic;
    WCLK : in std_ulogic;
    WE   : in std_ulogic
    );
end RAM32X1S;

architecture RAM32X1S_V of RAM32X1S is
  signal MEM : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT));

begin
  VITALReadBehavior  : process(A0, A1, A2, A3, A4, MEM)
    variable Index   : integer := 32;
    variable Address : std_logic_vector (4 downto 0);

  begin
    Address := (A4, A3, A2, A1, A0);
    Index   := SLV_TO_INT(SLV => Address);
    O <= MEM(Index);      
  end process VITALReadBehavior;

  VITALWriteBehavior : process(WCLK)
    variable Index   : integer := 32;
    variable Address : std_logic_vector (4 downto 0);

  begin
    if (rising_edge(WCLK)) then
      if (WE = '1') then
        Address := (A4, A3, A2, A1, A0);
        Index   := SLV_TO_INT(SLV => Address);
        MEM(Index) <= D after 100 ps;
      end if;
    end if;
  end process VITALWriteBehavior;
end RAM32X1S_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram32x1s_1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Synchronous RAM 32-Deep by 1-Wide
-- /___/   /\     Filename : RAM32X1S_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:48 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM32X1S_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM32X1S_1 is
  generic (
    INIT : bit_vector(31 downto 0) := X"00000000"
    );

  port (
    O : out std_ulogic;

    A0   : in std_ulogic;
    A1   : in std_ulogic;
    A2   : in std_ulogic;
    A3   : in std_ulogic;
    A4   : in std_ulogic;
    D    : in std_ulogic;
    WCLK : in std_ulogic;
    WE   : in std_ulogic
    );
end RAM32X1S_1;

architecture RAM32X1S_1_V of RAM32X1S_1 is
  signal MEM : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT));

begin
  VITALReadBehavior  : process(A0, A1, A2, A3, A4, MEM)
    variable Index   : integer := 32;
    variable Address : std_logic_vector (4 downto 0);

  begin
    Address := (A4, A3, A2, A1, A0);
    Index   := SLV_TO_INT(SLV => Address);
    O <= MEM(Index);      
  end process VITALReadBehavior;

  VITALWriteBehavior : process(WCLK)
    variable Index   : integer := 32;
    variable Address : std_logic_vector (4 downto 0);

  begin
    if (falling_edge(WCLK)) then
      if (WE = '1') then
        Address := (A4, A3, A2, A1, A0);
        Index   := SLV_TO_INT(SLV => Address);
        MEM(Index) <= D after 100 ps;
      end if;
    end if;
  end process VITALWriteBehavior;
end RAM32X1S_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram32x2s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Synchronous RAM 32-Deep by 2-Wide
-- /___/   /\     Filename : RAM32X2S.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:48 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM32X2S -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM32X2S is

  generic (
    INIT_00 : bit_vector(31 downto 0) := X"00000000";
    INIT_01 : bit_vector(31 downto 0) := X"00000000"
    );

  port (
    O0 : out std_ulogic;
    O1 : out std_ulogic;

    A0   : in std_ulogic;
    A1   : in std_ulogic;
    A2   : in std_ulogic;
    A3   : in std_ulogic;
    A4   : in std_ulogic;
    D0   : in std_ulogic;
    D1   : in std_ulogic;
    WCLK : in std_ulogic;
    WE   : in std_ulogic
    );
end RAM32X2S;

architecture RAM32X2S_V of RAM32X2S is
  signal MEM0 : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT_00));
  signal MEM1 : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT_01));

begin
  VITALReadBehavior  : process(A0, A1, A2, A3, A4, MEM0, MEM1)
    variable Index   : integer := 32;
    variable Address : std_logic_vector (4 downto 0);

  begin
    Address := (A4, A3, A2, A1, A0);
    Index   := SLV_TO_INT(SLV => Address);
    O0 <= MEM0(Index);      
    O1 <= MEM1(Index);      
  end process VITALReadBehavior;

  VITALWriteBehavior : process(WCLK)
    variable Index   : integer := 32;
    variable Address : std_logic_vector (4 downto 0);

  begin
    if (rising_edge(WCLK)) then
      if (WE = '1') then
        Address := (A4, A3, A2, A1, A0);
        Index   := SLV_TO_INT(SLV => Address);
        MEM0(Index) <= D0 after 100 ps;
        MEM1(Index) <= D1 after 100 ps;
      end if;
    end if;
  end process VITALWriteBehavior;
end RAM32X2S_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram32x4s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Synchronous RAM 32-Deep by 4-Wide
-- /___/   /\     Filename : RAM32X4S.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:49 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM32X4S -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM32X4S is

  generic (
    INIT_00 : bit_vector(31 downto 0) := X"00000000";
    INIT_01 : bit_vector(31 downto 0) := X"00000000";
    INIT_02 : bit_vector(31 downto 0) := X"00000000";
    INIT_03 : bit_vector(31 downto 0) := X"00000000"
    );

  port (
    O0 : out std_ulogic;
    O1 : out std_ulogic;
    O2 : out std_ulogic;
    O3 : out std_ulogic;

    A0   : in std_ulogic;
    A1   : in std_ulogic;
    A2   : in std_ulogic;
    A3   : in std_ulogic;
    A4   : in std_ulogic;
    D0   : in std_ulogic;
    D1   : in std_ulogic;
    D2   : in std_ulogic;
    D3   : in std_ulogic;
    WCLK : in std_ulogic;
    WE   : in std_ulogic
    );
end RAM32X4S;

architecture RAM32X4S_V of RAM32X4S is
  signal MEM0 : std_logic_vector( 32 downto 0 ) := ('X' & To_StdLogicVector(INIT_00) );
  signal MEM1 : std_logic_vector( 32 downto 0 ) := ('X' & To_StdLogicVector(INIT_01) );
  signal MEM2 : std_logic_vector( 32 downto 0 ) := ('X' & To_StdLogicVector(INIT_02) );
  signal MEM3 : std_logic_vector( 32 downto 0 ) := ('X' & To_StdLogicVector(INIT_03) );

begin
  VITALReadBehavior  : process(A0, A1, A2, A3, A4, MEM0, MEM1, MEM2, MEM3)
    variable Index   : integer := 32;
    variable Address : std_logic_vector (4 downto 0);

  begin
    Address := (A4, A3, A2, A1, A0);
    Index   := SLV_TO_INT(SLV => Address);
    O0 <= MEM0(Index);      
    O1 <= MEM1(Index);      
    O2 <= MEM2(Index);      
    O3 <= MEM3(Index);      
  end process VITALReadBehavior;

  VITALWriteBehavior : process(WCLK)
    variable Index   : integer := 32;
    variable Address : std_logic_vector (4 downto 0);

  begin
    if (rising_edge(WCLK)) then
      if (WE = '1') then
        Address := (A4, A3, A2, A1, A0);
        Index   := SLV_TO_INT(SLV => Address);
        MEM0(Index) <= D0 after 100 ps;
        MEM1(Index) <= D1 after 100 ps;
        MEM2(Index) <= D2 after 100 ps;
        MEM3(Index) <= D3 after 100 ps;
      end if;
    end if;
  end process VITALWriteBehavior;
end RAM32X4S_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram32x8s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Synchronous RAM 32-Deep by 8-Wide
-- /___/   /\     Filename : RAM32X8S.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:49 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM32X8S -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM32X8S is

  generic (
    INIT_00 : bit_vector(31 downto 0) := X"00000000";
    INIT_01 : bit_vector(31 downto 0) := X"00000000";
    INIT_02 : bit_vector(31 downto 0) := X"00000000";
    INIT_03 : bit_vector(31 downto 0) := X"00000000";
    INIT_04 : bit_vector(31 downto 0) := X"00000000";
    INIT_05 : bit_vector(31 downto 0) := X"00000000";
    INIT_06 : bit_vector(31 downto 0) := X"00000000";
    INIT_07 : bit_vector(31 downto 0) := X"00000000"
    );

  port (
    O : out std_logic_vector ( 7 downto 0);

    A0   : in std_ulogic;
    A1   : in std_ulogic;
    A2   : in std_ulogic;
    A3   : in std_ulogic;
    A4   : in std_ulogic;
    D    : in std_logic_vector ( 7 downto 0);
    WCLK : in std_ulogic;
    WE   : in std_ulogic
    );
end RAM32X8S;

architecture RAM32X8S_V of RAM32X8S is
  signal MEM0 : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT_00));
  signal MEM1 : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT_01));
  signal MEM2 : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT_02));
  signal MEM3 : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT_03));
  signal MEM4 : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT_04));
  signal MEM5 : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT_05));
  signal MEM6 : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT_06));
  signal MEM7 : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT_07));

begin
  VITALReadBehavior : process(A0, A1, A2, A3, A4, MEM0, MEM1, MEM2, MEM3, MEM4, MEM5, MEM6, MEM7)

    variable Index   : integer := 32;
    variable Address : std_logic_vector (4 downto 0);

  begin
    Address := (A4, A3, A2, A1, A0);
    Index   := SLV_TO_INT(SLV => Address);

      O(0) <= MEM0(Index);      
      O(1) <= MEM1(Index);      
      O(2) <= MEM2(Index);      
      O(3) <= MEM3(Index);      
      O(4) <= MEM4(Index);      
      O(5) <= MEM5(Index);      
      O(6) <= MEM6(Index);      
      O(7) <= MEM7(Index);      
  end process VITALReadBehavior;

  VITALWriteBehavior : process(WCLK)
    variable Index   : integer := 32;
    variable Address : std_logic_vector (4 downto 0);
  begin
    if (rising_edge(WCLK)) then
      if (WE = '1') then
        Address                := (A4, A3, A2, A1, A0);
        Index                  := SLV_TO_INT(SLV => Address);
        MEM0(Index) <= D(0) after 100 ps;
        MEM1(Index) <= D(1) after 100 ps;
        MEM2(Index) <= D(2) after 100 ps;
        MEM3(Index) <= D(3) after 100 ps;
        MEM4(Index) <= D(4) after 100 ps;
        MEM5(Index) <= D(5) after 100 ps;
        MEM6(Index) <= D(6) after 100 ps;
        MEM7(Index) <= D(7) after 100 ps;
      end if;
    end if;
  end process VITALWriteBehavior;
end RAM32X8S_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram64x1d.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Dual Port Synchronous RAM 64-Deep by 1-Wide
-- /___/   /\     Filename : RAM64X1D.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:49 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM64X1D -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM64X1D is
  generic (
    INIT : bit_vector(63 downto 0) := X"0000000000000000"
    );

  port (
    DPO : out std_ulogic;
    SPO : out std_ulogic;

    A0    : in std_ulogic;
    A1    : in std_ulogic;
    A2    : in std_ulogic;
    A3    : in std_ulogic;
    A4    : in std_ulogic;
    A5    : in std_ulogic;
    D     : in std_ulogic;
    DPRA0 : in std_ulogic;
    DPRA1 : in std_ulogic;
    DPRA2 : in std_ulogic;
    DPRA3 : in std_ulogic;
    DPRA4 : in std_ulogic;
    DPRA5 : in std_ulogic;
    WCLK  : in std_ulogic;
    WE    : in std_ulogic
    );
end RAM64X1D;

architecture RAM64X1D_V of RAM64X1D is
  signal MEM : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT) );

begin
  VITALReadBehavior   : process(A0, A1, A2, A3, A4, A5, DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0, WCLK, MEM)
    variable Index_SP : integer := 64;
    variable Index_DP : integer := 64;
    variable Raddress : std_logic_vector (5 downto 0);
    variable Waddress : std_logic_vector (5 downto 0);

  begin
    Waddress := (A5, A4, A3, A2, A1, A0);
    Raddress := (DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0);
    Index_SP := SLV_TO_INT(SLV => Waddress);
    Index_DP := SLV_TO_INT(SLV => Raddress);
    SPO <= MEM(Index_SP);
    DPO <= MEM(Index_DP);      
  end process VITALReadBehavior;

  VITALWriteBehavior  : process(WCLK)
    variable Index_SP : integer := 32;
    variable Index_DP : integer := 32;
    variable Address  : std_logic_vector( 5 downto 0);

  begin
    Address  := (A5, A4, A3, A2, A1, A0);
    Index_SP := SLV_TO_INT(SLV => Address );
    if ((WE = '1') and (wclk'event) and (wclk'last_value = '0') and (wclk = '1')) then
      MEM(Index_SP) <= D after 100 ps;      
    end if;
  end process VITALWriteBehavior;
end RAM64X1D_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram64x1d_1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Dual Port Synchronous RAM 64-Deep by 1-Wide
-- /___/   /\     Filename : RAM64X1D_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:49 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM64X1D_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM64X1D_1 is
  generic (
    INIT : bit_vector(63 downto 0) := X"0000000000000000"
    );

  port (
    DPO : out std_ulogic;
    SPO : out std_ulogic;

    A0    : in std_ulogic;
    A1    : in std_ulogic;
    A2    : in std_ulogic;
    A3    : in std_ulogic;
    A4    : in std_ulogic;
    A5    : in std_ulogic;
    D     : in std_ulogic;
    DPRA0 : in std_ulogic;
    DPRA1 : in std_ulogic;
    DPRA2 : in std_ulogic;
    DPRA3 : in std_ulogic;
    DPRA4 : in std_ulogic;
    DPRA5 : in std_ulogic;
    WCLK  : in std_ulogic;
    WE    : in std_ulogic
    );
end RAM64X1D_1;

architecture RAM64X1D_1_V of RAM64X1D_1 is
  signal MEM : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT) );

begin
  VITALReadBehavior   : process(A0, A1, A2, A3, A4, A5, DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0, WCLK, MEM)
    variable Index_SP : integer := 64;
    variable Index_DP : integer := 64;
    variable Raddress : std_logic_vector (5 downto 0);
    variable Waddress : std_logic_vector (5 downto 0);

  begin
    Waddress := (A5, A4, A3, A2, A1, A0);
    Raddress := (DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0);
    Index_SP := SLV_TO_INT(SLV => Waddress);
    Index_DP := SLV_TO_INT(SLV => Raddress);
    SPO <= MEM(Index_SP);
    DPO <= MEM(Index_DP);      
  end process VITALReadBehavior;

  VITALWriteBehavior  : process(WCLK)
    variable Index_SP : integer := 32;
    variable Index_DP : integer := 32;
    variable Address  : std_logic_vector( 5 downto 0);

  begin
    Address  := (A5, A4, A3, A2, A1, A0);
    Index_SP := SLV_TO_INT(SLV => Address );
    if ((WE = '1') and (wclk'event) and (wclk'last_value = '1') and (wclk = '0')) then
      MEM(Index_SP) <= D after 100 ps;      
    end if;
  end process VITALWriteBehavior;
end RAM64X1D_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram64x1s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Synchronous RAM 64-Deep by 1-Wide
-- /___/   /\     Filename : RAM64X1S.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:49 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM64X1S -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM64X1S is
  generic (
    INIT : bit_vector(63 downto 0) := X"0000000000000000"
    );

  port (
    O : out std_ulogic;

    A0   : in std_ulogic;
    A1   : in std_ulogic;
    A2   : in std_ulogic;
    A3   : in std_ulogic;
    A4   : in std_ulogic;
    A5   : in std_ulogic;
    D    : in std_ulogic;
    WCLK : in std_ulogic;
    WE   : in std_ulogic
    );
end RAM64X1S;

architecture RAM64X1S_V of RAM64X1S is
  signal MEM : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT) );

begin
  VITALReadBehavior  : process(A0, A1, A2, A3, A4, A5, MEM)
    variable Index   : integer := 64;
    variable Address : std_logic_vector (5 downto 0);

  begin
    Address := (A5, A4, A3, A2, A1, A0);
    Index   := SLV_TO_INT(SLV => Address);
    O <= MEM(Index);      
  end process VITALReadBehavior;

  VITALWriteBehavior : process(WCLK)
    variable Index   : integer := 64;
    variable Address : std_logic_vector (5 downto 0);
  begin
    if (rising_edge(WCLK)) then
      if (WE = '1') then
        Address                := (A5, A4, A3, A2, A1, A0);
        Index                  := SLV_TO_INT(SLV => Address);
        MEM(Index) <= D after 100 ps;
      end if;
    end if;
  end process VITALWriteBehavior;
end RAM64X1S_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram64x1s_1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Synchronous RAM 64-Deep by 1-Wide
-- /___/   /\     Filename : RAM64X1S_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:49 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM64X1S_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM64X1S_1 is
  generic (
    INIT : bit_vector(63 downto 0) := X"0000000000000000"
    );

  port (
    O : out std_ulogic;

    A0   : in std_ulogic;
    A1   : in std_ulogic;
    A2   : in std_ulogic;
    A3   : in std_ulogic;
    A4   : in std_ulogic;
    A5   : in std_ulogic;
    D    : in std_ulogic;
    WCLK : in std_ulogic;
    WE   : in std_ulogic
    );
end RAM64X1S_1;

architecture RAM64X1S_1_V of RAM64X1S_1 is
  signal MEM : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT) );

begin
  VITALReadBehavior  : process(A0, A1, A2, A3, A4, A5, MEM)
    variable Index   : integer := 64;
    variable Address : std_logic_vector (5 downto 0);

  begin
    Address := (A5, A4, A3, A2, A1, A0);
    Index   := SLV_TO_INT(SLV => Address);
    O <= MEM(Index);      
  end process VITALReadBehavior;

  VITALWriteBehavior : process(WCLK)
    variable Index   : integer := 64;
    variable Address : std_logic_vector (5 downto 0);
  begin
    if (falling_edge(WCLK)) then
      if (WE = '1') then
        Address                := (A5, A4, A3, A2, A1, A0);
        Index                  := SLV_TO_INT(SLV => Address);
        MEM(Index) <= D after 100 ps;
      end if;
    end if;
  end process VITALWriteBehavior;
end RAM64X1S_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram64x2s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Synchronous RAM 64-Deep by 2-Wide
-- /___/   /\     Filename : RAM64X2S.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:49 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAM64X2S -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM64X2S is
  generic (
       INIT_00 : bit_vector(63 downto 0) := X"0000000000000000";
       INIT_01 : bit_vector(63 downto 0) := X"0000000000000000"
  );

  port (
        O0   : out std_ulogic;
        O1   : out std_ulogic;
        
        A0   : in std_ulogic;
        A1   : in std_ulogic;
        A2   : in std_ulogic;
        A3   : in std_ulogic;
        A4   : in std_ulogic;
        A5   : in std_ulogic;        
        D0   : in std_ulogic;
	D1   : in std_ulogic;
        WCLK : in std_ulogic;        
        WE   : in std_ulogic
       );
end RAM64X2S;

architecture RAM64X2S_V of RAM64X2S is
  signal MEM0       : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT_00) );
  signal MEM1       : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT_01) );

begin
  VITALReadBehavior : process(A0, A1, A2, A3, A4, A5, MEM0, MEM1)
    variable Index   : integer := 32;
    variable Address : std_logic_vector (5 downto 0);    
  begin
        Address := (A5, A4, A3, A2 , A1 , A0);
        Index      := SLV_TO_INT(SLV => Address);
        O0 <= MEM0(Index);      
        O1 <= MEM1(Index);      
  end process VITALReadBehavior;

  VITALWriteBehavior : process(WCLK)
    variable Index   : integer := 32;
    variable Address : std_logic_vector (5 downto 0);    
  begin
    if (rising_edge(WCLK)) then
      if (WE = '1') then
        Address := (A5, A4, A3, A2, A1, A0);
        Index   := SLV_TO_INT(SLV => Address);
        MEM0(Index) <= D0 after 100 ps;
        MEM1(Index) <= D1 after 100 ps;
      end if;
    end if;    
end process VITALWriteBehavior;
end RAM64X2S_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb16_s1.vhd,v 1.7 2005/10/07 18:35:24 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Single Port Block RAM
-- /___/   /\     Filename : RAMB16_S1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:49 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    09/26/05 - Fixed CR# 216846. INIT and SRVAL attributes length check and adjustment.
-- END Revision

----- CELL RAMB16_S1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S1 is

  generic (
    INIT : bit_vector := X"0";
    SRVAL : bit_vector := X"0";
    WRITE_MODE : string := "WRITE_FIRST";    

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
    );

  port (
    DO : out STD_LOGIC_VECTOR (0 downto 0);

    ADDR : in STD_LOGIC_VECTOR (13 downto 0);
    CLK : in STD_ULOGIC;
    DI : in STD_LOGIC_VECTOR (0 downto 0);
    EN : in STD_ULOGIC;
    SSR : in STD_ULOGIC;
    WE : in STD_ULOGIC
    );
end RAMB16_S1;

architecture RAMB16_S1_V of RAMB16_S1 is
  constant length : integer := 16384;
  constant width : integer := 1;

  type Two_D_array_type is array ((length -  1) downto 0) of std_logic_vector((width - 1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;    
begin

  VITALBehavior : process
    variable address : integer;
    variable valid_addr : boolean := FALSE;
    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F & INIT_3E & INIT_3D & INIT_3C &
                                                                             INIT_3B & INIT_3A & INIT_39 & INIT_38 &
                                                                             INIT_37 & INIT_36 & INIT_35 & INIT_34 &
                                                                             INIT_33 & INIT_32 & INIT_31 & INIT_30 &
                                                                             INIT_2F & INIT_2E & INIT_2D & INIT_2C &
                                                                             INIT_2B & INIT_2A & INIT_29 & INIT_28 &
                                                                             INIT_27 & INIT_26 & INIT_25 & INIT_24 &
                                                                             INIT_23 & INIT_22 & INIT_21 & INIT_20 &
                                                                             INIT_1F & INIT_1E & INIT_1D & INIT_1C &
                                                                             INIT_1B & INIT_1A & INIT_19 & INIT_18 &
                                                                             INIT_17 & INIT_16 & INIT_15 & INIT_14 &
                                                                             INIT_13 & INIT_12 & INIT_11 & INIT_10 &
                                                                             INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                             INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                             INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                             INIT_03 & INIT_02 & INIT_01 & INIT_00);
    variable mem : Two_D_array_type := slv_to_two_D_array(length, width, mem_slv);

    variable wr_mode : integer := 0;    
    variable first_time : boolean := true;    

    variable INIT_reg         : std_logic_vector (0 downto 0) := "0";
    variable SRVAL_reg         : std_logic_vector (0 downto 0) := "0";            
  begin
    if (first_time) then
      if ((WRITE_MODE = "write_first") or (WRITE_MODE = "WRITE_FIRST")) then
        wr_mode := 0;
      elsif ((WRITE_MODE = "read_first") or (WRITE_MODE = "READ_FIRST")) then
        wr_mode := 1;
      elsif ((WRITE_MODE = "no_change") or (WRITE_MODE = "NO_CHANGE")) then
        wr_mode := 2;
      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Error ",
           GenericName          => " WRITE_MODE ",
           EntityName           => "/RAMB16_S1",
           GenericValue         => WRITE_MODE,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => error
           );
      end if;
      if (INIT'length > 1) then
        INIT_reg(0 downto 0) := To_StdLogicVector(INIT)(0 downto 0);
      else
        INIT_reg(INIT'length-1 downto 0) := To_StdLogicVector(INIT);
      end if;      
      DO <= INIT_reg(0 downto 0);
      if (SRVAL'length > 1) then
        SRVAL_reg(0 downto 0) := To_StdLogicVector(SRVAL)(0 downto 0);
      else
        SRVAL_reg(SRVAL'length-1 downto 0) := To_StdLogicVector(SRVAL);
      end if;            
      first_time := false;
    end if;
      
    valid_addr := addr_is_valid(addr);
    
    if (valid_addr) then
      address := slv_to_int(addr);
    end if;
    
    if (rising_edge(CLK)) then
      if (EN = '1') then
        if (SSR = '1') then
          DO <= SRVAL_reg(0 downto 0) after 100 ps;
        else    
          if (WE = '1') then
            if (wr_mode = 0) then
              DO <= DI after 100 ps;
            elsif (wr_mode = 1) then
              DO <= mem(address) after 100 ps;  
            end if;
          else 
            if (valid_addr) then
              DO <= mem(address) after 100 ps;
            end if;
          end if;
        end if;
        if (WE = '1') then
          if (valid_addr) then
            mem(address) := DI;
          end if;
        end if;  
      end if;
    end if;
    wait on CLK;    
  end process VITALBehavior;
end RAMB16_S1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb16_s18.vhd,v 1.10 2007/07/13 20:39:25 wloo Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Single Port Block RAM
-- /___/   /\     Filename : RAMB16_S18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:50 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    09/26/05 - Fixed CR# 216846. INIT and SRVAL attributes length check and adjustment.
--    07/09/07 - Changed generic write_mode to uppercase (CR 441954).
-- End Revision

----- CELL RAMB16_S18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S18 is

  generic (
    INIT : bit_vector := X"00000";
    SRVAL : bit_vector := X"00000";
    WRITE_MODE : string := "WRITE_FIRST";
    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"

    );

  port (
    DO : out std_logic_vector (15 downto 0);
    DOP : out std_logic_vector (1 downto 0);
    ADDR : in std_logic_vector (9 downto 0);
    CLK : in std_ulogic;
    DI : in std_logic_vector (15 downto 0);
    DIP : in std_logic_vector (1 downto 0);
    EN : in std_ulogic;
    SSR : in std_ulogic;
    WE : in std_ulogic
    );
end RAMB16_S18;

architecture RAMB16_S18_V of RAMB16_S18 is
  constant length : integer := 1024;
  constant width : integer := 16;

  constant parity_width : integer := 2;
  
  type Two_D_array_type is array ((length -  1) downto 0) of std_logic_vector((width - 1) downto 0);
  type Two_D_parity_array_type is array ((length -  1) downto 0) of std_logic_vector((parity_width - 1) downto 0);    

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

  function slv_to_two_D_parity_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_parity_array_type is
    variable two_D_parity_array : two_D_parity_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_parity_array(i) := intermediate; 
    end loop;
    return two_D_parity_array;
  end;      
begin

  VITALBehavior : process

    variable address : integer;
    variable valid_addr : boolean := FALSE;
    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F & INIT_3E & INIT_3D & INIT_3C &
                                                                             INIT_3B & INIT_3A & INIT_39 & INIT_38 &
                                                                             INIT_37 & INIT_36 & INIT_35 & INIT_34 &
                                                                             INIT_33 & INIT_32 & INIT_31 & INIT_30 &
                                                                             INIT_2F & INIT_2E & INIT_2D & INIT_2C &
                                                                             INIT_2B & INIT_2A & INIT_29 & INIT_28 &
                                                                             INIT_27 & INIT_26 & INIT_25 & INIT_24 &
                                                                             INIT_23 & INIT_22 & INIT_21 & INIT_20 &
                                                                             INIT_1F & INIT_1E & INIT_1D & INIT_1C &
                                                                             INIT_1B & INIT_1A & INIT_19 & INIT_18 &
                                                                             INIT_17 & INIT_16 & INIT_15 & INIT_14 &
                                                                             INIT_13 & INIT_12 & INIT_11 & INIT_10 &
                                                                             INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                             INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                             INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                             INIT_03 & INIT_02 & INIT_01 & INIT_00);

    variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07 & INITP_06 & INITP_05 & INITP_04 &
                                                                              INITP_03 & INITP_02 & INITP_01 & INITP_00);    
    variable mem : Two_D_array_type := slv_to_two_D_array(length, width, mem_slv);
    variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length, parity_width, memp_slv);    

    variable wr_mode : integer := 0;    
    variable first_time : boolean := true;

    variable INIT_reg         : std_logic_vector (17 downto 0) := "000000000000000000";
    variable SRVAL_reg         : std_logic_vector (17 downto 0) := "000000000000000000";        
    
  begin
    if (first_time) then
      if ((WRITE_MODE = "write_first") or (WRITE_MODE = "WRITE_FIRST")) then
        wr_mode := 0;
      elsif ((WRITE_MODE = "read_first") or (WRITE_MODE = "READ_FIRST")) then
        wr_mode := 1;
      elsif ((WRITE_MODE = "no_change") or (WRITE_MODE = "NO_CHANGE")) then
        wr_mode := 2;
      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Error ",
           GenericName          => " WRITE_MODE ",
           EntityName           => "/RAMB16_S18",
           GenericValue         => WRITE_MODE,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => error
           );
      end if;
      if (INIT'length > 18) then
        INIT_reg(17 downto 0) := To_StdLogicVector(INIT)(17 downto 0);
      else
        INIT_reg(INIT'length-1 downto 0) := To_StdLogicVector(INIT);
      end if;
      
      DO <= INIT_reg(15 downto 0);
      DOP <= INIT_reg(17 downto 16);
      
      if (SRVAL'length > 18) then
        SRVAL_reg(17 downto 0) := To_StdLogicVector(SRVAL)(17 downto 0);
      else
        SRVAL_reg(SRVAL'length-1 downto 0) := To_StdLogicVector(SRVAL);
      end if;            
      first_time := false;
    end if;
      
    valid_addr := addr_is_valid(addr);
    
    if (valid_addr) then
      address := slv_to_int(addr);
    end if;
    
    if (rising_edge(CLK)) then
      if (EN = '1') then
        if (SSR = '1') then
          DO <= SRVAL_reg(15 downto 0) after 100 ps;
          DOP <= SRVAL_reg(17 downto 16) after 100 ps;          
        else    
          if (WE = '1') then
            if (wr_mode = 0) then
              DO <= DI after 100 ps;
              DOP <= DIP after 100 ps;              
            elsif (wr_mode = 1) then
              DO <= mem(address) after 100 ps;
              DOP <= memp(address) after 100 ps;                
            end if;
          else 
            if (valid_addr) then
              DO <= mem(address) after 100 ps;
              DOP <= memp(address) after 100 ps;              
            end if;
          end if;
        end if;
        if (WE = '1') then
          if (valid_addr) then
            mem(address) := DI;
            memp(address) := DIP;            
          end if;
        end if;  
      end if;
    end if;
    wait on CLK;    
  end process VITALBehavior;
end RAMB16_S18_V;


-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S18_S18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s18_s18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S18_S18 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(9 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPA  : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(9 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPB  : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKA_DOPA : VitalDelayArrayType01(1 downto 0)  := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOPB : VitalDelayArrayType01(1 downto 0)  := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_DIPA_CLKA_negedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    tsetup_DIPA_CLKA_posedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    tsetup_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_DIPA_CLKA_negedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    thold_DIPA_CLKA_posedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    thold_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"00000";
    INIT_B : bit_vector := X"00000";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"00000";
    SRVAL_B : bit_vector := X"00000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(15 downto 0);
    DOB  : out std_logic_vector(15 downto 0);
    DOPA : out std_logic_vector(1 downto 0);
    DOPB : out std_logic_vector(1 downto 0);

    ADDRA : in std_logic_vector(9 downto 0);
    ADDRB : in std_logic_vector(9 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(15 downto 0);
    DIB   : in std_logic_vector(15 downto 0);
    DIPA  : in std_logic_vector(1 downto 0);
    DIPB  : in std_logic_vector(1 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S18_S18 : entity is true;
end ramb16_s18_s18;

architecture RAMB16_S18_S18_V of RAMB16_S18_S18 is
  attribute VITAL_LEVEL0 of
    RAMB16_S18_S18_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(9 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(15 downto 0) := (others => 'X');
  signal DIPA_ipd  : std_logic_vector(1 downto 0)  := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(9 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(15 downto 0) := (others => 'X');
  signal DIPB_ipd  : std_logic_vector(1 downto 0)  := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 1024;
  constant length_b : integer := 1024;
  constant width_a : integer := 16;
  constant width_b : integer := 16;  

  constant parity_width_a : integer := 2;
  constant parity_width_b : integer := 2;  
  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);
  type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

  function slv_to_two_D_parity_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_parity_array_type is
    variable two_D_parity_array : two_D_parity_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_parity_array(i) := intermediate; 
    end loop;
    return two_D_parity_array;
  end;        
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 9 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 15 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    DIPA_DELAY  : for i in 1 downto 0 generate
      VitalWireDelay (DIPA_ipd(i), DIPA(i), tipd_DIPA(i));
    end generate DIPA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 9 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 15 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    DIPB_DELAY  : for i in 1 downto 0 generate
      VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i));
    end generate DIPB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA2_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA3_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA4_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA5_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA6_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA7_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA8_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA9_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA10_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA11_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA12_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA13_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA14_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA15_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIPA0_CLKA_posedge  : std_ulogic := '0';
    variable Tviol_DIPA1_CLKA_posedge  : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB8_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB9_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB10_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB11_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB12_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB13_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB14_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB15_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIPB0_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB1_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA2_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA3_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA4_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA5_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA6_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA7_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA8_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA9_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA10_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA11_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA12_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA13_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA14_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA15_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPA0_CLKA_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPA1_CLKA_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB8_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB9_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB10_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB11_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB12_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB13_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB14_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB15_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB0_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB1_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;
    variable DOA_GlitchData2  : VitalGlitchDataType;
    variable DOA_GlitchData3  : VitalGlitchDataType;
    variable DOA_GlitchData4  : VitalGlitchDataType;
    variable DOA_GlitchData5  : VitalGlitchDataType;
    variable DOA_GlitchData6  : VitalGlitchDataType;
    variable DOA_GlitchData7  : VitalGlitchDataType;
    variable DOA_GlitchData8  : VitalGlitchDataType;
    variable DOA_GlitchData9  : VitalGlitchDataType;
    variable DOA_GlitchData10  : VitalGlitchDataType;
    variable DOA_GlitchData11  : VitalGlitchDataType;
    variable DOA_GlitchData12  : VitalGlitchDataType;
    variable DOA_GlitchData13  : VitalGlitchDataType;
    variable DOA_GlitchData14  : VitalGlitchDataType;
    variable DOA_GlitchData15  : VitalGlitchDataType;
    variable DOPA_GlitchData0 : VitalGlitchDataType;
    variable DOPA_GlitchData1 : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;
    variable DOB_GlitchData8  : VitalGlitchDataType;
    variable DOB_GlitchData9  : VitalGlitchDataType;
    variable DOB_GlitchData10  : VitalGlitchDataType;
    variable DOB_GlitchData11  : VitalGlitchDataType;
    variable DOB_GlitchData12  : VitalGlitchDataType;
    variable DOB_GlitchData13  : VitalGlitchDataType;
    variable DOB_GlitchData14  : VitalGlitchDataType;
    variable DOB_GlitchData15  : VitalGlitchDataType;
    variable DOPB_GlitchData0 : VitalGlitchDataType;
    variable DOPB_GlitchData1 : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) &
                                                       To_StdLogicVector(INITP_06) &
                                                       To_StdLogicVector(INITP_05) &
                                                       To_StdLogicVector(INITP_04) &
                                                       To_StdLogicVector(INITP_03) &
                                                       To_StdLogicVector(INITP_02) &
                                                       To_StdLogicVector(INITP_01) &
                                                       To_StdLogicVector(INITP_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);
    variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv);        


    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable DOPA_OV_LSB       : integer := 0;
    variable DOPA_OV_MSB       : integer := 1;
    variable DOPB_OV_LSB       : integer := 0;
    variable DOPB_OV_MSB       : integer := 1;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (17 downto 0)              := "000000000000000000";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (17 downto 0)              := "000000000000000000";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (17 downto 0)              := "000000000000000000";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (17 downto 0)              := "000000000000000000";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(15 downto 0) := INI_A(15 downto 0);
    variable DOB_zd  : std_logic_vector(15 downto 0) := INI_B(15 downto 0);
    variable DOPA_zd : std_logic_vector(1 downto 0)  := INI_A(17 downto 16);
    variable DOPB_zd : std_logic_vector(1 downto 0)  := INI_B(17 downto 16);

    variable ADDRA_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S18_S18",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 18) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(17 downto 0)                      := INI_A_UNBOUND(17 downto 0);

        for I in INI_A_UNBOUND'high downto 18 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  18 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S18_S18",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 18,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 18) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S18_S18",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 18,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 18) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 18) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(17 downto 0)                      := INI_B_UNBOUND(17 downto 0);

        for I in INI_B_UNBOUND'high downto 18 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  18 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S18_S18",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 18,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 18) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S18_S18",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 18,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 18) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 18) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(17 downto 0)                       := SRVA_A_UNBOUND(17 downto 0);

        for I in SRVA_A_UNBOUND'high downto 18 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  18 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S18_S18",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 18,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 18) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S18_S18",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 18,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 18) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 18) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(17 downto 0)                       := SRVA_B_UNBOUND(17 downto 0);

        for I in SRVA_B_UNBOUND'high downto 18 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  18 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S18_S18",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 18,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 18) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S18_S18",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 18,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 18) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(15 downto 0) := INI_A(15 downto 0);
      DOB_zd(15 downto 0) := INI_B(15 downto 0);
      DOPA_zd(1 downto 0) := INI_A(17 downto 16);
      DOPB_zd(1 downto 0) := INI_B(17 downto 16);
      DOA  <= DOA_zd;
      DOPA <= DOPA_zd;
      DOB  <= DOB_zd;
      DOPB <= DOPB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S18_S18",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S18_S18",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPA0_CLKA_posedge,
        TimingData     => Tmkr_DIPA0_CLKA_posedge,
        TestSignal     => DIPA_ipd(0),
        TestSignalName => "DIPA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIPA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIPA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIPA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA1_CLKA_posedge,
        TimingData     => Tmkr_DIA1_CLKA_posedge,
        TestSignal     => DIA_ipd(1),
        TestSignalName => "DIA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(1),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA2_CLKA_posedge,
        TimingData     => Tmkr_DIA2_CLKA_posedge,
        TestSignal     => DIA_ipd(2),
        TestSignalName => "DIA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(2),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA3_CLKA_posedge,
        TimingData     => Tmkr_DIA3_CLKA_posedge,
        TestSignal     => DIA_ipd(3),
        TestSignalName => "DIA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(3),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(3),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA4_CLKA_posedge,
        TimingData     => Tmkr_DIA4_CLKA_posedge,
        TestSignal     => DIA_ipd(4),
        TestSignalName => "DIA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(4),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(4),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA5_CLKA_posedge,
        TimingData     => Tmkr_DIA5_CLKA_posedge,
        TestSignal     => DIA_ipd(5),
        TestSignalName => "DIA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(5),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(5),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA6_CLKA_posedge,
        TimingData     => Tmkr_DIA6_CLKA_posedge,
        TestSignal     => DIA_ipd(6),
        TestSignalName => "DIA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(6),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(6),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA7_CLKA_posedge,
        TimingData     => Tmkr_DIA7_CLKA_posedge,
        TestSignal     => DIA_ipd(7),
        TestSignalName => "DIA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(7),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(7),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA8_CLKA_posedge,
        TimingData     => Tmkr_DIA8_CLKA_posedge,
        TestSignal     => DIA_ipd(8),
        TestSignalName => "DIA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(8),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(8),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA9_CLKA_posedge,
        TimingData     => Tmkr_DIA9_CLKA_posedge,
        TestSignal     => DIA_ipd(9),
        TestSignalName => "DIA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(9),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(9),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA10_CLKA_posedge,
        TimingData     => Tmkr_DIA10_CLKA_posedge,
        TestSignal     => DIA_ipd(10),
        TestSignalName => "DIA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(10),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(10),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA11_CLKA_posedge,
        TimingData     => Tmkr_DIA11_CLKA_posedge,
        TestSignal     => DIA_ipd(11),
        TestSignalName => "DIA(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(11),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(11),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(11),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(11),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA12_CLKA_posedge,
        TimingData     => Tmkr_DIA12_CLKA_posedge,
        TestSignal     => DIA_ipd(12),
        TestSignalName => "DIA(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(12),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(12),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(12),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(12),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA13_CLKA_posedge,
        TimingData     => Tmkr_DIA13_CLKA_posedge,
        TestSignal     => DIA_ipd(13),
        TestSignalName => "DIA(13)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(13),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(13),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(13),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(13),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA14_CLKA_posedge,
        TimingData     => Tmkr_DIA14_CLKA_posedge,
        TestSignal     => DIA_ipd(14),
        TestSignalName => "DIA(14)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(14),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(14),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(14),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(14),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB0_CLKB_posedge,
        TimingData     => Tmkr_DIPB0_CLKB_posedge,
        TestSignal     => DIPB_ipd(0),
        TestSignalName => "DIPB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB7_CLKB_posedge,
        TimingData     => Tmkr_DIB7_CLKB_posedge,
        TestSignal     => DIB_ipd(7),
        TestSignalName => "DIB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(7),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(7),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB8_CLKB_posedge,
        TimingData     => Tmkr_DIB8_CLKB_posedge,
        TestSignal     => DIB_ipd(8),
        TestSignalName => "DIB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(8),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(8),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB9_CLKB_posedge,
        TimingData     => Tmkr_DIB9_CLKB_posedge,
        TestSignal     => DIB_ipd(9),
        TestSignalName => "DIB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(9),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(9),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB10_CLKB_posedge,
        TimingData     => Tmkr_DIB10_CLKB_posedge,
        TestSignal     => DIB_ipd(10),
        TestSignalName => "DIB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(10),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(10),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB11_CLKB_posedge,
        TimingData     => Tmkr_DIB11_CLKB_posedge,
        TestSignal     => DIB_ipd(11),
        TestSignalName => "DIB(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(11),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(11),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(11),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(11),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB12_CLKB_posedge,
        TimingData     => Tmkr_DIB12_CLKB_posedge,
        TestSignal     => DIB_ipd(12),
        TestSignalName => "DIB(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(12),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(12),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(12),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(12),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB13_CLKB_posedge,
        TimingData     => Tmkr_DIB13_CLKB_posedge,
        TestSignal     => DIB_ipd(13),
        TestSignalName => "DIB(13)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(13),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(13),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(13),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(13),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB14_CLKB_posedge,
        TimingData     => Tmkr_DIB14_CLKB_posedge,
        TestSignal     => DIB_ipd(14),
        TestSignalName => "DIB(14)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(14),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(14),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(14),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(14),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_DIA2_CLKA_posedge or
                  Tviol_DIA3_CLKA_posedge or
                  Tviol_DIA4_CLKA_posedge or
                  Tviol_DIA5_CLKA_posedge or
                  Tviol_DIA6_CLKA_posedge or
                  Tviol_DIA7_CLKA_posedge or
                  Tviol_DIA8_CLKA_posedge or
                  Tviol_DIA9_CLKA_posedge or
                  Tviol_DIA10_CLKA_posedge or
                  Tviol_DIA11_CLKA_posedge or
                  Tviol_DIA12_CLKA_posedge or
                  Tviol_DIA13_CLKA_posedge or
                  Tviol_DIA14_CLKA_posedge or
                  Tviol_DIA15_CLKA_posedge or
                  Tviol_DIPA0_CLKA_posedge or
                  Tviol_DIPA1_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_DIB8_CLKB_posedge or
                  Tviol_DIB9_CLKB_posedge or
                  Tviol_DIB10_CLKB_posedge or
                  Tviol_DIB11_CLKB_posedge or
                  Tviol_DIB12_CLKB_posedge or
                  Tviol_DIB13_CLKB_posedge or
                  Tviol_DIB14_CLKB_posedge or
                  Tviol_DIB15_CLKB_posedge or
                  Tviol_DIPB0_CLKB_posedge or
                  Tviol_DIPB1_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
      addr_overlap (address_a, address_b, parity_width_a, parity_width_b, has_overlap_p, olpp_lsb, olpp_msb, dopa_ov_lsb, dopa_ov_msb, dopb_ov_lsb, dopb_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S18",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;
              DOPA_zd := DIPA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S18_S18",
                       InstanceName => ramb16_s18_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');    

                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                      DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S18_S18",
                       InstanceName => ramb16_s18_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;                                      
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                    DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB)                   := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                    MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S18_S18",
                       InstanceName => ramb16_s18_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                      DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S18_S18",
                       InstanceName => ramb16_s18_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                    MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB)                   := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S18_S18",
                       InstanceName => ramb16_s18_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                      DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S18_S18",
                       InstanceName => ramb16_s18_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                    DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB)                   := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                    MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
            DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S18_S18",
                 InstanceName => ramb16_s18_s18'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
              DOPA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(15 downto 0);
          DOPA_zd := SRVA_A(17 downto 16);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
              DOPB_zd := DIPB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S18_S18",
                       InstanceName => ramb16_s18_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                   MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                   DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                     DOPA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S18_S18",
                       InstanceName => ramb16_s18_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                DOPB_zd := MEMP(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S18_S18",
                       InstanceName => ramb16_s18_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                      DOPA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S18_S18",
                       InstanceName => ramb16_s18_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S18_S18",
                     InstanceName => ramb16_s18_s18'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S18_S18",
                       InstanceName => ramb16_s18_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
            DOPB_zd := MEMP(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S18_S18",
                 InstanceName => ramb16_s18_s18'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
              DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(15 downto 0);
          DOPB_zd := SRVA_B(17 downto 16);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
      MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
      MEMP(ADDRESS_B) := DIPB_ipd;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);
    DOA_zd(1)  := ViolationA xor DOA_zd(1);
    DOA_zd(2)  := ViolationA xor DOA_zd(2);
    DOA_zd(3)  := ViolationA xor DOA_zd(3);
    DOA_zd(4)  := ViolationA xor DOA_zd(4);
    DOA_zd(5)  := ViolationA xor DOA_zd(5);
    DOA_zd(6)  := ViolationA xor DOA_zd(6);
    DOA_zd(7)  := ViolationA xor DOA_zd(7);
    DOA_zd(8)  := ViolationA xor DOA_zd(8);
    DOA_zd(9)  := ViolationA xor DOA_zd(9);
    DOA_zd(10)  := ViolationA xor DOA_zd(10);
    DOA_zd(11)  := ViolationA xor DOA_zd(11);
    DOA_zd(12)  := ViolationA xor DOA_zd(12);
    DOA_zd(13)  := ViolationA xor DOA_zd(13);
    DOA_zd(14)  := ViolationA xor DOA_zd(14);
    DOA_zd(15)  := ViolationA xor DOA_zd(15);
    DOPA_zd(0) := ViolationA xor DOPA_zd(0);
    DOPA_zd(1) := ViolationA xor DOPA_zd(1);
    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);
    DOB_zd(8)  := ViolationB xor DOB_zd(8);
    DOB_zd(9)  := ViolationB xor DOB_zd(9);
    DOB_zd(10)  := ViolationB xor DOB_zd(10);
    DOB_zd(11)  := ViolationB xor DOB_zd(11);
    DOB_zd(12)  := ViolationB xor DOB_zd(12);
    DOB_zd(13)  := ViolationB xor DOB_zd(13);
    DOB_zd(14)  := ViolationB xor DOB_zd(14);
    DOB_zd(15)  := ViolationB xor DOB_zd(15);
    DOPB_zd(0) := ViolationB xor DOPB_zd(0);
    DOPB_zd(1) := ViolationB xor DOPB_zd(1);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(2),
      GlitchData    => DOA_GlitchData2,
      OutSignalName => "DOA(2)",
      OutTemp       => DOA_zd(2),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(3),
      GlitchData    => DOA_GlitchData3,
      OutSignalName => "DOA(3)",
      OutTemp       => DOA_zd(3),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(4),
      GlitchData    => DOA_GlitchData4,
      OutSignalName => "DOA(4)",
      OutTemp       => DOA_zd(4),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(5),
      GlitchData    => DOA_GlitchData5,
      OutSignalName => "DOA(5)",
      OutTemp       => DOA_zd(5),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(6),
      GlitchData    => DOA_GlitchData6,
      OutSignalName => "DOA(6)",
      OutTemp       => DOA_zd(6),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(7),
      GlitchData    => DOA_GlitchData7,
      OutSignalName => "DOA(7)",
      OutTemp       => DOA_zd(7),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(8),
      GlitchData    => DOA_GlitchData8,
      OutSignalName => "DOA(8)",
      OutTemp       => DOA_zd(8),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(8), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(9),
      GlitchData    => DOA_GlitchData9,
      OutSignalName => "DOA(9)",
      OutTemp       => DOA_zd(9),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(9), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(10),
      GlitchData    => DOA_GlitchData10,
      OutSignalName => "DOA(10)",
      OutTemp       => DOA_zd(10),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(10), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(11),
      GlitchData    => DOA_GlitchData11,
      OutSignalName => "DOA(11)",
      OutTemp       => DOA_zd(11),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(11), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(12),
      GlitchData    => DOA_GlitchData12,
      OutSignalName => "DOA(12)",
      OutTemp       => DOA_zd(12),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(12), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(13),
      GlitchData    => DOA_GlitchData13,
      OutSignalName => "DOA(13)",
      OutTemp       => DOA_zd(13),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(13), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(14),
      GlitchData    => DOA_GlitchData14,
      OutSignalName => "DOA(14)",
      OutTemp       => DOA_zd(14),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(14), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(15),
      GlitchData    => DOA_GlitchData15,
      OutSignalName => "DOA(15)",
      OutTemp       => DOA_zd(15),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(15), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPA(0),
      GlitchData    => DOPA_GlitchData0,
      OutSignalName => "DOPA(0)",
      OutTemp       => DOPA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPA(1),
      GlitchData    => DOPA_GlitchData1,
      OutSignalName => "DOPA(1)",
      OutTemp       => DOPA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(8),
      GlitchData    => DOB_GlitchData8,
      OutSignalName => "DOB(8)",
      OutTemp       => DOB_zd(8),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(9),
      GlitchData    => DOB_GlitchData9,
      OutSignalName => "DOB(9)",
      OutTemp       => DOB_zd(9),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(10),
      GlitchData    => DOB_GlitchData10,
      OutSignalName => "DOB(10)",
      OutTemp       => DOB_zd(10),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(11),
      GlitchData    => DOB_GlitchData11,
      OutSignalName => "DOB(11)",
      OutTemp       => DOB_zd(11),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(12),
      GlitchData    => DOB_GlitchData12,
      OutSignalName => "DOB(12)",
      OutTemp       => DOB_zd(12),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(13),
      GlitchData    => DOB_GlitchData13,
      OutSignalName => "DOB(13)",
      OutTemp       => DOB_zd(13),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(14),
      GlitchData    => DOB_GlitchData14,
      OutSignalName => "DOB(14)",
      OutTemp       => DOB_zd(14),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(15),
      GlitchData    => DOB_GlitchData15,
      OutSignalName => "DOB(15)",
      OutTemp       => DOB_zd(15),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(0),
      GlitchData    => DOPB_GlitchData0,
      OutSignalName => "DOPB(0)",
      OutTemp       => DOPB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(1),
      GlitchData    => DOPB_GlitchData1,
      OutSignalName => "DOPB(1)",
      OutTemp       => DOPB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPA_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S18_S18_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S18_S36.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s18_s36 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S18_S36 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(9 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPA  : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(8 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPB  : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKA_DOPA : VitalDelayArrayType01(1 downto 0)  := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_DIPA_CLKA_negedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    tsetup_DIPA_CLKA_posedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    tsetup_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    tsetup_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_DIPA_CLKA_negedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    thold_DIPA_CLKA_posedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    thold_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    thold_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"00000";
    INIT_B : bit_vector := X"000000000";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"00000";
    SRVAL_B : bit_vector := X"000000000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(15 downto 0);
    DOB  : out std_logic_vector(31 downto 0);
    DOPA : out std_logic_vector(1 downto 0);
    DOPB : out std_logic_vector(3 downto 0);

    ADDRA : in std_logic_vector(9 downto 0);
    ADDRB : in std_logic_vector(8 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(15 downto 0);
    DIB   : in std_logic_vector(31 downto 0);
    DIPA  : in std_logic_vector(1 downto 0);
    DIPB  : in std_logic_vector(3 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S18_S36 : entity is true;
end ramb16_s18_s36;

architecture RAMB16_S18_S36_V of RAMB16_S18_S36 is
  attribute VITAL_LEVEL0 of
    RAMB16_S18_S36_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(9 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(15 downto 0) := (others => 'X');
  signal DIPA_ipd  : std_logic_vector(1 downto 0)  := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(8 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(31 downto 0) := (others => 'X');
  signal DIPB_ipd  : std_logic_vector(3 downto 0)  := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 1024;
  constant length_b : integer := 512;
  constant width_a : integer := 16;
  constant width_b : integer := 32;  

  constant parity_width_a : integer := 2;
  constant parity_width_b : integer := 4;  
  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);
  type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

  function slv_to_two_D_parity_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_parity_array_type is
    variable two_D_parity_array : two_D_parity_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_parity_array(i) := intermediate; 
    end loop;
    return two_D_parity_array;
  end;        
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 9 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 15 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    DIPA_DELAY  : for i in 1 downto 0 generate
      VitalWireDelay (DIPA_ipd(i), DIPA(i), tipd_DIPA(i));
    end generate DIPA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 8 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 31 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    DIPB_DELAY  : for i in 3 downto 0 generate
      VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i));
    end generate DIPB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA2_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA3_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA4_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA5_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA6_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA7_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA8_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA9_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA10_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA11_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA12_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA13_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA14_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA15_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIPA0_CLKA_posedge  : std_ulogic := '0';
    variable Tviol_DIPA1_CLKA_posedge  : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB8_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB9_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB10_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB11_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB12_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB13_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB14_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB15_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB16_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB17_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB18_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB19_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB20_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB21_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB22_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB23_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB24_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB25_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB26_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB27_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB28_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB29_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB30_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB31_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIPB0_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB1_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB2_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB3_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA2_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA3_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA4_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA5_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA6_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA7_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA8_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA9_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA10_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA11_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA12_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA13_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA14_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA15_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPA0_CLKA_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPA1_CLKA_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB8_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB9_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB10_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB11_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB12_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB13_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB14_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB15_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB16_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB17_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB18_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB19_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB20_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB21_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB22_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB23_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB24_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB25_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB26_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB27_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB28_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB29_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB30_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB31_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB0_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB1_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB2_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB3_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;
    variable DOA_GlitchData2  : VitalGlitchDataType;
    variable DOA_GlitchData3  : VitalGlitchDataType;
    variable DOA_GlitchData4  : VitalGlitchDataType;
    variable DOA_GlitchData5  : VitalGlitchDataType;
    variable DOA_GlitchData6  : VitalGlitchDataType;
    variable DOA_GlitchData7  : VitalGlitchDataType;
    variable DOA_GlitchData8  : VitalGlitchDataType;
    variable DOA_GlitchData9  : VitalGlitchDataType;
    variable DOA_GlitchData10  : VitalGlitchDataType;
    variable DOA_GlitchData11  : VitalGlitchDataType;
    variable DOA_GlitchData12  : VitalGlitchDataType;
    variable DOA_GlitchData13  : VitalGlitchDataType;
    variable DOA_GlitchData14  : VitalGlitchDataType;
    variable DOA_GlitchData15  : VitalGlitchDataType;
    variable DOPA_GlitchData0 : VitalGlitchDataType;
    variable DOPA_GlitchData1 : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;
    variable DOB_GlitchData8  : VitalGlitchDataType;
    variable DOB_GlitchData9  : VitalGlitchDataType;
    variable DOB_GlitchData10  : VitalGlitchDataType;
    variable DOB_GlitchData11  : VitalGlitchDataType;
    variable DOB_GlitchData12  : VitalGlitchDataType;
    variable DOB_GlitchData13  : VitalGlitchDataType;
    variable DOB_GlitchData14  : VitalGlitchDataType;
    variable DOB_GlitchData15  : VitalGlitchDataType;
    variable DOB_GlitchData16  : VitalGlitchDataType;
    variable DOB_GlitchData17  : VitalGlitchDataType;
    variable DOB_GlitchData18  : VitalGlitchDataType;
    variable DOB_GlitchData19  : VitalGlitchDataType;
    variable DOB_GlitchData20  : VitalGlitchDataType;
    variable DOB_GlitchData21  : VitalGlitchDataType;
    variable DOB_GlitchData22  : VitalGlitchDataType;
    variable DOB_GlitchData23  : VitalGlitchDataType;
    variable DOB_GlitchData24  : VitalGlitchDataType;
    variable DOB_GlitchData25  : VitalGlitchDataType;
    variable DOB_GlitchData26  : VitalGlitchDataType;
    variable DOB_GlitchData27  : VitalGlitchDataType;
    variable DOB_GlitchData28  : VitalGlitchDataType;
    variable DOB_GlitchData29  : VitalGlitchDataType;
    variable DOB_GlitchData30  : VitalGlitchDataType;
    variable DOB_GlitchData31  : VitalGlitchDataType;
    variable DOPB_GlitchData0 : VitalGlitchDataType;
    variable DOPB_GlitchData1 : VitalGlitchDataType;
    variable DOPB_GlitchData2 : VitalGlitchDataType;
    variable DOPB_GlitchData3 : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) &
                                                       To_StdLogicVector(INITP_06) &
                                                       To_StdLogicVector(INITP_05) &
                                                       To_StdLogicVector(INITP_04) &
                                                       To_StdLogicVector(INITP_03) &
                                                       To_StdLogicVector(INITP_02) &
                                                       To_StdLogicVector(INITP_01) &
                                                       To_StdLogicVector(INITP_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);
    variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv);        


    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable DOPA_OV_LSB       : integer := 0;
    variable DOPA_OV_MSB       : integer := 1;
    variable DOPB_OV_LSB       : integer := 0;
    variable DOPB_OV_MSB       : integer := 3;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (17 downto 0)              := "000000000000000000";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (35 downto 0)              := "000000000000000000000000000000000000";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (17 downto 0)              := "000000000000000000";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (35 downto 0)              := "000000000000000000000000000000000000";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(15 downto 0) := INI_A(15 downto 0);
    variable DOB_zd  : std_logic_vector(31 downto 0) := INI_B(31 downto 0);
    variable DOPA_zd : std_logic_vector(1 downto 0)  := INI_A(17 downto 16);
    variable DOPB_zd : std_logic_vector(3 downto 0)  := INI_B(35 downto 32);

    variable ADDRA_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S18_S36",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 18) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(17 downto 0)                      := INI_A_UNBOUND(17 downto 0);

        for I in INI_A_UNBOUND'high downto 18 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  18 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S18_S36",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 18,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 18) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S18_S36",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 18,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 18) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 36) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(35 downto 0)                      := INI_B_UNBOUND(35 downto 0);

        for I in INI_B_UNBOUND'high downto 36 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  36 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S18_S36",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 36,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 36) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S18_S36",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 36,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 36) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 18) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(17 downto 0)                       := SRVA_A_UNBOUND(17 downto 0);

        for I in SRVA_A_UNBOUND'high downto 18 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  18 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S18_S36",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 18,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 18) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S18_S36",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 18,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 18) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 36) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(35 downto 0)                       := SRVA_B_UNBOUND(35 downto 0);

        for I in SRVA_B_UNBOUND'high downto 36 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  36 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S18_S36",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 36,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 36) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S18_S36",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 36,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 36) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(15 downto 0) := INI_A(15 downto 0);
      DOB_zd(31 downto 0) := INI_B(31 downto 0);
      DOPA_zd(1 downto 0) := INI_A(17 downto 16);
      DOPB_zd(3 downto 0) := INI_B(35 downto 32);
      DOA  <= DOA_zd;
      DOPA <= DOPA_zd;
      DOB  <= DOB_zd;
      DOPB <= DOPB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S18_S36",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S18_S36",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPA0_CLKA_posedge,
        TimingData     => Tmkr_DIPA0_CLKA_posedge,
        TestSignal     => DIPA_ipd(0),
        TestSignalName => "DIPA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIPA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIPA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIPA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA1_CLKA_posedge,
        TimingData     => Tmkr_DIA1_CLKA_posedge,
        TestSignal     => DIA_ipd(1),
        TestSignalName => "DIA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(1),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA2_CLKA_posedge,
        TimingData     => Tmkr_DIA2_CLKA_posedge,
        TestSignal     => DIA_ipd(2),
        TestSignalName => "DIA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(2),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA3_CLKA_posedge,
        TimingData     => Tmkr_DIA3_CLKA_posedge,
        TestSignal     => DIA_ipd(3),
        TestSignalName => "DIA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(3),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(3),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA4_CLKA_posedge,
        TimingData     => Tmkr_DIA4_CLKA_posedge,
        TestSignal     => DIA_ipd(4),
        TestSignalName => "DIA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(4),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(4),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA5_CLKA_posedge,
        TimingData     => Tmkr_DIA5_CLKA_posedge,
        TestSignal     => DIA_ipd(5),
        TestSignalName => "DIA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(5),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(5),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA6_CLKA_posedge,
        TimingData     => Tmkr_DIA6_CLKA_posedge,
        TestSignal     => DIA_ipd(6),
        TestSignalName => "DIA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(6),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(6),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA7_CLKA_posedge,
        TimingData     => Tmkr_DIA7_CLKA_posedge,
        TestSignal     => DIA_ipd(7),
        TestSignalName => "DIA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(7),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(7),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA8_CLKA_posedge,
        TimingData     => Tmkr_DIA8_CLKA_posedge,
        TestSignal     => DIA_ipd(8),
        TestSignalName => "DIA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(8),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(8),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA9_CLKA_posedge,
        TimingData     => Tmkr_DIA9_CLKA_posedge,
        TestSignal     => DIA_ipd(9),
        TestSignalName => "DIA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(9),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(9),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA10_CLKA_posedge,
        TimingData     => Tmkr_DIA10_CLKA_posedge,
        TestSignal     => DIA_ipd(10),
        TestSignalName => "DIA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(10),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(10),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA11_CLKA_posedge,
        TimingData     => Tmkr_DIA11_CLKA_posedge,
        TestSignal     => DIA_ipd(11),
        TestSignalName => "DIA(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(11),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(11),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(11),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(11),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA12_CLKA_posedge,
        TimingData     => Tmkr_DIA12_CLKA_posedge,
        TestSignal     => DIA_ipd(12),
        TestSignalName => "DIA(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(12),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(12),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(12),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(12),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA13_CLKA_posedge,
        TimingData     => Tmkr_DIA13_CLKA_posedge,
        TestSignal     => DIA_ipd(13),
        TestSignalName => "DIA(13)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(13),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(13),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(13),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(13),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA14_CLKA_posedge,
        TimingData     => Tmkr_DIA14_CLKA_posedge,
        TestSignal     => DIA_ipd(14),
        TestSignalName => "DIA(14)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(14),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(14),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(14),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(14),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB0_CLKB_posedge,
        TimingData     => Tmkr_DIPB0_CLKB_posedge,
        TestSignal     => DIPB_ipd(0),
        TestSignalName => "DIPB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB1_CLKB_posedge,
        TimingData     => Tmkr_DIPB1_CLKB_posedge,
        TestSignal     => DIPB_ipd(1),
        TestSignalName => "DIPB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB2_CLKB_posedge,
        TimingData     => Tmkr_DIPB2_CLKB_posedge,
        TestSignal     => DIPB_ipd(2),
        TestSignalName => "DIPB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB7_CLKB_posedge,
        TimingData     => Tmkr_DIB7_CLKB_posedge,
        TestSignal     => DIB_ipd(7),
        TestSignalName => "DIB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(7),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(7),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB8_CLKB_posedge,
        TimingData     => Tmkr_DIB8_CLKB_posedge,
        TestSignal     => DIB_ipd(8),
        TestSignalName => "DIB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(8),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(8),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB9_CLKB_posedge,
        TimingData     => Tmkr_DIB9_CLKB_posedge,
        TestSignal     => DIB_ipd(9),
        TestSignalName => "DIB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(9),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(9),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB10_CLKB_posedge,
        TimingData     => Tmkr_DIB10_CLKB_posedge,
        TestSignal     => DIB_ipd(10),
        TestSignalName => "DIB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(10),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(10),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB11_CLKB_posedge,
        TimingData     => Tmkr_DIB11_CLKB_posedge,
        TestSignal     => DIB_ipd(11),
        TestSignalName => "DIB(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(11),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(11),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(11),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(11),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB12_CLKB_posedge,
        TimingData     => Tmkr_DIB12_CLKB_posedge,
        TestSignal     => DIB_ipd(12),
        TestSignalName => "DIB(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(12),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(12),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(12),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(12),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB13_CLKB_posedge,
        TimingData     => Tmkr_DIB13_CLKB_posedge,
        TestSignal     => DIB_ipd(13),
        TestSignalName => "DIB(13)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(13),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(13),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(13),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(13),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB14_CLKB_posedge,
        TimingData     => Tmkr_DIB14_CLKB_posedge,
        TestSignal     => DIB_ipd(14),
        TestSignalName => "DIB(14)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(14),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(14),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(14),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(14),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB15_CLKB_posedge,
        TimingData     => Tmkr_DIB15_CLKB_posedge,
        TestSignal     => DIB_ipd(15),
        TestSignalName => "DIB(15)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(15),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(15),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(15),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(15),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB16_CLKB_posedge,
        TimingData     => Tmkr_DIB16_CLKB_posedge,
        TestSignal     => DIB_ipd(16),
        TestSignalName => "DIB(16)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(16),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(16),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(16),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(16),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB17_CLKB_posedge,
        TimingData     => Tmkr_DIB17_CLKB_posedge,
        TestSignal     => DIB_ipd(17),
        TestSignalName => "DIB(17)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(17),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(17),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(17),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(17),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB18_CLKB_posedge,
        TimingData     => Tmkr_DIB18_CLKB_posedge,
        TestSignal     => DIB_ipd(18),
        TestSignalName => "DIB(18)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(18),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(18),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(18),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(18),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB19_CLKB_posedge,
        TimingData     => Tmkr_DIB19_CLKB_posedge,
        TestSignal     => DIB_ipd(19),
        TestSignalName => "DIB(19)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(19),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(19),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(19),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(19),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB20_CLKB_posedge,
        TimingData     => Tmkr_DIB20_CLKB_posedge,
        TestSignal     => DIB_ipd(20),
        TestSignalName => "DIB(20)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(20),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(20),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(20),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(20),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB21_CLKB_posedge,
        TimingData     => Tmkr_DIB21_CLKB_posedge,
        TestSignal     => DIB_ipd(21),
        TestSignalName => "DIB(21)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(21),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(21),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(21),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(21),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB22_CLKB_posedge,
        TimingData     => Tmkr_DIB22_CLKB_posedge,
        TestSignal     => DIB_ipd(22),
        TestSignalName => "DIB(22)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(22),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(22),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(22),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(22),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB23_CLKB_posedge,
        TimingData     => Tmkr_DIB23_CLKB_posedge,
        TestSignal     => DIB_ipd(23),
        TestSignalName => "DIB(23)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(23),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(23),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(23),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(23),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB24_CLKB_posedge,
        TimingData     => Tmkr_DIB24_CLKB_posedge,
        TestSignal     => DIB_ipd(24),
        TestSignalName => "DIB(24)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(24),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(24),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(24),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(24),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB25_CLKB_posedge,
        TimingData     => Tmkr_DIB25_CLKB_posedge,
        TestSignal     => DIB_ipd(25),
        TestSignalName => "DIB(25)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(25),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(25),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(25),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(25),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB26_CLKB_posedge,
        TimingData     => Tmkr_DIB26_CLKB_posedge,
        TestSignal     => DIB_ipd(26),
        TestSignalName => "DIB(26)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(26),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(26),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(26),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(26),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB27_CLKB_posedge,
        TimingData     => Tmkr_DIB27_CLKB_posedge,
        TestSignal     => DIB_ipd(27),
        TestSignalName => "DIB(27)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(27),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(27),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(27),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(27),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB28_CLKB_posedge,
        TimingData     => Tmkr_DIB28_CLKB_posedge,
        TestSignal     => DIB_ipd(28),
        TestSignalName => "DIB(28)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(28),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(28),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(28),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(28),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB29_CLKB_posedge,
        TimingData     => Tmkr_DIB29_CLKB_posedge,
        TestSignal     => DIB_ipd(29),
        TestSignalName => "DIB(29)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(29),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(29),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(29),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(29),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB30_CLKB_posedge,
        TimingData     => Tmkr_DIB30_CLKB_posedge,
        TestSignal     => DIB_ipd(30),
        TestSignalName => "DIB(30)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(30),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(30),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(30),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(30),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_DIA2_CLKA_posedge or
                  Tviol_DIA3_CLKA_posedge or
                  Tviol_DIA4_CLKA_posedge or
                  Tviol_DIA5_CLKA_posedge or
                  Tviol_DIA6_CLKA_posedge or
                  Tviol_DIA7_CLKA_posedge or
                  Tviol_DIA8_CLKA_posedge or
                  Tviol_DIA9_CLKA_posedge or
                  Tviol_DIA10_CLKA_posedge or
                  Tviol_DIA11_CLKA_posedge or
                  Tviol_DIA12_CLKA_posedge or
                  Tviol_DIA13_CLKA_posedge or
                  Tviol_DIA14_CLKA_posedge or
                  Tviol_DIA15_CLKA_posedge or
                  Tviol_DIPA0_CLKA_posedge or
                  Tviol_DIPA1_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_DIB8_CLKB_posedge or
                  Tviol_DIB9_CLKB_posedge or
                  Tviol_DIB10_CLKB_posedge or
                  Tviol_DIB11_CLKB_posedge or
                  Tviol_DIB12_CLKB_posedge or
                  Tviol_DIB13_CLKB_posedge or
                  Tviol_DIB14_CLKB_posedge or
                  Tviol_DIB15_CLKB_posedge or
                  Tviol_DIB16_CLKB_posedge or
                  Tviol_DIB17_CLKB_posedge or
                  Tviol_DIB18_CLKB_posedge or
                  Tviol_DIB19_CLKB_posedge or
                  Tviol_DIB20_CLKB_posedge or
                  Tviol_DIB21_CLKB_posedge or
                  Tviol_DIB22_CLKB_posedge or
                  Tviol_DIB23_CLKB_posedge or
                  Tviol_DIB24_CLKB_posedge or
                  Tviol_DIB25_CLKB_posedge or
                  Tviol_DIB26_CLKB_posedge or
                  Tviol_DIB27_CLKB_posedge or
                  Tviol_DIB28_CLKB_posedge or
                  Tviol_DIB29_CLKB_posedge or
                  Tviol_DIB30_CLKB_posedge or
                  Tviol_DIB31_CLKB_posedge or
                  Tviol_DIPB0_CLKB_posedge or
                  Tviol_DIPB1_CLKB_posedge or
                  Tviol_DIPB2_CLKB_posedge or
                  Tviol_DIPB3_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
      addr_overlap (address_a, address_b, parity_width_a, parity_width_b, has_overlap_p, olpp_lsb, olpp_msb, dopa_ov_lsb, dopa_ov_msb, dopb_ov_lsb, dopb_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S18_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;
              DOPA_zd := DIPA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S18_S36",
                       InstanceName => ramb16_s18_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');    

                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                      DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S18_S36",
                       InstanceName => ramb16_s18_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;                                      
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                    DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB)                   := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                    MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S18_S36",
                       InstanceName => ramb16_s18_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                      DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S18_S36",
                       InstanceName => ramb16_s18_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                    MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB)                   := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S18_S36",
                       InstanceName => ramb16_s18_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                      DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S18_S36",
                       InstanceName => ramb16_s18_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                    DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB)                   := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                    MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
            DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S18_S36",
                 InstanceName => ramb16_s18_s36'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
              DOPA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(15 downto 0);
          DOPA_zd := SRVA_A(17 downto 16);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
              DOPB_zd := DIPB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S18_S36",
                       InstanceName => ramb16_s18_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                   MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                   DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                     DOPA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S18_S36",
                       InstanceName => ramb16_s18_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                DOPB_zd := MEMP(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S18_S36",
                       InstanceName => ramb16_s18_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                      DOPA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S18_S36",
                       InstanceName => ramb16_s18_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S18_S36",
                     InstanceName => ramb16_s18_s36'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S18_S36",
                       InstanceName => ramb16_s18_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
            DOPB_zd := MEMP(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S18_S36",
                 InstanceName => ramb16_s18_s36'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
              DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(31 downto 0);
          DOPB_zd := SRVA_B(35 downto 32);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
      MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
      MEMP(ADDRESS_B) := DIPB_ipd;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);
    DOA_zd(1)  := ViolationA xor DOA_zd(1);
    DOA_zd(2)  := ViolationA xor DOA_zd(2);
    DOA_zd(3)  := ViolationA xor DOA_zd(3);
    DOA_zd(4)  := ViolationA xor DOA_zd(4);
    DOA_zd(5)  := ViolationA xor DOA_zd(5);
    DOA_zd(6)  := ViolationA xor DOA_zd(6);
    DOA_zd(7)  := ViolationA xor DOA_zd(7);
    DOA_zd(8)  := ViolationA xor DOA_zd(8);
    DOA_zd(9)  := ViolationA xor DOA_zd(9);
    DOA_zd(10)  := ViolationA xor DOA_zd(10);
    DOA_zd(11)  := ViolationA xor DOA_zd(11);
    DOA_zd(12)  := ViolationA xor DOA_zd(12);
    DOA_zd(13)  := ViolationA xor DOA_zd(13);
    DOA_zd(14)  := ViolationA xor DOA_zd(14);
    DOA_zd(15)  := ViolationA xor DOA_zd(15);
    DOPA_zd(0) := ViolationA xor DOPA_zd(0);
    DOPA_zd(1) := ViolationA xor DOPA_zd(1);
    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);
    DOB_zd(8)  := ViolationB xor DOB_zd(8);
    DOB_zd(9)  := ViolationB xor DOB_zd(9);
    DOB_zd(10)  := ViolationB xor DOB_zd(10);
    DOB_zd(11)  := ViolationB xor DOB_zd(11);
    DOB_zd(12)  := ViolationB xor DOB_zd(12);
    DOB_zd(13)  := ViolationB xor DOB_zd(13);
    DOB_zd(14)  := ViolationB xor DOB_zd(14);
    DOB_zd(15)  := ViolationB xor DOB_zd(15);
    DOB_zd(16)  := ViolationB xor DOB_zd(16);
    DOB_zd(17)  := ViolationB xor DOB_zd(17);
    DOB_zd(18)  := ViolationB xor DOB_zd(18);
    DOB_zd(19)  := ViolationB xor DOB_zd(19);
    DOB_zd(20)  := ViolationB xor DOB_zd(20);
    DOB_zd(21)  := ViolationB xor DOB_zd(21);
    DOB_zd(22)  := ViolationB xor DOB_zd(22);
    DOB_zd(23)  := ViolationB xor DOB_zd(23);
    DOB_zd(24)  := ViolationB xor DOB_zd(24);
    DOB_zd(25)  := ViolationB xor DOB_zd(25);
    DOB_zd(26)  := ViolationB xor DOB_zd(26);
    DOB_zd(27)  := ViolationB xor DOB_zd(27);
    DOB_zd(28)  := ViolationB xor DOB_zd(28);
    DOB_zd(29)  := ViolationB xor DOB_zd(29);
    DOB_zd(30)  := ViolationB xor DOB_zd(30);
    DOB_zd(31)  := ViolationB xor DOB_zd(31);
    DOPB_zd(0) := ViolationB xor DOPB_zd(0);
    DOPB_zd(1) := ViolationB xor DOPB_zd(1);
    DOPB_zd(2) := ViolationB xor DOPB_zd(2);
    DOPB_zd(3) := ViolationB xor DOPB_zd(3);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(2),
      GlitchData    => DOA_GlitchData2,
      OutSignalName => "DOA(2)",
      OutTemp       => DOA_zd(2),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(3),
      GlitchData    => DOA_GlitchData3,
      OutSignalName => "DOA(3)",
      OutTemp       => DOA_zd(3),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(4),
      GlitchData    => DOA_GlitchData4,
      OutSignalName => "DOA(4)",
      OutTemp       => DOA_zd(4),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(5),
      GlitchData    => DOA_GlitchData5,
      OutSignalName => "DOA(5)",
      OutTemp       => DOA_zd(5),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(6),
      GlitchData    => DOA_GlitchData6,
      OutSignalName => "DOA(6)",
      OutTemp       => DOA_zd(6),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(7),
      GlitchData    => DOA_GlitchData7,
      OutSignalName => "DOA(7)",
      OutTemp       => DOA_zd(7),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(8),
      GlitchData    => DOA_GlitchData8,
      OutSignalName => "DOA(8)",
      OutTemp       => DOA_zd(8),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(8), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(9),
      GlitchData    => DOA_GlitchData9,
      OutSignalName => "DOA(9)",
      OutTemp       => DOA_zd(9),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(9), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(10),
      GlitchData    => DOA_GlitchData10,
      OutSignalName => "DOA(10)",
      OutTemp       => DOA_zd(10),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(10), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(11),
      GlitchData    => DOA_GlitchData11,
      OutSignalName => "DOA(11)",
      OutTemp       => DOA_zd(11),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(11), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(12),
      GlitchData    => DOA_GlitchData12,
      OutSignalName => "DOA(12)",
      OutTemp       => DOA_zd(12),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(12), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(13),
      GlitchData    => DOA_GlitchData13,
      OutSignalName => "DOA(13)",
      OutTemp       => DOA_zd(13),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(13), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(14),
      GlitchData    => DOA_GlitchData14,
      OutSignalName => "DOA(14)",
      OutTemp       => DOA_zd(14),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(14), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(15),
      GlitchData    => DOA_GlitchData15,
      OutSignalName => "DOA(15)",
      OutTemp       => DOA_zd(15),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(15), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPA(0),
      GlitchData    => DOPA_GlitchData0,
      OutSignalName => "DOPA(0)",
      OutTemp       => DOPA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPA(1),
      GlitchData    => DOPA_GlitchData1,
      OutSignalName => "DOPA(1)",
      OutTemp       => DOPA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(8),
      GlitchData    => DOB_GlitchData8,
      OutSignalName => "DOB(8)",
      OutTemp       => DOB_zd(8),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(9),
      GlitchData    => DOB_GlitchData9,
      OutSignalName => "DOB(9)",
      OutTemp       => DOB_zd(9),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(10),
      GlitchData    => DOB_GlitchData10,
      OutSignalName => "DOB(10)",
      OutTemp       => DOB_zd(10),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(11),
      GlitchData    => DOB_GlitchData11,
      OutSignalName => "DOB(11)",
      OutTemp       => DOB_zd(11),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(12),
      GlitchData    => DOB_GlitchData12,
      OutSignalName => "DOB(12)",
      OutTemp       => DOB_zd(12),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(13),
      GlitchData    => DOB_GlitchData13,
      OutSignalName => "DOB(13)",
      OutTemp       => DOB_zd(13),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(14),
      GlitchData    => DOB_GlitchData14,
      OutSignalName => "DOB(14)",
      OutTemp       => DOB_zd(14),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(15),
      GlitchData    => DOB_GlitchData15,
      OutSignalName => "DOB(15)",
      OutTemp       => DOB_zd(15),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(16),
      GlitchData    => DOB_GlitchData16,
      OutSignalName => "DOB(16)",
      OutTemp       => DOB_zd(16),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(16), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(17),
      GlitchData    => DOB_GlitchData17,
      OutSignalName => "DOB(17)",
      OutTemp       => DOB_zd(17),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(17), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(18),
      GlitchData    => DOB_GlitchData18,
      OutSignalName => "DOB(18)",
      OutTemp       => DOB_zd(18),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(18), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(19),
      GlitchData    => DOB_GlitchData19,
      OutSignalName => "DOB(19)",
      OutTemp       => DOB_zd(19),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(19), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(20),
      GlitchData    => DOB_GlitchData20,
      OutSignalName => "DOB(20)",
      OutTemp       => DOB_zd(20),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(20), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(21),
      GlitchData    => DOB_GlitchData21,
      OutSignalName => "DOB(21)",
      OutTemp       => DOB_zd(21),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(21), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(22),
      GlitchData    => DOB_GlitchData22,
      OutSignalName => "DOB(22)",
      OutTemp       => DOB_zd(22),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(22), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(23),
      GlitchData    => DOB_GlitchData23,
      OutSignalName => "DOB(23)",
      OutTemp       => DOB_zd(23),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(23), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(24),
      GlitchData    => DOB_GlitchData24,
      OutSignalName => "DOB(24)",
      OutTemp       => DOB_zd(24),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(24), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(25),
      GlitchData    => DOB_GlitchData25,
      OutSignalName => "DOB(25)",
      OutTemp       => DOB_zd(25),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(25), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(26),
      GlitchData    => DOB_GlitchData26,
      OutSignalName => "DOB(26)",
      OutTemp       => DOB_zd(26),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(26), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(27),
      GlitchData    => DOB_GlitchData27,
      OutSignalName => "DOB(27)",
      OutTemp       => DOB_zd(27),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(27), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(28),
      GlitchData    => DOB_GlitchData28,
      OutSignalName => "DOB(28)",
      OutTemp       => DOB_zd(28),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(28), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(29),
      GlitchData    => DOB_GlitchData29,
      OutSignalName => "DOB(29)",
      OutTemp       => DOB_zd(29),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(29), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(30),
      GlitchData    => DOB_GlitchData30,
      OutSignalName => "DOB(30)",
      OutTemp       => DOB_zd(30),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(30), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(31),
      GlitchData    => DOB_GlitchData31,
      OutSignalName => "DOB(31)",
      OutTemp       => DOB_zd(31),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(31), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(0),
      GlitchData    => DOPB_GlitchData0,
      OutSignalName => "DOPB(0)",
      OutTemp       => DOPB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(1),
      GlitchData    => DOPB_GlitchData1,
      OutSignalName => "DOPB(1)",
      OutTemp       => DOPB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(2),
      GlitchData    => DOPB_GlitchData2,
      OutSignalName => "DOPB(2)",
      OutTemp       => DOPB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(3),
      GlitchData    => DOPB_GlitchData3,
      OutSignalName => "DOPB(3)",
      OutTemp       => DOPB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPA_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S18_S36_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S1_S1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s1_s1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S1_S1 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(13 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(13 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";


    INIT_A : bit_vector := X"0";
    INIT_B : bit_vector := X"0";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"0";
    SRVAL_B : bit_vector := X"0";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(0 downto 0);
    DOB  : out std_logic_vector(0 downto 0);

    ADDRA : in std_logic_vector(13 downto 0);
    ADDRB : in std_logic_vector(13 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(0 downto 0);
    DIB   : in std_logic_vector(0 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S1_S1 : entity is true;
end ramb16_s1_s1;

architecture RAMB16_S1_S1_V of RAMB16_S1_S1 is
  attribute VITAL_LEVEL0 of
    RAMB16_S1_S1_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(13 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(0 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(13 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(0 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 16384;
  constant length_b : integer := 16384;
  constant width_a : integer := 1;
  constant width_b : integer := 1;  

  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 13 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 0 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 13 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 0 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA13_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB11_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB12_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB13_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA13_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB13_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);

    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (0 downto 0)              := "0";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (0 downto 0)              := "0";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (0 downto 0)              := "0";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (0 downto 0)              := "0";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(0 downto 0) := INI_A(0 downto 0);
    variable DOB_zd  : std_logic_vector(0 downto 0) := INI_B(0 downto 0);

    variable ADDRA_ipd_sampled : std_logic_vector(13 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(13 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S1_S1",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 1) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(0 downto 0)                      := INI_A_UNBOUND(0 downto 0);

        for I in INI_A_UNBOUND'high downto 1 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  1 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S1_S1",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 1,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 1) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S1_S1",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 1,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 1) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 1) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(0 downto 0)                      := INI_B_UNBOUND(0 downto 0);

        for I in INI_B_UNBOUND'high downto 1 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  1 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S1_S1",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 1,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 1) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S1_S1",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 1,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 1) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 1) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(0 downto 0)                       := SRVA_A_UNBOUND(0 downto 0);

        for I in SRVA_A_UNBOUND'high downto 1 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  1 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S1_S1",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 1,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 1) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S1_S1",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 1,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 1) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 1) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(0 downto 0)                       := SRVA_B_UNBOUND(0 downto 0);

        for I in SRVA_B_UNBOUND'high downto 1 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  1 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S1_S1",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 1,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 1) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S1_S1",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 1,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 1) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(0 downto 0) := INI_A(0 downto 0);
      DOB_zd(0 downto 0) := INI_B(0 downto 0);
      DOA  <= DOA_zd;
      DOB  <= DOB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S1_S1",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S1_S1",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA10_CLKA_posedge,
        TimingData     => Tmkr_ADDRA10_CLKA_posedge,
        TestSignal     => ADDRA_ipd(10),
        TestSignalName => "ADDRA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(10),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(10),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA11_CLKA_posedge,
        TimingData     => Tmkr_ADDRA11_CLKA_posedge,
        TestSignal     => ADDRA_ipd(11),
        TestSignalName => "ADDRA(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(11),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(11),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(11),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(11),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA12_CLKA_posedge,
        TimingData     => Tmkr_ADDRA12_CLKA_posedge,
        TestSignal     => ADDRA_ipd(12),
        TestSignalName => "ADDRA(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(12),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(12),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(12),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(12),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB9_CLKB_posedge,
        TimingData     => Tmkr_ADDRB9_CLKB_posedge,
        TestSignal     => ADDRB_ipd(9),
        TestSignalName => "ADDRB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(9),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(9),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB10_CLKB_posedge,
        TimingData     => Tmkr_ADDRB10_CLKB_posedge,
        TestSignal     => ADDRB_ipd(10),
        TestSignalName => "ADDRB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(10),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(10),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB11_CLKB_posedge,
        TimingData     => Tmkr_ADDRB11_CLKB_posedge,
        TestSignal     => ADDRB_ipd(11),
        TestSignalName => "ADDRB(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(11),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(11),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(11),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(11),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB12_CLKB_posedge,
        TimingData     => Tmkr_ADDRB12_CLKB_posedge,
        TestSignal     => ADDRB_ipd(12),
        TestSignalName => "ADDRB(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(12),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(12),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(12),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(12),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_ADDRA11_CLKA_posedge or
                  Tviol_ADDRA12_CLKA_posedge or
                  Tviol_ADDRA13_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_ADDRB10_CLKB_posedge or
                  Tviol_ADDRB11_CLKB_posedge or
                  Tviol_ADDRB12_CLKB_posedge or
                  Tviol_ADDRB13_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S1",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S1",
                       InstanceName => ramb16_s1_s1'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S1_S1",
                       InstanceName => ramb16_s1_s1'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S1",
                       InstanceName => ramb16_s1_s1'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S1_S1",
                       InstanceName => ramb16_s1_s1'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S1",
                       InstanceName => ramb16_s1_s1'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S1_S1",
                       InstanceName => ramb16_s1_s1'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S1_S1",
                 InstanceName => ramb16_s1_s1'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(0 downto 0);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S1",
                       InstanceName => ramb16_s1_s1'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S1_S1",
                       InstanceName => ramb16_s1_s1'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S1",
                       InstanceName => ramb16_s1_s1'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S1_S1",
                       InstanceName => ramb16_s1_s1'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S1_S1",
                     InstanceName => ramb16_s1_s1'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S1_S1",
                       InstanceName => ramb16_s1_s1'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S1_S1",
                 InstanceName => ramb16_s1_s1'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(0 downto 0);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
    end if;

    DOB_zd(0)  := ViolationB xor DOB_zd(0);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S1_S1_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S1_S18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s1_s18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S1_S18 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(13 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(9 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPB  : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOPB : VitalDelayArrayType01(1 downto 0)  := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    tsetup_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    thold_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"0";
    INIT_B : bit_vector := X"00000";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"0";
    SRVAL_B : bit_vector := X"00000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(0 downto 0);
    DOB  : out std_logic_vector(15 downto 0);
    DOPB : out std_logic_vector(1 downto 0);

    ADDRA : in std_logic_vector(13 downto 0);
    ADDRB : in std_logic_vector(9 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(0 downto 0);
    DIB   : in std_logic_vector(15 downto 0);
    DIPB  : in std_logic_vector(1 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S1_S18 : entity is true;
end ramb16_s1_s18;

architecture RAMB16_S1_S18_V of RAMB16_S1_S18 is
  attribute VITAL_LEVEL0 of
    RAMB16_S1_S18_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(13 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(0 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(9 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(15 downto 0) := (others => 'X');
  signal DIPB_ipd  : std_logic_vector(1 downto 0)  := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 16384;
  constant length_b : integer := 1024;
  constant width_a : integer := 1;
  constant width_b : integer := 16;  

  constant parity_width_b : integer := 2;  
  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);
  type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

  function slv_to_two_D_parity_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_parity_array_type is
    variable two_D_parity_array : two_D_parity_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_parity_array(i) := intermediate; 
    end loop;
    return two_D_parity_array;
  end;        
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 13 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 0 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 9 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 15 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    DIPB_DELAY  : for i in 1 downto 0 generate
      VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i));
    end generate DIPB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA13_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB8_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB9_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB10_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB11_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB12_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB13_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB14_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB15_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIPB0_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB1_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA13_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB8_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB9_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB10_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB11_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB12_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB13_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB14_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB15_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB0_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB1_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;
    variable DOB_GlitchData8  : VitalGlitchDataType;
    variable DOB_GlitchData9  : VitalGlitchDataType;
    variable DOB_GlitchData10  : VitalGlitchDataType;
    variable DOB_GlitchData11  : VitalGlitchDataType;
    variable DOB_GlitchData12  : VitalGlitchDataType;
    variable DOB_GlitchData13  : VitalGlitchDataType;
    variable DOB_GlitchData14  : VitalGlitchDataType;
    variable DOB_GlitchData15  : VitalGlitchDataType;
    variable DOPB_GlitchData0 : VitalGlitchDataType;
    variable DOPB_GlitchData1 : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) &
                                                       To_StdLogicVector(INITP_06) &
                                                       To_StdLogicVector(INITP_05) &
                                                       To_StdLogicVector(INITP_04) &
                                                       To_StdLogicVector(INITP_03) &
                                                       To_StdLogicVector(INITP_02) &
                                                       To_StdLogicVector(INITP_01) &
                                                       To_StdLogicVector(INITP_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);
    variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv);        


    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable DOPB_OV_LSB       : integer := 0;
    variable DOPB_OV_MSB       : integer := 1;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (0 downto 0)              := "0";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (17 downto 0)              := "000000000000000000";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (0 downto 0)              := "0";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (17 downto 0)              := "000000000000000000";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(0 downto 0) := INI_A(0 downto 0);
    variable DOB_zd  : std_logic_vector(15 downto 0) := INI_B(15 downto 0);
    variable DOPB_zd : std_logic_vector(1 downto 0)  := INI_B(17 downto 16);

    variable ADDRA_ipd_sampled : std_logic_vector(13 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S1_S18",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 1) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(0 downto 0)                      := INI_A_UNBOUND(0 downto 0);

        for I in INI_A_UNBOUND'high downto 1 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  1 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S1_S18",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 1,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 1) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S1_S18",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 1,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 1) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 18) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(17 downto 0)                      := INI_B_UNBOUND(17 downto 0);

        for I in INI_B_UNBOUND'high downto 18 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  18 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S1_S18",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 18,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 18) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S1_S18",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 18,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 18) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 1) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(0 downto 0)                       := SRVA_A_UNBOUND(0 downto 0);

        for I in SRVA_A_UNBOUND'high downto 1 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  1 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S1_S18",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 1,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 1) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S1_S18",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 1,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 1) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 18) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(17 downto 0)                       := SRVA_B_UNBOUND(17 downto 0);

        for I in SRVA_B_UNBOUND'high downto 18 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  18 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S1_S18",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 18,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 18) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S1_S18",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 18,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 18) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(0 downto 0) := INI_A(0 downto 0);
      DOB_zd(15 downto 0) := INI_B(15 downto 0);
      DOPB_zd(1 downto 0) := INI_B(17 downto 16);
      DOA  <= DOA_zd;
      DOB  <= DOB_zd;
      DOPB <= DOPB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S1_S18",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S1_S18",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA10_CLKA_posedge,
        TimingData     => Tmkr_ADDRA10_CLKA_posedge,
        TestSignal     => ADDRA_ipd(10),
        TestSignalName => "ADDRA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(10),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(10),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA11_CLKA_posedge,
        TimingData     => Tmkr_ADDRA11_CLKA_posedge,
        TestSignal     => ADDRA_ipd(11),
        TestSignalName => "ADDRA(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(11),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(11),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(11),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(11),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA12_CLKA_posedge,
        TimingData     => Tmkr_ADDRA12_CLKA_posedge,
        TestSignal     => ADDRA_ipd(12),
        TestSignalName => "ADDRA(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(12),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(12),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(12),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(12),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB0_CLKB_posedge,
        TimingData     => Tmkr_DIPB0_CLKB_posedge,
        TestSignal     => DIPB_ipd(0),
        TestSignalName => "DIPB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB7_CLKB_posedge,
        TimingData     => Tmkr_DIB7_CLKB_posedge,
        TestSignal     => DIB_ipd(7),
        TestSignalName => "DIB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(7),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(7),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB8_CLKB_posedge,
        TimingData     => Tmkr_DIB8_CLKB_posedge,
        TestSignal     => DIB_ipd(8),
        TestSignalName => "DIB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(8),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(8),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB9_CLKB_posedge,
        TimingData     => Tmkr_DIB9_CLKB_posedge,
        TestSignal     => DIB_ipd(9),
        TestSignalName => "DIB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(9),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(9),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB10_CLKB_posedge,
        TimingData     => Tmkr_DIB10_CLKB_posedge,
        TestSignal     => DIB_ipd(10),
        TestSignalName => "DIB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(10),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(10),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB11_CLKB_posedge,
        TimingData     => Tmkr_DIB11_CLKB_posedge,
        TestSignal     => DIB_ipd(11),
        TestSignalName => "DIB(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(11),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(11),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(11),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(11),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB12_CLKB_posedge,
        TimingData     => Tmkr_DIB12_CLKB_posedge,
        TestSignal     => DIB_ipd(12),
        TestSignalName => "DIB(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(12),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(12),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(12),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(12),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB13_CLKB_posedge,
        TimingData     => Tmkr_DIB13_CLKB_posedge,
        TestSignal     => DIB_ipd(13),
        TestSignalName => "DIB(13)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(13),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(13),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(13),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(13),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB14_CLKB_posedge,
        TimingData     => Tmkr_DIB14_CLKB_posedge,
        TestSignal     => DIB_ipd(14),
        TestSignalName => "DIB(14)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(14),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(14),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(14),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(14),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_ADDRA11_CLKA_posedge or
                  Tviol_ADDRA12_CLKA_posedge or
                  Tviol_ADDRA13_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_DIB8_CLKB_posedge or
                  Tviol_DIB9_CLKB_posedge or
                  Tviol_DIB10_CLKB_posedge or
                  Tviol_DIB11_CLKB_posedge or
                  Tviol_DIB12_CLKB_posedge or
                  Tviol_DIB13_CLKB_posedge or
                  Tviol_DIB14_CLKB_posedge or
                  Tviol_DIB15_CLKB_posedge or
                  Tviol_DIPB0_CLKB_posedge or
                  Tviol_DIPB1_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S18",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S18",
                       InstanceName => ramb16_s1_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S1_S18",
                       InstanceName => ramb16_s1_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S18",
                       InstanceName => ramb16_s1_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S1_S18",
                       InstanceName => ramb16_s1_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S18",
                       InstanceName => ramb16_s1_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S1_S18",
                       InstanceName => ramb16_s1_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S1_S18",
                 InstanceName => ramb16_s1_s18'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(0 downto 0);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
              DOPB_zd := DIPB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S18",
                       InstanceName => ramb16_s1_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S1_S18",
                       InstanceName => ramb16_s1_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                DOPB_zd := MEMP(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S18",
                       InstanceName => ramb16_s1_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S1_S18",
                       InstanceName => ramb16_s1_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S1_S18",
                     InstanceName => ramb16_s1_s18'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S1_S18",
                       InstanceName => ramb16_s1_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
            DOPB_zd := MEMP(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S1_S18",
                 InstanceName => ramb16_s1_s18'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(15 downto 0);
          DOPB_zd := SRVA_B(17 downto 16);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
      MEMP(ADDRESS_B) := DIPB_ipd;
    end if;

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);
    DOB_zd(8)  := ViolationB xor DOB_zd(8);
    DOB_zd(9)  := ViolationB xor DOB_zd(9);
    DOB_zd(10)  := ViolationB xor DOB_zd(10);
    DOB_zd(11)  := ViolationB xor DOB_zd(11);
    DOB_zd(12)  := ViolationB xor DOB_zd(12);
    DOB_zd(13)  := ViolationB xor DOB_zd(13);
    DOB_zd(14)  := ViolationB xor DOB_zd(14);
    DOB_zd(15)  := ViolationB xor DOB_zd(15);
    DOPB_zd(0) := ViolationB xor DOPB_zd(0);
    DOPB_zd(1) := ViolationB xor DOPB_zd(1);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(8),
      GlitchData    => DOB_GlitchData8,
      OutSignalName => "DOB(8)",
      OutTemp       => DOB_zd(8),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(9),
      GlitchData    => DOB_GlitchData9,
      OutSignalName => "DOB(9)",
      OutTemp       => DOB_zd(9),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(10),
      GlitchData    => DOB_GlitchData10,
      OutSignalName => "DOB(10)",
      OutTemp       => DOB_zd(10),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(11),
      GlitchData    => DOB_GlitchData11,
      OutSignalName => "DOB(11)",
      OutTemp       => DOB_zd(11),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(12),
      GlitchData    => DOB_GlitchData12,
      OutSignalName => "DOB(12)",
      OutTemp       => DOB_zd(12),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(13),
      GlitchData    => DOB_GlitchData13,
      OutSignalName => "DOB(13)",
      OutTemp       => DOB_zd(13),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(14),
      GlitchData    => DOB_GlitchData14,
      OutSignalName => "DOB(14)",
      OutTemp       => DOB_zd(14),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(15),
      GlitchData    => DOB_GlitchData15,
      OutSignalName => "DOB(15)",
      OutTemp       => DOB_zd(15),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(0),
      GlitchData    => DOPB_GlitchData0,
      OutSignalName => "DOPB(0)",
      OutTemp       => DOPB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(1),
      GlitchData    => DOPB_GlitchData1,
      OutSignalName => "DOPB(1)",
      OutTemp       => DOPB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S1_S18_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S1_S2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s1_s2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S1_S2 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(13 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(12 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";


    INIT_A : bit_vector := X"0";
    INIT_B : bit_vector := X"0";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"0";
    SRVAL_B : bit_vector := X"0";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(0 downto 0);
    DOB  : out std_logic_vector(1 downto 0);

    ADDRA : in std_logic_vector(13 downto 0);
    ADDRB : in std_logic_vector(12 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(0 downto 0);
    DIB   : in std_logic_vector(1 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S1_S2 : entity is true;
end ramb16_s1_s2;

architecture RAMB16_S1_S2_V of RAMB16_S1_S2 is
  attribute VITAL_LEVEL0 of
    RAMB16_S1_S2_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(13 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(0 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(12 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(1 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 16384;
  constant length_b : integer := 8192;
  constant width_a : integer := 1;
  constant width_b : integer := 2;  

  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 13 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 0 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 12 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 1 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA13_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB11_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB12_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA13_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);

    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (0 downto 0)              := "0";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (1 downto 0)              := "00";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (0 downto 0)              := "0";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (1 downto 0)              := "00";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(0 downto 0) := INI_A(0 downto 0);
    variable DOB_zd  : std_logic_vector(1 downto 0) := INI_B(1 downto 0);

    variable ADDRA_ipd_sampled : std_logic_vector(13 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(12 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S1_S2",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 1) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(0 downto 0)                      := INI_A_UNBOUND(0 downto 0);

        for I in INI_A_UNBOUND'high downto 1 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  1 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S1_S2",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 1,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 1) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S1_S2",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 1,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 1) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 2) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(1 downto 0)                      := INI_B_UNBOUND(1 downto 0);

        for I in INI_B_UNBOUND'high downto 2 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  2 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S1_S2",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 2,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 2) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S1_S2",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 2,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 2) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 1) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(0 downto 0)                       := SRVA_A_UNBOUND(0 downto 0);

        for I in SRVA_A_UNBOUND'high downto 1 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  1 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S1_S2",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 1,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 1) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S1_S2",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 1,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 1) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 2) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(1 downto 0)                       := SRVA_B_UNBOUND(1 downto 0);

        for I in SRVA_B_UNBOUND'high downto 2 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  2 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S1_S2",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 2,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 2) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S1_S2",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 2,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 2) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(0 downto 0) := INI_A(0 downto 0);
      DOB_zd(1 downto 0) := INI_B(1 downto 0);
      DOA  <= DOA_zd;
      DOB  <= DOB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S1_S2",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S1_S2",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA10_CLKA_posedge,
        TimingData     => Tmkr_ADDRA10_CLKA_posedge,
        TestSignal     => ADDRA_ipd(10),
        TestSignalName => "ADDRA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(10),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(10),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA11_CLKA_posedge,
        TimingData     => Tmkr_ADDRA11_CLKA_posedge,
        TestSignal     => ADDRA_ipd(11),
        TestSignalName => "ADDRA(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(11),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(11),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(11),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(11),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA12_CLKA_posedge,
        TimingData     => Tmkr_ADDRA12_CLKA_posedge,
        TestSignal     => ADDRA_ipd(12),
        TestSignalName => "ADDRA(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(12),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(12),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(12),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(12),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB9_CLKB_posedge,
        TimingData     => Tmkr_ADDRB9_CLKB_posedge,
        TestSignal     => ADDRB_ipd(9),
        TestSignalName => "ADDRB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(9),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(9),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB10_CLKB_posedge,
        TimingData     => Tmkr_ADDRB10_CLKB_posedge,
        TestSignal     => ADDRB_ipd(10),
        TestSignalName => "ADDRB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(10),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(10),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB11_CLKB_posedge,
        TimingData     => Tmkr_ADDRB11_CLKB_posedge,
        TestSignal     => ADDRB_ipd(11),
        TestSignalName => "ADDRB(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(11),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(11),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(11),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(11),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_ADDRA11_CLKA_posedge or
                  Tviol_ADDRA12_CLKA_posedge or
                  Tviol_ADDRA13_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_ADDRB10_CLKB_posedge or
                  Tviol_ADDRB11_CLKB_posedge or
                  Tviol_ADDRB12_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S2",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S2",
                       InstanceName => ramb16_s1_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S1_S2",
                       InstanceName => ramb16_s1_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S2",
                       InstanceName => ramb16_s1_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S1_S2",
                       InstanceName => ramb16_s1_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S2",
                       InstanceName => ramb16_s1_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S1_S2",
                       InstanceName => ramb16_s1_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S1_S2",
                 InstanceName => ramb16_s1_s2'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(0 downto 0);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S2",
                       InstanceName => ramb16_s1_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S1_S2",
                       InstanceName => ramb16_s1_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S2",
                       InstanceName => ramb16_s1_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S1_S2",
                       InstanceName => ramb16_s1_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S1_S2",
                     InstanceName => ramb16_s1_s2'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S1_S2",
                       InstanceName => ramb16_s1_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S1_S2",
                 InstanceName => ramb16_s1_s2'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(1 downto 0);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
    end if;

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S1_S2_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S1_S36.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s1_s36 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S1_S36 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(13 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(8 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPB  : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    tsetup_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    tsetup_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    thold_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    thold_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"0";
    INIT_B : bit_vector := X"000000000";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"0";
    SRVAL_B : bit_vector := X"000000000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(0 downto 0);
    DOB  : out std_logic_vector(31 downto 0);
    DOPB : out std_logic_vector(3 downto 0);

    ADDRA : in std_logic_vector(13 downto 0);
    ADDRB : in std_logic_vector(8 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(0 downto 0);
    DIB   : in std_logic_vector(31 downto 0);
    DIPB  : in std_logic_vector(3 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S1_S36 : entity is true;
end ramb16_s1_s36;

architecture RAMB16_S1_S36_V of RAMB16_S1_S36 is
  attribute VITAL_LEVEL0 of
    RAMB16_S1_S36_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(13 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(0 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(8 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(31 downto 0) := (others => 'X');
  signal DIPB_ipd  : std_logic_vector(3 downto 0)  := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 16384;
  constant length_b : integer := 512;
  constant width_a : integer := 1;
  constant width_b : integer := 32;  

  constant parity_width_b : integer := 4;  
  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);
  type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

  function slv_to_two_D_parity_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_parity_array_type is
    variable two_D_parity_array : two_D_parity_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_parity_array(i) := intermediate; 
    end loop;
    return two_D_parity_array;
  end;        
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 13 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 0 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 8 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 31 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    DIPB_DELAY  : for i in 3 downto 0 generate
      VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i));
    end generate DIPB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA13_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB8_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB9_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB10_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB11_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB12_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB13_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB14_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB15_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB16_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB17_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB18_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB19_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB20_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB21_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB22_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB23_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB24_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB25_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB26_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB27_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB28_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB29_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB30_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB31_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIPB0_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB1_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB2_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB3_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA13_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB8_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB9_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB10_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB11_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB12_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB13_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB14_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB15_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB16_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB17_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB18_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB19_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB20_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB21_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB22_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB23_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB24_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB25_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB26_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB27_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB28_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB29_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB30_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB31_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB0_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB1_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB2_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB3_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;
    variable DOB_GlitchData8  : VitalGlitchDataType;
    variable DOB_GlitchData9  : VitalGlitchDataType;
    variable DOB_GlitchData10  : VitalGlitchDataType;
    variable DOB_GlitchData11  : VitalGlitchDataType;
    variable DOB_GlitchData12  : VitalGlitchDataType;
    variable DOB_GlitchData13  : VitalGlitchDataType;
    variable DOB_GlitchData14  : VitalGlitchDataType;
    variable DOB_GlitchData15  : VitalGlitchDataType;
    variable DOB_GlitchData16  : VitalGlitchDataType;
    variable DOB_GlitchData17  : VitalGlitchDataType;
    variable DOB_GlitchData18  : VitalGlitchDataType;
    variable DOB_GlitchData19  : VitalGlitchDataType;
    variable DOB_GlitchData20  : VitalGlitchDataType;
    variable DOB_GlitchData21  : VitalGlitchDataType;
    variable DOB_GlitchData22  : VitalGlitchDataType;
    variable DOB_GlitchData23  : VitalGlitchDataType;
    variable DOB_GlitchData24  : VitalGlitchDataType;
    variable DOB_GlitchData25  : VitalGlitchDataType;
    variable DOB_GlitchData26  : VitalGlitchDataType;
    variable DOB_GlitchData27  : VitalGlitchDataType;
    variable DOB_GlitchData28  : VitalGlitchDataType;
    variable DOB_GlitchData29  : VitalGlitchDataType;
    variable DOB_GlitchData30  : VitalGlitchDataType;
    variable DOB_GlitchData31  : VitalGlitchDataType;
    variable DOPB_GlitchData0 : VitalGlitchDataType;
    variable DOPB_GlitchData1 : VitalGlitchDataType;
    variable DOPB_GlitchData2 : VitalGlitchDataType;
    variable DOPB_GlitchData3 : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) &
                                                       To_StdLogicVector(INITP_06) &
                                                       To_StdLogicVector(INITP_05) &
                                                       To_StdLogicVector(INITP_04) &
                                                       To_StdLogicVector(INITP_03) &
                                                       To_StdLogicVector(INITP_02) &
                                                       To_StdLogicVector(INITP_01) &
                                                       To_StdLogicVector(INITP_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);
    variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv);        


    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable DOPB_OV_LSB       : integer := 0;
    variable DOPB_OV_MSB       : integer := 3;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (0 downto 0)              := "0";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (35 downto 0)              := "000000000000000000000000000000000000";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (0 downto 0)              := "0";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (35 downto 0)              := "000000000000000000000000000000000000";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(0 downto 0) := INI_A(0 downto 0);
    variable DOB_zd  : std_logic_vector(31 downto 0) := INI_B(31 downto 0);
    variable DOPB_zd : std_logic_vector(3 downto 0)  := INI_B(35 downto 32);

    variable ADDRA_ipd_sampled : std_logic_vector(13 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S1_S36",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 1) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(0 downto 0)                      := INI_A_UNBOUND(0 downto 0);

        for I in INI_A_UNBOUND'high downto 1 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  1 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S1_S36",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 1,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 1) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S1_S36",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 1,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 1) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 36) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(35 downto 0)                      := INI_B_UNBOUND(35 downto 0);

        for I in INI_B_UNBOUND'high downto 36 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  36 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S1_S36",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 36,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 36) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S1_S36",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 36,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 36) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 1) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(0 downto 0)                       := SRVA_A_UNBOUND(0 downto 0);

        for I in SRVA_A_UNBOUND'high downto 1 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  1 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S1_S36",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 1,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 1) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S1_S36",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 1,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 1) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 36) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(35 downto 0)                       := SRVA_B_UNBOUND(35 downto 0);

        for I in SRVA_B_UNBOUND'high downto 36 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  36 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S1_S36",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 36,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 36) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S1_S36",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 36,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 36) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(0 downto 0) := INI_A(0 downto 0);
      DOB_zd(31 downto 0) := INI_B(31 downto 0);
      DOPB_zd(3 downto 0) := INI_B(35 downto 32);
      DOA  <= DOA_zd;
      DOB  <= DOB_zd;
      DOPB <= DOPB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S1_S36",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S1_S36",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA10_CLKA_posedge,
        TimingData     => Tmkr_ADDRA10_CLKA_posedge,
        TestSignal     => ADDRA_ipd(10),
        TestSignalName => "ADDRA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(10),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(10),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA11_CLKA_posedge,
        TimingData     => Tmkr_ADDRA11_CLKA_posedge,
        TestSignal     => ADDRA_ipd(11),
        TestSignalName => "ADDRA(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(11),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(11),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(11),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(11),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA12_CLKA_posedge,
        TimingData     => Tmkr_ADDRA12_CLKA_posedge,
        TestSignal     => ADDRA_ipd(12),
        TestSignalName => "ADDRA(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(12),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(12),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(12),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(12),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB0_CLKB_posedge,
        TimingData     => Tmkr_DIPB0_CLKB_posedge,
        TestSignal     => DIPB_ipd(0),
        TestSignalName => "DIPB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB1_CLKB_posedge,
        TimingData     => Tmkr_DIPB1_CLKB_posedge,
        TestSignal     => DIPB_ipd(1),
        TestSignalName => "DIPB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB2_CLKB_posedge,
        TimingData     => Tmkr_DIPB2_CLKB_posedge,
        TestSignal     => DIPB_ipd(2),
        TestSignalName => "DIPB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB7_CLKB_posedge,
        TimingData     => Tmkr_DIB7_CLKB_posedge,
        TestSignal     => DIB_ipd(7),
        TestSignalName => "DIB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(7),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(7),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB8_CLKB_posedge,
        TimingData     => Tmkr_DIB8_CLKB_posedge,
        TestSignal     => DIB_ipd(8),
        TestSignalName => "DIB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(8),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(8),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB9_CLKB_posedge,
        TimingData     => Tmkr_DIB9_CLKB_posedge,
        TestSignal     => DIB_ipd(9),
        TestSignalName => "DIB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(9),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(9),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB10_CLKB_posedge,
        TimingData     => Tmkr_DIB10_CLKB_posedge,
        TestSignal     => DIB_ipd(10),
        TestSignalName => "DIB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(10),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(10),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB11_CLKB_posedge,
        TimingData     => Tmkr_DIB11_CLKB_posedge,
        TestSignal     => DIB_ipd(11),
        TestSignalName => "DIB(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(11),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(11),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(11),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(11),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB12_CLKB_posedge,
        TimingData     => Tmkr_DIB12_CLKB_posedge,
        TestSignal     => DIB_ipd(12),
        TestSignalName => "DIB(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(12),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(12),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(12),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(12),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB13_CLKB_posedge,
        TimingData     => Tmkr_DIB13_CLKB_posedge,
        TestSignal     => DIB_ipd(13),
        TestSignalName => "DIB(13)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(13),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(13),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(13),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(13),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB14_CLKB_posedge,
        TimingData     => Tmkr_DIB14_CLKB_posedge,
        TestSignal     => DIB_ipd(14),
        TestSignalName => "DIB(14)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(14),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(14),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(14),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(14),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB15_CLKB_posedge,
        TimingData     => Tmkr_DIB15_CLKB_posedge,
        TestSignal     => DIB_ipd(15),
        TestSignalName => "DIB(15)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(15),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(15),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(15),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(15),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB16_CLKB_posedge,
        TimingData     => Tmkr_DIB16_CLKB_posedge,
        TestSignal     => DIB_ipd(16),
        TestSignalName => "DIB(16)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(16),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(16),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(16),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(16),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB17_CLKB_posedge,
        TimingData     => Tmkr_DIB17_CLKB_posedge,
        TestSignal     => DIB_ipd(17),
        TestSignalName => "DIB(17)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(17),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(17),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(17),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(17),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB18_CLKB_posedge,
        TimingData     => Tmkr_DIB18_CLKB_posedge,
        TestSignal     => DIB_ipd(18),
        TestSignalName => "DIB(18)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(18),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(18),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(18),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(18),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB19_CLKB_posedge,
        TimingData     => Tmkr_DIB19_CLKB_posedge,
        TestSignal     => DIB_ipd(19),
        TestSignalName => "DIB(19)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(19),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(19),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(19),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(19),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB20_CLKB_posedge,
        TimingData     => Tmkr_DIB20_CLKB_posedge,
        TestSignal     => DIB_ipd(20),
        TestSignalName => "DIB(20)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(20),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(20),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(20),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(20),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB21_CLKB_posedge,
        TimingData     => Tmkr_DIB21_CLKB_posedge,
        TestSignal     => DIB_ipd(21),
        TestSignalName => "DIB(21)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(21),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(21),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(21),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(21),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB22_CLKB_posedge,
        TimingData     => Tmkr_DIB22_CLKB_posedge,
        TestSignal     => DIB_ipd(22),
        TestSignalName => "DIB(22)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(22),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(22),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(22),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(22),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB23_CLKB_posedge,
        TimingData     => Tmkr_DIB23_CLKB_posedge,
        TestSignal     => DIB_ipd(23),
        TestSignalName => "DIB(23)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(23),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(23),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(23),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(23),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB24_CLKB_posedge,
        TimingData     => Tmkr_DIB24_CLKB_posedge,
        TestSignal     => DIB_ipd(24),
        TestSignalName => "DIB(24)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(24),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(24),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(24),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(24),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB25_CLKB_posedge,
        TimingData     => Tmkr_DIB25_CLKB_posedge,
        TestSignal     => DIB_ipd(25),
        TestSignalName => "DIB(25)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(25),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(25),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(25),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(25),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB26_CLKB_posedge,
        TimingData     => Tmkr_DIB26_CLKB_posedge,
        TestSignal     => DIB_ipd(26),
        TestSignalName => "DIB(26)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(26),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(26),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(26),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(26),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB27_CLKB_posedge,
        TimingData     => Tmkr_DIB27_CLKB_posedge,
        TestSignal     => DIB_ipd(27),
        TestSignalName => "DIB(27)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(27),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(27),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(27),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(27),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB28_CLKB_posedge,
        TimingData     => Tmkr_DIB28_CLKB_posedge,
        TestSignal     => DIB_ipd(28),
        TestSignalName => "DIB(28)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(28),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(28),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(28),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(28),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB29_CLKB_posedge,
        TimingData     => Tmkr_DIB29_CLKB_posedge,
        TestSignal     => DIB_ipd(29),
        TestSignalName => "DIB(29)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(29),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(29),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(29),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(29),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB30_CLKB_posedge,
        TimingData     => Tmkr_DIB30_CLKB_posedge,
        TestSignal     => DIB_ipd(30),
        TestSignalName => "DIB(30)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(30),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(30),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(30),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(30),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_ADDRA11_CLKA_posedge or
                  Tviol_ADDRA12_CLKA_posedge or
                  Tviol_ADDRA13_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_DIB8_CLKB_posedge or
                  Tviol_DIB9_CLKB_posedge or
                  Tviol_DIB10_CLKB_posedge or
                  Tviol_DIB11_CLKB_posedge or
                  Tviol_DIB12_CLKB_posedge or
                  Tviol_DIB13_CLKB_posedge or
                  Tviol_DIB14_CLKB_posedge or
                  Tviol_DIB15_CLKB_posedge or
                  Tviol_DIB16_CLKB_posedge or
                  Tviol_DIB17_CLKB_posedge or
                  Tviol_DIB18_CLKB_posedge or
                  Tviol_DIB19_CLKB_posedge or
                  Tviol_DIB20_CLKB_posedge or
                  Tviol_DIB21_CLKB_posedge or
                  Tviol_DIB22_CLKB_posedge or
                  Tviol_DIB23_CLKB_posedge or
                  Tviol_DIB24_CLKB_posedge or
                  Tviol_DIB25_CLKB_posedge or
                  Tviol_DIB26_CLKB_posedge or
                  Tviol_DIB27_CLKB_posedge or
                  Tviol_DIB28_CLKB_posedge or
                  Tviol_DIB29_CLKB_posedge or
                  Tviol_DIB30_CLKB_posedge or
                  Tviol_DIB31_CLKB_posedge or
                  Tviol_DIPB0_CLKB_posedge or
                  Tviol_DIPB1_CLKB_posedge or
                  Tviol_DIPB2_CLKB_posedge or
                  Tviol_DIPB3_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S36",
                       InstanceName => ramb16_s1_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S1_S36",
                       InstanceName => ramb16_s1_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S36",
                       InstanceName => ramb16_s1_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S1_S36",
                       InstanceName => ramb16_s1_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S36",
                       InstanceName => ramb16_s1_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S1_S36",
                       InstanceName => ramb16_s1_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S1_S36",
                 InstanceName => ramb16_s1_s36'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(0 downto 0);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
              DOPB_zd := DIPB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S36",
                       InstanceName => ramb16_s1_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S1_S36",
                       InstanceName => ramb16_s1_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                DOPB_zd := MEMP(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S36",
                       InstanceName => ramb16_s1_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S1_S36",
                       InstanceName => ramb16_s1_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S1_S36",
                     InstanceName => ramb16_s1_s36'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S1_S36",
                       InstanceName => ramb16_s1_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
            DOPB_zd := MEMP(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S1_S36",
                 InstanceName => ramb16_s1_s36'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(31 downto 0);
          DOPB_zd := SRVA_B(35 downto 32);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
      MEMP(ADDRESS_B) := DIPB_ipd;
    end if;

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);
    DOB_zd(8)  := ViolationB xor DOB_zd(8);
    DOB_zd(9)  := ViolationB xor DOB_zd(9);
    DOB_zd(10)  := ViolationB xor DOB_zd(10);
    DOB_zd(11)  := ViolationB xor DOB_zd(11);
    DOB_zd(12)  := ViolationB xor DOB_zd(12);
    DOB_zd(13)  := ViolationB xor DOB_zd(13);
    DOB_zd(14)  := ViolationB xor DOB_zd(14);
    DOB_zd(15)  := ViolationB xor DOB_zd(15);
    DOB_zd(16)  := ViolationB xor DOB_zd(16);
    DOB_zd(17)  := ViolationB xor DOB_zd(17);
    DOB_zd(18)  := ViolationB xor DOB_zd(18);
    DOB_zd(19)  := ViolationB xor DOB_zd(19);
    DOB_zd(20)  := ViolationB xor DOB_zd(20);
    DOB_zd(21)  := ViolationB xor DOB_zd(21);
    DOB_zd(22)  := ViolationB xor DOB_zd(22);
    DOB_zd(23)  := ViolationB xor DOB_zd(23);
    DOB_zd(24)  := ViolationB xor DOB_zd(24);
    DOB_zd(25)  := ViolationB xor DOB_zd(25);
    DOB_zd(26)  := ViolationB xor DOB_zd(26);
    DOB_zd(27)  := ViolationB xor DOB_zd(27);
    DOB_zd(28)  := ViolationB xor DOB_zd(28);
    DOB_zd(29)  := ViolationB xor DOB_zd(29);
    DOB_zd(30)  := ViolationB xor DOB_zd(30);
    DOB_zd(31)  := ViolationB xor DOB_zd(31);
    DOPB_zd(0) := ViolationB xor DOPB_zd(0);
    DOPB_zd(1) := ViolationB xor DOPB_zd(1);
    DOPB_zd(2) := ViolationB xor DOPB_zd(2);
    DOPB_zd(3) := ViolationB xor DOPB_zd(3);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(8),
      GlitchData    => DOB_GlitchData8,
      OutSignalName => "DOB(8)",
      OutTemp       => DOB_zd(8),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(9),
      GlitchData    => DOB_GlitchData9,
      OutSignalName => "DOB(9)",
      OutTemp       => DOB_zd(9),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(10),
      GlitchData    => DOB_GlitchData10,
      OutSignalName => "DOB(10)",
      OutTemp       => DOB_zd(10),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(11),
      GlitchData    => DOB_GlitchData11,
      OutSignalName => "DOB(11)",
      OutTemp       => DOB_zd(11),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(12),
      GlitchData    => DOB_GlitchData12,
      OutSignalName => "DOB(12)",
      OutTemp       => DOB_zd(12),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(13),
      GlitchData    => DOB_GlitchData13,
      OutSignalName => "DOB(13)",
      OutTemp       => DOB_zd(13),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(14),
      GlitchData    => DOB_GlitchData14,
      OutSignalName => "DOB(14)",
      OutTemp       => DOB_zd(14),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(15),
      GlitchData    => DOB_GlitchData15,
      OutSignalName => "DOB(15)",
      OutTemp       => DOB_zd(15),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(16),
      GlitchData    => DOB_GlitchData16,
      OutSignalName => "DOB(16)",
      OutTemp       => DOB_zd(16),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(16), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(17),
      GlitchData    => DOB_GlitchData17,
      OutSignalName => "DOB(17)",
      OutTemp       => DOB_zd(17),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(17), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(18),
      GlitchData    => DOB_GlitchData18,
      OutSignalName => "DOB(18)",
      OutTemp       => DOB_zd(18),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(18), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(19),
      GlitchData    => DOB_GlitchData19,
      OutSignalName => "DOB(19)",
      OutTemp       => DOB_zd(19),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(19), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(20),
      GlitchData    => DOB_GlitchData20,
      OutSignalName => "DOB(20)",
      OutTemp       => DOB_zd(20),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(20), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(21),
      GlitchData    => DOB_GlitchData21,
      OutSignalName => "DOB(21)",
      OutTemp       => DOB_zd(21),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(21), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(22),
      GlitchData    => DOB_GlitchData22,
      OutSignalName => "DOB(22)",
      OutTemp       => DOB_zd(22),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(22), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(23),
      GlitchData    => DOB_GlitchData23,
      OutSignalName => "DOB(23)",
      OutTemp       => DOB_zd(23),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(23), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(24),
      GlitchData    => DOB_GlitchData24,
      OutSignalName => "DOB(24)",
      OutTemp       => DOB_zd(24),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(24), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(25),
      GlitchData    => DOB_GlitchData25,
      OutSignalName => "DOB(25)",
      OutTemp       => DOB_zd(25),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(25), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(26),
      GlitchData    => DOB_GlitchData26,
      OutSignalName => "DOB(26)",
      OutTemp       => DOB_zd(26),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(26), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(27),
      GlitchData    => DOB_GlitchData27,
      OutSignalName => "DOB(27)",
      OutTemp       => DOB_zd(27),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(27), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(28),
      GlitchData    => DOB_GlitchData28,
      OutSignalName => "DOB(28)",
      OutTemp       => DOB_zd(28),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(28), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(29),
      GlitchData    => DOB_GlitchData29,
      OutSignalName => "DOB(29)",
      OutTemp       => DOB_zd(29),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(29), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(30),
      GlitchData    => DOB_GlitchData30,
      OutSignalName => "DOB(30)",
      OutTemp       => DOB_zd(30),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(30), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(31),
      GlitchData    => DOB_GlitchData31,
      OutSignalName => "DOB(31)",
      OutTemp       => DOB_zd(31),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(31), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(0),
      GlitchData    => DOPB_GlitchData0,
      OutSignalName => "DOPB(0)",
      OutTemp       => DOPB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(1),
      GlitchData    => DOPB_GlitchData1,
      OutSignalName => "DOPB(1)",
      OutTemp       => DOPB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(2),
      GlitchData    => DOPB_GlitchData2,
      OutSignalName => "DOPB(2)",
      OutTemp       => DOPB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(3),
      GlitchData    => DOPB_GlitchData3,
      OutSignalName => "DOPB(3)",
      OutTemp       => DOPB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S1_S36_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S1_S4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s1_s4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S1_S4 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(13 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(11 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";


    INIT_A : bit_vector := X"0";
    INIT_B : bit_vector := X"0";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"0";
    SRVAL_B : bit_vector := X"0";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(0 downto 0);
    DOB  : out std_logic_vector(3 downto 0);

    ADDRA : in std_logic_vector(13 downto 0);
    ADDRB : in std_logic_vector(11 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(0 downto 0);
    DIB   : in std_logic_vector(3 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S1_S4 : entity is true;
end ramb16_s1_s4;

architecture RAMB16_S1_S4_V of RAMB16_S1_S4 is
  attribute VITAL_LEVEL0 of
    RAMB16_S1_S4_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(13 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(0 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(11 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(3 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 16384;
  constant length_b : integer := 4096;
  constant width_a : integer := 1;
  constant width_b : integer := 4;  

  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 13 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 0 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 11 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 3 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA13_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB11_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA13_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);

    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (0 downto 0)              := "0";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (3 downto 0)              := "0000";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (0 downto 0)              := "0";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (3 downto 0)              := "0000";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(0 downto 0) := INI_A(0 downto 0);
    variable DOB_zd  : std_logic_vector(3 downto 0) := INI_B(3 downto 0);

    variable ADDRA_ipd_sampled : std_logic_vector(13 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S1_S4",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 1) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(0 downto 0)                      := INI_A_UNBOUND(0 downto 0);

        for I in INI_A_UNBOUND'high downto 1 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  1 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S1_S4",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 1,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 1) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S1_S4",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 1,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 1) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 4) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(3 downto 0)                      := INI_B_UNBOUND(3 downto 0);

        for I in INI_B_UNBOUND'high downto 4 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  4 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S1_S4",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 4,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 4) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S1_S4",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 4,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 4) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 1) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(0 downto 0)                       := SRVA_A_UNBOUND(0 downto 0);

        for I in SRVA_A_UNBOUND'high downto 1 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  1 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S1_S4",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 1,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 1) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S1_S4",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 1,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 1) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 4) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(3 downto 0)                       := SRVA_B_UNBOUND(3 downto 0);

        for I in SRVA_B_UNBOUND'high downto 4 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  4 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S1_S4",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 4,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 4) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S1_S4",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 4,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 4) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(0 downto 0) := INI_A(0 downto 0);
      DOB_zd(3 downto 0) := INI_B(3 downto 0);
      DOA  <= DOA_zd;
      DOB  <= DOB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S1_S4",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S1_S4",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA10_CLKA_posedge,
        TimingData     => Tmkr_ADDRA10_CLKA_posedge,
        TestSignal     => ADDRA_ipd(10),
        TestSignalName => "ADDRA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(10),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(10),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA11_CLKA_posedge,
        TimingData     => Tmkr_ADDRA11_CLKA_posedge,
        TestSignal     => ADDRA_ipd(11),
        TestSignalName => "ADDRA(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(11),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(11),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(11),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(11),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA12_CLKA_posedge,
        TimingData     => Tmkr_ADDRA12_CLKA_posedge,
        TestSignal     => ADDRA_ipd(12),
        TestSignalName => "ADDRA(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(12),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(12),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(12),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(12),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB9_CLKB_posedge,
        TimingData     => Tmkr_ADDRB9_CLKB_posedge,
        TestSignal     => ADDRB_ipd(9),
        TestSignalName => "ADDRB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(9),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(9),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB10_CLKB_posedge,
        TimingData     => Tmkr_ADDRB10_CLKB_posedge,
        TestSignal     => ADDRB_ipd(10),
        TestSignalName => "ADDRB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(10),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(10),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_ADDRA11_CLKA_posedge or
                  Tviol_ADDRA12_CLKA_posedge or
                  Tviol_ADDRA13_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_ADDRB10_CLKB_posedge or
                  Tviol_ADDRB11_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S4",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S4",
                       InstanceName => ramb16_s1_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S1_S4",
                       InstanceName => ramb16_s1_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S4",
                       InstanceName => ramb16_s1_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S1_S4",
                       InstanceName => ramb16_s1_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S4",
                       InstanceName => ramb16_s1_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S1_S4",
                       InstanceName => ramb16_s1_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S1_S4",
                 InstanceName => ramb16_s1_s4'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(0 downto 0);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S4",
                       InstanceName => ramb16_s1_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S1_S4",
                       InstanceName => ramb16_s1_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S4",
                       InstanceName => ramb16_s1_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S1_S4",
                       InstanceName => ramb16_s1_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S1_S4",
                     InstanceName => ramb16_s1_s4'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S1_S4",
                       InstanceName => ramb16_s1_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S1_S4",
                 InstanceName => ramb16_s1_s4'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(3 downto 0);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
    end if;

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S1_S4_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S1_S9.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s1_s9 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S1_S9 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(13 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(10 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPB  : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOPB : VitalDelayArrayType01(0 downto 0)  := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    tsetup_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    thold_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"0";
    INIT_B : bit_vector := X"000";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"0";
    SRVAL_B : bit_vector := X"000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(0 downto 0);
    DOB  : out std_logic_vector(7 downto 0);
    DOPB : out std_logic_vector(0 downto 0);

    ADDRA : in std_logic_vector(13 downto 0);
    ADDRB : in std_logic_vector(10 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(0 downto 0);
    DIB   : in std_logic_vector(7 downto 0);
    DIPB  : in std_logic_vector(0 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S1_S9 : entity is true;
end ramb16_s1_s9;

architecture RAMB16_S1_S9_V of RAMB16_S1_S9 is
  attribute VITAL_LEVEL0 of
    RAMB16_S1_S9_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(13 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(0 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(10 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(7 downto 0) := (others => 'X');
  signal DIPB_ipd  : std_logic_vector(0 downto 0)  := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 16384;
  constant length_b : integer := 2048;
  constant width_a : integer := 1;
  constant width_b : integer := 8;  

  constant parity_width_b : integer := 1;  
  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);
  type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

  function slv_to_two_D_parity_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_parity_array_type is
    variable two_D_parity_array : two_D_parity_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_parity_array(i) := intermediate; 
    end loop;
    return two_D_parity_array;
  end;        
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 13 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 0 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 10 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 7 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    DIPB_DELAY  : for i in 0 downto 0 generate
      VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i));
    end generate DIPB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA13_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIPB0_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA13_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB0_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;
    variable DOPB_GlitchData0 : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) &
                                                       To_StdLogicVector(INITP_06) &
                                                       To_StdLogicVector(INITP_05) &
                                                       To_StdLogicVector(INITP_04) &
                                                       To_StdLogicVector(INITP_03) &
                                                       To_StdLogicVector(INITP_02) &
                                                       To_StdLogicVector(INITP_01) &
                                                       To_StdLogicVector(INITP_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);
    variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv);        


    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable DOPB_OV_LSB       : integer := 0;
    variable DOPB_OV_MSB       : integer := 0;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (0 downto 0)              := "0";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (8 downto 0)              := "000000000";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (0 downto 0)              := "0";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (8 downto 0)              := "000000000";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(0 downto 0) := INI_A(0 downto 0);
    variable DOB_zd  : std_logic_vector(7 downto 0) := INI_B(7 downto 0);
    variable DOPB_zd : std_logic_vector(0 downto 0)  := INI_B(8 downto 8);

    variable ADDRA_ipd_sampled : std_logic_vector(13 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S1_S9",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 1) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(0 downto 0)                      := INI_A_UNBOUND(0 downto 0);

        for I in INI_A_UNBOUND'high downto 1 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  1 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S1_S9",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 1,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 1) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S1_S9",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 1,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 1) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 9) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(8 downto 0)                      := INI_B_UNBOUND(8 downto 0);

        for I in INI_B_UNBOUND'high downto 9 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  9 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S1_S9",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 9,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 9) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S1_S9",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 9,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 9) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 1) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(0 downto 0)                       := SRVA_A_UNBOUND(0 downto 0);

        for I in SRVA_A_UNBOUND'high downto 1 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  1 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S1_S9",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 1,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 1) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S1_S9",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 1,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 1) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 9) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(8 downto 0)                       := SRVA_B_UNBOUND(8 downto 0);

        for I in SRVA_B_UNBOUND'high downto 9 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  9 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S1_S9",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 9,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 9) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S1_S9",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 9,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 9) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(0 downto 0) := INI_A(0 downto 0);
      DOB_zd(7 downto 0) := INI_B(7 downto 0);
      DOPB_zd(0 downto 0) := INI_B(8 downto 8);
      DOA  <= DOA_zd;
      DOB  <= DOB_zd;
      DOPB <= DOPB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S1_S9",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S1_S9",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA10_CLKA_posedge,
        TimingData     => Tmkr_ADDRA10_CLKA_posedge,
        TestSignal     => ADDRA_ipd(10),
        TestSignalName => "ADDRA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(10),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(10),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA11_CLKA_posedge,
        TimingData     => Tmkr_ADDRA11_CLKA_posedge,
        TestSignal     => ADDRA_ipd(11),
        TestSignalName => "ADDRA(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(11),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(11),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(11),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(11),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA12_CLKA_posedge,
        TimingData     => Tmkr_ADDRA12_CLKA_posedge,
        TestSignal     => ADDRA_ipd(12),
        TestSignalName => "ADDRA(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(12),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(12),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(12),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(12),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB9_CLKB_posedge,
        TimingData     => Tmkr_ADDRB9_CLKB_posedge,
        TestSignal     => ADDRB_ipd(9),
        TestSignalName => "ADDRB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(9),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(9),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_ADDRA11_CLKA_posedge or
                  Tviol_ADDRA12_CLKA_posedge or
                  Tviol_ADDRA13_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_ADDRB10_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_DIPB0_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S1_S9",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S9",
                       InstanceName => ramb16_s1_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S1_S9",
                       InstanceName => ramb16_s1_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S9",
                       InstanceName => ramb16_s1_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S1_S9",
                       InstanceName => ramb16_s1_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S9",
                       InstanceName => ramb16_s1_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S1_S9",
                       InstanceName => ramb16_s1_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S1_S9",
                 InstanceName => ramb16_s1_s9'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(0 downto 0);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
              DOPB_zd := DIPB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S9",
                       InstanceName => ramb16_s1_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S1_S9",
                       InstanceName => ramb16_s1_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                DOPB_zd := MEMP(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S1_S9",
                       InstanceName => ramb16_s1_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S1_S9",
                       InstanceName => ramb16_s1_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S1_S9",
                     InstanceName => ramb16_s1_s9'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S1_S9",
                       InstanceName => ramb16_s1_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
            DOPB_zd := MEMP(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S1_S9",
                 InstanceName => ramb16_s1_s9'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(7 downto 0);
          DOPB_zd := SRVA_B(8 downto 8);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
      MEMP(ADDRESS_B) := DIPB_ipd;
    end if;

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);
    DOPB_zd(0) := ViolationB xor DOPB_zd(0);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(0),
      GlitchData    => DOPB_GlitchData0,
      OutSignalName => "DOPB(0)",
      OutTemp       => DOPB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S1_S9_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb16_s2.vhd,v 1.7 2005/10/07 18:35:24 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Single Port Block RAM
-- /___/   /\     Filename : RAMB16_S2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:51 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    09/26/05 - Fixed CR# 216846. INIT and SRVAL attributes length check and adjustment.
-- END Revision

----- CELL RAMB16_S2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S2 is

  generic (
    INIT : bit_vector := X"0";
    SRVAL : bit_vector := X"0";
    WRITE_MODE : string := "WRITE_FIRST";

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
    );

  port (
    DO : out STD_LOGIC_VECTOR (1 downto 0);
    
    ADDR : in STD_LOGIC_VECTOR (12 downto 0);
    CLK : in STD_ULOGIC;
    DI : in STD_LOGIC_VECTOR (1 downto 0);
    EN : in STD_ULOGIC;
    SSR : in STD_ULOGIC;
    WE : in STD_ULOGIC
    );
end RAMB16_S2;

architecture RAMB16_S2_V of RAMB16_S2 is
  constant length : integer := 8192;
  constant width : integer := 2;

  type Two_D_array_type is array ((length -  1) downto 0) of std_logic_vector((width - 1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;  
begin
  VITALBehavior : process
    variable address : integer;
    variable valid_addr : boolean := FALSE;
    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F & INIT_3E & INIT_3D & INIT_3C &
                                                                             INIT_3B & INIT_3A & INIT_39 & INIT_38 &
                                                                             INIT_37 & INIT_36 & INIT_35 & INIT_34 &
                                                                             INIT_33 & INIT_32 & INIT_31 & INIT_30 &
                                                                             INIT_2F & INIT_2E & INIT_2D & INIT_2C &
                                                                             INIT_2B & INIT_2A & INIT_29 & INIT_28 &
                                                                             INIT_27 & INIT_26 & INIT_25 & INIT_24 &
                                                                             INIT_23 & INIT_22 & INIT_21 & INIT_20 &
                                                                             INIT_1F & INIT_1E & INIT_1D & INIT_1C &
                                                                             INIT_1B & INIT_1A & INIT_19 & INIT_18 &
                                                                             INIT_17 & INIT_16 & INIT_15 & INIT_14 &
                                                                             INIT_13 & INIT_12 & INIT_11 & INIT_10 &
                                                                             INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                             INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                             INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                             INIT_03 & INIT_02 & INIT_01 & INIT_00);
    variable mem : Two_D_array_type := slv_to_two_D_array(length, width, mem_slv);

    variable wr_mode : integer := 0;    
    variable first_time : boolean := true;

    variable INIT_reg         : std_logic_vector (1 downto 0) := "00";
    variable SRVAL_reg         : std_logic_vector (1 downto 0) := "00";            

  begin
    if (first_time) then
      if ((WRITE_MODE = "write_first") or (WRITE_MODE = "WRITE_FIRST")) then
        wr_mode := 0;
      elsif ((WRITE_MODE = "read_first") or (WRITE_MODE = "READ_FIRST")) then
        wr_mode := 1;
      elsif ((WRITE_MODE = "no_change") or (WRITE_MODE = "NO_CHANGE")) then
        wr_mode := 2;
      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Error ",
           GenericName          => " WRITE_MODE ",
           EntityName           => "/RAMB16_S2",
           GenericValue         => WRITE_MODE,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => error
           );
      end if;
      if (INIT'length > 2) then
        INIT_reg(1 downto 0) := To_StdLogicVector(INIT)(1 downto 0);
      else
        INIT_reg(INIT'length-1 downto 0) := To_StdLogicVector(INIT);
      end if;      
      DO <= INIT_reg(1 downto 0);
      
      if (SRVAL'length > 2) then
        SRVAL_reg(1 downto 0) := To_StdLogicVector(SRVAL)(1 downto 0);
      else
        SRVAL_reg(SRVAL'length-1 downto 0) := To_StdLogicVector(SRVAL);
      end if;            
      first_time := false;
    end if;
      
    valid_addr := addr_is_valid(addr);
    
    if (valid_addr) then
      address := slv_to_int(addr);
    end if;
    
    if (rising_edge(CLK)) then
      if (EN = '1') then
        if (SSR = '1') then
          DO <= SRVAL_reg(1 downto 0) after 100 ps;
        else    
          if (WE = '1') then
            if (wr_mode = 0) then
              DO <= DI after 100 ps;
            elsif (wr_mode = 1) then
              DO <= mem(address) after 100 ps;  
            end if;
          else 
            if (valid_addr) then
              DO <= mem(address) after 100 ps;
            end if;
          end if;
        end if;
        if (WE = '1') then
          if (valid_addr) then
            mem(address) := DI;
          end if;
        end if;  
      end if;
    end if;
    wait on CLK;    

  end process VITALBehavior;

end RAMB16_S2_V;


-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S2_S18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s2_s18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S2_S18 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(12 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(9 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPB  : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOPB : VitalDelayArrayType01(1 downto 0)  := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    tsetup_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    thold_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"0";
    INIT_B : bit_vector := X"00000";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"0";
    SRVAL_B : bit_vector := X"00000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(1 downto 0);
    DOB  : out std_logic_vector(15 downto 0);
    DOPB : out std_logic_vector(1 downto 0);

    ADDRA : in std_logic_vector(12 downto 0);
    ADDRB : in std_logic_vector(9 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(1 downto 0);
    DIB   : in std_logic_vector(15 downto 0);
    DIPB  : in std_logic_vector(1 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S2_S18 : entity is true;
end ramb16_s2_s18;

architecture RAMB16_S2_S18_V of RAMB16_S2_S18 is
  attribute VITAL_LEVEL0 of
    RAMB16_S2_S18_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(12 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(1 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(9 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(15 downto 0) := (others => 'X');
  signal DIPB_ipd  : std_logic_vector(1 downto 0)  := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 8192;
  constant length_b : integer := 1024;
  constant width_a : integer := 2;
  constant width_b : integer := 16;  

  constant parity_width_b : integer := 2;  
  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);
  type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

  function slv_to_two_D_parity_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_parity_array_type is
    variable two_D_parity_array : two_D_parity_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_parity_array(i) := intermediate; 
    end loop;
    return two_D_parity_array;
  end;        
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 12 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 1 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 9 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 15 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    DIPB_DELAY  : for i in 1 downto 0 generate
      VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i));
    end generate DIPB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB8_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB9_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB10_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB11_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB12_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB13_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB14_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB15_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIPB0_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB1_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB8_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB9_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB10_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB11_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB12_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB13_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB14_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB15_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB0_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB1_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;
    variable DOB_GlitchData8  : VitalGlitchDataType;
    variable DOB_GlitchData9  : VitalGlitchDataType;
    variable DOB_GlitchData10  : VitalGlitchDataType;
    variable DOB_GlitchData11  : VitalGlitchDataType;
    variable DOB_GlitchData12  : VitalGlitchDataType;
    variable DOB_GlitchData13  : VitalGlitchDataType;
    variable DOB_GlitchData14  : VitalGlitchDataType;
    variable DOB_GlitchData15  : VitalGlitchDataType;
    variable DOPB_GlitchData0 : VitalGlitchDataType;
    variable DOPB_GlitchData1 : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) &
                                                       To_StdLogicVector(INITP_06) &
                                                       To_StdLogicVector(INITP_05) &
                                                       To_StdLogicVector(INITP_04) &
                                                       To_StdLogicVector(INITP_03) &
                                                       To_StdLogicVector(INITP_02) &
                                                       To_StdLogicVector(INITP_01) &
                                                       To_StdLogicVector(INITP_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);
    variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv);        


    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable DOPB_OV_LSB       : integer := 0;
    variable DOPB_OV_MSB       : integer := 1;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (1 downto 0)              := "00";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (17 downto 0)              := "000000000000000000";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (1 downto 0)              := "00";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (17 downto 0)              := "000000000000000000";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(1 downto 0) := INI_A(1 downto 0);
    variable DOB_zd  : std_logic_vector(15 downto 0) := INI_B(15 downto 0);
    variable DOPB_zd : std_logic_vector(1 downto 0)  := INI_B(17 downto 16);

    variable ADDRA_ipd_sampled : std_logic_vector(12 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S2_S18",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 2) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(1 downto 0)                      := INI_A_UNBOUND(1 downto 0);

        for I in INI_A_UNBOUND'high downto 2 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  2 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S2_S18",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 2,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 2) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S2_S18",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 2,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 2) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 18) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(17 downto 0)                      := INI_B_UNBOUND(17 downto 0);

        for I in INI_B_UNBOUND'high downto 18 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  18 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S2_S18",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 18,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 18) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S2_S18",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 18,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 18) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 2) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(1 downto 0)                       := SRVA_A_UNBOUND(1 downto 0);

        for I in SRVA_A_UNBOUND'high downto 2 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  2 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S2_S18",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 2,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 2) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S2_S18",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 2,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 2) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 18) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(17 downto 0)                       := SRVA_B_UNBOUND(17 downto 0);

        for I in SRVA_B_UNBOUND'high downto 18 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  18 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S2_S18",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 18,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 18) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S2_S18",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 18,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 18) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(1 downto 0) := INI_A(1 downto 0);
      DOB_zd(15 downto 0) := INI_B(15 downto 0);
      DOPB_zd(1 downto 0) := INI_B(17 downto 16);
      DOA  <= DOA_zd;
      DOB  <= DOB_zd;
      DOPB <= DOPB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S2_S18",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S2_S18",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA10_CLKA_posedge,
        TimingData     => Tmkr_ADDRA10_CLKA_posedge,
        TestSignal     => ADDRA_ipd(10),
        TestSignalName => "ADDRA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(10),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(10),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA11_CLKA_posedge,
        TimingData     => Tmkr_ADDRA11_CLKA_posedge,
        TestSignal     => ADDRA_ipd(11),
        TestSignalName => "ADDRA(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(11),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(11),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(11),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(11),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB0_CLKB_posedge,
        TimingData     => Tmkr_DIPB0_CLKB_posedge,
        TestSignal     => DIPB_ipd(0),
        TestSignalName => "DIPB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB7_CLKB_posedge,
        TimingData     => Tmkr_DIB7_CLKB_posedge,
        TestSignal     => DIB_ipd(7),
        TestSignalName => "DIB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(7),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(7),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB8_CLKB_posedge,
        TimingData     => Tmkr_DIB8_CLKB_posedge,
        TestSignal     => DIB_ipd(8),
        TestSignalName => "DIB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(8),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(8),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB9_CLKB_posedge,
        TimingData     => Tmkr_DIB9_CLKB_posedge,
        TestSignal     => DIB_ipd(9),
        TestSignalName => "DIB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(9),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(9),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB10_CLKB_posedge,
        TimingData     => Tmkr_DIB10_CLKB_posedge,
        TestSignal     => DIB_ipd(10),
        TestSignalName => "DIB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(10),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(10),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB11_CLKB_posedge,
        TimingData     => Tmkr_DIB11_CLKB_posedge,
        TestSignal     => DIB_ipd(11),
        TestSignalName => "DIB(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(11),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(11),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(11),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(11),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB12_CLKB_posedge,
        TimingData     => Tmkr_DIB12_CLKB_posedge,
        TestSignal     => DIB_ipd(12),
        TestSignalName => "DIB(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(12),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(12),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(12),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(12),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB13_CLKB_posedge,
        TimingData     => Tmkr_DIB13_CLKB_posedge,
        TestSignal     => DIB_ipd(13),
        TestSignalName => "DIB(13)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(13),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(13),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(13),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(13),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB14_CLKB_posedge,
        TimingData     => Tmkr_DIB14_CLKB_posedge,
        TestSignal     => DIB_ipd(14),
        TestSignalName => "DIB(14)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(14),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(14),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(14),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(14),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_ADDRA11_CLKA_posedge or
                  Tviol_ADDRA12_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_DIB8_CLKB_posedge or
                  Tviol_DIB9_CLKB_posedge or
                  Tviol_DIB10_CLKB_posedge or
                  Tviol_DIB11_CLKB_posedge or
                  Tviol_DIB12_CLKB_posedge or
                  Tviol_DIB13_CLKB_posedge or
                  Tviol_DIB14_CLKB_posedge or
                  Tviol_DIB15_CLKB_posedge or
                  Tviol_DIPB0_CLKB_posedge or
                  Tviol_DIPB1_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S18",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S18",
                       InstanceName => ramb16_s2_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S2_S18",
                       InstanceName => ramb16_s2_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S18",
                       InstanceName => ramb16_s2_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S2_S18",
                       InstanceName => ramb16_s2_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S18",
                       InstanceName => ramb16_s2_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S2_S18",
                       InstanceName => ramb16_s2_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S2_S18",
                 InstanceName => ramb16_s2_s18'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(1 downto 0);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
              DOPB_zd := DIPB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S18",
                       InstanceName => ramb16_s2_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S2_S18",
                       InstanceName => ramb16_s2_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                DOPB_zd := MEMP(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S18",
                       InstanceName => ramb16_s2_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S2_S18",
                       InstanceName => ramb16_s2_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S2_S18",
                     InstanceName => ramb16_s2_s18'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S2_S18",
                       InstanceName => ramb16_s2_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
            DOPB_zd := MEMP(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S2_S18",
                 InstanceName => ramb16_s2_s18'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(15 downto 0);
          DOPB_zd := SRVA_B(17 downto 16);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
      MEMP(ADDRESS_B) := DIPB_ipd;
    end if;

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);
    DOB_zd(8)  := ViolationB xor DOB_zd(8);
    DOB_zd(9)  := ViolationB xor DOB_zd(9);
    DOB_zd(10)  := ViolationB xor DOB_zd(10);
    DOB_zd(11)  := ViolationB xor DOB_zd(11);
    DOB_zd(12)  := ViolationB xor DOB_zd(12);
    DOB_zd(13)  := ViolationB xor DOB_zd(13);
    DOB_zd(14)  := ViolationB xor DOB_zd(14);
    DOB_zd(15)  := ViolationB xor DOB_zd(15);
    DOPB_zd(0) := ViolationB xor DOPB_zd(0);
    DOPB_zd(1) := ViolationB xor DOPB_zd(1);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(8),
      GlitchData    => DOB_GlitchData8,
      OutSignalName => "DOB(8)",
      OutTemp       => DOB_zd(8),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(9),
      GlitchData    => DOB_GlitchData9,
      OutSignalName => "DOB(9)",
      OutTemp       => DOB_zd(9),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(10),
      GlitchData    => DOB_GlitchData10,
      OutSignalName => "DOB(10)",
      OutTemp       => DOB_zd(10),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(11),
      GlitchData    => DOB_GlitchData11,
      OutSignalName => "DOB(11)",
      OutTemp       => DOB_zd(11),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(12),
      GlitchData    => DOB_GlitchData12,
      OutSignalName => "DOB(12)",
      OutTemp       => DOB_zd(12),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(13),
      GlitchData    => DOB_GlitchData13,
      OutSignalName => "DOB(13)",
      OutTemp       => DOB_zd(13),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(14),
      GlitchData    => DOB_GlitchData14,
      OutSignalName => "DOB(14)",
      OutTemp       => DOB_zd(14),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(15),
      GlitchData    => DOB_GlitchData15,
      OutSignalName => "DOB(15)",
      OutTemp       => DOB_zd(15),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(0),
      GlitchData    => DOPB_GlitchData0,
      OutSignalName => "DOPB(0)",
      OutTemp       => DOPB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(1),
      GlitchData    => DOPB_GlitchData1,
      OutSignalName => "DOPB(1)",
      OutTemp       => DOPB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S2_S18_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S2_S2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s2_s2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S2_S2 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(12 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(12 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";


    INIT_A : bit_vector := X"0";
    INIT_B : bit_vector := X"0";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"0";
    SRVAL_B : bit_vector := X"0";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(1 downto 0);
    DOB  : out std_logic_vector(1 downto 0);

    ADDRA : in std_logic_vector(12 downto 0);
    ADDRB : in std_logic_vector(12 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(1 downto 0);
    DIB   : in std_logic_vector(1 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S2_S2 : entity is true;
end ramb16_s2_s2;

architecture RAMB16_S2_S2_V of RAMB16_S2_S2 is
  attribute VITAL_LEVEL0 of
    RAMB16_S2_S2_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(12 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(1 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(12 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(1 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 8192;
  constant length_b : integer := 8192;
  constant width_a : integer := 2;
  constant width_b : integer := 2;  

  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 12 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 1 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 12 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 1 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB11_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB12_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);

    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (1 downto 0)              := "00";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (1 downto 0)              := "00";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (1 downto 0)              := "00";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (1 downto 0)              := "00";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(1 downto 0) := INI_A(1 downto 0);
    variable DOB_zd  : std_logic_vector(1 downto 0) := INI_B(1 downto 0);

    variable ADDRA_ipd_sampled : std_logic_vector(12 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(12 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S2_S2",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 2) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(1 downto 0)                      := INI_A_UNBOUND(1 downto 0);

        for I in INI_A_UNBOUND'high downto 2 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  2 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S2_S2",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 2,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 2) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S2_S2",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 2,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 2) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 2) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(1 downto 0)                      := INI_B_UNBOUND(1 downto 0);

        for I in INI_B_UNBOUND'high downto 2 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  2 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S2_S2",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 2,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 2) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S2_S2",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 2,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 2) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 2) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(1 downto 0)                       := SRVA_A_UNBOUND(1 downto 0);

        for I in SRVA_A_UNBOUND'high downto 2 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  2 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S2_S2",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 2,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 2) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S2_S2",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 2,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 2) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 2) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(1 downto 0)                       := SRVA_B_UNBOUND(1 downto 0);

        for I in SRVA_B_UNBOUND'high downto 2 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  2 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S2_S2",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 2,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 2) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S2_S2",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 2,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 2) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(1 downto 0) := INI_A(1 downto 0);
      DOB_zd(1 downto 0) := INI_B(1 downto 0);
      DOA  <= DOA_zd;
      DOB  <= DOB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S2_S2",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S2_S2",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA10_CLKA_posedge,
        TimingData     => Tmkr_ADDRA10_CLKA_posedge,
        TestSignal     => ADDRA_ipd(10),
        TestSignalName => "ADDRA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(10),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(10),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA11_CLKA_posedge,
        TimingData     => Tmkr_ADDRA11_CLKA_posedge,
        TestSignal     => ADDRA_ipd(11),
        TestSignalName => "ADDRA(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(11),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(11),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(11),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(11),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB9_CLKB_posedge,
        TimingData     => Tmkr_ADDRB9_CLKB_posedge,
        TestSignal     => ADDRB_ipd(9),
        TestSignalName => "ADDRB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(9),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(9),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB10_CLKB_posedge,
        TimingData     => Tmkr_ADDRB10_CLKB_posedge,
        TestSignal     => ADDRB_ipd(10),
        TestSignalName => "ADDRB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(10),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(10),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB11_CLKB_posedge,
        TimingData     => Tmkr_ADDRB11_CLKB_posedge,
        TestSignal     => ADDRB_ipd(11),
        TestSignalName => "ADDRB(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(11),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(11),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(11),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(11),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_ADDRA11_CLKA_posedge or
                  Tviol_ADDRA12_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_ADDRB10_CLKB_posedge or
                  Tviol_ADDRB11_CLKB_posedge or
                  Tviol_ADDRB12_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S2",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S2",
                       InstanceName => ramb16_s2_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S2_S2",
                       InstanceName => ramb16_s2_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S2",
                       InstanceName => ramb16_s2_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S2_S2",
                       InstanceName => ramb16_s2_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S2",
                       InstanceName => ramb16_s2_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S2_S2",
                       InstanceName => ramb16_s2_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S2_S2",
                 InstanceName => ramb16_s2_s2'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(1 downto 0);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S2",
                       InstanceName => ramb16_s2_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S2_S2",
                       InstanceName => ramb16_s2_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S2",
                       InstanceName => ramb16_s2_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S2_S2",
                       InstanceName => ramb16_s2_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S2_S2",
                     InstanceName => ramb16_s2_s2'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S2_S2",
                       InstanceName => ramb16_s2_s2'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S2_S2",
                 InstanceName => ramb16_s2_s2'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(1 downto 0);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
    end if;

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S2_S2_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S2_S36.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s2_s36 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S2_S36 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(12 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(8 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPB  : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    tsetup_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    tsetup_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    thold_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    thold_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"0";
    INIT_B : bit_vector := X"000000000";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"0";
    SRVAL_B : bit_vector := X"000000000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(1 downto 0);
    DOB  : out std_logic_vector(31 downto 0);
    DOPB : out std_logic_vector(3 downto 0);

    ADDRA : in std_logic_vector(12 downto 0);
    ADDRB : in std_logic_vector(8 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(1 downto 0);
    DIB   : in std_logic_vector(31 downto 0);
    DIPB  : in std_logic_vector(3 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S2_S36 : entity is true;
end ramb16_s2_s36;

architecture RAMB16_S2_S36_V of RAMB16_S2_S36 is
  attribute VITAL_LEVEL0 of
    RAMB16_S2_S36_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(12 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(1 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(8 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(31 downto 0) := (others => 'X');
  signal DIPB_ipd  : std_logic_vector(3 downto 0)  := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 8192;
  constant length_b : integer := 512;
  constant width_a : integer := 2;
  constant width_b : integer := 32;  

  constant parity_width_b : integer := 4;  
  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);
  type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

  function slv_to_two_D_parity_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_parity_array_type is
    variable two_D_parity_array : two_D_parity_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_parity_array(i) := intermediate; 
    end loop;
    return two_D_parity_array;
  end;        
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 12 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 1 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 8 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 31 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    DIPB_DELAY  : for i in 3 downto 0 generate
      VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i));
    end generate DIPB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB8_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB9_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB10_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB11_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB12_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB13_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB14_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB15_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB16_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB17_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB18_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB19_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB20_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB21_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB22_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB23_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB24_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB25_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB26_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB27_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB28_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB29_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB30_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB31_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIPB0_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB1_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB2_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB3_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB8_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB9_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB10_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB11_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB12_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB13_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB14_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB15_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB16_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB17_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB18_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB19_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB20_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB21_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB22_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB23_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB24_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB25_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB26_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB27_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB28_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB29_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB30_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB31_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB0_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB1_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB2_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB3_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;
    variable DOB_GlitchData8  : VitalGlitchDataType;
    variable DOB_GlitchData9  : VitalGlitchDataType;
    variable DOB_GlitchData10  : VitalGlitchDataType;
    variable DOB_GlitchData11  : VitalGlitchDataType;
    variable DOB_GlitchData12  : VitalGlitchDataType;
    variable DOB_GlitchData13  : VitalGlitchDataType;
    variable DOB_GlitchData14  : VitalGlitchDataType;
    variable DOB_GlitchData15  : VitalGlitchDataType;
    variable DOB_GlitchData16  : VitalGlitchDataType;
    variable DOB_GlitchData17  : VitalGlitchDataType;
    variable DOB_GlitchData18  : VitalGlitchDataType;
    variable DOB_GlitchData19  : VitalGlitchDataType;
    variable DOB_GlitchData20  : VitalGlitchDataType;
    variable DOB_GlitchData21  : VitalGlitchDataType;
    variable DOB_GlitchData22  : VitalGlitchDataType;
    variable DOB_GlitchData23  : VitalGlitchDataType;
    variable DOB_GlitchData24  : VitalGlitchDataType;
    variable DOB_GlitchData25  : VitalGlitchDataType;
    variable DOB_GlitchData26  : VitalGlitchDataType;
    variable DOB_GlitchData27  : VitalGlitchDataType;
    variable DOB_GlitchData28  : VitalGlitchDataType;
    variable DOB_GlitchData29  : VitalGlitchDataType;
    variable DOB_GlitchData30  : VitalGlitchDataType;
    variable DOB_GlitchData31  : VitalGlitchDataType;
    variable DOPB_GlitchData0 : VitalGlitchDataType;
    variable DOPB_GlitchData1 : VitalGlitchDataType;
    variable DOPB_GlitchData2 : VitalGlitchDataType;
    variable DOPB_GlitchData3 : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) &
                                                       To_StdLogicVector(INITP_06) &
                                                       To_StdLogicVector(INITP_05) &
                                                       To_StdLogicVector(INITP_04) &
                                                       To_StdLogicVector(INITP_03) &
                                                       To_StdLogicVector(INITP_02) &
                                                       To_StdLogicVector(INITP_01) &
                                                       To_StdLogicVector(INITP_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);
    variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv);        


    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable DOPB_OV_LSB       : integer := 0;
    variable DOPB_OV_MSB       : integer := 3;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (1 downto 0)              := "00";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (35 downto 0)              := "000000000000000000000000000000000000";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (1 downto 0)              := "00";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (35 downto 0)              := "000000000000000000000000000000000000";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(1 downto 0) := INI_A(1 downto 0);
    variable DOB_zd  : std_logic_vector(31 downto 0) := INI_B(31 downto 0);
    variable DOPB_zd : std_logic_vector(3 downto 0)  := INI_B(35 downto 32);

    variable ADDRA_ipd_sampled : std_logic_vector(12 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S2_S36",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 2) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(1 downto 0)                      := INI_A_UNBOUND(1 downto 0);

        for I in INI_A_UNBOUND'high downto 2 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  2 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S2_S36",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 2,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 2) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S2_S36",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 2,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 2) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 36) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(35 downto 0)                      := INI_B_UNBOUND(35 downto 0);

        for I in INI_B_UNBOUND'high downto 36 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  36 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S2_S36",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 36,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 36) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S2_S36",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 36,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 36) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 2) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(1 downto 0)                       := SRVA_A_UNBOUND(1 downto 0);

        for I in SRVA_A_UNBOUND'high downto 2 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  2 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S2_S36",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 2,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 2) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S2_S36",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 2,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 2) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 36) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(35 downto 0)                       := SRVA_B_UNBOUND(35 downto 0);

        for I in SRVA_B_UNBOUND'high downto 36 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  36 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S2_S36",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 36,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 36) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S2_S36",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 36,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 36) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(1 downto 0) := INI_A(1 downto 0);
      DOB_zd(31 downto 0) := INI_B(31 downto 0);
      DOPB_zd(3 downto 0) := INI_B(35 downto 32);
      DOA  <= DOA_zd;
      DOB  <= DOB_zd;
      DOPB <= DOPB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S2_S36",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S2_S36",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA10_CLKA_posedge,
        TimingData     => Tmkr_ADDRA10_CLKA_posedge,
        TestSignal     => ADDRA_ipd(10),
        TestSignalName => "ADDRA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(10),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(10),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA11_CLKA_posedge,
        TimingData     => Tmkr_ADDRA11_CLKA_posedge,
        TestSignal     => ADDRA_ipd(11),
        TestSignalName => "ADDRA(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(11),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(11),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(11),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(11),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB0_CLKB_posedge,
        TimingData     => Tmkr_DIPB0_CLKB_posedge,
        TestSignal     => DIPB_ipd(0),
        TestSignalName => "DIPB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB1_CLKB_posedge,
        TimingData     => Tmkr_DIPB1_CLKB_posedge,
        TestSignal     => DIPB_ipd(1),
        TestSignalName => "DIPB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB2_CLKB_posedge,
        TimingData     => Tmkr_DIPB2_CLKB_posedge,
        TestSignal     => DIPB_ipd(2),
        TestSignalName => "DIPB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB7_CLKB_posedge,
        TimingData     => Tmkr_DIB7_CLKB_posedge,
        TestSignal     => DIB_ipd(7),
        TestSignalName => "DIB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(7),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(7),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB8_CLKB_posedge,
        TimingData     => Tmkr_DIB8_CLKB_posedge,
        TestSignal     => DIB_ipd(8),
        TestSignalName => "DIB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(8),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(8),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB9_CLKB_posedge,
        TimingData     => Tmkr_DIB9_CLKB_posedge,
        TestSignal     => DIB_ipd(9),
        TestSignalName => "DIB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(9),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(9),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB10_CLKB_posedge,
        TimingData     => Tmkr_DIB10_CLKB_posedge,
        TestSignal     => DIB_ipd(10),
        TestSignalName => "DIB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(10),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(10),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB11_CLKB_posedge,
        TimingData     => Tmkr_DIB11_CLKB_posedge,
        TestSignal     => DIB_ipd(11),
        TestSignalName => "DIB(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(11),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(11),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(11),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(11),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB12_CLKB_posedge,
        TimingData     => Tmkr_DIB12_CLKB_posedge,
        TestSignal     => DIB_ipd(12),
        TestSignalName => "DIB(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(12),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(12),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(12),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(12),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB13_CLKB_posedge,
        TimingData     => Tmkr_DIB13_CLKB_posedge,
        TestSignal     => DIB_ipd(13),
        TestSignalName => "DIB(13)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(13),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(13),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(13),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(13),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB14_CLKB_posedge,
        TimingData     => Tmkr_DIB14_CLKB_posedge,
        TestSignal     => DIB_ipd(14),
        TestSignalName => "DIB(14)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(14),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(14),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(14),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(14),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB15_CLKB_posedge,
        TimingData     => Tmkr_DIB15_CLKB_posedge,
        TestSignal     => DIB_ipd(15),
        TestSignalName => "DIB(15)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(15),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(15),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(15),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(15),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB16_CLKB_posedge,
        TimingData     => Tmkr_DIB16_CLKB_posedge,
        TestSignal     => DIB_ipd(16),
        TestSignalName => "DIB(16)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(16),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(16),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(16),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(16),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB17_CLKB_posedge,
        TimingData     => Tmkr_DIB17_CLKB_posedge,
        TestSignal     => DIB_ipd(17),
        TestSignalName => "DIB(17)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(17),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(17),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(17),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(17),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB18_CLKB_posedge,
        TimingData     => Tmkr_DIB18_CLKB_posedge,
        TestSignal     => DIB_ipd(18),
        TestSignalName => "DIB(18)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(18),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(18),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(18),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(18),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB19_CLKB_posedge,
        TimingData     => Tmkr_DIB19_CLKB_posedge,
        TestSignal     => DIB_ipd(19),
        TestSignalName => "DIB(19)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(19),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(19),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(19),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(19),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB20_CLKB_posedge,
        TimingData     => Tmkr_DIB20_CLKB_posedge,
        TestSignal     => DIB_ipd(20),
        TestSignalName => "DIB(20)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(20),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(20),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(20),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(20),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB21_CLKB_posedge,
        TimingData     => Tmkr_DIB21_CLKB_posedge,
        TestSignal     => DIB_ipd(21),
        TestSignalName => "DIB(21)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(21),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(21),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(21),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(21),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB22_CLKB_posedge,
        TimingData     => Tmkr_DIB22_CLKB_posedge,
        TestSignal     => DIB_ipd(22),
        TestSignalName => "DIB(22)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(22),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(22),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(22),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(22),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB23_CLKB_posedge,
        TimingData     => Tmkr_DIB23_CLKB_posedge,
        TestSignal     => DIB_ipd(23),
        TestSignalName => "DIB(23)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(23),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(23),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(23),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(23),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB24_CLKB_posedge,
        TimingData     => Tmkr_DIB24_CLKB_posedge,
        TestSignal     => DIB_ipd(24),
        TestSignalName => "DIB(24)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(24),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(24),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(24),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(24),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB25_CLKB_posedge,
        TimingData     => Tmkr_DIB25_CLKB_posedge,
        TestSignal     => DIB_ipd(25),
        TestSignalName => "DIB(25)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(25),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(25),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(25),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(25),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB26_CLKB_posedge,
        TimingData     => Tmkr_DIB26_CLKB_posedge,
        TestSignal     => DIB_ipd(26),
        TestSignalName => "DIB(26)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(26),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(26),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(26),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(26),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB27_CLKB_posedge,
        TimingData     => Tmkr_DIB27_CLKB_posedge,
        TestSignal     => DIB_ipd(27),
        TestSignalName => "DIB(27)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(27),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(27),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(27),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(27),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB28_CLKB_posedge,
        TimingData     => Tmkr_DIB28_CLKB_posedge,
        TestSignal     => DIB_ipd(28),
        TestSignalName => "DIB(28)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(28),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(28),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(28),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(28),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB29_CLKB_posedge,
        TimingData     => Tmkr_DIB29_CLKB_posedge,
        TestSignal     => DIB_ipd(29),
        TestSignalName => "DIB(29)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(29),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(29),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(29),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(29),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB30_CLKB_posedge,
        TimingData     => Tmkr_DIB30_CLKB_posedge,
        TestSignal     => DIB_ipd(30),
        TestSignalName => "DIB(30)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(30),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(30),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(30),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(30),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_ADDRA11_CLKA_posedge or
                  Tviol_ADDRA12_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_DIB8_CLKB_posedge or
                  Tviol_DIB9_CLKB_posedge or
                  Tviol_DIB10_CLKB_posedge or
                  Tviol_DIB11_CLKB_posedge or
                  Tviol_DIB12_CLKB_posedge or
                  Tviol_DIB13_CLKB_posedge or
                  Tviol_DIB14_CLKB_posedge or
                  Tviol_DIB15_CLKB_posedge or
                  Tviol_DIB16_CLKB_posedge or
                  Tviol_DIB17_CLKB_posedge or
                  Tviol_DIB18_CLKB_posedge or
                  Tviol_DIB19_CLKB_posedge or
                  Tviol_DIB20_CLKB_posedge or
                  Tviol_DIB21_CLKB_posedge or
                  Tviol_DIB22_CLKB_posedge or
                  Tviol_DIB23_CLKB_posedge or
                  Tviol_DIB24_CLKB_posedge or
                  Tviol_DIB25_CLKB_posedge or
                  Tviol_DIB26_CLKB_posedge or
                  Tviol_DIB27_CLKB_posedge or
                  Tviol_DIB28_CLKB_posedge or
                  Tviol_DIB29_CLKB_posedge or
                  Tviol_DIB30_CLKB_posedge or
                  Tviol_DIB31_CLKB_posedge or
                  Tviol_DIPB0_CLKB_posedge or
                  Tviol_DIPB1_CLKB_posedge or
                  Tviol_DIPB2_CLKB_posedge or
                  Tviol_DIPB3_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S36",
                       InstanceName => ramb16_s2_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S2_S36",
                       InstanceName => ramb16_s2_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S36",
                       InstanceName => ramb16_s2_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S2_S36",
                       InstanceName => ramb16_s2_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S36",
                       InstanceName => ramb16_s2_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S2_S36",
                       InstanceName => ramb16_s2_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S2_S36",
                 InstanceName => ramb16_s2_s36'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(1 downto 0);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
              DOPB_zd := DIPB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S36",
                       InstanceName => ramb16_s2_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S2_S36",
                       InstanceName => ramb16_s2_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                DOPB_zd := MEMP(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S36",
                       InstanceName => ramb16_s2_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S2_S36",
                       InstanceName => ramb16_s2_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S2_S36",
                     InstanceName => ramb16_s2_s36'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S2_S36",
                       InstanceName => ramb16_s2_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
            DOPB_zd := MEMP(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S2_S36",
                 InstanceName => ramb16_s2_s36'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(31 downto 0);
          DOPB_zd := SRVA_B(35 downto 32);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
      MEMP(ADDRESS_B) := DIPB_ipd;
    end if;

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);
    DOB_zd(8)  := ViolationB xor DOB_zd(8);
    DOB_zd(9)  := ViolationB xor DOB_zd(9);
    DOB_zd(10)  := ViolationB xor DOB_zd(10);
    DOB_zd(11)  := ViolationB xor DOB_zd(11);
    DOB_zd(12)  := ViolationB xor DOB_zd(12);
    DOB_zd(13)  := ViolationB xor DOB_zd(13);
    DOB_zd(14)  := ViolationB xor DOB_zd(14);
    DOB_zd(15)  := ViolationB xor DOB_zd(15);
    DOB_zd(16)  := ViolationB xor DOB_zd(16);
    DOB_zd(17)  := ViolationB xor DOB_zd(17);
    DOB_zd(18)  := ViolationB xor DOB_zd(18);
    DOB_zd(19)  := ViolationB xor DOB_zd(19);
    DOB_zd(20)  := ViolationB xor DOB_zd(20);
    DOB_zd(21)  := ViolationB xor DOB_zd(21);
    DOB_zd(22)  := ViolationB xor DOB_zd(22);
    DOB_zd(23)  := ViolationB xor DOB_zd(23);
    DOB_zd(24)  := ViolationB xor DOB_zd(24);
    DOB_zd(25)  := ViolationB xor DOB_zd(25);
    DOB_zd(26)  := ViolationB xor DOB_zd(26);
    DOB_zd(27)  := ViolationB xor DOB_zd(27);
    DOB_zd(28)  := ViolationB xor DOB_zd(28);
    DOB_zd(29)  := ViolationB xor DOB_zd(29);
    DOB_zd(30)  := ViolationB xor DOB_zd(30);
    DOB_zd(31)  := ViolationB xor DOB_zd(31);
    DOPB_zd(0) := ViolationB xor DOPB_zd(0);
    DOPB_zd(1) := ViolationB xor DOPB_zd(1);
    DOPB_zd(2) := ViolationB xor DOPB_zd(2);
    DOPB_zd(3) := ViolationB xor DOPB_zd(3);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(8),
      GlitchData    => DOB_GlitchData8,
      OutSignalName => "DOB(8)",
      OutTemp       => DOB_zd(8),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(9),
      GlitchData    => DOB_GlitchData9,
      OutSignalName => "DOB(9)",
      OutTemp       => DOB_zd(9),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(10),
      GlitchData    => DOB_GlitchData10,
      OutSignalName => "DOB(10)",
      OutTemp       => DOB_zd(10),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(11),
      GlitchData    => DOB_GlitchData11,
      OutSignalName => "DOB(11)",
      OutTemp       => DOB_zd(11),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(12),
      GlitchData    => DOB_GlitchData12,
      OutSignalName => "DOB(12)",
      OutTemp       => DOB_zd(12),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(13),
      GlitchData    => DOB_GlitchData13,
      OutSignalName => "DOB(13)",
      OutTemp       => DOB_zd(13),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(14),
      GlitchData    => DOB_GlitchData14,
      OutSignalName => "DOB(14)",
      OutTemp       => DOB_zd(14),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(15),
      GlitchData    => DOB_GlitchData15,
      OutSignalName => "DOB(15)",
      OutTemp       => DOB_zd(15),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(16),
      GlitchData    => DOB_GlitchData16,
      OutSignalName => "DOB(16)",
      OutTemp       => DOB_zd(16),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(16), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(17),
      GlitchData    => DOB_GlitchData17,
      OutSignalName => "DOB(17)",
      OutTemp       => DOB_zd(17),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(17), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(18),
      GlitchData    => DOB_GlitchData18,
      OutSignalName => "DOB(18)",
      OutTemp       => DOB_zd(18),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(18), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(19),
      GlitchData    => DOB_GlitchData19,
      OutSignalName => "DOB(19)",
      OutTemp       => DOB_zd(19),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(19), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(20),
      GlitchData    => DOB_GlitchData20,
      OutSignalName => "DOB(20)",
      OutTemp       => DOB_zd(20),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(20), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(21),
      GlitchData    => DOB_GlitchData21,
      OutSignalName => "DOB(21)",
      OutTemp       => DOB_zd(21),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(21), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(22),
      GlitchData    => DOB_GlitchData22,
      OutSignalName => "DOB(22)",
      OutTemp       => DOB_zd(22),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(22), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(23),
      GlitchData    => DOB_GlitchData23,
      OutSignalName => "DOB(23)",
      OutTemp       => DOB_zd(23),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(23), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(24),
      GlitchData    => DOB_GlitchData24,
      OutSignalName => "DOB(24)",
      OutTemp       => DOB_zd(24),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(24), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(25),
      GlitchData    => DOB_GlitchData25,
      OutSignalName => "DOB(25)",
      OutTemp       => DOB_zd(25),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(25), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(26),
      GlitchData    => DOB_GlitchData26,
      OutSignalName => "DOB(26)",
      OutTemp       => DOB_zd(26),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(26), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(27),
      GlitchData    => DOB_GlitchData27,
      OutSignalName => "DOB(27)",
      OutTemp       => DOB_zd(27),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(27), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(28),
      GlitchData    => DOB_GlitchData28,
      OutSignalName => "DOB(28)",
      OutTemp       => DOB_zd(28),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(28), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(29),
      GlitchData    => DOB_GlitchData29,
      OutSignalName => "DOB(29)",
      OutTemp       => DOB_zd(29),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(29), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(30),
      GlitchData    => DOB_GlitchData30,
      OutSignalName => "DOB(30)",
      OutTemp       => DOB_zd(30),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(30), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(31),
      GlitchData    => DOB_GlitchData31,
      OutSignalName => "DOB(31)",
      OutTemp       => DOB_zd(31),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(31), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(0),
      GlitchData    => DOPB_GlitchData0,
      OutSignalName => "DOPB(0)",
      OutTemp       => DOPB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(1),
      GlitchData    => DOPB_GlitchData1,
      OutSignalName => "DOPB(1)",
      OutTemp       => DOPB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(2),
      GlitchData    => DOPB_GlitchData2,
      OutSignalName => "DOPB(2)",
      OutTemp       => DOPB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(3),
      GlitchData    => DOPB_GlitchData3,
      OutSignalName => "DOPB(3)",
      OutTemp       => DOPB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S2_S36_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S2_S4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s2_s4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S2_S4 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(12 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(11 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";


    INIT_A : bit_vector := X"0";
    INIT_B : bit_vector := X"0";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"0";
    SRVAL_B : bit_vector := X"0";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(1 downto 0);
    DOB  : out std_logic_vector(3 downto 0);

    ADDRA : in std_logic_vector(12 downto 0);
    ADDRB : in std_logic_vector(11 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(1 downto 0);
    DIB   : in std_logic_vector(3 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S2_S4 : entity is true;
end ramb16_s2_s4;

architecture RAMB16_S2_S4_V of RAMB16_S2_S4 is
  attribute VITAL_LEVEL0 of
    RAMB16_S2_S4_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(12 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(1 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(11 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(3 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 8192;
  constant length_b : integer := 4096;
  constant width_a : integer := 2;
  constant width_b : integer := 4;  

  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 12 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 1 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 11 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 3 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB11_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);

    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (1 downto 0)              := "00";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (3 downto 0)              := "0000";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (1 downto 0)              := "00";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (3 downto 0)              := "0000";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(1 downto 0) := INI_A(1 downto 0);
    variable DOB_zd  : std_logic_vector(3 downto 0) := INI_B(3 downto 0);

    variable ADDRA_ipd_sampled : std_logic_vector(12 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S2_S4",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 2) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(1 downto 0)                      := INI_A_UNBOUND(1 downto 0);

        for I in INI_A_UNBOUND'high downto 2 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  2 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S2_S4",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 2,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 2) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S2_S4",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 2,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 2) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 4) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(3 downto 0)                      := INI_B_UNBOUND(3 downto 0);

        for I in INI_B_UNBOUND'high downto 4 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  4 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S2_S4",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 4,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 4) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S2_S4",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 4,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 4) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 2) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(1 downto 0)                       := SRVA_A_UNBOUND(1 downto 0);

        for I in SRVA_A_UNBOUND'high downto 2 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  2 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S2_S4",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 2,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 2) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S2_S4",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 2,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 2) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 4) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(3 downto 0)                       := SRVA_B_UNBOUND(3 downto 0);

        for I in SRVA_B_UNBOUND'high downto 4 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  4 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S2_S4",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 4,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 4) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S2_S4",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 4,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 4) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(1 downto 0) := INI_A(1 downto 0);
      DOB_zd(3 downto 0) := INI_B(3 downto 0);
      DOA  <= DOA_zd;
      DOB  <= DOB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S2_S4",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S2_S4",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA10_CLKA_posedge,
        TimingData     => Tmkr_ADDRA10_CLKA_posedge,
        TestSignal     => ADDRA_ipd(10),
        TestSignalName => "ADDRA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(10),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(10),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA11_CLKA_posedge,
        TimingData     => Tmkr_ADDRA11_CLKA_posedge,
        TestSignal     => ADDRA_ipd(11),
        TestSignalName => "ADDRA(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(11),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(11),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(11),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(11),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB9_CLKB_posedge,
        TimingData     => Tmkr_ADDRB9_CLKB_posedge,
        TestSignal     => ADDRB_ipd(9),
        TestSignalName => "ADDRB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(9),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(9),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB10_CLKB_posedge,
        TimingData     => Tmkr_ADDRB10_CLKB_posedge,
        TestSignal     => ADDRB_ipd(10),
        TestSignalName => "ADDRB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(10),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(10),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_ADDRA11_CLKA_posedge or
                  Tviol_ADDRA12_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_ADDRB10_CLKB_posedge or
                  Tviol_ADDRB11_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S4",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S4",
                       InstanceName => ramb16_s2_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S2_S4",
                       InstanceName => ramb16_s2_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S4",
                       InstanceName => ramb16_s2_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S2_S4",
                       InstanceName => ramb16_s2_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S4",
                       InstanceName => ramb16_s2_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S2_S4",
                       InstanceName => ramb16_s2_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S2_S4",
                 InstanceName => ramb16_s2_s4'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(1 downto 0);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S4",
                       InstanceName => ramb16_s2_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S2_S4",
                       InstanceName => ramb16_s2_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S4",
                       InstanceName => ramb16_s2_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S2_S4",
                       InstanceName => ramb16_s2_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S2_S4",
                     InstanceName => ramb16_s2_s4'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S2_S4",
                       InstanceName => ramb16_s2_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S2_S4",
                 InstanceName => ramb16_s2_s4'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(3 downto 0);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
    end if;

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S2_S4_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S2_S9.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s2_s9 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S2_S9 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(12 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(10 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPB  : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOPB : VitalDelayArrayType01(0 downto 0)  := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    tsetup_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(12 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    thold_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"0";
    INIT_B : bit_vector := X"000";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"0";
    SRVAL_B : bit_vector := X"000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(1 downto 0);
    DOB  : out std_logic_vector(7 downto 0);
    DOPB : out std_logic_vector(0 downto 0);

    ADDRA : in std_logic_vector(12 downto 0);
    ADDRB : in std_logic_vector(10 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(1 downto 0);
    DIB   : in std_logic_vector(7 downto 0);
    DIPB  : in std_logic_vector(0 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S2_S9 : entity is true;
end ramb16_s2_s9;

architecture RAMB16_S2_S9_V of RAMB16_S2_S9 is
  attribute VITAL_LEVEL0 of
    RAMB16_S2_S9_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(12 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(1 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(10 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(7 downto 0) := (others => 'X');
  signal DIPB_ipd  : std_logic_vector(0 downto 0)  := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 8192;
  constant length_b : integer := 2048;
  constant width_a : integer := 2;
  constant width_b : integer := 8;  

  constant parity_width_b : integer := 1;  
  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);
  type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

  function slv_to_two_D_parity_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_parity_array_type is
    variable two_D_parity_array : two_D_parity_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_parity_array(i) := intermediate; 
    end loop;
    return two_D_parity_array;
  end;        
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 12 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 1 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 10 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 7 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    DIPB_DELAY  : for i in 0 downto 0 generate
      VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i));
    end generate DIPB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIPB0_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB0_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;
    variable DOPB_GlitchData0 : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) &
                                                       To_StdLogicVector(INITP_06) &
                                                       To_StdLogicVector(INITP_05) &
                                                       To_StdLogicVector(INITP_04) &
                                                       To_StdLogicVector(INITP_03) &
                                                       To_StdLogicVector(INITP_02) &
                                                       To_StdLogicVector(INITP_01) &
                                                       To_StdLogicVector(INITP_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);
    variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv);        


    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable DOPB_OV_LSB       : integer := 0;
    variable DOPB_OV_MSB       : integer := 0;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (1 downto 0)              := "00";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (8 downto 0)              := "000000000";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (1 downto 0)              := "00";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (8 downto 0)              := "000000000";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(1 downto 0) := INI_A(1 downto 0);
    variable DOB_zd  : std_logic_vector(7 downto 0) := INI_B(7 downto 0);
    variable DOPB_zd : std_logic_vector(0 downto 0)  := INI_B(8 downto 8);

    variable ADDRA_ipd_sampled : std_logic_vector(12 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S2_S9",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 2) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(1 downto 0)                      := INI_A_UNBOUND(1 downto 0);

        for I in INI_A_UNBOUND'high downto 2 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  2 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S2_S9",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 2,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 2) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S2_S9",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 2,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 2) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 9) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(8 downto 0)                      := INI_B_UNBOUND(8 downto 0);

        for I in INI_B_UNBOUND'high downto 9 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  9 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S2_S9",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 9,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 9) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S2_S9",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 9,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 9) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 2) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(1 downto 0)                       := SRVA_A_UNBOUND(1 downto 0);

        for I in SRVA_A_UNBOUND'high downto 2 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  2 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S2_S9",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 2,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 2) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S2_S9",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 2,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 2) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 9) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(8 downto 0)                       := SRVA_B_UNBOUND(8 downto 0);

        for I in SRVA_B_UNBOUND'high downto 9 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  9 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S2_S9",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 9,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 9) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S2_S9",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 9,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 9) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(1 downto 0) := INI_A(1 downto 0);
      DOB_zd(7 downto 0) := INI_B(7 downto 0);
      DOPB_zd(0 downto 0) := INI_B(8 downto 8);
      DOA  <= DOA_zd;
      DOB  <= DOB_zd;
      DOPB <= DOPB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S2_S9",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S2_S9",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA10_CLKA_posedge,
        TimingData     => Tmkr_ADDRA10_CLKA_posedge,
        TestSignal     => ADDRA_ipd(10),
        TestSignalName => "ADDRA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(10),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(10),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA11_CLKA_posedge,
        TimingData     => Tmkr_ADDRA11_CLKA_posedge,
        TestSignal     => ADDRA_ipd(11),
        TestSignalName => "ADDRA(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(11),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(11),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(11),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(11),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB9_CLKB_posedge,
        TimingData     => Tmkr_ADDRB9_CLKB_posedge,
        TestSignal     => ADDRB_ipd(9),
        TestSignalName => "ADDRB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(9),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(9),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_ADDRA11_CLKA_posedge or
                  Tviol_ADDRA12_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_ADDRB10_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_DIPB0_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S2_S9",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S9",
                       InstanceName => ramb16_s2_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S2_S9",
                       InstanceName => ramb16_s2_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S9",
                       InstanceName => ramb16_s2_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S2_S9",
                       InstanceName => ramb16_s2_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S9",
                       InstanceName => ramb16_s2_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S2_S9",
                       InstanceName => ramb16_s2_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S2_S9",
                 InstanceName => ramb16_s2_s9'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(1 downto 0);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
              DOPB_zd := DIPB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S9",
                       InstanceName => ramb16_s2_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S2_S9",
                       InstanceName => ramb16_s2_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                DOPB_zd := MEMP(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S2_S9",
                       InstanceName => ramb16_s2_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S2_S9",
                       InstanceName => ramb16_s2_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S2_S9",
                     InstanceName => ramb16_s2_s9'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S2_S9",
                       InstanceName => ramb16_s2_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
            DOPB_zd := MEMP(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S2_S9",
                 InstanceName => ramb16_s2_s9'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(7 downto 0);
          DOPB_zd := SRVA_B(8 downto 8);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
      MEMP(ADDRESS_B) := DIPB_ipd;
    end if;

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);
    DOPB_zd(0) := ViolationB xor DOPB_zd(0);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(0),
      GlitchData    => DOPB_GlitchData0,
      OutSignalName => "DOPB(0)",
      OutTemp       => DOPB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S2_S9_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb16_s36.vhd,v 1.8 2005/10/07 18:35:24 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Single Port Block RAM
-- /___/   /\     Filename : RAMB16_S36.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:52 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    09/26/05 - Fixed CR# 216846. INIT and SRVAL attributes length check and adjustment.
-- END Revision

----- CELL RAMB16_S36 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S36 is

  generic (
    INIT : bit_vector := X"000000000";
    SRVAL : bit_vector := X"000000000";
    WRITE_MODE : string := "WRITE_FIRST";
    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
    );

  port (
    DO : out STD_LOGIC_VECTOR (31 downto 0);
    DOP : out STD_LOGIC_VECTOR (3 downto 0);
    
    ADDR : in STD_LOGIC_VECTOR (8 downto 0);
    CLK : in STD_ULOGIC;
    DI : in STD_LOGIC_VECTOR (31 downto 0);
    DIP : in STD_LOGIC_VECTOR (3 downto 0);
    EN : in STD_ULOGIC;
    SSR : in STD_ULOGIC;
    WE : in STD_ULOGIC
    );
end RAMB16_S36;

architecture RAMB16_S36_V of RAMB16_S36 is
  constant length : integer := 512;
  constant width : integer := 32;

  constant parity_width : integer := 4;
  
  type Two_D_array_type is array ((length -  1) downto 0) of std_logic_vector((width - 1) downto 0);
  type Two_D_parity_array_type is array ((length -  1) downto 0) of std_logic_vector((parity_width - 1) downto 0);    

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

  function slv_to_two_D_parity_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_parity_array_type is
    variable two_D_parity_array : two_D_parity_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_parity_array(i) := intermediate; 
    end loop;
    return two_D_parity_array;
  end;      
begin
  VITALBehavior : process  
    variable address : integer;
    variable valid_addr : boolean := FALSE;
    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F & INIT_3E & INIT_3D & INIT_3C &
                                                                             INIT_3B & INIT_3A & INIT_39 & INIT_38 &
                                                                             INIT_37 & INIT_36 & INIT_35 & INIT_34 &
                                                                             INIT_33 & INIT_32 & INIT_31 & INIT_30 &
                                                                             INIT_2F & INIT_2E & INIT_2D & INIT_2C &
                                                                             INIT_2B & INIT_2A & INIT_29 & INIT_28 &
                                                                             INIT_27 & INIT_26 & INIT_25 & INIT_24 &
                                                                             INIT_23 & INIT_22 & INIT_21 & INIT_20 &
                                                                             INIT_1F & INIT_1E & INIT_1D & INIT_1C &
                                                                             INIT_1B & INIT_1A & INIT_19 & INIT_18 &
                                                                             INIT_17 & INIT_16 & INIT_15 & INIT_14 &
                                                                             INIT_13 & INIT_12 & INIT_11 & INIT_10 &
                                                                             INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                             INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                             INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                             INIT_03 & INIT_02 & INIT_01 & INIT_00);

    variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07 & INITP_06 & INITP_05 & INITP_04 &
                                                                              INITP_03 & INITP_02 & INITP_01 & INITP_00);    
    variable mem : Two_D_array_type := slv_to_two_D_array(length, width, mem_slv);
    variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length, parity_width, memp_slv);    

    variable wr_mode : integer := 0;    
    variable first_time : boolean := true;

    variable INIT_reg         : std_logic_vector (35 downto 0) := "000000000000000000000000000000000000";
    variable SRVAL_reg         : std_logic_vector (35 downto 0) := "000000000000000000000000000000000000";
    
  begin
    if (first_time) then
      if ((WRITE_MODE = "write_first") or (WRITE_MODE = "WRITE_FIRST")) then
        wr_mode := 0;
      elsif ((WRITE_MODE = "read_first") or (WRITE_MODE = "READ_FIRST")) then
        wr_mode := 1;
      elsif ((WRITE_MODE = "no_change") or (WRITE_MODE = "NO_CHANGE")) then
        wr_mode := 2;
      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Error ",
           GenericName          => " WRITE_MODE ",
           EntityName           => "/RAMB16_S36",
           GenericValue         => WRITE_MODE,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => error
           );
      end if;
      if (INIT'length > 36) then
        INIT_reg(35 downto 0) := To_StdLogicVector(INIT)(35 downto 0);
      else
        INIT_reg(INIT'length-1 downto 0) := To_StdLogicVector(INIT);
      end if;
      
      DO <= INIT_reg(31 downto 0);
      DOP <= INIT_reg(35 downto 32);

      if (SRVAL'length > 36) then
        SRVAL_reg(35 downto 0) := To_StdLogicVector(SRVAL)(35 downto 0);
      else
        SRVAL_reg(SRVAL'length-1 downto 0) := To_StdLogicVector(SRVAL);
      end if;
      
      first_time := false;
    end if;
      
    valid_addr := addr_is_valid(addr);
    
    if (valid_addr) then
      address := slv_to_int(addr);
    end if;
    
    if (rising_edge(CLK)) then
      if (EN = '1') then
        if (SSR = '1') then
          DO <= SRVAL_reg(31 downto 0) after 100 ps;
          DOP <= SRVAL_reg(35 downto 32) after 100 ps;          
        else    
          if (WE = '1') then
            if (wr_mode = 0) then
              DO <= DI after 100 ps;
              DOP <= DIP after 100 ps;              
            elsif (wr_mode = 1) then
              DO <= mem(address) after 100 ps;
              DOP <= memp(address) after 100 ps;                
            end if;
          else 
            if (valid_addr) then
              DO <= mem(address) after 100 ps;
              DOP <= memp(address) after 100 ps;              
            end if;
          end if;
        end if;
        if (WE = '1') then
          if (valid_addr) then
            mem(address) := DI;
            memp(address) := DIP;            
          end if;
        end if;  
      end if;
    end if;
    wait on CLK;    
  end process VITALBehavior;

end RAMB16_S36_V;


-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S36_S36.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s36_s36 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S36_S36 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(8 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPA  : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(8 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPB  : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(31 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKA_DOPA : VitalDelayArrayType01(3 downto 0)  := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    tsetup_DIPA_CLKA_negedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    tsetup_DIPA_CLKA_posedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    tsetup_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    tsetup_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    thold_DIPA_CLKA_negedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    thold_DIPA_CLKA_posedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    thold_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    thold_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"000000000";
    INIT_B : bit_vector := X"000000000";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"000000000";
    SRVAL_B : bit_vector := X"000000000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(31 downto 0);
    DOB  : out std_logic_vector(31 downto 0);
    DOPA : out std_logic_vector(3 downto 0);
    DOPB : out std_logic_vector(3 downto 0);

    ADDRA : in std_logic_vector(8 downto 0);
    ADDRB : in std_logic_vector(8 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(31 downto 0);
    DIB   : in std_logic_vector(31 downto 0);
    DIPA  : in std_logic_vector(3 downto 0);
    DIPB  : in std_logic_vector(3 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S36_S36 : entity is true;
end ramb16_s36_s36;

architecture RAMB16_S36_S36_V of RAMB16_S36_S36 is
  attribute VITAL_LEVEL0 of
    RAMB16_S36_S36_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(8 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(31 downto 0) := (others => 'X');
  signal DIPA_ipd  : std_logic_vector(3 downto 0)  := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(8 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(31 downto 0) := (others => 'X');
  signal DIPB_ipd  : std_logic_vector(3 downto 0)  := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 512;
  constant length_b : integer := 512;
  constant width_a : integer := 32;
  constant width_b : integer := 32;  

  constant parity_width_a : integer := 4;
  constant parity_width_b : integer := 4;  
  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);
  type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

  function slv_to_two_D_parity_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_parity_array_type is
    variable two_D_parity_array : two_D_parity_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_parity_array(i) := intermediate; 
    end loop;
    return two_D_parity_array;
  end;        
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 8 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 31 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    DIPA_DELAY  : for i in 3 downto 0 generate
      VitalWireDelay (DIPA_ipd(i), DIPA(i), tipd_DIPA(i));
    end generate DIPA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 8 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 31 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    DIPB_DELAY  : for i in 3 downto 0 generate
      VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i));
    end generate DIPB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA2_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA3_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA4_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA5_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA6_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA7_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA8_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA9_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA10_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA11_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA12_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA13_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA14_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA15_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA16_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA17_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA18_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA19_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA20_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA21_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA22_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA23_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA24_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA25_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA26_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA27_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA28_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA29_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA30_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA31_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIPA0_CLKA_posedge  : std_ulogic := '0';
    variable Tviol_DIPA1_CLKA_posedge  : std_ulogic := '0';
    variable Tviol_DIPA2_CLKA_posedge  : std_ulogic := '0';
    variable Tviol_DIPA3_CLKA_posedge  : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB8_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB9_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB10_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB11_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB12_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB13_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB14_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB15_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB16_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB17_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB18_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB19_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB20_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB21_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB22_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB23_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB24_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB25_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB26_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB27_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB28_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB29_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB30_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB31_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIPB0_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB1_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB2_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB3_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA2_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA3_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA4_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA5_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA6_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA7_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA8_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA9_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA10_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA11_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA12_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA13_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA14_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA15_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA16_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA17_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA18_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA19_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA20_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA21_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA22_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA23_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA24_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA25_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA26_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA27_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA28_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA29_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA30_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA31_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPA0_CLKA_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPA1_CLKA_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPA2_CLKA_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPA3_CLKA_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB8_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB9_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB10_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB11_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB12_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB13_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB14_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB15_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB16_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB17_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB18_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB19_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB20_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB21_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB22_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB23_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB24_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB25_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB26_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB27_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB28_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB29_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB30_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB31_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB0_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB1_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB2_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB3_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;
    variable DOA_GlitchData2  : VitalGlitchDataType;
    variable DOA_GlitchData3  : VitalGlitchDataType;
    variable DOA_GlitchData4  : VitalGlitchDataType;
    variable DOA_GlitchData5  : VitalGlitchDataType;
    variable DOA_GlitchData6  : VitalGlitchDataType;
    variable DOA_GlitchData7  : VitalGlitchDataType;
    variable DOA_GlitchData8  : VitalGlitchDataType;
    variable DOA_GlitchData9  : VitalGlitchDataType;
    variable DOA_GlitchData10  : VitalGlitchDataType;
    variable DOA_GlitchData11  : VitalGlitchDataType;
    variable DOA_GlitchData12  : VitalGlitchDataType;
    variable DOA_GlitchData13  : VitalGlitchDataType;
    variable DOA_GlitchData14  : VitalGlitchDataType;
    variable DOA_GlitchData15  : VitalGlitchDataType;
    variable DOA_GlitchData16  : VitalGlitchDataType;
    variable DOA_GlitchData17  : VitalGlitchDataType;
    variable DOA_GlitchData18  : VitalGlitchDataType;
    variable DOA_GlitchData19  : VitalGlitchDataType;
    variable DOA_GlitchData20  : VitalGlitchDataType;
    variable DOA_GlitchData21  : VitalGlitchDataType;
    variable DOA_GlitchData22  : VitalGlitchDataType;
    variable DOA_GlitchData23  : VitalGlitchDataType;
    variable DOA_GlitchData24  : VitalGlitchDataType;
    variable DOA_GlitchData25  : VitalGlitchDataType;
    variable DOA_GlitchData26  : VitalGlitchDataType;
    variable DOA_GlitchData27  : VitalGlitchDataType;
    variable DOA_GlitchData28  : VitalGlitchDataType;
    variable DOA_GlitchData29  : VitalGlitchDataType;
    variable DOA_GlitchData30  : VitalGlitchDataType;
    variable DOA_GlitchData31  : VitalGlitchDataType;
    variable DOPA_GlitchData0 : VitalGlitchDataType;
    variable DOPA_GlitchData1 : VitalGlitchDataType;
    variable DOPA_GlitchData2 : VitalGlitchDataType;
    variable DOPA_GlitchData3 : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;
    variable DOB_GlitchData8  : VitalGlitchDataType;
    variable DOB_GlitchData9  : VitalGlitchDataType;
    variable DOB_GlitchData10  : VitalGlitchDataType;
    variable DOB_GlitchData11  : VitalGlitchDataType;
    variable DOB_GlitchData12  : VitalGlitchDataType;
    variable DOB_GlitchData13  : VitalGlitchDataType;
    variable DOB_GlitchData14  : VitalGlitchDataType;
    variable DOB_GlitchData15  : VitalGlitchDataType;
    variable DOB_GlitchData16  : VitalGlitchDataType;
    variable DOB_GlitchData17  : VitalGlitchDataType;
    variable DOB_GlitchData18  : VitalGlitchDataType;
    variable DOB_GlitchData19  : VitalGlitchDataType;
    variable DOB_GlitchData20  : VitalGlitchDataType;
    variable DOB_GlitchData21  : VitalGlitchDataType;
    variable DOB_GlitchData22  : VitalGlitchDataType;
    variable DOB_GlitchData23  : VitalGlitchDataType;
    variable DOB_GlitchData24  : VitalGlitchDataType;
    variable DOB_GlitchData25  : VitalGlitchDataType;
    variable DOB_GlitchData26  : VitalGlitchDataType;
    variable DOB_GlitchData27  : VitalGlitchDataType;
    variable DOB_GlitchData28  : VitalGlitchDataType;
    variable DOB_GlitchData29  : VitalGlitchDataType;
    variable DOB_GlitchData30  : VitalGlitchDataType;
    variable DOB_GlitchData31  : VitalGlitchDataType;
    variable DOPB_GlitchData0 : VitalGlitchDataType;
    variable DOPB_GlitchData1 : VitalGlitchDataType;
    variable DOPB_GlitchData2 : VitalGlitchDataType;
    variable DOPB_GlitchData3 : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) &
                                                       To_StdLogicVector(INITP_06) &
                                                       To_StdLogicVector(INITP_05) &
                                                       To_StdLogicVector(INITP_04) &
                                                       To_StdLogicVector(INITP_03) &
                                                       To_StdLogicVector(INITP_02) &
                                                       To_StdLogicVector(INITP_01) &
                                                       To_StdLogicVector(INITP_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);
    variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv);        


    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable DOPA_OV_LSB       : integer := 0;
    variable DOPA_OV_MSB       : integer := 3;
    variable DOPB_OV_LSB       : integer := 0;
    variable DOPB_OV_MSB       : integer := 3;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (35 downto 0)              := "000000000000000000000000000000000000";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (35 downto 0)              := "000000000000000000000000000000000000";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (35 downto 0)              := "000000000000000000000000000000000000";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (35 downto 0)              := "000000000000000000000000000000000000";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(31 downto 0) := INI_A(31 downto 0);
    variable DOB_zd  : std_logic_vector(31 downto 0) := INI_B(31 downto 0);
    variable DOPA_zd : std_logic_vector(3 downto 0)  := INI_A(35 downto 32);
    variable DOPB_zd : std_logic_vector(3 downto 0)  := INI_B(35 downto 32);

    variable ADDRA_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S36_S36",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 36) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(35 downto 0)                      := INI_A_UNBOUND(35 downto 0);

        for I in INI_A_UNBOUND'high downto 36 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  36 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S36_S36",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 36,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 36) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S36_S36",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 36,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 36) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 36) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(35 downto 0)                      := INI_B_UNBOUND(35 downto 0);

        for I in INI_B_UNBOUND'high downto 36 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  36 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S36_S36",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 36,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 36) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S36_S36",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 36,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 36) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 36) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(35 downto 0)                       := SRVA_A_UNBOUND(35 downto 0);

        for I in SRVA_A_UNBOUND'high downto 36 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  36 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S36_S36",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 36,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 36) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S36_S36",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 36,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 36) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 36) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(35 downto 0)                       := SRVA_B_UNBOUND(35 downto 0);

        for I in SRVA_B_UNBOUND'high downto 36 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  36 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S36_S36",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 36,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 36) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S36_S36",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 36,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 36) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(31 downto 0) := INI_A(31 downto 0);
      DOB_zd(31 downto 0) := INI_B(31 downto 0);
      DOPA_zd(3 downto 0) := INI_A(35 downto 32);
      DOPB_zd(3 downto 0) := INI_B(35 downto 32);
      DOA  <= DOA_zd;
      DOPA <= DOPA_zd;
      DOB  <= DOB_zd;
      DOPB <= DOPB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S36_S36",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S36_S36",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPA0_CLKA_posedge,
        TimingData     => Tmkr_DIPA0_CLKA_posedge,
        TestSignal     => DIPA_ipd(0),
        TestSignalName => "DIPA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIPA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIPA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIPA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPA1_CLKA_posedge,
        TimingData     => Tmkr_DIPA1_CLKA_posedge,
        TestSignal     => DIPA_ipd(1),
        TestSignalName => "DIPA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_DIPA_CLKA_negedge_posedge(1),
        HoldLow        => thold_DIPA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_DIPA_CLKA_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPA2_CLKA_posedge,
        TimingData     => Tmkr_DIPA2_CLKA_posedge,
        TestSignal     => DIPA_ipd(2),
        TestSignalName => "DIPA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_DIPA_CLKA_negedge_posedge(2),
        HoldLow        => thold_DIPA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_DIPA_CLKA_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA1_CLKA_posedge,
        TimingData     => Tmkr_DIA1_CLKA_posedge,
        TestSignal     => DIA_ipd(1),
        TestSignalName => "DIA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(1),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA2_CLKA_posedge,
        TimingData     => Tmkr_DIA2_CLKA_posedge,
        TestSignal     => DIA_ipd(2),
        TestSignalName => "DIA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(2),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA3_CLKA_posedge,
        TimingData     => Tmkr_DIA3_CLKA_posedge,
        TestSignal     => DIA_ipd(3),
        TestSignalName => "DIA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(3),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(3),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA4_CLKA_posedge,
        TimingData     => Tmkr_DIA4_CLKA_posedge,
        TestSignal     => DIA_ipd(4),
        TestSignalName => "DIA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(4),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(4),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA5_CLKA_posedge,
        TimingData     => Tmkr_DIA5_CLKA_posedge,
        TestSignal     => DIA_ipd(5),
        TestSignalName => "DIA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(5),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(5),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA6_CLKA_posedge,
        TimingData     => Tmkr_DIA6_CLKA_posedge,
        TestSignal     => DIA_ipd(6),
        TestSignalName => "DIA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(6),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(6),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA7_CLKA_posedge,
        TimingData     => Tmkr_DIA7_CLKA_posedge,
        TestSignal     => DIA_ipd(7),
        TestSignalName => "DIA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(7),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(7),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA8_CLKA_posedge,
        TimingData     => Tmkr_DIA8_CLKA_posedge,
        TestSignal     => DIA_ipd(8),
        TestSignalName => "DIA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(8),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(8),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA9_CLKA_posedge,
        TimingData     => Tmkr_DIA9_CLKA_posedge,
        TestSignal     => DIA_ipd(9),
        TestSignalName => "DIA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(9),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(9),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA10_CLKA_posedge,
        TimingData     => Tmkr_DIA10_CLKA_posedge,
        TestSignal     => DIA_ipd(10),
        TestSignalName => "DIA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(10),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(10),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA11_CLKA_posedge,
        TimingData     => Tmkr_DIA11_CLKA_posedge,
        TestSignal     => DIA_ipd(11),
        TestSignalName => "DIA(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(11),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(11),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(11),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(11),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA12_CLKA_posedge,
        TimingData     => Tmkr_DIA12_CLKA_posedge,
        TestSignal     => DIA_ipd(12),
        TestSignalName => "DIA(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(12),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(12),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(12),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(12),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA13_CLKA_posedge,
        TimingData     => Tmkr_DIA13_CLKA_posedge,
        TestSignal     => DIA_ipd(13),
        TestSignalName => "DIA(13)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(13),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(13),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(13),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(13),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA14_CLKA_posedge,
        TimingData     => Tmkr_DIA14_CLKA_posedge,
        TestSignal     => DIA_ipd(14),
        TestSignalName => "DIA(14)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(14),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(14),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(14),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(14),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA15_CLKA_posedge,
        TimingData     => Tmkr_DIA15_CLKA_posedge,
        TestSignal     => DIA_ipd(15),
        TestSignalName => "DIA(15)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(15),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(15),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(15),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(15),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA16_CLKA_posedge,
        TimingData     => Tmkr_DIA16_CLKA_posedge,
        TestSignal     => DIA_ipd(16),
        TestSignalName => "DIA(16)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(16),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(16),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(16),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(16),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA17_CLKA_posedge,
        TimingData     => Tmkr_DIA17_CLKA_posedge,
        TestSignal     => DIA_ipd(17),
        TestSignalName => "DIA(17)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(17),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(17),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(17),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(17),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA18_CLKA_posedge,
        TimingData     => Tmkr_DIA18_CLKA_posedge,
        TestSignal     => DIA_ipd(18),
        TestSignalName => "DIA(18)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(18),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(18),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(18),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(18),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA19_CLKA_posedge,
        TimingData     => Tmkr_DIA19_CLKA_posedge,
        TestSignal     => DIA_ipd(19),
        TestSignalName => "DIA(19)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(19),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(19),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(19),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(19),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA20_CLKA_posedge,
        TimingData     => Tmkr_DIA20_CLKA_posedge,
        TestSignal     => DIA_ipd(20),
        TestSignalName => "DIA(20)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(20),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(20),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(20),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(20),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA21_CLKA_posedge,
        TimingData     => Tmkr_DIA21_CLKA_posedge,
        TestSignal     => DIA_ipd(21),
        TestSignalName => "DIA(21)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(21),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(21),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(21),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(21),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA22_CLKA_posedge,
        TimingData     => Tmkr_DIA22_CLKA_posedge,
        TestSignal     => DIA_ipd(22),
        TestSignalName => "DIA(22)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(22),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(22),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(22),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(22),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA23_CLKA_posedge,
        TimingData     => Tmkr_DIA23_CLKA_posedge,
        TestSignal     => DIA_ipd(23),
        TestSignalName => "DIA(23)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(23),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(23),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(23),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(23),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA24_CLKA_posedge,
        TimingData     => Tmkr_DIA24_CLKA_posedge,
        TestSignal     => DIA_ipd(24),
        TestSignalName => "DIA(24)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(24),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(24),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(24),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(24),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA25_CLKA_posedge,
        TimingData     => Tmkr_DIA25_CLKA_posedge,
        TestSignal     => DIA_ipd(25),
        TestSignalName => "DIA(25)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(25),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(25),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(25),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(25),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA26_CLKA_posedge,
        TimingData     => Tmkr_DIA26_CLKA_posedge,
        TestSignal     => DIA_ipd(26),
        TestSignalName => "DIA(26)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(26),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(26),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(26),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(26),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA27_CLKA_posedge,
        TimingData     => Tmkr_DIA27_CLKA_posedge,
        TestSignal     => DIA_ipd(27),
        TestSignalName => "DIA(27)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(27),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(27),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(27),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(27),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA28_CLKA_posedge,
        TimingData     => Tmkr_DIA28_CLKA_posedge,
        TestSignal     => DIA_ipd(28),
        TestSignalName => "DIA(28)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(28),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(28),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(28),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(28),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA29_CLKA_posedge,
        TimingData     => Tmkr_DIA29_CLKA_posedge,
        TestSignal     => DIA_ipd(29),
        TestSignalName => "DIA(29)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(29),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(29),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(29),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(29),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA30_CLKA_posedge,
        TimingData     => Tmkr_DIA30_CLKA_posedge,
        TestSignal     => DIA_ipd(30),
        TestSignalName => "DIA(30)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(30),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(30),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(30),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(30),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB0_CLKB_posedge,
        TimingData     => Tmkr_DIPB0_CLKB_posedge,
        TestSignal     => DIPB_ipd(0),
        TestSignalName => "DIPB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB1_CLKB_posedge,
        TimingData     => Tmkr_DIPB1_CLKB_posedge,
        TestSignal     => DIPB_ipd(1),
        TestSignalName => "DIPB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB2_CLKB_posedge,
        TimingData     => Tmkr_DIPB2_CLKB_posedge,
        TestSignal     => DIPB_ipd(2),
        TestSignalName => "DIPB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB7_CLKB_posedge,
        TimingData     => Tmkr_DIB7_CLKB_posedge,
        TestSignal     => DIB_ipd(7),
        TestSignalName => "DIB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(7),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(7),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB8_CLKB_posedge,
        TimingData     => Tmkr_DIB8_CLKB_posedge,
        TestSignal     => DIB_ipd(8),
        TestSignalName => "DIB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(8),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(8),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB9_CLKB_posedge,
        TimingData     => Tmkr_DIB9_CLKB_posedge,
        TestSignal     => DIB_ipd(9),
        TestSignalName => "DIB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(9),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(9),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB10_CLKB_posedge,
        TimingData     => Tmkr_DIB10_CLKB_posedge,
        TestSignal     => DIB_ipd(10),
        TestSignalName => "DIB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(10),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(10),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB11_CLKB_posedge,
        TimingData     => Tmkr_DIB11_CLKB_posedge,
        TestSignal     => DIB_ipd(11),
        TestSignalName => "DIB(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(11),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(11),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(11),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(11),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB12_CLKB_posedge,
        TimingData     => Tmkr_DIB12_CLKB_posedge,
        TestSignal     => DIB_ipd(12),
        TestSignalName => "DIB(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(12),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(12),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(12),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(12),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB13_CLKB_posedge,
        TimingData     => Tmkr_DIB13_CLKB_posedge,
        TestSignal     => DIB_ipd(13),
        TestSignalName => "DIB(13)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(13),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(13),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(13),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(13),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB14_CLKB_posedge,
        TimingData     => Tmkr_DIB14_CLKB_posedge,
        TestSignal     => DIB_ipd(14),
        TestSignalName => "DIB(14)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(14),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(14),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(14),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(14),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB15_CLKB_posedge,
        TimingData     => Tmkr_DIB15_CLKB_posedge,
        TestSignal     => DIB_ipd(15),
        TestSignalName => "DIB(15)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(15),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(15),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(15),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(15),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB16_CLKB_posedge,
        TimingData     => Tmkr_DIB16_CLKB_posedge,
        TestSignal     => DIB_ipd(16),
        TestSignalName => "DIB(16)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(16),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(16),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(16),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(16),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB17_CLKB_posedge,
        TimingData     => Tmkr_DIB17_CLKB_posedge,
        TestSignal     => DIB_ipd(17),
        TestSignalName => "DIB(17)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(17),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(17),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(17),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(17),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB18_CLKB_posedge,
        TimingData     => Tmkr_DIB18_CLKB_posedge,
        TestSignal     => DIB_ipd(18),
        TestSignalName => "DIB(18)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(18),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(18),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(18),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(18),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB19_CLKB_posedge,
        TimingData     => Tmkr_DIB19_CLKB_posedge,
        TestSignal     => DIB_ipd(19),
        TestSignalName => "DIB(19)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(19),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(19),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(19),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(19),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB20_CLKB_posedge,
        TimingData     => Tmkr_DIB20_CLKB_posedge,
        TestSignal     => DIB_ipd(20),
        TestSignalName => "DIB(20)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(20),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(20),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(20),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(20),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB21_CLKB_posedge,
        TimingData     => Tmkr_DIB21_CLKB_posedge,
        TestSignal     => DIB_ipd(21),
        TestSignalName => "DIB(21)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(21),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(21),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(21),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(21),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB22_CLKB_posedge,
        TimingData     => Tmkr_DIB22_CLKB_posedge,
        TestSignal     => DIB_ipd(22),
        TestSignalName => "DIB(22)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(22),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(22),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(22),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(22),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB23_CLKB_posedge,
        TimingData     => Tmkr_DIB23_CLKB_posedge,
        TestSignal     => DIB_ipd(23),
        TestSignalName => "DIB(23)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(23),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(23),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(23),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(23),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB24_CLKB_posedge,
        TimingData     => Tmkr_DIB24_CLKB_posedge,
        TestSignal     => DIB_ipd(24),
        TestSignalName => "DIB(24)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(24),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(24),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(24),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(24),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB25_CLKB_posedge,
        TimingData     => Tmkr_DIB25_CLKB_posedge,
        TestSignal     => DIB_ipd(25),
        TestSignalName => "DIB(25)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(25),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(25),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(25),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(25),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB26_CLKB_posedge,
        TimingData     => Tmkr_DIB26_CLKB_posedge,
        TestSignal     => DIB_ipd(26),
        TestSignalName => "DIB(26)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(26),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(26),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(26),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(26),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB27_CLKB_posedge,
        TimingData     => Tmkr_DIB27_CLKB_posedge,
        TestSignal     => DIB_ipd(27),
        TestSignalName => "DIB(27)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(27),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(27),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(27),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(27),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB28_CLKB_posedge,
        TimingData     => Tmkr_DIB28_CLKB_posedge,
        TestSignal     => DIB_ipd(28),
        TestSignalName => "DIB(28)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(28),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(28),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(28),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(28),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB29_CLKB_posedge,
        TimingData     => Tmkr_DIB29_CLKB_posedge,
        TestSignal     => DIB_ipd(29),
        TestSignalName => "DIB(29)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(29),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(29),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(29),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(29),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB30_CLKB_posedge,
        TimingData     => Tmkr_DIB30_CLKB_posedge,
        TestSignal     => DIB_ipd(30),
        TestSignalName => "DIB(30)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(30),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(30),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(30),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(30),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_DIA2_CLKA_posedge or
                  Tviol_DIA3_CLKA_posedge or
                  Tviol_DIA4_CLKA_posedge or
                  Tviol_DIA5_CLKA_posedge or
                  Tviol_DIA6_CLKA_posedge or
                  Tviol_DIA7_CLKA_posedge or
                  Tviol_DIA8_CLKA_posedge or
                  Tviol_DIA9_CLKA_posedge or
                  Tviol_DIA10_CLKA_posedge or
                  Tviol_DIA11_CLKA_posedge or
                  Tviol_DIA12_CLKA_posedge or
                  Tviol_DIA13_CLKA_posedge or
                  Tviol_DIA14_CLKA_posedge or
                  Tviol_DIA15_CLKA_posedge or
                  Tviol_DIA16_CLKA_posedge or
                  Tviol_DIA17_CLKA_posedge or
                  Tviol_DIA18_CLKA_posedge or
                  Tviol_DIA19_CLKA_posedge or
                  Tviol_DIA20_CLKA_posedge or
                  Tviol_DIA21_CLKA_posedge or
                  Tviol_DIA22_CLKA_posedge or
                  Tviol_DIA23_CLKA_posedge or
                  Tviol_DIA24_CLKA_posedge or
                  Tviol_DIA25_CLKA_posedge or
                  Tviol_DIA26_CLKA_posedge or
                  Tviol_DIA27_CLKA_posedge or
                  Tviol_DIA28_CLKA_posedge or
                  Tviol_DIA29_CLKA_posedge or
                  Tviol_DIA30_CLKA_posedge or
                  Tviol_DIA31_CLKA_posedge or
                  Tviol_DIPA0_CLKA_posedge or
                  Tviol_DIPA1_CLKA_posedge or
                  Tviol_DIPA2_CLKA_posedge or
                  Tviol_DIPA3_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_DIB8_CLKB_posedge or
                  Tviol_DIB9_CLKB_posedge or
                  Tviol_DIB10_CLKB_posedge or
                  Tviol_DIB11_CLKB_posedge or
                  Tviol_DIB12_CLKB_posedge or
                  Tviol_DIB13_CLKB_posedge or
                  Tviol_DIB14_CLKB_posedge or
                  Tviol_DIB15_CLKB_posedge or
                  Tviol_DIB16_CLKB_posedge or
                  Tviol_DIB17_CLKB_posedge or
                  Tviol_DIB18_CLKB_posedge or
                  Tviol_DIB19_CLKB_posedge or
                  Tviol_DIB20_CLKB_posedge or
                  Tviol_DIB21_CLKB_posedge or
                  Tviol_DIB22_CLKB_posedge or
                  Tviol_DIB23_CLKB_posedge or
                  Tviol_DIB24_CLKB_posedge or
                  Tviol_DIB25_CLKB_posedge or
                  Tviol_DIB26_CLKB_posedge or
                  Tviol_DIB27_CLKB_posedge or
                  Tviol_DIB28_CLKB_posedge or
                  Tviol_DIB29_CLKB_posedge or
                  Tviol_DIB30_CLKB_posedge or
                  Tviol_DIB31_CLKB_posedge or
                  Tviol_DIPB0_CLKB_posedge or
                  Tviol_DIPB1_CLKB_posedge or
                  Tviol_DIPB2_CLKB_posedge or
                  Tviol_DIPB3_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
      addr_overlap (address_a, address_b, parity_width_a, parity_width_b, has_overlap_p, olpp_lsb, olpp_msb, dopa_ov_lsb, dopa_ov_msb, dopb_ov_lsb, dopb_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S36_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;
              DOPA_zd := DIPA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S36_S36",
                       InstanceName => ramb16_s36_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');    

                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                      DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S36_S36",
                       InstanceName => ramb16_s36_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;                                      
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                    DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB)                   := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                    MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S36_S36",
                       InstanceName => ramb16_s36_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                      DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S36_S36",
                       InstanceName => ramb16_s36_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                    MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB)                   := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S36_S36",
                       InstanceName => ramb16_s36_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                      DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S36_S36",
                       InstanceName => ramb16_s36_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                    DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB)                   := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                    MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
            DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S36_S36",
                 InstanceName => ramb16_s36_s36'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
              DOPA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(31 downto 0);
          DOPA_zd := SRVA_A(35 downto 32);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
              DOPB_zd := DIPB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S36_S36",
                       InstanceName => ramb16_s36_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                   MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                   DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                     DOPA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S36_S36",
                       InstanceName => ramb16_s36_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                DOPB_zd := MEMP(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S36_S36",
                       InstanceName => ramb16_s36_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                      DOPA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S36_S36",
                       InstanceName => ramb16_s36_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S36_S36",
                     InstanceName => ramb16_s36_s36'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S36_S36",
                       InstanceName => ramb16_s36_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
            DOPB_zd := MEMP(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S36_S36",
                 InstanceName => ramb16_s36_s36'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
              DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(31 downto 0);
          DOPB_zd := SRVA_B(35 downto 32);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
      MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
      MEMP(ADDRESS_B) := DIPB_ipd;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);
    DOA_zd(1)  := ViolationA xor DOA_zd(1);
    DOA_zd(2)  := ViolationA xor DOA_zd(2);
    DOA_zd(3)  := ViolationA xor DOA_zd(3);
    DOA_zd(4)  := ViolationA xor DOA_zd(4);
    DOA_zd(5)  := ViolationA xor DOA_zd(5);
    DOA_zd(6)  := ViolationA xor DOA_zd(6);
    DOA_zd(7)  := ViolationA xor DOA_zd(7);
    DOA_zd(8)  := ViolationA xor DOA_zd(8);
    DOA_zd(9)  := ViolationA xor DOA_zd(9);
    DOA_zd(10)  := ViolationA xor DOA_zd(10);
    DOA_zd(11)  := ViolationA xor DOA_zd(11);
    DOA_zd(12)  := ViolationA xor DOA_zd(12);
    DOA_zd(13)  := ViolationA xor DOA_zd(13);
    DOA_zd(14)  := ViolationA xor DOA_zd(14);
    DOA_zd(15)  := ViolationA xor DOA_zd(15);
    DOA_zd(16)  := ViolationA xor DOA_zd(16);
    DOA_zd(17)  := ViolationA xor DOA_zd(17);
    DOA_zd(18)  := ViolationA xor DOA_zd(18);
    DOA_zd(19)  := ViolationA xor DOA_zd(19);
    DOA_zd(20)  := ViolationA xor DOA_zd(20);
    DOA_zd(21)  := ViolationA xor DOA_zd(21);
    DOA_zd(22)  := ViolationA xor DOA_zd(22);
    DOA_zd(23)  := ViolationA xor DOA_zd(23);
    DOA_zd(24)  := ViolationA xor DOA_zd(24);
    DOA_zd(25)  := ViolationA xor DOA_zd(25);
    DOA_zd(26)  := ViolationA xor DOA_zd(26);
    DOA_zd(27)  := ViolationA xor DOA_zd(27);
    DOA_zd(28)  := ViolationA xor DOA_zd(28);
    DOA_zd(29)  := ViolationA xor DOA_zd(29);
    DOA_zd(30)  := ViolationA xor DOA_zd(30);
    DOA_zd(31)  := ViolationA xor DOA_zd(31);
    DOPA_zd(0) := ViolationA xor DOPA_zd(0);
    DOPA_zd(1) := ViolationA xor DOPA_zd(1);
    DOPA_zd(2) := ViolationA xor DOPA_zd(2);
    DOPA_zd(3) := ViolationA xor DOPA_zd(3);
    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);
    DOB_zd(8)  := ViolationB xor DOB_zd(8);
    DOB_zd(9)  := ViolationB xor DOB_zd(9);
    DOB_zd(10)  := ViolationB xor DOB_zd(10);
    DOB_zd(11)  := ViolationB xor DOB_zd(11);
    DOB_zd(12)  := ViolationB xor DOB_zd(12);
    DOB_zd(13)  := ViolationB xor DOB_zd(13);
    DOB_zd(14)  := ViolationB xor DOB_zd(14);
    DOB_zd(15)  := ViolationB xor DOB_zd(15);
    DOB_zd(16)  := ViolationB xor DOB_zd(16);
    DOB_zd(17)  := ViolationB xor DOB_zd(17);
    DOB_zd(18)  := ViolationB xor DOB_zd(18);
    DOB_zd(19)  := ViolationB xor DOB_zd(19);
    DOB_zd(20)  := ViolationB xor DOB_zd(20);
    DOB_zd(21)  := ViolationB xor DOB_zd(21);
    DOB_zd(22)  := ViolationB xor DOB_zd(22);
    DOB_zd(23)  := ViolationB xor DOB_zd(23);
    DOB_zd(24)  := ViolationB xor DOB_zd(24);
    DOB_zd(25)  := ViolationB xor DOB_zd(25);
    DOB_zd(26)  := ViolationB xor DOB_zd(26);
    DOB_zd(27)  := ViolationB xor DOB_zd(27);
    DOB_zd(28)  := ViolationB xor DOB_zd(28);
    DOB_zd(29)  := ViolationB xor DOB_zd(29);
    DOB_zd(30)  := ViolationB xor DOB_zd(30);
    DOB_zd(31)  := ViolationB xor DOB_zd(31);
    DOPB_zd(0) := ViolationB xor DOPB_zd(0);
    DOPB_zd(1) := ViolationB xor DOPB_zd(1);
    DOPB_zd(2) := ViolationB xor DOPB_zd(2);
    DOPB_zd(3) := ViolationB xor DOPB_zd(3);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(2),
      GlitchData    => DOA_GlitchData2,
      OutSignalName => "DOA(2)",
      OutTemp       => DOA_zd(2),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(3),
      GlitchData    => DOA_GlitchData3,
      OutSignalName => "DOA(3)",
      OutTemp       => DOA_zd(3),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(4),
      GlitchData    => DOA_GlitchData4,
      OutSignalName => "DOA(4)",
      OutTemp       => DOA_zd(4),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(5),
      GlitchData    => DOA_GlitchData5,
      OutSignalName => "DOA(5)",
      OutTemp       => DOA_zd(5),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(6),
      GlitchData    => DOA_GlitchData6,
      OutSignalName => "DOA(6)",
      OutTemp       => DOA_zd(6),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(7),
      GlitchData    => DOA_GlitchData7,
      OutSignalName => "DOA(7)",
      OutTemp       => DOA_zd(7),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(8),
      GlitchData    => DOA_GlitchData8,
      OutSignalName => "DOA(8)",
      OutTemp       => DOA_zd(8),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(8), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(9),
      GlitchData    => DOA_GlitchData9,
      OutSignalName => "DOA(9)",
      OutTemp       => DOA_zd(9),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(9), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(10),
      GlitchData    => DOA_GlitchData10,
      OutSignalName => "DOA(10)",
      OutTemp       => DOA_zd(10),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(10), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(11),
      GlitchData    => DOA_GlitchData11,
      OutSignalName => "DOA(11)",
      OutTemp       => DOA_zd(11),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(11), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(12),
      GlitchData    => DOA_GlitchData12,
      OutSignalName => "DOA(12)",
      OutTemp       => DOA_zd(12),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(12), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(13),
      GlitchData    => DOA_GlitchData13,
      OutSignalName => "DOA(13)",
      OutTemp       => DOA_zd(13),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(13), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(14),
      GlitchData    => DOA_GlitchData14,
      OutSignalName => "DOA(14)",
      OutTemp       => DOA_zd(14),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(14), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(15),
      GlitchData    => DOA_GlitchData15,
      OutSignalName => "DOA(15)",
      OutTemp       => DOA_zd(15),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(15), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(16),
      GlitchData    => DOA_GlitchData16,
      OutSignalName => "DOA(16)",
      OutTemp       => DOA_zd(16),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(16), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(17),
      GlitchData    => DOA_GlitchData17,
      OutSignalName => "DOA(17)",
      OutTemp       => DOA_zd(17),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(17), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(18),
      GlitchData    => DOA_GlitchData18,
      OutSignalName => "DOA(18)",
      OutTemp       => DOA_zd(18),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(18), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(19),
      GlitchData    => DOA_GlitchData19,
      OutSignalName => "DOA(19)",
      OutTemp       => DOA_zd(19),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(19), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(20),
      GlitchData    => DOA_GlitchData20,
      OutSignalName => "DOA(20)",
      OutTemp       => DOA_zd(20),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(20), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(21),
      GlitchData    => DOA_GlitchData21,
      OutSignalName => "DOA(21)",
      OutTemp       => DOA_zd(21),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(21), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(22),
      GlitchData    => DOA_GlitchData22,
      OutSignalName => "DOA(22)",
      OutTemp       => DOA_zd(22),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(22), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(23),
      GlitchData    => DOA_GlitchData23,
      OutSignalName => "DOA(23)",
      OutTemp       => DOA_zd(23),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(23), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(24),
      GlitchData    => DOA_GlitchData24,
      OutSignalName => "DOA(24)",
      OutTemp       => DOA_zd(24),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(24), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(25),
      GlitchData    => DOA_GlitchData25,
      OutSignalName => "DOA(25)",
      OutTemp       => DOA_zd(25),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(25), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(26),
      GlitchData    => DOA_GlitchData26,
      OutSignalName => "DOA(26)",
      OutTemp       => DOA_zd(26),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(26), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(27),
      GlitchData    => DOA_GlitchData27,
      OutSignalName => "DOA(27)",
      OutTemp       => DOA_zd(27),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(27), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(28),
      GlitchData    => DOA_GlitchData28,
      OutSignalName => "DOA(28)",
      OutTemp       => DOA_zd(28),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(28), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(29),
      GlitchData    => DOA_GlitchData29,
      OutSignalName => "DOA(29)",
      OutTemp       => DOA_zd(29),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(29), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(30),
      GlitchData    => DOA_GlitchData30,
      OutSignalName => "DOA(30)",
      OutTemp       => DOA_zd(30),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(30), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(31),
      GlitchData    => DOA_GlitchData31,
      OutSignalName => "DOA(31)",
      OutTemp       => DOA_zd(31),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(31), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPA(0),
      GlitchData    => DOPA_GlitchData0,
      OutSignalName => "DOPA(0)",
      OutTemp       => DOPA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPA(1),
      GlitchData    => DOPA_GlitchData1,
      OutSignalName => "DOPA(1)",
      OutTemp       => DOPA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPA(2),
      GlitchData    => DOPA_GlitchData2,
      OutSignalName => "DOPA(2)",
      OutTemp       => DOPA_zd(2),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPA(3),
      GlitchData    => DOPA_GlitchData3,
      OutSignalName => "DOPA(3)",
      OutTemp       => DOPA_zd(3),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(8),
      GlitchData    => DOB_GlitchData8,
      OutSignalName => "DOB(8)",
      OutTemp       => DOB_zd(8),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(9),
      GlitchData    => DOB_GlitchData9,
      OutSignalName => "DOB(9)",
      OutTemp       => DOB_zd(9),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(10),
      GlitchData    => DOB_GlitchData10,
      OutSignalName => "DOB(10)",
      OutTemp       => DOB_zd(10),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(11),
      GlitchData    => DOB_GlitchData11,
      OutSignalName => "DOB(11)",
      OutTemp       => DOB_zd(11),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(12),
      GlitchData    => DOB_GlitchData12,
      OutSignalName => "DOB(12)",
      OutTemp       => DOB_zd(12),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(13),
      GlitchData    => DOB_GlitchData13,
      OutSignalName => "DOB(13)",
      OutTemp       => DOB_zd(13),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(14),
      GlitchData    => DOB_GlitchData14,
      OutSignalName => "DOB(14)",
      OutTemp       => DOB_zd(14),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(15),
      GlitchData    => DOB_GlitchData15,
      OutSignalName => "DOB(15)",
      OutTemp       => DOB_zd(15),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(16),
      GlitchData    => DOB_GlitchData16,
      OutSignalName => "DOB(16)",
      OutTemp       => DOB_zd(16),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(16), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(17),
      GlitchData    => DOB_GlitchData17,
      OutSignalName => "DOB(17)",
      OutTemp       => DOB_zd(17),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(17), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(18),
      GlitchData    => DOB_GlitchData18,
      OutSignalName => "DOB(18)",
      OutTemp       => DOB_zd(18),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(18), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(19),
      GlitchData    => DOB_GlitchData19,
      OutSignalName => "DOB(19)",
      OutTemp       => DOB_zd(19),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(19), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(20),
      GlitchData    => DOB_GlitchData20,
      OutSignalName => "DOB(20)",
      OutTemp       => DOB_zd(20),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(20), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(21),
      GlitchData    => DOB_GlitchData21,
      OutSignalName => "DOB(21)",
      OutTemp       => DOB_zd(21),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(21), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(22),
      GlitchData    => DOB_GlitchData22,
      OutSignalName => "DOB(22)",
      OutTemp       => DOB_zd(22),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(22), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(23),
      GlitchData    => DOB_GlitchData23,
      OutSignalName => "DOB(23)",
      OutTemp       => DOB_zd(23),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(23), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(24),
      GlitchData    => DOB_GlitchData24,
      OutSignalName => "DOB(24)",
      OutTemp       => DOB_zd(24),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(24), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(25),
      GlitchData    => DOB_GlitchData25,
      OutSignalName => "DOB(25)",
      OutTemp       => DOB_zd(25),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(25), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(26),
      GlitchData    => DOB_GlitchData26,
      OutSignalName => "DOB(26)",
      OutTemp       => DOB_zd(26),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(26), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(27),
      GlitchData    => DOB_GlitchData27,
      OutSignalName => "DOB(27)",
      OutTemp       => DOB_zd(27),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(27), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(28),
      GlitchData    => DOB_GlitchData28,
      OutSignalName => "DOB(28)",
      OutTemp       => DOB_zd(28),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(28), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(29),
      GlitchData    => DOB_GlitchData29,
      OutSignalName => "DOB(29)",
      OutTemp       => DOB_zd(29),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(29), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(30),
      GlitchData    => DOB_GlitchData30,
      OutSignalName => "DOB(30)",
      OutTemp       => DOB_zd(30),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(30), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(31),
      GlitchData    => DOB_GlitchData31,
      OutSignalName => "DOB(31)",
      OutTemp       => DOB_zd(31),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(31), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(0),
      GlitchData    => DOPB_GlitchData0,
      OutSignalName => "DOPB(0)",
      OutTemp       => DOPB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(1),
      GlitchData    => DOPB_GlitchData1,
      OutSignalName => "DOPB(1)",
      OutTemp       => DOPB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(2),
      GlitchData    => DOPB_GlitchData2,
      OutSignalName => "DOPB(2)",
      OutTemp       => DOPB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(3),
      GlitchData    => DOPB_GlitchData3,
      OutSignalName => "DOPB(3)",
      OutTemp       => DOPB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPA_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S36_S36_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb16_s4.vhd,v 1.7 2005/10/07 18:35:24 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Single Port Block RAM
-- /___/   /\     Filename : RAMB16_S4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:52 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    09/26/05 - Fixed CR# 216846. INIT and SRVAL attributes length check and adjustment.
-- END Revision

----- CELL RAMB16_S4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S4 is

  generic (
       INIT : bit_vector   := X"0";
       SRVAL : bit_vector  := X"0";
       WRITE_MODE : string := "WRITE_FIRST";

       INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
  );

  port (
        DO     : out STD_LOGIC_VECTOR (3 downto 0);
        
        ADDR   : in STD_LOGIC_VECTOR (11 downto 0);
        CLK    : in STD_ULOGIC;        
        DI     : in STD_LOGIC_VECTOR (3 downto 0);
        EN     : in STD_ULOGIC;
        SSR    : in STD_ULOGIC;        
        WE     : in STD_ULOGIC
       ); 
end RAMB16_S4;

architecture RAMB16_S4_V of RAMB16_S4 is
  constant length : integer := 4096;
  constant width : integer := 4;

  type Two_D_array_type is array ((length -  1) downto 0) of std_logic_vector((width - 1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;      
begin
  VITALBehavior : process
    variable address : integer;
    variable valid_addr : boolean := FALSE;
    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F & INIT_3E & INIT_3D & INIT_3C &
                                                                             INIT_3B & INIT_3A & INIT_39 & INIT_38 &
                                                                             INIT_37 & INIT_36 & INIT_35 & INIT_34 &
                                                                             INIT_33 & INIT_32 & INIT_31 & INIT_30 &
                                                                             INIT_2F & INIT_2E & INIT_2D & INIT_2C &
                                                                             INIT_2B & INIT_2A & INIT_29 & INIT_28 &
                                                                             INIT_27 & INIT_26 & INIT_25 & INIT_24 &
                                                                             INIT_23 & INIT_22 & INIT_21 & INIT_20 &
                                                                             INIT_1F & INIT_1E & INIT_1D & INIT_1C &
                                                                             INIT_1B & INIT_1A & INIT_19 & INIT_18 &
                                                                             INIT_17 & INIT_16 & INIT_15 & INIT_14 &
                                                                             INIT_13 & INIT_12 & INIT_11 & INIT_10 &
                                                                             INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                             INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                             INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                             INIT_03 & INIT_02 & INIT_01 & INIT_00);
    variable mem : Two_D_array_type := slv_to_two_D_array(length, width, mem_slv);

    variable wr_mode : integer := 0;    
    variable first_time : boolean := true;

    variable INIT_reg         : std_logic_vector (3 downto 0) := "0000";
    variable SRVAL_reg         : std_logic_vector (3 downto 0) := "0000"; 
  begin
    if (first_time) then
      if ((WRITE_MODE = "write_first") or (WRITE_MODE = "WRITE_FIRST")) then
        wr_mode := 0;
      elsif ((WRITE_MODE = "read_first") or (WRITE_MODE = "READ_FIRST")) then
        wr_mode := 1;
      elsif ((WRITE_MODE = "no_change") or (WRITE_MODE = "NO_CHANGE")) then
        wr_mode := 2;
      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Error ",
           GenericName          => " WRITE_MODE ",
           EntityName           => "/RAMB16_S4",
           GenericValue         => WRITE_MODE,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => error
           );
      end if;
      if (INIT'length > 4) then
        INIT_reg(3 downto 0) := To_StdLogicVector(INIT)(3 downto 0);
      else
        INIT_reg(INIT'length-1 downto 0) := To_StdLogicVector(INIT);
      end if;      
      DO <= INIT_reg(3 downto 0);
      if (SRVAL'length > 4) then
        SRVAL_reg(3 downto 0) := To_StdLogicVector(SRVAL)(3 downto 0);
      else
        SRVAL_reg(SRVAL'length-1 downto 0) := To_StdLogicVector(SRVAL);
      end if;                  
      first_time := false;
    end if;
      
    valid_addr := addr_is_valid(addr);
    
    if (valid_addr) then
      address := slv_to_int(addr);
    end if;
    
    if (rising_edge(CLK)) then
      if (EN = '1') then
        if (SSR = '1') then
          DO <= SRVAL_reg(3 downto 0) after 100 ps;
        else    
          if (WE = '1') then
            if (wr_mode = 0) then
              DO <= DI after 100 ps;
            elsif (wr_mode = 1) then
              DO <= mem(address) after 100 ps;  
            end if;
          else 
            if (valid_addr) then
              DO <= mem(address) after 100 ps;
            end if;
          end if;
        end if;
        if (WE = '1') then
          if (valid_addr) then
            mem(address) := DI;
          end if;
        end if;  
      end if;
    end if;
    wait on CLK;        
  end process VITALBehavior;
end RAMB16_S4_V;


-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S4_S18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s4_s18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S4_S18 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(11 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(9 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPB  : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOPB : VitalDelayArrayType01(1 downto 0)  := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    tsetup_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    thold_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"0";
    INIT_B : bit_vector := X"00000";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"0";
    SRVAL_B : bit_vector := X"00000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(3 downto 0);
    DOB  : out std_logic_vector(15 downto 0);
    DOPB : out std_logic_vector(1 downto 0);

    ADDRA : in std_logic_vector(11 downto 0);
    ADDRB : in std_logic_vector(9 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(3 downto 0);
    DIB   : in std_logic_vector(15 downto 0);
    DIPB  : in std_logic_vector(1 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S4_S18 : entity is true;
end ramb16_s4_s18;

architecture RAMB16_S4_S18_V of RAMB16_S4_S18 is
  attribute VITAL_LEVEL0 of
    RAMB16_S4_S18_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(11 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(3 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(9 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(15 downto 0) := (others => 'X');
  signal DIPB_ipd  : std_logic_vector(1 downto 0)  := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 4096;
  constant length_b : integer := 1024;
  constant width_a : integer := 4;
  constant width_b : integer := 16;  

  constant parity_width_b : integer := 2;  
  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);
  type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

  function slv_to_two_D_parity_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_parity_array_type is
    variable two_D_parity_array : two_D_parity_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_parity_array(i) := intermediate; 
    end loop;
    return two_D_parity_array;
  end;        
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 11 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 3 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 9 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 15 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    DIPB_DELAY  : for i in 1 downto 0 generate
      VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i));
    end generate DIPB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA2_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA3_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB8_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB9_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB10_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB11_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB12_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB13_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB14_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB15_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIPB0_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB1_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA2_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA3_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB8_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB9_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB10_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB11_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB12_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB13_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB14_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB15_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB0_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB1_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;
    variable DOA_GlitchData2  : VitalGlitchDataType;
    variable DOA_GlitchData3  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;
    variable DOB_GlitchData8  : VitalGlitchDataType;
    variable DOB_GlitchData9  : VitalGlitchDataType;
    variable DOB_GlitchData10  : VitalGlitchDataType;
    variable DOB_GlitchData11  : VitalGlitchDataType;
    variable DOB_GlitchData12  : VitalGlitchDataType;
    variable DOB_GlitchData13  : VitalGlitchDataType;
    variable DOB_GlitchData14  : VitalGlitchDataType;
    variable DOB_GlitchData15  : VitalGlitchDataType;
    variable DOPB_GlitchData0 : VitalGlitchDataType;
    variable DOPB_GlitchData1 : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) &
                                                       To_StdLogicVector(INITP_06) &
                                                       To_StdLogicVector(INITP_05) &
                                                       To_StdLogicVector(INITP_04) &
                                                       To_StdLogicVector(INITP_03) &
                                                       To_StdLogicVector(INITP_02) &
                                                       To_StdLogicVector(INITP_01) &
                                                       To_StdLogicVector(INITP_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);
    variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv);        


    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable DOPB_OV_LSB       : integer := 0;
    variable DOPB_OV_MSB       : integer := 1;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (3 downto 0)              := "0000";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (17 downto 0)              := "000000000000000000";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (3 downto 0)              := "0000";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (17 downto 0)              := "000000000000000000";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(3 downto 0) := INI_A(3 downto 0);
    variable DOB_zd  : std_logic_vector(15 downto 0) := INI_B(15 downto 0);
    variable DOPB_zd : std_logic_vector(1 downto 0)  := INI_B(17 downto 16);

    variable ADDRA_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S4_S18",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 4) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(3 downto 0)                      := INI_A_UNBOUND(3 downto 0);

        for I in INI_A_UNBOUND'high downto 4 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  4 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S4_S18",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 4,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 4) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S4_S18",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 4,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 4) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 18) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(17 downto 0)                      := INI_B_UNBOUND(17 downto 0);

        for I in INI_B_UNBOUND'high downto 18 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  18 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S4_S18",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 18,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 18) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S4_S18",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 18,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 18) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 4) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(3 downto 0)                       := SRVA_A_UNBOUND(3 downto 0);

        for I in SRVA_A_UNBOUND'high downto 4 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  4 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S4_S18",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 4,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 4) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S4_S18",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 4,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 4) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 18) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(17 downto 0)                       := SRVA_B_UNBOUND(17 downto 0);

        for I in SRVA_B_UNBOUND'high downto 18 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  18 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S4_S18",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 18,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 18) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S4_S18",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 18,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 18) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(3 downto 0) := INI_A(3 downto 0);
      DOB_zd(15 downto 0) := INI_B(15 downto 0);
      DOPB_zd(1 downto 0) := INI_B(17 downto 16);
      DOA  <= DOA_zd;
      DOB  <= DOB_zd;
      DOPB <= DOPB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S4_S18",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S4_S18",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA10_CLKA_posedge,
        TimingData     => Tmkr_ADDRA10_CLKA_posedge,
        TestSignal     => ADDRA_ipd(10),
        TestSignalName => "ADDRA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(10),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(10),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA1_CLKA_posedge,
        TimingData     => Tmkr_DIA1_CLKA_posedge,
        TestSignal     => DIA_ipd(1),
        TestSignalName => "DIA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(1),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA2_CLKA_posedge,
        TimingData     => Tmkr_DIA2_CLKA_posedge,
        TestSignal     => DIA_ipd(2),
        TestSignalName => "DIA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(2),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB0_CLKB_posedge,
        TimingData     => Tmkr_DIPB0_CLKB_posedge,
        TestSignal     => DIPB_ipd(0),
        TestSignalName => "DIPB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB7_CLKB_posedge,
        TimingData     => Tmkr_DIB7_CLKB_posedge,
        TestSignal     => DIB_ipd(7),
        TestSignalName => "DIB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(7),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(7),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB8_CLKB_posedge,
        TimingData     => Tmkr_DIB8_CLKB_posedge,
        TestSignal     => DIB_ipd(8),
        TestSignalName => "DIB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(8),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(8),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB9_CLKB_posedge,
        TimingData     => Tmkr_DIB9_CLKB_posedge,
        TestSignal     => DIB_ipd(9),
        TestSignalName => "DIB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(9),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(9),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB10_CLKB_posedge,
        TimingData     => Tmkr_DIB10_CLKB_posedge,
        TestSignal     => DIB_ipd(10),
        TestSignalName => "DIB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(10),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(10),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB11_CLKB_posedge,
        TimingData     => Tmkr_DIB11_CLKB_posedge,
        TestSignal     => DIB_ipd(11),
        TestSignalName => "DIB(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(11),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(11),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(11),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(11),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB12_CLKB_posedge,
        TimingData     => Tmkr_DIB12_CLKB_posedge,
        TestSignal     => DIB_ipd(12),
        TestSignalName => "DIB(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(12),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(12),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(12),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(12),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB13_CLKB_posedge,
        TimingData     => Tmkr_DIB13_CLKB_posedge,
        TestSignal     => DIB_ipd(13),
        TestSignalName => "DIB(13)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(13),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(13),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(13),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(13),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB14_CLKB_posedge,
        TimingData     => Tmkr_DIB14_CLKB_posedge,
        TestSignal     => DIB_ipd(14),
        TestSignalName => "DIB(14)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(14),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(14),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(14),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(14),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_ADDRA11_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_DIA2_CLKA_posedge or
                  Tviol_DIA3_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_DIB8_CLKB_posedge or
                  Tviol_DIB9_CLKB_posedge or
                  Tviol_DIB10_CLKB_posedge or
                  Tviol_DIB11_CLKB_posedge or
                  Tviol_DIB12_CLKB_posedge or
                  Tviol_DIB13_CLKB_posedge or
                  Tviol_DIB14_CLKB_posedge or
                  Tviol_DIB15_CLKB_posedge or
                  Tviol_DIPB0_CLKB_posedge or
                  Tviol_DIPB1_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S18",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S4_S18",
                       InstanceName => ramb16_s4_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S4_S18",
                       InstanceName => ramb16_s4_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S4_S18",
                       InstanceName => ramb16_s4_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S4_S18",
                       InstanceName => ramb16_s4_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S4_S18",
                       InstanceName => ramb16_s4_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S4_S18",
                       InstanceName => ramb16_s4_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S4_S18",
                 InstanceName => ramb16_s4_s18'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(3 downto 0);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
              DOPB_zd := DIPB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S4_S18",
                       InstanceName => ramb16_s4_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S4_S18",
                       InstanceName => ramb16_s4_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                DOPB_zd := MEMP(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S4_S18",
                       InstanceName => ramb16_s4_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S4_S18",
                       InstanceName => ramb16_s4_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S4_S18",
                     InstanceName => ramb16_s4_s18'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S4_S18",
                       InstanceName => ramb16_s4_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
            DOPB_zd := MEMP(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S4_S18",
                 InstanceName => ramb16_s4_s18'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(15 downto 0);
          DOPB_zd := SRVA_B(17 downto 16);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
      MEMP(ADDRESS_B) := DIPB_ipd;
    end if;

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);
    DOB_zd(8)  := ViolationB xor DOB_zd(8);
    DOB_zd(9)  := ViolationB xor DOB_zd(9);
    DOB_zd(10)  := ViolationB xor DOB_zd(10);
    DOB_zd(11)  := ViolationB xor DOB_zd(11);
    DOB_zd(12)  := ViolationB xor DOB_zd(12);
    DOB_zd(13)  := ViolationB xor DOB_zd(13);
    DOB_zd(14)  := ViolationB xor DOB_zd(14);
    DOB_zd(15)  := ViolationB xor DOB_zd(15);
    DOPB_zd(0) := ViolationB xor DOPB_zd(0);
    DOPB_zd(1) := ViolationB xor DOPB_zd(1);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(2),
      GlitchData    => DOA_GlitchData2,
      OutSignalName => "DOA(2)",
      OutTemp       => DOA_zd(2),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(3),
      GlitchData    => DOA_GlitchData3,
      OutSignalName => "DOA(3)",
      OutTemp       => DOA_zd(3),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(8),
      GlitchData    => DOB_GlitchData8,
      OutSignalName => "DOB(8)",
      OutTemp       => DOB_zd(8),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(9),
      GlitchData    => DOB_GlitchData9,
      OutSignalName => "DOB(9)",
      OutTemp       => DOB_zd(9),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(10),
      GlitchData    => DOB_GlitchData10,
      OutSignalName => "DOB(10)",
      OutTemp       => DOB_zd(10),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(11),
      GlitchData    => DOB_GlitchData11,
      OutSignalName => "DOB(11)",
      OutTemp       => DOB_zd(11),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(12),
      GlitchData    => DOB_GlitchData12,
      OutSignalName => "DOB(12)",
      OutTemp       => DOB_zd(12),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(13),
      GlitchData    => DOB_GlitchData13,
      OutSignalName => "DOB(13)",
      OutTemp       => DOB_zd(13),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(14),
      GlitchData    => DOB_GlitchData14,
      OutSignalName => "DOB(14)",
      OutTemp       => DOB_zd(14),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(15),
      GlitchData    => DOB_GlitchData15,
      OutSignalName => "DOB(15)",
      OutTemp       => DOB_zd(15),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(0),
      GlitchData    => DOPB_GlitchData0,
      OutSignalName => "DOPB(0)",
      OutTemp       => DOPB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(1),
      GlitchData    => DOPB_GlitchData1,
      OutSignalName => "DOPB(1)",
      OutTemp       => DOPB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S4_S18_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S4_S36.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s4_s36 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S4_S36 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(11 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(8 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPB  : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    tsetup_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    tsetup_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    thold_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    thold_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"0";
    INIT_B : bit_vector := X"000000000";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"0";
    SRVAL_B : bit_vector := X"000000000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(3 downto 0);
    DOB  : out std_logic_vector(31 downto 0);
    DOPB : out std_logic_vector(3 downto 0);

    ADDRA : in std_logic_vector(11 downto 0);
    ADDRB : in std_logic_vector(8 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(3 downto 0);
    DIB   : in std_logic_vector(31 downto 0);
    DIPB  : in std_logic_vector(3 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S4_S36 : entity is true;
end ramb16_s4_s36;

architecture RAMB16_S4_S36_V of RAMB16_S4_S36 is
  attribute VITAL_LEVEL0 of
    RAMB16_S4_S36_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(11 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(3 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(8 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(31 downto 0) := (others => 'X');
  signal DIPB_ipd  : std_logic_vector(3 downto 0)  := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 4096;
  constant length_b : integer := 512;
  constant width_a : integer := 4;
  constant width_b : integer := 32;  

  constant parity_width_b : integer := 4;  
  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);
  type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

  function slv_to_two_D_parity_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_parity_array_type is
    variable two_D_parity_array : two_D_parity_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_parity_array(i) := intermediate; 
    end loop;
    return two_D_parity_array;
  end;        
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 11 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 3 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 8 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 31 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    DIPB_DELAY  : for i in 3 downto 0 generate
      VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i));
    end generate DIPB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA2_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA3_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB8_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB9_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB10_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB11_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB12_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB13_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB14_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB15_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB16_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB17_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB18_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB19_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB20_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB21_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB22_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB23_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB24_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB25_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB26_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB27_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB28_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB29_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB30_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB31_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIPB0_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB1_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB2_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB3_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA2_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA3_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB8_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB9_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB10_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB11_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB12_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB13_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB14_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB15_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB16_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB17_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB18_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB19_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB20_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB21_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB22_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB23_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB24_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB25_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB26_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB27_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB28_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB29_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB30_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB31_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB0_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB1_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB2_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB3_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;
    variable DOA_GlitchData2  : VitalGlitchDataType;
    variable DOA_GlitchData3  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;
    variable DOB_GlitchData8  : VitalGlitchDataType;
    variable DOB_GlitchData9  : VitalGlitchDataType;
    variable DOB_GlitchData10  : VitalGlitchDataType;
    variable DOB_GlitchData11  : VitalGlitchDataType;
    variable DOB_GlitchData12  : VitalGlitchDataType;
    variable DOB_GlitchData13  : VitalGlitchDataType;
    variable DOB_GlitchData14  : VitalGlitchDataType;
    variable DOB_GlitchData15  : VitalGlitchDataType;
    variable DOB_GlitchData16  : VitalGlitchDataType;
    variable DOB_GlitchData17  : VitalGlitchDataType;
    variable DOB_GlitchData18  : VitalGlitchDataType;
    variable DOB_GlitchData19  : VitalGlitchDataType;
    variable DOB_GlitchData20  : VitalGlitchDataType;
    variable DOB_GlitchData21  : VitalGlitchDataType;
    variable DOB_GlitchData22  : VitalGlitchDataType;
    variable DOB_GlitchData23  : VitalGlitchDataType;
    variable DOB_GlitchData24  : VitalGlitchDataType;
    variable DOB_GlitchData25  : VitalGlitchDataType;
    variable DOB_GlitchData26  : VitalGlitchDataType;
    variable DOB_GlitchData27  : VitalGlitchDataType;
    variable DOB_GlitchData28  : VitalGlitchDataType;
    variable DOB_GlitchData29  : VitalGlitchDataType;
    variable DOB_GlitchData30  : VitalGlitchDataType;
    variable DOB_GlitchData31  : VitalGlitchDataType;
    variable DOPB_GlitchData0 : VitalGlitchDataType;
    variable DOPB_GlitchData1 : VitalGlitchDataType;
    variable DOPB_GlitchData2 : VitalGlitchDataType;
    variable DOPB_GlitchData3 : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) &
                                                       To_StdLogicVector(INITP_06) &
                                                       To_StdLogicVector(INITP_05) &
                                                       To_StdLogicVector(INITP_04) &
                                                       To_StdLogicVector(INITP_03) &
                                                       To_StdLogicVector(INITP_02) &
                                                       To_StdLogicVector(INITP_01) &
                                                       To_StdLogicVector(INITP_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);
    variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv);        


    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable DOPB_OV_LSB       : integer := 0;
    variable DOPB_OV_MSB       : integer := 3;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (3 downto 0)              := "0000";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (35 downto 0)              := "000000000000000000000000000000000000";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (3 downto 0)              := "0000";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (35 downto 0)              := "000000000000000000000000000000000000";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(3 downto 0) := INI_A(3 downto 0);
    variable DOB_zd  : std_logic_vector(31 downto 0) := INI_B(31 downto 0);
    variable DOPB_zd : std_logic_vector(3 downto 0)  := INI_B(35 downto 32);

    variable ADDRA_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S4_S36",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 4) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(3 downto 0)                      := INI_A_UNBOUND(3 downto 0);

        for I in INI_A_UNBOUND'high downto 4 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  4 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S4_S36",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 4,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 4) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S4_S36",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 4,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 4) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 36) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(35 downto 0)                      := INI_B_UNBOUND(35 downto 0);

        for I in INI_B_UNBOUND'high downto 36 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  36 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S4_S36",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 36,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 36) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S4_S36",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 36,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 36) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 4) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(3 downto 0)                       := SRVA_A_UNBOUND(3 downto 0);

        for I in SRVA_A_UNBOUND'high downto 4 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  4 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S4_S36",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 4,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 4) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S4_S36",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 4,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 4) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 36) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(35 downto 0)                       := SRVA_B_UNBOUND(35 downto 0);

        for I in SRVA_B_UNBOUND'high downto 36 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  36 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S4_S36",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 36,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 36) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S4_S36",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 36,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 36) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(3 downto 0) := INI_A(3 downto 0);
      DOB_zd(31 downto 0) := INI_B(31 downto 0);
      DOPB_zd(3 downto 0) := INI_B(35 downto 32);
      DOA  <= DOA_zd;
      DOB  <= DOB_zd;
      DOPB <= DOPB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S4_S36",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S4_S36",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA10_CLKA_posedge,
        TimingData     => Tmkr_ADDRA10_CLKA_posedge,
        TestSignal     => ADDRA_ipd(10),
        TestSignalName => "ADDRA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(10),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(10),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA1_CLKA_posedge,
        TimingData     => Tmkr_DIA1_CLKA_posedge,
        TestSignal     => DIA_ipd(1),
        TestSignalName => "DIA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(1),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA2_CLKA_posedge,
        TimingData     => Tmkr_DIA2_CLKA_posedge,
        TestSignal     => DIA_ipd(2),
        TestSignalName => "DIA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(2),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB0_CLKB_posedge,
        TimingData     => Tmkr_DIPB0_CLKB_posedge,
        TestSignal     => DIPB_ipd(0),
        TestSignalName => "DIPB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB1_CLKB_posedge,
        TimingData     => Tmkr_DIPB1_CLKB_posedge,
        TestSignal     => DIPB_ipd(1),
        TestSignalName => "DIPB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB2_CLKB_posedge,
        TimingData     => Tmkr_DIPB2_CLKB_posedge,
        TestSignal     => DIPB_ipd(2),
        TestSignalName => "DIPB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB7_CLKB_posedge,
        TimingData     => Tmkr_DIB7_CLKB_posedge,
        TestSignal     => DIB_ipd(7),
        TestSignalName => "DIB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(7),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(7),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB8_CLKB_posedge,
        TimingData     => Tmkr_DIB8_CLKB_posedge,
        TestSignal     => DIB_ipd(8),
        TestSignalName => "DIB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(8),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(8),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB9_CLKB_posedge,
        TimingData     => Tmkr_DIB9_CLKB_posedge,
        TestSignal     => DIB_ipd(9),
        TestSignalName => "DIB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(9),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(9),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB10_CLKB_posedge,
        TimingData     => Tmkr_DIB10_CLKB_posedge,
        TestSignal     => DIB_ipd(10),
        TestSignalName => "DIB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(10),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(10),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB11_CLKB_posedge,
        TimingData     => Tmkr_DIB11_CLKB_posedge,
        TestSignal     => DIB_ipd(11),
        TestSignalName => "DIB(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(11),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(11),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(11),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(11),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB12_CLKB_posedge,
        TimingData     => Tmkr_DIB12_CLKB_posedge,
        TestSignal     => DIB_ipd(12),
        TestSignalName => "DIB(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(12),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(12),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(12),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(12),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB13_CLKB_posedge,
        TimingData     => Tmkr_DIB13_CLKB_posedge,
        TestSignal     => DIB_ipd(13),
        TestSignalName => "DIB(13)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(13),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(13),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(13),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(13),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB14_CLKB_posedge,
        TimingData     => Tmkr_DIB14_CLKB_posedge,
        TestSignal     => DIB_ipd(14),
        TestSignalName => "DIB(14)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(14),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(14),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(14),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(14),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB15_CLKB_posedge,
        TimingData     => Tmkr_DIB15_CLKB_posedge,
        TestSignal     => DIB_ipd(15),
        TestSignalName => "DIB(15)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(15),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(15),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(15),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(15),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB16_CLKB_posedge,
        TimingData     => Tmkr_DIB16_CLKB_posedge,
        TestSignal     => DIB_ipd(16),
        TestSignalName => "DIB(16)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(16),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(16),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(16),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(16),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB17_CLKB_posedge,
        TimingData     => Tmkr_DIB17_CLKB_posedge,
        TestSignal     => DIB_ipd(17),
        TestSignalName => "DIB(17)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(17),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(17),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(17),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(17),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB18_CLKB_posedge,
        TimingData     => Tmkr_DIB18_CLKB_posedge,
        TestSignal     => DIB_ipd(18),
        TestSignalName => "DIB(18)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(18),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(18),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(18),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(18),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB19_CLKB_posedge,
        TimingData     => Tmkr_DIB19_CLKB_posedge,
        TestSignal     => DIB_ipd(19),
        TestSignalName => "DIB(19)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(19),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(19),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(19),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(19),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB20_CLKB_posedge,
        TimingData     => Tmkr_DIB20_CLKB_posedge,
        TestSignal     => DIB_ipd(20),
        TestSignalName => "DIB(20)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(20),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(20),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(20),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(20),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB21_CLKB_posedge,
        TimingData     => Tmkr_DIB21_CLKB_posedge,
        TestSignal     => DIB_ipd(21),
        TestSignalName => "DIB(21)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(21),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(21),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(21),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(21),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB22_CLKB_posedge,
        TimingData     => Tmkr_DIB22_CLKB_posedge,
        TestSignal     => DIB_ipd(22),
        TestSignalName => "DIB(22)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(22),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(22),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(22),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(22),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB23_CLKB_posedge,
        TimingData     => Tmkr_DIB23_CLKB_posedge,
        TestSignal     => DIB_ipd(23),
        TestSignalName => "DIB(23)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(23),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(23),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(23),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(23),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB24_CLKB_posedge,
        TimingData     => Tmkr_DIB24_CLKB_posedge,
        TestSignal     => DIB_ipd(24),
        TestSignalName => "DIB(24)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(24),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(24),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(24),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(24),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB25_CLKB_posedge,
        TimingData     => Tmkr_DIB25_CLKB_posedge,
        TestSignal     => DIB_ipd(25),
        TestSignalName => "DIB(25)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(25),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(25),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(25),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(25),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB26_CLKB_posedge,
        TimingData     => Tmkr_DIB26_CLKB_posedge,
        TestSignal     => DIB_ipd(26),
        TestSignalName => "DIB(26)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(26),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(26),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(26),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(26),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB27_CLKB_posedge,
        TimingData     => Tmkr_DIB27_CLKB_posedge,
        TestSignal     => DIB_ipd(27),
        TestSignalName => "DIB(27)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(27),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(27),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(27),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(27),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB28_CLKB_posedge,
        TimingData     => Tmkr_DIB28_CLKB_posedge,
        TestSignal     => DIB_ipd(28),
        TestSignalName => "DIB(28)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(28),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(28),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(28),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(28),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB29_CLKB_posedge,
        TimingData     => Tmkr_DIB29_CLKB_posedge,
        TestSignal     => DIB_ipd(29),
        TestSignalName => "DIB(29)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(29),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(29),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(29),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(29),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB30_CLKB_posedge,
        TimingData     => Tmkr_DIB30_CLKB_posedge,
        TestSignal     => DIB_ipd(30),
        TestSignalName => "DIB(30)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(30),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(30),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(30),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(30),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_ADDRA11_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_DIA2_CLKA_posedge or
                  Tviol_DIA3_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_DIB8_CLKB_posedge or
                  Tviol_DIB9_CLKB_posedge or
                  Tviol_DIB10_CLKB_posedge or
                  Tviol_DIB11_CLKB_posedge or
                  Tviol_DIB12_CLKB_posedge or
                  Tviol_DIB13_CLKB_posedge or
                  Tviol_DIB14_CLKB_posedge or
                  Tviol_DIB15_CLKB_posedge or
                  Tviol_DIB16_CLKB_posedge or
                  Tviol_DIB17_CLKB_posedge or
                  Tviol_DIB18_CLKB_posedge or
                  Tviol_DIB19_CLKB_posedge or
                  Tviol_DIB20_CLKB_posedge or
                  Tviol_DIB21_CLKB_posedge or
                  Tviol_DIB22_CLKB_posedge or
                  Tviol_DIB23_CLKB_posedge or
                  Tviol_DIB24_CLKB_posedge or
                  Tviol_DIB25_CLKB_posedge or
                  Tviol_DIB26_CLKB_posedge or
                  Tviol_DIB27_CLKB_posedge or
                  Tviol_DIB28_CLKB_posedge or
                  Tviol_DIB29_CLKB_posedge or
                  Tviol_DIB30_CLKB_posedge or
                  Tviol_DIB31_CLKB_posedge or
                  Tviol_DIPB0_CLKB_posedge or
                  Tviol_DIPB1_CLKB_posedge or
                  Tviol_DIPB2_CLKB_posedge or
                  Tviol_DIPB3_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S4_S36",
                       InstanceName => ramb16_s4_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S4_S36",
                       InstanceName => ramb16_s4_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S4_S36",
                       InstanceName => ramb16_s4_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S4_S36",
                       InstanceName => ramb16_s4_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S4_S36",
                       InstanceName => ramb16_s4_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S4_S36",
                       InstanceName => ramb16_s4_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S4_S36",
                 InstanceName => ramb16_s4_s36'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(3 downto 0);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
              DOPB_zd := DIPB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S4_S36",
                       InstanceName => ramb16_s4_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S4_S36",
                       InstanceName => ramb16_s4_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                DOPB_zd := MEMP(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S4_S36",
                       InstanceName => ramb16_s4_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S4_S36",
                       InstanceName => ramb16_s4_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S4_S36",
                     InstanceName => ramb16_s4_s36'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S4_S36",
                       InstanceName => ramb16_s4_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
            DOPB_zd := MEMP(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S4_S36",
                 InstanceName => ramb16_s4_s36'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(31 downto 0);
          DOPB_zd := SRVA_B(35 downto 32);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
      MEMP(ADDRESS_B) := DIPB_ipd;
    end if;

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);
    DOB_zd(8)  := ViolationB xor DOB_zd(8);
    DOB_zd(9)  := ViolationB xor DOB_zd(9);
    DOB_zd(10)  := ViolationB xor DOB_zd(10);
    DOB_zd(11)  := ViolationB xor DOB_zd(11);
    DOB_zd(12)  := ViolationB xor DOB_zd(12);
    DOB_zd(13)  := ViolationB xor DOB_zd(13);
    DOB_zd(14)  := ViolationB xor DOB_zd(14);
    DOB_zd(15)  := ViolationB xor DOB_zd(15);
    DOB_zd(16)  := ViolationB xor DOB_zd(16);
    DOB_zd(17)  := ViolationB xor DOB_zd(17);
    DOB_zd(18)  := ViolationB xor DOB_zd(18);
    DOB_zd(19)  := ViolationB xor DOB_zd(19);
    DOB_zd(20)  := ViolationB xor DOB_zd(20);
    DOB_zd(21)  := ViolationB xor DOB_zd(21);
    DOB_zd(22)  := ViolationB xor DOB_zd(22);
    DOB_zd(23)  := ViolationB xor DOB_zd(23);
    DOB_zd(24)  := ViolationB xor DOB_zd(24);
    DOB_zd(25)  := ViolationB xor DOB_zd(25);
    DOB_zd(26)  := ViolationB xor DOB_zd(26);
    DOB_zd(27)  := ViolationB xor DOB_zd(27);
    DOB_zd(28)  := ViolationB xor DOB_zd(28);
    DOB_zd(29)  := ViolationB xor DOB_zd(29);
    DOB_zd(30)  := ViolationB xor DOB_zd(30);
    DOB_zd(31)  := ViolationB xor DOB_zd(31);
    DOPB_zd(0) := ViolationB xor DOPB_zd(0);
    DOPB_zd(1) := ViolationB xor DOPB_zd(1);
    DOPB_zd(2) := ViolationB xor DOPB_zd(2);
    DOPB_zd(3) := ViolationB xor DOPB_zd(3);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(2),
      GlitchData    => DOA_GlitchData2,
      OutSignalName => "DOA(2)",
      OutTemp       => DOA_zd(2),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(3),
      GlitchData    => DOA_GlitchData3,
      OutSignalName => "DOA(3)",
      OutTemp       => DOA_zd(3),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(8),
      GlitchData    => DOB_GlitchData8,
      OutSignalName => "DOB(8)",
      OutTemp       => DOB_zd(8),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(9),
      GlitchData    => DOB_GlitchData9,
      OutSignalName => "DOB(9)",
      OutTemp       => DOB_zd(9),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(10),
      GlitchData    => DOB_GlitchData10,
      OutSignalName => "DOB(10)",
      OutTemp       => DOB_zd(10),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(11),
      GlitchData    => DOB_GlitchData11,
      OutSignalName => "DOB(11)",
      OutTemp       => DOB_zd(11),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(12),
      GlitchData    => DOB_GlitchData12,
      OutSignalName => "DOB(12)",
      OutTemp       => DOB_zd(12),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(13),
      GlitchData    => DOB_GlitchData13,
      OutSignalName => "DOB(13)",
      OutTemp       => DOB_zd(13),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(14),
      GlitchData    => DOB_GlitchData14,
      OutSignalName => "DOB(14)",
      OutTemp       => DOB_zd(14),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(15),
      GlitchData    => DOB_GlitchData15,
      OutSignalName => "DOB(15)",
      OutTemp       => DOB_zd(15),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(16),
      GlitchData    => DOB_GlitchData16,
      OutSignalName => "DOB(16)",
      OutTemp       => DOB_zd(16),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(16), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(17),
      GlitchData    => DOB_GlitchData17,
      OutSignalName => "DOB(17)",
      OutTemp       => DOB_zd(17),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(17), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(18),
      GlitchData    => DOB_GlitchData18,
      OutSignalName => "DOB(18)",
      OutTemp       => DOB_zd(18),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(18), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(19),
      GlitchData    => DOB_GlitchData19,
      OutSignalName => "DOB(19)",
      OutTemp       => DOB_zd(19),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(19), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(20),
      GlitchData    => DOB_GlitchData20,
      OutSignalName => "DOB(20)",
      OutTemp       => DOB_zd(20),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(20), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(21),
      GlitchData    => DOB_GlitchData21,
      OutSignalName => "DOB(21)",
      OutTemp       => DOB_zd(21),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(21), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(22),
      GlitchData    => DOB_GlitchData22,
      OutSignalName => "DOB(22)",
      OutTemp       => DOB_zd(22),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(22), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(23),
      GlitchData    => DOB_GlitchData23,
      OutSignalName => "DOB(23)",
      OutTemp       => DOB_zd(23),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(23), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(24),
      GlitchData    => DOB_GlitchData24,
      OutSignalName => "DOB(24)",
      OutTemp       => DOB_zd(24),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(24), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(25),
      GlitchData    => DOB_GlitchData25,
      OutSignalName => "DOB(25)",
      OutTemp       => DOB_zd(25),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(25), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(26),
      GlitchData    => DOB_GlitchData26,
      OutSignalName => "DOB(26)",
      OutTemp       => DOB_zd(26),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(26), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(27),
      GlitchData    => DOB_GlitchData27,
      OutSignalName => "DOB(27)",
      OutTemp       => DOB_zd(27),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(27), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(28),
      GlitchData    => DOB_GlitchData28,
      OutSignalName => "DOB(28)",
      OutTemp       => DOB_zd(28),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(28), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(29),
      GlitchData    => DOB_GlitchData29,
      OutSignalName => "DOB(29)",
      OutTemp       => DOB_zd(29),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(29), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(30),
      GlitchData    => DOB_GlitchData30,
      OutSignalName => "DOB(30)",
      OutTemp       => DOB_zd(30),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(30), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(31),
      GlitchData    => DOB_GlitchData31,
      OutSignalName => "DOB(31)",
      OutTemp       => DOB_zd(31),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(31), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(0),
      GlitchData    => DOPB_GlitchData0,
      OutSignalName => "DOPB(0)",
      OutTemp       => DOPB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(1),
      GlitchData    => DOPB_GlitchData1,
      OutSignalName => "DOPB(1)",
      OutTemp       => DOPB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(2),
      GlitchData    => DOPB_GlitchData2,
      OutSignalName => "DOPB(2)",
      OutTemp       => DOPB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(3),
      GlitchData    => DOPB_GlitchData3,
      OutSignalName => "DOPB(3)",
      OutTemp       => DOPB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S4_S36_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S4_S4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s4_s4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S4_S4 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(11 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(11 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";


    INIT_A : bit_vector := X"0";
    INIT_B : bit_vector := X"0";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"0";
    SRVAL_B : bit_vector := X"0";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(3 downto 0);
    DOB  : out std_logic_vector(3 downto 0);

    ADDRA : in std_logic_vector(11 downto 0);
    ADDRB : in std_logic_vector(11 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(3 downto 0);
    DIB   : in std_logic_vector(3 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S4_S4 : entity is true;
end ramb16_s4_s4;

architecture RAMB16_S4_S4_V of RAMB16_S4_S4 is
  attribute VITAL_LEVEL0 of
    RAMB16_S4_S4_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(11 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(3 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(11 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(3 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 4096;
  constant length_b : integer := 4096;
  constant width_a : integer := 4;
  constant width_b : integer := 4;  

  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 11 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 3 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 11 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 3 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA2_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA3_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB11_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA2_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA3_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;
    variable DOA_GlitchData2  : VitalGlitchDataType;
    variable DOA_GlitchData3  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);

    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (3 downto 0)              := "0000";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (3 downto 0)              := "0000";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (3 downto 0)              := "0000";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (3 downto 0)              := "0000";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(3 downto 0) := INI_A(3 downto 0);
    variable DOB_zd  : std_logic_vector(3 downto 0) := INI_B(3 downto 0);

    variable ADDRA_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S4_S4",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 4) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(3 downto 0)                      := INI_A_UNBOUND(3 downto 0);

        for I in INI_A_UNBOUND'high downto 4 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  4 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S4_S4",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 4,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 4) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S4_S4",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 4,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 4) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 4) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(3 downto 0)                      := INI_B_UNBOUND(3 downto 0);

        for I in INI_B_UNBOUND'high downto 4 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  4 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S4_S4",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 4,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 4) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S4_S4",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 4,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 4) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 4) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(3 downto 0)                       := SRVA_A_UNBOUND(3 downto 0);

        for I in SRVA_A_UNBOUND'high downto 4 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  4 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S4_S4",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 4,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 4) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S4_S4",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 4,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 4) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 4) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(3 downto 0)                       := SRVA_B_UNBOUND(3 downto 0);

        for I in SRVA_B_UNBOUND'high downto 4 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  4 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S4_S4",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 4,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 4) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S4_S4",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 4,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 4) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(3 downto 0) := INI_A(3 downto 0);
      DOB_zd(3 downto 0) := INI_B(3 downto 0);
      DOA  <= DOA_zd;
      DOB  <= DOB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S4_S4",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S4_S4",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA10_CLKA_posedge,
        TimingData     => Tmkr_ADDRA10_CLKA_posedge,
        TestSignal     => ADDRA_ipd(10),
        TestSignalName => "ADDRA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(10),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(10),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA1_CLKA_posedge,
        TimingData     => Tmkr_DIA1_CLKA_posedge,
        TestSignal     => DIA_ipd(1),
        TestSignalName => "DIA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(1),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA2_CLKA_posedge,
        TimingData     => Tmkr_DIA2_CLKA_posedge,
        TestSignal     => DIA_ipd(2),
        TestSignalName => "DIA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(2),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB9_CLKB_posedge,
        TimingData     => Tmkr_ADDRB9_CLKB_posedge,
        TestSignal     => ADDRB_ipd(9),
        TestSignalName => "ADDRB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(9),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(9),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB10_CLKB_posedge,
        TimingData     => Tmkr_ADDRB10_CLKB_posedge,
        TestSignal     => ADDRB_ipd(10),
        TestSignalName => "ADDRB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(10),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(10),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_ADDRA11_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_DIA2_CLKA_posedge or
                  Tviol_DIA3_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_ADDRB10_CLKB_posedge or
                  Tviol_ADDRB11_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S4",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S4_S4",
                       InstanceName => ramb16_s4_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S4_S4",
                       InstanceName => ramb16_s4_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S4_S4",
                       InstanceName => ramb16_s4_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S4_S4",
                       InstanceName => ramb16_s4_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S4_S4",
                       InstanceName => ramb16_s4_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S4_S4",
                       InstanceName => ramb16_s4_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S4_S4",
                 InstanceName => ramb16_s4_s4'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(3 downto 0);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S4_S4",
                       InstanceName => ramb16_s4_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S4_S4",
                       InstanceName => ramb16_s4_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S4_S4",
                       InstanceName => ramb16_s4_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S4_S4",
                       InstanceName => ramb16_s4_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S4_S4",
                     InstanceName => ramb16_s4_s4'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S4_S4",
                       InstanceName => ramb16_s4_s4'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S4_S4",
                 InstanceName => ramb16_s4_s4'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(3 downto 0);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
    end if;

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(2),
      GlitchData    => DOA_GlitchData2,
      OutSignalName => "DOA(2)",
      OutTemp       => DOA_zd(2),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(3),
      GlitchData    => DOA_GlitchData3,
      OutSignalName => "DOA(3)",
      OutTemp       => DOA_zd(3),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S4_S4_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S4_S9.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s4_s9 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S4_S9 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(11 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(10 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPB  : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOPB : VitalDelayArrayType01(0 downto 0)  := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    tsetup_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    thold_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"0";
    INIT_B : bit_vector := X"000";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"0";
    SRVAL_B : bit_vector := X"000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(3 downto 0);
    DOB  : out std_logic_vector(7 downto 0);
    DOPB : out std_logic_vector(0 downto 0);

    ADDRA : in std_logic_vector(11 downto 0);
    ADDRB : in std_logic_vector(10 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(3 downto 0);
    DIB   : in std_logic_vector(7 downto 0);
    DIPB  : in std_logic_vector(0 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S4_S9 : entity is true;
end ramb16_s4_s9;

architecture RAMB16_S4_S9_V of RAMB16_S4_S9 is
  attribute VITAL_LEVEL0 of
    RAMB16_S4_S9_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(11 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(3 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(10 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(7 downto 0) := (others => 'X');
  signal DIPB_ipd  : std_logic_vector(0 downto 0)  := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 4096;
  constant length_b : integer := 2048;
  constant width_a : integer := 4;
  constant width_b : integer := 8;  

  constant parity_width_b : integer := 1;  
  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);
  type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

  function slv_to_two_D_parity_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_parity_array_type is
    variable two_D_parity_array : two_D_parity_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_parity_array(i) := intermediate; 
    end loop;
    return two_D_parity_array;
  end;        
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 11 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 3 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 10 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 7 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    DIPB_DELAY  : for i in 0 downto 0 generate
      VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i));
    end generate DIPB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA2_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA3_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIPB0_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA2_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA3_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB0_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;
    variable DOA_GlitchData2  : VitalGlitchDataType;
    variable DOA_GlitchData3  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;
    variable DOPB_GlitchData0 : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) &
                                                       To_StdLogicVector(INITP_06) &
                                                       To_StdLogicVector(INITP_05) &
                                                       To_StdLogicVector(INITP_04) &
                                                       To_StdLogicVector(INITP_03) &
                                                       To_StdLogicVector(INITP_02) &
                                                       To_StdLogicVector(INITP_01) &
                                                       To_StdLogicVector(INITP_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);
    variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv);        


    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable DOPB_OV_LSB       : integer := 0;
    variable DOPB_OV_MSB       : integer := 0;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (3 downto 0)              := "0000";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (8 downto 0)              := "000000000";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (3 downto 0)              := "0000";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (8 downto 0)              := "000000000";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(3 downto 0) := INI_A(3 downto 0);
    variable DOB_zd  : std_logic_vector(7 downto 0) := INI_B(7 downto 0);
    variable DOPB_zd : std_logic_vector(0 downto 0)  := INI_B(8 downto 8);

    variable ADDRA_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S4_S9",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 4) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(3 downto 0)                      := INI_A_UNBOUND(3 downto 0);

        for I in INI_A_UNBOUND'high downto 4 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  4 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S4_S9",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 4,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 4) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S4_S9",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 4,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 4) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 9) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(8 downto 0)                      := INI_B_UNBOUND(8 downto 0);

        for I in INI_B_UNBOUND'high downto 9 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  9 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S4_S9",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 9,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 9) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S4_S9",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 9,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 9) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 4) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(3 downto 0)                       := SRVA_A_UNBOUND(3 downto 0);

        for I in SRVA_A_UNBOUND'high downto 4 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  4 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S4_S9",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 4,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 4) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S4_S9",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 4,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 4) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 9) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(8 downto 0)                       := SRVA_B_UNBOUND(8 downto 0);

        for I in SRVA_B_UNBOUND'high downto 9 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  9 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S4_S9",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 9,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 9) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S4_S9",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 9,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 9) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(3 downto 0) := INI_A(3 downto 0);
      DOB_zd(7 downto 0) := INI_B(7 downto 0);
      DOPB_zd(0 downto 0) := INI_B(8 downto 8);
      DOA  <= DOA_zd;
      DOB  <= DOB_zd;
      DOPB <= DOPB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S4_S9",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S4_S9",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA10_CLKA_posedge,
        TimingData     => Tmkr_ADDRA10_CLKA_posedge,
        TestSignal     => ADDRA_ipd(10),
        TestSignalName => "ADDRA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(10),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(10),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA1_CLKA_posedge,
        TimingData     => Tmkr_DIA1_CLKA_posedge,
        TestSignal     => DIA_ipd(1),
        TestSignalName => "DIA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(1),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA2_CLKA_posedge,
        TimingData     => Tmkr_DIA2_CLKA_posedge,
        TestSignal     => DIA_ipd(2),
        TestSignalName => "DIA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(2),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB9_CLKB_posedge,
        TimingData     => Tmkr_ADDRB9_CLKB_posedge,
        TestSignal     => ADDRB_ipd(9),
        TestSignalName => "ADDRB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(9),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(9),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_ADDRA11_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_DIA2_CLKA_posedge or
                  Tviol_DIA3_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_ADDRB10_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_DIPB0_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S4_S9",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S4_S9",
                       InstanceName => ramb16_s4_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S4_S9",
                       InstanceName => ramb16_s4_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S4_S9",
                       InstanceName => ramb16_s4_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S4_S9",
                       InstanceName => ramb16_s4_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S4_S9",
                       InstanceName => ramb16_s4_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S4_S9",
                       InstanceName => ramb16_s4_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S4_S9",
                 InstanceName => ramb16_s4_s9'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(3 downto 0);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
              DOPB_zd := DIPB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S4_S9",
                       InstanceName => ramb16_s4_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S4_S9",
                       InstanceName => ramb16_s4_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                DOPB_zd := MEMP(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S4_S9",
                       InstanceName => ramb16_s4_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S4_S9",
                       InstanceName => ramb16_s4_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S4_S9",
                     InstanceName => ramb16_s4_s9'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S4_S9",
                       InstanceName => ramb16_s4_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
            DOPB_zd := MEMP(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S4_S9",
                 InstanceName => ramb16_s4_s9'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(7 downto 0);
          DOPB_zd := SRVA_B(8 downto 8);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
      MEMP(ADDRESS_B) := DIPB_ipd;
    end if;

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);
    DOPB_zd(0) := ViolationB xor DOPB_zd(0);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(2),
      GlitchData    => DOA_GlitchData2,
      OutSignalName => "DOA(2)",
      OutTemp       => DOA_zd(2),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(3),
      GlitchData    => DOA_GlitchData3,
      OutSignalName => "DOA(3)",
      OutTemp       => DOA_zd(3),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(0),
      GlitchData    => DOPB_GlitchData0,
      OutSignalName => "DOPB(0)",
      OutTemp       => DOPB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S4_S9_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb16_s9.vhd,v 1.7 2005/10/07 18:35:24 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Single Port Block RAM
-- /___/   /\     Filename : RAMB16_S9.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:53 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    09/26/05 - Fixed CR# 216846. INIT and SRVAL attributes length check and adjustment.
-- END Revision

----- CELL RAMB16_S9 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S9 is

  generic (
       INIT  : bit_vector  := X"000";
       SRVAL : bit_vector  := X"000";
       WRITE_MODE : string := "WRITE_FIRST";

       INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
       INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"       
  );

  port (
        DO     : out STD_LOGIC_VECTOR (7 downto 0);
        DOP    : out STD_LOGIC_VECTOR (0 downto 0);
        
        ADDR   : in STD_LOGIC_VECTOR (10 downto 0);
        CLK    : in STD_ULOGIC;        
        DI     : in STD_LOGIC_VECTOR (7 downto 0);
        DIP    : in STD_LOGIC_VECTOR (0 downto 0);
        EN     : in STD_ULOGIC;
        SSR    : in STD_ULOGIC;        
        WE     : in STD_ULOGIC
       ); 
end RAMB16_S9;

architecture RAMB16_S9_V of RAMB16_S9 is
  constant length : integer := 2048;
  constant width : integer := 8;

  constant parity_width : integer := 1;
  
  type Two_D_array_type is array ((length -  1) downto 0) of std_logic_vector((width - 1) downto 0);
  type Two_D_parity_array_type is array ((length -  1) downto 0) of std_logic_vector((parity_width - 1) downto 0);    

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

  function slv_to_two_D_parity_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_parity_array_type is
    variable two_D_parity_array : two_D_parity_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_parity_array(i) := intermediate; 
    end loop;
    return two_D_parity_array;
  end;  
begin
  VITALBehavior : process
    variable address : integer;
    variable valid_addr : boolean := FALSE;
    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F & INIT_3E & INIT_3D & INIT_3C &
                                                                             INIT_3B & INIT_3A & INIT_39 & INIT_38 &
                                                                             INIT_37 & INIT_36 & INIT_35 & INIT_34 &
                                                                             INIT_33 & INIT_32 & INIT_31 & INIT_30 &
                                                                             INIT_2F & INIT_2E & INIT_2D & INIT_2C &
                                                                             INIT_2B & INIT_2A & INIT_29 & INIT_28 &
                                                                             INIT_27 & INIT_26 & INIT_25 & INIT_24 &
                                                                             INIT_23 & INIT_22 & INIT_21 & INIT_20 &
                                                                             INIT_1F & INIT_1E & INIT_1D & INIT_1C &
                                                                             INIT_1B & INIT_1A & INIT_19 & INIT_18 &
                                                                             INIT_17 & INIT_16 & INIT_15 & INIT_14 &
                                                                             INIT_13 & INIT_12 & INIT_11 & INIT_10 &
                                                                             INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                             INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                             INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                             INIT_03 & INIT_02 & INIT_01 & INIT_00);

    variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07 & INITP_06 & INITP_05 & INITP_04 &
                                                                              INITP_03 & INITP_02 & INITP_01 & INITP_00);    
    variable mem : Two_D_array_type := slv_to_two_D_array(length, width, mem_slv);
    variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length, parity_width, memp_slv);    

    variable wr_mode : integer := 0;    
    variable first_time : boolean := true;

    variable INIT_reg         : std_logic_vector (8 downto 0) := "000000000";
    variable SRVAL_reg         : std_logic_vector (8 downto 0) := "000000000";
  begin
    if (first_time) then
      if ((WRITE_MODE = "write_first") or (WRITE_MODE = "WRITE_FIRST")) then
        wr_mode := 0;
      elsif ((WRITE_MODE = "read_first") or (WRITE_MODE = "READ_FIRST")) then
        wr_mode := 1;
      elsif ((WRITE_MODE = "no_change") or (WRITE_MODE = "NO_CHANGE")) then
        wr_mode := 2;
      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Error ",
           GenericName          => " WRITE_MODE ",
           EntityName           => "/RAMB16_S9",
           GenericValue         => WRITE_MODE,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => error
           );
      end if;

      if (INIT'length > 9) then
        INIT_reg(8 downto 0) := To_StdLogicVector(INIT)(8 downto 0);
      else
        INIT_reg(INIT'length-1 downto 0) := To_StdLogicVector(INIT);
      end if;      
      DO <= INIT_reg(7 downto 0);
      DOP <= INIT_reg(8 downto 8);
      if (SRVAL'length > 9) then
        SRVAL_reg(8 downto 0) := To_StdLogicVector(SRVAL)(8 downto 0);
      else
        SRVAL_reg(SRVAL'length-1 downto 0) := To_StdLogicVector(SRVAL);
      end if;                  
      first_time := false;
    end if;
      
    valid_addr := addr_is_valid(addr);
    
    if (valid_addr) then
      address := slv_to_int(addr);
    end if;
    
    if (rising_edge(CLK)) then
      if (EN = '1') then
        if (SSR = '1') then
          DO <= SRVAL_reg(7 downto 0) after 100 ps;
          DOP <= SRVAL_reg(8 downto 8) after 100 ps;          
        else    
          if (WE = '1') then
            if (wr_mode = 0) then
              DO <= DI after 100 ps;
              DOP <= DIP after 100 ps;              
            elsif (wr_mode = 1) then
              DO <= mem(address) after 100 ps;
              DOP <= memp(address) after 100 ps;                
            end if;
          else 
            if (valid_addr) then
              DO <= mem(address) after 100 ps;
              DOP <= memp(address) after 100 ps;              
            end if;
          end if;
        end if;
        if (WE = '1') then
          if (valid_addr) then
            mem(address) := DI;
            memp(address) := DIP;            
          end if;
        end if;  
      end if;
    end if;
    wait on CLK;        
  end process VITALBehavior;
end RAMB16_S9_V;


-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S9_S18.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s9_s18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S9_S18 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(10 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPA  : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(9 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPB  : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKA_DOPA : VitalDelayArrayType01(0 downto 0)  := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOPB : VitalDelayArrayType01(1 downto 0)  := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_DIPA_CLKA_negedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    tsetup_DIPA_CLKA_posedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    tsetup_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_DIPA_CLKA_negedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    thold_DIPA_CLKA_posedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    thold_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(1 downto 0)  := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"000";
    INIT_B : bit_vector := X"00000";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"000";
    SRVAL_B : bit_vector := X"00000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(7 downto 0);
    DOB  : out std_logic_vector(15 downto 0);
    DOPA : out std_logic_vector(0 downto 0);
    DOPB : out std_logic_vector(1 downto 0);

    ADDRA : in std_logic_vector(10 downto 0);
    ADDRB : in std_logic_vector(9 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(7 downto 0);
    DIB   : in std_logic_vector(15 downto 0);
    DIPA  : in std_logic_vector(0 downto 0);
    DIPB  : in std_logic_vector(1 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S9_S18 : entity is true;
end ramb16_s9_s18;

architecture RAMB16_S9_S18_V of RAMB16_S9_S18 is
  attribute VITAL_LEVEL0 of
    RAMB16_S9_S18_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(10 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(7 downto 0) := (others => 'X');
  signal DIPA_ipd  : std_logic_vector(0 downto 0)  := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(9 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(15 downto 0) := (others => 'X');
  signal DIPB_ipd  : std_logic_vector(1 downto 0)  := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 2048;
  constant length_b : integer := 1024;
  constant width_a : integer := 8;
  constant width_b : integer := 16;  

  constant parity_width_a : integer := 1;
  constant parity_width_b : integer := 2;  
  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);
  type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

  function slv_to_two_D_parity_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_parity_array_type is
    variable two_D_parity_array : two_D_parity_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_parity_array(i) := intermediate; 
    end loop;
    return two_D_parity_array;
  end;        
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 10 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 7 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    DIPA_DELAY  : for i in 0 downto 0 generate
      VitalWireDelay (DIPA_ipd(i), DIPA(i), tipd_DIPA(i));
    end generate DIPA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 9 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 15 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    DIPB_DELAY  : for i in 1 downto 0 generate
      VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i));
    end generate DIPB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA2_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA3_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA4_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA5_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA6_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA7_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIPA0_CLKA_posedge  : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB8_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB9_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB10_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB11_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB12_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB13_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB14_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB15_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIPB0_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB1_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA2_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA3_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA4_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA5_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA6_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA7_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPA0_CLKA_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB8_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB9_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB10_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB11_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB12_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB13_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB14_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB15_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB0_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB1_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;
    variable DOA_GlitchData2  : VitalGlitchDataType;
    variable DOA_GlitchData3  : VitalGlitchDataType;
    variable DOA_GlitchData4  : VitalGlitchDataType;
    variable DOA_GlitchData5  : VitalGlitchDataType;
    variable DOA_GlitchData6  : VitalGlitchDataType;
    variable DOA_GlitchData7  : VitalGlitchDataType;
    variable DOPA_GlitchData0 : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;
    variable DOB_GlitchData8  : VitalGlitchDataType;
    variable DOB_GlitchData9  : VitalGlitchDataType;
    variable DOB_GlitchData10  : VitalGlitchDataType;
    variable DOB_GlitchData11  : VitalGlitchDataType;
    variable DOB_GlitchData12  : VitalGlitchDataType;
    variable DOB_GlitchData13  : VitalGlitchDataType;
    variable DOB_GlitchData14  : VitalGlitchDataType;
    variable DOB_GlitchData15  : VitalGlitchDataType;
    variable DOPB_GlitchData0 : VitalGlitchDataType;
    variable DOPB_GlitchData1 : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) &
                                                       To_StdLogicVector(INITP_06) &
                                                       To_StdLogicVector(INITP_05) &
                                                       To_StdLogicVector(INITP_04) &
                                                       To_StdLogicVector(INITP_03) &
                                                       To_StdLogicVector(INITP_02) &
                                                       To_StdLogicVector(INITP_01) &
                                                       To_StdLogicVector(INITP_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);
    variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv);        


    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable DOPA_OV_LSB       : integer := 0;
    variable DOPA_OV_MSB       : integer := 0;
    variable DOPB_OV_LSB       : integer := 0;
    variable DOPB_OV_MSB       : integer := 1;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (8 downto 0)              := "000000000";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (17 downto 0)              := "000000000000000000";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (8 downto 0)              := "000000000";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (17 downto 0)              := "000000000000000000";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(7 downto 0) := INI_A(7 downto 0);
    variable DOB_zd  : std_logic_vector(15 downto 0) := INI_B(15 downto 0);
    variable DOPA_zd : std_logic_vector(0 downto 0)  := INI_A(8 downto 8);
    variable DOPB_zd : std_logic_vector(1 downto 0)  := INI_B(17 downto 16);

    variable ADDRA_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S9_S18",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 9) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(8 downto 0)                      := INI_A_UNBOUND(8 downto 0);

        for I in INI_A_UNBOUND'high downto 9 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  9 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S9_S18",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 9,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 9) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S9_S18",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 9,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 9) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 18) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(17 downto 0)                      := INI_B_UNBOUND(17 downto 0);

        for I in INI_B_UNBOUND'high downto 18 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  18 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S9_S18",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 18,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 18) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S9_S18",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 18,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 18) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 9) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(8 downto 0)                       := SRVA_A_UNBOUND(8 downto 0);

        for I in SRVA_A_UNBOUND'high downto 9 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  9 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S9_S18",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 9,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 9) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S9_S18",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 9,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 9) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 18) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(17 downto 0)                       := SRVA_B_UNBOUND(17 downto 0);

        for I in SRVA_B_UNBOUND'high downto 18 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  18 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S9_S18",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 18,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 18) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S9_S18",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 18,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 18) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(7 downto 0) := INI_A(7 downto 0);
      DOB_zd(15 downto 0) := INI_B(15 downto 0);
      DOPA_zd(0 downto 0) := INI_A(8 downto 8);
      DOPB_zd(1 downto 0) := INI_B(17 downto 16);
      DOA  <= DOA_zd;
      DOPA <= DOPA_zd;
      DOB  <= DOB_zd;
      DOPB <= DOPB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S9_S18",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S9_S18",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA1_CLKA_posedge,
        TimingData     => Tmkr_DIA1_CLKA_posedge,
        TestSignal     => DIA_ipd(1),
        TestSignalName => "DIA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(1),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA2_CLKA_posedge,
        TimingData     => Tmkr_DIA2_CLKA_posedge,
        TestSignal     => DIA_ipd(2),
        TestSignalName => "DIA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(2),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA3_CLKA_posedge,
        TimingData     => Tmkr_DIA3_CLKA_posedge,
        TestSignal     => DIA_ipd(3),
        TestSignalName => "DIA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(3),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(3),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA4_CLKA_posedge,
        TimingData     => Tmkr_DIA4_CLKA_posedge,
        TestSignal     => DIA_ipd(4),
        TestSignalName => "DIA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(4),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(4),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA5_CLKA_posedge,
        TimingData     => Tmkr_DIA5_CLKA_posedge,
        TestSignal     => DIA_ipd(5),
        TestSignalName => "DIA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(5),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(5),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA6_CLKA_posedge,
        TimingData     => Tmkr_DIA6_CLKA_posedge,
        TestSignal     => DIA_ipd(6),
        TestSignalName => "DIA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(6),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(6),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB0_CLKB_posedge,
        TimingData     => Tmkr_DIPB0_CLKB_posedge,
        TestSignal     => DIPB_ipd(0),
        TestSignalName => "DIPB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB7_CLKB_posedge,
        TimingData     => Tmkr_DIB7_CLKB_posedge,
        TestSignal     => DIB_ipd(7),
        TestSignalName => "DIB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(7),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(7),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB8_CLKB_posedge,
        TimingData     => Tmkr_DIB8_CLKB_posedge,
        TestSignal     => DIB_ipd(8),
        TestSignalName => "DIB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(8),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(8),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB9_CLKB_posedge,
        TimingData     => Tmkr_DIB9_CLKB_posedge,
        TestSignal     => DIB_ipd(9),
        TestSignalName => "DIB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(9),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(9),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB10_CLKB_posedge,
        TimingData     => Tmkr_DIB10_CLKB_posedge,
        TestSignal     => DIB_ipd(10),
        TestSignalName => "DIB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(10),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(10),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB11_CLKB_posedge,
        TimingData     => Tmkr_DIB11_CLKB_posedge,
        TestSignal     => DIB_ipd(11),
        TestSignalName => "DIB(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(11),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(11),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(11),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(11),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB12_CLKB_posedge,
        TimingData     => Tmkr_DIB12_CLKB_posedge,
        TestSignal     => DIB_ipd(12),
        TestSignalName => "DIB(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(12),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(12),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(12),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(12),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB13_CLKB_posedge,
        TimingData     => Tmkr_DIB13_CLKB_posedge,
        TestSignal     => DIB_ipd(13),
        TestSignalName => "DIB(13)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(13),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(13),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(13),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(13),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB14_CLKB_posedge,
        TimingData     => Tmkr_DIB14_CLKB_posedge,
        TestSignal     => DIB_ipd(14),
        TestSignalName => "DIB(14)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(14),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(14),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(14),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(14),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_DIA2_CLKA_posedge or
                  Tviol_DIA3_CLKA_posedge or
                  Tviol_DIA4_CLKA_posedge or
                  Tviol_DIA5_CLKA_posedge or
                  Tviol_DIA6_CLKA_posedge or
                  Tviol_DIA7_CLKA_posedge or
                  Tviol_DIPA0_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_DIB8_CLKB_posedge or
                  Tviol_DIB9_CLKB_posedge or
                  Tviol_DIB10_CLKB_posedge or
                  Tviol_DIB11_CLKB_posedge or
                  Tviol_DIB12_CLKB_posedge or
                  Tviol_DIB13_CLKB_posedge or
                  Tviol_DIB14_CLKB_posedge or
                  Tviol_DIB15_CLKB_posedge or
                  Tviol_DIPB0_CLKB_posedge or
                  Tviol_DIPB1_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
      addr_overlap (address_a, address_b, parity_width_a, parity_width_b, has_overlap_p, olpp_lsb, olpp_msb, dopa_ov_lsb, dopa_ov_msb, dopb_ov_lsb, dopb_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S18",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;
              DOPA_zd := DIPA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S9_S18",
                       InstanceName => ramb16_s9_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');    

                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                      DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S9_S18",
                       InstanceName => ramb16_s9_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;                                      
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                    DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB)                   := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                    MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S9_S18",
                       InstanceName => ramb16_s9_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                      DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S9_S18",
                       InstanceName => ramb16_s9_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                    MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB)                   := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S9_S18",
                       InstanceName => ramb16_s9_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                      DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S9_S18",
                       InstanceName => ramb16_s9_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                    DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB)                   := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                    MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
            DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S9_S18",
                 InstanceName => ramb16_s9_s18'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
              DOPA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(7 downto 0);
          DOPA_zd := SRVA_A(8 downto 8);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
              DOPB_zd := DIPB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S9_S18",
                       InstanceName => ramb16_s9_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                   MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                   DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                     DOPA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S9_S18",
                       InstanceName => ramb16_s9_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                DOPB_zd := MEMP(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S9_S18",
                       InstanceName => ramb16_s9_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                      DOPA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S9_S18",
                       InstanceName => ramb16_s9_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S9_S18",
                     InstanceName => ramb16_s9_s18'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S9_S18",
                       InstanceName => ramb16_s9_s18'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
            DOPB_zd := MEMP(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S9_S18",
                 InstanceName => ramb16_s9_s18'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
              DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(15 downto 0);
          DOPB_zd := SRVA_B(17 downto 16);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
      MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
      MEMP(ADDRESS_B) := DIPB_ipd;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);
    DOA_zd(1)  := ViolationA xor DOA_zd(1);
    DOA_zd(2)  := ViolationA xor DOA_zd(2);
    DOA_zd(3)  := ViolationA xor DOA_zd(3);
    DOA_zd(4)  := ViolationA xor DOA_zd(4);
    DOA_zd(5)  := ViolationA xor DOA_zd(5);
    DOA_zd(6)  := ViolationA xor DOA_zd(6);
    DOA_zd(7)  := ViolationA xor DOA_zd(7);
    DOPA_zd(0) := ViolationA xor DOPA_zd(0);
    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);
    DOB_zd(8)  := ViolationB xor DOB_zd(8);
    DOB_zd(9)  := ViolationB xor DOB_zd(9);
    DOB_zd(10)  := ViolationB xor DOB_zd(10);
    DOB_zd(11)  := ViolationB xor DOB_zd(11);
    DOB_zd(12)  := ViolationB xor DOB_zd(12);
    DOB_zd(13)  := ViolationB xor DOB_zd(13);
    DOB_zd(14)  := ViolationB xor DOB_zd(14);
    DOB_zd(15)  := ViolationB xor DOB_zd(15);
    DOPB_zd(0) := ViolationB xor DOPB_zd(0);
    DOPB_zd(1) := ViolationB xor DOPB_zd(1);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(2),
      GlitchData    => DOA_GlitchData2,
      OutSignalName => "DOA(2)",
      OutTemp       => DOA_zd(2),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(3),
      GlitchData    => DOA_GlitchData3,
      OutSignalName => "DOA(3)",
      OutTemp       => DOA_zd(3),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(4),
      GlitchData    => DOA_GlitchData4,
      OutSignalName => "DOA(4)",
      OutTemp       => DOA_zd(4),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(5),
      GlitchData    => DOA_GlitchData5,
      OutSignalName => "DOA(5)",
      OutTemp       => DOA_zd(5),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(6),
      GlitchData    => DOA_GlitchData6,
      OutSignalName => "DOA(6)",
      OutTemp       => DOA_zd(6),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(7),
      GlitchData    => DOA_GlitchData7,
      OutSignalName => "DOA(7)",
      OutTemp       => DOA_zd(7),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPA(0),
      GlitchData    => DOPA_GlitchData0,
      OutSignalName => "DOPA(0)",
      OutTemp       => DOPA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(8),
      GlitchData    => DOB_GlitchData8,
      OutSignalName => "DOB(8)",
      OutTemp       => DOB_zd(8),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(9),
      GlitchData    => DOB_GlitchData9,
      OutSignalName => "DOB(9)",
      OutTemp       => DOB_zd(9),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(10),
      GlitchData    => DOB_GlitchData10,
      OutSignalName => "DOB(10)",
      OutTemp       => DOB_zd(10),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(11),
      GlitchData    => DOB_GlitchData11,
      OutSignalName => "DOB(11)",
      OutTemp       => DOB_zd(11),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(12),
      GlitchData    => DOB_GlitchData12,
      OutSignalName => "DOB(12)",
      OutTemp       => DOB_zd(12),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(13),
      GlitchData    => DOB_GlitchData13,
      OutSignalName => "DOB(13)",
      OutTemp       => DOB_zd(13),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(14),
      GlitchData    => DOB_GlitchData14,
      OutSignalName => "DOB(14)",
      OutTemp       => DOB_zd(14),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(15),
      GlitchData    => DOB_GlitchData15,
      OutSignalName => "DOB(15)",
      OutTemp       => DOB_zd(15),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(0),
      GlitchData    => DOPB_GlitchData0,
      OutSignalName => "DOPB(0)",
      OutTemp       => DOPB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(1),
      GlitchData    => DOPB_GlitchData1,
      OutSignalName => "DOPB(1)",
      OutTemp       => DOPB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPA_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S9_S18_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S9_S36.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s9_s36 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S9_S36 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(10 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPA  : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(8 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPB  : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKA_DOPA : VitalDelayArrayType01(0 downto 0)  := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_DIPA_CLKA_negedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    tsetup_DIPA_CLKA_posedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    tsetup_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    tsetup_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_DIPA_CLKA_negedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    thold_DIPA_CLKA_posedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(31 downto 0) := (others => 0 ps);
    thold_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    thold_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(3 downto 0)  := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"000";
    INIT_B : bit_vector := X"000000000";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"000";
    SRVAL_B : bit_vector := X"000000000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(7 downto 0);
    DOB  : out std_logic_vector(31 downto 0);
    DOPA : out std_logic_vector(0 downto 0);
    DOPB : out std_logic_vector(3 downto 0);

    ADDRA : in std_logic_vector(10 downto 0);
    ADDRB : in std_logic_vector(8 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(7 downto 0);
    DIB   : in std_logic_vector(31 downto 0);
    DIPA  : in std_logic_vector(0 downto 0);
    DIPB  : in std_logic_vector(3 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S9_S36 : entity is true;
end ramb16_s9_s36;

architecture RAMB16_S9_S36_V of RAMB16_S9_S36 is
  attribute VITAL_LEVEL0 of
    RAMB16_S9_S36_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(10 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(7 downto 0) := (others => 'X');
  signal DIPA_ipd  : std_logic_vector(0 downto 0)  := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(8 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(31 downto 0) := (others => 'X');
  signal DIPB_ipd  : std_logic_vector(3 downto 0)  := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 2048;
  constant length_b : integer := 512;
  constant width_a : integer := 8;
  constant width_b : integer := 32;  

  constant parity_width_a : integer := 1;
  constant parity_width_b : integer := 4;  
  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);
  type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

  function slv_to_two_D_parity_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_parity_array_type is
    variable two_D_parity_array : two_D_parity_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_parity_array(i) := intermediate; 
    end loop;
    return two_D_parity_array;
  end;        
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 10 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 7 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    DIPA_DELAY  : for i in 0 downto 0 generate
      VitalWireDelay (DIPA_ipd(i), DIPA(i), tipd_DIPA(i));
    end generate DIPA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 8 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 31 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    DIPB_DELAY  : for i in 3 downto 0 generate
      VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i));
    end generate DIPB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA2_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA3_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA4_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA5_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA6_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA7_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIPA0_CLKA_posedge  : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB8_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB9_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB10_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB11_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB12_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB13_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB14_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB15_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB16_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB17_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB18_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB19_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB20_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB21_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB22_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB23_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB24_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB25_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB26_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB27_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB28_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB29_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB30_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB31_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIPB0_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB1_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB2_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_DIPB3_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA2_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA3_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA4_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA5_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA6_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA7_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPA0_CLKA_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB8_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB9_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB10_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB11_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB12_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB13_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB14_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB15_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB16_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB17_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB18_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB19_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB20_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB21_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB22_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB23_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB24_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB25_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB26_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB27_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB28_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB29_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB30_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB31_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB0_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB1_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB2_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB3_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;
    variable DOA_GlitchData2  : VitalGlitchDataType;
    variable DOA_GlitchData3  : VitalGlitchDataType;
    variable DOA_GlitchData4  : VitalGlitchDataType;
    variable DOA_GlitchData5  : VitalGlitchDataType;
    variable DOA_GlitchData6  : VitalGlitchDataType;
    variable DOA_GlitchData7  : VitalGlitchDataType;
    variable DOPA_GlitchData0 : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;
    variable DOB_GlitchData8  : VitalGlitchDataType;
    variable DOB_GlitchData9  : VitalGlitchDataType;
    variable DOB_GlitchData10  : VitalGlitchDataType;
    variable DOB_GlitchData11  : VitalGlitchDataType;
    variable DOB_GlitchData12  : VitalGlitchDataType;
    variable DOB_GlitchData13  : VitalGlitchDataType;
    variable DOB_GlitchData14  : VitalGlitchDataType;
    variable DOB_GlitchData15  : VitalGlitchDataType;
    variable DOB_GlitchData16  : VitalGlitchDataType;
    variable DOB_GlitchData17  : VitalGlitchDataType;
    variable DOB_GlitchData18  : VitalGlitchDataType;
    variable DOB_GlitchData19  : VitalGlitchDataType;
    variable DOB_GlitchData20  : VitalGlitchDataType;
    variable DOB_GlitchData21  : VitalGlitchDataType;
    variable DOB_GlitchData22  : VitalGlitchDataType;
    variable DOB_GlitchData23  : VitalGlitchDataType;
    variable DOB_GlitchData24  : VitalGlitchDataType;
    variable DOB_GlitchData25  : VitalGlitchDataType;
    variable DOB_GlitchData26  : VitalGlitchDataType;
    variable DOB_GlitchData27  : VitalGlitchDataType;
    variable DOB_GlitchData28  : VitalGlitchDataType;
    variable DOB_GlitchData29  : VitalGlitchDataType;
    variable DOB_GlitchData30  : VitalGlitchDataType;
    variable DOB_GlitchData31  : VitalGlitchDataType;
    variable DOPB_GlitchData0 : VitalGlitchDataType;
    variable DOPB_GlitchData1 : VitalGlitchDataType;
    variable DOPB_GlitchData2 : VitalGlitchDataType;
    variable DOPB_GlitchData3 : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) &
                                                       To_StdLogicVector(INITP_06) &
                                                       To_StdLogicVector(INITP_05) &
                                                       To_StdLogicVector(INITP_04) &
                                                       To_StdLogicVector(INITP_03) &
                                                       To_StdLogicVector(INITP_02) &
                                                       To_StdLogicVector(INITP_01) &
                                                       To_StdLogicVector(INITP_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);
    variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv);        


    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable DOPA_OV_LSB       : integer := 0;
    variable DOPA_OV_MSB       : integer := 0;
    variable DOPB_OV_LSB       : integer := 0;
    variable DOPB_OV_MSB       : integer := 3;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (8 downto 0)              := "000000000";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (35 downto 0)              := "000000000000000000000000000000000000";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (8 downto 0)              := "000000000";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (35 downto 0)              := "000000000000000000000000000000000000";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(7 downto 0) := INI_A(7 downto 0);
    variable DOB_zd  : std_logic_vector(31 downto 0) := INI_B(31 downto 0);
    variable DOPA_zd : std_logic_vector(0 downto 0)  := INI_A(8 downto 8);
    variable DOPB_zd : std_logic_vector(3 downto 0)  := INI_B(35 downto 32);

    variable ADDRA_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S9_S36",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 9) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(8 downto 0)                      := INI_A_UNBOUND(8 downto 0);

        for I in INI_A_UNBOUND'high downto 9 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  9 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S9_S36",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 9,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 9) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S9_S36",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 9,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 9) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 36) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(35 downto 0)                      := INI_B_UNBOUND(35 downto 0);

        for I in INI_B_UNBOUND'high downto 36 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  36 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S9_S36",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 36,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 36) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S9_S36",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 36,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 36) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 9) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(8 downto 0)                       := SRVA_A_UNBOUND(8 downto 0);

        for I in SRVA_A_UNBOUND'high downto 9 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  9 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S9_S36",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 9,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 9) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S9_S36",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 9,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 9) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 36) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(35 downto 0)                       := SRVA_B_UNBOUND(35 downto 0);

        for I in SRVA_B_UNBOUND'high downto 36 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  36 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S9_S36",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 36,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 36) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S9_S36",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 36,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 36) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(7 downto 0) := INI_A(7 downto 0);
      DOB_zd(31 downto 0) := INI_B(31 downto 0);
      DOPA_zd(0 downto 0) := INI_A(8 downto 8);
      DOPB_zd(3 downto 0) := INI_B(35 downto 32);
      DOA  <= DOA_zd;
      DOPA <= DOPA_zd;
      DOB  <= DOB_zd;
      DOPB <= DOPB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S9_S36",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S9_S36",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA1_CLKA_posedge,
        TimingData     => Tmkr_DIA1_CLKA_posedge,
        TestSignal     => DIA_ipd(1),
        TestSignalName => "DIA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(1),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA2_CLKA_posedge,
        TimingData     => Tmkr_DIA2_CLKA_posedge,
        TestSignal     => DIA_ipd(2),
        TestSignalName => "DIA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(2),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA3_CLKA_posedge,
        TimingData     => Tmkr_DIA3_CLKA_posedge,
        TestSignal     => DIA_ipd(3),
        TestSignalName => "DIA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(3),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(3),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA4_CLKA_posedge,
        TimingData     => Tmkr_DIA4_CLKA_posedge,
        TestSignal     => DIA_ipd(4),
        TestSignalName => "DIA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(4),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(4),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA5_CLKA_posedge,
        TimingData     => Tmkr_DIA5_CLKA_posedge,
        TestSignal     => DIA_ipd(5),
        TestSignalName => "DIA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(5),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(5),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA6_CLKA_posedge,
        TimingData     => Tmkr_DIA6_CLKA_posedge,
        TestSignal     => DIA_ipd(6),
        TestSignalName => "DIA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(6),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(6),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB0_CLKB_posedge,
        TimingData     => Tmkr_DIPB0_CLKB_posedge,
        TestSignal     => DIPB_ipd(0),
        TestSignalName => "DIPB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB1_CLKB_posedge,
        TimingData     => Tmkr_DIPB1_CLKB_posedge,
        TestSignal     => DIPB_ipd(1),
        TestSignalName => "DIPB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIPB2_CLKB_posedge,
        TimingData     => Tmkr_DIPB2_CLKB_posedge,
        TestSignal     => DIPB_ipd(2),
        TestSignalName => "DIPB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIPB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIPB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIPB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIPB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB7_CLKB_posedge,
        TimingData     => Tmkr_DIB7_CLKB_posedge,
        TestSignal     => DIB_ipd(7),
        TestSignalName => "DIB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(7),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(7),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB8_CLKB_posedge,
        TimingData     => Tmkr_DIB8_CLKB_posedge,
        TestSignal     => DIB_ipd(8),
        TestSignalName => "DIB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(8),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(8),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB9_CLKB_posedge,
        TimingData     => Tmkr_DIB9_CLKB_posedge,
        TestSignal     => DIB_ipd(9),
        TestSignalName => "DIB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(9),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(9),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB10_CLKB_posedge,
        TimingData     => Tmkr_DIB10_CLKB_posedge,
        TestSignal     => DIB_ipd(10),
        TestSignalName => "DIB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(10),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(10),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB11_CLKB_posedge,
        TimingData     => Tmkr_DIB11_CLKB_posedge,
        TestSignal     => DIB_ipd(11),
        TestSignalName => "DIB(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(11),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(11),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(11),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(11),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB12_CLKB_posedge,
        TimingData     => Tmkr_DIB12_CLKB_posedge,
        TestSignal     => DIB_ipd(12),
        TestSignalName => "DIB(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(12),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(12),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(12),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(12),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB13_CLKB_posedge,
        TimingData     => Tmkr_DIB13_CLKB_posedge,
        TestSignal     => DIB_ipd(13),
        TestSignalName => "DIB(13)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(13),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(13),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(13),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(13),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB14_CLKB_posedge,
        TimingData     => Tmkr_DIB14_CLKB_posedge,
        TestSignal     => DIB_ipd(14),
        TestSignalName => "DIB(14)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(14),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(14),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(14),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(14),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB15_CLKB_posedge,
        TimingData     => Tmkr_DIB15_CLKB_posedge,
        TestSignal     => DIB_ipd(15),
        TestSignalName => "DIB(15)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(15),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(15),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(15),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(15),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB16_CLKB_posedge,
        TimingData     => Tmkr_DIB16_CLKB_posedge,
        TestSignal     => DIB_ipd(16),
        TestSignalName => "DIB(16)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(16),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(16),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(16),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(16),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB17_CLKB_posedge,
        TimingData     => Tmkr_DIB17_CLKB_posedge,
        TestSignal     => DIB_ipd(17),
        TestSignalName => "DIB(17)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(17),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(17),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(17),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(17),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB18_CLKB_posedge,
        TimingData     => Tmkr_DIB18_CLKB_posedge,
        TestSignal     => DIB_ipd(18),
        TestSignalName => "DIB(18)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(18),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(18),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(18),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(18),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB19_CLKB_posedge,
        TimingData     => Tmkr_DIB19_CLKB_posedge,
        TestSignal     => DIB_ipd(19),
        TestSignalName => "DIB(19)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(19),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(19),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(19),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(19),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB20_CLKB_posedge,
        TimingData     => Tmkr_DIB20_CLKB_posedge,
        TestSignal     => DIB_ipd(20),
        TestSignalName => "DIB(20)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(20),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(20),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(20),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(20),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB21_CLKB_posedge,
        TimingData     => Tmkr_DIB21_CLKB_posedge,
        TestSignal     => DIB_ipd(21),
        TestSignalName => "DIB(21)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(21),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(21),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(21),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(21),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB22_CLKB_posedge,
        TimingData     => Tmkr_DIB22_CLKB_posedge,
        TestSignal     => DIB_ipd(22),
        TestSignalName => "DIB(22)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(22),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(22),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(22),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(22),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB23_CLKB_posedge,
        TimingData     => Tmkr_DIB23_CLKB_posedge,
        TestSignal     => DIB_ipd(23),
        TestSignalName => "DIB(23)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(23),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(23),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(23),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(23),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB24_CLKB_posedge,
        TimingData     => Tmkr_DIB24_CLKB_posedge,
        TestSignal     => DIB_ipd(24),
        TestSignalName => "DIB(24)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(24),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(24),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(24),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(24),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB25_CLKB_posedge,
        TimingData     => Tmkr_DIB25_CLKB_posedge,
        TestSignal     => DIB_ipd(25),
        TestSignalName => "DIB(25)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(25),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(25),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(25),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(25),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB26_CLKB_posedge,
        TimingData     => Tmkr_DIB26_CLKB_posedge,
        TestSignal     => DIB_ipd(26),
        TestSignalName => "DIB(26)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(26),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(26),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(26),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(26),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB27_CLKB_posedge,
        TimingData     => Tmkr_DIB27_CLKB_posedge,
        TestSignal     => DIB_ipd(27),
        TestSignalName => "DIB(27)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(27),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(27),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(27),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(27),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB28_CLKB_posedge,
        TimingData     => Tmkr_DIB28_CLKB_posedge,
        TestSignal     => DIB_ipd(28),
        TestSignalName => "DIB(28)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(28),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(28),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(28),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(28),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB29_CLKB_posedge,
        TimingData     => Tmkr_DIB29_CLKB_posedge,
        TestSignal     => DIB_ipd(29),
        TestSignalName => "DIB(29)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(29),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(29),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(29),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(29),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB30_CLKB_posedge,
        TimingData     => Tmkr_DIB30_CLKB_posedge,
        TestSignal     => DIB_ipd(30),
        TestSignalName => "DIB(30)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(30),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(30),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(30),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(30),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_DIA2_CLKA_posedge or
                  Tviol_DIA3_CLKA_posedge or
                  Tviol_DIA4_CLKA_posedge or
                  Tviol_DIA5_CLKA_posedge or
                  Tviol_DIA6_CLKA_posedge or
                  Tviol_DIA7_CLKA_posedge or
                  Tviol_DIPA0_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_DIB8_CLKB_posedge or
                  Tviol_DIB9_CLKB_posedge or
                  Tviol_DIB10_CLKB_posedge or
                  Tviol_DIB11_CLKB_posedge or
                  Tviol_DIB12_CLKB_posedge or
                  Tviol_DIB13_CLKB_posedge or
                  Tviol_DIB14_CLKB_posedge or
                  Tviol_DIB15_CLKB_posedge or
                  Tviol_DIB16_CLKB_posedge or
                  Tviol_DIB17_CLKB_posedge or
                  Tviol_DIB18_CLKB_posedge or
                  Tviol_DIB19_CLKB_posedge or
                  Tviol_DIB20_CLKB_posedge or
                  Tviol_DIB21_CLKB_posedge or
                  Tviol_DIB22_CLKB_posedge or
                  Tviol_DIB23_CLKB_posedge or
                  Tviol_DIB24_CLKB_posedge or
                  Tviol_DIB25_CLKB_posedge or
                  Tviol_DIB26_CLKB_posedge or
                  Tviol_DIB27_CLKB_posedge or
                  Tviol_DIB28_CLKB_posedge or
                  Tviol_DIB29_CLKB_posedge or
                  Tviol_DIB30_CLKB_posedge or
                  Tviol_DIB31_CLKB_posedge or
                  Tviol_DIPB0_CLKB_posedge or
                  Tviol_DIPB1_CLKB_posedge or
                  Tviol_DIPB2_CLKB_posedge or
                  Tviol_DIPB3_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
      addr_overlap (address_a, address_b, parity_width_a, parity_width_b, has_overlap_p, olpp_lsb, olpp_msb, dopa_ov_lsb, dopa_ov_msb, dopb_ov_lsb, dopb_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S36",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;
              DOPA_zd := DIPA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S9_S36",
                       InstanceName => ramb16_s9_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');    

                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                      DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S9_S36",
                       InstanceName => ramb16_s9_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;                                      
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                    DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB)                   := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                    MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S9_S36",
                       InstanceName => ramb16_s9_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                      DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S9_S36",
                       InstanceName => ramb16_s9_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                    MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB)                   := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S9_S36",
                       InstanceName => ramb16_s9_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                      DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S9_S36",
                       InstanceName => ramb16_s9_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                    DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB)                   := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                    MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
            DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S9_S36",
                 InstanceName => ramb16_s9_s36'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
              DOPA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(7 downto 0);
          DOPA_zd := SRVA_A(8 downto 8);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
              DOPB_zd := DIPB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S9_S36",
                       InstanceName => ramb16_s9_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                   MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                   DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                     DOPA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S9_S36",
                       InstanceName => ramb16_s9_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                DOPB_zd := MEMP(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S9_S36",
                       InstanceName => ramb16_s9_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                      DOPA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S9_S36",
                       InstanceName => ramb16_s9_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S9_S36",
                     InstanceName => ramb16_s9_s36'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S9_S36",
                       InstanceName => ramb16_s9_s36'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
            DOPB_zd := MEMP(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S9_S36",
                 InstanceName => ramb16_s9_s36'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
              DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(31 downto 0);
          DOPB_zd := SRVA_B(35 downto 32);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
      MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
      MEMP(ADDRESS_B) := DIPB_ipd;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);
    DOA_zd(1)  := ViolationA xor DOA_zd(1);
    DOA_zd(2)  := ViolationA xor DOA_zd(2);
    DOA_zd(3)  := ViolationA xor DOA_zd(3);
    DOA_zd(4)  := ViolationA xor DOA_zd(4);
    DOA_zd(5)  := ViolationA xor DOA_zd(5);
    DOA_zd(6)  := ViolationA xor DOA_zd(6);
    DOA_zd(7)  := ViolationA xor DOA_zd(7);
    DOPA_zd(0) := ViolationA xor DOPA_zd(0);
    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);
    DOB_zd(8)  := ViolationB xor DOB_zd(8);
    DOB_zd(9)  := ViolationB xor DOB_zd(9);
    DOB_zd(10)  := ViolationB xor DOB_zd(10);
    DOB_zd(11)  := ViolationB xor DOB_zd(11);
    DOB_zd(12)  := ViolationB xor DOB_zd(12);
    DOB_zd(13)  := ViolationB xor DOB_zd(13);
    DOB_zd(14)  := ViolationB xor DOB_zd(14);
    DOB_zd(15)  := ViolationB xor DOB_zd(15);
    DOB_zd(16)  := ViolationB xor DOB_zd(16);
    DOB_zd(17)  := ViolationB xor DOB_zd(17);
    DOB_zd(18)  := ViolationB xor DOB_zd(18);
    DOB_zd(19)  := ViolationB xor DOB_zd(19);
    DOB_zd(20)  := ViolationB xor DOB_zd(20);
    DOB_zd(21)  := ViolationB xor DOB_zd(21);
    DOB_zd(22)  := ViolationB xor DOB_zd(22);
    DOB_zd(23)  := ViolationB xor DOB_zd(23);
    DOB_zd(24)  := ViolationB xor DOB_zd(24);
    DOB_zd(25)  := ViolationB xor DOB_zd(25);
    DOB_zd(26)  := ViolationB xor DOB_zd(26);
    DOB_zd(27)  := ViolationB xor DOB_zd(27);
    DOB_zd(28)  := ViolationB xor DOB_zd(28);
    DOB_zd(29)  := ViolationB xor DOB_zd(29);
    DOB_zd(30)  := ViolationB xor DOB_zd(30);
    DOB_zd(31)  := ViolationB xor DOB_zd(31);
    DOPB_zd(0) := ViolationB xor DOPB_zd(0);
    DOPB_zd(1) := ViolationB xor DOPB_zd(1);
    DOPB_zd(2) := ViolationB xor DOPB_zd(2);
    DOPB_zd(3) := ViolationB xor DOPB_zd(3);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(2),
      GlitchData    => DOA_GlitchData2,
      OutSignalName => "DOA(2)",
      OutTemp       => DOA_zd(2),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(3),
      GlitchData    => DOA_GlitchData3,
      OutSignalName => "DOA(3)",
      OutTemp       => DOA_zd(3),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(4),
      GlitchData    => DOA_GlitchData4,
      OutSignalName => "DOA(4)",
      OutTemp       => DOA_zd(4),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(5),
      GlitchData    => DOA_GlitchData5,
      OutSignalName => "DOA(5)",
      OutTemp       => DOA_zd(5),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(6),
      GlitchData    => DOA_GlitchData6,
      OutSignalName => "DOA(6)",
      OutTemp       => DOA_zd(6),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(7),
      GlitchData    => DOA_GlitchData7,
      OutSignalName => "DOA(7)",
      OutTemp       => DOA_zd(7),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPA(0),
      GlitchData    => DOPA_GlitchData0,
      OutSignalName => "DOPA(0)",
      OutTemp       => DOPA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(8),
      GlitchData    => DOB_GlitchData8,
      OutSignalName => "DOB(8)",
      OutTemp       => DOB_zd(8),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(9),
      GlitchData    => DOB_GlitchData9,
      OutSignalName => "DOB(9)",
      OutTemp       => DOB_zd(9),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(10),
      GlitchData    => DOB_GlitchData10,
      OutSignalName => "DOB(10)",
      OutTemp       => DOB_zd(10),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(11),
      GlitchData    => DOB_GlitchData11,
      OutSignalName => "DOB(11)",
      OutTemp       => DOB_zd(11),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(12),
      GlitchData    => DOB_GlitchData12,
      OutSignalName => "DOB(12)",
      OutTemp       => DOB_zd(12),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(13),
      GlitchData    => DOB_GlitchData13,
      OutSignalName => "DOB(13)",
      OutTemp       => DOB_zd(13),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(14),
      GlitchData    => DOB_GlitchData14,
      OutSignalName => "DOB(14)",
      OutTemp       => DOB_zd(14),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(15),
      GlitchData    => DOB_GlitchData15,
      OutSignalName => "DOB(15)",
      OutTemp       => DOB_zd(15),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(16),
      GlitchData    => DOB_GlitchData16,
      OutSignalName => "DOB(16)",
      OutTemp       => DOB_zd(16),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(16), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(17),
      GlitchData    => DOB_GlitchData17,
      OutSignalName => "DOB(17)",
      OutTemp       => DOB_zd(17),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(17), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(18),
      GlitchData    => DOB_GlitchData18,
      OutSignalName => "DOB(18)",
      OutTemp       => DOB_zd(18),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(18), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(19),
      GlitchData    => DOB_GlitchData19,
      OutSignalName => "DOB(19)",
      OutTemp       => DOB_zd(19),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(19), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(20),
      GlitchData    => DOB_GlitchData20,
      OutSignalName => "DOB(20)",
      OutTemp       => DOB_zd(20),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(20), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(21),
      GlitchData    => DOB_GlitchData21,
      OutSignalName => "DOB(21)",
      OutTemp       => DOB_zd(21),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(21), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(22),
      GlitchData    => DOB_GlitchData22,
      OutSignalName => "DOB(22)",
      OutTemp       => DOB_zd(22),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(22), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(23),
      GlitchData    => DOB_GlitchData23,
      OutSignalName => "DOB(23)",
      OutTemp       => DOB_zd(23),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(23), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(24),
      GlitchData    => DOB_GlitchData24,
      OutSignalName => "DOB(24)",
      OutTemp       => DOB_zd(24),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(24), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(25),
      GlitchData    => DOB_GlitchData25,
      OutSignalName => "DOB(25)",
      OutTemp       => DOB_zd(25),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(25), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(26),
      GlitchData    => DOB_GlitchData26,
      OutSignalName => "DOB(26)",
      OutTemp       => DOB_zd(26),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(26), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(27),
      GlitchData    => DOB_GlitchData27,
      OutSignalName => "DOB(27)",
      OutTemp       => DOB_zd(27),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(27), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(28),
      GlitchData    => DOB_GlitchData28,
      OutSignalName => "DOB(28)",
      OutTemp       => DOB_zd(28),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(28), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(29),
      GlitchData    => DOB_GlitchData29,
      OutSignalName => "DOB(29)",
      OutTemp       => DOB_zd(29),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(29), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(30),
      GlitchData    => DOB_GlitchData30,
      OutSignalName => "DOB(30)",
      OutTemp       => DOB_zd(30),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(30), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(31),
      GlitchData    => DOB_GlitchData31,
      OutSignalName => "DOB(31)",
      OutTemp       => DOB_zd(31),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(31), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(0),
      GlitchData    => DOPB_GlitchData0,
      OutSignalName => "DOPB(0)",
      OutTemp       => DOPB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(1),
      GlitchData    => DOPB_GlitchData1,
      OutSignalName => "DOPB(1)",
      OutTemp       => DOPB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(2),
      GlitchData    => DOPB_GlitchData2,
      OutSignalName => "DOPB(2)",
      OutTemp       => DOPB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(3),
      GlitchData    => DOPB_GlitchData3,
      OutSignalName => "DOPB(3)",
      OutTemp       => DOPB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPA_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S9_S36_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16_S9_S9.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/07 - Fixed invalid address of port B. (CR 430253).
-- End Revision
  
----- CELL ramb16_s9_s9 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library STD;
use STD.TEXTIO.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB16_S9_S9 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(10 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPA  : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRA  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := (0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(10 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
    tipd_DIPB  : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := (0 ps, 0 ps);
    tipd_SSRB  : VitalDelayType01                   := (0 ps, 0 ps);

    tpd_CLKA_DOA  : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKA_DOPA : VitalDelayArrayType01(0 downto 0)  := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB  : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOPB : VitalDelayArrayType01(0 downto 0)  := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_DIPA_CLKA_negedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    tsetup_DIPA_CLKA_posedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    tsetup_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_DIPA_CLKA_negedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    thold_DIPA_CLKA_posedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_DIPB_CLKB_negedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    thold_DIPB_CLKB_posedge_posedge  : VitalDelayArrayType(0 downto 0)  := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_SSRB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"000";
    INIT_B : bit_vector := X"000";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A : bit_vector := X"000";
    SRVAL_B : bit_vector := X"000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA  : out std_logic_vector(7 downto 0);
    DOB  : out std_logic_vector(7 downto 0);
    DOPA : out std_logic_vector(0 downto 0);
    DOPB : out std_logic_vector(0 downto 0);

    ADDRA : in std_logic_vector(10 downto 0);
    ADDRB : in std_logic_vector(10 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(7 downto 0);
    DIB   : in std_logic_vector(7 downto 0);
    DIPA  : in std_logic_vector(0 downto 0);
    DIPB  : in std_logic_vector(0 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    SSRA  : in std_ulogic;
    SSRB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB16_S9_S9 : entity is true;
end ramb16_s9_s9;

architecture RAMB16_S9_S9_V of RAMB16_S9_S9 is
  attribute VITAL_LEVEL0 of
    RAMB16_S9_S9_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(10 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(7 downto 0) := (others => 'X');
  signal DIPA_ipd  : std_logic_vector(0 downto 0)  := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal SSRA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(10 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(7 downto 0) := (others => 'X');
  signal DIPB_ipd  : std_logic_vector(0 downto 0)  := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal SSRB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL        : VitalDelayType := 1000 ps;
  constant SETUP_READ_FIRST : VitalDelayType := 1000 ps;
  constant length_a : integer := 2048;
  constant length_b : integer := 2048;
  constant width_a : integer := 8;
  constant width_b : integer := 8;  

  constant parity_width_a : integer := 1;
  constant parity_width_b : integer := 1;  
  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);
  type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0);

  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;

  function slv_to_two_D_parity_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_parity_array_type is
    variable two_D_parity_array : two_D_parity_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_parity_array(i) := intermediate; 
    end loop;
    return two_D_parity_array;
  end;        
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 10 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 7 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    DIPA_DELAY  : for i in 0 downto 0 generate
      VitalWireDelay (DIPA_ipd(i), DIPA(i), tipd_DIPA(i));
    end generate DIPA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 10 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 7 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    DIPB_DELAY  : for i in 0 downto 0 generate
      VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i));
    end generate DIPB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA2_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA3_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA4_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA5_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA6_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA7_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIPA0_CLKA_posedge  : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_SSRA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIPB0_CLKB_posedge  : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_SSRB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA                 : std_ulogic := '0';
    variable PViol_CLKB                 : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_all        : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_all        : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA2_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA3_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA4_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA5_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA6_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA7_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPA0_CLKA_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIPB0_CLKB_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_SSRB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA                : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB                : VitalPeriodDataType := VitalPeriodDataInit;
    variable Tmkr_CLKA_CLKB_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_all        : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;
    variable DOA_GlitchData2  : VitalGlitchDataType;
    variable DOA_GlitchData3  : VitalGlitchDataType;
    variable DOA_GlitchData4  : VitalGlitchDataType;
    variable DOA_GlitchData5  : VitalGlitchDataType;
    variable DOA_GlitchData6  : VitalGlitchDataType;
    variable DOA_GlitchData7  : VitalGlitchDataType;
    variable DOPA_GlitchData0 : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;
    variable DOPB_GlitchData0 : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) &
                                                       To_StdLogicVector(INITP_06) &
                                                       To_StdLogicVector(INITP_05) &
                                                       To_StdLogicVector(INITP_04) &
                                                       To_StdLogicVector(INITP_03) &
                                                       To_StdLogicVector(INITP_02) &
                                                       To_StdLogicVector(INITP_01) &
                                                       To_StdLogicVector(INITP_00);

    variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv);
    variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv);        


    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;
    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable DOPA_OV_LSB       : integer := 0;
    variable DOPA_OV_MSB       : integer := 0;
    variable DOPB_OV_LSB       : integer := 0;
    variable DOPB_OV_MSB       : integer := 0;
    variable FIRST_TIME        : boolean                                     := true;
    variable HAS_OVERLAP       : boolean                                     := false;
    variable HAS_OVERLAP_P     : boolean                                     := false;
    variable INIT_A_val        : std_logic_vector(INIT_A'length-1 downto 0)  := (others => 'X');
    variable INIT_B_val        : std_logic_vector(INIT_B'length-1 downto 0)  := (others => 'X');
    variable INI_A             : std_logic_vector (8 downto 0)              := "000000000";
    variable INI_A_UNBOUND     : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B             : std_logic_vector (8 downto 0)              := "000000000";
    variable INI_B_UNBOUND     : std_logic_vector (INIT_B'length-1 downto 0);
    variable IS_VALID          : boolean                                     := true;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVAL_A_val       : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X');
    variable SRVAL_B_val       : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X');
    variable SRVA_A            : std_logic_vector (8 downto 0)              := "000000000";
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (8 downto 0)              := "000000000";
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable TEMPLINE          : line;
    variable VALID_ADDRA       : boolean                                     := false;
    variable VALID_ADDRB       : boolean                                     := false;
    variable WR_A_LATER        : boolean                                     := false;
    variable WR_B_LATER        : boolean                                     := false;
    variable ViolationA        : std_ulogic                                  := '0';
    variable ViolationB        : std_ulogic                                  := '0';
    variable ViolationCLKAB    : std_ulogic                                  := '0';
    variable ViolationCLKAB_S0 : boolean                                     := false;
    variable Violation_S1      : boolean                                     := false;
    variable Violation_S3      : boolean                                     := false;
    variable wr_mode_a         : integer                                     := 0;
    variable wr_mode_b         : integer                                     := 0;

    variable DOA_zd  : std_logic_vector(7 downto 0) := INI_A(7 downto 0);
    variable DOB_zd  : std_logic_vector(7 downto 0) := INI_B(7 downto 0);
    variable DOPA_zd : std_logic_vector(0 downto 0)  := INI_A(8 downto 8);
    variable DOPB_zd : std_logic_vector(0 downto 0)  := INI_B(8 downto 8);

    variable ADDRA_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X');
    variable ADDRB_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable SSRA_ipd_sampled  : std_ulogic                    := 'X';
    variable SSRB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';
    variable full_4bit_words   : integer                       := 0;
    variable needed_bits       : integer                       := 0;
    variable collision_type : integer := 3;

  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then        
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB16_S9_S9",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      if (INIT_A'length > 9) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        INI_A(8 downto 0)                      := INI_A_UNBOUND(8 downto 0);

        for I in INI_A_UNBOUND'high downto 9 loop
          if (INI_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  9 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_A ",
             EntityName           => "/RAMB16_S9_S9",
             GenericValue         => INIT_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 9,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_A'length < 9) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_A ",
           EntityName           => "/RAMB16_S9_S9",
           GenericValue         => INIT_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 9,
           TailMsg              => " Remaining MSB's of INIT_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_A'length = 9) then
        INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
      end if;

      if (INIT_B'length > 9) then
        IS_VALID := true;
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        INI_B(8 downto 0)                      := INI_B_UNBOUND(8 downto 0);

        for I in INI_B_UNBOUND'high downto 9 loop
          if (INI_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  9 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(INIT_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
              write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " INIT_B ",
             EntityName           => "/RAMB16_S9_S9",
             GenericValue         => INIT_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 9,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (INIT_B'length < 9) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " INIT_B ",
           EntityName           => "/RAMB16_S9_S9",
           GenericValue         => INIT_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 9,
           TailMsg              => " Remaining MSB's of INIT_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (INIT_B'length = 9) then
        INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
      end if;

      if (SRVAL_A'length > 9) then
        IS_VALID := true;
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        SRVA_A(8 downto 0)                       := SRVA_A_UNBOUND(8 downto 0);

        for I in SRVA_A_UNBOUND'high downto 9 loop
          if (SRVA_A_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  9 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_A'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_A ",
             EntityName           => "/RAMB16_S9_S9",
             GenericValue         => SRVAL_A'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 9,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_A'length < 9) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_A ",
           EntityName           => "/RAMB16_S9_S9",
           GenericValue         => SRVAL_A'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 9,
           TailMsg              => " Remaining MSB's of SRVAL_A are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_A'length = 9) then
        SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
      end if;

      if (SRVAL_B'length > 9) then
        IS_VALID := true;
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        SRVA_B(8 downto 0)                       := SRVA_B_UNBOUND(8 downto 0);

        for I in SRVA_B_UNBOUND'high downto 9 loop
          if (SRVA_B_UNBOUND(I) /= '0') then
            IS_VALID := false;
          end if;
        end loop;

        if (IS_VALID = true) then
          full_4bit_words :=  9 / 4;
          needed_bits := (full_4bit_words +1) * 4;
          if(SRVAL_B'length /= needed_bits) then
            write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one."));
            write(TEMPLINE, LF);
            write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros."));
            write(TEMPLINE, LF);
            assert false report
              TEMPLINE.all
              severity warning;
            write(TEMPLINE, LF);
            DEALLOCATE (TEMPLINE);
          end if;

        else
          GenericValueCheckMessage
            (HeaderMsg            => " Attribute Syntax Warning ",
             GenericName          => " SRVAL_B ",
             EntityName           => "/RAMB16_S9_S9",
             GenericValue         => SRVAL_B'length,
             Unit                 => " bit value ",
             ExpectedValueMsg     => " The expected length for this attribute is ",
             ExpectedGenericValue => 9,
             TailMsg              => "",
             MsgSeverity          => warning
             );
        end if;

      elsif (SRVAL_B'length < 9) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " SRVAL_B ",
           EntityName           => "/RAMB16_S9_S9",
           GenericValue         => SRVAL_B'length,
           Unit                 => " bit value ",
           ExpectedValueMsg     => " The expected length for this attribute is ",
           ExpectedGenericValue => 9,
           TailMsg              => " Remaining MSB's of SRVAL_B are padded with 0's ",
           MsgSeverity          => warning
           );

      elsif (SRVAL_B'length = 9) then
        SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
      end if;

      DOA_zd(7 downto 0) := INI_A(7 downto 0);
      DOB_zd(7 downto 0) := INI_B(7 downto 0);
      DOPA_zd(0 downto 0) := INI_A(8 downto 8);
      DOPB_zd(0 downto 0) := INI_B(8 downto 8);
      DOA  <= DOA_zd;
      DOPA <= DOPA_zd;
      DOB  <= DOB_zd;
      DOPB <= DOPB_zd;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := 0;

      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := 1;

      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_A ",
           EntityName           => "/RAMB16_S9_S9",
           GenericValue         => WRITE_MODE_A,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := 0;

      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := 1;

      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := 2;

      else
        GenericValueCheckMessage
          (HeaderMsg            => " Attribute Syntax Warning ",
           GenericName          => " WRITE_MODE_B ",
           EntityName           => "/RAMB16_S9_S9",
           GenericValue         => WRITE_MODE_B,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
           TailMsg              => "",
           MsgSeverity          => warning
           );
      end if;

      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      SSRA_ipd_sampled  := SSRA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      SSRB_ipd_sampled  := SSRB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRA_CLKA_posedge,
        TimingData     => Tmkr_SSRA_CLKA_posedge,
        TestSignal     => SSRA_ipd,
        TestSignalName => "SSRA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRA_CLKA_posedge_posedge,
        SetupLow       => tsetup_SSRA_CLKA_negedge_posedge,
        HoldLow        => thold_SSRA_CLKA_posedge_posedge,
        HoldHigh       => thold_SSRA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA1_CLKA_posedge,
        TimingData     => Tmkr_DIA1_CLKA_posedge,
        TestSignal     => DIA_ipd(1),
        TestSignalName => "DIA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(1),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA2_CLKA_posedge,
        TimingData     => Tmkr_DIA2_CLKA_posedge,
        TestSignal     => DIA_ipd(2),
        TestSignalName => "DIA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(2),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA3_CLKA_posedge,
        TimingData     => Tmkr_DIA3_CLKA_posedge,
        TestSignal     => DIA_ipd(3),
        TestSignalName => "DIA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(3),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(3),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA4_CLKA_posedge,
        TimingData     => Tmkr_DIA4_CLKA_posedge,
        TestSignal     => DIA_ipd(4),
        TestSignalName => "DIA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(4),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(4),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA5_CLKA_posedge,
        TimingData     => Tmkr_DIA5_CLKA_posedge,
        TestSignal     => DIA_ipd(5),
        TestSignalName => "DIA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(5),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(5),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA6_CLKA_posedge,
        TimingData     => Tmkr_DIA6_CLKA_posedge,
        TestSignal     => DIA_ipd(6),
        TestSignalName => "DIA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(6),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(6),
        CheckEnabled   => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_SSRB_CLKB_posedge,
        TimingData     => Tmkr_SSRB_CLKB_posedge,
        TestSignal     => SSRB_ipd,
        TestSignalName => "SSRB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_SSRB_CLKB_posedge_posedge,
        SetupLow       => tsetup_SSRB_CLKB_negedge_posedge,
        HoldLow        => thold_SSRB_CLKB_posedge_posedge,
        HoldHigh       => thold_SSRB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB9_CLKB_posedge,
        TimingData     => Tmkr_ADDRB9_CLKB_posedge,
        TestSignal     => ADDRB_ipd(9),
        TestSignalName => "ADDRB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(9),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(9),
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ena_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(enb_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_DIA2_CLKA_posedge or
                  Tviol_DIA3_CLKA_posedge or
                  Tviol_DIA4_CLKA_posedge or
                  Tviol_DIA5_CLKA_posedge or
                  Tviol_DIA6_CLKA_posedge or
                  Tviol_DIA7_CLKA_posedge or
                  Tviol_DIPA0_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_SSRA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_ADDRB10_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_DIPB0_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_SSRB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(addra_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
      addr_overlap (address_a, address_b, parity_width_a, parity_width_b, has_overlap_p, olpp_lsb, olpp_msb, dopa_ov_lsb, dopa_ov_msb, dopb_ov_lsb, dopb_ov_msb);
    end if;

    ViolationCLKAB    := '0';
    ViolationCLKAB_S0 := false;
    Violation_S1      := false;
    Violation_S3      := false;

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then    
      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_all,
        TimingData     => Tmkr_CLKB_CLKA_all,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_all,
        TimingData     => Tmkr_CLKA_CLKB_all,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_ALL,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKB_CLKA_read_first,
        TimingData     => Tmkr_CLKB_CLKA_read_first,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);

      VitalRecoveryRemovalCheck (
        Violation      => Tviol_CLKA_CLKB_read_first,
        TimingData     => Tmkr_CLKA_CLKB_read_first,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        Recovery       => SETUP_READ_FIRST,
        Removal       => 1 ps,
        ActiveLow      => true,
        CheckEnabled   => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB16_S9_S9",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);        
    end if;
    ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first;        


    WR_A_LATER := false;
    WR_B_LATER := false;

    if (ena_ipd_sampled = '1')then
      if (rising_edge(CLKA_ipd)) then

        if (wea_ipd_sampled = '1') then
          case wr_mode_a is
            when 0 =>
              DOA_zd  := DIA_ipd;
              DOPA_zd := DIPA_ipd;

              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S9_S9",
                       InstanceName => ramb16_s9_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');    

                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                      DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
                    end if;

                  end if;
                else
                  if ((collision_type = 1) or (collision_type = 3)) then                
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S9_S9",
                       InstanceName => ramb16_s9_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;                                      
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                    DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB)                   := (others => 'X');
                  end if;
                end if;

              else
                if (VALID_ADDRA ) then
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                    MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                end if;
              end if;

            when 1 =>
               if (VALID_ADDRA ) then
                DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
                DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a)));
                WR_A_LATER := true;
              end if;

              if (ViolationCLKAB = 'X') then

                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S9_S9",
                       InstanceName => ramb16_s9_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                      DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S9_S9",
                       InstanceName => ramb16_s9_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                    MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                if ((collision_type = 2) or (collision_type = 3)) then                
                  DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                  DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB)                   := (others => 'X');
                end if;
              end if;

            end if;

            when 2 =>
              if (ViolationCLKAB = 'X') then
                if (web_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S9_S9",
                       InstanceName => ramb16_s9_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    if (wr_mode_b /= 2 ) then
                      DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                      DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_B_Write_A,
                       EntityName => "RAMB16_S9_S9",
                       InstanceName => ramb16_s9_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)                      := (others => 'X');
                    DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB)                   := (others => 'X');
                  end if;
                    MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                    MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                end if;

              else
                if (VALID_ADDRA) then
                  MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
                  MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
                end if;
              end if;

            when others => null;
          end case;

        else
          if (VALID_ADDRA) then
            DOA_zd  := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));
            DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a)));
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB16_S9_S9",
                 InstanceName => ramb16_s9_s9'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOA_zd := (others => 'X');
              DOPA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (ssra_ipd_sampled = '1') then
          DOA_zd  := SRVA_A(7 downto 0);
          DOPA_zd := SRVA_A(8 downto 8);
        end if;
      end if;
    end if;

    if (enb_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (web_ipd_sampled = '1') then
          case wr_mode_b is
            when 0 =>
              DOB_zd  := DIB_ipd;
              DOPB_zd := DIPB_ipd;
               if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S9_S9",
                       InstanceName => ramb16_s9_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                 end if;
                 if ((collision_type = 2) or (collision_type = 3)) then
                   MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                   MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                   DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                   DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                   if (wr_mode_a /= 2 ) then
                     DOA_zd := (others => 'X');
                     DOPA_zd := (others => 'X');
                   end if;
                 end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S9_S9",
                       InstanceName => ramb16_s9_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 1 =>
              if (VALID_ADDRB) then
                DOB_zd  := MEM(ADDRESS_B);
                DOPB_zd := MEMP(ADDRESS_B);
                WR_B_LATER := true;
                MEM(ADDRESS_B)     := DIB_ipd ;
                MEMP(ADDRESS_B) := DIPB_ipd;
               end if;
              if (ViolationCLKAB = 'X') then
                if (wea_ipd_sampled /= '0') then
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Write_A_Write_B,
                       EntityName => "RAMB16_S9_S9",
                       InstanceName => ramb16_s9_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
                    DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                    if (wr_mode_a /= 2 ) then
                      DOA_zd := (others => 'X');
                      DOPA_zd := (others => 'X');
                    end if;
                  end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S9_S9",
                       InstanceName => ramb16_s9_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;
              end if;

            when 2 =>
              if (VALID_ADDRB) then
                MEM(ADDRESS_B) := DIB_ipd;
                MEMP(ADDRESS_B) := DIPB_ipd;
            end if;
            if (ViolationCLKAB = 'X') then

              if (wea_ipd_sampled /= '0') then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Write_A_Write_B,
                     EntityName => "RAMB16_S9_S9",
                     InstanceName => ramb16_s9_s9'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                    MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                    MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');

                  if (wr_mode_a /= 2 ) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;

                else
                  if ((collision_type = 1) or (collision_type = 3)) then
                    Memory_Collision_Msg
                      (collision_type => Read_A_Write_B,
                       EntityName => "RAMB16_S9_S9",
                       InstanceName => ramb16_s9_s9'path_name,
                       address_a => addra_ipd_sampled,
                       address_b => addrb_ipd_sampled
                       );
                  end if;
                  if ((collision_type = 2) or (collision_type = 3)) then
                    DOA_zd := (others => 'X');
                    DOPA_zd := (others => 'X');
                  end if;
                end if;
              end if;
            when others => null;
          end case;

        else
          if (VALID_ADDRB) then
            DOB_zd  := MEM(ADDRESS_B);
            DOPB_zd := MEMP(ADDRESS_B);
           end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then                
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB16_S9_S9",
                 InstanceName => ramb16_s9_s9'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then                
              DOB_zd (DOB_OV_MSB downto DOB_OV_LSB)    := (others => 'X');
              DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (ssrb_ipd_sampled = '1') then
          DOB_zd  := SRVA_B(7 downto 0);
          DOPB_zd := SRVA_B(8 downto 8);
        end if;
      end if;
    end if;

    if ((WR_A_LATER = true) and (VALID_ADDRA)) then
      MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
      MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd;
    end if;

    if ((WR_B_LATER = true ) and (VALID_ADDRB))then
      MEM(ADDRESS_B) := DIB_ipd;
      MEMP(ADDRESS_B) := DIPB_ipd;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);
    DOA_zd(1)  := ViolationA xor DOA_zd(1);
    DOA_zd(2)  := ViolationA xor DOA_zd(2);
    DOA_zd(3)  := ViolationA xor DOA_zd(3);
    DOA_zd(4)  := ViolationA xor DOA_zd(4);
    DOA_zd(5)  := ViolationA xor DOA_zd(5);
    DOA_zd(6)  := ViolationA xor DOA_zd(6);
    DOA_zd(7)  := ViolationA xor DOA_zd(7);
    DOPA_zd(0) := ViolationA xor DOPA_zd(0);
    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);
    DOPB_zd(0) := ViolationB xor DOPB_zd(0);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(2),
      GlitchData    => DOA_GlitchData2,
      OutSignalName => "DOA(2)",
      OutTemp       => DOA_zd(2),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(3),
      GlitchData    => DOA_GlitchData3,
      OutSignalName => "DOA(3)",
      OutTemp       => DOA_zd(3),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(4),
      GlitchData    => DOA_GlitchData4,
      OutSignalName => "DOA(4)",
      OutTemp       => DOA_zd(4),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(5),
      GlitchData    => DOA_GlitchData5,
      OutSignalName => "DOA(5)",
      OutTemp       => DOA_zd(5),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(6),
      GlitchData    => DOA_GlitchData6,
      OutSignalName => "DOA(6)",
      OutTemp       => DOA_zd(6),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(7),
      GlitchData    => DOA_GlitchData7,
      OutSignalName => "DOA(7)",
      OutTemp       => DOA_zd(7),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPA(0),
      GlitchData    => DOPA_GlitchData0,
      OutSignalName => "DOPA(0)",
      OutTemp       => DOPA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOPB(0),
      GlitchData    => DOPB_GlitchData0,
      OutSignalName => "DOPB(0)",
      OutTemp       => DOPB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPA_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB16_S9_S9_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb4_s1.vhd,v 1.5 2004/08/31 13:40:21 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4K-Bit Data Single Port Block RAM
-- /___/   /\     Filename : RAMB4_S1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:53 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAMB4_S1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB4_S1 is
  
  generic (
    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
    );

  port (
    DO     : out STD_LOGIC_VECTOR (0 downto 0);
    
    ADDR   : in STD_LOGIC_VECTOR (11 downto 0);
    CLK    : in STD_ULOGIC;        
    DI     : in STD_LOGIC_VECTOR (0 downto 0);
    EN     : in STD_ULOGIC;
    RST    : in STD_ULOGIC;        
    WE     : in STD_ULOGIC
    );
end RAMB4_S1;

architecture RAMB4_S1_V of RAMB4_S1 is
  constant length : integer := 4096;
  constant width : integer := 1;
  type Two_D_array_type is array ((length -  1) downto 0) of std_logic_vector((width - 1) downto 0);

  function slv_to_two_D_array(
    SLV : in std_logic_vector)
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((width - 1) downto 0);
  begin
    for i in two_D_array'low to two_D_array'high loop
      intermediate := SLV(((i*width) + (width - 1)) downto (i* width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;
    
begin

  VITALBehavior : process

    variable address : integer;
    variable valid_addr : boolean := FALSE;
    variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                            INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                            INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                            INIT_03 & INIT_02 & INIT_01 & INIT_00);     
    variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv);
    
  begin
    valid_addr := addr_is_valid(addr);
    
    if (valid_addr) then
      address := slv_to_int(addr);
    end if;

    if (rising_edge(CLK)) then
      if (EN = '1') then
        if (RST = '1') then
          DO <= (others => '0') after 100 ps;
        else    
          if (WE = '1') then
            DO <= DI after 100 ps;
          else 
            if (valid_addr) then
              DO <= mem(address) after 100 ps;
            end if;
          end if;
        end if;
        if (WE = '1') then
          if (valid_addr) then
            mem(address) := DI;
          end if;
        end if;  
      end if;
    end if;
    wait on CLK;

  end process VITALBehavior;
end RAMB4_S1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb4_s16.vhd,v 1.5 2004/08/31 13:40:21 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4K-Bit Data Single Port Block RAM
-- /___/   /\     Filename : RAMB4_S16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:53 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAMB4_S16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB4_S16 is

  generic (
    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
  );

  port (
    DO     : out STD_LOGIC_VECTOR (15 downto 0);
        
    ADDR   : in STD_LOGIC_VECTOR (7 downto 0);
    CLK    : in STD_ULOGIC;        
    DI     : in STD_LOGIC_VECTOR (15 downto 0);
    EN     : in STD_ULOGIC;
    RST    : in STD_ULOGIC;        
    WE     : in STD_ULOGIC
    );
end RAMB4_S16;

architecture RAMB4_S16_V of RAMB4_S16 is
  constant length : integer := 256;
  constant width : integer := 16;
  type Two_D_array_type is array ((length -  1) downto 0) of std_logic_vector((width - 1) downto 0);

  function slv_to_two_D_array(
    SLV : in std_logic_vector)
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((width - 1) downto 0);
  begin
    for i in two_D_array'low to two_D_array'high loop
      intermediate := SLV(((i*width) + (width - 1)) downto (i* width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;  
begin

  VITALBehavior : process


    variable address : integer;
    variable valid_addr : boolean := FALSE;
    variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                            INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                            INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                            INIT_03 & INIT_02 & INIT_01 & INIT_00);    
    variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv);    

  begin

    valid_addr := addr_is_valid(addr);

    if (valid_addr) then
        address := slv_to_int(addr);
    end if;

    if (rising_edge(CLK)) then
      if (EN = '1') then
        if (RST = '1') then
          DO <= (others => '0') after 100 ps;
        else    
          if (WE = '1') then
            DO <= DI after 100 ps;
          else 
            if (valid_addr) then
              DO <= mem(address) after 100 ps;
            end if;
          end if;
        end if;
        if (WE = '1') then
          if (valid_addr) then
            mem(address) := DI;
          end if;
        end if;  
      end if;
    end if;
    wait on CLK;
  end process VITALBehavior;
end RAMB4_S16_V;


-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4K-Bit Data Dual Port Block RAM
-- /___/   /\     Filename : RAMB4_S16_S16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
----- CELL ramb4_s16_s16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB4_S16_S16 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(7 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(7 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tpd_CLKA_DOA : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    SIM_COLLISION_CHECK : string := "ALL"

    );

  port(
    DOA   : out std_logic_vector(15 downto 0);
    DOB   : out std_logic_vector(15 downto 0);

    ADDRA : in std_logic_vector(7 downto 0);
    ADDRB : in std_logic_vector(7 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(15 downto 0);
    DIB   : in std_logic_vector(15 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    RSTA  : in std_ulogic;
    RSTB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB4_S16_S16 : entity is true;
end ramb4_s16_s16;

architecture RAMB4_S16_S16_V of RAMB4_S16_S16 is
  attribute VITAL_LEVEL0 of
    RAMB4_S16_S16_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(7 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(15 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal RSTA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(7 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(15 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal RSTB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL : VitalDelayType := 1000 ps;
  constant length_a : integer := 256;
  constant length_b : integer := 256;
  constant width_a : integer := 16;
  constant width_b   : integer := 16;  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    SLV : in std_logic_vector)
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((width_b - 1) downto 0);
  begin
    for i in two_D_array'low to two_D_array'high loop
      intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;    
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 7 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 15 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 7 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 15 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA2_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA3_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA4_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA5_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA6_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA7_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA8_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA9_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA10_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA11_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA12_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA13_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA14_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA15_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_RSTA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB8_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB9_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB10_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB11_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB12_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB13_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB14_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB15_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_RSTB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA : std_ulogic := '0';
    variable PViol_CLKB : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA2_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA3_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA4_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA5_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA6_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA7_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA8_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA9_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA10_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA11_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA12_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA13_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA14_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA15_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB8_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB9_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB10_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB11_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB12_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB13_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB14_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB15_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;
    variable DOA_GlitchData2  : VitalGlitchDataType;
    variable DOA_GlitchData3  : VitalGlitchDataType;
    variable DOA_GlitchData4  : VitalGlitchDataType;
    variable DOA_GlitchData5  : VitalGlitchDataType;
    variable DOA_GlitchData6  : VitalGlitchDataType;
    variable DOA_GlitchData7  : VitalGlitchDataType;
    variable DOA_GlitchData8  : VitalGlitchDataType;
    variable DOA_GlitchData9  : VitalGlitchDataType;
    variable DOA_GlitchData10  : VitalGlitchDataType;
    variable DOA_GlitchData11  : VitalGlitchDataType;
    variable DOA_GlitchData12  : VitalGlitchDataType;
    variable DOA_GlitchData13  : VitalGlitchDataType;
    variable DOA_GlitchData14  : VitalGlitchDataType;
    variable DOA_GlitchData15  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;
    variable DOB_GlitchData8  : VitalGlitchDataType;
    variable DOB_GlitchData9  : VitalGlitchDataType;
    variable DOB_GlitchData10  : VitalGlitchDataType;
    variable DOB_GlitchData11  : VitalGlitchDataType;
    variable DOB_GlitchData12  : VitalGlitchDataType;
    variable DOB_GlitchData13  : VitalGlitchDataType;
    variable DOB_GlitchData14  : VitalGlitchDataType;
    variable DOB_GlitchData15  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                            INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                            INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                            INIT_03 & INIT_02 & INIT_01 & INIT_00);     
    variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv);    


    variable ADDRESS_A      : integer;
    variable ADDRESS_B      : integer;
    variable DOA_OV_LSB     : integer;
    variable DOA_OV_MSB     : integer;
    variable DOA_zd         : std_logic_vector(15 downto 0) := (others => 'X');
    variable DOB_OV_LSB     : integer;
    variable DOB_OV_MSB     : integer;
    variable DOB_zd         : std_logic_vector(15 downto 0) := (others => 'X');
    variable FIRST_TIME     : boolean                       := true;
    variable HAS_OVERLAP    : boolean                       := false;
    variable OLP_LSB        : integer;
    variable OLP_MSB        : integer;
    variable VALID_ADDRA    : boolean                       := false;
    variable VALID_ADDRB    : boolean                       := false;
    variable ViolationA     : std_ulogic                    := '0';
    variable ViolationB     : std_ulogic                    := '0';
    variable ViolationCLKAB : std_ulogic                    := '0';

    variable ADDRA_ipd_sampled : std_logic_vector(7 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTA_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';

    variable ADDRB_ipd_sampled : std_logic_vector(7 downto 0) := (others => 'X');
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';

    variable collision_type : integer := 3;
  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB4_S16_S16",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      DOA <= DOA_zd;
      DOB <= DOB_zd;
      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      RSTA_ipd_sampled  := RSTA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      RSTB_ipd_sampled  := RSTB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTA_CLKA_posedge,
        TimingData     => Tmkr_RSTA_CLKA_posedge,
        TestSignal     => RSTA_ipd,
        TestSignalName => "RSTA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTA_CLKA_posedge_posedge,
        SetupLow       => tsetup_RSTA_CLKA_negedge_posedge,
        HoldLow        => thold_RSTA_CLKA_posedge_posedge,
        HoldHigh       => thold_RSTA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA1_CLKA_posedge,
        TimingData     => Tmkr_DIA1_CLKA_posedge,
        TestSignal     => DIA_ipd(1),
        TestSignalName => "DIA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(1),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA2_CLKA_posedge,
        TimingData     => Tmkr_DIA2_CLKA_posedge,
        TestSignal     => DIA_ipd(2),
        TestSignalName => "DIA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(2),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA3_CLKA_posedge,
        TimingData     => Tmkr_DIA3_CLKA_posedge,
        TestSignal     => DIA_ipd(3),
        TestSignalName => "DIA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(3),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(3),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA4_CLKA_posedge,
        TimingData     => Tmkr_DIA4_CLKA_posedge,
        TestSignal     => DIA_ipd(4),
        TestSignalName => "DIA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(4),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(4),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA5_CLKA_posedge,
        TimingData     => Tmkr_DIA5_CLKA_posedge,
        TestSignal     => DIA_ipd(5),
        TestSignalName => "DIA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(5),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(5),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA6_CLKA_posedge,
        TimingData     => Tmkr_DIA6_CLKA_posedge,
        TestSignal     => DIA_ipd(6),
        TestSignalName => "DIA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(6),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(6),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA7_CLKA_posedge,
        TimingData     => Tmkr_DIA7_CLKA_posedge,
        TestSignal     => DIA_ipd(7),
        TestSignalName => "DIA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(7),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(7),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA8_CLKA_posedge,
        TimingData     => Tmkr_DIA8_CLKA_posedge,
        TestSignal     => DIA_ipd(8),
        TestSignalName => "DIA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(8),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(8),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA9_CLKA_posedge,
        TimingData     => Tmkr_DIA9_CLKA_posedge,
        TestSignal     => DIA_ipd(9),
        TestSignalName => "DIA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(9),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(9),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA10_CLKA_posedge,
        TimingData     => Tmkr_DIA10_CLKA_posedge,
        TestSignal     => DIA_ipd(10),
        TestSignalName => "DIA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(10),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(10),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA11_CLKA_posedge,
        TimingData     => Tmkr_DIA11_CLKA_posedge,
        TestSignal     => DIA_ipd(11),
        TestSignalName => "DIA(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(11),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(11),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(11),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(11),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA12_CLKA_posedge,
        TimingData     => Tmkr_DIA12_CLKA_posedge,
        TestSignal     => DIA_ipd(12),
        TestSignalName => "DIA(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(12),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(12),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(12),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(12),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA13_CLKA_posedge,
        TimingData     => Tmkr_DIA13_CLKA_posedge,
        TestSignal     => DIA_ipd(13),
        TestSignalName => "DIA(13)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(13),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(13),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(13),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(13),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA14_CLKA_posedge,
        TimingData     => Tmkr_DIA14_CLKA_posedge,
        TestSignal     => DIA_ipd(14),
        TestSignalName => "DIA(14)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(14),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(14),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(14),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(14),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTB_CLKB_posedge,
        TimingData     => Tmkr_RSTB_CLKB_posedge,
        TestSignal     => RSTB_ipd,
        TestSignalName => "RSTB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTB_CLKB_posedge_posedge,
        SetupLow       => tsetup_RSTB_CLKB_negedge_posedge,
        HoldLow        => thold_RSTB_CLKB_posedge_posedge,
        HoldHigh       => thold_RSTB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB7_CLKB_posedge,
        TimingData     => Tmkr_DIB7_CLKB_posedge,
        TestSignal     => DIB_ipd(7),
        TestSignalName => "DIB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(7),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(7),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB8_CLKB_posedge,
        TimingData     => Tmkr_DIB8_CLKB_posedge,
        TestSignal     => DIB_ipd(8),
        TestSignalName => "DIB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(8),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(8),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB9_CLKB_posedge,
        TimingData     => Tmkr_DIB9_CLKB_posedge,
        TestSignal     => DIB_ipd(9),
        TestSignalName => "DIB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(9),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(9),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB10_CLKB_posedge,
        TimingData     => Tmkr_DIB10_CLKB_posedge,
        TestSignal     => DIB_ipd(10),
        TestSignalName => "DIB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(10),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(10),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB11_CLKB_posedge,
        TimingData     => Tmkr_DIB11_CLKB_posedge,
        TestSignal     => DIB_ipd(11),
        TestSignalName => "DIB(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(11),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(11),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(11),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(11),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB12_CLKB_posedge,
        TimingData     => Tmkr_DIB12_CLKB_posedge,
        TestSignal     => DIB_ipd(12),
        TestSignalName => "DIB(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(12),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(12),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(12),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(12),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB13_CLKB_posedge,
        TimingData     => Tmkr_DIB13_CLKB_posedge,
        TestSignal     => DIB_ipd(13),
        TestSignalName => "DIB(13)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(13),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(13),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(13),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(13),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB14_CLKB_posedge,
        TimingData     => Tmkr_DIB14_CLKB_posedge,
        TestSignal     => DIB_ipd(14),
        TestSignalName => "DIB(14)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(14),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(14),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(14),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(14),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_DIA2_CLKA_posedge or
                  Tviol_DIA3_CLKA_posedge or
                  Tviol_DIA4_CLKA_posedge or
                  Tviol_DIA5_CLKA_posedge or
                  Tviol_DIA6_CLKA_posedge or
                  Tviol_DIA7_CLKA_posedge or
                  Tviol_DIA8_CLKA_posedge or
                  Tviol_DIA9_CLKA_posedge or
                  Tviol_DIA10_CLKA_posedge or
                  Tviol_DIA11_CLKA_posedge or
                  Tviol_DIA12_CLKA_posedge or
                  Tviol_DIA13_CLKA_posedge or
                  Tviol_DIA14_CLKA_posedge or
                  Tviol_DIA15_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_RSTA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_DIB8_CLKB_posedge or
                  Tviol_DIB9_CLKB_posedge or
                  Tviol_DIB10_CLKB_posedge or
                  Tviol_DIB11_CLKB_posedge or
                  Tviol_DIB12_CLKB_posedge or
                  Tviol_DIB13_CLKB_posedge or
                  Tviol_DIB14_CLKB_posedge or
                  Tviol_DIB15_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_RSTB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB := '0';

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKB_CLKA_posedge,
        TimingData     => Tmkr_CLKB_CLKA_posedge,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKA_CLKB_posedge,
        TimingData     => Tmkr_CLKA_CLKB_posedge,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S16_S16",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
    end if;

    ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge;

    if (ENA_ipd_sampled = '1') then
      if (rising_edge(CLKA_ipd)) then
        if (WEA_ipd_sampled = '1') then
          if (VALID_ADDRA) then
            MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
          end if;
          DOA_zd                                                 := DIA_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEB_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S16_S16",
                   InstanceName => ramb4_s16_s16'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                DOA_zd := (others => 'X');

                if (RSTB_ipd_sampled = '0' ) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;

            else
              if (RSTB_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_B_Write_A,
                     EntityName => "RAMB4_S16_S16",
                     InstanceName => ramb4_s16_s16'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRA) then
            DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));                        
          end if;
          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB4_S16_S16",
                 InstanceName => ramb4_s16_s16'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTA_ipd_sampled = '1') then
          DOA_zd := (others => '0');
        end if;
      end if;
    end if;

    if (ENB_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (WEB_ipd_sampled = '1') then
          if (VALID_ADDRB) then
            MEM(ADDRESS_B) := DIB_ipd;
          end if;
          DOB_zd                                                 := DIB_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEA_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S16_S16",
                   InstanceName => ramb4_s16_s16'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                if (RSTA_ipd_sampled = '0' ) then
                  DOA_zd := (others => 'X');
                end if;
              end if;

            else
              if (RSTA_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_A_Write_B,
                     EntityName => "RAMB4_S16_S16",
                     InstanceName => ramb4_s16_s16'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOA_zd := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRB) then
            DOB_zd := MEM(ADDRESS_B);
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB4_S16_S16",
                 InstanceName => ramb4_s16_s16'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTB_ipd_sampled = '1') then
          DOB_zd := (others => '0');
        end if;
      end if;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);
    DOA_zd(1)  := ViolationA xor DOA_zd(1);
    DOA_zd(2)  := ViolationA xor DOA_zd(2);
    DOA_zd(3)  := ViolationA xor DOA_zd(3);
    DOA_zd(4)  := ViolationA xor DOA_zd(4);
    DOA_zd(5)  := ViolationA xor DOA_zd(5);
    DOA_zd(6)  := ViolationA xor DOA_zd(6);
    DOA_zd(7)  := ViolationA xor DOA_zd(7);
    DOA_zd(8)  := ViolationA xor DOA_zd(8);
    DOA_zd(9)  := ViolationA xor DOA_zd(9);
    DOA_zd(10)  := ViolationA xor DOA_zd(10);
    DOA_zd(11)  := ViolationA xor DOA_zd(11);
    DOA_zd(12)  := ViolationA xor DOA_zd(12);
    DOA_zd(13)  := ViolationA xor DOA_zd(13);
    DOA_zd(14)  := ViolationA xor DOA_zd(14);
    DOA_zd(15)  := ViolationA xor DOA_zd(15);

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);
    DOB_zd(8)  := ViolationB xor DOB_zd(8);
    DOB_zd(9)  := ViolationB xor DOB_zd(9);
    DOB_zd(10)  := ViolationB xor DOB_zd(10);
    DOB_zd(11)  := ViolationB xor DOB_zd(11);
    DOB_zd(12)  := ViolationB xor DOB_zd(12);
    DOB_zd(13)  := ViolationB xor DOB_zd(13);
    DOB_zd(14)  := ViolationB xor DOB_zd(14);
    DOB_zd(15)  := ViolationB xor DOB_zd(15);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(2),
      GlitchData    => DOA_GlitchData2,
      OutSignalName => "DOA(2)",
      OutTemp       => DOA_zd(2),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(3),
      GlitchData    => DOA_GlitchData3,
      OutSignalName => "DOA(3)",
      OutTemp       => DOA_zd(3),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(4),
      GlitchData    => DOA_GlitchData4,
      OutSignalName => "DOA(4)",
      OutTemp       => DOA_zd(4),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(5),
      GlitchData    => DOA_GlitchData5,
      OutSignalName => "DOA(5)",
      OutTemp       => DOA_zd(5),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(6),
      GlitchData    => DOA_GlitchData6,
      OutSignalName => "DOA(6)",
      OutTemp       => DOA_zd(6),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(7),
      GlitchData    => DOA_GlitchData7,
      OutSignalName => "DOA(7)",
      OutTemp       => DOA_zd(7),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(8),
      GlitchData    => DOA_GlitchData8,
      OutSignalName => "DOA(8)",
      OutTemp       => DOA_zd(8),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(8), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(9),
      GlitchData    => DOA_GlitchData9,
      OutSignalName => "DOA(9)",
      OutTemp       => DOA_zd(9),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(9), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(10),
      GlitchData    => DOA_GlitchData10,
      OutSignalName => "DOA(10)",
      OutTemp       => DOA_zd(10),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(10), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(11),
      GlitchData    => DOA_GlitchData11,
      OutSignalName => "DOA(11)",
      OutTemp       => DOA_zd(11),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(11), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(12),
      GlitchData    => DOA_GlitchData12,
      OutSignalName => "DOA(12)",
      OutTemp       => DOA_zd(12),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(12), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(13),
      GlitchData    => DOA_GlitchData13,
      OutSignalName => "DOA(13)",
      OutTemp       => DOA_zd(13),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(13), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(14),
      GlitchData    => DOA_GlitchData14,
      OutSignalName => "DOA(14)",
      OutTemp       => DOA_zd(14),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(14), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(15),
      GlitchData    => DOA_GlitchData15,
      OutSignalName => "DOA(15)",
      OutTemp       => DOA_zd(15),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(15), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(8),
      GlitchData    => DOB_GlitchData8,
      OutSignalName => "DOB(8)",
      OutTemp       => DOB_zd(8),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(9),
      GlitchData    => DOB_GlitchData9,
      OutSignalName => "DOB(9)",
      OutTemp       => DOB_zd(9),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(10),
      GlitchData    => DOB_GlitchData10,
      OutSignalName => "DOB(10)",
      OutTemp       => DOB_zd(10),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(11),
      GlitchData    => DOB_GlitchData11,
      OutSignalName => "DOB(11)",
      OutTemp       => DOB_zd(11),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(12),
      GlitchData    => DOB_GlitchData12,
      OutSignalName => "DOB(12)",
      OutTemp       => DOB_zd(12),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(13),
      GlitchData    => DOB_GlitchData13,
      OutSignalName => "DOB(13)",
      OutTemp       => DOB_zd(13),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(14),
      GlitchData    => DOB_GlitchData14,
      OutSignalName => "DOB(14)",
      OutTemp       => DOB_zd(14),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(15),
      GlitchData    => DOB_GlitchData15,
      OutSignalName => "DOB(15)",
      OutTemp       => DOB_zd(15),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB4_S16_S16_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4K-Bit Data Dual Port Block RAM
-- /___/   /\     Filename : RAMB4_S1_S1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
----- CELL ramb4_s1_s1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB4_S1_S1 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(11 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(11 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tpd_CLKA_DOA : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    SIM_COLLISION_CHECK : string := "ALL"

    );

  port(
    DOA   : out std_logic_vector(0 downto 0);
    DOB   : out std_logic_vector(0 downto 0);

    ADDRA : in std_logic_vector(11 downto 0);
    ADDRB : in std_logic_vector(11 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(0 downto 0);
    DIB   : in std_logic_vector(0 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    RSTA  : in std_ulogic;
    RSTB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB4_S1_S1 : entity is true;
end ramb4_s1_s1;

architecture RAMB4_S1_S1_V of RAMB4_S1_S1 is
  attribute VITAL_LEVEL0 of
    RAMB4_S1_S1_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(11 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(0 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal RSTA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(11 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(0 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal RSTB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL : VitalDelayType := 1000 ps;
  constant length_a : integer := 4096;
  constant length_b : integer := 4096;
  constant width_a : integer := 1;
  constant width_b   : integer := 1;  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    SLV : in std_logic_vector)
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((width_b - 1) downto 0);
  begin
    for i in two_D_array'low to two_D_array'high loop
      intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;    
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 11 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 0 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 11 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 0 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_RSTA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB11_CLKB_posedge : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_RSTB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA : std_ulogic := '0';
    variable PViol_CLKB : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                            INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                            INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                            INIT_03 & INIT_02 & INIT_01 & INIT_00);     
    variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv);    


    variable ADDRESS_A      : integer;
    variable ADDRESS_B      : integer;
    variable DOA_OV_LSB     : integer;
    variable DOA_OV_MSB     : integer;
    variable DOA_zd         : std_logic_vector(0 downto 0) := (others => 'X');
    variable DOB_OV_LSB     : integer;
    variable DOB_OV_MSB     : integer;
    variable DOB_zd         : std_logic_vector(0 downto 0) := (others => 'X');
    variable FIRST_TIME     : boolean                       := true;
    variable HAS_OVERLAP    : boolean                       := false;
    variable OLP_LSB        : integer;
    variable OLP_MSB        : integer;
    variable VALID_ADDRA    : boolean                       := false;
    variable VALID_ADDRB    : boolean                       := false;
    variable ViolationA     : std_ulogic                    := '0';
    variable ViolationB     : std_ulogic                    := '0';
    variable ViolationCLKAB : std_ulogic                    := '0';

    variable ADDRA_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTA_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';

    variable ADDRB_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X');
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';

    variable collision_type : integer := 3;
  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB4_S1_S1",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      DOA <= DOA_zd;
      DOB <= DOB_zd;
      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      RSTA_ipd_sampled  := RSTA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      RSTB_ipd_sampled  := RSTB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTA_CLKA_posedge,
        TimingData     => Tmkr_RSTA_CLKA_posedge,
        TestSignal     => RSTA_ipd,
        TestSignalName => "RSTA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTA_CLKA_posedge_posedge,
        SetupLow       => tsetup_RSTA_CLKA_negedge_posedge,
        HoldLow        => thold_RSTA_CLKA_posedge_posedge,
        HoldHigh       => thold_RSTA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA10_CLKA_posedge,
        TimingData     => Tmkr_ADDRA10_CLKA_posedge,
        TestSignal     => ADDRA_ipd(10),
        TestSignalName => "ADDRA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(10),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(10),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTB_CLKB_posedge,
        TimingData     => Tmkr_RSTB_CLKB_posedge,
        TestSignal     => RSTB_ipd,
        TestSignalName => "RSTB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTB_CLKB_posedge_posedge,
        SetupLow       => tsetup_RSTB_CLKB_negedge_posedge,
        HoldLow        => thold_RSTB_CLKB_posedge_posedge,
        HoldHigh       => thold_RSTB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB9_CLKB_posedge,
        TimingData     => Tmkr_ADDRB9_CLKB_posedge,
        TestSignal     => ADDRB_ipd(9),
        TestSignalName => "ADDRB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(9),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(9),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB10_CLKB_posedge,
        TimingData     => Tmkr_ADDRB10_CLKB_posedge,
        TestSignal     => ADDRB_ipd(10),
        TestSignalName => "ADDRB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(10),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(10),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_ADDRA11_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_RSTA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_ADDRB10_CLKB_posedge or
                  Tviol_ADDRB11_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_RSTB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB := '0';

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKB_CLKA_posedge,
        TimingData     => Tmkr_CLKB_CLKA_posedge,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKA_CLKB_posedge,
        TimingData     => Tmkr_CLKA_CLKB_posedge,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S1",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
    end if;

    ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge;

    if (ENA_ipd_sampled = '1') then
      if (rising_edge(CLKA_ipd)) then
        if (WEA_ipd_sampled = '1') then
          if (VALID_ADDRA) then
            MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
          end if;
          DOA_zd                                                 := DIA_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEB_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S1_S1",
                   InstanceName => ramb4_s1_s1'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                DOA_zd := (others => 'X');

                if (RSTB_ipd_sampled = '0' ) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;

            else
              if (RSTB_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_B_Write_A,
                     EntityName => "RAMB4_S1_S1",
                     InstanceName => ramb4_s1_s1'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRA) then
            DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));                        
          end if;
          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB4_S1_S1",
                 InstanceName => ramb4_s1_s1'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTA_ipd_sampled = '1') then
          DOA_zd := (others => '0');
        end if;
      end if;
    end if;

    if (ENB_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (WEB_ipd_sampled = '1') then
          if (VALID_ADDRB) then
            MEM(ADDRESS_B) := DIB_ipd;
          end if;
          DOB_zd                                                 := DIB_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEA_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S1_S1",
                   InstanceName => ramb4_s1_s1'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                if (RSTA_ipd_sampled = '0' ) then
                  DOA_zd := (others => 'X');
                end if;
              end if;

            else
              if (RSTA_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_A_Write_B,
                     EntityName => "RAMB4_S1_S1",
                     InstanceName => ramb4_s1_s1'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOA_zd := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRB) then
            DOB_zd := MEM(ADDRESS_B);
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB4_S1_S1",
                 InstanceName => ramb4_s1_s1'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTB_ipd_sampled = '1') then
          DOB_zd := (others => '0');
        end if;
      end if;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);

    DOB_zd(0)  := ViolationB xor DOB_zd(0);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB4_S1_S1_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4K-Bit Data Dual Port Block RAM
-- /___/   /\     Filename : RAMB4_S1_S16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
----- CELL ramb4_s1_s16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB4_S1_S16 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(11 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(7 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tpd_CLKA_DOA : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    SIM_COLLISION_CHECK : string := "ALL"

    );

  port(
    DOA   : out std_logic_vector(0 downto 0);
    DOB   : out std_logic_vector(15 downto 0);

    ADDRA : in std_logic_vector(11 downto 0);
    ADDRB : in std_logic_vector(7 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(0 downto 0);
    DIB   : in std_logic_vector(15 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    RSTA  : in std_ulogic;
    RSTB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB4_S1_S16 : entity is true;
end ramb4_s1_s16;

architecture RAMB4_S1_S16_V of RAMB4_S1_S16 is
  attribute VITAL_LEVEL0 of
    RAMB4_S1_S16_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(11 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(0 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal RSTA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(7 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(15 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal RSTB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL : VitalDelayType := 1000 ps;
  constant length_a : integer := 4096;
  constant length_b : integer := 256;
  constant width_a : integer := 1;
  constant width_b   : integer := 16;  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    SLV : in std_logic_vector)
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((width_b - 1) downto 0);
  begin
    for i in two_D_array'low to two_D_array'high loop
      intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;    
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 11 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 0 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 7 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 15 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_RSTA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB8_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB9_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB10_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB11_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB12_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB13_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB14_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB15_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_RSTB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA : std_ulogic := '0';
    variable PViol_CLKB : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB8_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB9_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB10_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB11_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB12_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB13_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB14_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB15_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;
    variable DOB_GlitchData8  : VitalGlitchDataType;
    variable DOB_GlitchData9  : VitalGlitchDataType;
    variable DOB_GlitchData10  : VitalGlitchDataType;
    variable DOB_GlitchData11  : VitalGlitchDataType;
    variable DOB_GlitchData12  : VitalGlitchDataType;
    variable DOB_GlitchData13  : VitalGlitchDataType;
    variable DOB_GlitchData14  : VitalGlitchDataType;
    variable DOB_GlitchData15  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                            INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                            INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                            INIT_03 & INIT_02 & INIT_01 & INIT_00);     
    variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv);    


    variable ADDRESS_A      : integer;
    variable ADDRESS_B      : integer;
    variable DOA_OV_LSB     : integer;
    variable DOA_OV_MSB     : integer;
    variable DOA_zd         : std_logic_vector(0 downto 0) := (others => 'X');
    variable DOB_OV_LSB     : integer;
    variable DOB_OV_MSB     : integer;
    variable DOB_zd         : std_logic_vector(15 downto 0) := (others => 'X');
    variable FIRST_TIME     : boolean                       := true;
    variable HAS_OVERLAP    : boolean                       := false;
    variable OLP_LSB        : integer;
    variable OLP_MSB        : integer;
    variable VALID_ADDRA    : boolean                       := false;
    variable VALID_ADDRB    : boolean                       := false;
    variable ViolationA     : std_ulogic                    := '0';
    variable ViolationB     : std_ulogic                    := '0';
    variable ViolationCLKAB : std_ulogic                    := '0';

    variable ADDRA_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTA_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';

    variable ADDRB_ipd_sampled : std_logic_vector(7 downto 0) := (others => 'X');
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';

    variable collision_type : integer := 3;
  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB4_S1_S16",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      DOA <= DOA_zd;
      DOB <= DOB_zd;
      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      RSTA_ipd_sampled  := RSTA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      RSTB_ipd_sampled  := RSTB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTA_CLKA_posedge,
        TimingData     => Tmkr_RSTA_CLKA_posedge,
        TestSignal     => RSTA_ipd,
        TestSignalName => "RSTA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTA_CLKA_posedge_posedge,
        SetupLow       => tsetup_RSTA_CLKA_negedge_posedge,
        HoldLow        => thold_RSTA_CLKA_posedge_posedge,
        HoldHigh       => thold_RSTA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA10_CLKA_posedge,
        TimingData     => Tmkr_ADDRA10_CLKA_posedge,
        TestSignal     => ADDRA_ipd(10),
        TestSignalName => "ADDRA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(10),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(10),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTB_CLKB_posedge,
        TimingData     => Tmkr_RSTB_CLKB_posedge,
        TestSignal     => RSTB_ipd,
        TestSignalName => "RSTB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTB_CLKB_posedge_posedge,
        SetupLow       => tsetup_RSTB_CLKB_negedge_posedge,
        HoldLow        => thold_RSTB_CLKB_posedge_posedge,
        HoldHigh       => thold_RSTB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB7_CLKB_posedge,
        TimingData     => Tmkr_DIB7_CLKB_posedge,
        TestSignal     => DIB_ipd(7),
        TestSignalName => "DIB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(7),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(7),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB8_CLKB_posedge,
        TimingData     => Tmkr_DIB8_CLKB_posedge,
        TestSignal     => DIB_ipd(8),
        TestSignalName => "DIB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(8),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(8),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB9_CLKB_posedge,
        TimingData     => Tmkr_DIB9_CLKB_posedge,
        TestSignal     => DIB_ipd(9),
        TestSignalName => "DIB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(9),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(9),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB10_CLKB_posedge,
        TimingData     => Tmkr_DIB10_CLKB_posedge,
        TestSignal     => DIB_ipd(10),
        TestSignalName => "DIB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(10),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(10),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB11_CLKB_posedge,
        TimingData     => Tmkr_DIB11_CLKB_posedge,
        TestSignal     => DIB_ipd(11),
        TestSignalName => "DIB(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(11),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(11),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(11),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(11),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB12_CLKB_posedge,
        TimingData     => Tmkr_DIB12_CLKB_posedge,
        TestSignal     => DIB_ipd(12),
        TestSignalName => "DIB(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(12),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(12),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(12),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(12),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB13_CLKB_posedge,
        TimingData     => Tmkr_DIB13_CLKB_posedge,
        TestSignal     => DIB_ipd(13),
        TestSignalName => "DIB(13)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(13),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(13),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(13),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(13),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB14_CLKB_posedge,
        TimingData     => Tmkr_DIB14_CLKB_posedge,
        TestSignal     => DIB_ipd(14),
        TestSignalName => "DIB(14)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(14),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(14),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(14),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(14),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_ADDRA11_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_RSTA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_DIB8_CLKB_posedge or
                  Tviol_DIB9_CLKB_posedge or
                  Tviol_DIB10_CLKB_posedge or
                  Tviol_DIB11_CLKB_posedge or
                  Tviol_DIB12_CLKB_posedge or
                  Tviol_DIB13_CLKB_posedge or
                  Tviol_DIB14_CLKB_posedge or
                  Tviol_DIB15_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_RSTB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB := '0';

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKB_CLKA_posedge,
        TimingData     => Tmkr_CLKB_CLKA_posedge,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKA_CLKB_posedge,
        TimingData     => Tmkr_CLKA_CLKB_posedge,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S16",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
    end if;

    ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge;

    if (ENA_ipd_sampled = '1') then
      if (rising_edge(CLKA_ipd)) then
        if (WEA_ipd_sampled = '1') then
          if (VALID_ADDRA) then
            MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
          end if;
          DOA_zd                                                 := DIA_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEB_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S1_S16",
                   InstanceName => ramb4_s1_s16'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                DOA_zd := (others => 'X');

                if (RSTB_ipd_sampled = '0' ) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;

            else
              if (RSTB_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_B_Write_A,
                     EntityName => "RAMB4_S1_S16",
                     InstanceName => ramb4_s1_s16'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRA) then
            DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));                        
          end if;
          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB4_S1_S16",
                 InstanceName => ramb4_s1_s16'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTA_ipd_sampled = '1') then
          DOA_zd := (others => '0');
        end if;
      end if;
    end if;

    if (ENB_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (WEB_ipd_sampled = '1') then
          if (VALID_ADDRB) then
            MEM(ADDRESS_B) := DIB_ipd;
          end if;
          DOB_zd                                                 := DIB_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEA_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S1_S16",
                   InstanceName => ramb4_s1_s16'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                if (RSTA_ipd_sampled = '0' ) then
                  DOA_zd := (others => 'X');
                end if;
              end if;

            else
              if (RSTA_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_A_Write_B,
                     EntityName => "RAMB4_S1_S16",
                     InstanceName => ramb4_s1_s16'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOA_zd := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRB) then
            DOB_zd := MEM(ADDRESS_B);
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB4_S1_S16",
                 InstanceName => ramb4_s1_s16'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTB_ipd_sampled = '1') then
          DOB_zd := (others => '0');
        end if;
      end if;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);
    DOB_zd(8)  := ViolationB xor DOB_zd(8);
    DOB_zd(9)  := ViolationB xor DOB_zd(9);
    DOB_zd(10)  := ViolationB xor DOB_zd(10);
    DOB_zd(11)  := ViolationB xor DOB_zd(11);
    DOB_zd(12)  := ViolationB xor DOB_zd(12);
    DOB_zd(13)  := ViolationB xor DOB_zd(13);
    DOB_zd(14)  := ViolationB xor DOB_zd(14);
    DOB_zd(15)  := ViolationB xor DOB_zd(15);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(8),
      GlitchData    => DOB_GlitchData8,
      OutSignalName => "DOB(8)",
      OutTemp       => DOB_zd(8),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(9),
      GlitchData    => DOB_GlitchData9,
      OutSignalName => "DOB(9)",
      OutTemp       => DOB_zd(9),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(10),
      GlitchData    => DOB_GlitchData10,
      OutSignalName => "DOB(10)",
      OutTemp       => DOB_zd(10),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(11),
      GlitchData    => DOB_GlitchData11,
      OutSignalName => "DOB(11)",
      OutTemp       => DOB_zd(11),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(12),
      GlitchData    => DOB_GlitchData12,
      OutSignalName => "DOB(12)",
      OutTemp       => DOB_zd(12),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(13),
      GlitchData    => DOB_GlitchData13,
      OutSignalName => "DOB(13)",
      OutTemp       => DOB_zd(13),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(14),
      GlitchData    => DOB_GlitchData14,
      OutSignalName => "DOB(14)",
      OutTemp       => DOB_zd(14),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(15),
      GlitchData    => DOB_GlitchData15,
      OutSignalName => "DOB(15)",
      OutTemp       => DOB_zd(15),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB4_S1_S16_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4K-Bit Data Dual Port Block RAM
-- /___/   /\     Filename : RAMB4_S1_S2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
----- CELL ramb4_s1_s2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB4_S1_S2 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(11 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(10 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tpd_CLKA_DOA : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    SIM_COLLISION_CHECK : string := "ALL"

    );

  port(
    DOA   : out std_logic_vector(0 downto 0);
    DOB   : out std_logic_vector(1 downto 0);

    ADDRA : in std_logic_vector(11 downto 0);
    ADDRB : in std_logic_vector(10 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(0 downto 0);
    DIB   : in std_logic_vector(1 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    RSTA  : in std_ulogic;
    RSTB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB4_S1_S2 : entity is true;
end ramb4_s1_s2;

architecture RAMB4_S1_S2_V of RAMB4_S1_S2 is
  attribute VITAL_LEVEL0 of
    RAMB4_S1_S2_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(11 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(0 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal RSTA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(10 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(1 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal RSTB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL : VitalDelayType := 1000 ps;
  constant length_a : integer := 4096;
  constant length_b : integer := 2048;
  constant width_a : integer := 1;
  constant width_b   : integer := 2;  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    SLV : in std_logic_vector)
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((width_b - 1) downto 0);
  begin
    for i in two_D_array'low to two_D_array'high loop
      intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;    
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 11 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 0 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 10 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 1 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_RSTA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_RSTB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA : std_ulogic := '0';
    variable PViol_CLKB : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                            INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                            INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                            INIT_03 & INIT_02 & INIT_01 & INIT_00);     
    variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv);    


    variable ADDRESS_A      : integer;
    variable ADDRESS_B      : integer;
    variable DOA_OV_LSB     : integer;
    variable DOA_OV_MSB     : integer;
    variable DOA_zd         : std_logic_vector(0 downto 0) := (others => 'X');
    variable DOB_OV_LSB     : integer;
    variable DOB_OV_MSB     : integer;
    variable DOB_zd         : std_logic_vector(1 downto 0) := (others => 'X');
    variable FIRST_TIME     : boolean                       := true;
    variable HAS_OVERLAP    : boolean                       := false;
    variable OLP_LSB        : integer;
    variable OLP_MSB        : integer;
    variable VALID_ADDRA    : boolean                       := false;
    variable VALID_ADDRB    : boolean                       := false;
    variable ViolationA     : std_ulogic                    := '0';
    variable ViolationB     : std_ulogic                    := '0';
    variable ViolationCLKAB : std_ulogic                    := '0';

    variable ADDRA_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTA_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';

    variable ADDRB_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X');
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';

    variable collision_type : integer := 3;
  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB4_S1_S2",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      DOA <= DOA_zd;
      DOB <= DOB_zd;
      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      RSTA_ipd_sampled  := RSTA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      RSTB_ipd_sampled  := RSTB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTA_CLKA_posedge,
        TimingData     => Tmkr_RSTA_CLKA_posedge,
        TestSignal     => RSTA_ipd,
        TestSignalName => "RSTA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTA_CLKA_posedge_posedge,
        SetupLow       => tsetup_RSTA_CLKA_negedge_posedge,
        HoldLow        => thold_RSTA_CLKA_posedge_posedge,
        HoldHigh       => thold_RSTA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA10_CLKA_posedge,
        TimingData     => Tmkr_ADDRA10_CLKA_posedge,
        TestSignal     => ADDRA_ipd(10),
        TestSignalName => "ADDRA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(10),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(10),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTB_CLKB_posedge,
        TimingData     => Tmkr_RSTB_CLKB_posedge,
        TestSignal     => RSTB_ipd,
        TestSignalName => "RSTB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTB_CLKB_posedge_posedge,
        SetupLow       => tsetup_RSTB_CLKB_negedge_posedge,
        HoldLow        => thold_RSTB_CLKB_posedge_posedge,
        HoldHigh       => thold_RSTB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB9_CLKB_posedge,
        TimingData     => Tmkr_ADDRB9_CLKB_posedge,
        TestSignal     => ADDRB_ipd(9),
        TestSignalName => "ADDRB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(9),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(9),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_ADDRA11_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_RSTA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_ADDRB10_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_RSTB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB := '0';

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKB_CLKA_posedge,
        TimingData     => Tmkr_CLKB_CLKA_posedge,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKA_CLKB_posedge,
        TimingData     => Tmkr_CLKA_CLKB_posedge,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S2",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
    end if;

    ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge;

    if (ENA_ipd_sampled = '1') then
      if (rising_edge(CLKA_ipd)) then
        if (WEA_ipd_sampled = '1') then
          if (VALID_ADDRA) then
            MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
          end if;
          DOA_zd                                                 := DIA_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEB_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S1_S2",
                   InstanceName => ramb4_s1_s2'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                DOA_zd := (others => 'X');

                if (RSTB_ipd_sampled = '0' ) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;

            else
              if (RSTB_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_B_Write_A,
                     EntityName => "RAMB4_S1_S2",
                     InstanceName => ramb4_s1_s2'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRA) then
            DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));                        
          end if;
          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB4_S1_S2",
                 InstanceName => ramb4_s1_s2'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTA_ipd_sampled = '1') then
          DOA_zd := (others => '0');
        end if;
      end if;
    end if;

    if (ENB_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (WEB_ipd_sampled = '1') then
          if (VALID_ADDRB) then
            MEM(ADDRESS_B) := DIB_ipd;
          end if;
          DOB_zd                                                 := DIB_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEA_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S1_S2",
                   InstanceName => ramb4_s1_s2'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                if (RSTA_ipd_sampled = '0' ) then
                  DOA_zd := (others => 'X');
                end if;
              end if;

            else
              if (RSTA_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_A_Write_B,
                     EntityName => "RAMB4_S1_S2",
                     InstanceName => ramb4_s1_s2'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOA_zd := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRB) then
            DOB_zd := MEM(ADDRESS_B);
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB4_S1_S2",
                 InstanceName => ramb4_s1_s2'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTB_ipd_sampled = '1') then
          DOB_zd := (others => '0');
        end if;
      end if;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB4_S1_S2_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4K-Bit Data Dual Port Block RAM
-- /___/   /\     Filename : RAMB4_S1_S4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
----- CELL ramb4_s1_s4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB4_S1_S4 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(11 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(9 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tpd_CLKA_DOA : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    SIM_COLLISION_CHECK : string := "ALL"

    );

  port(
    DOA   : out std_logic_vector(0 downto 0);
    DOB   : out std_logic_vector(3 downto 0);

    ADDRA : in std_logic_vector(11 downto 0);
    ADDRB : in std_logic_vector(9 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(0 downto 0);
    DIB   : in std_logic_vector(3 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    RSTA  : in std_ulogic;
    RSTB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB4_S1_S4 : entity is true;
end ramb4_s1_s4;

architecture RAMB4_S1_S4_V of RAMB4_S1_S4 is
  attribute VITAL_LEVEL0 of
    RAMB4_S1_S4_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(11 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(0 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal RSTA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(9 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(3 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal RSTB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL : VitalDelayType := 1000 ps;
  constant length_a : integer := 4096;
  constant length_b : integer := 1024;
  constant width_a : integer := 1;
  constant width_b   : integer := 4;  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    SLV : in std_logic_vector)
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((width_b - 1) downto 0);
  begin
    for i in two_D_array'low to two_D_array'high loop
      intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;    
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 11 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 0 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 9 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 3 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_RSTA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_RSTB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA : std_ulogic := '0';
    variable PViol_CLKB : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                            INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                            INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                            INIT_03 & INIT_02 & INIT_01 & INIT_00);     
    variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv);    


    variable ADDRESS_A      : integer;
    variable ADDRESS_B      : integer;
    variable DOA_OV_LSB     : integer;
    variable DOA_OV_MSB     : integer;
    variable DOA_zd         : std_logic_vector(0 downto 0) := (others => 'X');
    variable DOB_OV_LSB     : integer;
    variable DOB_OV_MSB     : integer;
    variable DOB_zd         : std_logic_vector(3 downto 0) := (others => 'X');
    variable FIRST_TIME     : boolean                       := true;
    variable HAS_OVERLAP    : boolean                       := false;
    variable OLP_LSB        : integer;
    variable OLP_MSB        : integer;
    variable VALID_ADDRA    : boolean                       := false;
    variable VALID_ADDRB    : boolean                       := false;
    variable ViolationA     : std_ulogic                    := '0';
    variable ViolationB     : std_ulogic                    := '0';
    variable ViolationCLKAB : std_ulogic                    := '0';

    variable ADDRA_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTA_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';

    variable ADDRB_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X');
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';

    variable collision_type : integer := 3;
  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB4_S1_S4",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      DOA <= DOA_zd;
      DOB <= DOB_zd;
      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      RSTA_ipd_sampled  := RSTA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      RSTB_ipd_sampled  := RSTB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTA_CLKA_posedge,
        TimingData     => Tmkr_RSTA_CLKA_posedge,
        TestSignal     => RSTA_ipd,
        TestSignalName => "RSTA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTA_CLKA_posedge_posedge,
        SetupLow       => tsetup_RSTA_CLKA_negedge_posedge,
        HoldLow        => thold_RSTA_CLKA_posedge_posedge,
        HoldHigh       => thold_RSTA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA10_CLKA_posedge,
        TimingData     => Tmkr_ADDRA10_CLKA_posedge,
        TestSignal     => ADDRA_ipd(10),
        TestSignalName => "ADDRA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(10),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(10),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTB_CLKB_posedge,
        TimingData     => Tmkr_RSTB_CLKB_posedge,
        TestSignal     => RSTB_ipd,
        TestSignalName => "RSTB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTB_CLKB_posedge_posedge,
        SetupLow       => tsetup_RSTB_CLKB_negedge_posedge,
        HoldLow        => thold_RSTB_CLKB_posedge_posedge,
        HoldHigh       => thold_RSTB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_ADDRA11_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_RSTA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_RSTB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB := '0';

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKB_CLKA_posedge,
        TimingData     => Tmkr_CLKB_CLKA_posedge,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKA_CLKB_posedge,
        TimingData     => Tmkr_CLKA_CLKB_posedge,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S4",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
    end if;

    ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge;

    if (ENA_ipd_sampled = '1') then
      if (rising_edge(CLKA_ipd)) then
        if (WEA_ipd_sampled = '1') then
          if (VALID_ADDRA) then
            MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
          end if;
          DOA_zd                                                 := DIA_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEB_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S1_S4",
                   InstanceName => ramb4_s1_s4'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                DOA_zd := (others => 'X');

                if (RSTB_ipd_sampled = '0' ) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;

            else
              if (RSTB_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_B_Write_A,
                     EntityName => "RAMB4_S1_S4",
                     InstanceName => ramb4_s1_s4'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRA) then
            DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));                        
          end if;
          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB4_S1_S4",
                 InstanceName => ramb4_s1_s4'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTA_ipd_sampled = '1') then
          DOA_zd := (others => '0');
        end if;
      end if;
    end if;

    if (ENB_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (WEB_ipd_sampled = '1') then
          if (VALID_ADDRB) then
            MEM(ADDRESS_B) := DIB_ipd;
          end if;
          DOB_zd                                                 := DIB_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEA_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S1_S4",
                   InstanceName => ramb4_s1_s4'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                if (RSTA_ipd_sampled = '0' ) then
                  DOA_zd := (others => 'X');
                end if;
              end if;

            else
              if (RSTA_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_A_Write_B,
                     EntityName => "RAMB4_S1_S4",
                     InstanceName => ramb4_s1_s4'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOA_zd := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRB) then
            DOB_zd := MEM(ADDRESS_B);
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB4_S1_S4",
                 InstanceName => ramb4_s1_s4'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTB_ipd_sampled = '1') then
          DOB_zd := (others => '0');
        end if;
      end if;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB4_S1_S4_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4K-Bit Data Dual Port Block RAM
-- /___/   /\     Filename : RAMB4_S1_S8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
----- CELL ramb4_s1_s8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB4_S1_S8 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(11 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(8 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tpd_CLKA_DOA : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(0 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    SIM_COLLISION_CHECK : string := "ALL"

    );

  port(
    DOA   : out std_logic_vector(0 downto 0);
    DOB   : out std_logic_vector(7 downto 0);

    ADDRA : in std_logic_vector(11 downto 0);
    ADDRB : in std_logic_vector(8 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(0 downto 0);
    DIB   : in std_logic_vector(7 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    RSTA  : in std_ulogic;
    RSTB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB4_S1_S8 : entity is true;
end ramb4_s1_s8;

architecture RAMB4_S1_S8_V of RAMB4_S1_S8 is
  attribute VITAL_LEVEL0 of
    RAMB4_S1_S8_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(11 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(0 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal RSTA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(8 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(7 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal RSTB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL : VitalDelayType := 1000 ps;
  constant length_a : integer := 4096;
  constant length_b : integer := 512;
  constant width_a : integer := 1;
  constant width_b   : integer := 8;  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    SLV : in std_logic_vector)
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((width_b - 1) downto 0);
  begin
    for i in two_D_array'low to two_D_array'high loop
      intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;    
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 11 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 0 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 8 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 7 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_RSTA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_RSTB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA : std_ulogic := '0';
    variable PViol_CLKB : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                            INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                            INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                            INIT_03 & INIT_02 & INIT_01 & INIT_00);     
    variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv);    


    variable ADDRESS_A      : integer;
    variable ADDRESS_B      : integer;
    variable DOA_OV_LSB     : integer;
    variable DOA_OV_MSB     : integer;
    variable DOA_zd         : std_logic_vector(0 downto 0) := (others => 'X');
    variable DOB_OV_LSB     : integer;
    variable DOB_OV_MSB     : integer;
    variable DOB_zd         : std_logic_vector(7 downto 0) := (others => 'X');
    variable FIRST_TIME     : boolean                       := true;
    variable HAS_OVERLAP    : boolean                       := false;
    variable OLP_LSB        : integer;
    variable OLP_MSB        : integer;
    variable VALID_ADDRA    : boolean                       := false;
    variable VALID_ADDRB    : boolean                       := false;
    variable ViolationA     : std_ulogic                    := '0';
    variable ViolationB     : std_ulogic                    := '0';
    variable ViolationCLKAB : std_ulogic                    := '0';

    variable ADDRA_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTA_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';

    variable ADDRB_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X');
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';

    variable collision_type : integer := 3;
  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB4_S1_S8",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      DOA <= DOA_zd;
      DOB <= DOB_zd;
      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      RSTA_ipd_sampled  := RSTA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      RSTB_ipd_sampled  := RSTB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTA_CLKA_posedge,
        TimingData     => Tmkr_RSTA_CLKA_posedge,
        TestSignal     => RSTA_ipd,
        TestSignalName => "RSTA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTA_CLKA_posedge_posedge,
        SetupLow       => tsetup_RSTA_CLKA_negedge_posedge,
        HoldLow        => thold_RSTA_CLKA_posedge_posedge,
        HoldHigh       => thold_RSTA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA10_CLKA_posedge,
        TimingData     => Tmkr_ADDRA10_CLKA_posedge,
        TestSignal     => ADDRA_ipd(10),
        TestSignalName => "ADDRA(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(10),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(10),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(10),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(10),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTB_CLKB_posedge,
        TimingData     => Tmkr_RSTB_CLKB_posedge,
        TestSignal     => RSTB_ipd,
        TestSignalName => "RSTB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTB_CLKB_posedge_posedge,
        SetupLow       => tsetup_RSTB_CLKB_negedge_posedge,
        HoldLow        => thold_RSTB_CLKB_posedge_posedge,
        HoldHigh       => thold_RSTB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_ADDRA11_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_RSTA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_RSTB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB := '0';

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKB_CLKA_posedge,
        TimingData     => Tmkr_CLKB_CLKA_posedge,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKA_CLKB_posedge,
        TimingData     => Tmkr_CLKA_CLKB_posedge,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S1_S8",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
    end if;

    ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge;

    if (ENA_ipd_sampled = '1') then
      if (rising_edge(CLKA_ipd)) then
        if (WEA_ipd_sampled = '1') then
          if (VALID_ADDRA) then
            MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
          end if;
          DOA_zd                                                 := DIA_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEB_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S1_S8",
                   InstanceName => ramb4_s1_s8'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                DOA_zd := (others => 'X');

                if (RSTB_ipd_sampled = '0' ) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;

            else
              if (RSTB_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_B_Write_A,
                     EntityName => "RAMB4_S1_S8",
                     InstanceName => ramb4_s1_s8'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRA) then
            DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));                        
          end if;
          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB4_S1_S8",
                 InstanceName => ramb4_s1_s8'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTA_ipd_sampled = '1') then
          DOA_zd := (others => '0');
        end if;
      end if;
    end if;

    if (ENB_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (WEB_ipd_sampled = '1') then
          if (VALID_ADDRB) then
            MEM(ADDRESS_B) := DIB_ipd;
          end if;
          DOB_zd                                                 := DIB_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEA_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S1_S8",
                   InstanceName => ramb4_s1_s8'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                if (RSTA_ipd_sampled = '0' ) then
                  DOA_zd := (others => 'X');
                end if;
              end if;

            else
              if (RSTA_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_A_Write_B,
                     EntityName => "RAMB4_S1_S8",
                     InstanceName => ramb4_s1_s8'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOA_zd := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRB) then
            DOB_zd := MEM(ADDRESS_B);
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB4_S1_S8",
                 InstanceName => ramb4_s1_s8'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTB_ipd_sampled = '1') then
          DOB_zd := (others => '0');
        end if;
      end if;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB4_S1_S8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb4_s2.vhd,v 1.5 2004/08/31 13:40:21 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4K-Bit Data Single Port Block RAM
-- /___/   /\     Filename : RAMB4_S2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:54 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAMB4_S2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB4_S2 is

  generic (
    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
    );

  port (
    DO     : out STD_LOGIC_VECTOR (1 downto 0);
    
    ADDR   : in STD_LOGIC_VECTOR (10 downto 0);
    CLK    : in STD_ULOGIC;        
    DI     : in STD_LOGIC_VECTOR (1 downto 0);
    EN     : in STD_ULOGIC;
    RST    : in STD_ULOGIC;        
    WE     : in STD_ULOGIC
    );
end RAMB4_S2;

architecture RAMB4_S2_V of RAMB4_S2 is
  constant length : integer := 2048;
  constant width : integer := 2;
  type Two_D_array_type is array ((length -  1) downto 0) of std_logic_vector((width - 1) downto 0);

  function slv_to_two_D_array(
    SLV : in std_logic_vector)
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((width - 1) downto 0);
  begin
    for i in two_D_array'low to two_D_array'high loop
      intermediate := SLV(((i*width) + (width - 1)) downto (i* width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;
begin
  VITALBehavior : process

    variable address : integer;
    variable valid_addr : boolean := FALSE;
    variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                            INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                            INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                            INIT_03 & INIT_02 & INIT_01 & INIT_00);     
    variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv);    

  begin
    valid_addr := addr_is_valid(addr);
    
    if (valid_addr) then
      address := slv_to_int(addr);
    end if;
    
    if (rising_edge(CLK)) then
      if (EN = '1') then
        if (RST = '1') then
          DO <= (others => '0') after 100 ps;
        else    
          if (WE = '1') then
            DO <= DI after 100 ps;
          else 
            if (valid_addr) then
              DO <= mem(address) after 100 ps;
            end if;
          end if;
        end if;
        if (WE = '1') then
          if (valid_addr) then
            mem(address) := DI;
          end if;
        end if;  
      end if;
    end if;
    wait on CLK;
  end process VITALBehavior;
end RAMB4_S2_V;


-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4K-Bit Data Dual Port Block RAM
-- /___/   /\     Filename : RAMB4_S2_S16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
----- CELL ramb4_s2_s16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB4_S2_S16 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(10 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(7 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tpd_CLKA_DOA : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    SIM_COLLISION_CHECK : string := "ALL"

    );

  port(
    DOA   : out std_logic_vector(1 downto 0);
    DOB   : out std_logic_vector(15 downto 0);

    ADDRA : in std_logic_vector(10 downto 0);
    ADDRB : in std_logic_vector(7 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(1 downto 0);
    DIB   : in std_logic_vector(15 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    RSTA  : in std_ulogic;
    RSTB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB4_S2_S16 : entity is true;
end ramb4_s2_s16;

architecture RAMB4_S2_S16_V of RAMB4_S2_S16 is
  attribute VITAL_LEVEL0 of
    RAMB4_S2_S16_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(10 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(1 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal RSTA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(7 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(15 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal RSTB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL : VitalDelayType := 1000 ps;
  constant length_a : integer := 2048;
  constant length_b : integer := 256;
  constant width_a : integer := 2;
  constant width_b   : integer := 16;  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    SLV : in std_logic_vector)
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((width_b - 1) downto 0);
  begin
    for i in two_D_array'low to two_D_array'high loop
      intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;    
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 10 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 1 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 7 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 15 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_RSTA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB8_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB9_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB10_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB11_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB12_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB13_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB14_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB15_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_RSTB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA : std_ulogic := '0';
    variable PViol_CLKB : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB8_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB9_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB10_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB11_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB12_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB13_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB14_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB15_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;
    variable DOB_GlitchData8  : VitalGlitchDataType;
    variable DOB_GlitchData9  : VitalGlitchDataType;
    variable DOB_GlitchData10  : VitalGlitchDataType;
    variable DOB_GlitchData11  : VitalGlitchDataType;
    variable DOB_GlitchData12  : VitalGlitchDataType;
    variable DOB_GlitchData13  : VitalGlitchDataType;
    variable DOB_GlitchData14  : VitalGlitchDataType;
    variable DOB_GlitchData15  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                            INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                            INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                            INIT_03 & INIT_02 & INIT_01 & INIT_00);     
    variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv);    


    variable ADDRESS_A      : integer;
    variable ADDRESS_B      : integer;
    variable DOA_OV_LSB     : integer;
    variable DOA_OV_MSB     : integer;
    variable DOA_zd         : std_logic_vector(1 downto 0) := (others => 'X');
    variable DOB_OV_LSB     : integer;
    variable DOB_OV_MSB     : integer;
    variable DOB_zd         : std_logic_vector(15 downto 0) := (others => 'X');
    variable FIRST_TIME     : boolean                       := true;
    variable HAS_OVERLAP    : boolean                       := false;
    variable OLP_LSB        : integer;
    variable OLP_MSB        : integer;
    variable VALID_ADDRA    : boolean                       := false;
    variable VALID_ADDRB    : boolean                       := false;
    variable ViolationA     : std_ulogic                    := '0';
    variable ViolationB     : std_ulogic                    := '0';
    variable ViolationCLKAB : std_ulogic                    := '0';

    variable ADDRA_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTA_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';

    variable ADDRB_ipd_sampled : std_logic_vector(7 downto 0) := (others => 'X');
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';

    variable collision_type : integer := 3;
  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB4_S2_S16",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      DOA <= DOA_zd;
      DOB <= DOB_zd;
      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      RSTA_ipd_sampled  := RSTA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      RSTB_ipd_sampled  := RSTB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTA_CLKA_posedge,
        TimingData     => Tmkr_RSTA_CLKA_posedge,
        TestSignal     => RSTA_ipd,
        TestSignalName => "RSTA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTA_CLKA_posedge_posedge,
        SetupLow       => tsetup_RSTA_CLKA_negedge_posedge,
        HoldLow        => thold_RSTA_CLKA_posedge_posedge,
        HoldHigh       => thold_RSTA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTB_CLKB_posedge,
        TimingData     => Tmkr_RSTB_CLKB_posedge,
        TestSignal     => RSTB_ipd,
        TestSignalName => "RSTB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTB_CLKB_posedge_posedge,
        SetupLow       => tsetup_RSTB_CLKB_negedge_posedge,
        HoldLow        => thold_RSTB_CLKB_posedge_posedge,
        HoldHigh       => thold_RSTB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB7_CLKB_posedge,
        TimingData     => Tmkr_DIB7_CLKB_posedge,
        TestSignal     => DIB_ipd(7),
        TestSignalName => "DIB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(7),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(7),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB8_CLKB_posedge,
        TimingData     => Tmkr_DIB8_CLKB_posedge,
        TestSignal     => DIB_ipd(8),
        TestSignalName => "DIB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(8),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(8),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB9_CLKB_posedge,
        TimingData     => Tmkr_DIB9_CLKB_posedge,
        TestSignal     => DIB_ipd(9),
        TestSignalName => "DIB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(9),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(9),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB10_CLKB_posedge,
        TimingData     => Tmkr_DIB10_CLKB_posedge,
        TestSignal     => DIB_ipd(10),
        TestSignalName => "DIB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(10),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(10),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB11_CLKB_posedge,
        TimingData     => Tmkr_DIB11_CLKB_posedge,
        TestSignal     => DIB_ipd(11),
        TestSignalName => "DIB(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(11),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(11),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(11),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(11),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB12_CLKB_posedge,
        TimingData     => Tmkr_DIB12_CLKB_posedge,
        TestSignal     => DIB_ipd(12),
        TestSignalName => "DIB(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(12),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(12),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(12),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(12),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB13_CLKB_posedge,
        TimingData     => Tmkr_DIB13_CLKB_posedge,
        TestSignal     => DIB_ipd(13),
        TestSignalName => "DIB(13)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(13),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(13),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(13),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(13),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB14_CLKB_posedge,
        TimingData     => Tmkr_DIB14_CLKB_posedge,
        TestSignal     => DIB_ipd(14),
        TestSignalName => "DIB(14)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(14),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(14),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(14),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(14),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_RSTA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_DIB8_CLKB_posedge or
                  Tviol_DIB9_CLKB_posedge or
                  Tviol_DIB10_CLKB_posedge or
                  Tviol_DIB11_CLKB_posedge or
                  Tviol_DIB12_CLKB_posedge or
                  Tviol_DIB13_CLKB_posedge or
                  Tviol_DIB14_CLKB_posedge or
                  Tviol_DIB15_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_RSTB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB := '0';

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKB_CLKA_posedge,
        TimingData     => Tmkr_CLKB_CLKA_posedge,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKA_CLKB_posedge,
        TimingData     => Tmkr_CLKA_CLKB_posedge,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S16",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
    end if;

    ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge;

    if (ENA_ipd_sampled = '1') then
      if (rising_edge(CLKA_ipd)) then
        if (WEA_ipd_sampled = '1') then
          if (VALID_ADDRA) then
            MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
          end if;
          DOA_zd                                                 := DIA_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEB_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S2_S16",
                   InstanceName => ramb4_s2_s16'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                DOA_zd := (others => 'X');

                if (RSTB_ipd_sampled = '0' ) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;

            else
              if (RSTB_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_B_Write_A,
                     EntityName => "RAMB4_S2_S16",
                     InstanceName => ramb4_s2_s16'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRA) then
            DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));                        
          end if;
          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB4_S2_S16",
                 InstanceName => ramb4_s2_s16'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTA_ipd_sampled = '1') then
          DOA_zd := (others => '0');
        end if;
      end if;
    end if;

    if (ENB_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (WEB_ipd_sampled = '1') then
          if (VALID_ADDRB) then
            MEM(ADDRESS_B) := DIB_ipd;
          end if;
          DOB_zd                                                 := DIB_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEA_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S2_S16",
                   InstanceName => ramb4_s2_s16'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                if (RSTA_ipd_sampled = '0' ) then
                  DOA_zd := (others => 'X');
                end if;
              end if;

            else
              if (RSTA_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_A_Write_B,
                     EntityName => "RAMB4_S2_S16",
                     InstanceName => ramb4_s2_s16'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOA_zd := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRB) then
            DOB_zd := MEM(ADDRESS_B);
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB4_S2_S16",
                 InstanceName => ramb4_s2_s16'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTB_ipd_sampled = '1') then
          DOB_zd := (others => '0');
        end if;
      end if;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);
    DOA_zd(1)  := ViolationA xor DOA_zd(1);

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);
    DOB_zd(8)  := ViolationB xor DOB_zd(8);
    DOB_zd(9)  := ViolationB xor DOB_zd(9);
    DOB_zd(10)  := ViolationB xor DOB_zd(10);
    DOB_zd(11)  := ViolationB xor DOB_zd(11);
    DOB_zd(12)  := ViolationB xor DOB_zd(12);
    DOB_zd(13)  := ViolationB xor DOB_zd(13);
    DOB_zd(14)  := ViolationB xor DOB_zd(14);
    DOB_zd(15)  := ViolationB xor DOB_zd(15);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(8),
      GlitchData    => DOB_GlitchData8,
      OutSignalName => "DOB(8)",
      OutTemp       => DOB_zd(8),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(9),
      GlitchData    => DOB_GlitchData9,
      OutSignalName => "DOB(9)",
      OutTemp       => DOB_zd(9),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(10),
      GlitchData    => DOB_GlitchData10,
      OutSignalName => "DOB(10)",
      OutTemp       => DOB_zd(10),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(11),
      GlitchData    => DOB_GlitchData11,
      OutSignalName => "DOB(11)",
      OutTemp       => DOB_zd(11),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(12),
      GlitchData    => DOB_GlitchData12,
      OutSignalName => "DOB(12)",
      OutTemp       => DOB_zd(12),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(13),
      GlitchData    => DOB_GlitchData13,
      OutSignalName => "DOB(13)",
      OutTemp       => DOB_zd(13),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(14),
      GlitchData    => DOB_GlitchData14,
      OutSignalName => "DOB(14)",
      OutTemp       => DOB_zd(14),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(15),
      GlitchData    => DOB_GlitchData15,
      OutSignalName => "DOB(15)",
      OutTemp       => DOB_zd(15),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB4_S2_S16_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4K-Bit Data Dual Port Block RAM
-- /___/   /\     Filename : RAMB4_S2_S2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
----- CELL ramb4_s2_s2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB4_S2_S2 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(10 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(10 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tpd_CLKA_DOA : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    SIM_COLLISION_CHECK : string := "ALL"

    );

  port(
    DOA   : out std_logic_vector(1 downto 0);
    DOB   : out std_logic_vector(1 downto 0);

    ADDRA : in std_logic_vector(10 downto 0);
    ADDRB : in std_logic_vector(10 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(1 downto 0);
    DIB   : in std_logic_vector(1 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    RSTA  : in std_ulogic;
    RSTB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB4_S2_S2 : entity is true;
end ramb4_s2_s2;

architecture RAMB4_S2_S2_V of RAMB4_S2_S2 is
  attribute VITAL_LEVEL0 of
    RAMB4_S2_S2_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(10 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(1 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal RSTA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(10 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(1 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal RSTB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL : VitalDelayType := 1000 ps;
  constant length_a : integer := 2048;
  constant length_b : integer := 2048;
  constant width_a : integer := 2;
  constant width_b   : integer := 2;  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    SLV : in std_logic_vector)
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((width_b - 1) downto 0);
  begin
    for i in two_D_array'low to two_D_array'high loop
      intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;    
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 10 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 1 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 10 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 1 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_RSTA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_RSTB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA : std_ulogic := '0';
    variable PViol_CLKB : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                            INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                            INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                            INIT_03 & INIT_02 & INIT_01 & INIT_00);     
    variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv);    


    variable ADDRESS_A      : integer;
    variable ADDRESS_B      : integer;
    variable DOA_OV_LSB     : integer;
    variable DOA_OV_MSB     : integer;
    variable DOA_zd         : std_logic_vector(1 downto 0) := (others => 'X');
    variable DOB_OV_LSB     : integer;
    variable DOB_OV_MSB     : integer;
    variable DOB_zd         : std_logic_vector(1 downto 0) := (others => 'X');
    variable FIRST_TIME     : boolean                       := true;
    variable HAS_OVERLAP    : boolean                       := false;
    variable OLP_LSB        : integer;
    variable OLP_MSB        : integer;
    variable VALID_ADDRA    : boolean                       := false;
    variable VALID_ADDRB    : boolean                       := false;
    variable ViolationA     : std_ulogic                    := '0';
    variable ViolationB     : std_ulogic                    := '0';
    variable ViolationCLKAB : std_ulogic                    := '0';

    variable ADDRA_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTA_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';

    variable ADDRB_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X');
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';

    variable collision_type : integer := 3;
  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB4_S2_S2",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      DOA <= DOA_zd;
      DOB <= DOB_zd;
      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      RSTA_ipd_sampled  := RSTA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      RSTB_ipd_sampled  := RSTB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTA_CLKA_posedge,
        TimingData     => Tmkr_RSTA_CLKA_posedge,
        TestSignal     => RSTA_ipd,
        TestSignalName => "RSTA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTA_CLKA_posedge_posedge,
        SetupLow       => tsetup_RSTA_CLKA_negedge_posedge,
        HoldLow        => thold_RSTA_CLKA_posedge_posedge,
        HoldHigh       => thold_RSTA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTB_CLKB_posedge,
        TimingData     => Tmkr_RSTB_CLKB_posedge,
        TestSignal     => RSTB_ipd,
        TestSignalName => "RSTB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTB_CLKB_posedge_posedge,
        SetupLow       => tsetup_RSTB_CLKB_negedge_posedge,
        HoldLow        => thold_RSTB_CLKB_posedge_posedge,
        HoldHigh       => thold_RSTB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB9_CLKB_posedge,
        TimingData     => Tmkr_ADDRB9_CLKB_posedge,
        TestSignal     => ADDRB_ipd(9),
        TestSignalName => "ADDRB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(9),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(9),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_RSTA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_ADDRB10_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_RSTB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB := '0';

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKB_CLKA_posedge,
        TimingData     => Tmkr_CLKB_CLKA_posedge,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKA_CLKB_posedge,
        TimingData     => Tmkr_CLKA_CLKB_posedge,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S2",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
    end if;

    ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge;

    if (ENA_ipd_sampled = '1') then
      if (rising_edge(CLKA_ipd)) then
        if (WEA_ipd_sampled = '1') then
          if (VALID_ADDRA) then
            MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
          end if;
          DOA_zd                                                 := DIA_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEB_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S2_S2",
                   InstanceName => ramb4_s2_s2'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                DOA_zd := (others => 'X');

                if (RSTB_ipd_sampled = '0' ) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;

            else
              if (RSTB_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_B_Write_A,
                     EntityName => "RAMB4_S2_S2",
                     InstanceName => ramb4_s2_s2'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRA) then
            DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));                        
          end if;
          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB4_S2_S2",
                 InstanceName => ramb4_s2_s2'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTA_ipd_sampled = '1') then
          DOA_zd := (others => '0');
        end if;
      end if;
    end if;

    if (ENB_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (WEB_ipd_sampled = '1') then
          if (VALID_ADDRB) then
            MEM(ADDRESS_B) := DIB_ipd;
          end if;
          DOB_zd                                                 := DIB_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEA_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S2_S2",
                   InstanceName => ramb4_s2_s2'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                if (RSTA_ipd_sampled = '0' ) then
                  DOA_zd := (others => 'X');
                end if;
              end if;

            else
              if (RSTA_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_A_Write_B,
                     EntityName => "RAMB4_S2_S2",
                     InstanceName => ramb4_s2_s2'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOA_zd := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRB) then
            DOB_zd := MEM(ADDRESS_B);
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB4_S2_S2",
                 InstanceName => ramb4_s2_s2'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTB_ipd_sampled = '1') then
          DOB_zd := (others => '0');
        end if;
      end if;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);
    DOA_zd(1)  := ViolationA xor DOA_zd(1);

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB4_S2_S2_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4K-Bit Data Dual Port Block RAM
-- /___/   /\     Filename : RAMB4_S2_S4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
----- CELL ramb4_s2_s4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB4_S2_S4 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(10 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(9 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tpd_CLKA_DOA : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    SIM_COLLISION_CHECK : string := "ALL"

    );

  port(
    DOA   : out std_logic_vector(1 downto 0);
    DOB   : out std_logic_vector(3 downto 0);

    ADDRA : in std_logic_vector(10 downto 0);
    ADDRB : in std_logic_vector(9 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(1 downto 0);
    DIB   : in std_logic_vector(3 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    RSTA  : in std_ulogic;
    RSTB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB4_S2_S4 : entity is true;
end ramb4_s2_s4;

architecture RAMB4_S2_S4_V of RAMB4_S2_S4 is
  attribute VITAL_LEVEL0 of
    RAMB4_S2_S4_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(10 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(1 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal RSTA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(9 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(3 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal RSTB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL : VitalDelayType := 1000 ps;
  constant length_a : integer := 2048;
  constant length_b : integer := 1024;
  constant width_a : integer := 2;
  constant width_b   : integer := 4;  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    SLV : in std_logic_vector)
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((width_b - 1) downto 0);
  begin
    for i in two_D_array'low to two_D_array'high loop
      intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;    
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 10 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 1 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 9 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 3 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_RSTA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_RSTB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA : std_ulogic := '0';
    variable PViol_CLKB : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                            INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                            INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                            INIT_03 & INIT_02 & INIT_01 & INIT_00);     
    variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv);    


    variable ADDRESS_A      : integer;
    variable ADDRESS_B      : integer;
    variable DOA_OV_LSB     : integer;
    variable DOA_OV_MSB     : integer;
    variable DOA_zd         : std_logic_vector(1 downto 0) := (others => 'X');
    variable DOB_OV_LSB     : integer;
    variable DOB_OV_MSB     : integer;
    variable DOB_zd         : std_logic_vector(3 downto 0) := (others => 'X');
    variable FIRST_TIME     : boolean                       := true;
    variable HAS_OVERLAP    : boolean                       := false;
    variable OLP_LSB        : integer;
    variable OLP_MSB        : integer;
    variable VALID_ADDRA    : boolean                       := false;
    variable VALID_ADDRB    : boolean                       := false;
    variable ViolationA     : std_ulogic                    := '0';
    variable ViolationB     : std_ulogic                    := '0';
    variable ViolationCLKAB : std_ulogic                    := '0';

    variable ADDRA_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTA_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';

    variable ADDRB_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X');
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';

    variable collision_type : integer := 3;
  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB4_S2_S4",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      DOA <= DOA_zd;
      DOB <= DOB_zd;
      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      RSTA_ipd_sampled  := RSTA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      RSTB_ipd_sampled  := RSTB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTA_CLKA_posedge,
        TimingData     => Tmkr_RSTA_CLKA_posedge,
        TestSignal     => RSTA_ipd,
        TestSignalName => "RSTA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTA_CLKA_posedge_posedge,
        SetupLow       => tsetup_RSTA_CLKA_negedge_posedge,
        HoldLow        => thold_RSTA_CLKA_posedge_posedge,
        HoldHigh       => thold_RSTA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTB_CLKB_posedge,
        TimingData     => Tmkr_RSTB_CLKB_posedge,
        TestSignal     => RSTB_ipd,
        TestSignalName => "RSTB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTB_CLKB_posedge_posedge,
        SetupLow       => tsetup_RSTB_CLKB_negedge_posedge,
        HoldLow        => thold_RSTB_CLKB_posedge_posedge,
        HoldHigh       => thold_RSTB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_RSTA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_RSTB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB := '0';

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKB_CLKA_posedge,
        TimingData     => Tmkr_CLKB_CLKA_posedge,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKA_CLKB_posedge,
        TimingData     => Tmkr_CLKA_CLKB_posedge,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S4",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
    end if;

    ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge;

    if (ENA_ipd_sampled = '1') then
      if (rising_edge(CLKA_ipd)) then
        if (WEA_ipd_sampled = '1') then
          if (VALID_ADDRA) then
            MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
          end if;
          DOA_zd                                                 := DIA_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEB_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S2_S4",
                   InstanceName => ramb4_s2_s4'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                DOA_zd := (others => 'X');

                if (RSTB_ipd_sampled = '0' ) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;

            else
              if (RSTB_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_B_Write_A,
                     EntityName => "RAMB4_S2_S4",
                     InstanceName => ramb4_s2_s4'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRA) then
            DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));                        
          end if;
          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB4_S2_S4",
                 InstanceName => ramb4_s2_s4'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTA_ipd_sampled = '1') then
          DOA_zd := (others => '0');
        end if;
      end if;
    end if;

    if (ENB_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (WEB_ipd_sampled = '1') then
          if (VALID_ADDRB) then
            MEM(ADDRESS_B) := DIB_ipd;
          end if;
          DOB_zd                                                 := DIB_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEA_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S2_S4",
                   InstanceName => ramb4_s2_s4'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                if (RSTA_ipd_sampled = '0' ) then
                  DOA_zd := (others => 'X');
                end if;
              end if;

            else
              if (RSTA_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_A_Write_B,
                     EntityName => "RAMB4_S2_S4",
                     InstanceName => ramb4_s2_s4'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOA_zd := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRB) then
            DOB_zd := MEM(ADDRESS_B);
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB4_S2_S4",
                 InstanceName => ramb4_s2_s4'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTB_ipd_sampled = '1') then
          DOB_zd := (others => '0');
        end if;
      end if;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);
    DOA_zd(1)  := ViolationA xor DOA_zd(1);

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB4_S2_S4_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4K-Bit Data Dual Port Block RAM
-- /___/   /\     Filename : RAMB4_S2_S8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
----- CELL ramb4_s2_s8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB4_S2_S8 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(10 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(8 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tpd_CLKA_DOA : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(1 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    SIM_COLLISION_CHECK : string := "ALL"

    );

  port(
    DOA   : out std_logic_vector(1 downto 0);
    DOB   : out std_logic_vector(7 downto 0);

    ADDRA : in std_logic_vector(10 downto 0);
    ADDRB : in std_logic_vector(8 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(1 downto 0);
    DIB   : in std_logic_vector(7 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    RSTA  : in std_ulogic;
    RSTB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB4_S2_S8 : entity is true;
end ramb4_s2_s8;

architecture RAMB4_S2_S8_V of RAMB4_S2_S8 is
  attribute VITAL_LEVEL0 of
    RAMB4_S2_S8_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(10 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(1 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal RSTA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(8 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(7 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal RSTB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL : VitalDelayType := 1000 ps;
  constant length_a : integer := 2048;
  constant length_b : integer := 512;
  constant width_a : integer := 2;
  constant width_b   : integer := 8;  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    SLV : in std_logic_vector)
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((width_b - 1) downto 0);
  begin
    for i in two_D_array'low to two_D_array'high loop
      intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;    
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 10 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 1 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 8 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 7 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_RSTA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_RSTB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA : std_ulogic := '0';
    variable PViol_CLKB : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                            INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                            INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                            INIT_03 & INIT_02 & INIT_01 & INIT_00);     
    variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv);    


    variable ADDRESS_A      : integer;
    variable ADDRESS_B      : integer;
    variable DOA_OV_LSB     : integer;
    variable DOA_OV_MSB     : integer;
    variable DOA_zd         : std_logic_vector(1 downto 0) := (others => 'X');
    variable DOB_OV_LSB     : integer;
    variable DOB_OV_MSB     : integer;
    variable DOB_zd         : std_logic_vector(7 downto 0) := (others => 'X');
    variable FIRST_TIME     : boolean                       := true;
    variable HAS_OVERLAP    : boolean                       := false;
    variable OLP_LSB        : integer;
    variable OLP_MSB        : integer;
    variable VALID_ADDRA    : boolean                       := false;
    variable VALID_ADDRB    : boolean                       := false;
    variable ViolationA     : std_ulogic                    := '0';
    variable ViolationB     : std_ulogic                    := '0';
    variable ViolationCLKAB : std_ulogic                    := '0';

    variable ADDRA_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTA_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';

    variable ADDRB_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X');
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';

    variable collision_type : integer := 3;
  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB4_S2_S8",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      DOA <= DOA_zd;
      DOB <= DOB_zd;
      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      RSTA_ipd_sampled  := RSTA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      RSTB_ipd_sampled  := RSTB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTA_CLKA_posedge,
        TimingData     => Tmkr_RSTA_CLKA_posedge,
        TestSignal     => RSTA_ipd,
        TestSignalName => "RSTA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTA_CLKA_posedge_posedge,
        SetupLow       => tsetup_RSTA_CLKA_negedge_posedge,
        HoldLow        => thold_RSTA_CLKA_posedge_posedge,
        HoldHigh       => thold_RSTA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA9_CLKA_posedge,
        TimingData     => Tmkr_ADDRA9_CLKA_posedge,
        TestSignal     => ADDRA_ipd(9),
        TestSignalName => "ADDRA(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(9),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(9),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(9),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(9),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTB_CLKB_posedge,
        TimingData     => Tmkr_RSTB_CLKB_posedge,
        TestSignal     => RSTB_ipd,
        TestSignalName => "RSTB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTB_CLKB_posedge_posedge,
        SetupLow       => tsetup_RSTB_CLKB_negedge_posedge,
        HoldLow        => thold_RSTB_CLKB_posedge_posedge,
        HoldHigh       => thold_RSTB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_ADDRA10_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_RSTA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_RSTB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB := '0';

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKB_CLKA_posedge,
        TimingData     => Tmkr_CLKB_CLKA_posedge,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKA_CLKB_posedge,
        TimingData     => Tmkr_CLKA_CLKB_posedge,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S2_S8",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
    end if;

    ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge;

    if (ENA_ipd_sampled = '1') then
      if (rising_edge(CLKA_ipd)) then
        if (WEA_ipd_sampled = '1') then
          if (VALID_ADDRA) then
            MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
          end if;
          DOA_zd                                                 := DIA_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEB_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S2_S8",
                   InstanceName => ramb4_s2_s8'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                DOA_zd := (others => 'X');

                if (RSTB_ipd_sampled = '0' ) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;

            else
              if (RSTB_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_B_Write_A,
                     EntityName => "RAMB4_S2_S8",
                     InstanceName => ramb4_s2_s8'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRA) then
            DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));                        
          end if;
          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB4_S2_S8",
                 InstanceName => ramb4_s2_s8'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTA_ipd_sampled = '1') then
          DOA_zd := (others => '0');
        end if;
      end if;
    end if;

    if (ENB_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (WEB_ipd_sampled = '1') then
          if (VALID_ADDRB) then
            MEM(ADDRESS_B) := DIB_ipd;
          end if;
          DOB_zd                                                 := DIB_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEA_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S2_S8",
                   InstanceName => ramb4_s2_s8'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                if (RSTA_ipd_sampled = '0' ) then
                  DOA_zd := (others => 'X');
                end if;
              end if;

            else
              if (RSTA_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_A_Write_B,
                     EntityName => "RAMB4_S2_S8",
                     InstanceName => ramb4_s2_s8'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOA_zd := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRB) then
            DOB_zd := MEM(ADDRESS_B);
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB4_S2_S8",
                 InstanceName => ramb4_s2_s8'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTB_ipd_sampled = '1') then
          DOB_zd := (others => '0');
        end if;
      end if;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);
    DOA_zd(1)  := ViolationA xor DOA_zd(1);

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB4_S2_S8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb4_s4.vhd,v 1.5 2004/08/31 13:40:21 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4K-Bit Data Single Port Block RAM
-- /___/   /\     Filename : RAMB4_S4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:55 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAMB4_S4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB4_S4 is

  generic (
    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
    );

  port (
    DO     : out STD_LOGIC_VECTOR (3 downto 0);
        
    ADDR   : in STD_LOGIC_VECTOR (9 downto 0);
    CLK    : in STD_ULOGIC;        
    DI     : in STD_LOGIC_VECTOR (3 downto 0);
    EN     : in STD_ULOGIC;
    RST    : in STD_ULOGIC;        
    WE     : in STD_ULOGIC
    );
end RAMB4_S4;

architecture RAMB4_S4_V of RAMB4_S4 is
  constant length : integer := 1024;
  constant width : integer := 4;
  type Two_D_array_type is array ((length -  1) downto 0) of std_logic_vector((width - 1) downto 0);

  function slv_to_two_D_array(
    SLV : in std_logic_vector)
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((width - 1) downto 0);
  begin
    for i in two_D_array'low to two_D_array'high loop
      intermediate := SLV(((i*width) + (width - 1)) downto (i* width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;  
begin

  VITALBehavior : process

    variable address : integer;
    variable valid_addr : boolean := FALSE;
    variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                            INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                            INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                            INIT_03 & INIT_02 & INIT_01 & INIT_00);     
    variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv);

  begin 
    valid_addr := addr_is_valid(addr);
    
    if (valid_addr) then
      address := slv_to_int(addr);
    end if;
    
    if (rising_edge(CLK)) then
      if (EN = '1') then
        if (RST = '1') then
          DO <= (others => '0') after 100 ps;
        else    
          if (WE = '1') then
            DO <= DI after 100 ps;
          else 
            if (valid_addr) then
              DO <= mem(address) after 100 ps;
            end if;
          end if;
        end if;
        if (WE = '1') then
          if (valid_addr) then
            mem(address) := DI;
          end if;
        end if;  
      end if;
    end if;
    wait on CLK;
  end process VITALBehavior;
end RAMB4_S4_V;


-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4K-Bit Data Dual Port Block RAM
-- /___/   /\     Filename : RAMB4_S4_S16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
----- CELL ramb4_s4_s16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB4_S4_S16 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(9 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(7 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tpd_CLKA_DOA : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    SIM_COLLISION_CHECK : string := "ALL"

    );

  port(
    DOA   : out std_logic_vector(3 downto 0);
    DOB   : out std_logic_vector(15 downto 0);

    ADDRA : in std_logic_vector(9 downto 0);
    ADDRB : in std_logic_vector(7 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(3 downto 0);
    DIB   : in std_logic_vector(15 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    RSTA  : in std_ulogic;
    RSTB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB4_S4_S16 : entity is true;
end ramb4_s4_s16;

architecture RAMB4_S4_S16_V of RAMB4_S4_S16 is
  attribute VITAL_LEVEL0 of
    RAMB4_S4_S16_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(9 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(3 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal RSTA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(7 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(15 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal RSTB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL : VitalDelayType := 1000 ps;
  constant length_a : integer := 1024;
  constant length_b : integer := 256;
  constant width_a : integer := 4;
  constant width_b   : integer := 16;  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    SLV : in std_logic_vector)
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((width_b - 1) downto 0);
  begin
    for i in two_D_array'low to two_D_array'high loop
      intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;    
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 9 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 3 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 7 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 15 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA2_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA3_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_RSTA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB8_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB9_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB10_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB11_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB12_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB13_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB14_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB15_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_RSTB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA : std_ulogic := '0';
    variable PViol_CLKB : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA2_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA3_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB8_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB9_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB10_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB11_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB12_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB13_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB14_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB15_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;
    variable DOA_GlitchData2  : VitalGlitchDataType;
    variable DOA_GlitchData3  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;
    variable DOB_GlitchData8  : VitalGlitchDataType;
    variable DOB_GlitchData9  : VitalGlitchDataType;
    variable DOB_GlitchData10  : VitalGlitchDataType;
    variable DOB_GlitchData11  : VitalGlitchDataType;
    variable DOB_GlitchData12  : VitalGlitchDataType;
    variable DOB_GlitchData13  : VitalGlitchDataType;
    variable DOB_GlitchData14  : VitalGlitchDataType;
    variable DOB_GlitchData15  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                            INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                            INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                            INIT_03 & INIT_02 & INIT_01 & INIT_00);     
    variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv);    


    variable ADDRESS_A      : integer;
    variable ADDRESS_B      : integer;
    variable DOA_OV_LSB     : integer;
    variable DOA_OV_MSB     : integer;
    variable DOA_zd         : std_logic_vector(3 downto 0) := (others => 'X');
    variable DOB_OV_LSB     : integer;
    variable DOB_OV_MSB     : integer;
    variable DOB_zd         : std_logic_vector(15 downto 0) := (others => 'X');
    variable FIRST_TIME     : boolean                       := true;
    variable HAS_OVERLAP    : boolean                       := false;
    variable OLP_LSB        : integer;
    variable OLP_MSB        : integer;
    variable VALID_ADDRA    : boolean                       := false;
    variable VALID_ADDRB    : boolean                       := false;
    variable ViolationA     : std_ulogic                    := '0';
    variable ViolationB     : std_ulogic                    := '0';
    variable ViolationCLKAB : std_ulogic                    := '0';

    variable ADDRA_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTA_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';

    variable ADDRB_ipd_sampled : std_logic_vector(7 downto 0) := (others => 'X');
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';

    variable collision_type : integer := 3;
  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB4_S4_S16",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      DOA <= DOA_zd;
      DOB <= DOB_zd;
      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      RSTA_ipd_sampled  := RSTA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      RSTB_ipd_sampled  := RSTB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTA_CLKA_posedge,
        TimingData     => Tmkr_RSTA_CLKA_posedge,
        TestSignal     => RSTA_ipd,
        TestSignalName => "RSTA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTA_CLKA_posedge_posedge,
        SetupLow       => tsetup_RSTA_CLKA_negedge_posedge,
        HoldLow        => thold_RSTA_CLKA_posedge_posedge,
        HoldHigh       => thold_RSTA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA1_CLKA_posedge,
        TimingData     => Tmkr_DIA1_CLKA_posedge,
        TestSignal     => DIA_ipd(1),
        TestSignalName => "DIA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(1),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA2_CLKA_posedge,
        TimingData     => Tmkr_DIA2_CLKA_posedge,
        TestSignal     => DIA_ipd(2),
        TestSignalName => "DIA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(2),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTB_CLKB_posedge,
        TimingData     => Tmkr_RSTB_CLKB_posedge,
        TestSignal     => RSTB_ipd,
        TestSignalName => "RSTB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTB_CLKB_posedge_posedge,
        SetupLow       => tsetup_RSTB_CLKB_negedge_posedge,
        HoldLow        => thold_RSTB_CLKB_posedge_posedge,
        HoldHigh       => thold_RSTB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB7_CLKB_posedge,
        TimingData     => Tmkr_DIB7_CLKB_posedge,
        TestSignal     => DIB_ipd(7),
        TestSignalName => "DIB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(7),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(7),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB8_CLKB_posedge,
        TimingData     => Tmkr_DIB8_CLKB_posedge,
        TestSignal     => DIB_ipd(8),
        TestSignalName => "DIB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(8),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(8),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB9_CLKB_posedge,
        TimingData     => Tmkr_DIB9_CLKB_posedge,
        TestSignal     => DIB_ipd(9),
        TestSignalName => "DIB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(9),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(9),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB10_CLKB_posedge,
        TimingData     => Tmkr_DIB10_CLKB_posedge,
        TestSignal     => DIB_ipd(10),
        TestSignalName => "DIB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(10),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(10),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB11_CLKB_posedge,
        TimingData     => Tmkr_DIB11_CLKB_posedge,
        TestSignal     => DIB_ipd(11),
        TestSignalName => "DIB(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(11),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(11),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(11),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(11),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB12_CLKB_posedge,
        TimingData     => Tmkr_DIB12_CLKB_posedge,
        TestSignal     => DIB_ipd(12),
        TestSignalName => "DIB(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(12),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(12),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(12),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(12),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB13_CLKB_posedge,
        TimingData     => Tmkr_DIB13_CLKB_posedge,
        TestSignal     => DIB_ipd(13),
        TestSignalName => "DIB(13)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(13),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(13),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(13),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(13),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB14_CLKB_posedge,
        TimingData     => Tmkr_DIB14_CLKB_posedge,
        TestSignal     => DIB_ipd(14),
        TestSignalName => "DIB(14)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(14),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(14),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(14),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(14),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_DIA2_CLKA_posedge or
                  Tviol_DIA3_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_RSTA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_DIB8_CLKB_posedge or
                  Tviol_DIB9_CLKB_posedge or
                  Tviol_DIB10_CLKB_posedge or
                  Tviol_DIB11_CLKB_posedge or
                  Tviol_DIB12_CLKB_posedge or
                  Tviol_DIB13_CLKB_posedge or
                  Tviol_DIB14_CLKB_posedge or
                  Tviol_DIB15_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_RSTB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB := '0';

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKB_CLKA_posedge,
        TimingData     => Tmkr_CLKB_CLKA_posedge,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKA_CLKB_posedge,
        TimingData     => Tmkr_CLKA_CLKB_posedge,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S16",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
    end if;

    ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge;

    if (ENA_ipd_sampled = '1') then
      if (rising_edge(CLKA_ipd)) then
        if (WEA_ipd_sampled = '1') then
          if (VALID_ADDRA) then
            MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
          end if;
          DOA_zd                                                 := DIA_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEB_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S4_S16",
                   InstanceName => ramb4_s4_s16'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                DOA_zd := (others => 'X');

                if (RSTB_ipd_sampled = '0' ) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;

            else
              if (RSTB_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_B_Write_A,
                     EntityName => "RAMB4_S4_S16",
                     InstanceName => ramb4_s4_s16'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRA) then
            DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));                        
          end if;
          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB4_S4_S16",
                 InstanceName => ramb4_s4_s16'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTA_ipd_sampled = '1') then
          DOA_zd := (others => '0');
        end if;
      end if;
    end if;

    if (ENB_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (WEB_ipd_sampled = '1') then
          if (VALID_ADDRB) then
            MEM(ADDRESS_B) := DIB_ipd;
          end if;
          DOB_zd                                                 := DIB_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEA_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S4_S16",
                   InstanceName => ramb4_s4_s16'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                if (RSTA_ipd_sampled = '0' ) then
                  DOA_zd := (others => 'X');
                end if;
              end if;

            else
              if (RSTA_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_A_Write_B,
                     EntityName => "RAMB4_S4_S16",
                     InstanceName => ramb4_s4_s16'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOA_zd := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRB) then
            DOB_zd := MEM(ADDRESS_B);
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB4_S4_S16",
                 InstanceName => ramb4_s4_s16'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTB_ipd_sampled = '1') then
          DOB_zd := (others => '0');
        end if;
      end if;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);
    DOA_zd(1)  := ViolationA xor DOA_zd(1);
    DOA_zd(2)  := ViolationA xor DOA_zd(2);
    DOA_zd(3)  := ViolationA xor DOA_zd(3);

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);
    DOB_zd(8)  := ViolationB xor DOB_zd(8);
    DOB_zd(9)  := ViolationB xor DOB_zd(9);
    DOB_zd(10)  := ViolationB xor DOB_zd(10);
    DOB_zd(11)  := ViolationB xor DOB_zd(11);
    DOB_zd(12)  := ViolationB xor DOB_zd(12);
    DOB_zd(13)  := ViolationB xor DOB_zd(13);
    DOB_zd(14)  := ViolationB xor DOB_zd(14);
    DOB_zd(15)  := ViolationB xor DOB_zd(15);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(2),
      GlitchData    => DOA_GlitchData2,
      OutSignalName => "DOA(2)",
      OutTemp       => DOA_zd(2),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(3),
      GlitchData    => DOA_GlitchData3,
      OutSignalName => "DOA(3)",
      OutTemp       => DOA_zd(3),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(8),
      GlitchData    => DOB_GlitchData8,
      OutSignalName => "DOB(8)",
      OutTemp       => DOB_zd(8),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(9),
      GlitchData    => DOB_GlitchData9,
      OutSignalName => "DOB(9)",
      OutTemp       => DOB_zd(9),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(10),
      GlitchData    => DOB_GlitchData10,
      OutSignalName => "DOB(10)",
      OutTemp       => DOB_zd(10),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(11),
      GlitchData    => DOB_GlitchData11,
      OutSignalName => "DOB(11)",
      OutTemp       => DOB_zd(11),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(12),
      GlitchData    => DOB_GlitchData12,
      OutSignalName => "DOB(12)",
      OutTemp       => DOB_zd(12),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(13),
      GlitchData    => DOB_GlitchData13,
      OutSignalName => "DOB(13)",
      OutTemp       => DOB_zd(13),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(14),
      GlitchData    => DOB_GlitchData14,
      OutSignalName => "DOB(14)",
      OutTemp       => DOB_zd(14),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(15),
      GlitchData    => DOB_GlitchData15,
      OutSignalName => "DOB(15)",
      OutTemp       => DOB_zd(15),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB4_S4_S16_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4K-Bit Data Dual Port Block RAM
-- /___/   /\     Filename : RAMB4_S4_S4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
----- CELL ramb4_s4_s4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB4_S4_S4 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(9 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(9 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tpd_CLKA_DOA : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    SIM_COLLISION_CHECK : string := "ALL"

    );

  port(
    DOA   : out std_logic_vector(3 downto 0);
    DOB   : out std_logic_vector(3 downto 0);

    ADDRA : in std_logic_vector(9 downto 0);
    ADDRB : in std_logic_vector(9 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(3 downto 0);
    DIB   : in std_logic_vector(3 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    RSTA  : in std_ulogic;
    RSTB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB4_S4_S4 : entity is true;
end ramb4_s4_s4;

architecture RAMB4_S4_S4_V of RAMB4_S4_S4 is
  attribute VITAL_LEVEL0 of
    RAMB4_S4_S4_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(9 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(3 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal RSTA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(9 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(3 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal RSTB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL : VitalDelayType := 1000 ps;
  constant length_a : integer := 1024;
  constant length_b : integer := 1024;
  constant width_a : integer := 4;
  constant width_b   : integer := 4;  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    SLV : in std_logic_vector)
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((width_b - 1) downto 0);
  begin
    for i in two_D_array'low to two_D_array'high loop
      intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;    
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 9 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 3 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 9 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 3 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA2_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA3_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_RSTA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_RSTB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA : std_ulogic := '0';
    variable PViol_CLKB : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA2_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA3_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;
    variable DOA_GlitchData2  : VitalGlitchDataType;
    variable DOA_GlitchData3  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                            INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                            INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                            INIT_03 & INIT_02 & INIT_01 & INIT_00);     
    variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv);    


    variable ADDRESS_A      : integer;
    variable ADDRESS_B      : integer;
    variable DOA_OV_LSB     : integer;
    variable DOA_OV_MSB     : integer;
    variable DOA_zd         : std_logic_vector(3 downto 0) := (others => 'X');
    variable DOB_OV_LSB     : integer;
    variable DOB_OV_MSB     : integer;
    variable DOB_zd         : std_logic_vector(3 downto 0) := (others => 'X');
    variable FIRST_TIME     : boolean                       := true;
    variable HAS_OVERLAP    : boolean                       := false;
    variable OLP_LSB        : integer;
    variable OLP_MSB        : integer;
    variable VALID_ADDRA    : boolean                       := false;
    variable VALID_ADDRB    : boolean                       := false;
    variable ViolationA     : std_ulogic                    := '0';
    variable ViolationB     : std_ulogic                    := '0';
    variable ViolationCLKAB : std_ulogic                    := '0';

    variable ADDRA_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTA_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';

    variable ADDRB_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X');
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';

    variable collision_type : integer := 3;
  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB4_S4_S4",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      DOA <= DOA_zd;
      DOB <= DOB_zd;
      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      RSTA_ipd_sampled  := RSTA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      RSTB_ipd_sampled  := RSTB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTA_CLKA_posedge,
        TimingData     => Tmkr_RSTA_CLKA_posedge,
        TestSignal     => RSTA_ipd,
        TestSignalName => "RSTA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTA_CLKA_posedge_posedge,
        SetupLow       => tsetup_RSTA_CLKA_negedge_posedge,
        HoldLow        => thold_RSTA_CLKA_posedge_posedge,
        HoldHigh       => thold_RSTA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA1_CLKA_posedge,
        TimingData     => Tmkr_DIA1_CLKA_posedge,
        TestSignal     => DIA_ipd(1),
        TestSignalName => "DIA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(1),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA2_CLKA_posedge,
        TimingData     => Tmkr_DIA2_CLKA_posedge,
        TestSignal     => DIA_ipd(2),
        TestSignalName => "DIA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(2),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTB_CLKB_posedge,
        TimingData     => Tmkr_RSTB_CLKB_posedge,
        TestSignal     => RSTB_ipd,
        TestSignalName => "RSTB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTB_CLKB_posedge_posedge,
        SetupLow       => tsetup_RSTB_CLKB_negedge_posedge,
        HoldLow        => thold_RSTB_CLKB_posedge_posedge,
        HoldHigh       => thold_RSTB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB8_CLKB_posedge,
        TimingData     => Tmkr_ADDRB8_CLKB_posedge,
        TestSignal     => ADDRB_ipd(8),
        TestSignalName => "ADDRB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(8),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(8),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_DIA2_CLKA_posedge or
                  Tviol_DIA3_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_RSTA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_ADDRB9_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_RSTB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB := '0';

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKB_CLKA_posedge,
        TimingData     => Tmkr_CLKB_CLKA_posedge,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKA_CLKB_posedge,
        TimingData     => Tmkr_CLKA_CLKB_posedge,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S4",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
    end if;

    ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge;

    if (ENA_ipd_sampled = '1') then
      if (rising_edge(CLKA_ipd)) then
        if (WEA_ipd_sampled = '1') then
          if (VALID_ADDRA) then
            MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
          end if;
          DOA_zd                                                 := DIA_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEB_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S4_S4",
                   InstanceName => ramb4_s4_s4'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                DOA_zd := (others => 'X');

                if (RSTB_ipd_sampled = '0' ) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;

            else
              if (RSTB_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_B_Write_A,
                     EntityName => "RAMB4_S4_S4",
                     InstanceName => ramb4_s4_s4'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRA) then
            DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));                        
          end if;
          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB4_S4_S4",
                 InstanceName => ramb4_s4_s4'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTA_ipd_sampled = '1') then
          DOA_zd := (others => '0');
        end if;
      end if;
    end if;

    if (ENB_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (WEB_ipd_sampled = '1') then
          if (VALID_ADDRB) then
            MEM(ADDRESS_B) := DIB_ipd;
          end if;
          DOB_zd                                                 := DIB_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEA_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S4_S4",
                   InstanceName => ramb4_s4_s4'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                if (RSTA_ipd_sampled = '0' ) then
                  DOA_zd := (others => 'X');
                end if;
              end if;

            else
              if (RSTA_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_A_Write_B,
                     EntityName => "RAMB4_S4_S4",
                     InstanceName => ramb4_s4_s4'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOA_zd := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRB) then
            DOB_zd := MEM(ADDRESS_B);
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB4_S4_S4",
                 InstanceName => ramb4_s4_s4'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTB_ipd_sampled = '1') then
          DOB_zd := (others => '0');
        end if;
      end if;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);
    DOA_zd(1)  := ViolationA xor DOA_zd(1);
    DOA_zd(2)  := ViolationA xor DOA_zd(2);
    DOA_zd(3)  := ViolationA xor DOA_zd(3);

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(2),
      GlitchData    => DOA_GlitchData2,
      OutSignalName => "DOA(2)",
      OutTemp       => DOA_zd(2),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(3),
      GlitchData    => DOA_GlitchData3,
      OutSignalName => "DOA(3)",
      OutTemp       => DOA_zd(3),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB4_S4_S4_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4K-Bit Data Dual Port Block RAM
-- /___/   /\     Filename : RAMB4_S4_S8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
----- CELL ramb4_s4_s8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB4_S4_S8 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(9 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(8 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tpd_CLKA_DOA : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(9 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(3 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    SIM_COLLISION_CHECK : string := "ALL"

    );

  port(
    DOA   : out std_logic_vector(3 downto 0);
    DOB   : out std_logic_vector(7 downto 0);

    ADDRA : in std_logic_vector(9 downto 0);
    ADDRB : in std_logic_vector(8 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(3 downto 0);
    DIB   : in std_logic_vector(7 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    RSTA  : in std_ulogic;
    RSTB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB4_S4_S8 : entity is true;
end ramb4_s4_s8;

architecture RAMB4_S4_S8_V of RAMB4_S4_S8 is
  attribute VITAL_LEVEL0 of
    RAMB4_S4_S8_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(9 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(3 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal RSTA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(8 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(7 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal RSTB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL : VitalDelayType := 1000 ps;
  constant length_a : integer := 1024;
  constant length_b : integer := 512;
  constant width_a : integer := 4;
  constant width_b   : integer := 8;  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    SLV : in std_logic_vector)
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((width_b - 1) downto 0);
  begin
    for i in two_D_array'low to two_D_array'high loop
      intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;    
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 9 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 3 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 8 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 7 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA2_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA3_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_RSTA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_RSTB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA : std_ulogic := '0';
    variable PViol_CLKB : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA2_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA3_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;
    variable DOA_GlitchData2  : VitalGlitchDataType;
    variable DOA_GlitchData3  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                            INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                            INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                            INIT_03 & INIT_02 & INIT_01 & INIT_00);     
    variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv);    


    variable ADDRESS_A      : integer;
    variable ADDRESS_B      : integer;
    variable DOA_OV_LSB     : integer;
    variable DOA_OV_MSB     : integer;
    variable DOA_zd         : std_logic_vector(3 downto 0) := (others => 'X');
    variable DOB_OV_LSB     : integer;
    variable DOB_OV_MSB     : integer;
    variable DOB_zd         : std_logic_vector(7 downto 0) := (others => 'X');
    variable FIRST_TIME     : boolean                       := true;
    variable HAS_OVERLAP    : boolean                       := false;
    variable OLP_LSB        : integer;
    variable OLP_MSB        : integer;
    variable VALID_ADDRA    : boolean                       := false;
    variable VALID_ADDRB    : boolean                       := false;
    variable ViolationA     : std_ulogic                    := '0';
    variable ViolationB     : std_ulogic                    := '0';
    variable ViolationCLKAB : std_ulogic                    := '0';

    variable ADDRA_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTA_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';

    variable ADDRB_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X');
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';

    variable collision_type : integer := 3;
  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB4_S4_S8",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      DOA <= DOA_zd;
      DOB <= DOB_zd;
      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      RSTA_ipd_sampled  := RSTA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      RSTB_ipd_sampled  := RSTB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTA_CLKA_posedge,
        TimingData     => Tmkr_RSTA_CLKA_posedge,
        TestSignal     => RSTA_ipd,
        TestSignalName => "RSTA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTA_CLKA_posedge_posedge,
        SetupLow       => tsetup_RSTA_CLKA_negedge_posedge,
        HoldLow        => thold_RSTA_CLKA_posedge_posedge,
        HoldHigh       => thold_RSTA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA8_CLKA_posedge,
        TimingData     => Tmkr_ADDRA8_CLKA_posedge,
        TestSignal     => ADDRA_ipd(8),
        TestSignalName => "ADDRA(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(8),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(8),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(8),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(8),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA1_CLKA_posedge,
        TimingData     => Tmkr_DIA1_CLKA_posedge,
        TestSignal     => DIA_ipd(1),
        TestSignalName => "DIA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(1),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA2_CLKA_posedge,
        TimingData     => Tmkr_DIA2_CLKA_posedge,
        TestSignal     => DIA_ipd(2),
        TestSignalName => "DIA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(2),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTB_CLKB_posedge,
        TimingData     => Tmkr_RSTB_CLKB_posedge,
        TestSignal     => RSTB_ipd,
        TestSignalName => "RSTB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTB_CLKB_posedge_posedge,
        SetupLow       => tsetup_RSTB_CLKB_negedge_posedge,
        HoldLow        => thold_RSTB_CLKB_posedge_posedge,
        HoldHigh       => thold_RSTB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_ADDRA9_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_DIA2_CLKA_posedge or
                  Tviol_DIA3_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_RSTA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_RSTB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB := '0';

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKB_CLKA_posedge,
        TimingData     => Tmkr_CLKB_CLKA_posedge,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKA_CLKB_posedge,
        TimingData     => Tmkr_CLKA_CLKB_posedge,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S4_S8",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
    end if;

    ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge;

    if (ENA_ipd_sampled = '1') then
      if (rising_edge(CLKA_ipd)) then
        if (WEA_ipd_sampled = '1') then
          if (VALID_ADDRA) then
            MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
          end if;
          DOA_zd                                                 := DIA_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEB_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S4_S8",
                   InstanceName => ramb4_s4_s8'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                DOA_zd := (others => 'X');

                if (RSTB_ipd_sampled = '0' ) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;

            else
              if (RSTB_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_B_Write_A,
                     EntityName => "RAMB4_S4_S8",
                     InstanceName => ramb4_s4_s8'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRA) then
            DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));                        
          end if;
          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB4_S4_S8",
                 InstanceName => ramb4_s4_s8'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTA_ipd_sampled = '1') then
          DOA_zd := (others => '0');
        end if;
      end if;
    end if;

    if (ENB_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (WEB_ipd_sampled = '1') then
          if (VALID_ADDRB) then
            MEM(ADDRESS_B) := DIB_ipd;
          end if;
          DOB_zd                                                 := DIB_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEA_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S4_S8",
                   InstanceName => ramb4_s4_s8'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                if (RSTA_ipd_sampled = '0' ) then
                  DOA_zd := (others => 'X');
                end if;
              end if;

            else
              if (RSTA_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_A_Write_B,
                     EntityName => "RAMB4_S4_S8",
                     InstanceName => ramb4_s4_s8'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOA_zd := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRB) then
            DOB_zd := MEM(ADDRESS_B);
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB4_S4_S8",
                 InstanceName => ramb4_s4_s8'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTB_ipd_sampled = '1') then
          DOB_zd := (others => '0');
        end if;
      end if;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);
    DOA_zd(1)  := ViolationA xor DOA_zd(1);
    DOA_zd(2)  := ViolationA xor DOA_zd(2);
    DOA_zd(3)  := ViolationA xor DOA_zd(3);

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(2),
      GlitchData    => DOA_GlitchData2,
      OutSignalName => "DOA(2)",
      OutTemp       => DOA_zd(2),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(3),
      GlitchData    => DOA_GlitchData3,
      OutSignalName => "DOA(3)",
      OutTemp       => DOA_zd(3),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB4_S4_S8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb4_s8.vhd,v 1.5 2004/08/31 13:40:21 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4K-Bit Data Single Port Block RAM
-- /___/   /\     Filename : RAMB4_S8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAMB4_S8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB4_S8 is

  generic (
    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
    );

  port (
    DO     : out STD_LOGIC_VECTOR (7 downto 0);
        
    ADDR   : in STD_LOGIC_VECTOR (8 downto 0);
    CLK    : in STD_ULOGIC;        
    DI     : in STD_LOGIC_VECTOR (7 downto 0);
    EN     : in STD_ULOGIC;
    RST    : in STD_ULOGIC;        
    WE     : in STD_ULOGIC
    );
end RAMB4_S8;

architecture RAMB4_S8_V of RAMB4_S8 is
  constant length : integer := 512;
  constant width : integer := 8;
  type Two_D_array_type is array ((length -  1) downto 0) of std_logic_vector((width - 1) downto 0);

  function slv_to_two_D_array(
    SLV : in std_logic_vector)
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((width - 1) downto 0);
  begin
    for i in two_D_array'low to two_D_array'high loop
      intermediate := SLV(((i*width) + (width - 1)) downto (i* width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;  
begin 

  VITALBehavior : process
    
    variable address : integer;
    variable valid_addr : boolean := FALSE;
    variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                            INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                            INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                            INIT_03 & INIT_02 & INIT_01 & INIT_00);     
    variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv);
    
  begin
    valid_addr := addr_is_valid(addr);
    
    if (valid_addr) then
      address := slv_to_int(addr);
    end if;
    
    if (rising_edge(CLK)) then
      if (EN = '1') then
        if (RST = '1') then
          DO <= (others => '0') after 100 ps;
        else    
          if (WE = '1') then
            DO <= DI after 100 ps;
          else 
            if (valid_addr) then
              DO <= mem(address) after 100 ps;
            end if;
          end if;
        end if;
        if (WE = '1') then
          if (valid_addr) then
            mem(address) := DI;
          end if;
        end if;  
      end if;
    end if;
    wait on CLK;
  end process VITALBehavior;
end RAMB4_S8_V;


-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4K-Bit Data Dual Port Block RAM
-- /___/   /\     Filename : RAMB4_S8_S16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
----- CELL ramb4_s8_s16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB4_S8_S16 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(8 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(7 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tpd_CLKA_DOA : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(15 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    SIM_COLLISION_CHECK : string := "ALL"

    );

  port(
    DOA   : out std_logic_vector(7 downto 0);
    DOB   : out std_logic_vector(15 downto 0);

    ADDRA : in std_logic_vector(8 downto 0);
    ADDRB : in std_logic_vector(7 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(7 downto 0);
    DIB   : in std_logic_vector(15 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    RSTA  : in std_ulogic;
    RSTB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB4_S8_S16 : entity is true;
end ramb4_s8_s16;

architecture RAMB4_S8_S16_V of RAMB4_S8_S16 is
  attribute VITAL_LEVEL0 of
    RAMB4_S8_S16_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(8 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(7 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal RSTA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(7 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(15 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal RSTB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL : VitalDelayType := 1000 ps;
  constant length_a : integer := 512;
  constant length_b : integer := 256;
  constant width_a : integer := 8;
  constant width_b   : integer := 16;  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    SLV : in std_logic_vector)
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((width_b - 1) downto 0);
  begin
    for i in two_D_array'low to two_D_array'high loop
      intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;    
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 8 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 7 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 7 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 15 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA2_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA3_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA4_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA5_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA6_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA7_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_RSTA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB8_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB9_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB10_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB11_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB12_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB13_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB14_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB15_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_RSTB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA : std_ulogic := '0';
    variable PViol_CLKB : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA2_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA3_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA4_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA5_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA6_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA7_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB8_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB9_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB10_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB11_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB12_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB13_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB14_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB15_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;
    variable DOA_GlitchData2  : VitalGlitchDataType;
    variable DOA_GlitchData3  : VitalGlitchDataType;
    variable DOA_GlitchData4  : VitalGlitchDataType;
    variable DOA_GlitchData5  : VitalGlitchDataType;
    variable DOA_GlitchData6  : VitalGlitchDataType;
    variable DOA_GlitchData7  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;
    variable DOB_GlitchData8  : VitalGlitchDataType;
    variable DOB_GlitchData9  : VitalGlitchDataType;
    variable DOB_GlitchData10  : VitalGlitchDataType;
    variable DOB_GlitchData11  : VitalGlitchDataType;
    variable DOB_GlitchData12  : VitalGlitchDataType;
    variable DOB_GlitchData13  : VitalGlitchDataType;
    variable DOB_GlitchData14  : VitalGlitchDataType;
    variable DOB_GlitchData15  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                            INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                            INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                            INIT_03 & INIT_02 & INIT_01 & INIT_00);     
    variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv);    


    variable ADDRESS_A      : integer;
    variable ADDRESS_B      : integer;
    variable DOA_OV_LSB     : integer;
    variable DOA_OV_MSB     : integer;
    variable DOA_zd         : std_logic_vector(7 downto 0) := (others => 'X');
    variable DOB_OV_LSB     : integer;
    variable DOB_OV_MSB     : integer;
    variable DOB_zd         : std_logic_vector(15 downto 0) := (others => 'X');
    variable FIRST_TIME     : boolean                       := true;
    variable HAS_OVERLAP    : boolean                       := false;
    variable OLP_LSB        : integer;
    variable OLP_MSB        : integer;
    variable VALID_ADDRA    : boolean                       := false;
    variable VALID_ADDRB    : boolean                       := false;
    variable ViolationA     : std_ulogic                    := '0';
    variable ViolationB     : std_ulogic                    := '0';
    variable ViolationCLKAB : std_ulogic                    := '0';

    variable ADDRA_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTA_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';

    variable ADDRB_ipd_sampled : std_logic_vector(7 downto 0) := (others => 'X');
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';

    variable collision_type : integer := 3;
  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB4_S8_S16",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      DOA <= DOA_zd;
      DOB <= DOB_zd;
      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      RSTA_ipd_sampled  := RSTA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      RSTB_ipd_sampled  := RSTB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTA_CLKA_posedge,
        TimingData     => Tmkr_RSTA_CLKA_posedge,
        TestSignal     => RSTA_ipd,
        TestSignalName => "RSTA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTA_CLKA_posedge_posedge,
        SetupLow       => tsetup_RSTA_CLKA_negedge_posedge,
        HoldLow        => thold_RSTA_CLKA_posedge_posedge,
        HoldHigh       => thold_RSTA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA1_CLKA_posedge,
        TimingData     => Tmkr_DIA1_CLKA_posedge,
        TestSignal     => DIA_ipd(1),
        TestSignalName => "DIA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(1),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA2_CLKA_posedge,
        TimingData     => Tmkr_DIA2_CLKA_posedge,
        TestSignal     => DIA_ipd(2),
        TestSignalName => "DIA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(2),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA3_CLKA_posedge,
        TimingData     => Tmkr_DIA3_CLKA_posedge,
        TestSignal     => DIA_ipd(3),
        TestSignalName => "DIA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(3),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(3),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA4_CLKA_posedge,
        TimingData     => Tmkr_DIA4_CLKA_posedge,
        TestSignal     => DIA_ipd(4),
        TestSignalName => "DIA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(4),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(4),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA5_CLKA_posedge,
        TimingData     => Tmkr_DIA5_CLKA_posedge,
        TestSignal     => DIA_ipd(5),
        TestSignalName => "DIA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(5),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(5),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA6_CLKA_posedge,
        TimingData     => Tmkr_DIA6_CLKA_posedge,
        TestSignal     => DIA_ipd(6),
        TestSignalName => "DIA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(6),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(6),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTB_CLKB_posedge,
        TimingData     => Tmkr_RSTB_CLKB_posedge,
        TestSignal     => RSTB_ipd,
        TestSignalName => "RSTB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTB_CLKB_posedge_posedge,
        SetupLow       => tsetup_RSTB_CLKB_negedge_posedge,
        HoldLow        => thold_RSTB_CLKB_posedge_posedge,
        HoldHigh       => thold_RSTB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB7_CLKB_posedge,
        TimingData     => Tmkr_DIB7_CLKB_posedge,
        TestSignal     => DIB_ipd(7),
        TestSignalName => "DIB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(7),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(7),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB8_CLKB_posedge,
        TimingData     => Tmkr_DIB8_CLKB_posedge,
        TestSignal     => DIB_ipd(8),
        TestSignalName => "DIB(8)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(8),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(8),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(8),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(8),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB9_CLKB_posedge,
        TimingData     => Tmkr_DIB9_CLKB_posedge,
        TestSignal     => DIB_ipd(9),
        TestSignalName => "DIB(9)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(9),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(9),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(9),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(9),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB10_CLKB_posedge,
        TimingData     => Tmkr_DIB10_CLKB_posedge,
        TestSignal     => DIB_ipd(10),
        TestSignalName => "DIB(10)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(10),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(10),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(10),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(10),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB11_CLKB_posedge,
        TimingData     => Tmkr_DIB11_CLKB_posedge,
        TestSignal     => DIB_ipd(11),
        TestSignalName => "DIB(11)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(11),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(11),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(11),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(11),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB12_CLKB_posedge,
        TimingData     => Tmkr_DIB12_CLKB_posedge,
        TestSignal     => DIB_ipd(12),
        TestSignalName => "DIB(12)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(12),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(12),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(12),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(12),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB13_CLKB_posedge,
        TimingData     => Tmkr_DIB13_CLKB_posedge,
        TestSignal     => DIB_ipd(13),
        TestSignalName => "DIB(13)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(13),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(13),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(13),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(13),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB14_CLKB_posedge,
        TimingData     => Tmkr_DIB14_CLKB_posedge,
        TestSignal     => DIB_ipd(14),
        TestSignalName => "DIB(14)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(14),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(14),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(14),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(14),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_DIA2_CLKA_posedge or
                  Tviol_DIA3_CLKA_posedge or
                  Tviol_DIA4_CLKA_posedge or
                  Tviol_DIA5_CLKA_posedge or
                  Tviol_DIA6_CLKA_posedge or
                  Tviol_DIA7_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_RSTA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_DIB8_CLKB_posedge or
                  Tviol_DIB9_CLKB_posedge or
                  Tviol_DIB10_CLKB_posedge or
                  Tviol_DIB11_CLKB_posedge or
                  Tviol_DIB12_CLKB_posedge or
                  Tviol_DIB13_CLKB_posedge or
                  Tviol_DIB14_CLKB_posedge or
                  Tviol_DIB15_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_RSTB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB := '0';

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKB_CLKA_posedge,
        TimingData     => Tmkr_CLKB_CLKA_posedge,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKA_CLKB_posedge,
        TimingData     => Tmkr_CLKA_CLKB_posedge,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S16",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
    end if;

    ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge;

    if (ENA_ipd_sampled = '1') then
      if (rising_edge(CLKA_ipd)) then
        if (WEA_ipd_sampled = '1') then
          if (VALID_ADDRA) then
            MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
          end if;
          DOA_zd                                                 := DIA_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEB_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S8_S16",
                   InstanceName => ramb4_s8_s16'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                DOA_zd := (others => 'X');

                if (RSTB_ipd_sampled = '0' ) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;

            else
              if (RSTB_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_B_Write_A,
                     EntityName => "RAMB4_S8_S16",
                     InstanceName => ramb4_s8_s16'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRA) then
            DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));                        
          end if;
          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB4_S8_S16",
                 InstanceName => ramb4_s8_s16'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTA_ipd_sampled = '1') then
          DOA_zd := (others => '0');
        end if;
      end if;
    end if;

    if (ENB_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (WEB_ipd_sampled = '1') then
          if (VALID_ADDRB) then
            MEM(ADDRESS_B) := DIB_ipd;
          end if;
          DOB_zd                                                 := DIB_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEA_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S8_S16",
                   InstanceName => ramb4_s8_s16'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                if (RSTA_ipd_sampled = '0' ) then
                  DOA_zd := (others => 'X');
                end if;
              end if;

            else
              if (RSTA_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_A_Write_B,
                     EntityName => "RAMB4_S8_S16",
                     InstanceName => ramb4_s8_s16'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOA_zd := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRB) then
            DOB_zd := MEM(ADDRESS_B);
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB4_S8_S16",
                 InstanceName => ramb4_s8_s16'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTB_ipd_sampled = '1') then
          DOB_zd := (others => '0');
        end if;
      end if;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);
    DOA_zd(1)  := ViolationA xor DOA_zd(1);
    DOA_zd(2)  := ViolationA xor DOA_zd(2);
    DOA_zd(3)  := ViolationA xor DOA_zd(3);
    DOA_zd(4)  := ViolationA xor DOA_zd(4);
    DOA_zd(5)  := ViolationA xor DOA_zd(5);
    DOA_zd(6)  := ViolationA xor DOA_zd(6);
    DOA_zd(7)  := ViolationA xor DOA_zd(7);

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);
    DOB_zd(8)  := ViolationB xor DOB_zd(8);
    DOB_zd(9)  := ViolationB xor DOB_zd(9);
    DOB_zd(10)  := ViolationB xor DOB_zd(10);
    DOB_zd(11)  := ViolationB xor DOB_zd(11);
    DOB_zd(12)  := ViolationB xor DOB_zd(12);
    DOB_zd(13)  := ViolationB xor DOB_zd(13);
    DOB_zd(14)  := ViolationB xor DOB_zd(14);
    DOB_zd(15)  := ViolationB xor DOB_zd(15);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(2),
      GlitchData    => DOA_GlitchData2,
      OutSignalName => "DOA(2)",
      OutTemp       => DOA_zd(2),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(3),
      GlitchData    => DOA_GlitchData3,
      OutSignalName => "DOA(3)",
      OutTemp       => DOA_zd(3),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(4),
      GlitchData    => DOA_GlitchData4,
      OutSignalName => "DOA(4)",
      OutTemp       => DOA_zd(4),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(5),
      GlitchData    => DOA_GlitchData5,
      OutSignalName => "DOA(5)",
      OutTemp       => DOA_zd(5),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(6),
      GlitchData    => DOA_GlitchData6,
      OutSignalName => "DOA(6)",
      OutTemp       => DOA_zd(6),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(7),
      GlitchData    => DOA_GlitchData7,
      OutSignalName => "DOA(7)",
      OutTemp       => DOA_zd(7),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(8),
      GlitchData    => DOB_GlitchData8,
      OutSignalName => "DOB(8)",
      OutTemp       => DOB_zd(8),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(9),
      GlitchData    => DOB_GlitchData9,
      OutSignalName => "DOB(9)",
      OutTemp       => DOB_zd(9),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(10),
      GlitchData    => DOB_GlitchData10,
      OutSignalName => "DOB(10)",
      OutTemp       => DOB_zd(10),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(11),
      GlitchData    => DOB_GlitchData11,
      OutSignalName => "DOB(11)",
      OutTemp       => DOB_zd(11),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(12),
      GlitchData    => DOB_GlitchData12,
      OutSignalName => "DOB(12)",
      OutTemp       => DOB_zd(12),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(13),
      GlitchData    => DOB_GlitchData13,
      OutSignalName => "DOB(13)",
      OutTemp       => DOB_zd(13),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(14),
      GlitchData    => DOB_GlitchData14,
      OutSignalName => "DOB(14)",
      OutTemp       => DOB_zd(14),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(15),
      GlitchData    => DOB_GlitchData15,
      OutSignalName => "DOB(15)",
      OutTemp       => DOB_zd(15),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB4_S8_S16_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4K-Bit Data Dual Port Block RAM
-- /___/   /\     Filename : RAMB4_S8_S8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
----- CELL ramb4_s8_s8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAMB4_S8_S8 is
  generic (
    TimingChecksOn : boolean := false;
    Xon            : boolean := false;
    MsgOn          : boolean := false;

    tipd_ADDRA : VitalDelayArrayType01(8 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIA   : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENA   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTA  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEA   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tipd_ADDRB : VitalDelayArrayType01(8 downto 0)  := (others => (0 ps, 0 ps));
    tipd_CLKB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_DIB   : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
    tipd_ENB   : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_RSTB  : VitalDelayType01                   := ( 0 ps, 0 ps);
    tipd_WEB   : VitalDelayType01                   := ( 0 ps, 0 ps);

    tpd_CLKA_DOA : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps));
    tpd_CLKB_DOB : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps));

    tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    tsetup_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    tsetup_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    tsetup_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_DIA_CLKA_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_DIA_CLKA_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_ENA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTA_CLKA_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEA_CLKA_posedge_posedge   : VitalDelayType                   := 0 ps;

    thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0)  := (others => 0 ps);
    thold_DIB_CLKB_negedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_DIB_CLKB_posedge_posedge   : VitalDelayArrayType(7 downto 0) := (others => 0 ps);
    thold_ENB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_ENB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_negedge_posedge  : VitalDelayType                   := 0 ps;
    thold_RSTB_CLKB_posedge_posedge  : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
    thold_WEB_CLKB_posedge_posedge   : VitalDelayType                   := 0 ps;

    tpw_CLKA_negedge : VitalDelayType := 0 ps;
    tpw_CLKA_posedge : VitalDelayType := 0 ps;
    tpw_CLKB_negedge : VitalDelayType := 0 ps;
    tpw_CLKB_posedge : VitalDelayType := 0 ps;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    SIM_COLLISION_CHECK : string := "ALL"

    );

  port(
    DOA   : out std_logic_vector(7 downto 0);
    DOB   : out std_logic_vector(7 downto 0);

    ADDRA : in std_logic_vector(8 downto 0);
    ADDRB : in std_logic_vector(8 downto 0);
    CLKA  : in std_ulogic;
    CLKB  : in std_ulogic;
    DIA   : in std_logic_vector(7 downto 0);
    DIB   : in std_logic_vector(7 downto 0);
    ENA   : in std_ulogic;
    ENB   : in std_ulogic;
    RSTA  : in std_ulogic;
    RSTB  : in std_ulogic;
    WEA   : in std_ulogic;
    WEB   : in std_ulogic
    );

  attribute VITAL_LEVEL0 of
    RAMB4_S8_S8 : entity is true;
end ramb4_s8_s8;

architecture RAMB4_S8_S8_V of RAMB4_S8_S8 is
  attribute VITAL_LEVEL0 of
    RAMB4_S8_S8_V : architecture is true;

  signal ADDRA_ipd : std_logic_vector(8 downto 0)  := (others => 'X');
  signal CLKA_ipd  : std_ulogic                    := 'X';
  signal DIA_ipd   : std_logic_vector(7 downto 0) := (others => 'X');
  signal ENA_ipd   : std_ulogic                    := 'X';
  signal RSTA_ipd  : std_ulogic                    := 'X';
  signal WEA_ipd   : std_ulogic                    := 'X';

  signal ADDRB_ipd : std_logic_vector(8 downto 0)  := (others => 'X');
  signal CLKB_ipd  : std_ulogic                    := 'X';
  signal DIB_ipd   : std_logic_vector(7 downto 0) := (others => 'X');
  signal ENB_ipd   : std_ulogic                    := 'X';
  signal RSTB_ipd  : std_ulogic                    := 'X';
  signal WEB_ipd   : std_ulogic                    := 'X';

  constant SETUP_ALL : VitalDelayType := 1000 ps;
  constant length_a : integer := 512;
  constant length_b : integer := 512;
  constant width_a : integer := 8;
  constant width_b   : integer := 8;  
  type Two_D_array_type is array ((length_b -  1) downto 0) of std_logic_vector((width_b - 1) downto 0);

  function slv_to_two_D_array(
    SLV : in std_logic_vector)
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((width_b - 1) downto 0);
  begin
    for i in two_D_array'low to two_D_array'high loop
      intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;    
begin
  WireDelay     : block
  begin
    ADDRA_DELAY : for i in 8 downto 0 generate
      VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i));
    end generate ADDRA_DELAY;
    VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA);
    DIA_DELAY   : for i in 7 downto 0 generate
      VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i));
    end generate DIA_DELAY;
    VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
    VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA);
    VitalWireDelay (WEA_ipd, WEA, tipd_WEA);

    ADDRB_DELAY : for i in 8 downto 0 generate
      VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i));
    end generate ADDRB_DELAY;
    VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB);
    DIB_DELAY   : for i in 7 downto 0 generate
      VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i));
    end generate DIB_DELAY;
    VitalWireDelay (ENB_ipd, ENB, tipd_ENB);
    VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB);
    VitalWireDelay (WEB_ipd, WEB, tipd_WEB);
  end block;

  VITALBehavior                        : process
    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0';
    variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0';
    variable Tviol_CLKB_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA0_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA1_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA2_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA3_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA4_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA5_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA6_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_DIA7_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_ENA_CLKA_posedge    : std_ulogic := '0';
    variable Tviol_RSTA_CLKA_posedge   : std_ulogic := '0';
    variable Tviol_WEA_CLKA_posedge    : std_ulogic := '0';

    variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0';
    variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0';
    variable Tviol_CLKA_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB0_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB1_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB2_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB3_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB4_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB5_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB6_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_DIB7_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_ENB_CLKB_posedge    : std_ulogic := '0';
    variable Tviol_RSTB_CLKB_posedge   : std_ulogic := '0';
    variable Tviol_WEB_CLKB_posedge    : std_ulogic := '0';

    variable PViol_CLKA : std_ulogic := '0';
    variable PViol_CLKB : std_ulogic := '0';

    variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKB_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA0_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA1_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA2_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA3_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA4_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA5_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA6_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIA7_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTA_CLKA_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEA_CLKA_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_CLKA_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB0_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB1_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB2_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB3_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB4_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB5_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB6_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_DIB7_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_ENB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_RSTB_CLKB_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WEB_CLKB_posedge    : VitalTimingDataType := VitalTimingDataInit;

    variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit;
    variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit;

    variable DOA_GlitchData0  : VitalGlitchDataType;
    variable DOA_GlitchData1  : VitalGlitchDataType;
    variable DOA_GlitchData2  : VitalGlitchDataType;
    variable DOA_GlitchData3  : VitalGlitchDataType;
    variable DOA_GlitchData4  : VitalGlitchDataType;
    variable DOA_GlitchData5  : VitalGlitchDataType;
    variable DOA_GlitchData6  : VitalGlitchDataType;
    variable DOA_GlitchData7  : VitalGlitchDataType;

    variable DOB_GlitchData0  : VitalGlitchDataType;
    variable DOB_GlitchData1  : VitalGlitchDataType;
    variable DOB_GlitchData2  : VitalGlitchDataType;
    variable DOB_GlitchData3  : VitalGlitchDataType;
    variable DOB_GlitchData4  : VitalGlitchDataType;
    variable DOB_GlitchData5  : VitalGlitchDataType;
    variable DOB_GlitchData6  : VitalGlitchDataType;
    variable DOB_GlitchData7  : VitalGlitchDataType;

    variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C &
                                                                            INIT_0B & INIT_0A & INIT_09 & INIT_08 &
                                                                            INIT_07 & INIT_06 & INIT_05 & INIT_04 &
                                                                            INIT_03 & INIT_02 & INIT_01 & INIT_00);     
    variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv);    


    variable ADDRESS_A      : integer;
    variable ADDRESS_B      : integer;
    variable DOA_OV_LSB     : integer;
    variable DOA_OV_MSB     : integer;
    variable DOA_zd         : std_logic_vector(7 downto 0) := (others => 'X');
    variable DOB_OV_LSB     : integer;
    variable DOB_OV_MSB     : integer;
    variable DOB_zd         : std_logic_vector(7 downto 0) := (others => 'X');
    variable FIRST_TIME     : boolean                       := true;
    variable HAS_OVERLAP    : boolean                       := false;
    variable OLP_LSB        : integer;
    variable OLP_MSB        : integer;
    variable VALID_ADDRA    : boolean                       := false;
    variable VALID_ADDRB    : boolean                       := false;
    variable ViolationA     : std_ulogic                    := '0';
    variable ViolationB     : std_ulogic                    := '0';
    variable ViolationCLKAB : std_ulogic                    := '0';

    variable ADDRA_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X');
    variable ENA_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTA_ipd_sampled  : std_ulogic                    := 'X';
    variable WEA_ipd_sampled   : std_ulogic                    := 'X';

    variable ADDRB_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X');
    variable ENB_ipd_sampled   : std_ulogic                    := 'X';
    variable RSTB_ipd_sampled  : std_ulogic                    := 'X';
    variable WEB_ipd_sampled   : std_ulogic                    := 'X';

    variable collision_type : integer := 3;
  begin
    if (FIRST_TIME) then
      if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE"))  then
        collision_type := 0;
      elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY"))  then
        collision_type := 1;
      elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY"))  then
        collision_type := 2;
      elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL"))  then
        collision_type := 3;
      else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "RAMB4_S8_S8",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
      DOA <= DOA_zd;
      DOB <= DOB_zd;
      FIRST_TIME := false;
    end if;

    if (CLKA_ipd'event) then
      ENA_ipd_sampled   := ENA_ipd;
      RSTA_ipd_sampled  := RSTA_ipd;
      WEA_ipd_sampled   := WEA_ipd;
      ADDRA_ipd_sampled := ADDRA_ipd;
    end if;

    if (CLKB_ipd'event) then
      ENB_ipd_sampled   := ENB_ipd;
      RSTB_ipd_sampled  := RSTB_ipd;
      WEB_ipd_sampled   := WEB_ipd;
      ADDRB_ipd_sampled := ADDRB_ipd;
    end if;

    if (TimingChecksOn) then
      VitalSetupHoldCheck (
        Violation      => Tviol_ENA_CLKA_posedge,
        TimingData     => Tmkr_ENA_CLKA_posedge,
        TestSignal     => ENA_ipd,
        TestSignalName => "ENA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENA_CLKA_posedge_posedge,
        SetupLow       => tsetup_ENA_CLKA_negedge_posedge,
        HoldLow        => thold_ENA_CLKA_posedge_posedge,
        HoldHigh       => thold_ENA_CLKA_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTA_CLKA_posedge,
        TimingData     => Tmkr_RSTA_CLKA_posedge,
        TestSignal     => RSTA_ipd,
        TestSignalName => "RSTA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTA_CLKA_posedge_posedge,
        SetupLow       => tsetup_RSTA_CLKA_negedge_posedge,
        HoldLow        => thold_RSTA_CLKA_posedge_posedge,
        HoldHigh       => thold_RSTA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEA_CLKA_posedge,
        TimingData     => Tmkr_WEA_CLKA_posedge,
        TestSignal     => WEA_ipd,
        TestSignalName => "WEA",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEA_CLKA_posedge_posedge,
        SetupLow       => tsetup_WEA_CLKA_negedge_posedge,
        HoldLow        => thold_WEA_CLKA_posedge_posedge,
        HoldHigh       => thold_WEA_CLKA_negedge_posedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA0_CLKA_posedge,
        TimingData     => Tmkr_ADDRA0_CLKA_posedge,
        TestSignal     => ADDRA_ipd(0),
        TestSignalName => "ADDRA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(0),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA1_CLKA_posedge,
        TimingData     => Tmkr_ADDRA1_CLKA_posedge,
        TestSignal     => ADDRA_ipd(1),
        TestSignalName => "ADDRA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(1),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA2_CLKA_posedge,
        TimingData     => Tmkr_ADDRA2_CLKA_posedge,
        TestSignal     => ADDRA_ipd(2),
        TestSignalName => "ADDRA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(2),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA3_CLKA_posedge,
        TimingData     => Tmkr_ADDRA3_CLKA_posedge,
        TestSignal     => ADDRA_ipd(3),
        TestSignalName => "ADDRA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(3),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA4_CLKA_posedge,
        TimingData     => Tmkr_ADDRA4_CLKA_posedge,
        TestSignal     => ADDRA_ipd(4),
        TestSignalName => "ADDRA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(4),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA5_CLKA_posedge,
        TimingData     => Tmkr_ADDRA5_CLKA_posedge,
        TestSignal     => ADDRA_ipd(5),
        TestSignalName => "ADDRA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(5),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA6_CLKA_posedge,
        TimingData     => Tmkr_ADDRA6_CLKA_posedge,
        TestSignal     => ADDRA_ipd(6),
        TestSignalName => "ADDRA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(6),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRA7_CLKA_posedge,
        TimingData     => Tmkr_ADDRA7_CLKA_posedge,
        TestSignal     => ADDRA_ipd(7),
        TestSignalName => "ADDRA(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRA_CLKA_posedge_posedge(7),
        SetupLow       => tsetup_ADDRA_CLKA_negedge_posedge(7),
        HoldLow        => thold_ADDRA_CLKA_posedge_posedge(7),
        HoldHigh       => thold_ADDRA_CLKA_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA0_CLKA_posedge,
        TimingData     => Tmkr_DIA0_CLKA_posedge,
        TestSignal     => DIA_ipd(0),
        TestSignalName => "DIA(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(0),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(0),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(0),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA1_CLKA_posedge,
        TimingData     => Tmkr_DIA1_CLKA_posedge,
        TestSignal     => DIA_ipd(1),
        TestSignalName => "DIA(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(1),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(1),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(1),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA2_CLKA_posedge,
        TimingData     => Tmkr_DIA2_CLKA_posedge,
        TestSignal     => DIA_ipd(2),
        TestSignalName => "DIA(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(2),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(2),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(2),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA3_CLKA_posedge,
        TimingData     => Tmkr_DIA3_CLKA_posedge,
        TestSignal     => DIA_ipd(3),
        TestSignalName => "DIA(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(3),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(3),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(3),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(3),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA4_CLKA_posedge,
        TimingData     => Tmkr_DIA4_CLKA_posedge,
        TestSignal     => DIA_ipd(4),
        TestSignalName => "DIA(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(4),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(4),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(4),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(4),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA5_CLKA_posedge,
        TimingData     => Tmkr_DIA5_CLKA_posedge,
        TestSignal     => DIA_ipd(5),
        TestSignalName => "DIA(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(5),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(5),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(5),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(5),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIA6_CLKA_posedge,
        TimingData     => Tmkr_DIA6_CLKA_posedge,
        TestSignal     => DIA_ipd(6),
        TestSignalName => "DIA(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIA_CLKA_posedge_posedge(6),
        SetupLow       => tsetup_DIA_CLKA_negedge_posedge(6),
        HoldLow        => thold_DIA_CLKA_posedge_posedge(6),
        HoldHigh       => thold_DIA_CLKA_negedge_posedge(6),
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ENB_CLKB_posedge,
        TimingData     => Tmkr_ENB_CLKB_posedge,
        TestSignal     => ENB_ipd,
        TestSignalName => "ENB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ENB_CLKB_posedge_posedge,
        SetupLow       => tsetup_ENB_CLKB_negedge_posedge,
        HoldLow        => thold_ENB_CLKB_posedge_posedge,
        HoldHigh       => thold_ENB_CLKB_negedge_posedge,
        CheckEnabled   => true,
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_RSTB_CLKB_posedge,
        TimingData     => Tmkr_RSTB_CLKB_posedge,
        TestSignal     => RSTB_ipd,
        TestSignalName => "RSTB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_RSTB_CLKB_posedge_posedge,
        SetupLow       => tsetup_RSTB_CLKB_negedge_posedge,
        HoldLow        => thold_RSTB_CLKB_posedge_posedge,
        HoldHigh       => thold_RSTB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_WEB_CLKB_posedge,
        TimingData     => Tmkr_WEB_CLKB_posedge,
        TestSignal     => WEB_ipd,
        TestSignalName => "WEB",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_WEB_CLKB_posedge_posedge,
        SetupLow       => tsetup_WEB_CLKB_negedge_posedge,
        HoldLow        => thold_WEB_CLKB_posedge_posedge,
        HoldHigh       => thold_WEB_CLKB_negedge_posedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB0_CLKB_posedge,
        TimingData     => Tmkr_ADDRB0_CLKB_posedge,
        TestSignal     => ADDRB_ipd(0),
        TestSignalName => "ADDRB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(0),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(0),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB1_CLKB_posedge,
        TimingData     => Tmkr_ADDRB1_CLKB_posedge,
        TestSignal     => ADDRB_ipd(1),
        TestSignalName => "ADDRB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(1),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(1),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB2_CLKB_posedge,
        TimingData     => Tmkr_ADDRB2_CLKB_posedge,
        TestSignal     => ADDRB_ipd(2),
        TestSignalName => "ADDRB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(2),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(2),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB3_CLKB_posedge,
        TimingData     => Tmkr_ADDRB3_CLKB_posedge,
        TestSignal     => ADDRB_ipd(3),
        TestSignalName => "ADDRB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(3),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(3),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB4_CLKB_posedge,
        TimingData     => Tmkr_ADDRB4_CLKB_posedge,
        TestSignal     => ADDRB_ipd(4),
        TestSignalName => "ADDRB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(4),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(4),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB5_CLKB_posedge,
        TimingData     => Tmkr_ADDRB5_CLKB_posedge,
        TestSignal     => ADDRB_ipd(5),
        TestSignalName => "ADDRB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(5),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(5),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB6_CLKB_posedge,
        TimingData     => Tmkr_ADDRB6_CLKB_posedge,
        TestSignal     => ADDRB_ipd(6),
        TestSignalName => "ADDRB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(6),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(6),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_ADDRB7_CLKB_posedge,
        TimingData     => Tmkr_ADDRB7_CLKB_posedge,
        TestSignal     => ADDRB_ipd(7),
        TestSignalName => "ADDRB(7)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_ADDRB_CLKB_posedge_posedge(7),
        SetupLow       => tsetup_ADDRB_CLKB_negedge_posedge(7),
        HoldLow        => thold_ADDRB_CLKB_posedge_posedge(7),
        HoldHigh       => thold_ADDRB_CLKB_negedge_posedge(7),
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        RefTransition  => 'R',
        HeaderMsg      => "/${CELL}",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB0_CLKB_posedge,
        TimingData     => Tmkr_DIB0_CLKB_posedge,
        TestSignal     => DIB_ipd(0),
        TestSignalName => "DIB(0)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(0),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(0),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(0),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(0),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB1_CLKB_posedge,
        TimingData     => Tmkr_DIB1_CLKB_posedge,
        TestSignal     => DIB_ipd(1),
        TestSignalName => "DIB(1)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(1),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(1),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(1),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(1),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB2_CLKB_posedge,
        TimingData     => Tmkr_DIB2_CLKB_posedge,
        TestSignal     => DIB_ipd(2),
        TestSignalName => "DIB(2)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(2),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(2),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(2),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(2),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB3_CLKB_posedge,
        TimingData     => Tmkr_DIB3_CLKB_posedge,
        TestSignal     => DIB_ipd(3),
        TestSignalName => "DIB(3)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(3),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(3),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(3),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(3),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB4_CLKB_posedge,
        TimingData     => Tmkr_DIB4_CLKB_posedge,
        TestSignal     => DIB_ipd(4),
        TestSignalName => "DIB(4)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(4),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(4),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(4),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(4),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB5_CLKB_posedge,
        TimingData     => Tmkr_DIB5_CLKB_posedge,
        TestSignal     => DIB_ipd(5),
        TestSignalName => "DIB(5)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(5),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(5),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(5),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(5),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_DIB6_CLKB_posedge,
        TimingData     => Tmkr_DIB6_CLKB_posedge,
        TestSignal     => DIB_ipd(6),
        TestSignalName => "DIB(6)",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => tsetup_DIB_CLKB_posedge_posedge(6),
        SetupLow       => tsetup_DIB_CLKB_negedge_posedge(6),
        HoldLow        => thold_DIB_CLKB_posedge_posedge(6),
        HoldHigh       => thold_DIB_CLKB_negedge_posedge(6),
        CheckEnabled   => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKA,
        PeriodData     => PInfo_CLKA,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKA_posedge,
        PulseWidthLow  => tpw_CLKA_negedge,
        CheckEnabled   => TO_X01(ENA_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
      VitalPeriodPulseCheck (
        Violation      => Pviol_CLKB,
        PeriodData     => PInfo_CLKB,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        Period         => 0 ps,
        PulseWidthHigh => tpw_CLKB_posedge,
        PulseWidthLow  => tpw_CLKB_negedge,
        CheckEnabled   => TO_X01(ENB_ipd_sampled) = '1',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => Xon,
        MsgOn          => MsgOn,
        MsgSeverity    => warning);
    end if;

    ViolationA := Pviol_CLKA or
                  Tviol_ADDRA0_CLKA_posedge or
                  Tviol_ADDRA1_CLKA_posedge or
                  Tviol_ADDRA2_CLKA_posedge or
                  Tviol_ADDRA3_CLKA_posedge or
                  Tviol_ADDRA4_CLKA_posedge or
                  Tviol_ADDRA5_CLKA_posedge or
                  Tviol_ADDRA6_CLKA_posedge or
                  Tviol_ADDRA7_CLKA_posedge or
                  Tviol_ADDRA8_CLKA_posedge or
                  Tviol_DIA0_CLKA_posedge or
                  Tviol_DIA1_CLKA_posedge or
                  Tviol_DIA2_CLKA_posedge or
                  Tviol_DIA3_CLKA_posedge or
                  Tviol_DIA4_CLKA_posedge or
                  Tviol_DIA5_CLKA_posedge or
                  Tviol_DIA6_CLKA_posedge or
                  Tviol_DIA7_CLKA_posedge or
                  Tviol_ENA_CLKA_posedge or
                  Tviol_RSTA_CLKA_posedge or
                  Tviol_WEA_CLKA_posedge;

    ViolationB := Pviol_CLKB or
                  Tviol_ADDRB0_CLKB_posedge or
                  Tviol_ADDRB1_CLKB_posedge or
                  Tviol_ADDRB2_CLKB_posedge or
                  Tviol_ADDRB3_CLKB_posedge or
                  Tviol_ADDRB4_CLKB_posedge or
                  Tviol_ADDRB5_CLKB_posedge or
                  Tviol_ADDRB6_CLKB_posedge or
                  Tviol_ADDRB7_CLKB_posedge or
                  Tviol_ADDRB8_CLKB_posedge or
                  Tviol_DIB0_CLKB_posedge or
                  Tviol_DIB1_CLKB_posedge or
                  Tviol_DIB2_CLKB_posedge or
                  Tviol_DIB3_CLKB_posedge or
                  Tviol_DIB4_CLKB_posedge or
                  Tviol_DIB5_CLKB_posedge or
                  Tviol_DIB6_CLKB_posedge or
                  Tviol_DIB7_CLKB_posedge or
                  Tviol_ENB_CLKB_posedge or
                  Tviol_RSTB_CLKB_posedge or
                  Tviol_WEB_CLKB_posedge;

    VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled);
    VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled);

    if (VALID_ADDRA) then
      ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled);
    end if;

    if (VALID_ADDRB) then
      ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled);
    end if;

    if (VALID_ADDRA and VALID_ADDRB) then
      addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb);
    end if;

    ViolationCLKAB := '0';

    if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKB_CLKA_posedge,
        TimingData     => Tmkr_CLKB_CLKA_posedge,
        TestSignal     => CLKB_ipd,
        TestSignalName => "CLKB",
        TestDelay      => 0 ps,
        RefSignal      => CLKA_ipd,
        RefSignalName  => "CLKA",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
      VitalSetupHoldCheck (
        Violation      => Tviol_CLKA_CLKB_posedge,
        TimingData     => Tmkr_CLKA_CLKB_posedge,
        TestSignal     => CLKA_ipd,
        TestSignalName => "CLKA",
        TestDelay      => 0 ps,
        RefSignal      => CLKB_ipd,
        RefSignalName  => "CLKB",
        RefDelay       => 0 ps,
        SetupHigh      => SETUP_ALL,
        CheckEnabled   => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true),
        RefTransition  => 'R',
        HeaderMsg      => "/RAMB4_S8_S8",
        Xon            => true,
        MsgOn          => false,
        MsgSeverity    => warning);
    end if;

    ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge;

    if (ENA_ipd_sampled = '1') then
      if (rising_edge(CLKA_ipd)) then
        if (WEA_ipd_sampled = '1') then
          if (VALID_ADDRA) then
            MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd;
          end if;
          DOA_zd                                                 := DIA_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEB_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S8_S8",
                   InstanceName => ramb4_s8_s8'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                DOA_zd := (others => 'X');

                if (RSTB_ipd_sampled = '0' ) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;

            else
              if (RSTB_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_B_Write_A,
                     EntityName => "RAMB4_S8_S8",
                     InstanceName => ramb4_s8_s8'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRA) then
            DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a)));                        
          end if;
          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_A_Write_B,
                 EntityName => "RAMB4_S8_S8",
                 InstanceName => ramb4_s8_s8'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOA_zd := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTA_ipd_sampled = '1') then
          DOA_zd := (others => '0');
        end if;
      end if;
    end if;

    if (ENB_ipd_sampled = '1') then
      if (rising_edge(CLKB_ipd)) then

        if (WEB_ipd_sampled = '1') then
          if (VALID_ADDRB) then
            MEM(ADDRESS_B) := DIB_ipd;
          end if;
          DOB_zd                                                 := DIB_ipd;

          if (ViolationCLKAB = 'X') then
            if (WEA_ipd_sampled /= '0') then
              if ((collision_type = 1) or (collision_type = 3)) then
                Memory_Collision_Msg
                  (collision_type => Write_A_Write_B,
                   EntityName => "RAMB4_S8_S8",
                   InstanceName => ramb4_s8_s8'path_name,
                   address_a => addra_ipd_sampled,
                   address_b => addrb_ipd_sampled
                   );
              end if;
              if ((collision_type = 2) or (collision_type = 3)) then
                MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');

                if (RSTA_ipd_sampled = '0' ) then
                  DOA_zd := (others => 'X');
                end if;
              end if;

            else
              if (RSTA_ipd_sampled = '0' ) then
                if ((collision_type = 1) or (collision_type = 3)) then
                  Memory_Collision_Msg
                    (collision_type => Read_A_Write_B,
                     EntityName => "RAMB4_S8_S8",
                     InstanceName => ramb4_s8_s8'path_name,
                     address_a => addra_ipd_sampled,
                     address_b => addrb_ipd_sampled
                     );
                end if;
                if ((collision_type = 2) or (collision_type = 3)) then
                  DOA_zd := (others => 'X');
                end if;
              end if;
            end if;
          end if;

        else
          if (VALID_ADDRB) then
            DOB_zd := MEM(ADDRESS_B);
          end if;

          if (ViolationCLKAB = 'X') then
            if ((collision_type = 1) or (collision_type = 3)) then
              Memory_Collision_Msg
                (collision_type => Read_B_Write_A,
                 EntityName => "RAMB4_S8_S8",
                 InstanceName => ramb4_s8_s8'path_name,
                 address_a => addra_ipd_sampled,
                 address_b => addrb_ipd_sampled
                 );
            end if;
            if ((collision_type = 2) or (collision_type = 3)) then
              DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X');
            end if;
          end if;
        end if;

        if (RSTB_ipd_sampled = '1') then
          DOB_zd := (others => '0');
        end if;
      end if;
    end if;

    DOA_zd(0)  := ViolationA xor DOA_zd(0);
    DOA_zd(1)  := ViolationA xor DOA_zd(1);
    DOA_zd(2)  := ViolationA xor DOA_zd(2);
    DOA_zd(3)  := ViolationA xor DOA_zd(3);
    DOA_zd(4)  := ViolationA xor DOA_zd(4);
    DOA_zd(5)  := ViolationA xor DOA_zd(5);
    DOA_zd(6)  := ViolationA xor DOA_zd(6);
    DOA_zd(7)  := ViolationA xor DOA_zd(7);

    DOB_zd(0)  := ViolationB xor DOB_zd(0);
    DOB_zd(1)  := ViolationB xor DOB_zd(1);
    DOB_zd(2)  := ViolationB xor DOB_zd(2);
    DOB_zd(3)  := ViolationB xor DOB_zd(3);
    DOB_zd(4)  := ViolationB xor DOB_zd(4);
    DOB_zd(5)  := ViolationB xor DOB_zd(5);
    DOB_zd(6)  := ViolationB xor DOB_zd(6);
    DOB_zd(7)  := ViolationB xor DOB_zd(7);

    VitalPathDelay01 (
      OutSignal     => DOA(0),
      GlitchData    => DOA_GlitchData0,
      OutSignalName => "DOA(0)",
      OutTemp       => DOA_zd(0),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(1),
      GlitchData    => DOA_GlitchData1,
      OutSignalName => "DOA(1)",
      OutTemp       => DOA_zd(1),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(2),
      GlitchData    => DOA_GlitchData2,
      OutSignalName => "DOA(2)",
      OutTemp       => DOA_zd(2),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(3),
      GlitchData    => DOA_GlitchData3,
      OutSignalName => "DOA(3)",
      OutTemp       => DOA_zd(3),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(4),
      GlitchData    => DOA_GlitchData4,
      OutSignalName => "DOA(4)",
      OutTemp       => DOA_zd(4),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(5),
      GlitchData    => DOA_GlitchData5,
      OutSignalName => "DOA(5)",
      OutTemp       => DOA_zd(5),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(6),
      GlitchData    => DOA_GlitchData6,
      OutSignalName => "DOA(6)",
      OutTemp       => DOA_zd(6),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOA(7),
      GlitchData    => DOA_GlitchData7,
      OutSignalName => "DOA(7)",
      OutTemp       => DOA_zd(7),
      Paths         => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(0),
      GlitchData    => DOB_GlitchData0,
      OutSignalName => "DOB(0)",
      OutTemp       => DOB_zd(0),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(1),
      GlitchData    => DOB_GlitchData1,
      OutSignalName => "DOB(1)",
      OutTemp       => DOB_zd(1),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(2),
      GlitchData    => DOB_GlitchData2,
      OutSignalName => "DOB(2)",
      OutTemp       => DOB_zd(2),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(3),
      GlitchData    => DOB_GlitchData3,
      OutSignalName => "DOB(3)",
      OutTemp       => DOB_zd(3),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(4),
      GlitchData    => DOB_GlitchData4,
      OutSignalName => "DOB(4)",
      OutTemp       => DOB_zd(4),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(5),
      GlitchData    => DOB_GlitchData5,
      OutSignalName => "DOB(5)",
      OutTemp       => DOB_zd(5),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(6),
      GlitchData    => DOB_GlitchData6,
      OutSignalName => "DOB(6)",
      OutTemp       => DOB_zd(6),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);
    VitalPathDelay01 (
      OutSignal     => DOB(7),
      GlitchData    => DOB_GlitchData7,
      OutSignalName => "DOB(7)",
      OutTemp       => DOB_zd(7),
      Paths         => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)),
      Mode          => OnEvent,
      Xon           => Xon,
      MsgOn         => MsgOn,
      MsgSeverity   => warning);

    wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd;
  end process VITALBehavior;
end RAMB4_S8_S8_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/roc.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Reset On Configuration
-- /___/   /\     Filename : ROC.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL ROC -----

library IEEE;
use IEEE.std_logic_1164.all;

entity ROC is
  generic (
    InstancePath : string := "*";
    WIDTH : time := 100 ns
    );
  port(
    O : out std_ulogic := '1'
    );
end ROC;

architecture ROC_V of ROC is
begin
  ONE_SHOT : process
  begin
    if (WIDTH <= 0 ns) then
      assert false report
        "*** Error : a positive value of WIDTH must be specified ***"
        severity failure;
    else
      wait for WIDTH;
      O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end ROC_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/rocbuf.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Reset On Configuration Buffer
-- /___/   /\     Filename : ROCBUF.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:56 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL ROCBUF -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity ROCBUF is
  port(
    O : out std_ulogic;
    I : in  std_ulogic
    );
end ROCBUF;

architecture ROCBUF_V of ROCBUF is
begin
  O <= I;
end ROCBUF_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/rom128x1.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  128-Deep by 1-Wide ROM
-- /___/   /\     Filename : ROM128X1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:57 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL ROM128X1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity ROM128X1 is

  generic (
    INIT : bit_vector := X"00000000000000000000000000000000"
    );

  port (
    O : out std_ulogic;

    A0 : in std_ulogic;
    A1 : in std_ulogic;
    A2 : in std_ulogic;
    A3 : in std_ulogic;
    A4 : in std_ulogic;
    A5 : in std_ulogic;
    A6 : in std_ulogic
    );
end ROM128X1;

architecture ROM128X1_V of ROM128X1 is
begin
  VITALBehavior         : process (A6, A5, A4, A3, A2, A1, A0)
    variable INIT_BITS  : std_logic_vector(127 downto 0) := To_StdLogicVector(INIT);
    variable MEM        : std_logic_vector( 128 downto 0 );
    variable Index      : integer := 128;
    variable Raddress   : std_logic_vector (6 downto 0);
    variable FIRST_TIME : boolean := true;

  begin
    if (FIRST_TIME = true) then
      MEM        := ('X' & INIT_BITS(127 downto 0));
      FIRST_TIME := false;
    end if;
    Raddress     := (A6, A5, A4, A3, A2, A1, A0);
    Index        := SLV_TO_INT(SLV => Raddress);
    O <= MEM(Index);
  end process VITALBehavior;
end ROM128X1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/rom16x1.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16-Deep by 1-Wide ROM
-- /___/   /\     Filename : ROM16X1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:57 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL ROM16X1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity ROM16X1 is
  generic (
       INIT : bit_vector := X"0000"
  );

  port (
        O : out std_ulogic;
        
        A0 : in std_ulogic;
        A1 : in std_ulogic;
        A2 : in std_ulogic;
        A3 : in std_ulogic
       );
end ROM16X1;

architecture ROM16X1_V of ROM16X1 is
begin
  VITALBehavior : process (A3, A2, A1, A0)
    variable INIT_BITS  : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT);
    variable MEM : std_logic_vector( 16 downto 0 ) ;
    variable Index : integer := 16;
    variable FIRST_TIME : boolean := TRUE;    
  begin
     if (FIRST_TIME = TRUE) then
       MEM := ('X' & INIT_BITS(15 downto 0));
      FIRST_TIME := FALSE;
    end if;
    Index := DECODE_ADDR4(ADDRESS => (A3, A2, A1, A0));
    O <= MEM(Index); 
  end process VITALBehavior;
end ROM16X1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/rom256x1.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  256-Deep by 1-Wide ROM
-- /___/   /\     Filename : ROM256X1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:57 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL ROM256X1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity ROM256X1 is
  generic (
    INIT : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
    );

  port (
    O : out std_ulogic;

    A0 : in std_ulogic;
    A1 : in std_ulogic;
    A2 : in std_ulogic;
    A3 : in std_ulogic;
    A4 : in std_ulogic;
    A5 : in std_ulogic;
    A6 : in std_ulogic;
    A7 : in std_ulogic
    );
end ROM256X1;

architecture ROM256X1_V of ROM256X1 is
begin
  VITALBehavior         : process (A7, A6, A5, A4, A3, A2, A1, A0)
    variable INIT_BITS  : std_logic_vector(255 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
    variable MEM        : std_logic_vector( 256 downto 0 );
    variable Index      : integer                        := 256;
    variable Raddress   : std_logic_vector (7 downto 0);
    variable FIRST_TIME : boolean                        := true;

  begin
    if (FIRST_TIME = true) then
      INIT_BITS(INIT'length-1 downto 0) := To_StdLogicVector(INIT );
      MEM        := ('X' & INIT_BITS(255 downto 0));
      FIRST_TIME := false;
    end if;
    Raddress     := (A7, A6, A5, A4, A3, A2, A1, A0);
    Index        := SLV_TO_INT(SLV => Raddress );
    O <= MEM(Index);
  end process VITALBehavior;
end ROM256X1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/rom32x1.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  32-Deep by 1-Wide ROM
-- /___/   /\     Filename : ROM32X1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:57 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL ROM32X1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity ROM32X1 is
  generic (
    INIT : bit_vector := X"00000000"
    );

  port (
    O : out std_ulogic;

    A0 : in std_ulogic;
    A1 : in std_ulogic;
    A2 : in std_ulogic;
    A3 : in std_ulogic;
    A4 : in std_ulogic
    );
end ROM32X1;

architecture ROM32X1_V of ROM32X1 is
begin
  VITALBehavior         : process (A4, A3, A2, A1, A0)
    variable INIT_BITS  : std_logic_vector(31 downto 0) := To_StdLogicVector(INIT);
    variable MEM        : std_logic_vector( 32 downto 0 );
    variable Index      : integer                       := 32;
    variable FIRST_TIME : boolean                       := true;

  begin
    if (FIRST_TIME = true) then
      MEM        := ('X' & INIT_BITS(31 downto 0));
      FIRST_TIME := false;
    end if;
    Index        := DECODE_ADDR5(ADDRESS => (A4, A3, A2, A1, A0));
    O <= MEM(Index);
  end process VITALBehavior;
end ROM32X1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/rom64x1.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  64-Deep by 1-Wide ROM
-- /___/   /\     Filename : ROM64X1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:57 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL ROM64X1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity ROM64X1 is
  generic (
    INIT : bit_vector := X"0000000000000000"
    );

  port (
    O : out std_ulogic;

    A0 : in std_ulogic;
    A1 : in std_ulogic;
    A2 : in std_ulogic;
    A3 : in std_ulogic;
    A4 : in std_ulogic;
    A5 : in std_ulogic
    );
end ROM64X1;
architecture ROM64X1_V of ROM64X1 is
begin
  VITALBehavior        : process (A5, A4, A3, A2, A1, A0)
    variable INIT_BITS : std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
    variable MEM       : std_logic_vector( 64 downto 0 );
    variable Index     : integer                       := 64;
    variable Raddress  : std_logic_vector (5 downto 0);
    variable FIRST_TIME : boolean                       := true;
  begin
    if (FIRST_TIME = true) then
      INIT_BITS(INIT'length-1 downto 0) := To_StdLogicVector(INIT );
      MEM        := ('X' & INIT_BITS(63 downto 0));
      FIRST_TIME := false;
    end if;
    Raddress     := (A5, A4, A3, A2, A1, A0);
    Index        := SLV_TO_INT(SLV => Raddress );
    O <= MEM(Index);
  end process VITALBehavior;
end ROM64X1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/srl16.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16-Bit Shift Register Look-Up-Table
-- /___/   /\     Filename : SRL16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:57 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL SRL16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity SRL16 is

  generic (
       INIT : bit_vector := X"0000"
  );

  port (
        Q   : out STD_ULOGIC;
        
        A0  : in STD_ULOGIC;
        A1  : in STD_ULOGIC;
        A2  : in STD_ULOGIC;
        A3  : in STD_ULOGIC;
        CLK : in STD_ULOGIC;        
        D   : in STD_ULOGIC
       ); 
end SRL16;

architecture SRL16_V of SRL16 is

  signal SHIFT_REG : std_logic_vector (16 downto 0) := ('X' & To_StdLogicVector(INIT));
 
begin

  VITALReadBehavior : process(A0, A1, A2, A3, SHIFT_REG)

    variable VALID_ADDR : boolean := FALSE;
    variable LENGTH : integer;
    variable ADDR: std_logic_vector (3 downto 0) ;

  begin

    ADDR := (A3, A2, A1, A0);
    VALID_ADDR := ADDR_IS_VALID(SLV => ADDR);

    if (VALID_ADDR) then
        LENGTH := SLV_TO_INT(SLV => ADDR);
    else
        LENGTH := 16;
    end if;
    Q <= SHIFT_REG(LENGTH);

  end process VITALReadBehavior;

VITALWriteBehavior : process

    variable FIRST_TIME : boolean := TRUE;

  begin

    if (FIRST_TIME) then
        wait until ((CLK'last_value = '0' or CLK'last_value = '1') and
                    (CLK = '0' or CLK = '1'));
        FIRST_TIME := FALSE;
    end if;

    if (CLK'event AND CLK'last_value = '0') then
      if (CLK = '1') then
        for I in 15 downto 1 loop
          SHIFT_REG(I) <= SHIFT_REG(I-1) after 100 ps;
        end loop;
        SHIFT_REG(0) <= D after 100 ps;
      elsif (CLK = 'X') then
        SHIFT_REG <= (others => 'X') after 100 ps;
      end if;
    elsif (CLK'event AND CLK'last_value = 'X') then
      if (CLK = '1') then
        SHIFT_REG <= (others => 'X') after 100 ps;
      end if;
    end if;

    wait on CLK;

  end process VITALWriteBehavior;

end SRL16_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/srl16_1.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16-Bit Shift Register Look-Up-Table with Negative-Edge Clock
-- /___/   /\     Filename : SRL16_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:57 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL SRL16_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity SRL16_1 is

  generic (
       INIT : bit_vector := X"0000"
  );

  port (
        Q   : out STD_ULOGIC;
        
        A0  : in STD_ULOGIC;
        A1  : in STD_ULOGIC;
        A2  : in STD_ULOGIC;
        A3  : in STD_ULOGIC;
        CLK : in STD_ULOGIC;        
        D   : in STD_ULOGIC
       ); 
end SRL16_1;

architecture SRL16_1_V of SRL16_1 is
  signal SHIFT_REG : std_logic_vector (16 downto 0) := ('X' & To_StdLogicVector(INIT));  
begin

  VITALreadBehavior : process (A0, A1, A2, A3, SHIFT_REG)

    variable VALID_ADDR : boolean := FALSE;
    variable LENGTH : integer;
    variable ADDR: std_logic_vector (3 downto 0) ;

  begin
    ADDR := (A3, A2, A1, A0);
    VALID_ADDR := ADDR_IS_VALID(SLV => ADDR);

    if (VALID_ADDR) then
        LENGTH := SLV_TO_INT(SLV => ADDR);
    else
        LENGTH := 16;
    end if;
    Q <= SHIFT_REG(LENGTH);

  end process VITALReadBehavior;

VITALWriteBehavior : process
    variable FIRST_TIME : boolean := TRUE;
  begin

    if (FIRST_TIME) then
        wait until ((CLK'last_value = '0' or CLK'last_value = '1') and
                    (CLK = '0' or CLK = '1'));
        FIRST_TIME := FALSE;
    end if;

    if (CLK'event AND CLK'last_value = '1') then
      if (CLK = '0') then
        for I in 15 downto 1 loop
          SHIFT_REG(I) <= SHIFT_REG(I-1) after 100 ps;
        end loop;
        SHIFT_REG(0) <= D after 100 ps;
      elsif (CLK = 'X') then
        SHIFT_REG <= (others => 'X') after 100 ps;
      end if;
    elsif (CLK'event AND CLK'last_value = 'X') then
      if (CLK = '0') then
        SHIFT_REG <= (others => 'X') after 100 ps;
      end if;
    end if;

    wait on CLK;

  end process VITALWriteBehavior;
end SRL16_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/srl16e.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16-Bit Shift Register Look-Up-Table with Clock Enable
-- /___/   /\     Filename : SRL16E.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:57 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL SRL16E -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity SRL16E is

  generic (
       INIT : bit_vector := X"0000"
  );

  port (
        Q   : out STD_ULOGIC;
        
        A0  : in STD_ULOGIC;
        A1  : in STD_ULOGIC;
        A2  : in STD_ULOGIC;
        A3  : in STD_ULOGIC;
        CE  : in STD_ULOGIC;        
        CLK : in STD_ULOGIC;
        D   : in STD_ULOGIC
       ); 
end SRL16E;

architecture SRL16E_V of SRL16E is
    signal SHIFT_REG : std_logic_vector (16 downto 0) := ('X' & To_StdLogicVector(INIT));
begin
  VITALReadBehavior : process(A0, A1, A2, A3, SHIFT_REG)

    variable VALID_ADDR : boolean := FALSE;
    variable LENGTH : integer;
    variable ADDR : std_logic_vector(3 downto 0);

  begin

    ADDR := (A3, A2, A1, A0);
    VALID_ADDR := ADDR_IS_VALID(SLV => ADDR);

    if (VALID_ADDR) then
        LENGTH := SLV_TO_INT(SLV => ADDR);
    else
        LENGTH := 16;
    end if;
    Q <= SHIFT_REG(LENGTH);

  end process VITALReadBehavior;

  VITALWriteBehavior : process
    variable FIRST_TIME : boolean := TRUE;
  begin

    if (FIRST_TIME) then
        wait until ((CE = '1' or CE = '0') and
                   (CLK'last_value = '0' or CLK'last_value = '1') and
                   (CLK = '0' or CLK = '1'));
        FIRST_TIME := FALSE;
    end if;

    if (CLK'event AND CLK'last_value = '0') then
      if (CLK = '1') then
        if (CE = '1') then
          for I in 15 downto 1 loop
            SHIFT_REG(I) <= SHIFT_REG(I-1) after 100 ps;
          end loop;
          SHIFT_REG(0) <= D after 100 ps;
        elsif (CE = 'X') then
          SHIFT_REG <= (others => 'X') after 100 ps;
        end if;
      elsif (CLK = 'X') then
        if (CE /= '0') then
          SHIFT_REG <= (others => 'X') after 100 ps;
        end if;
      end if;
    elsif (CLK'event AND CLK'last_value = 'X') then
      if (CLK = '1') then
        if (CE /= '0') then
          SHIFT_REG <= (others => 'X') after 100 ps;
        end if;
      end if;
    end if;
    wait on CLK;
  end process VITALWriteBehavior;
end SRL16E_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/srl16e_1.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16-Bit Shift Register Look-Up-Table with Clock Enable and Negative-Edge Clock
-- /___/   /\     Filename : SRL16E_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:57 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL SRL16E_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity SRL16E_1 is

  generic (
       INIT : bit_vector := X"0000"
  );

  port (
        Q   : out STD_ULOGIC;
        
        A0  : in STD_ULOGIC;
        A1  : in STD_ULOGIC;
        A2  : in STD_ULOGIC;
        A3  : in STD_ULOGIC;        
        CE  : in STD_ULOGIC;
        CLK : in STD_ULOGIC;
        D   : in STD_ULOGIC
       ); 
end SRL16E_1;

architecture SRL16E_1_V of SRL16E_1 is
signal SHIFT_REG : std_logic_vector (16 downto 0) := ('X' & To_StdLogicVector( INIT));

 
begin
  VITALReadBehavior : process(A0, A1, A2, A3, SHIFT_REG)
    variable ADDR : std_logic_vector(3 downto 0);
    variable VALID_ADDR : boolean := FALSE;
    variable LENGTH : integer;

  begin

    ADDR := (A3, A2, A1, A0);
    VALID_ADDR := ADDR_IS_VALID(SLV => ADDR);

    if (VALID_ADDR) then
        LENGTH := SLV_TO_INT(SLV => ADDR);
    else
        LENGTH := 16;
    end if;
    Q <= SHIFT_REG(LENGTH);

  end process VITALReadBehavior;

  VITALWriteBehavior : process
    variable FIRST_TIME : boolean := TRUE;
  begin
    if (FIRST_TIME) then
        wait until ((CE = '1' or CE = '0') and 
                   (CLK'last_value = '0' or CLK'last_value = '1') and
                   (CLK = '0' or CLK = '1'));
        FIRST_TIME := FALSE;
    end if;

    if (CLK'event AND CLK'last_value = '1') then
      if (CLK = '0') then
        if (CE = '1') then
          for I in 15 downto 1 loop
            SHIFT_REG(I) <= SHIFT_REG(I-1) after 100 ps;
          end loop;
          SHIFT_REG(0) <= D after 100 ps;
        elsif (CE = 'X') then
          SHIFT_REG <= (others => 'X') after 100 ps;
        end if;
      elsif (CLK = 'X') then
        if (CE /= '0') then
          SHIFT_REG <= (others => 'X') after 100 ps;
        end if;
      end if;
    elsif (CLK'event AND CLK'last_value = 'X') then
      if (CLK = '0') then
        if (CE /= '0') then
          SHIFT_REG <= (others => 'X') after 100 ps;
        end if;
      end if;
    end if;
    wait on CLK;
  end process VITALWriteBehavior;

end SRL16E_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/srlc16.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16-Bit Shift Register Look-Up-Table with Carry
-- /___/   /\     Filename : SRLC16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:58 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL SRLC16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity SRLC16 is

  generic (
       INIT : bit_vector := X"0000"
  );

  port (
        Q   : out STD_ULOGIC;
        Q15 : out STD_ULOGIC;
        
        A0  : in STD_ULOGIC;
        A1  : in STD_ULOGIC;
        A2  : in STD_ULOGIC;
        A3  : in STD_ULOGIC;
        CLK : in STD_ULOGIC;        
        D   : in STD_ULOGIC
       ); 
end SRLC16;

architecture SRLC16_V of SRLC16 is
  signal SHIFT_REG : std_logic_vector (16 downto 0) := ('X' & To_StdLogicVector(INIT));
begin
  VITALReadBehavior : process(A0, A1, A2, A3, SHIFT_REG)

    variable VALID_ADDR : boolean := FALSE;
    variable LENGTH : integer;
    variable ADDR: std_logic_vector (3 downto 0) ;

  begin

    ADDR := (A3, A2, A1, A0);
    VALID_ADDR := ADDR_IS_VALID(SLV => ADDR);

    if (VALID_ADDR) then
        LENGTH := SLV_TO_INT(SLV => ADDR);
    else
        LENGTH := 16;
    end if;
    Q <= SHIFT_REG(LENGTH);
    Q15 <= SHIFT_REG(15);

  end process VITALReadBehavior;

VITALWriteBehavior : process

    variable FIRST_TIME : boolean := TRUE;

  begin -- process

    if (FIRST_TIME) then
        wait until ((CLK'last_value = '0' or CLK'last_value = '1') and
                    (CLK = '0' or CLK = '1'));
        FIRST_TIME := FALSE;
    end if;

    if (CLK'event AND CLK'last_value = '0') then
      if (CLK = '1') then
        for I in 15 downto 1 loop
          SHIFT_REG(I) <= SHIFT_REG(I-1) after 100 ps;
        end loop;
        SHIFT_REG(0) <= D after 100 ps;
      elsif (CLK = 'X') then
        SHIFT_REG <= (others => 'X') after 100 ps;
      end if;
    elsif (CLK'event AND CLK'last_value = 'X') then
      if (CLK = '1') then
        SHIFT_REG <= (others => 'X') after 100 ps;
      end if;
    end if;

    wait on CLK;
  end process VITALWriteBehavior;
end SRLC16_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/srlc16_1.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16-Bit Shift Register Look-Up-Table with Carry and Negative-Edge Clock
-- /___/   /\     Filename : SRLC16_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:58 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL SRLC16_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity SRLC16_1 is

  generic (
       INIT : bit_vector := X"0000"
  );

  port (
        Q   : out STD_ULOGIC;
        Q15   : out STD_ULOGIC;
        
        A0  : in STD_ULOGIC;
        A1  : in STD_ULOGIC;
        A2  : in STD_ULOGIC;
        A3  : in STD_ULOGIC;
        CLK : in STD_ULOGIC;        
        D   : in STD_ULOGIC
       ); 
end SRLC16_1;

architecture SRLC16_1_V of SRLC16_1 is
  signal SHIFT_REG : std_logic_vector (16 downto 0) := ('X' & To_StdLogicVector(INIT));
begin
  VITALreadBehavior : process (A0, A1, A2, A3, SHIFT_REG)

    variable VALID_ADDR : boolean := FALSE;
    variable LENGTH : integer;
    variable ADDR: std_logic_vector (3 downto 0) ;

  begin

    ADDR := (A3, A2, A1, A0);
    VALID_ADDR := ADDR_IS_VALID(SLV => ADDR);

    if (VALID_ADDR) then
        LENGTH := SLV_TO_INT(SLV => ADDR);
    else
        LENGTH := 16;
    end if;
    Q <= SHIFT_REG(LENGTH);
    Q15 <= SHIFT_REG(15);
  end process VITALReadBehavior;

VITALWriteBehavior : process
    variable FIRST_TIME : boolean := TRUE;
  begin
    if (FIRST_TIME) then
        wait until ((CLK'last_value = '0' or CLK'last_value = '1') and
                    (CLK = '0' or CLK = '1'));
        FIRST_TIME := FALSE;
    end if;

    if (CLK'event AND CLK'last_value = '1') then
      if (CLK = '0') then
        for I in 15 downto 1 loop
          SHIFT_REG(I) <= SHIFT_REG(I-1) after 100 ps;
        end loop;
        SHIFT_REG(0) <= D after 100 ps;
      elsif (CLK = 'X') then
        SHIFT_REG <= (others => 'X') after 100 ps;
      end if;
    elsif (CLK'event AND CLK'last_value = 'X') then
      if (CLK = '0') then
        SHIFT_REG <= (others => 'X') after 100 ps;
      end if;
    end if;

    wait on CLK;

  end process VITALWriteBehavior;
end SRLC16_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/srlc16e.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16-Bit Shift Register Look-Up-Table with Carry and Clock Enable
-- /___/   /\     Filename : SRLC16E.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:58 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL SRLC16E -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity SRLC16E is

  generic (
       INIT : bit_vector := X"0000"
  );

  port (
        Q   : out STD_ULOGIC;
        Q15 : out STD_ULOGIC;
        
        A0  : in STD_ULOGIC;
        A1  : in STD_ULOGIC;
        A2  : in STD_ULOGIC;
        A3  : in STD_ULOGIC;
        CE  : in STD_ULOGIC;
        CLK : in STD_ULOGIC;        
        D   : in STD_ULOGIC
       ); 
end SRLC16E;

architecture SRLC16E_V of SRLC16E is
  signal SHIFT_REG : std_logic_vector (16 downto 0) := ('X' & To_StdLogicVector(INIT));
begin
  VITALReadBehavior : process(A0, A1, A2, A3, SHIFT_REG)

    variable VALID_ADDR : boolean := FALSE;
    variable LENGTH : integer;
    variable ADDR : std_logic_vector(3 downto 0);

  begin

    ADDR := (A3, A2, A1, A0);
    VALID_ADDR := ADDR_IS_VALID(SLV => ADDR);

    if (VALID_ADDR) then
        LENGTH := SLV_TO_INT(SLV => ADDR);
    else
        LENGTH := 16;
    end if;
    Q <= SHIFT_REG(LENGTH);
    Q15 <= SHIFT_REG(15);

  end process VITALReadBehavior;

  VITALWriteBehavior : process

    variable FIRST_TIME : boolean := TRUE;

  begin

    if (FIRST_TIME) then
        wait until ((CE = '1' or CE = '0') and
                   (CLK'last_value = '0' or CLK'last_value = '1') and
                   (CLK = '0' or CLK = '1'));
        FIRST_TIME := FALSE;
    end if;

    if (CLK'event AND CLK'last_value = '0') then
      if (CLK = '1') then
        if (CE = '1') then
          for I in 15 downto 1 loop
            SHIFT_REG(I) <= SHIFT_REG(I-1) after 100 ps;
          end loop;
          SHIFT_REG(0) <= D after 100 ps;
        elsif (CE = 'X') then
          SHIFT_REG <= (others => 'X') after 100 ps;
        end if;
      elsif (CLK = 'X') then
        if (CE /= '0') then
          SHIFT_REG <= (others => 'X') after 100 ps;
        end if;
      end if;
    elsif (CLK'event AND CLK'last_value = 'X') then
      if (CLK = '1') then
        if (CE /= '0') then
          SHIFT_REG <= (others => 'X') after 100 ps;
        end if;
      end if;
    end if;

    wait on CLK;

  end process VITALWriteBehavior;
end SRLC16E_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/srlc16e_1.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16-Bit Shift Register Look-Up-Table with Carry, Clock Enable and Negative-Edge Clock
-- /___/   /\     Filename : SRLC16E_1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:58 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL SRLC16E_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity SRLC16E_1 is

  generic (
       INIT : bit_vector := X"0000"
  );

  port (
        Q   : out STD_ULOGIC;
        Q15   : out STD_ULOGIC;
        
        A0  : in STD_ULOGIC;
        A1  : in STD_ULOGIC;
        A2  : in STD_ULOGIC;
        A3  : in STD_ULOGIC;
        CE  : in STD_ULOGIC;        
        CLK : in STD_ULOGIC;
        D   : in STD_ULOGIC
       ); 
end SRLC16E_1;

architecture SRLC16E_1_V of SRLC16E_1 is
  signal SHIFT_REG : std_logic_vector (16 downto 0) := ('X' & To_StdLogicVector( INIT));

begin
  VITALReadBehavior : process(A0, A1, A2, A3, SHIFT_REG)

    variable ADDR : std_logic_vector(3 downto 0);
    variable VALID_ADDR : boolean := FALSE;
    variable LENGTH : integer;

  begin

    ADDR := (A3, A2, A1, A0);
    VALID_ADDR := ADDR_IS_VALID(SLV => ADDR);

    if (VALID_ADDR) then
        LENGTH := SLV_TO_INT(SLV => ADDR);
    else
        LENGTH := 16;
    end if;
    Q <= SHIFT_REG(LENGTH);
    Q15 <= SHIFT_REG(15);

  end process VITALReadBehavior;

  VITALWriteBehavior : process

    variable FIRST_TIME : boolean := TRUE;


  begin

    if (FIRST_TIME) then
        wait until ((CE = '1' or CE = '0') and 
                   (CLK'last_value = '0' or CLK'last_value = '1') and
                   (CLK = '0' or CLK = '1'));
        FIRST_TIME := FALSE;
    end if;
    if (CLK'event AND CLK'last_value = '1') then
      if (CLK = '0') then
        if (CE = '1') then
          for I in 15 downto 1 loop
            SHIFT_REG(I) <= SHIFT_REG(I-1) after 100 ps;
          end loop;
          SHIFT_REG(0) <= D after 100 ps;
        elsif (CE = 'X') then
          SHIFT_REG <= (others => 'X') after 100 ps;
        end if;
      elsif (CLK = 'X') then
        if (CE /= '0') then
          SHIFT_REG <= (others => 'X') after 100 ps;
        end if;
      end if;
    elsif (CLK'event AND CLK'last_value = 'X') then
      if (CLK = '0') then
        if (CE /= '0') then
          SHIFT_REG <= (others => 'X') after 100 ps;
        end if;
      end if;
    end if;

    wait on CLK;

  end process VITALWriteBehavior;
end SRLC16E_1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/startbuf_fpgacore.vhd,v 1.5 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  User Interface to Global Clock, Reset and 3-State Controls for FPGACORE
-- /___/   /\     Filename : STARTBUF_FPGACORE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:58 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL STARTBUF_FPGACORE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity STARTBUF_FPGACORE is
    port(
          GSROUT    : out std_ulogic;

          CLKIN     : in std_ulogic := 'X';          
          GSRIN     : in std_ulogic := 'X'
);
end STARTBUF_FPGACORE;

architecture STARTBUF_FPGACORE_V of STARTBUF_FPGACORE is
begin
      GSROUT    <= TO_X01(GSRIN);
end STARTBUF_FPGACORE_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/startbuf_spartan2.vhd,v 1.5 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  User Interface to Global Clock, Reset and 3-State Controls for SPARTAN2
-- /___/   /\     Filename : STARTBUF_SPARTAN2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:58 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL STARTBUF_SPARTAN2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity STARTBUF_SPARTAN2 is
    port(
          GSROUT    : out std_ulogic;                    
          GTSOUT    : out std_ulogic;
          
          CLKIN     : in std_ulogic := 'X';
          GSRIN     : in std_ulogic := 'X';
          GTSIN     : in std_ulogic := 'X'
          );
end STARTBUF_SPARTAN2;

architecture STARTBUF_SPARTAN2_V of STARTBUF_SPARTAN2 is
  begin
      GTSOUT    <= TO_X01(GTSIN);
      GSROUT    <= TO_X01(GSRIN);
 end STARTBUF_SPARTAN2_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/startbuf_spartan3.vhd,v 1.5 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  User Interface to Global Clock, Reset and 3-State Controls for SPARTAN3
-- /___/   /\     Filename : STARTBUF_SPARTAN3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:58 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL STARTBUF_SPARTAN3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity STARTBUF_SPARTAN3 is
    port(
          GSROUT    : out std_ulogic;
          GTSOUT    : out std_ulogic;
          
          CLKIN     : in std_ulogic := 'X';          
          GSRIN     : in std_ulogic := 'X';
          GTSIN     : in std_ulogic := 'X'
);
end STARTBUF_SPARTAN3;

architecture STARTBUF_SPARTAN3_V of STARTBUF_SPARTAN3 is
   begin
      GTSOUT    <= TO_X01(GTSIN);
      GSROUT    <= TO_X01(GSRIN);
 end STARTBUF_SPARTAN3_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/startbuf_virtex.vhd,v 1.5 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  User Interface to Global Clock, Reset and 3-State Controls for VIRTEX
-- /___/   /\     Filename : STARTBUF_VIRTEX.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:58 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL STARTBUF_VIRTEX -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity STARTBUF_VIRTEX is
    port(
          GSROUT    : out std_ulogic;
          GTSOUT    : out std_ulogic;
          
          CLKIN     : in std_ulogic := 'X';          
          GSRIN     : in std_ulogic := 'X';
          GTSIN     : in std_ulogic := 'X'
);
end STARTBUF_VIRTEX;

architecture STARTBUF_VIRTEX_V of STARTBUF_VIRTEX is
  begin
      GTSOUT    <= TO_X01(GTSIN);
      GSROUT    <= TO_X01(GSRIN);
 end STARTBUF_VIRTEX_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/startbuf_virtex2.vhd,v 1.5 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  User Interface to Global Clock, Reset and 3-State Controls for VIRTEX2
-- /___/   /\     Filename : STARTBUF_VIRTEX2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:58 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL STARTBUF_VIRTEX2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity STARTBUF_VIRTEX2 is
    port(
          GSROUT    : out std_ulogic;
          GTSOUT    : out std_ulogic;
          
          CLKIN     : in std_ulogic := 'X';          
          GSRIN     : in std_ulogic := 'X';
          GTSIN     : in std_ulogic := 'X'
);
end STARTBUF_VIRTEX2;

architecture STARTBUF_VIRTEX2_V of STARTBUF_VIRTEX2 is
  begin
      GTSOUT    <= TO_X01(GTSIN);
      GSROUT    <= TO_X01(GSRIN);
 end STARTBUF_VIRTEX2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/startup_fpgacore.vhd,v 1.5 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  User Interface to Global Clock, Reset and 3-State Controls for FPGACORE
-- /___/   /\     Filename : STARTUP_FPGACORE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:59 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL STARTUP_FPGACORE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity STARTUP_FPGACORE is
  port(
    CLK : in std_ulogic := 'X';
    GSR : in std_ulogic := 'X'
    );
end STARTUP_FPGACORE;

architecture STARTUP_FPGACORE_V of STARTUP_FPGACORE is
begin
end STARTUP_FPGACORE_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/startup_spartan2.vhd,v 1.5 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  User Interface to Global Clock, Reset and 3-State Controls for SPARTAN2
-- /___/   /\     Filename : STARTUP_SPARTAN2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:59 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL STARTUP_SPARTAN2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity STARTUP_SPARTAN2 is
  port(
    CLK : in std_ulogic := 'X';
    GSR : in std_ulogic := 'X';
    GTS : in std_ulogic := 'X'
    );
end STARTUP_SPARTAN2;

architecture STARTUP_SPARTAN2_V of STARTUP_SPARTAN2 is
begin
end STARTUP_SPARTAN2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/startup_spartan3.vhd,v 1.5 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  User Interface to Global Clock, Reset and 3-State Controls for SPARTAN3
-- /___/   /\     Filename : STARTUP_SPARTAN3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:59 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL STARTUP_SPARTAN3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity STARTUP_SPARTAN3 is
  port(
    CLK : in std_ulogic := 'X';
    GSR : in std_ulogic := 'X';
    GTS : in std_ulogic := 'X'
    );
end STARTUP_SPARTAN3;

architecture STARTUP_SPARTAN3_V of STARTUP_SPARTAN3 is
begin
end STARTUP_SPARTAN3_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/startup_virtex.vhd,v 1.5 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  User Interface to Global Clock, Reset and 3-State Controls for VIRTEX
-- /___/   /\     Filename : STARTUP_VIRTEX.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:59 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL STARTUP_VIRTEX -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity STARTUP_VIRTEX is
  port(
    CLK : in std_ulogic := 'X';
    GSR : in std_ulogic := 'X';
    GTS : in std_ulogic := 'X'
    );
end STARTUP_VIRTEX;

architecture STARTUP_VIRTEX_V of STARTUP_VIRTEX is
begin
end STARTUP_VIRTEX_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/startup_virtex2.vhd,v 1.5 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  User Interface to Global Clock, Reset and 3-State Controls for VIRTEX2
-- /___/   /\     Filename : STARTUP_VIRTEX2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:59 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL STARTUP_VIRTEX2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity STARTUP_VIRTEX2 is
  port(
    CLK : in std_ulogic := 'X';
    GSR : in std_ulogic := 'X';
    GTS : in std_ulogic := 'X'
    );
end STARTUP_VIRTEX2;

architecture STARTUP_VIRTEX2_V of STARTUP_VIRTEX2 is
begin
end STARTUP_VIRTEX2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/tblock.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  
-- /___/   /\     Filename : TBLOCK.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:59 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL TBLOCK -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity TBLOCK is
end TBLOCK;

architecture TBLOCK_V of TBLOCK is
begin
end TBLOCK_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/timegrp.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  
-- /___/   /\     Filename : TIMEGRP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:59 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL TIMEGRP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity TIMEGRP is
end TIMEGRP;

architecture TIMEGRP_V of TIMEGRP is
begin
end TIMEGRP_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/timespec.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  
-- /___/   /\     Filename : TIMESPEC.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:59 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL TIMESPEC -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity TIMESPEC is
end TIMESPEC;

architecture TIMESPEC_V of TIMESPEC is
begin
end TIMESPEC_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/toc.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Three-State on Configuration
-- /___/   /\     Filename : TOC.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:00 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL TOC -----

library IEEE;
use IEEE.std_logic_1164.all;

entity TOC is
  generic (
    InstancePath : string := "*";
    WIDTH        : time   := 100 ns
    );

  port(
    O : out std_ulogic := '0'
    );
end TOC;

architecture TOC_V of TOC is
begin
  ONE_SHOT : process
  begin
    O         <= '1';
    if (WIDTH <= 0 ns) then
      O       <= '0';
    else
      wait for WIDTH;
      O       <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end TOC_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/tocbuf.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Three-State on Configuration Buffer
-- /___/   /\     Filename : TOCBUF.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:00 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL TOCBUF -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity TOCBUF is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end TOCBUF;

architecture TOCBUF_V of TOCBUF is
begin
  O <= I;
end TOCBUF_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/vcc.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  VCC Connection
-- /___/   /\     Filename : VCC.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:00 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL VCC -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity VCC is
  port(
    P : out std_ulogic := '1'
    );
end VCC;

architecture VCC_V of VCC is
begin
  P <= '1';
end VCC_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xnor2.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-input XNOR Gate
-- /___/   /\     Filename : XNOR2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:00 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL XNOR2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity XNOR2 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic
    );
end XNOR2;

architecture XNOR2_V of XNOR2 is
begin
  O <= (not (I0 xor I1));
end XNOR2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xnor3.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-input XNOR Gate
-- /___/   /\     Filename : XNOR3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:00 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL XNOR3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity XNOR3 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic
    );
end XNOR3;

architecture XNOR3_V of XNOR3 is
begin
  O <= (not (I0 xor I1 xor I2));
end XNOR3_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xnor4.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input XNOR Gate
-- /___/   /\     Filename : XNOR4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:00 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL XNOR4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity XNOR4 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic
    );
end XNOR4;

architecture XNOR4_V of XNOR4 is
begin
  O <= (not (I0 xor I1 xor I2 xor I3));
end XNOR4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xnor5.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input XNOR Gate
-- /___/   /\     Filename : XNOR5.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:00 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL XNOR5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity XNOR5 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end XNOR5;

architecture XNOR5_V of XNOR5 is
begin
  O <= (not (I0 xor I1 xor I2 xor I3 xor I4));
end XNOR5_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xor2.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  2-input XOR Gate
-- /___/   /\     Filename : XOR2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:00 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL XOR2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity XOR2 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic
    );
end XOR2;

architecture XOR2_V of XOR2 is
begin
  O <= (I0 xor I1);
end XOR2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xor3.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-input XOR Gate
-- /___/   /\     Filename : XOR3.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:01 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL XOR3 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity XOR3 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic
    );
end XOR3;

architecture XOR3_V of XOR3 is
begin
  O <= (I0 xor I1 xor I2);
end XOR3_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xor4.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  4-input XOR Gate
-- /___/   /\     Filename : XOR4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:01 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL XOR4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity XOR4 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic
    );
end XOR4;

architecture XOR4_V of XOR4 is
begin
  O <= (I0 xor I1 xor I2 xor I3);
end XOR4_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xor5.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input XOR Gate
-- /___/   /\     Filename : XOR5.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:01 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL XOR5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity XOR5 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end XOR5;

architecture XOR5_V of XOR5 is
begin
  O <= (I0 xor I1 xor I2 xor I3 xor I4);
end XOR5_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xorcy.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  XOR for Carry Logic with General Output
-- /___/   /\     Filename : XORCY.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:01 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL XORCY -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity XORCY is
  port(
    O : out std_ulogic;

    CI : in std_ulogic;
    LI : in std_ulogic
    );
end XORCY;

architecture XORCY_V of XORCY is
begin
    O <= (CI xor LI);
end XORCY_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xorcy_d.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  XOR for Carry Logic with Dual Output
-- /___/   /\     Filename : XORCY_D.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:01 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL XORCY_D -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity XORCY_D is
  port(
    LO : out std_ulogic;
    O  : out std_ulogic;

    CI : in std_ulogic;
    LI : in std_ulogic
    );
end XORCY_D;

architecture XORCY_D_V of XORCY_D is
begin
  O     <= (CI xor LI);
  LO <= (CI xor LI);
end XORCY_D_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xorcy_l.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  XOR for Carry Logic with Local Output
-- /___/   /\     Filename : XORCY_L.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:01 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL XORCY_L -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity XORCY_L is
  port(
    LO : out std_ulogic;

    CI : in std_ulogic;
    LI : in std_ulogic
    );
end XORCY_L;

architecture XORCY_L_V of XORCY_L is
begin
  LO <= (CI xor LI);
end XORCY_L_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/and6.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  6-input AND Gate
-- /___/   /\     Filename : AND6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:14 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND6 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic;
    I5 : in std_ulogic
    );
end AND6;

architecture AND6_V of AND6 is
begin
  O <= I0 and I1 and I2 and I3 and I4 and I5;
end AND6_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/and7.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  7-input AND Gate
-- /___/   /\     Filename : AND7.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:14 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND7 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND7 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic;
    I5 : in std_ulogic;
    I6 : in std_ulogic
    );
end AND7;

architecture AND7_V of AND7 is
begin
  O <= I0 and I1 and I2 and I3 and I4 and I5 and I6;
end AND7_V;



-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/and8.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  8-input AND Gate
-- /___/   /\     Filename : AND8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:14 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL AND8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AND8 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic;
    I5 : in std_ulogic;
    I6 : in std_ulogic;
    I7 : in std_ulogic
    );
end AND8;

architecture AND8_V of AND8 is
begin
  O <= I0 and I1 and I2 and I3 and I4 and I5 and I6 and I7;
end AND8_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/buffoe.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  
-- /___/   /\     Filename : BUFFOE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:15 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL BUFFOE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BUFFOE is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end BUFFOE;

architecture BUFFOE_V of BUFFOE is
begin
  O <= TO_X01(I);
end BUFFOE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/bufgsr.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Set/Reset Input Buffer
-- /___/   /\     Filename : BUFGSR.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:16 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL BUFGSR -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BUFGSR is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end BUFGSR;

architecture BUFGSR_V of BUFGSR is
begin
  O <= TO_X01(I);
end BUFGSR_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/bufgts.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global 3-State Input Buffer
-- /___/   /\     Filename : BUFGTS.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:16 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL BUFGTS -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BUFGTS is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end BUFGTS;

architecture BUFGTS_V of BUFGTS is
begin
  O <= TO_X01(I);
end BUFGTS_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div10.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider
-- /___/   /\     Filename : CLK_DIV10.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:17 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV10 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV10 is
  generic (
    DIVIDE_BY : integer := 10
    );
  port(
    CLKDV : out std_ulogic := '0';
    
    CLKIN : in std_ulogic := '0'
    );

end CLK_DIV10;

architecture CLK_DIV10_V of CLK_DIV10 is

  signal CLKDV_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE : process (CLKIN)
    variable CLOCK_DIVIDER : integer := 0;

  begin
    if (CLKIN'event and CLKIN = '1') then
      CLOCK_DIVIDER := CLOCK_DIVIDER + 1;
      if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
        CLOCK_DIVIDER := 1;
        CLKDV_i <= not CLKDV_i;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV10_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div10r.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Synchronous Reset
-- /___/   /\     Filename : CLK_DIV10R.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:17 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV10R -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV10R is
  generic (
    DIVIDE_BY :     integer := 10
    );
  port(
    CLKDV     : out std_ulogic := '0';

    CDRST : in std_ulogic := '0';
    CLKIN : in std_ulogic := '0'
    );

end CLK_DIV10R;

architecture CLK_DIV10R_V of CLK_DIV10R is

  signal CLKDV_i : std_ulogic := '0';
  signal CDRST_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                 : process (CLKIN, CDRST)
    variable RESET_WAIT_COUNT  : integer := 0;
    variable CLOCK_DIVIDER     : integer := 0;
    variable NO_BITS_REMAINING : integer := 0;
    variable DELAY_RESET       : boolean := false;
    variable STARTUP           : boolean := true;

  begin
    if (CLKIN'event and CLKIN = '0') then
      CDRST_i <= CDRST;
    end if;

    if (CLKIN'event and CLKIN = '1') then

      if (CDRST_i = '1' and CLKDV_i = '0') then
        CLOCK_DIVIDER := 0;
        STARTUP       := true;
      end if;

      if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true then
        CLKDV_i <= '0';
        CLOCK_DIVIDER := 0;
      end if;


      if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false then
        NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER);
        DELAY_RESET       := true;
      end if;

      if (DELAY_RESET = true) then
        RESET_WAIT_COUNT   := RESET_WAIT_COUNT + 1;
        if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then
          CLKDV_i <= '0';
          DELAY_RESET      := false;
          RESET_WAIT_COUNT := 0;
          STARTUP          := true;
          CLOCK_DIVIDER    := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_RESET = false) then
        if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then
          CLKDV_i <= '1';
        end if;

        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          STARTUP       := false;
          CLKDV_i <= not CLKDV_i;
          CLOCK_DIVIDER := 1;
        end if;
      end if;
    end if;

  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV10R_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div10rsd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Synchronous Reset and Start Delay
-- /___/   /\     Filename : CLK_DIV10RSD.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:17 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV10RSD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV10RSD is
  generic (
    DIVIDE_BY     :     integer := 10;
    DIVIDER_DELAY :     integer := 1
    );
  port(
    CLKDV         : out std_ulogic := '0';

    CDRST : in std_ulogic := '0';
    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV10RSD;

architecture CLK_DIV10RSD_V of CLK_DIV10RSD is

  signal CLKDV_i : std_ulogic := '0';
  signal CDRST_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                 : process (CLKIN, CDRST)
    variable CLOCK_DIVIDER     : integer := 0;
    variable RESET_WAIT_COUNT  : integer := 0;
    variable START_WAIT_COUNT  : integer := 0;
    variable DELAY_RESET       : boolean := false;
    variable STARTUP           : boolean := true;
    variable DELAY_START       : integer := DIVIDER_DELAY;
    variable NO_BITS_REMAINING : integer := 0;

  begin
    if (CLKIN'event and CLKIN = '0') then
      CDRST_i <= CDRST;
    end if;

    if (CLKIN'event and CLKIN = '1') then

      if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true) then
        CLKDV_i <= '0';
        CLOCK_DIVIDER := 0;
        DELAY_START   := 1;
      end if;

      if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false) then
        NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER);
        DELAY_RESET       := true;
        DELAY_START       := DIVIDER_DELAY;
      end if;

      if (DELAY_RESET = true) then
        RESET_WAIT_COUNT   := RESET_WAIT_COUNT + 1;
        if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then
          CLKDV_i <= '0';
          DELAY_RESET      := false;
          RESET_WAIT_COUNT := 0;
          STARTUP          := true;
          CLOCK_DIVIDER    := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_START = 1) then
        START_WAIT_COUNT   := START_WAIT_COUNT + 1;
        if (START_WAIT_COUNT = DIVIDE_BY+1) then
          START_WAIT_COUNT := 0;
          DELAY_START      := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_START = 0 and DELAY_RESET = false) then

        if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then
          CLKDV_i <= '1';
        end if;

        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          STARTUP       := false;
          CLOCK_DIVIDER := 1;
          CLKDV_i <= not CLKDV_i;
        end if;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV10RSD_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div10sd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Start Delay
-- /___/   /\     Filename : CLK_DIV10SD.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:17 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV10SD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV10SD is
  generic (
    DIVIDE_BY     : integer := 10;
    DIVIDER_DELAY : integer := 1
    );

  port(
    CLKDV : out std_ulogic := '0';

    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV10SD;

architecture CLK_DIV10SD_V of CLK_DIV10SD is

  signal CLKDV_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                : process (CLKIN)
    variable START_WAIT_COUNT : integer := 0;
    variable CLOCK_DIVIDER    : integer := 0;
    variable DELAY_START      : integer := DIVIDER_DELAY;

  begin
    if (CLKIN'event and CLKIN = '1') then

      if (DELAY_START = 1) then
        START_WAIT_COUNT   := START_WAIT_COUNT + 1;
        if (START_WAIT_COUNT = DIVIDE_BY+1) then
          DELAY_START      := 0;
          START_WAIT_COUNT := 0;
        end if;
      end if;

      if (DELAY_START = 0) then
        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          CLOCK_DIVIDER := 1;
          CLKDV_i <= not CLKDV_i;
        end if;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV10SD_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div12.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider
-- /___/   /\     Filename : CLK_DIV12.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:17 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV12 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV12 is
  generic (
    DIVIDE_BY :     integer := 12
    );
  port(
    CLKDV     : out std_ulogic := '0';

    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV12;

architecture CLK_DIV12_V of CLK_DIV12 is

  signal CLKDV_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE             : process (CLKIN)
    variable CLOCK_DIVIDER : integer := 0;

  begin
    if (CLKIN'event and CLKIN = '1') then
      CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
      if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
        CLOCK_DIVIDER := 1;
        CLKDV_i <= not CLKDV_i;
      end if;
    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV12_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div12r.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Synchronous Reset
-- /___/   /\     Filename : CLK_DIV12R.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:17 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV12R -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV12R is
  generic (
    DIVIDE_BY : integer := 12
    );

  port(
    CLKDV : out std_ulogic := '0';

    CDRST : in std_ulogic := '0';
    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV12R;

architecture CLK_DIV12R_V of CLK_DIV12R is

  signal CLKDV_i : std_ulogic := '0';
  signal CDRST_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                 : process (CLKIN, CDRST)
    variable RESET_WAIT_COUNT  : integer := 0;
    variable CLOCK_DIVIDER     : integer := 0;
    variable NO_BITS_REMAINING : integer := 0;
    variable DELAY_RESET       : boolean := false;
    variable STARTUP           : boolean := true;

  begin
    if (CLKIN'event and CLKIN = '0') then
      CDRST_i <= CDRST;
    end if;

    if (CLKIN'event and CLKIN = '1') then

      if (CDRST_i = '1' and CLKDV_i = '0') then
        CLOCK_DIVIDER := 0;
        STARTUP       := true;
      end if;

      if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true then
        CLKDV_i <= '0';
        CLOCK_DIVIDER := 0;
      end if;


      if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false then
        NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER);
        DELAY_RESET       := true;
      end if;

      if (DELAY_RESET = true) then
        RESET_WAIT_COUNT   := RESET_WAIT_COUNT + 1;
        if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then
          CLKDV_i <= '0';
          DELAY_RESET      := false;
          RESET_WAIT_COUNT := 0;
          STARTUP          := true;
          CLOCK_DIVIDER    := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_RESET = false) then
        if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then
          CLKDV_i <= '1';
        end if;

        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          STARTUP       := false;
          CLKDV_i <= not CLKDV_i;
          CLOCK_DIVIDER := 1;
        end if;
      end if;
    end if;

  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV12R_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div12rsd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Synchronous Reset and Start Delay
-- /___/   /\     Filename : CLK_DIV12RSD.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:18 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV12RSD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV12RSD is
  generic (
    DIVIDE_BY     :     integer := 12;
    DIVIDER_DELAY :     integer := 1
    );
  port(
    CLKDV         : out std_ulogic := '0';
    CDRST         : in  std_ulogic := '0';

    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV12RSD;

architecture CLK_DIV12RSD_V of CLK_DIV12RSD is

  signal CLKDV_i : std_ulogic := '0';
  signal CDRST_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                 : process (CLKIN, CDRST)
    variable CLOCK_DIVIDER     : integer := 0;
    variable RESET_WAIT_COUNT  : integer := 0;
    variable START_WAIT_COUNT  : integer := 0;
    variable DELAY_RESET       : boolean := false;
    variable STARTUP           : boolean := true;
    variable DELAY_START       : integer := DIVIDER_DELAY;
    variable NO_BITS_REMAINING : integer := 0;

  begin
    if (CLKIN'event and CLKIN = '0') then
      CDRST_i <= CDRST;
    end if;

    if (CLKIN'event and CLKIN = '1') then

      if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true) then
        CLKDV_i <= '0';
        CLOCK_DIVIDER := 0;
        DELAY_START   := 1;
      end if;

      if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false) then
        NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER);
        DELAY_RESET       := true;
        DELAY_START       := DIVIDER_DELAY;
      end if;

      if (DELAY_RESET = true) then
        RESET_WAIT_COUNT   := RESET_WAIT_COUNT + 1;
        if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then
          CLKDV_i <= '0';
          DELAY_RESET      := false;
          RESET_WAIT_COUNT := 0;
          STARTUP          := true;
          CLOCK_DIVIDER    := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_START = 1) then
        START_WAIT_COUNT   := START_WAIT_COUNT + 1;
        if (START_WAIT_COUNT = DIVIDE_BY+1) then
          START_WAIT_COUNT := 0;
          DELAY_START      := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_START = 0 and DELAY_RESET = false) then

        if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then
          CLKDV_i <= '1';
        end if;

        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          STARTUP       := false;
          CLOCK_DIVIDER := 1;
          CLKDV_i <= not CLKDV_i;
        end if;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV12RSD_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div12sd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Start Delay
-- /___/   /\     Filename : CLK_DIV12SD.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:18 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV12SD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV12SD is
  generic (
    DIVIDE_BY     :     integer := 12;
    DIVIDER_DELAY :     integer := 1
    );
  port(
    CLKDV         : out std_ulogic := '0';

    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV12SD;

architecture CLK_DIV12SD_V of CLK_DIV12SD is

  signal CLKDV_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                : process (CLKIN)
    variable START_WAIT_COUNT : integer := 0;
    variable CLOCK_DIVIDER    : integer := 0;
    variable DELAY_START      : integer := DIVIDER_DELAY;

  begin
    if (CLKIN'event and CLKIN = '1') then

      if (DELAY_START = 1) then
        START_WAIT_COUNT   := START_WAIT_COUNT + 1;
        if (START_WAIT_COUNT = DIVIDE_BY+1) then
          DELAY_START      := 0;
          START_WAIT_COUNT := 0;
        end if;
      end if;

      if (DELAY_START = 0) then
        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          CLOCK_DIVIDER := 1;
          CLKDV_i <= not CLKDV_i;
        end if;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV12SD_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div14.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider
-- /___/   /\     Filename : CLK_DIV14.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:18 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV14 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV14 is
  generic (
    DIVIDE_BY : integer := 14
    );

  port(
    CLKDV : out std_ulogic := '0';
    CLKIN : in  std_ulogic := '0'
    );
end CLK_DIV14;

architecture CLK_DIV14_V of CLK_DIV14 is

  signal CLKDV_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE             : process (CLKIN)
    variable CLOCK_DIVIDER : integer := 0;

  begin
    if (CLKIN'event and CLKIN = '1') then
      CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
      if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
        CLOCK_DIVIDER := 1;
        CLKDV_i <= not CLKDV_i;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV14_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div14r.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Synchronous Reset
-- /___/   /\     Filename : CLK_DIV14R.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:18 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV14R -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV14R is
  generic (
    DIVIDE_BY :     integer := 14
    );
  port(
    CLKDV     : out std_ulogic := '0';

    CDRST : in std_ulogic := '0';
    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV14R;

architecture CLK_DIV14R_V of CLK_DIV14R is

  signal CLKDV_i : std_ulogic := '0';
  signal CDRST_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                 : process (CLKIN, CDRST)
    variable RESET_WAIT_COUNT  : integer := 0;
    variable CLOCK_DIVIDER     : integer := 0;
    variable NO_BITS_REMAINING : integer := 0;
    variable DELAY_RESET       : boolean := false;
    variable STARTUP           : boolean := true;

  begin
    if (CLKIN'event and CLKIN = '0') then
      CDRST_i <= CDRST;
    end if;

    if (CLKIN'event and CLKIN = '1') then

      if (CDRST_i = '1' and CLKDV_i = '0') then
        CLOCK_DIVIDER := 0;
        STARTUP       := true;
      end if;

      if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true then
        CLKDV_i <= '0';
        CLOCK_DIVIDER := 0;
      end if;


      if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false then
        NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER);
        DELAY_RESET       := true;
      end if;

      if (DELAY_RESET = true) then
        RESET_WAIT_COUNT   := RESET_WAIT_COUNT + 1;
        if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then
          CLKDV_i <= '0';
          DELAY_RESET      := false;
          RESET_WAIT_COUNT := 0;
          STARTUP          := true;
          CLOCK_DIVIDER    := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_RESET = false) then
        if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then
          CLKDV_i <= '1';
        end if;

        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          STARTUP       := false;
          CLKDV_i <= not CLKDV_i;
          CLOCK_DIVIDER := 1;
        end if;
      end if;
    end if;

  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV14R_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div14rsd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Synchronous Reset and Start Delay
-- /___/   /\     Filename : CLK_DIV14RSD.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:18 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV14RSD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV14RSD is
  generic (
    DIVIDE_BY     : integer := 14;
    DIVIDER_DELAY : integer := 1
    );

  port(
    CLKDV : out std_ulogic := '0';

    CDRST : in std_ulogic := '0';
    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV14RSD;

architecture CLK_DIV14RSD_V of CLK_DIV14RSD is

  signal CLKDV_i : std_ulogic := '0';
  signal CDRST_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                 : process (CLKIN, CDRST)
    variable CLOCK_DIVIDER     : integer := 0;
    variable RESET_WAIT_COUNT  : integer := 0;
    variable START_WAIT_COUNT  : integer := 0;
    variable DELAY_RESET       : boolean := false;
    variable STARTUP           : boolean := true;
    variable DELAY_START       : integer := DIVIDER_DELAY;
    variable NO_BITS_REMAINING : integer := 0;

  begin
    if (CLKIN'event and CLKIN = '0') then
      CDRST_i <= CDRST;
    end if;

    if (CLKIN'event and CLKIN = '1') then

      if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true) then
        CLKDV_i <= '0';
        CLOCK_DIVIDER := 0;
        DELAY_START   := 1;
      end if;

      if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false) then
        NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER);
        DELAY_RESET       := true;
        DELAY_START       := DIVIDER_DELAY;
      end if;

      if (DELAY_RESET = true) then
        RESET_WAIT_COUNT   := RESET_WAIT_COUNT + 1;
        if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then
          CLKDV_i <= '0';
          DELAY_RESET      := false;
          RESET_WAIT_COUNT := 0;
          STARTUP          := true;
          CLOCK_DIVIDER    := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_START = 1) then
        START_WAIT_COUNT   := START_WAIT_COUNT + 1;
        if (START_WAIT_COUNT = DIVIDE_BY+1) then
          START_WAIT_COUNT := 0;
          DELAY_START      := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_START = 0 and DELAY_RESET = false) then

        if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then
          CLKDV_i <= '1';
        end if;

        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          STARTUP       := false;
          CLOCK_DIVIDER := 1;
          CLKDV_i <= not CLKDV_i;
        end if;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV14RSD_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div14sd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Start Delay
-- /___/   /\     Filename : CLK_DIV14SD.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:18 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV14SD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV14SD is
  generic (
    DIVIDE_BY     : integer := 14;
    DIVIDER_DELAY : integer := 1
    );

  port(
    CLKDV : out std_ulogic := '0';
    
    CLKIN : in  std_ulogic := '0'
    );
end CLK_DIV14SD;

architecture CLK_DIV14SD_V of CLK_DIV14SD is

  signal CLKDV_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                : process (CLKIN)
    variable START_WAIT_COUNT : integer := 0;
    variable CLOCK_DIVIDER    : integer := 0;
    variable DELAY_START      : integer := DIVIDER_DELAY;

  begin
    if (CLKIN'event and CLKIN = '1') then

      if (DELAY_START = 1) then
        START_WAIT_COUNT   := START_WAIT_COUNT + 1;
        if (START_WAIT_COUNT = DIVIDE_BY+1) then
          DELAY_START      := 0;
          START_WAIT_COUNT := 0;
        end if;
      end if;

      if (DELAY_START = 0) then
        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          CLOCK_DIVIDER := 1;
          CLKDV_i <= not CLKDV_i;
        end if;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV14SD_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div16.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider
-- /___/   /\     Filename : CLK_DIV16.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:18 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV16 is
  generic (
    DIVIDE_BY : integer := 16
    );

  port(
    CLKDV : out std_ulogic := '0';

    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV16;

architecture CLK_DIV16_V of CLK_DIV16 is

  signal CLKDV_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE             : process (CLKIN)
    variable CLOCK_DIVIDER : integer := 0;

  begin
    if (CLKIN'event and CLKIN = '1') then
      CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
      if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
        CLOCK_DIVIDER := 1;
        CLKDV_i <= not CLKDV_i;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV16_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div16r.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Synchronous Reset
-- /___/   /\     Filename : CLK_DIV16R.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:18 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV16R -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV16R is
  generic (
    DIVIDE_BY :     integer := 16
    );
  port(
    CLKDV     : out std_ulogic := '0';

    CDRST : in std_ulogic := '0';
    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV16R;

architecture CLK_DIV16R_V of CLK_DIV16R is

  signal CLKDV_i : std_ulogic := '0';
  signal CDRST_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                 : process (CLKIN, CDRST)
    variable RESET_WAIT_COUNT  : integer := 0;
    variable CLOCK_DIVIDER     : integer := 0;
    variable NO_BITS_REMAINING : integer := 0;
    variable DELAY_RESET       : boolean := false;
    variable STARTUP           : boolean := true;

  begin
    if (CLKIN'event and CLKIN = '0') then
      CDRST_i <= CDRST;
    end if;

    if (CLKIN'event and CLKIN = '1') then

      if (CDRST_i = '1' and CLKDV_i = '0') then
        CLOCK_DIVIDER := 0;
        STARTUP       := true;
      end if;

      if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true then
        CLKDV_i <= '0';
        CLOCK_DIVIDER := 0;
      end if;


      if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false then
        NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER);
        DELAY_RESET       := true;
      end if;

      if (DELAY_RESET = true) then
        RESET_WAIT_COUNT   := RESET_WAIT_COUNT + 1;
        if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then
          CLKDV_i <= '0';
          DELAY_RESET      := false;
          RESET_WAIT_COUNT := 0;
          STARTUP          := true;
          CLOCK_DIVIDER    := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_RESET = false) then
        if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then
          CLKDV_i <= '1';
        end if;

        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          STARTUP       := false;
          CLKDV_i <= not CLKDV_i;
          CLOCK_DIVIDER := 1;
        end if;
      end if;
    end if;

  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV16R_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div16rsd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Synchronous Reset and Start Delay
-- /___/   /\     Filename : CLK_DIV16RSD.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:18 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV16RSD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV16RSD is
  generic (
    DIVIDE_BY     : integer := 16;
    DIVIDER_DELAY : integer := 1
    );

  port(
    CLKDV : out std_ulogic := '0';

    CDRST : in std_ulogic := '0';
    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV16RSD;

architecture CLK_DIV16RSD_V of CLK_DIV16RSD is

  signal CLKDV_i : std_ulogic := '0';
  signal CDRST_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                 : process (CLKIN, CDRST)
    variable CLOCK_DIVIDER     : integer := 0;
    variable RESET_WAIT_COUNT  : integer := 0;
    variable START_WAIT_COUNT  : integer := 0;
    variable DELAY_RESET       : boolean := false;
    variable STARTUP           : boolean := true;
    variable DELAY_START       : integer := DIVIDER_DELAY;
    variable NO_BITS_REMAINING : integer := 0;

  begin
    if (CLKIN'event and CLKIN = '0') then
      CDRST_i <= CDRST;
    end if;

    if (CLKIN'event and CLKIN = '1') then

      if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true) then
        CLKDV_i <= '0';
        CLOCK_DIVIDER := 0;
        DELAY_START   := 1;
      end if;

      if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false) then
        NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER);
        DELAY_RESET       := true;
        DELAY_START       := DIVIDER_DELAY;
      end if;

      if (DELAY_RESET = true) then
        RESET_WAIT_COUNT   := RESET_WAIT_COUNT + 1;
        if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then
          CLKDV_i <= '0';
          DELAY_RESET      := false;
          RESET_WAIT_COUNT := 0;
          STARTUP          := true;
          CLOCK_DIVIDER    := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_START = 1) then
        START_WAIT_COUNT   := START_WAIT_COUNT + 1;
        if (START_WAIT_COUNT = DIVIDE_BY+1) then
          START_WAIT_COUNT := 0;
          DELAY_START      := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_START = 0 and DELAY_RESET = false) then

        if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then
          CLKDV_i <= '1';
        end if;

        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          STARTUP       := false;
          CLOCK_DIVIDER := 1;
          CLKDV_i <= not CLKDV_i;
        end if;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV16RSD_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div16sd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Start Delay
-- /___/   /\     Filename : CLK_DIV16SD.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:19 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV16SD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV16SD is
  generic (
    DIVIDE_BY     :     integer := 16;
    DIVIDER_DELAY :     integer := 1
    );
  port(
    CLKDV         : out std_ulogic := '0';

    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV16SD;

architecture CLK_DIV16SD_V of CLK_DIV16SD is

  signal CLKDV_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                : process (CLKIN)
    variable START_WAIT_COUNT : integer := 0;
    variable CLOCK_DIVIDER    : integer := 0;
    variable DELAY_START      : integer := DIVIDER_DELAY;

  begin
    if (CLKIN'event and CLKIN = '1') then

      if (DELAY_START = 1) then
        START_WAIT_COUNT   := START_WAIT_COUNT + 1;
        if (START_WAIT_COUNT = DIVIDE_BY+1) then
          DELAY_START      := 0;
          START_WAIT_COUNT := 0;
        end if;
      end if;

      if (DELAY_START = 0) then
        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          CLOCK_DIVIDER := 1;
          CLKDV_i <= not CLKDV_i;
        end if;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV16SD_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div2.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider
-- /___/   /\     Filename : CLK_DIV2.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:19 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV2 is
  generic (
    DIVIDE_BY : integer := 2
    );

  port(
    CLKDV : out std_ulogic := '0';

    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV2;

architecture CLK_DIV2_V of CLK_DIV2 is

  signal CLKDV_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE             : process (CLKIN)
    variable CLOCK_DIVIDER : integer := 0;

  begin
    if (CLKIN'event and CLKIN = '1') then
      CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
      if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
        CLOCK_DIVIDER := 1;
        CLKDV_i <= not CLKDV_i;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV2_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div2r.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Synchronous Reset
-- /___/   /\     Filename : CLK_DIV2R.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:19 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV2R -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV2R is
  generic (
    DIVIDE_BY :     integer := 2
    );
  port(
    CLKDV     : out std_ulogic := '0';

    CDRST : in std_ulogic := '0';
    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV2R;

architecture CLK_DIV2R_V of CLK_DIV2R is

  signal CLKDV_i : std_ulogic := '0';
  signal CDRST_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                 : process (CLKIN, CDRST)
    variable RESET_WAIT_COUNT  : integer := 0;
    variable CLOCK_DIVIDER     : integer := 0;
    variable NO_BITS_REMAINING : integer := 0;
    variable DELAY_RESET       : boolean := false;
    variable STARTUP           : boolean := true;

  begin
    if (CLKIN'event and CLKIN = '0') then
      CDRST_i <= CDRST;
    end if;

    if (CLKIN'event and CLKIN = '1') then

      if (CDRST_i = '1' and CLKDV_i = '0') then
        CLOCK_DIVIDER := 0;
        STARTUP       := true;
      end if;

      if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true then
        CLKDV_i <= '0';
        CLOCK_DIVIDER := 0;
      end if;


      if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false then
        NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER);
        DELAY_RESET       := true;
      end if;

      if (DELAY_RESET = true) then
        RESET_WAIT_COUNT   := RESET_WAIT_COUNT + 1;
        if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then
          CLKDV_i <= '0';
          DELAY_RESET      := false;
          RESET_WAIT_COUNT := 0;
          STARTUP          := true;
          CLOCK_DIVIDER    := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_RESET = false) then
        if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then
          CLKDV_i <= '1';
        end if;

        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          STARTUP       := false;
          CLKDV_i <= not CLKDV_i;
          CLOCK_DIVIDER := 1;
        end if;
      end if;
    end if;

  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV2R_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div2rsd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Synchronous Reset and Start Delay
-- /___/   /\     Filename : CLK_DIV2RSD.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:19 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV2RSD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV2RSD is
  generic (
    DIVIDE_BY     : integer := 2;
    DIVIDER_DELAY : integer := 1
    );

  port(
    CLKDV : out std_ulogic := '0';

    CDRST : in std_ulogic := '0';
    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV2RSD;

architecture CLK_DIV2RSD_V of CLK_DIV2RSD is

  signal CLKDV_i : std_ulogic := '0';
  signal CDRST_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                 : process (CLKIN, CDRST)
    variable CLOCK_DIVIDER     : integer := 0;
    variable RESET_WAIT_COUNT  : integer := 0;
    variable START_WAIT_COUNT  : integer := 0;
    variable DELAY_RESET       : boolean := false;
    variable STARTUP           : boolean := true;
    variable DELAY_START       : integer := DIVIDER_DELAY;
    variable NO_BITS_REMAINING : integer := 0;

  begin
    if (CLKIN'event and CLKIN = '0') then
      CDRST_i <= CDRST;
    end if;

    if (CLKIN'event and CLKIN = '1') then

      if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true) then
        CLKDV_i <= '0';
        CLOCK_DIVIDER := 0;
        DELAY_START   := 1;
      end if;

      if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false) then
        NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER);
        DELAY_RESET       := true;
        DELAY_START       := DIVIDER_DELAY;
      end if;

      if (DELAY_RESET = true) then
        RESET_WAIT_COUNT   := RESET_WAIT_COUNT + 1;
        if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then
          CLKDV_i <= '0';
          DELAY_RESET      := false;
          RESET_WAIT_COUNT := 0;
          STARTUP          := true;
          CLOCK_DIVIDER    := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_START = 1) then
        START_WAIT_COUNT   := START_WAIT_COUNT + 1;
        if (START_WAIT_COUNT = DIVIDE_BY+1) then
          START_WAIT_COUNT := 0;
          DELAY_START      := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_START = 0 and DELAY_RESET = false) then

        if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then
          CLKDV_i <= '1';
        end if;

        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          STARTUP       := false;
          CLOCK_DIVIDER := 1;
          CLKDV_i <= not CLKDV_i;
        end if;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV2RSD_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div2sd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Start Delay
-- /___/   /\     Filename : CLK_DIV2SD.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:19 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV2SD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV2SD is
  generic (
    DIVIDE_BY     : integer := 2;
    DIVIDER_DELAY : integer := 1
    );

  port(
    CLKDV : out std_ulogic := '0';

    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV2SD;

architecture CLK_DIV2SD_V of CLK_DIV2SD is

  signal CLKDV_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                : process (CLKIN)
    variable START_WAIT_COUNT : integer := 0;
    variable CLOCK_DIVIDER    : integer := 0;
    variable DELAY_START      : integer := DIVIDER_DELAY;

  begin
    if (CLKIN'event and CLKIN = '1') then

      if (DELAY_START = 1) then
        START_WAIT_COUNT   := START_WAIT_COUNT + 1;
        if (START_WAIT_COUNT = DIVIDE_BY+1) then
          DELAY_START      := 0;
          START_WAIT_COUNT := 0;
        end if;
      end if;

      if (DELAY_START = 0) then
        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          CLOCK_DIVIDER := 1;
          CLKDV_i <= not CLKDV_i;
        end if;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV2SD_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div4.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider
-- /___/   /\     Filename : CLK_DIV4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:19 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV4 is
  generic (
    DIVIDE_BY : integer := 4
    );

  port(
    CLKDV : out std_ulogic := '0';
    
    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV4;

architecture CLK_DIV4_V of CLK_DIV4 is

  signal CLKDV_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE             : process (CLKIN)
    variable CLOCK_DIVIDER : integer := 0;

  begin
    if (CLKIN'event and CLKIN = '1') then
      CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
      if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
        CLOCK_DIVIDER := 1;
        CLKDV_i <= not CLKDV_i;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV4_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div4r.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Synchronous Reset
-- /___/   /\     Filename : CLK_DIV4R.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:19 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV4R -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV4R is
  generic (
    DIVIDE_BY : integer := 4
    );

  port(
    CLKDV : out std_ulogic := '0';

    CDRST : in std_ulogic := '0';
    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV4R;

architecture CLK_DIV4R_V of CLK_DIV4R is

  signal CLKDV_i : std_ulogic := '0';
  signal CDRST_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                 : process (CLKIN, CDRST)
    variable RESET_WAIT_COUNT  : integer := 0;
    variable CLOCK_DIVIDER     : integer := 0;
    variable NO_BITS_REMAINING : integer := 0;
    variable DELAY_RESET       : boolean := false;
    variable STARTUP           : boolean := true;

  begin
    if (CLKIN'event and CLKIN = '0') then
      CDRST_i <= CDRST;
    end if;

    if (CLKIN'event and CLKIN = '1') then

      if (CDRST_i = '1' and CLKDV_i = '0') then
        CLOCK_DIVIDER := 0;
        STARTUP       := true;
      end if;

      if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true then
        CLKDV_i <= '0';
        CLOCK_DIVIDER := 0;
      end if;


      if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false then
        NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER);
        DELAY_RESET       := true;
      end if;

      if (DELAY_RESET = true) then
        RESET_WAIT_COUNT   := RESET_WAIT_COUNT + 1;
        if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then
          CLKDV_i <= '0';
          DELAY_RESET      := false;
          RESET_WAIT_COUNT := 0;
          STARTUP          := true;
          CLOCK_DIVIDER    := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_RESET = false) then
        if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then
          CLKDV_i <= '1';
        end if;

        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          STARTUP       := false;
          CLKDV_i <= not CLKDV_i;
          CLOCK_DIVIDER := 1;
        end if;
      end if;
    end if;

  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV4R_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div4rsd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Synchronous Reset and Start Delay
-- /___/   /\     Filename : CLK_DIV4RSD.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:19 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV4RSD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV4RSD is
  generic (
    DIVIDE_BY     :     integer := 4;
    DIVIDER_DELAY :     integer := 1
    );
  port(
    CLKDV         : out std_ulogic := '0';
    CDRST         : in  std_ulogic := '0';

    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV4RSD;

architecture CLK_DIV4RSD_V of CLK_DIV4RSD is

  signal CLKDV_i : std_ulogic := '0';
  signal CDRST_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                 : process (CLKIN, CDRST)
    variable CLOCK_DIVIDER     : integer := 0;
    variable RESET_WAIT_COUNT  : integer := 0;
    variable START_WAIT_COUNT  : integer := 0;
    variable DELAY_RESET       : boolean := false;
    variable STARTUP           : boolean := true;
    variable DELAY_START       : integer := DIVIDER_DELAY;
    variable NO_BITS_REMAINING : integer := 0;

  begin
    if (CLKIN'event and CLKIN = '0') then
      CDRST_i <= CDRST;
    end if;

    if (CLKIN'event and CLKIN = '1') then

      if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true) then
        CLKDV_i <= '0';
        CLOCK_DIVIDER := 0;
        DELAY_START   := 1;
      end if;

      if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false) then
        NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER);
        DELAY_RESET       := true;
        DELAY_START       := DIVIDER_DELAY;
      end if;

      if (DELAY_RESET = true) then
        RESET_WAIT_COUNT   := RESET_WAIT_COUNT + 1;
        if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then
          CLKDV_i <= '0';
          DELAY_RESET      := false;
          RESET_WAIT_COUNT := 0;
          STARTUP          := true;
          CLOCK_DIVIDER    := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_START = 1) then
        START_WAIT_COUNT   := START_WAIT_COUNT + 1;
        if (START_WAIT_COUNT = DIVIDE_BY+1) then
          START_WAIT_COUNT := 0;
          DELAY_START      := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_START = 0 and DELAY_RESET = false) then

        if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then
          CLKDV_i <= '1';
        end if;

        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          STARTUP       := false;
          CLOCK_DIVIDER := 1;
          CLKDV_i <= not CLKDV_i;
        end if;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV4RSD_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div4sd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Start Delay
-- /___/   /\     Filename : CLK_DIV4SD.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:19 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV4SD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV4SD is
  generic (
    DIVIDE_BY     :     integer := 4;
    DIVIDER_DELAY :     integer := 1
    );
  port(
    CLKDV         : out std_ulogic := '0';

    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV4SD;

architecture CLK_DIV4SD_V of CLK_DIV4SD is

  signal CLKDV_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                : process (CLKIN)
    variable START_WAIT_COUNT : integer := 0;
    variable CLOCK_DIVIDER    : integer := 0;
    variable DELAY_START      : integer := DIVIDER_DELAY;

  begin
    if (CLKIN'event and CLKIN = '1') then

      if (DELAY_START = 1) then
        START_WAIT_COUNT   := START_WAIT_COUNT + 1;
        if (START_WAIT_COUNT = DIVIDE_BY+1) then
          DELAY_START      := 0;
          START_WAIT_COUNT := 0;
        end if;
      end if;

      if (DELAY_START = 0) then
        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          CLOCK_DIVIDER := 1;
          CLKDV_i <= not CLKDV_i;
        end if;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV4SD_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div6.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider
-- /___/   /\     Filename : CLK_DIV6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:20 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV6 is
  generic (
    DIVIDE_BY : integer := 6
    );

  port(
    CLKDV : out std_ulogic := '0';

    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV6;

architecture CLK_DIV6_V of CLK_DIV6 is

  signal CLKDV_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE             : process (CLKIN)
    variable CLOCK_DIVIDER : integer := 0;

  begin
    if (CLKIN'event and CLKIN = '1') then
      CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
      if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
        CLOCK_DIVIDER := 1;
        CLKDV_i <= not CLKDV_i;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV6_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div6r.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Synchronous Reset
-- /___/   /\     Filename : CLK_DIV6R.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:20 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV6R -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV6R is
  generic (
    DIVIDE_BY :     integer := 6
    );
  port(
    CLKDV     : out std_ulogic := '0';

    CDRST : in std_ulogic := '0';
    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV6R;

architecture CLK_DIV6R_V of CLK_DIV6R is

  signal CLKDV_i : std_ulogic := '0';
  signal CDRST_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                 : process (CLKIN, CDRST)
    variable RESET_WAIT_COUNT  : integer := 0;
    variable CLOCK_DIVIDER     : integer := 0;
    variable NO_BITS_REMAINING : integer := 0;
    variable DELAY_RESET       : boolean := false;
    variable STARTUP           : boolean := true;

  begin
    if (CLKIN'event and CLKIN = '0') then
      CDRST_i <= CDRST;
    end if;

    if (CLKIN'event and CLKIN = '1') then

      if (CDRST_i = '1' and CLKDV_i = '0') then
        CLOCK_DIVIDER := 0;
        STARTUP       := true;
      end if;

      if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true then
        CLKDV_i <= '0';
        CLOCK_DIVIDER := 0;
      end if;


      if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false then
        NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER);
        DELAY_RESET       := true;
      end if;

      if (DELAY_RESET = true) then
        RESET_WAIT_COUNT   := RESET_WAIT_COUNT + 1;
        if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then
          CLKDV_i <= '0';
          DELAY_RESET      := false;
          RESET_WAIT_COUNT := 0;
          STARTUP          := true;
          CLOCK_DIVIDER    := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_RESET = false) then
        if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then
          CLKDV_i <= '1';
        end if;

        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          STARTUP       := false;
          CLKDV_i <= not CLKDV_i;
          CLOCK_DIVIDER := 1;
        end if;
      end if;
    end if;

  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV6R_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div6rsd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Synchronous Reset and Start Delay
-- /___/   /\     Filename : CLK_DIV6RSD.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:20 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV6RSD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV6RSD is
  generic (
    DIVIDE_BY     : integer := 6;
    DIVIDER_DELAY : integer := 1
    );

  port(
    CLKDV : out std_ulogic := '0';

    CDRST : in std_ulogic := '0';
    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV6RSD;

architecture CLK_DIV6RSD_V of CLK_DIV6RSD is

  signal CLKDV_i : std_ulogic := '0';
  signal CDRST_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                 : process (CLKIN, CDRST)
    variable CLOCK_DIVIDER     : integer := 0;
    variable RESET_WAIT_COUNT  : integer := 0;
    variable START_WAIT_COUNT  : integer := 0;
    variable DELAY_RESET       : boolean := false;
    variable STARTUP           : boolean := true;
    variable DELAY_START       : integer := DIVIDER_DELAY;
    variable NO_BITS_REMAINING : integer := 0;

  begin
    if (CLKIN'event and CLKIN = '0') then
      CDRST_i <= CDRST;
    end if;

    if (CLKIN'event and CLKIN = '1') then

      if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true) then
        CLKDV_i <= '0';
        CLOCK_DIVIDER := 0;
        DELAY_START   := 1;
      end if;

      if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false) then
        NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER);
        DELAY_RESET       := true;
        DELAY_START       := DIVIDER_DELAY;
      end if;

      if (DELAY_RESET = true) then
        RESET_WAIT_COUNT   := RESET_WAIT_COUNT + 1;
        if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then
          CLKDV_i <= '0';
          DELAY_RESET      := false;
          RESET_WAIT_COUNT := 0;
          STARTUP          := true;
          CLOCK_DIVIDER    := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_START = 1) then
        START_WAIT_COUNT   := START_WAIT_COUNT + 1;
        if (START_WAIT_COUNT = DIVIDE_BY+1) then
          START_WAIT_COUNT := 0;
          DELAY_START      := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_START = 0 and DELAY_RESET = false) then

        if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then
          CLKDV_i <= '1';
        end if;

        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          STARTUP       := false;
          CLOCK_DIVIDER := 1;
          CLKDV_i <= not CLKDV_i;
        end if;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV6RSD_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div6sd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Start Delay
-- /___/   /\     Filename : CLK_DIV6SD.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:20 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV6SD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV6SD is
  generic (
    DIVIDE_BY     : integer := 6;
    DIVIDER_DELAY : integer := 1
    );

  port(
    CLKDV : out std_ulogic := '0';

    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV6SD;

architecture CLK_DIV6SD_V of CLK_DIV6SD is

  signal CLKDV_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                : process (CLKIN)
    variable START_WAIT_COUNT : integer := 0;
    variable CLOCK_DIVIDER    : integer := 0;
    variable DELAY_START      : integer := DIVIDER_DELAY;

  begin
    if (CLKIN'event and CLKIN = '1') then

      if (DELAY_START = 1) then
        START_WAIT_COUNT   := START_WAIT_COUNT + 1;
        if (START_WAIT_COUNT = DIVIDE_BY+1) then
          DELAY_START      := 0;
          START_WAIT_COUNT := 0;
        end if;
      end if;

      if (DELAY_START = 0) then
        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          CLOCK_DIVIDER := 1;
          CLKDV_i <= not CLKDV_i;
        end if;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV6SD_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div8.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider
-- /___/   /\     Filename : CLK_DIV8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:20 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV8 is
  generic (
    DIVIDE_BY : integer := 8
    );

  port(
    CLKDV : out std_ulogic := '0';

    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV8;

architecture CLK_DIV8_V of CLK_DIV8 is

  signal CLKDV_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE             : process (CLKIN)
    variable CLOCK_DIVIDER : integer := 0;

  begin
    if (CLKIN'event and CLKIN = '1') then
      CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
      if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
        CLOCK_DIVIDER := 1;
        CLKDV_i <= not CLKDV_i;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV8_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div8r.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Synchronous Reset
-- /___/   /\     Filename : CLK_DIV8R.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:20 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV8R -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV8R is
  generic (
    DIVIDE_BY : integer := 8
    );

  port(
    CLKDV : out std_ulogic := '0';

    CDRST : in std_ulogic := '0';
    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV8R;

architecture CLK_DIV8R_V of CLK_DIV8R is

  signal CLKDV_i : std_ulogic := '0';
  signal CDRST_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                 : process (CLKIN, CDRST)
    variable RESET_WAIT_COUNT  : integer := 0;
    variable CLOCK_DIVIDER     : integer := 0;
    variable NO_BITS_REMAINING : integer := 0;
    variable DELAY_RESET       : boolean := false;
    variable STARTUP           : boolean := true;

  begin
    if (CLKIN'event and CLKIN = '0') then
      CDRST_i <= CDRST;
    end if;

    if (CLKIN'event and CLKIN = '1') then

      if (CDRST_i = '1' and CLKDV_i = '0') then
        CLOCK_DIVIDER := 0;
        STARTUP       := true;
      end if;

      if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true then
        CLKDV_i <= '0';
        CLOCK_DIVIDER := 0;
      end if;


      if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false then
        NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER);
        DELAY_RESET       := true;
      end if;

      if (DELAY_RESET = true) then
        RESET_WAIT_COUNT   := RESET_WAIT_COUNT + 1;
        if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then
          CLKDV_i <= '0';
          DELAY_RESET      := false;
          RESET_WAIT_COUNT := 0;
          STARTUP          := true;
          CLOCK_DIVIDER    := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_RESET = false) then
        if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then
          CLKDV_i <= '1';
        end if;

        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          STARTUP       := false;
          CLKDV_i <= not CLKDV_i;
          CLOCK_DIVIDER := 1;
        end if;
      end if;
    end if;

  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV8R_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div8rsd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Synchronous Reset and Start Delay
-- /___/   /\     Filename : CLK_DIV8RSD.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:20 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV8RSD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV8RSD is
  generic (
    DIVIDE_BY     : integer := 8;
    DIVIDER_DELAY : integer := 1
    );

  port(
    CLKDV : out std_ulogic := '0';

    CDRST : in std_ulogic := '0';
    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV8RSD;

architecture CLK_DIV8RSD_V of CLK_DIV8RSD is

  signal CLKDV_i : std_ulogic := '0';
  signal CDRST_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                 : process (CLKIN, CDRST)
    variable CLOCK_DIVIDER     : integer := 0;
    variable RESET_WAIT_COUNT  : integer := 0;
    variable START_WAIT_COUNT  : integer := 0;
    variable DELAY_RESET       : boolean := false;
    variable STARTUP           : boolean := true;
    variable DELAY_START       : integer := DIVIDER_DELAY;
    variable NO_BITS_REMAINING : integer := 0;

  begin
    if (CLKIN'event and CLKIN = '0') then
      CDRST_i <= CDRST;
    end if;

    if (CLKIN'event and CLKIN = '1') then

      if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true) then
        CLKDV_i <= '0';
        CLOCK_DIVIDER := 0;
        DELAY_START   := 1;
      end if;

      if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false) then
        NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER);
        DELAY_RESET       := true;
        DELAY_START       := DIVIDER_DELAY;
      end if;

      if (DELAY_RESET = true) then
        RESET_WAIT_COUNT   := RESET_WAIT_COUNT + 1;
        if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then
          CLKDV_i <= '0';
          DELAY_RESET      := false;
          RESET_WAIT_COUNT := 0;
          STARTUP          := true;
          CLOCK_DIVIDER    := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_START = 1) then
        START_WAIT_COUNT   := START_WAIT_COUNT + 1;
        if (START_WAIT_COUNT = DIVIDE_BY+1) then
          START_WAIT_COUNT := 0;
          DELAY_START      := 0;
        end if;
      end if;

      if (CDRST_i = '0' and DELAY_START = 0 and DELAY_RESET = false) then

        if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then
          CLKDV_i <= '1';
        end if;

        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          STARTUP       := false;
          CLOCK_DIVIDER := 1;
          CLKDV_i <= not CLKDV_i;
        end if;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV8RSD_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div8sd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Divider with Start Delay
-- /___/   /\     Filename : CLK_DIV8SD.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:20 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CLK_DIV8SD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK_DIV8SD is
  generic (
    DIVIDE_BY     :     integer := 8;
    DIVIDER_DELAY :     integer := 1
    );
  port(
    CLKDV         : out std_ulogic := '0';

    CLKIN : in std_ulogic := '0'
    );
end CLK_DIV8SD;

architecture CLK_DIV8SD_V of CLK_DIV8SD is

  signal CLKDV_i : std_ulogic := '0';

begin

  CLOCK_DIVIDE                : process (CLKIN)
    variable START_WAIT_COUNT : integer := 0;
    variable CLOCK_DIVIDER    : integer := 0;
    variable DELAY_START      : integer := DIVIDER_DELAY;

  begin
    if (CLKIN'event and CLKIN = '1') then

      if (DELAY_START = 1) then
        START_WAIT_COUNT   := START_WAIT_COUNT + 1;
        if (START_WAIT_COUNT = DIVIDE_BY+1) then
          DELAY_START      := 0;
          START_WAIT_COUNT := 0;
        end if;
      end if;

      if (DELAY_START = 0) then
        CLOCK_DIVIDER   := CLOCK_DIVIDER + 1;
        if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then
          CLOCK_DIVIDER := 1;
          CLKDV_i <= not CLKDV_i;
        end if;
      end if;

    end if;
  end process;

  CLKDV <= CLKDV_i;

end CLK_DIV8SD_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/fdcpx1.vhd,v 1.2 2005/07/23 00:43:54 fphillip Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  D Flip-Flop with Asynchronous Clear and Preset
-- /___/   /\     Filename : FDCPX1.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:22 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    07/23/05 -- Removed INIT to match verilog
-- End Revision

----- CELL FDCPX1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FDCPX1 is
  port(
    Q : out std_ulogic;

    C   : in std_ulogic;
    CLR : in std_ulogic;
    D   : in std_ulogic;
    PRE : in std_ulogic
    );
end FDCPX1;

architecture FDCPX1_V of FDCPX1 is
begin
  VITALBehavior         : process(C, CLR, PRE)
    variable FIRST_TIME : boolean := true ;
  begin

    if (FIRST_TIME = true) then
      Q <= '0';
      FIRST_TIME := false;
    end if;

    if (CLR = '1') then
      Q <= '0';
    elsif (PRE = '1') then
      Q <= '1';
    elsif (rising_edge(C)) then
      Q <= D after 100 ps;
    end if;
  end process;
end FDCPX1_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/fdd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Dual Edge Triggered D Flip-Flop
-- /___/   /\     Filename : FDD.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:22 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity FDD is
   generic(
      TimingChecksOn: Boolean := TRUE;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := False;
      INIT                           :  bit := '0'  ;
      tpd_C_Q : VitalDelayType01 := (0.1 ns, 0.1 ns);
      tsetup_D_C_posedge_posedge : VitalDelayType := 0.000 ns;
      tsetup_D_C_negedge_posedge : VitalDelayType := 0.000 ns;
      thold_D_C_posedge_posedge : VitalDelayType := 0.000 ns;
      thold_D_C_negedge_posedge : VitalDelayType := 0.000 ns;
      tpw_C_posedge : VitalDelayType := 0.000 ns;
      tpw_C_negedge : VitalDelayType := 0.000 ns;
      tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)
      );

   port(
      Q                              :  out   STD_ULOGIC;

      C                              :  in    STD_ULOGIC;
      D                              :  in    STD_ULOGIC      
      );
attribute VITAL_LEVEL0 of FDD : entity is TRUE;
end FDD;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library UNISIM;
use unisim.VPKG.all;
architecture FDD_V of FDD is
   --attribute VITAL_LEVEL1 of FDD_V : architecture is TRUE;

   SIGNAL D_ipd  : STD_ULOGIC := 'X';
   SIGNAL C_ipd  : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (C_ipd, C, tipd_C);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process 

   -- timing check results
   VARIABLE Tviol_D_C_posedge   : STD_ULOGIC := '0';
   VARIABLE Tmkr_D_C_posedge    : VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_C     : STD_ULOGIC := '0';
   VARIABLE PInfo_C     : VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2);
   VARIABLE D_delayed : STD_ULOGIC := 'X';
   VARIABLE C_delayed : STD_ULOGIC := 'X';
   --VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   VARIABLE Q_zd : STD_ULOGIC := TO_X01(INIT);
   VARIABLE FIRST_TIME : boolean := True ;

   -- output glitch detection variables
   VARIABLE Q_GlitchData        : VitalGlitchDataType;

   begin

    if (FIRST_TIME = TRUE) then

       Q <= Q_zd ;

       wait until (rising_edge(c_ipd) );

       C_delayed := C_ipd'last_value;
       D_delayed := D_ipd;


       FIRST_TIME := FALSE;
    end if;

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_C_posedge,
          TimingData              => Tmkr_D_C_posedge,
          TestSignal              => D_ipd,
          TestSignalName          => "D",
          TestDelay               => 0 ns,
          RefSignal               => C_ipd,
          RefSignalName          => "C",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D_C_posedge_posedge,
          SetupLow                => tsetup_D_C_negedge_posedge,
          HoldLow                => thold_D_C_posedge_posedge,
          HoldHigh                 => thold_D_C_negedge_posedge,
          CheckEnabled            => 
                           TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/FDD",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_C,
          PeriodData              => PInfo_C,
          TestSignal              => C_ipd,
          TestSignalName          => "C",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_C_posedge,
          PulseWidthLow           => tpw_C_negedge,
          CheckEnabled            =>  TRUE,
          HeaderMsg               => InstancePath &"/FDD",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_C_posedge or Pviol_C;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => FDD_Q_tab,
        DataIn => (
               C_delayed, D_delayed, C_ipd));
      Q_zd := Violation XOR Q_zd;
      D_delayed := D_ipd;
      C_delayed := C_ipd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (C_ipd'last_event, tpd_C_Q, TRUE)),
       Mode => OnEvent,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

   wait on D_ipd, C_ipd;
end process;

end FDD_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/fddc.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Dual Edge Triggered D Flip-Flop with Asynchronous Clear
-- /___/   /\     Filename : FDDC.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:22 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDDC -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity FDDC is
   generic(
      TimingChecksOn: Boolean := TRUE;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := False;
      INIT                           :  bit := '0'  ;
      tpd_CLR_Q : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_C_Q : VitalDelayType01 := (0.1 ns, 0.1 ns);
      tsetup_D_C_posedge_posedge : VitalDelayType := 0.000 ns;
      tsetup_D_C_negedge_posedge : VitalDelayType := 0.000 ns;
      thold_D_C_posedge_posedge : VitalDelayType := 0.000 ns;
      thold_D_C_negedge_posedge : VitalDelayType := 0.000 ns;
      trecovery_CLR_C_negedge_posedge : VitalDelayType := 0.000 ns;
      thold_CLR_C_negedge_posedge : VitalDelayType := 0.000 ns;
      tpw_C_posedge : VitalDelayType := 0.000 ns;
      tpw_CLR_posedge : VitalDelayType := 0.000 ns;
      tpw_C_negedge : VitalDelayType := 0.000 ns;
      tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)
      );

   port(
      Q                              :  out   STD_ULOGIC;
      
      C                              :  in    STD_ULOGIC;
      CLR                            :  in    STD_ULOGIC;      
      D                              :  in    STD_ULOGIC
      );
attribute VITAL_LEVEL0 of FDDC : entity is TRUE;
end FDDC;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library UNISIM;
use unisim.VPKG.all;
architecture FDDC_V of FDDC is
   --attribute VITAL_LEVEL1 of FDDC_V : architecture is TRUE;

   SIGNAL D_ipd  : STD_ULOGIC := 'X';
   SIGNAL C_ipd  : STD_ULOGIC := 'X';
   SIGNAL CLR_ipd        : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (C_ipd, C, tipd_C);
   VitalWireDelay (CLR_ipd, CLR, tipd_CLR);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process 

   -- timing check results
   VARIABLE Tviol_D_C_posedge   : STD_ULOGIC := '0';
   VARIABLE Tmkr_D_C_posedge    : VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CLR_C_posedge : STD_ULOGIC := '0';
   VARIABLE Tmkr_CLR_C_posedge  : VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_C     : STD_ULOGIC := '0';
   VARIABLE PInfo_C     : VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE Pviol_CLR   : STD_ULOGIC := '0';
   VARIABLE PInfo_CLR   : VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE D_delayed : STD_ULOGIC := 'X';
   VARIABLE C_delayed : STD_ULOGIC := 'X';
   --VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   VARIABLE Q_zd : STD_ULOGIC := TO_X01(INIT);
   VARIABLE FIRST_TIME : boolean := True ;

   -- output glitch detection variables
   VARIABLE Q_GlitchData        : VitalGlitchDataType;

   begin
     
     
      if (FIRST_TIME = TRUE) then

       Q <= Q_zd;

       wait until (CLR_ipd = '1' or rising_edge(c_ipd));

       C_delayed := C_ipd'last_value;
       D_delayed := D_ipd;


       FIRST_TIME := FALSE;
      end if;

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_C_posedge,
          TimingData              => Tmkr_D_C_posedge,
          TestSignal              => D_ipd,
          TestSignalName          => "D",
          TestDelay               => 0 ns,
          RefSignal               => C_ipd,
          RefSignalName          => "C",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D_C_posedge_posedge,
          SetupLow                => tsetup_D_C_negedge_posedge,
          HoldLow                => thold_D_C_posedge_posedge,
          HoldHigh                 => thold_D_C_negedge_posedge,
          CheckEnabled            => 
                           TO_X01((NOT CLR_ipd)) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/FDDC",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_CLR_C_posedge,
          TimingData              => Tmkr_CLR_C_posedge,
          TestSignal              => CLR_ipd,
          TestSignalName          => "CLR",
          TestDelay               => 0 ns,
          RefSignal               => C_ipd,
          RefSignalName          => "C",
          RefDelay                => 0 ns,
          Recovery                => trecovery_CLR_C_negedge_posedge,
          Removal                 => thold_CLR_C_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => 
                           TO_X01(CLR_ipd ) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/FDDC",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_C,
          PeriodData              => PInfo_C,
          TestSignal              => C_ipd,
          TestSignalName          => "C",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_C_posedge,
          PulseWidthLow           => tpw_C_negedge,
          CheckEnabled            =>  TRUE,
          HeaderMsg               => InstancePath &"/FDDC",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLR,
          PeriodData              => PInfo_CLR,
          TestSignal              => CLR_ipd,
          TestSignalName          => "CLR",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLR_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            =>  TRUE,
          HeaderMsg               => InstancePath &"/FDDC",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_C_posedge or Tviol_CLR_C_posedge or Pviol_C or Pviol_CLR;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => FDDC_Q_tab,
        DataIn => (
               C_delayed, D_delayed, C_ipd, CLR_ipd));
      Q_zd := Violation XOR Q_zd;
      D_delayed := D_ipd;
      C_delayed := C_ipd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE),
                 1 => (C_ipd'last_event, tpd_C_Q, TRUE)),
       Mode => OnEvent,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

   wait on D_ipd, C_ipd, CLR_ipd;
end process;

end FDDC_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/fddce.vhd,v 1.2 2005/07/23 00:43:54 fphillip Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Dual Edge Triggered D Flip-Flop with Asynchronous Clear and Clock Enable
-- /___/   /\     Filename : FDDCE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:23 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    07/23/05 -- Removed INIT to match verilog
-- End Revision

----- CELL FDDCE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity FDDCE is
   generic(
      TimingChecksOn: Boolean := TRUE;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := False;
      tpd_CLR_Q : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_C_Q : VitalDelayType01 := (0.1 ns, 0.1 ns);
      tsetup_D_C_posedge_posedge : VitalDelayType := 0.000 ns;
      tsetup_D_C_negedge_posedge : VitalDelayType := 0.000 ns;
      thold_D_C_posedge_posedge : VitalDelayType := 0.000 ns;
      thold_D_C_negedge_posedge : VitalDelayType := 0.000 ns;
      tsetup_CE_C_posedge_posedge : VitalDelayType := 0.000 ns;
      tsetup_CE_C_negedge_posedge : VitalDelayType := 0.000 ns;
      thold_CE_C_posedge_posedge : VitalDelayType := 0.000 ns;
      thold_CE_C_negedge_posedge : VitalDelayType := 0.000 ns;
      trecovery_CLR_C_negedge_posedge : VitalDelayType := 0.000 ns;
      thold_CLR_C_negedge_posedge : VitalDelayType := 0.000 ns;
      tpw_C_posedge : VitalDelayType := 0.000 ns;
      tpw_CLR_posedge : VitalDelayType := 0.000 ns;
      tpw_C_negedge : VitalDelayType := 0.000 ns;
      tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CE : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      Q                              :  out   STD_ULOGIC;
      
      C                              :  in    STD_ULOGIC;
      CE                             :  in    STD_ULOGIC;
      CLR                            :  in    STD_ULOGIC;
      D                              :  in    STD_ULOGIC
      );
attribute VITAL_LEVEL0 of FDDCE : entity is TRUE;
end FDDCE;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library UNISIM;
use unisim.VPKG.all;
architecture FDDCE_V of FDDCE is
   --attribute VITAL_LEVEL1 of FDDCE_V : architecture is TRUE;

   SIGNAL D_ipd  : STD_ULOGIC := 'X';
   SIGNAL C_ipd  : STD_ULOGIC := 'X';
   SIGNAL CE_ipd         : STD_ULOGIC := 'X';
   SIGNAL CLR_ipd        : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (C_ipd, C, tipd_C);
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (CLR_ipd, CLR, tipd_CLR);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process 

   -- timing check results
   VARIABLE Tviol_D_C_posedge   : STD_ULOGIC := '0';
   VARIABLE Tmkr_D_C_posedge    : VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_C_posedge  : STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_C_posedge   : VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CLR_C_posedge : STD_ULOGIC := '0';
   VARIABLE Tmkr_CLR_C_posedge  : VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_C     : STD_ULOGIC := '0';
   VARIABLE PInfo_C     : VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE Pviol_CLR   : STD_ULOGIC := '0';
   VARIABLE PInfo_CLR   : VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5);
   VARIABLE D_delayed : STD_ULOGIC := 'X';
   VARIABLE C_delayed : STD_ULOGIC := 'X';
   VARIABLE CE_delayed : STD_ULOGIC := 'X';
   --VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   --ALIAS Q_zd : STD_LOGIC is Results(1);
--   variable Q_zd : STD_ULOGIC := TO_X01(INIT);
   variable Q_zd : STD_ULOGIC := '0';
   VARIABLE FIRST_TIME : boolean := True ;

   -- output glitch detection variables
   VARIABLE Q_GlitchData        : VitalGlitchDataType;

   begin

      if (FIRST_TIME = TRUE) then

       Q <= '0';

       wait until (CLR_ipd = '1' or rising_edge(c_ipd ));
       CE_delayed := CE_ipd;
       D_delayed := D_ipd;
       C_delayed := C_ipd'last_value;

       FIRST_TIME := FALSE;
      end if;
      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_C_posedge,
          TimingData              => Tmkr_D_C_posedge,
          TestSignal              => D_ipd,
          TestSignalName          => "D",
          TestDelay               => 0 ns,
          RefSignal               => C_ipd,
          RefSignalName          => "C",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D_C_posedge_posedge,
          SetupLow                => tsetup_D_C_negedge_posedge,
          HoldLow                => thold_D_C_posedge_posedge,
          HoldHigh                 => thold_D_C_negedge_posedge,
          CheckEnabled            => 
                           TO_X01(((NOT CLR_ipd)) AND (CE_ipd)) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/FDDCE",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_C_posedge,
          TimingData              => Tmkr_CE_C_posedge,
          TestSignal              => CE_ipd,
          TestSignalName          => "CE",
          TestDelay               => 0 ns,
          RefSignal               => C_ipd,
          RefSignalName          => "C",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE_C_posedge_posedge,
          SetupLow                => tsetup_CE_C_negedge_posedge,
          HoldLow                => thold_CE_C_posedge_posedge,
          HoldHigh                 => thold_CE_C_negedge_posedge,
          CheckEnabled            => 
                           TO_X01(((NOT CLR_ipd)) AND ((Q_zd) XOR (D_ipd)))
                            /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/FDDCE",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_CLR_C_posedge,
          TimingData              => Tmkr_CLR_C_posedge,
          TestSignal              => CLR_ipd,
          TestSignalName          => "CLR",
          TestDelay               => 0 ns,
          RefSignal               => C_ipd,
          RefSignalName          => "C",
          RefDelay                => 0 ns,
          Recovery                => trecovery_CLR_C_negedge_posedge,
          Removal                 => thold_CLR_C_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => 
                           TO_X01(CE_ipd) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/FDDCE",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_C,
          PeriodData              => PInfo_C,
          TestSignal              => C_ipd,
          TestSignalName          => "C",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_C_posedge,
          PulseWidthLow           => tpw_C_negedge,
          CheckEnabled            =>  TRUE,
          HeaderMsg               => InstancePath &"/FDDCE",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLR,
          PeriodData              => PInfo_CLR,
          TestSignal              => CLR_ipd,
          TestSignalName          => "CLR",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLR_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            =>  TRUE,
          HeaderMsg               => InstancePath &"/FDDCE",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_C_posedge or Tviol_CLR_C_posedge or Pviol_C or Tviol_CE_C_posedge or Pviol_CLR;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => FDDCE_Q_tab,
        DataIn => (
               C_delayed, Q_zd, D_delayed, CE_delayed, C_ipd, CLR_ipd));
      Q_zd := Violation XOR Q_zd;
      D_delayed := D_ipd;
      C_delayed := C_ipd;
      CE_delayed := CE_ipd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE),
                 1 => (C_ipd'last_event, tpd_C_Q, TRUE)),
       Mode => OnEvent,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

   wait on D_ipd, C_ipd, CE_ipd, CLR_ipd;
end process;

end FDDCE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/fddcp.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Dual Edge Triggered D Flip-Flop with Asynchronous Clear and Preset
-- /___/   /\     Filename : FDDCP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:23 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDDCP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity FDDCP is
   generic(
      TimingChecksOn: Boolean := TRUE;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := False;
      INIT                           :  bit := '0'  ;
      tpd_CLR_Q : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_PRE_Q : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_C_Q : VitalDelayType01 := (0.1 ns, 0.1 ns);
      tsetup_D_C_posedge_posedge : VitalDelayType := 0.000 ns;
      tsetup_D_C_negedge_posedge : VitalDelayType := 0.000 ns;
      thold_D_C_posedge_posedge : VitalDelayType := 0.000 ns;
      thold_D_C_negedge_posedge : VitalDelayType := 0.000 ns;
      trecovery_CLR_C_negedge_posedge : VitalDelayType := 0.000 ns;
      thold_CLR_C_negedge_posedge : VitalDelayType := 0.000 ns;
      trecovery_PRE_C_negedge_posedge : VitalDelayType := 0.000 ns;
      thold_PRE_C_negedge_posedge : VitalDelayType := 0.000 ns;
      tpw_C_posedge : VitalDelayType := 0.000 ns;
      tpw_CLR_posedge : VitalDelayType := 0.000 ns;
      tpw_PRE_posedge : VitalDelayType := 0.000 ns;
      tpw_C_negedge : VitalDelayType := 0.000 ns;
      tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      Q                              :  out   STD_ULOGIC;
      
      C                              :  in    STD_ULOGIC;
      CLR                            :  in    STD_ULOGIC;
      D                              :  in    STD_ULOGIC;
      PRE                            :  in    STD_ULOGIC
      );
attribute VITAL_LEVEL0 of FDDCP : entity is TRUE;
end FDDCP;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library UNISIM;
use unisim.VPKG.all;
architecture FDDCP_V of FDDCP is
   --attribute VITAL_LEVEL1 of FDDCP_V : architecture is TRUE;

   SIGNAL D_ipd  : STD_ULOGIC := 'X';
   SIGNAL C_ipd  : STD_ULOGIC := 'X';
   SIGNAL CLR_ipd        : STD_ULOGIC := 'X';
   SIGNAL PRE_ipd        : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (C_ipd, C, tipd_C);
   VitalWireDelay (CLR_ipd, CLR, tipd_CLR);
   VitalWireDelay (PRE_ipd, PRE, tipd_PRE);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process 

   -- timing check results
   VARIABLE Tviol_D_C_posedge   : STD_ULOGIC := '0';
   VARIABLE Tmkr_D_C_posedge    : VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CLR_C_posedge : STD_ULOGIC := '0';
   VARIABLE Tmkr_CLR_C_posedge  : VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_PRE_C_posedge : STD_ULOGIC := '0';
   VARIABLE Tmkr_PRE_C_posedge  : VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_C     : STD_ULOGIC := '0';
   VARIABLE PInfo_C     : VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE Pviol_CLR   : STD_ULOGIC := '0';
   VARIABLE PInfo_CLR   : VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE Pviol_PRE   : STD_ULOGIC := '0';
   VARIABLE PInfo_PRE   : VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE D_delayed : STD_ULOGIC := 'X';
   VARIABLE C_delayed : STD_ULOGIC := 'X';
   --VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   --ALIAS Q_zd : STD_LOGIC is Results(1);
   variable Q_zd : STD_ULOGIC := TO_X01(INIT);
   VARIABLE FIRST_TIME : boolean := True ;

   -- output glitch detection variables
   VARIABLE Q_GlitchData        : VitalGlitchDataType;

   begin

      if (FIRST_TIME = TRUE) then

       Q <= Q_zd;

       wait until (CLR_ipd = '1' or PRE_ipd = '1' or rising_edge(c_ipd));
       C_delayed := C_ipd'last_value;
       D_delayed := D_ipd;

       FIRST_TIME := FALSE;
      end if;
      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_C_posedge,
          TimingData              => Tmkr_D_C_posedge,
          TestSignal              => D_ipd,
          TestSignalName          => "D",
          TestDelay               => 0 ns,
          RefSignal               => C_ipd,
          RefSignalName          => "C",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D_C_posedge_posedge,
          SetupLow                => tsetup_D_C_negedge_posedge,
          HoldLow                => thold_D_C_posedge_posedge,
          HoldHigh                 => thold_D_C_negedge_posedge,
          CheckEnabled            => 
                           TO_X01(((NOT PRE_ipd)) AND ((NOT CLR_ipd))) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/FDDCP",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_CLR_C_posedge,
          TimingData              => Tmkr_CLR_C_posedge,
          TestSignal              => CLR_ipd,
          TestSignalName          => "CLR",
          TestDelay               => 0 ns,
          RefSignal               => C_ipd,
          RefSignalName          => "C",
          RefDelay                => 0 ns,
          Recovery                => trecovery_CLR_C_negedge_posedge,
          Removal                 => thold_CLR_C_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => 
                           TO_X01((NOT PRE_ipd)) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/FDDCP",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_PRE_C_posedge,
          TimingData              => Tmkr_PRE_C_posedge,
          TestSignal              => PRE_ipd,
          TestSignalName          => "PRE",
          TestDelay               => 0 ns,
          RefSignal               => C_ipd,
          RefSignalName          => "C",
          RefDelay                => 0 ns,
          Recovery                => trecovery_PRE_C_negedge_posedge,
          Removal                 => thold_PRE_C_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => 
                           TO_X01((NOT CLR_ipd)) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/FDDCP",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_C,
          PeriodData              => PInfo_C,
          TestSignal              => C_ipd,
          TestSignalName          => "C",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_C_posedge,
          PulseWidthLow           => tpw_C_negedge,
          CheckEnabled            =>  TRUE,
          HeaderMsg               => InstancePath &"/FDDCP",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLR,
          PeriodData              => PInfo_CLR,
          TestSignal              => CLR_ipd,
          TestSignalName          => "CLR",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLR_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            =>  TRUE,
          HeaderMsg               => InstancePath &"/FDDCP",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_PRE,
          PeriodData              => PInfo_PRE,
          TestSignal              => PRE_ipd,
          TestSignalName          => "PRE",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_PRE_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            =>  TRUE,
          HeaderMsg               => InstancePath &"/FDDCP",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_C_posedge or Tviol_CLR_C_posedge or Tviol_PRE_C_posedge or Pviol_PRE or Pviol_C or Pviol_CLR;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => FDDCP_Q_tab,
        DataIn => (
               C_delayed, D_delayed, PRE_ipd, C_ipd, CLR_ipd));
      Q_zd := Violation XOR Q_zd;
      D_delayed := D_ipd;
      C_delayed := C_ipd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE),
                 1 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE),
                 2 => (C_ipd'last_event, tpd_C_Q, TRUE)),
       Mode => OnEvent,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

   wait on D_ipd, C_ipd, CLR_ipd, PRE_ipd;
end process;

end FDDCP_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/fddcpe.vhd,v 1.2 2005/07/23 00:43:54 fphillip Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Dual Edge Triggered D Flip-Flop with Asynchronous Clear and Preset and Clock Enable
-- /___/   /\     Filename : FDDCPE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:23 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    07/23/05 -- Removed INIT to match verilog
-- End Revision

----- CELL FDDCPE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity FDDCPE is
   generic(
      TimingChecksOn: Boolean := TRUE;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := False;
      tpd_PRE_Q : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CLR_Q : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_C_Q : VitalDelayType01 := (0.1 ns, 0.1 ns);
      tsetup_D_C_posedge_posedge : VitalDelayType := 0.000 ns;
      tsetup_D_C_negedge_posedge : VitalDelayType := 0.000 ns;
      thold_D_C_posedge_posedge : VitalDelayType := 0.000 ns;
      thold_D_C_negedge_posedge : VitalDelayType := 0.000 ns;
      tsetup_CE_C_posedge_posedge : VitalDelayType := 0.000 ns;
      tsetup_CE_C_negedge_posedge : VitalDelayType := 0.000 ns;
      thold_CE_C_posedge_posedge : VitalDelayType := 0.000 ns;
      thold_CE_C_negedge_posedge : VitalDelayType := 0.000 ns;
      trecovery_CLR_C_negedge_posedge : VitalDelayType := 0.000 ns;
      thold_CLR_C_negedge_posedge : VitalDelayType := 0.000 ns;
      trecovery_PRE_C_negedge_posedge : VitalDelayType := 0.000 ns;
      thold_PRE_C_negedge_posedge : VitalDelayType := 0.000 ns;
      tpw_C_posedge : VitalDelayType := 0.000 ns;
      tpw_CLR_posedge : VitalDelayType := 0.000 ns;
      tpw_PRE_posedge : VitalDelayType := 0.000 ns;
      tpw_C_negedge : VitalDelayType := 0.000 ns;
      tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CE : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      Q                              :  out   STD_ULOGIC;
      
      C                              :  in    STD_ULOGIC;
      CE                             :  in    STD_ULOGIC;
      CLR                            :  in    STD_ULOGIC;
      D                              :  in    STD_ULOGIC;
      PRE                            :  in    STD_ULOGIC
      );
attribute VITAL_LEVEL0 of FDDCPE : entity is TRUE;
end FDDCPE;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library UNISIM;
use unisim.VPKG.all;
architecture FDDCPE_V of FDDCPE is
   --attribute VITAL_LEVEL1 of FDDCPE_V : architecture is TRUE;

   SIGNAL D_ipd  : STD_ULOGIC := 'X';
   SIGNAL C_ipd  : STD_ULOGIC := 'X';
   SIGNAL CE_ipd         : STD_ULOGIC := 'X';
   SIGNAL CLR_ipd        : STD_ULOGIC := 'X';
   SIGNAL PRE_ipd        : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (C_ipd, C, tipd_C);
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (CLR_ipd, CLR, tipd_CLR);
   VitalWireDelay (PRE_ipd, PRE, tipd_PRE);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process 

   -- timing check results
   VARIABLE Tviol_D_C_posedge   : STD_ULOGIC := '0';
   VARIABLE Tmkr_D_C_posedge    : VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_C_posedge  : STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_C_posedge   : VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CLR_C_posedge : STD_ULOGIC := '0';
   VARIABLE Tmkr_CLR_C_posedge  : VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_PRE_C_posedge : STD_ULOGIC := '0';
   VARIABLE Tmkr_PRE_C_posedge  : VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_C     : STD_ULOGIC := '0';
   VARIABLE PInfo_C     : VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE Pviol_CLR   : STD_ULOGIC := '0';
   VARIABLE PInfo_CLR   : VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE Pviol_PRE   : STD_ULOGIC := '0';
   VARIABLE PInfo_PRE   : VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 6);
   VARIABLE D_delayed : STD_ULOGIC := 'X';
   VARIABLE C_delayed : STD_ULOGIC := 'X';
   VARIABLE CE_delayed : STD_ULOGIC := 'X';
   --VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   --ALIAS Q_zd : STD_LOGIC is Results(1);
   -- variable Q_zd : STD_ULOGIC := TO_X01(INIT);
   variable Q_zd : STD_ULOGIC := '0';
   VARIABLE FIRST_TIME : boolean := True ;

   -- output glitch detection variables
   VARIABLE Q_GlitchData        : VitalGlitchDataType;

   begin

      if (FIRST_TIME = TRUE) then

       Q <= '0';

       wait until (CLR_ipd = '1' or PRE_ipd = '1' or rising_edge(c_ipd ));

       CE_delayed := CE_ipd;
       C_delayed := C_ipd'last_value;
       D_delayed := D_ipd;

       FIRST_TIME := FALSE;
      end if;
      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_C_posedge,
          TimingData              => Tmkr_D_C_posedge,
          TestSignal              => D_ipd,
          TestSignalName          => "D",
          TestDelay               => 0 ns,
          RefSignal               => C_ipd,
          RefSignalName          => "C",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D_C_posedge_posedge,
          SetupLow                => tsetup_D_C_negedge_posedge,
          HoldLow                => thold_D_C_posedge_posedge,
          HoldHigh                 => thold_D_C_negedge_posedge,
          CheckEnabled            => 
                           TO_X01(((NOT CLR_ipd)) AND (CE_ipd) AND ((NOT
                            PRE_ipd))) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/FDDCPE",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_C_posedge,
          TimingData              => Tmkr_CE_C_posedge,
          TestSignal              => CE_ipd,
          TestSignalName          => "CE",
          TestDelay               => 0 ns,
          RefSignal               => C_ipd,
          RefSignalName          => "C",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE_C_posedge_posedge,
          SetupLow                => tsetup_CE_C_negedge_posedge,
          HoldLow                => thold_CE_C_posedge_posedge,
          HoldHigh                 => thold_CE_C_negedge_posedge,
          CheckEnabled            => 
                           TO_X01(((NOT CLR_ipd)) AND ((Q_zd) XOR (D_ipd))
                            AND ((NOT PRE_ipd))) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/FDDCPE",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_CLR_C_posedge,
          TimingData              => Tmkr_CLR_C_posedge,
          TestSignal              => CLR_ipd,
          TestSignalName          => "CLR",
          TestDelay               => 0 ns,
          RefSignal               => C_ipd,
          RefSignalName          => "C",
          RefDelay                => 0 ns,
          Recovery                => trecovery_CLR_C_negedge_posedge,
          Removal                 => thold_CLR_C_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => 
                           TO_X01(((NOT PRE_ipd)) AND (CE_ipd)) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/FDDCPE",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_PRE_C_posedge,
          TimingData              => Tmkr_PRE_C_posedge,
          TestSignal              => PRE_ipd,
          TestSignalName          => "PRE",
          TestDelay               => 0 ns,
          RefSignal               => C_ipd,
          RefSignalName          => "C",
          RefDelay                => 0 ns,
          Recovery                => trecovery_PRE_C_negedge_posedge,
          Removal                 => thold_PRE_C_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => 
                           TO_X01(((NOT CLR_ipd)) AND (CE_ipd)) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/FDDCPE",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_C,
          PeriodData              => PInfo_C,
          TestSignal              => C_ipd,
          TestSignalName          => "C",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_C_posedge,
          PulseWidthLow           => tpw_C_negedge,
          CheckEnabled            =>  TRUE,
          HeaderMsg               => InstancePath &"/FDDCPE",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLR,
          PeriodData              => PInfo_CLR,
          TestSignal              => CLR_ipd,
          TestSignalName          => "CLR",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLR_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            =>  TRUE,
          HeaderMsg               => InstancePath &"/FDDCPE",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_PRE,
          PeriodData              => PInfo_PRE,
          TestSignal              => PRE_ipd,
          TestSignalName          => "PRE",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_PRE_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            =>  TRUE,
          HeaderMsg               => InstancePath &"/FDDCPE",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_C_posedge or Tviol_CLR_C_posedge or Tviol_PRE_C_posedge or Pviol_PRE or Pviol_C or Tviol_CE_C_posedge or Pviol_CLR;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => FDDCPE_Q_tab,
        DataIn => (
               C_delayed, PRE_ipd, Q_zd, D_delayed, CE_delayed, C_ipd, CLR_ipd));
      Q_zd := Violation XOR Q_zd;
      D_delayed := D_ipd;
      C_delayed := C_ipd;
      CE_delayed := CE_ipd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE),
                 1 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE),
                 2 => (C_ipd'last_event, tpd_C_Q, TRUE)),
       Mode => OnEvent,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

   wait on D_ipd, C_ipd, CE_ipd, CLR_ipd, PRE_ipd;
end process;

end FDDCPE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/fddp.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Dual Edge Triggered D Flip-Flop with Asynchronous Preset
-- /___/   /\     Filename : FDDP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:23 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FDDP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity FDDP is
   generic(
      TimingChecksOn: Boolean := TRUE;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := False;
      INIT                           :  bit := '1'  ;
      tpd_PRE_Q : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_C_Q : VitalDelayType01 := (0.1 ns, 0.1 ns);
      tsetup_D_C_posedge_posedge : VitalDelayType := 0.000 ns;
      tsetup_D_C_negedge_posedge : VitalDelayType := 0.000 ns;
      thold_D_C_posedge_posedge : VitalDelayType := 0.000 ns;
      thold_D_C_negedge_posedge : VitalDelayType := 0.000 ns;
      trecovery_PRE_C_negedge_posedge : VitalDelayType := 0.000 ns;
      thold_PRE_C_negedge_posedge : VitalDelayType := 0.000 ns;
      tpw_C_posedge : VitalDelayType := 0.000 ns;
      tpw_PRE_posedge : VitalDelayType := 0.000 ns;
      tpw_C_negedge : VitalDelayType := 0.000 ns;
      tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      Q                              :  out   STD_ULOGIC;
      
      C                              :  in    STD_ULOGIC;
      D                              :  in    STD_ULOGIC;
      PRE                            :  in    STD_ULOGIC
      );
attribute VITAL_LEVEL0 of FDDP : entity is TRUE;
end FDDP;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library UNISIM;
use unisim.VPKG.all;
architecture FDDP_V of FDDP is
   --attribute VITAL_LEVEL1 of FDDP_V : architecture is TRUE;

   SIGNAL D_ipd  : STD_ULOGIC := 'X';
   SIGNAL C_ipd  : STD_ULOGIC := 'X';
   SIGNAL PRE_ipd        : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (C_ipd, C, tipd_C);
   VitalWireDelay (PRE_ipd, PRE, tipd_PRE);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process 

   -- timing check results
   VARIABLE Tviol_D_C_posedge   : STD_ULOGIC := '0';
   VARIABLE Tmkr_D_C_posedge    : VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_PRE_C_posedge : STD_ULOGIC := '0';
   VARIABLE Tmkr_PRE_C_posedge  : VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_C     : STD_ULOGIC := '0';
   VARIABLE PInfo_C     : VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE Pviol_PRE   : STD_ULOGIC := '0';
   VARIABLE PInfo_PRE   : VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE D_delayed : STD_ULOGIC := 'X';
   VARIABLE C_delayed : STD_ULOGIC := 'X';
   --VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   --ALIAS Q_zd : STD_LOGIC is Results(1);
   variable Q_zd : STD_ULOGIC := TO_X01(INIT);
   VARIABLE FIRST_TIME : boolean := True ;

   -- output glitch detection variables
   VARIABLE Q_GlitchData        : VitalGlitchDataType;

   begin

     if (FIRST_TIME = TRUE) then

       Q <= Q_zd;

       wait until (PRE_ipd = '1' or rising_edge(c_ipd ));

       C_delayed := C_ipd'last_value;
       D_delayed := D_ipd;

       FIRST_TIME := FALSE;
      end if;

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_C_posedge,
          TimingData              => Tmkr_D_C_posedge,
          TestSignal              => D_ipd,
          TestSignalName          => "D",
          TestDelay               => 0 ns,
          RefSignal               => C_ipd,
          RefSignalName          => "C",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D_C_posedge_posedge,
          SetupLow                => tsetup_D_C_negedge_posedge,
          HoldLow                => thold_D_C_posedge_posedge,
          HoldHigh                 => thold_D_C_negedge_posedge,
          CheckEnabled            => 
                           TO_X01((NOT PRE_ipd)) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/FDDP",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_PRE_C_posedge,
          TimingData              => Tmkr_PRE_C_posedge,
          TestSignal              => PRE_ipd,
          TestSignalName          => "PRE",
          TestDelay               => 0 ns,
          RefSignal               => C_ipd,
          RefSignalName          => "C",
          RefDelay                => 0 ns,
          Recovery                => trecovery_PRE_C_negedge_posedge,
          Removal                 => thold_PRE_C_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => 
                           TO_X01(PRE_ipd ) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/FDDP",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_C,
          PeriodData              => PInfo_C,
          TestSignal              => C_ipd,
          TestSignalName          => "C",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_C_posedge,
          PulseWidthLow           => tpw_C_negedge,
          CheckEnabled            =>  TRUE,
          HeaderMsg               => InstancePath &"/FDDP",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_PRE,
          PeriodData              => PInfo_PRE,
          TestSignal              => PRE_ipd,
          TestSignalName          => "PRE",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_PRE_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            =>  TRUE,
          HeaderMsg               => InstancePath &"/FDDP",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_C_posedge or Tviol_PRE_C_posedge or Pviol_PRE or Pviol_C;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => FDDP_Q_tab,
        DataIn => (
               C_delayed, D_delayed, PRE_ipd, C_ipd));
      Q_zd := Violation XOR Q_zd;
      D_delayed := D_ipd;
      C_delayed := C_ipd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE),
                 1 => (C_ipd'last_event, tpd_C_Q, TRUE)),
       Mode => OnEvent,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

   wait on D_ipd, C_ipd, PRE_ipd;
end process;

end FDDP_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/fddpe.vhd,v 1.2 2005/07/23 00:43:54 fphillip Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Dual Edge Triggered D Flip-Flop with Asynchronous Preset and Clock Enable
-- /___/   /\     Filename : FDDPE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:23 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    07/23/05 -- Removed INIT to match verilog
-- End Revision

----- CELL FDDPE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity FDDPE is
   generic(
      TimingChecksOn: Boolean := TRUE;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := False;
      tpd_PRE_Q : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_C_Q : VitalDelayType01 := (0.1 ns, 0.1 ns);
      tsetup_D_C_posedge_posedge : VitalDelayType := 0.000 ns;
      tsetup_D_C_negedge_posedge : VitalDelayType := 0.000 ns;
      thold_D_C_posedge_posedge : VitalDelayType := 0.000 ns;
      thold_D_C_negedge_posedge : VitalDelayType := 0.000 ns;
      tsetup_CE_C_posedge_posedge : VitalDelayType := 0.000 ns;
      tsetup_CE_C_negedge_posedge : VitalDelayType := 0.000 ns;
      thold_CE_C_posedge_posedge : VitalDelayType := 0.000 ns;
      thold_CE_C_negedge_posedge : VitalDelayType := 0.000 ns;
      trecovery_PRE_C_negedge_posedge : VitalDelayType := 0.000 ns;
      thold_PRE_C_negedge_posedge : VitalDelayType := 0.000 ns;
      tpw_C_posedge : VitalDelayType := 0.000 ns;
      tpw_PRE_posedge : VitalDelayType := 0.000 ns;
      tpw_C_negedge : VitalDelayType := 0.000 ns;
      tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CE : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      Q                              :  out   STD_ULOGIC;
      
      C                              :  in    STD_ULOGIC;
      CE                             :  in    STD_ULOGIC;
      D                              :  in    STD_ULOGIC;
      PRE                            :  in    STD_ULOGIC
      );
attribute VITAL_LEVEL0 of FDDPE : entity is TRUE;
end FDDPE;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library UNISIM;
use unisim.VPKG.all;
architecture FDDPE_V of FDDPE is
   --attribute VITAL_LEVEL1 of FDDPE_V : architecture is TRUE;

   SIGNAL D_ipd  : STD_ULOGIC := 'X';
   SIGNAL C_ipd  : STD_ULOGIC := 'X';
   SIGNAL CE_ipd         : STD_ULOGIC := 'X';
   SIGNAL PRE_ipd        : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (C_ipd, C, tipd_C);
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (PRE_ipd, PRE, tipd_PRE);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process 

   -- timing check results
   VARIABLE Tviol_D_C_posedge   : STD_ULOGIC := '0';
   VARIABLE Tmkr_D_C_posedge    : VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_C_posedge  : STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_C_posedge   : VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_PRE_C_posedge : STD_ULOGIC := '0';
   VARIABLE Tmkr_PRE_C_posedge  : VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_C     : STD_ULOGIC := '0';
   VARIABLE PInfo_C     : VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE Pviol_PRE   : STD_ULOGIC := '0';
   VARIABLE PInfo_PRE   : VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5);
   VARIABLE D_delayed : STD_ULOGIC := 'X';
   VARIABLE C_delayed : STD_ULOGIC := 'X';
   VARIABLE CE_delayed : STD_ULOGIC := 'X';
   --VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   --ALIAS Q_zd : STD_LOGIC is Results(1);
   -- variable Q_zd : STD_ULOGIC := TO_X01(INIT);
   variable Q_zd : STD_ULOGIC := '0';
   VARIABLE FIRST_TIME : boolean := True ;

   -- output glitch detection variables
   VARIABLE Q_GlitchData        : VitalGlitchDataType;

   begin

      if (FIRST_TIME = TRUE) then

       Q <= '1';

       wait until (PRE_ipd = '1' or rising_edge(c_ipd ));

       CE_delayed := CE_ipd;
       C_delayed := C_ipd'last_value;
       D_delayed := D_ipd;


       FIRST_TIME := FALSE;
      end if;
      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_C_posedge,
          TimingData              => Tmkr_D_C_posedge,
          TestSignal              => D_ipd,
          TestSignalName          => "D",
          TestDelay               => 0 ns,
          RefSignal               => C_ipd,
          RefSignalName          => "C",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D_C_posedge_posedge,
          SetupLow                => tsetup_D_C_negedge_posedge,
          HoldLow                => thold_D_C_posedge_posedge,
          HoldHigh                 => thold_D_C_negedge_posedge,
          CheckEnabled            => 
                           TO_X01(((NOT PRE_ipd)) AND (CE_ipd)) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/FDDPE",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_C_posedge,
          TimingData              => Tmkr_CE_C_posedge,
          TestSignal              => CE_ipd,
          TestSignalName          => "CE",
          TestDelay               => 0 ns,
          RefSignal               => C_ipd,
          RefSignalName          => "C",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE_C_posedge_posedge,
          SetupLow                => tsetup_CE_C_negedge_posedge,
          HoldLow                => thold_CE_C_posedge_posedge,
          HoldHigh                 => thold_CE_C_negedge_posedge,
          CheckEnabled            => 
                           TO_X01(((NOT PRE_ipd)) AND ((Q_zd) XOR (D_ipd)))
                            /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/FDDPE",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_PRE_C_posedge,
          TimingData              => Tmkr_PRE_C_posedge,
          TestSignal              => PRE_ipd,
          TestSignalName          => "PRE",
          TestDelay               => 0 ns,
          RefSignal               => C_ipd,
          RefSignalName          => "C",
          RefDelay                => 0 ns,
          Recovery                => trecovery_PRE_C_negedge_posedge,
          Removal                 => thold_PRE_C_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => 
                           TO_X01(CE_ipd) /= '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/FDDPE",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_C,
          PeriodData              => PInfo_C,
          TestSignal              => C_ipd,
          TestSignalName          => "C",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_C_posedge,
          PulseWidthLow           => tpw_C_negedge,
          CheckEnabled            =>  TRUE,
          HeaderMsg               => InstancePath &"/FDDPE",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_PRE,
          PeriodData              => PInfo_PRE,
          TestSignal              => PRE_ipd,
          TestSignalName          => "PRE",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_PRE_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            =>  TRUE,
          HeaderMsg               => InstancePath &"/FDDPE",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_C_posedge or Tviol_PRE_C_posedge or Pviol_PRE or Pviol_C or Tviol_CE_C_posedge;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => FDDPE_Q_tab,
        DataIn => (
               C_delayed, PRE_ipd, Q_zd, D_delayed, CE_delayed, C_ipd));
      Q_zd := Violation XOR Q_zd;
      D_delayed := D_ipd;
      C_delayed := C_ipd;
      CE_delayed := CE_ipd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE),
                 1 => (C_ipd'last_event, tpd_C_Q, TRUE)),
       Mode => OnEvent,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

   wait on D_ipd, C_ipd, CE_ipd, PRE_ipd;
end process;

end FDDPE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/ftc.vhd,v 1.2 2005/07/23 00:43:54 fphillip Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Toggle Flip-Flop with Toggle Enable and Asynchronous Clear
-- /___/   /\     Filename : FTC.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:26 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    07/23/05 -- Removed INIT to match verilog
-- End Revision

----- CELL FTC -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FTC is
  port(
    Q : out std_ulogic;

    C   : in std_ulogic;
    CLR : in std_ulogic;
    T   : in std_ulogic
    );
end FTC;

architecture FTC_V of FTC is
begin
  VITALBehavior         : process(C, CLR)
    variable FIRST_TIME : boolean := true ;
    variable Q_zd : std_ulogic := '0';
  begin

    if (FIRST_TIME = true) then
      Q <= '0';
      FIRST_TIME := false;
    end if;

    if (CLR = '1') then
      Q   <= '0';
    elsif (rising_edge(C)) then
      if (T = '1') then
        Q_zd := not Q_zd;
        Q <= Q_zd after 100 ps;        
      end if;

    end if;
  end process;
end FTC_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/ftcp.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Toggle Flip-Flop with Toggle Enable and Asynchronous Clear and Preset
-- /___/   /\     Filename : FTCP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:26 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FTCP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FTCP is
  generic(
    INIT : bit := '0'
    );

  port(
    Q : out std_ulogic;

    C   : in std_ulogic;
    CLR : in std_ulogic;
    PRE : in std_ulogic;
    T   : in std_ulogic
    );
end FTCP;

architecture FTCP_V of FTCP is
begin
  VITALBehavior         : process(C, CLR, PRE)
    variable FIRST_TIME : boolean := true ;
    variable Q_zd : std_ulogic := TO_X01(INIT);    
  begin

    if (FIRST_TIME = true) then
      Q <= TO_X01(INIT);
      FIRST_TIME := false;
    end if;

    if (CLR = '1') then
      Q   <= '0';
      Q_zd   := '0';
    elsif (PRE = '1') then
      Q   <= '1';
      Q_zd   := '1';
    elsif (C'event and C = '1') then
      if (T = '1') then
        Q_zd := not Q_zd;
        Q <= Q_zd  after 100 ps;
      end if;
    end if;
  end process;
end FTCP_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/ftp.vhd,v 1.2 2005/07/23 00:43:54 fphillip Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Toggle Flip-Flop with Toggle Enable and Asynchronous Preset
-- /___/   /\     Filename : FTP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:26 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    07/23/05 -- Removed INIT to match verilog
-- End Revision

----- CELL FTP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FTP is
  port(
    Q : out std_ulogic;

    C   : in std_ulogic;
    PRE : in std_ulogic;
    T   : in std_ulogic
    );
end FTP;

architecture FTP_V of FTP is
begin
  VITALBehavior         : process(C, PRE)
    variable FIRST_TIME : boolean := true ;
    variable Q_zd : std_ulogic := '1';
  begin

    if (FIRST_TIME = true) then
      Q <= '1';
      FIRST_TIME := false;
    end if;

    if (PRE = '1') then
      Q   <= '1';
    elsif (C'event and C = '1') then
      if (T = '1') then
        Q_zd := not Q_zd;
        Q <= Q_zd after 100 ps;
      end if;
    end if;
  end process;
end FTP_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/ild.vhd,v 1.2 2005/07/25 16:07:35 fphillip Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Tranparent Input Data Latch
-- /___/   /\     Filename : ILD.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:42 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    07/25/04 - Removed INIT to match the verilog model.

----- CELL ILD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity ILD is
  port(
    Q : out std_ulogic;

    D : in std_ulogic;
    G : in std_ulogic
    );
end ILD;

architecture ILD_V of ILD is
begin
  VITALBehavior   : process(D, G)
    variable Q_zd : std_ulogic := '0';
  begin
    if (G = '1') then
      Q <= D after 100 ps;
    end if;
  end process;
end ILD_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/iobufe.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer
-- /___/   /\     Filename : IOBUFE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:59 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUFE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUFE is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    E : in std_ulogic;
    I : in std_ulogic
    );
end IOBUFE;

architecture IOBUFE_V of IOBUFE is
begin
  VPKGBehavior     : process (IO, I, E)
    variable IO_zd : std_ulogic;
  begin
    O  <= IO;
    if ((E = '0') or (E = 'L')) then
      IO <= 'Z';
    elsif ((E = '1') or (E = 'H')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (E = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;    
  end process;
end IOBUFE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/iobufe_f.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer
-- /___/   /\     Filename : IOBUFE_F.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:59 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUFE_F -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUFE_F is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    E : in std_ulogic;
    I : in std_ulogic
    );
end IOBUFE_F;

architecture IOBUFE_F_V of IOBUFE_F is
begin
  VPKGBehavior     : process (IO, I, E)
    variable IO_zd : std_ulogic;
  begin
    O     <= IO;
    if ((E = '1') or (E = 'H')) then
      IO <= 'Z';
    elsif ((E = '0') or (E = 'L')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (E = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;    
  end process;
end IOBUFE_F_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/iobufe_s.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Bi-Directional Buffer
-- /___/   /\     Filename : IOBUFE_S.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:59 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IOBUFE_S -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity IOBUFE_S is
  port(
    O : out std_ulogic;

    IO : inout std_ulogic;

    E : in std_ulogic;
    I : in std_ulogic
    );
end IOBUFE_S;

architecture IOBUFE_S_V of IOBUFE_S is
begin
  VPKGBehavior     : process (IO, I, E)
    variable IO_zd : std_ulogic;
  begin
    O  <= IO;
    if ((E = '0') or (E = 'L')) then
      IO <= 'Z';
    elsif ((E = '1') or (E = 'H')) then
      if ((I = '1') or (I = 'H')) then
        IO <= '1';
      elsif ((I = '0') or (I = 'L')) then
        IO <= '0';
      elsif (I = 'U') then
        IO <= 'U';
      else
        IO <= 'X';  
      end if;
    elsif (E = 'U') then
      IO <= 'U';          
    else                                      
      IO <= 'X';  
    end if;        
  end process;
end IOBUFE_S_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/keep.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  
-- /___/   /\     Filename : KEEP.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:55:59 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL KEEP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity KEEP is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );
end KEEP;

architecture KEEP_V of KEEP is
begin
  VITALBehavior : process (I)
  begin
    O <= TO_X01(I);
  end process;
end KEEP_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/ldg.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Transparent Datagate Latch
-- /___/   /\     Filename : LDG.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:00 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL LDG -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity LDG is
   generic(
      TimingChecksOn: Boolean := TRUE;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := False;
      INIT                           :  bit := '0'  ;
      tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
      tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
      tsetup_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
      tsetup_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
      thold_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
      thold_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
      tpw_G_posedge : VitalDelayType := 0.000 ns;
      tpw_G_negedge : VitalDelayType := 0.000 ns;
      tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)
      );

   port(
      Q                              :	out   STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      G                              :	in    STD_ULOGIC
      );
attribute VITAL_LEVEL0 of LDG : entity is TRUE;
end LDG;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library UNISIM;
use UNISIM.VPKG.all;
architecture LDG_V of LDG is
   --attribute VITAL_LEVEL1 of LDG_V : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL G_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (G_ipd, G, tipd_G);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process 

   -- timing check results
   VARIABLE Tviol_D_G_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_G_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_G	: STD_ULOGIC := '0';
   VARIABLE PInfo_G	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 1);
   --VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   VARIABLE Q_zd : STD_ULOGIC := TO_X01(INIT);
   VARIABLE FIRST_TIME : boolean := True ;
   --ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

   if (FIRST_TIME = TRUE) then

       Q <= Q_zd ;

       wait until (G_ipd = '0' or G_ipd = '1');
                  

       FIRST_TIME := FALSE;
    end if;


      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_G_negedge,
          TimingData              => Tmkr_D_G_negedge,
          TestSignal              => D_ipd,
          TestSignalName          => "D",
          TestDelay               => 0 ns,
          RefSignal               => G_ipd,
          RefSignalName           => "G",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D_G_posedge_negedge,
          SetupLow                => tsetup_D_G_negedge_negedge,
          HoldHigh                => thold_D_G_posedge_negedge,
          HoldLow                 => thold_D_G_negedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/LD",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_G,
          PeriodData              => PInfo_G,
          TestSignal              => G_ipd,
          TestSignalName          => "G",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_G_posedge,
          PulseWidthLow           => tpw_G_negedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/LD",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_G_negedge or Pviol_G;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => ILDI_1_Q_tab,
        DataIn => (
               G_ipd, D_ipd));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE),
                 1 => (G_ipd'last_event, tpd_G_Q, TRUE)),
       Mode => OnEvent,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

wait on D_ipd, G_ipd;
end process;

end LDG_V;



-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/merge.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  
-- /___/   /\     Filename : MERGE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:02 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL MERGE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MERGE is
  port(
    I : in std_ulogic
    );
end MERGE;

architecture MERGE_V of MERGE is
begin
end MERGE_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/min_off.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  
-- /___/   /\     Filename : MIN_OFF.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:02 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL MIN_OFF -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MIN_OFF is
  port(
    I : in std_ulogic
    );
end MIN_OFF;

architecture MIN_OFF_V of MIN_OFF is
begin
end MIN_OFF_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/obufe.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  3-State Output Buffer
-- /___/   /\     Filename : OBUFE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:26 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OBUFE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OBUFE is
  port(
    O : out std_ulogic;
    I : in  std_ulogic;
    E : in  std_ulogic
    );
end OBUFE;

architecture OBUFE_V of OBUFE is
begin

  VITALBehavior   : process (I, E)
  begin
      if (((not E) = '1') or ((not E) = 'H')) then
        O <= 'Z';
      elsif (((not E) = '0') or ((not E) = 'L')) then
        if ((I = '1') or (I = 'H')) then
          O <= '1';
        elsif ((I = '0') or (I = 'L')) then
          O <= '0';
        elsif (I = 'U') then
          O <= 'U';
        else
          O <= 'X';  
        end if;
      elsif ((not E) = 'U') then
        O <= 'U';          
      else                                      
        O <= 'X';  
      end if;    
  end process;
end OBUFE_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/opt_off.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  
-- /___/   /\     Filename : OPT_OFF.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:44 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OPT_OFF -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OPT_OFF is
  port(
    I : in std_ulogic
    );
end OPT_OFF;

architecture OPT_OFF_V of OPT_OFF is
begin
end OPT_OFF_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/opt_uim.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  
-- /___/   /\     Filename : OPT_UIM.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:44 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OPT_UIM -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OPT_UIM is
  port(
    I : in std_ulogic
    );
end OPT_UIM;

architecture OPT_UIM_V of OPT_UIM is
begin
end OPT_UIM_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/or6.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  6-input OR Gate
-- /___/   /\     Filename : OR6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:46 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR6 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic;
    I5 : in std_ulogic
    );
end OR6;

architecture OR6_V of OR6 is
begin
  O <= (I0 or I1 or I2 or I3 or I4 or I5);
end OR6_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/or7.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  7-input OR Gate
-- /___/   /\     Filename : OR7.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:46 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR7 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR7 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic;
    I5 : in std_ulogic;
    I6 : in std_ulogic
    );
end OR7;

architecture OR7_V of OR7 is
begin
  O <= (I0 or I1 or I2 or I3 or I4 or I5 or I6);
end OR7_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/or8.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  8-input OR Gate
-- /___/   /\     Filename : OR8.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:47 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL OR8 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OR8 is
  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic;
    I5 : in std_ulogic;
    I6 : in std_ulogic;
    I7 : in std_ulogic
    );
end OR8;

architecture OR8_V of OR8 is
begin
  O <= (I0 or I1 or I2 or I3 or I4 or I5 or I6 or I7);
end OR8_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/wireand.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  
-- /___/   /\     Filename : WIREAND.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:00 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL WIREAND -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity WIREAND is
  port(
    I : in std_ulogic
    );
end WIREAND;
architecture WIREAND_V of WIREAND is
begin
end WIREAND_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/bscan_virtex4.vhd,v 1.6 2005/03/10 22:45:35 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Boundary Scan Logic Control Circuit for VIRTEX4
-- /___/   /\     Filename : BSCAN_VIRTEX4.v
-- \   \  /  \    Timestamp : Fri Mar 26 08:17:58 PST 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL BSCAN_VIRTEX4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.vcomponents.all;
entity BSCAN_VIRTEX4 is
  generic(
        JTAG_CHAIN : integer := 1
        );

  port(
    CAPTURE : out std_ulogic := 'H';
    DRCK    : out std_ulogic := 'H';
    RESET   : out std_ulogic := 'H';
    SEL     : out std_ulogic := 'L';
    SHIFT   : out std_ulogic := 'L';
    TDI     : out std_ulogic := 'L';
    UPDATE  : out std_ulogic := 'L';

    TDO     : in std_ulogic := 'X'
    );

end BSCAN_VIRTEX4;

architecture BSCAN_VIRTEX4_V of BSCAN_VIRTEX4 is

signal SEL_zd : std_ulogic := '0';
signal UPDATE_zd : std_ulogic := '0';

begin

--####################################################################
--#####                        Initialization                      ###
--####################################################################
  prcs_init:process
  begin
     if((JTAG_CHAIN /= 1) and (JTAG_CHAIN /= 2)  and (JTAG_CHAIN /= 3)
                                           and (JTAG_CHAIN /= 4)) then
        assert false
        report "Attribute Syntax Error: The allowed values for JTAG_CHAIN are 1, 2, 3 or 4"
        severity Failure;
     end if;
     wait;
  end process prcs_init;

-- synopsys translate_off

--####################################################################
--#####                        jtag_select                         ###
--####################################################################
  prcs_jtag_select:process (JTAG_SEL1_GLBL, JTAG_SEL2_GLBL, JTAG_SEL3_GLBL, JTAG_SEL4_GLBL)
  begin
      if(JTAG_CHAIN = 1) then
        SEL_zd <= JTAG_SEL1_GLBL;
      elsif(JTAG_CHAIN = 2) then
        SEL_zd <= JTAG_SEL2_GLBL;
      elsif(JTAG_CHAIN = 3) then
        SEL_zd <= JTAG_SEL3_GLBL;
      elsif(JTAG_CHAIN = 4) then
        SEL_zd <= JTAG_SEL4_GLBL;
     end if;

  end process prcs_jtag_select;

--####################################################################
--#####                        USER_TDO                            ###
--####################################################################
  prcs_jtag_UserTDO:process (TDO)
  begin
      if(JTAG_CHAIN = 1) then
        JTAG_USER_TDO1_GLBL <= TDO;
      elsif(JTAG_CHAIN = 2) then
        JTAG_USER_TDO2_GLBL <= TDO;
      elsif(JTAG_CHAIN = 3) then
        JTAG_USER_TDO3_GLBL <= TDO;
      elsif(JTAG_CHAIN = 4) then
        JTAG_USER_TDO4_GLBL <= TDO;
     end if;

  end process prcs_jtag_UserTDO;
--####################################################################

  CAPTURE <= JTAG_CAPTURE_GLBL;
  DRCK  <= ((SEL_zd and not JTAG_SHIFT_GLBL and not JTAG_CAPTURE_GLBL) or
            (SEL_zd and JTAG_SHIFT_GLBL and JTAG_TCK_GLBL) or
            (SEL_zd and JTAG_CAPTURE_GLBL and JTAG_TCK_GLBL));
  TDI     <= JTAG_TDI_GLBL;
  SEL     <= SEL_zd;
  SHIFT   <= JTAG_SHIFT_GLBL;
  UPDATE  <= JTAG_UPDATE_GLBL;
  RESET   <= JTAG_RESET_GLBL;

-- synopsys translate_on

end BSCAN_VIRTEX4_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Mux Buffer
-- /___/   /\     Filename : BUFGCTRL.vhd
-- \   \  /  \    Timestamp : Fri Mar 26 08:18:19 PST 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    11/28/05 - CR 221551 fix.
--    08/13/07 - CR 413180 Initialization mismatch fix for unisims.
--    04/07/08 - CR 469973 -- Header Description fix
--    05/22/08 - Add init_done to pass initial values (CR 473625).
-- End Revision

----- CELL BUFGCTRL -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;


library unisim;
use unisim.vpkg.all;
use unisim.vcomponents.all;

entity BUFGCTRL is

  generic(


      INIT_OUT     : integer := 0;
      PRESELECT_I0 : boolean := false;
      PRESELECT_I1 : boolean := false
    );

  port(
    O		: out std_ulogic;

    CE0		: in  std_ulogic;
    CE1		: in  std_ulogic;
    I0	        : in  std_ulogic;
    I1        	: in  std_ulogic;
    IGNORE0	: in  std_ulogic;
    IGNORE1	: in  std_ulogic;
    S0		: in  std_ulogic;
    S1		: in  std_ulogic
    );

end BUFGCTRL;

architecture BUFGCTRL_V OF BUFGCTRL is


  constant SYNC_PATH_DELAY : time := 100 ps;

  signal CE0_dly        : std_ulogic := 'X';
  signal CE1_dly        : std_ulogic := 'X';
  signal I0_dly         : std_ulogic := 'X';
  signal I1_dly         : std_ulogic := 'X';
  signal IGNORE0_dly    : std_ulogic := 'X';
  signal IGNORE1_dly    : std_ulogic := 'X';
  signal GSR_I0_dly     : std_ulogic := 'X';
  signal GSR_I1_dly     : std_ulogic := 'X';
  signal S0_dly         : std_ulogic := 'X';
  signal S1_dly         : std_ulogic := 'X';

  signal O_zd		: std_ulogic := 'X';

  signal q0             : std_ulogic := 'X';
  signal q1             : std_ulogic := 'X';
  signal q0_enable      : std_ulogic := 'X';
  signal q1_enable      : std_ulogic := 'X';

  signal preslct_i0     : std_ulogic := 'X';
  signal preslct_i1     : std_ulogic := 'X';

  signal i0_int         : std_ulogic := 'X';
  signal i1_int         : std_ulogic := 'X';
  signal init_done      : boolean := false;
begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  CE0_dly        	 <= CE0            	after 0 ps;
  CE1_dly        	 <= CE1            	after 0 ps;
  I0_dly         	 <= I0             	after 0 ps;
  I1_dly         	 <= I1             	after 0 ps;
  GSR_I0_dly		 <= GSR            	after 0 ps;
  GSR_I1_dly		 <= GSR            	after 0 ps;
  IGNORE0_dly    	 <= IGNORE0        	after 0 ps;
  IGNORE1_dly    	 <= IGNORE1        	after 0 ps;
  S0_dly         	 <= S0             	after 0 ps;
  S1_dly         	 <= S1             	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process
  variable FIRST_TIME : boolean := true;
  variable preslct_i0_var : std_ulogic;
  variable preslct_i1_var : std_ulogic;

  begin
    if(FIRST_TIME) then

      -- check for PRESELECT_I0
      case PRESELECT_I0  is
        when true  => preslct_i0_var := '1';
        when false => preslct_i0_var := '0';
        when others =>
         assert false report
           "*** Attribute Syntax Error: Legal values for PRESELECT_I0 are TRUE or FALSE"
          severity failure;
      end case;

      -- check for PRESELECT_I1
      case PRESELECT_I1  is
        when true  => preslct_i1_var := '1';
        when false => preslct_i1_var := '0';
        when others =>
         assert false report
           "*** Attribute Syntax Error: Legal values for PRESELECT_I0 are TRUE or FALSE"
          severity failure;
      end case;

      -- both preslcts can not be 1 simultaneously 
      if((preslct_i0_var = '1') and (preslct_i1_var = '1')) then
         assert false report
           "*** Attribute Syntax Error: The attributes PRESELECT_I0 and PRESELECT_I1 should not be set to TRUE simultaneously"
          severity failure;
      end if;
        
      -- check for INIT_OUT
      if((INIT_OUT /= 0) and (INIT_OUT /= 1)) then
         assert false report
           "*** Attribute Syntax Error: Legal values for INIT_OUT are 0 or 1 "
          severity failure;
      end if;

      preslct_i0 <= preslct_i0_var;
      preslct_i1 <= preslct_i1_var;
      FIRST_TIME := false;
      init_done <= true;

    end if;
    wait;

  end process prcs_init;


----- *** Start
     
  prcs_clk:process(i0_dly, i1_dly)
  begin
     if(INIT_OUT = 1) then
        i0_int <= NOT i0_dly; 
     else
        i0_int <= i0_dly; 
     end if;

     if(INIT_OUT = 1) then
        i1_int <= NOT i1_dly; 
     else
        i1_int <= i1_dly; 
     end if;
  end process prcs_clk;
--####################################################################
--#####                            I1                          #####
--####################################################################
----- *** Input enable for i1
  prcs_en_i1:process(IGNORE1_dly, i1_int, S1_dly, GSR_I1_dly, q0, init_done)
  variable FIRST_TIME        : boolean    := TRUE;
  begin
      if (((FIRST_TIME) and (init_done)) or (GSR_I1_dly = '1')) then
         q1_enable <= preslct_i1;
         FIRST_TIME := false;
      elsif (GSR_I1_dly = '0') then
         if ((i1_int  = '0') and (IGNORE1_dly = '0')) then 
             q1_enable <= q1_enable;
         elsif((i1_int = '1') or (IGNORE1_dly = '1')) then
             q1_enable <= ((NOT q0) AND (S1_dly));
          end if;
             
      end if;
  end process prcs_en_i1;
    
----- *** Output q1
  prcs_out_i1:process(q1_enable, CE1_dly, i1_int, IGNORE1_dly, GSR_I1_dly, init_done)
  variable FIRST_TIME        : boolean    := TRUE;
  begin
      if (((FIRST_TIME) and (init_done))or (GSR_I1_dly = '1')) then
         q1 <= preslct_i1;
         FIRST_TIME := false;
      elsif (GSR_I1_dly = '0') then
         if ((i1_int  = '1') and (IGNORE1_dly = '0')) then 
             q1 <= q1;
         elsif((i1_int = '0') or (IGNORE1_dly = '1')) then
             if ((CE0_dly='1' and q0_enable='1') and (CE1_dly='1' and q1_enable='1')) then
                q1 <=  'X';
             else
                q1 <=  CE1_dly AND q1_enable;
             end if;
         end if;
      end if;
  end process prcs_out_i1;

--####################################################################
--#####                            I0                          #####
--####################################################################
----- *** Input enable for i0
  prcs_en_i0:process(IGNORE0_dly, i0_int, S0_dly, GSR_I0_dly, q1, init_done)
  variable FIRST_TIME        : boolean    := TRUE;
  begin
      if (((FIRST_TIME) and (init_done)) or (GSR_I0_dly = '1')) then
         q0_enable <= preslct_i0;
         FIRST_TIME := false;
      elsif (GSR_I0_dly = '0') then
         if ((i0_int  = '0') and (IGNORE0_dly = '0')) then 
             q0_enable <= q0_enable;
         elsif((i0_int = '1') or (IGNORE0_dly = '1')) then
             q0_enable <= ((NOT q1) AND (S0_dly));
          end if;
             
      end if;
  end process prcs_en_i0;
    
----- *** Output q0
  prcs_out_i0:process(q0_enable, CE0_dly, i0_int, IGNORE0_dly, GSR_I0_dly, init_done)
  variable FIRST_TIME        : boolean    := TRUE;
  begin
      if (((FIRST_TIME) and (init_done)) or (GSR_I0_dly = '1')) then
         q0 <= preslct_i0;
         FIRST_TIME := false;
      elsif (GSR_I0_dly = '0') then
         if ((i0_int  = '1') and (IGNORE0_dly = '0')) then 
             q0 <= q0;
         elsif((i0_int = '0') or (IGNORE0_dly = '1')) then
             if ((CE0_dly='1' and q0_enable='1') and (CE1_dly='1' and q1_enable='1')) then
                q0 <=  'X';
             else
                q0 <=  CE0_dly AND q0_enable;
             end if;
         end if;
      end if;
  end process prcs_out_i0;

--####################################################################
--#####                          OUTPUT                          #####
--####################################################################
  prcs_selectout:process(q0, q1, i0_int, i1_int)
  variable tmp_buf : std_logic_vector(1 downto 0);
  begin
    tmp_buf := q1&q0;
    case tmp_buf is
      when "01" => O_zd <= I0_dly;
      when "10" => O_zd <= I1_dly;
      when "00" => 
            if(INIT_OUT = 1) then
              O_zd <= '1';
            elsif(INIT_OUT = 0) then
              O_zd <= '0';
            end if;
      when "XX" => 
              O_zd <= 'X';
      when others =>
    end case;
  end process prcs_selectout;
--####################################################################

-- CR 413180 enabling global GSR 
--####################################################################
--#####                         GSR                              #####
--####################################################################
--  prcs_gsr:process
--  variable FIRST_TIME : boolean := true;
--  begin
---- CR fix for 192413
--    if(FIRST_TIME) then
--      GSR <= '1',
---- undo CR fix for 192413
----             '0' after 100 ns;
--             '0' after 1 ns;
--      FIRST_TIME := false;
--    end if;
--    wait;
--  end process prcs_gsr;

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(O_zd)
  begin
-- CR fix for 221551
--      O <= O_zd after SYNC_PATH_DELAY;
      O <= O_zd;
  end process prcs_output;
--####################################################################

end BUFGCTRL_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/bufgmux_virtex4.vhd,v 1.5 2004/04/08 23:09:36 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Mux Buffer
-- /___/   /\     Filename : BUFGMUX_VIRTEX4.vhd
-- \   \  /  \    Timestamp : Fri Mar 26 08:17:58 PST 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL BUFGMUX_VIRTEX4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;

library unisim;
use unisim.vpkg.all;
use unisim.vcomponents.all;

entity BUFGMUX_VIRTEX4 is

  port(
      O			: out std_ulogic;

      I0		: in std_ulogic;
      I1		: in std_ulogic;
      S			: in std_ulogic
    );

end BUFGMUX_VIRTEX4;


architecture BUFGMUX_VIRTEX4_V OF BUFGMUX_VIRTEX4 is


  signal SigPullUp		: std_ulogic := '1';
  signal SigPullDown		: std_ulogic := '0';
  signal NOT_S			: std_ulogic := 'X';

begin

  NOT_S <= NOT S;

----------------------------------------------------------------------
-----------    Instant BUFGCTRL  -------------------------------------
----------------------------------------------------------------------
  INST_BUFGCTRL : BUFGCTRL
  generic map (
      INIT_OUT => 0,
      PRESELECT_I0 => true,
      PRESELECT_I1 => false
     )
  port map (
      O		=> O,

      CE0	=> SigPullUp,
      CE1	=> SigPullUp,
      I0	=> I0,
      I1	=> I1,
      IGNORE0	=> SigPullDown,
      IGNORE1	=> SigPullDown,
      S0	=> NOT_S,
      S1	=> S
      );
end BUFGMUX_VIRTEX4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/bufio.vhd,v 1.5 2004/04/08 23:09:36 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Local Clock Buffer for I/O
-- /___/   /\     Filename : BUFIO.v
-- \   \  /  \    Timestamp : Fri Mar 26 08:17:58 PST 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL BUFIO -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BUFIO is
  port(
    O : out std_ulogic;

    I : in std_ulogic
    );

end BUFIO;

architecture BUFIO_V of BUFIO is
begin
  O <= I after 0 ps;
end BUFIO_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                  Regional Clock Buffer
-- /___/   /\     Filename : BUFR.vhd
-- \   \  /  \    Timestamp : Fri Mar 26 08:18:19 PST 2004
--  \___\/\___\
-- Revision:
--    03/23/04 - Initial version.
--    04/04/2005 - Add SIM_DEVICE paramter to support rainier. CE pin has 4 clock
--                 latency for Virtex 4 and none for Rainier
--    06/30/2005 - CR # 211199 -- removed sync path delay. Made delayed start only
--                 depend on CE (not CLR)
--    07/25/05 - Updated names to Virtex5
--    08/31/05 - Add ce_en to sensitivity list of i_in which make ce asynch.
--    05/23/06 - Add clk_count =0 and first_time=true when CE = 0 (CR 232206).
--    08/09/06 - Initial output (CR217760).
-- End Revision


----- CELL BUFR -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;


library unisim;
use unisim.vpkg.all;

entity BUFR is

  generic(

      BUFR_DIVIDE   : string := "BYPASS";
      SIM_DEVICE    : string := "VIRTEX4"
      );

  port(
      O           : out std_ulogic;

      CE          : in  std_ulogic;
      CLR         : in  std_ulogic;
      I           : in  std_ulogic
      );

end BUFR;

architecture BUFR_V OF BUFR is


--    06/30/2005 - CR # 211199 -- 
--  constant SYNC_PATH_DELAY : time := 100 ps;

  signal CE_ipd	        : std_ulogic := 'X';
  signal GSR            : std_ulogic := '0';
  signal GSR_ipd	: std_ulogic := '0';
  signal I_ipd	        : std_ulogic := 'X';
  signal CLR_ipd	: std_ulogic := 'X';

  signal CE_dly       	: std_ulogic := 'X';
  signal GSR_dly	: std_ulogic := '0';
  signal I_dly       	: std_ulogic := 'X';
  signal CLR_dly	: std_ulogic := 'X';

  signal O_zd	        : std_ulogic := '0';
  signal O_viol	        : std_ulogic := '0';

  signal q4_sig	        : std_ulogic := 'X';
  signal ce_en	        : std_ulogic;

  signal divide   	: boolean    := false;
  signal divide_by	: integer    := -1;
  signal FIRST_TOGGLE_COUNT     : integer    := -1;
  signal SECOND_TOGGLE_COUNT    : integer    := -1;

begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  CE_dly         	 <= CE             	after 0 ps;
  CLR_dly        	 <= CLR            	after 0 ps;
  GSR_dly        	 <= GSR            	after 0 ps;
  I_dly          	 <= I              	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process
  variable FIRST_TOGGLE_COUNT_var  : integer    := -1;
  variable SECOND_TOGGLE_COUNT_var : integer    := -1;
  variable ODD                     : integer    := -1;
  variable divide_var  	   : boolean    := false;
  variable divide_by_var           :  integer    := -1;

  begin
      if(BUFR_DIVIDE = "BYPASS") then
         divide_var := false;
      elsif(BUFR_DIVIDE = "1") then
         divide_var    := true;
         divide_by_var := 1;
         FIRST_TOGGLE_COUNT_var  := 1;
         SECOND_TOGGLE_COUNT_var := 1;
      elsif(BUFR_DIVIDE = "2") then
         divide_var    := true;
         divide_by_var := 2;
         FIRST_TOGGLE_COUNT_var  := 2;
         SECOND_TOGGLE_COUNT_var := 2;
      elsif(BUFR_DIVIDE = "3") then
         divide_var    := true;
         divide_by_var := 3;
         FIRST_TOGGLE_COUNT_var  := 2;
         SECOND_TOGGLE_COUNT_var := 4;
      elsif(BUFR_DIVIDE = "4") then
         divide_var    := true;
         divide_by_var := 4;
         FIRST_TOGGLE_COUNT_var  := 4;
         SECOND_TOGGLE_COUNT_var := 4;
      elsif(BUFR_DIVIDE = "5") then
         divide_var    := true;
         divide_by_var := 5;
         FIRST_TOGGLE_COUNT_var  := 4;
         SECOND_TOGGLE_COUNT_var := 6;
      elsif(BUFR_DIVIDE = "6") then
         divide_var    := true;
         divide_by_var := 6;
         FIRST_TOGGLE_COUNT_var  := 6;
         SECOND_TOGGLE_COUNT_var := 6;
      elsif(BUFR_DIVIDE = "7") then
         divide_var    := true;
         divide_by_var := 7;
         FIRST_TOGGLE_COUNT_var  := 6;
         SECOND_TOGGLE_COUNT_var := 8;
      elsif(BUFR_DIVIDE = "8") then
         divide_var    := true;
         divide_by_var := 8;
         FIRST_TOGGLE_COUNT_var  := 8;
         SECOND_TOGGLE_COUNT_var := 8;
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " BUFR_DIVIDE ",
             EntityName => "/BUFR",
             GenericValue => BUFR_DIVIDE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " BYPASS, 1, 2, 3, 4, 5, 6, 7 or 8 ",
             TailMsg => "",
             MsgSeverity => ERROR 
         );
      end if;

     if (SIM_DEVICE /= "VIRTEX4" and SIM_DEVICE /= "VIRTEX5") then
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " SIM_DEVICE ",
             EntityName => "/BUFR",
             GenericValue => SIM_DEVICE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " VIRTEX4 or VIRTEX5 ",
             TailMsg => "",
             MsgSeverity => ERROR
         );
      end if;

      FIRST_TOGGLE_COUNT  <= FIRST_TOGGLE_COUNT_var; 
      SECOND_TOGGLE_COUNT <= SECOND_TOGGLE_COUNT_var; 

      divide    <= divide_var;
      divide_by <= divide_by_var;

     wait;
  end process prcs_init;
--####################################################################
--#####                      CLOCK_ENABLE                        #####
--####################################################################
   prcs_ce:process(I_Dly, GSR_dly)
   variable fall_i_count : integer    := 0;
   variable q4_var       : std_ulogic := '0';
   variable q3_var       : std_ulogic := '0';
   variable q2_var       : std_ulogic := '0';
   variable q1_var       : std_ulogic := '0';
   begin
--    06/30/2005 - CR # 211199 -- removed CLR_dly dependency
      if(GSR_dly = '1')  then
         q4_var := '0';
         q3_var := '0';
         q2_var := '0';
         q1_var := '0';
      elsif(GSR_dly = '0') then
         if(falling_edge(I_dly)) then
            q4_var := q3_var;
            q3_var := q2_var;
            q2_var := q1_var;
            q1_var := CE_dly;
         end if;
  
         q4_sig	 <= q4_var;
      end if;
   end process prcs_ce;

   ce_en <= CE_dly when (SIM_DEVICE = "VIRTEX5") else q4_sig;

--####################################################################
--#####                       CLK-I                              #####
--####################################################################
  prcs_I:process(I_dly, GSR_dly, CLR_dly, ce_en)
  variable clk_count      : integer := 0;
  variable toggle_count   : integer := 0;
  variable first          : boolean := true;
  variable FIRST_TIME     : boolean := true;
  begin
       if(divide) then
          if((GSR_dly = '1') or (CLR_dly = '1')) then
            O_zd       <= '0';
            clk_count  := 0;
            FIRST_TIME := true;
          elsif((GSR_dly = '0') and (CLR_dly = '0')) then
             if(ce_en = '1') then
                if((I_dly='1') and (FIRST_TIME)) then
                    O_zd <= '1';
                    first        := true;
                    toggle_count := FIRST_TOGGLE_COUNT;
                    FIRST_TIME := false;
                elsif ((I_dly'event) and ( FIRST_TIME = false)) then
                    if(clk_count = toggle_count) then
                       O_zd <= not O_zd;
                       clk_count := 0;
                       first := not first;
                       if(first = true) then
                         toggle_count := FIRST_TOGGLE_COUNT;
                       else
                         toggle_count := SECOND_TOGGLE_COUNT;
                       end if;
                    end if;
                 end if;
 
                 if (FIRST_TIME = false) then
                       clk_count := clk_count + 1;
                end if;
             else
                 clk_count := 0;
                 FIRST_TIME := true;
             end if;
          end if;
       else
          O_zd <= I_dly;
       end if;
  end process prcs_I;

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(O_zd)
  begin
--    06/30/2005 - CR # 211199 -- 
--    O <= O_zd after SYNC_PATH_DELAY;
      O <= O_zd;
  end process prcs_output;
--####################################################################


end BUFR_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/capture_virtex4.vhd,v 1.5 2004/04/08 18:46:30 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Register State Capture for Bitstream Readback for VIRTEX4
-- /___/   /\     Filename : CAPTURE_VIRTEX4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:03 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL CAPTURE_VIRTEX4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CAPTURE_VIRTEX4 is
  generic(
    ONESHOT : boolean := true
    );  
  port(
    CAP : in std_ulogic;
    CLK : in std_ulogic
    );

end CAPTURE_VIRTEX4;

architecture CAPTURE_VIRTEX4_V of CAPTURE_VIRTEX4 is

begin
end CAPTURE_VIRTEX4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/dcireset.vhd,v 1.7 2005/03/10 22:45:35 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Reset for DCI State Machine
-- /___/   /\     Filename : DCIRESET.vhd
-- \   \  /  \    Timestamp : Fri Mar 26 08:17:58 PST 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL DCIRESET -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;


library unisim;
use unisim.vpkg.all;

entity DCIRESET is

  port(
      LOCKED	: out std_ulogic;

      RST	: in  std_ulogic
    );

end DCIRESET;

architecture DCIRESET_V OF DCIRESET is

begin

  --------------------
  --  BEHAVIOR SECTION
  --------------------


--####################################################################
--#####                           OUTPUT                         #####
--####################################################################
  prcs_rst:process(RST)
  variable RiseTime  : time := 0 ps;
  variable FallTime  : time := 0 ps;
  variable HighPuLse : time := 0 ps;
  variable LowPuLse  : time := 0 ps;

  begin

     if(rising_edge(RST)) then
        RiseTime := now;
        if(RiseTime > 0 ps) then
           LowPulse := RiseTIme - FallTime;
        end if;
        
        if(LowPulse < 100 ns) then
           assert false
           report "Timing Violation Error : The low  pulse of RST signal in DCIRESET has to be greater than 100 ns" 
           severity Error; 
        end if;
     end if; 

     if(falling_edge(RST)) then
        FallTime := now;
        if(FallTime > 0 ps) then
           HighPulse := FallTime - RiseTime;
        end if;
        
        if(HighPulse < 100 ns) then
           assert false
           report "Timing Violation Error : The high pulse of RST signal in DCIRESET has to be greater than 100 ns" 
           severity Error; 
        end if;
     end if; 

     if(RST = '1') then
        LOCKED <= '0' after 0 ns;
     elsif(RST = '0') then
        LOCKED <= '1' after 100 ns;
     end if;
  end process prcs_rst;
end DCIRESET_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/dcm_adv.vhd,v 1.29.4.5 2008/03/28 19:14:21 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Digital Clock Manager with Advanced Features
-- /___/   /\     Filename : DCM_ADV.vhd
-- \   \  /  \    Timestamp : Fri Jun 18 10:57:23 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    04/22/05 - Change DRP set clkfx M/D value effected on RST=1, not rising
--               edge. (CR 206731)
--    05/03/05 - Made changes for speed improvement: seperate process for output
--               clocks; Use senstivity list instead of wait on; remove vital 
--               timing check related code.
--    05/11/05 - Add attribute DCM_AUTOCALIBRATION (CR 208095).
--               Add clkin alignment check control to remove the glitch when
--               clkin stopped. (CR207409).
--    05/25/05 - Seperate clock_second_pos and neg to another process due to 
--               wait caused unreset. (CR 208771)
--    06/03/05 - Use after instead wait for clk0_out(CR209283). 
--               Update error message (CR 209076).
--    07/05/05 - Use counter to generate clkdv_out to align with clk0_out. (CR211465). 
--    07/25/05 - Set CLKIN_PERIOD default to 10.0ns to (CR 213190).
--    08/30/05 - Change reset for CLK270, CLK180, etc (CR 213641).
--    09/08/05 - Add positive edge trig to dcm_maximum_period_check_v. (CR 216828).
--    12/05/05 - Add warning for  un-used DRP address use. (CR 221885)
--    12/22/05 - LOCKED = x when RST less than 3 clock cycles (CR 222795)
--    01/06/06 - Remove GSR from 3 cycle check. (223099).
--    01/12/06 - Remove GSR from reset logic. (223099).
--    01/26/06 - Add reset to maximum period check module (CR 224287).
--    02/28/06 - remove 1 ps in clkfx_out block to support fs resolution. (CR222390)
--               Add SIM_DEVICE generic to support V5 and V4 M and D for CLKFX (BT#1003).
--               Connect DO bit 4 to 15 to 0. (CR 226209)
--    08/10/06 - Set PSDONE to 0 when CLKOUT_PHASE_SHIFT=FIXED (CR 227018).
--    03/07/07 - Change DRP CLKFX Multiplier to bit 15 to 8 and Divider to bit 7 to 0.
--               (CR 435600).
--    04/06/07 - Enable the clock out in clock low time after reset in model
--               clock_divide_by_2  (CR 437471).
--    09/20/07 - Use 1.5 factor for clock stopped check when CLKIN divide by 2 set(CR446707).
--    11/01/07 - Add DRP DFS_FREQUENCY_MODE and DLL_FREQUENCY_MODE read/write support (CR435651)
--    12/20/07 - Add DRP CLKIN_DIV_BY_2 read/write support (CR457282)
--    02/21/08 - Align clk2x to both clk0 pos and neg edges. (CR467858).
--    03/01/08 - Disable alignment of clkfb and clkin_fb check when ps_lock high (CR468893).
--    03/11/08 - Not check clock lost when negative edge period smaller than positive edge
--               period in dcm_adv_clock_lost module (CR469499).
--    03/12/08 - always generate clk2x with even duty cycle regardless CLKIN duty cycle.(CR467858).
-- End Revision


----- dcm_adv_clock_divide_by_2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity dcm_adv_clock_divide_by_2 is
  port(
    clock_out : out std_ulogic := '0';

    clock : in std_ulogic;
    clock_type : in std_ulogic;
    rst : in std_ulogic
    );
end dcm_adv_clock_divide_by_2;

architecture dcm_adv_clock_divide_by_2_V of dcm_adv_clock_divide_by_2 is
  signal clock_div2 : std_ulogic := '0';
  signal rst_reg : std_logic_vector(2 downto 0);
  signal clk_src : std_ulogic;
begin

  CLKIN_DIVIDER : process
  begin
    if (rising_edge(clock)) then
      clock_div2 <= not clock_div2;
    end if;
    wait on clock;
  end process CLKIN_DIVIDER;

  gen_reset : process
  begin
    if (rising_edge(clock)) then      
      rst_reg(0) <= rst;
      rst_reg(1) <= rst_reg(0) and rst;
      rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst;
    end if;      
    wait on clock;    
  end process gen_reset;

  clk_src <= clock_div2 when (clock_type = '1') else clock;

  assign_clkout : process
  begin
    if (rst = '0') then
      clock_out <= clk_src;
    elsif (rst = '1') then
      clock_out <= '0';
      wait until falling_edge(rst_reg(2));
      if (clk_src = '1') then
         wait until falling_edge(clk_src);
      end if;
    end if;
    wait on clk_src, rst, rst_reg;
  end process assign_clkout;

end dcm_adv_clock_divide_by_2_V;

----- dcm_adv_maximum_period_check  -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;

library STD;
use STD.TEXTIO.all;

entity dcm_adv_maximum_period_check is
  generic (
    InstancePath : string := " ";

    clock_name : string := "";
    maximum_period : time);
  port(
    clock : in std_ulogic;
    rst : in std_ulogic
    );
end dcm_adv_maximum_period_check;

architecture dcm_adv_maximum_period_check_V of dcm_adv_maximum_period_check is
begin

  MAX_PERIOD_CHECKER : process
    variable clock_edge_previous : time := 0 ps;
    variable clock_edge_current : time := 0 ps;
    variable clock_period : time := 0 ps;
    variable Message : line;
  begin
   if (rising_edge(clock)) then
    clock_edge_previous := clock_edge_current;
    clock_edge_current := NOW;

    if (clock_edge_previous > 0 ps ) then
      clock_period := clock_edge_current - clock_edge_previous;
    end if;

    if (clock_period > maximum_period and rst = '0') then
      Write ( Message, string'(" Warning : Input Clock Period of "));
      Write ( Message, clock_period );
      Write ( Message, string'(" on the ") );
      Write ( Message, clock_name );      
      Write ( Message, string'(" port ") );      
      Write ( Message, string'(" of DCM_ADV instance ") );
      Write ( Message, string'(" exceeds allowed value of ") );
      Write ( Message, maximum_period );
      Write ( Message, string'(" at simulation time ") );
      Write ( Message, clock_edge_current );
      Write ( Message, '.' & LF );
      assert false report Message.all severity warning;
      DEALLOCATE (Message);
     end if;
    end if;
    wait on clock;
  end process MAX_PERIOD_CHECKER;
end dcm_adv_maximum_period_check_V;

----- dcm_adv_clock_lost  -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity dcm_adv_clock_lost is
  port(
    lost : out std_ulogic := '0';

    clock : in std_ulogic;
    enable : in boolean := false;
    rst :  in std_ulogic    
    );
end dcm_adv_clock_lost;

architecture dcm_adv_clock_lost_V of dcm_adv_clock_lost is
  signal period : time := 0 ps;
  signal period_neg : time := 0 ps;
  signal period_tmp_win : time := 0 ps;
  signal period_neg_tmp_win : time := 0 ps;
  signal period_chk_win : time := 0 ps;
  signal lost_r : std_ulogic := '0';
  signal lost_f : std_ulogic := '0';
  signal lost_sig : std_ulogic := '0';  
  signal clock_negedge, clock_posedge : integer := 0;
  signal clock_low, clock_high : integer := 0;
  signal clock_second_pos, clock_second_neg : integer := 0;
begin

  determine_period : process(clock,rst)
    variable clock_edge_previous : time := 0 ps;
    variable clock_edge_current : time := 0 ps;    
    variable period_tmp : time := 0 ps;    
  begin
      if (rst = '1') then
        period <= 0 ps;
      elsif (rising_edge(clock)) then
        clock_edge_previous := clock_edge_current;
        clock_edge_current := NOW;
        period_tmp := clock_edge_current - clock_edge_previous;
        if (period /= 0 ps and (period_tmp <= period_tmp_win)) then
          period <= period_tmp;
        elsif (period /= 0 ps and (period_tmp > period_tmp_win)) then
          period <= 0 ps;
        elsif ((period = 0 ps) and (clock_edge_previous /= 0 ps) and (clock_second_pos = 1)) then
          period <= period_tmp;
        end if;
      end if;      
  end process determine_period;

  period_15_p : process(period) begin
     period_tmp_win <= 1.5 * period;
     period_chk_win <= (period * 9.1) / 10;
  end process;

  determine_period_neg : process(clock,rst)
    variable clock_edge_neg_previous : time := 0 ps;
    variable clock_edge_neg_current : time := 0 ps;    
    variable period_neg_tmp : time := 0 ps;    
  begin
      if (rst = '1') then
        period_neg <= 0 ps;
      elsif (falling_edge(clock)) then
        clock_edge_neg_previous := clock_edge_neg_current;
        clock_edge_neg_current := NOW;
        period_neg_tmp := clock_edge_neg_current - clock_edge_neg_previous;
        if (period_neg /= 0 ps and (period_neg_tmp <= period_neg_tmp_win)) then
          period_neg <= period_neg_tmp;
        elsif (period_neg /= 0 ps and (period_neg_tmp > period_neg_tmp_win)) then
          period_neg <= 0 ps;
        elsif ((period_neg = 0 ps) and (clock_edge_neg_previous /= 0 ps) and (clock_second_neg = 1)) then
          period_neg <= period_neg_tmp;
        end if;
      end if;      
  end process determine_period_neg;

  period_15_neg_p : process(period_neg) begin
     period_neg_tmp_win <= 1.5 * period_neg;
  end process;

  CLOCK_LOST_CHECKER : process

  begin
      if (rst = '1') then
        clock_low <= 0;
        clock_high <= 0;
        clock_posedge <= 0;              
        clock_negedge <= 0;
      else
        if (rising_edge(clock)) then
          clock_low <= 0;
          clock_high <= 1;
          clock_posedge <= 0;              
          clock_negedge <= 1;
        end if;

        if (falling_edge(clock)) then
          clock_low <= 1;
          clock_high <= 0;
          clock_posedge <= 1;
          clock_negedge <= 0;
        end if;
      end if;

    wait on clock, rst;
  end process CLOCK_LOST_CHECKER;    
 
  CLOCK_SECOND_P : process
    begin
      if (rst = '1') then
        clock_second_pos <= 0;
        clock_second_neg <= 0;
    else
      if (rising_edge(clock)) then
        clock_second_pos <= 1;
      end if;
      if (falling_edge(clock)) then
          clock_second_neg <= 1;
      end if;
    end if;
    wait on clock, rst;
  end process CLOCK_SECOND_P;


  SET_RESET_LOST_R : process
    begin
    if (rst = '1') then
      lost_r <= '0';
    else
      if ((enable = true) and (clock_second_pos = 1))then
        if (rising_edge(clock)) then
          wait for 0 ps;
          wait for 0 ps;
          wait for 0 ps;                      
          if (period /= 0 ps) then
            lost_r <= '0';        
          end if;
          wait for period_chk_win;
          if ((clock_low /= 1) and (clock_posedge /= 1) and (rst = '0')) then
            lost_r <= '1';
          end if;
        end if;
      end if;
    end if;
    wait on clock, rst;    
  end process SET_RESET_LOST_R;

  SET_RESET_LOST_F : process
    begin
      if (rst = '1') then
        lost_f <= '0';
      else
          if ((enable = true) and (clock_second_neg = 1))then
            if (falling_edge(clock)) then
              if (period /= 0 ps) then      
                lost_f <= '0';
              end if;
              wait for period_chk_win;
              if ((clock_high /= 1) and (clock_negedge /= 1) and (rst = '0') and (period <= period_neg)) then
                lost_f <= '1';
              end if;      
            end if;        
          end if;
      end if;
    wait on clock, rst;    
  end process SET_RESET_LOST_F;      

  assign_lost : process
    begin
      if (enable = true) then
        if (lost_r'event) then
          lost <= lost_r;
        end if;
        if (lost_f'event) then
          lost <= lost_f;
        end if;
      end if;      
      wait on lost_r, lost_f;
    end process assign_lost;
end dcm_adv_clock_lost_V;



----- CELL DCM_ADV  -----
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;




library STD;
use STD.TEXTIO.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity DCM_ADV is
  generic (
    TimingChecksOn : boolean := true;
    InstancePath : string := " ";
    Xon : boolean := true;
    MsgOn : boolean := false;

    CLKDV_DIVIDE : real := 2.0;
    CLKFX_DIVIDE : integer := 1;
    CLKFX_MULTIPLY : integer := 4;
    CLKIN_DIVIDE_BY_2 : boolean := false;
    CLKIN_PERIOD : real := 10.0;                         --non-simulatable
    CLKOUT_PHASE_SHIFT : string := "NONE";
    CLK_FEEDBACK : string := "1X";
    DCM_AUTOCALIBRATION : boolean := true;
    DCM_PERFORMANCE_MODE : string := "MAX_SPEED";	-- non-simulatable    
    DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";     --non-simulatable
    DFS_FREQUENCY_MODE : string := "LOW";
    DLL_FREQUENCY_MODE : string := "LOW";
    DUTY_CYCLE_CORRECTION : boolean := true;
    FACTORY_JF : bit_vector := X"F0F0";                 --non-simulatable


    PHASE_SHIFT : integer := 0;


    SIM_DEVICE : string := "VIRTEX4";
    STARTUP_WAIT : boolean := false                     --non-simulatable
    );

  port (
    CLK0 : out std_ulogic := '0';
    CLK180 : out std_ulogic := '0';
    CLK270 : out std_ulogic := '0';
    CLK2X : out std_ulogic := '0';
    CLK2X180 : out std_ulogic := '0';
    CLK90 : out std_ulogic := '0';
    CLKDV : out std_ulogic := '0';
    CLKFX : out std_ulogic := '0';
    CLKFX180 : out std_ulogic := '0';
    DO : out std_logic_vector(15 downto 0) := "0000000000000000";
    DRDY : out std_ulogic := '0';    
    LOCKED : out std_ulogic := '0';
    PSDONE : out std_ulogic := '0';

    
    CLKFB : in std_ulogic := '0';
    CLKIN : in std_ulogic := '0';
    DADDR : in std_logic_vector(6 downto 0) := "0000000";
    DCLK : in std_ulogic := '0';    
    DEN : in std_ulogic := '0';
    DI : in std_logic_vector(15 downto 0) := "0000000000000000";
    DWE : in std_ulogic := '0';
    PSCLK : in std_ulogic := '0';
    PSEN : in std_ulogic := '0';
    PSINCDEC : in std_ulogic := '0';
    RST : in std_ulogic := '0'
    );



end DCM_ADV;

architecture DCM_ADV_V of DCM_ADV is
  

  component dcm_adv_clock_divide_by_2
    port(
      clock_out : out std_ulogic;

      clock : in std_ulogic;
      clock_type : in std_ulogic;
      rst : in std_ulogic
      );
  end component;

  component dcm_adv_maximum_period_check
    generic (
      InstancePath : string := " ";

      clock_name : string := "";
      maximum_period : time);
    port(
      clock : in std_ulogic;
      rst : in std_ulogic
      );
  end component;

  component dcm_adv_clock_lost
    port(
      lost : out std_ulogic;

      clock : in std_ulogic;
      enable : in boolean := false;
      rst :  in std_ulogic          
      );    
  end component;


  constant MAXPERCLKIN : time := 1000000 ps;
  constant MAXPERPSCLK : time := 100000000 ps;
  constant SIM_CLKIN_CYCLE_JITTER : time := 300 ps;
  constant SIM_CLKIN_PERIOD_JITTER : time := 1000 ps;

  signal clkfb_ipd : std_ulogic;
  signal clkin_ipd : std_ulogic;
  signal daddr_ipd : std_logic_vector(6 downto 0);
  signal dclk_ipd : std_ulogic;
  signal den_ipd : std_ulogic;
  signal di_ipd : std_logic_vector(15 downto 0);  
  signal dwe_ipd : std_ulogic;
  signal psclk_ipd : std_ulogic;
  signal psen_ipd : std_ulogic;
  signal psincdec_ipd : std_ulogic;
  signal rst_ipd : std_ulogic;

  signal   CLKIN_dly  :  std_ulogic;
  signal   CLKFB_dly  :  std_ulogic;
  signal   RST_dly  :  std_ulogic;
  signal   PSINCDEC_dly  :  std_ulogic;
  signal   PSEN_dly  :  std_ulogic;
  signal   PSCLK_dly  :  std_ulogic;
  signal   DADDR_dly  :  std_logic_vector(6 downto 0);
  signal   DI_dly  :  std_logic_vector(15 downto 0);
  signal   DWE_dly  :  std_ulogic;
  signal   DEN_dly  :  std_ulogic;
  signal   DCLK_dly  :  std_ulogic;    
  signal   GSR_dly   :  std_ulogic := '0';
  
  signal clk0_out : std_ulogic := '0';
  signal clk2x_out : std_ulogic := '0';
  signal clkdv_out : std_ulogic := '0';
  signal clkfx_out : std_ulogic := '0';
  signal drdy_out : std_ulogic := '0';
  signal do_out  : std_logic_vector(15 downto 0) := "0000000000000000";
  signal do_out_reg  : std_logic_vector(15 downto 0) := "0000000000000000";   
  signal do_out_s  : std_logic_vector(15 downto 0) := "0000000000000000";   
  signal do_out_drp  : std_logic_vector(15 downto 0) := "0000000000000000";   
  signal do_out_drp1  : std_logic_vector(15 downto 0) := "0000000000000000";   
  signal do_stat_en : std_ulogic := '1';
  signal clkfx_md_reg : std_logic_vector(15 downto 0);
  signal daddr_in_lat : std_logic_vector(6 downto 0); 
  signal clkdv_cnt : integer := 0;
  signal locked_out : std_ulogic := '0';
  signal psdone_out : std_ulogic := '0';

  signal locked_out_tmp : std_ulogic;

  signal locked_pulse : std_ulogic;      
  
  signal ps_overflow_out, ps_lock : std_ulogic := '0';

  signal clkfb_type : integer;
  signal divide_type : integer;
  signal clkin_type : std_ulogic := '0';
  signal ps_type : integer;
  signal deskew_adjust_mode : integer;
  signal dfs_mode_type : std_ulogic;
  signal dll_mode_type : std_logic_vector(1 downto 0);
  signal dfs_mode_reg : std_logic_vector(15 downto 0);
  signal dll_mode_reg : std_logic_vector(15 downto 0);
  signal clkin_div2_reg : std_logic_vector(15 downto 0);
  signal sim_device_type : std_ulogic;
  signal clk1x_type : integer;
  signal ps_in_current, ps_min, ps_max : integer;

  signal lock_period, lock_delay, lock_clkin, lock_clkfb : std_ulogic := '0';
  signal lock_out : std_logic_vector(1 downto 0) := "00";  
  signal lock_out1_neg : std_ulogic := '0';
  signal locked_out_out : std_ulogic := '0';

  signal lock_fb, lock_ps, lock_ps_dly : std_ulogic := '0';
  signal fb_delay_found : std_ulogic := '0';

  signal clkin_div : std_ulogic;
  signal clkin_ps : std_ulogic;
  signal clkin_fb : std_ulogic;


  signal ps_delay : time := 0 ps;


  type   real_array_usr is array (2 downto 0) of time; 
  signal clkin_period_real : real_array_usr := (0.000 ns, 0.000 ns, 0.000 ns);
  signal period : time := 0 ps;
  signal period_25 : time := 0 ps;
  signal period_50 : time := 0 ps;
  signal period_div : time := 0 ps;
  signal period_orig : time := 0 ps;
  signal period_stop_ck : time := 0 ps;
  signal period_ps : time := 0 ps;
  signal clkout_delay : time := 0 ps;
  signal fb_delay : time := 0 ps;
  signal period_fx, remain_fx : time := 0 ps;
  signal period_dv_high, period_dv_low : time := 0 ps;
  signal cycle_jitter, period_jitter : time := 0 ps;

  signal clkin_window, clkfb_window : std_ulogic := '0';
  signal rst_reg : std_logic_vector(2 downto 0) := "000";
  signal rst_flag : std_ulogic := '0';

  signal numerator : integer := CLKFX_MULTIPLY;
  signal denominator : integer := CLKFX_DIVIDE;    
  signal gcd : integer := 1;    

  signal clkin_lost_out : std_ulogic := '0';
  signal clkfx_lost_out : std_ulogic := '0';
  signal clkfb_lost_out : std_ulogic := '0';  

  signal remain_fx_temp : integer := 0;


  signal clk0_sig : std_ulogic := '0';
  signal clk2x_sig : std_ulogic := '0';
  signal clkfx_sig : std_ulogic := '0';    

  signal first_time_locked : boolean := false;

  signal mem : std_logic_vector(1521 downto 0);    

  signal drp_lock : std_ulogic := '0';
  signal drp_lock1 : std_ulogic := '0';

  constant CLKFX_MULTIPLY_ADDR : integer := 80;
  constant CLKFX_DIVIDE_ADDR : integer := 82;
  constant PHASE_SHIFT_ADDR : integer := 85;
  constant DFS_FREQ_MODE_ADDR : integer := 65;
  constant DLL_FREQ_MODE_ADDR : integer := 81;
  constant CLKIN_DIV_BY2_ADDR : integer := 68;

  constant PHASE_SHIFT_KICK_OFF_ADDR : integer := 17;
  
  constant DCM_DEFAULT_STATUS_ADDR : integer := 0;

  signal clkfx_multiply_drp : integer := CLKFX_MULTIPLY;
  signal clkfx_divide_drp : integer := CLKFX_DIVIDE;
  signal ps_in_drp : integer := 0;


  signal single_step_done : std_ulogic := '0';

  signal ps_drp_lock : std_ulogic := '0';
  signal ps_kick_off_cmd : std_ulogic := '0';  

  signal clock_stopped : std_ulogic := '1';
  signal clock_stopped_factor : real := 2.0;

  signal inc_dec : std_ulogic;

  signal tap_delay_step : time;

  signal en_status : boolean := false;

  signal ps_overflow_out_ext : std_ulogic := '0';  
  signal clkin_lost_out_ext : std_ulogic := '0';
  signal clkfx_lost_out_ext : std_ulogic := '0';
  signal clkfb_lost_out_ext : std_ulogic := '0';

  signal lock_period_dly : std_ulogic := '0';
  signal lock_period_pulse : std_ulogic := '0';

  signal clkin_chkin, clkfb_chkin : std_ulogic := '0';
  signal chk_enable, chk_rst : std_ulogic := '0';

  signal rst_input : std_ulogic;  

  
begin
  INITPROC : process
    variable Message : line;

    variable FACTORY_JF_slv : std_logic_vector(15 downto 0) := To_StdLogicVector(FACTORY_JF);    
  begin
    detect_resolution
      (model_name => "DCM_ADV"
       );
    if (CLKDV_DIVIDE = 1.5) then
      divide_type <= 3;
    elsif (CLKDV_DIVIDE = 2.0) then
      divide_type <= 4;
    elsif (CLKDV_DIVIDE = 2.5) then
      divide_type <= 5;
    elsif (CLKDV_DIVIDE = 3.0) then
      divide_type <= 6;
    elsif (CLKDV_DIVIDE = 3.5) then
      divide_type <= 7;
    elsif (CLKDV_DIVIDE = 4.0) then
      divide_type <= 8;
    elsif (CLKDV_DIVIDE = 4.5) then
      divide_type <= 9;
    elsif (CLKDV_DIVIDE = 5.0) then
      divide_type <= 10;
    elsif (CLKDV_DIVIDE = 5.5) then
      divide_type <= 11;
    elsif (CLKDV_DIVIDE = 6.0) then
      divide_type <= 12;
    elsif (CLKDV_DIVIDE = 6.5) then
      divide_type <= 13;
    elsif (CLKDV_DIVIDE = 7.0) then
      divide_type <= 14;
    elsif (CLKDV_DIVIDE = 7.5) then
      divide_type <= 15;
    elsif (CLKDV_DIVIDE = 8.0) then
      divide_type <= 16;
    elsif (CLKDV_DIVIDE = 9.0) then
      divide_type <= 18;
    elsif (CLKDV_DIVIDE = 10.0) then
      divide_type <= 20;
    elsif (CLKDV_DIVIDE = 11.0) then
      divide_type <= 22;
    elsif (CLKDV_DIVIDE = 12.0) then
      divide_type <= 24;
    elsif (CLKDV_DIVIDE = 13.0) then
      divide_type <= 26;
    elsif (CLKDV_DIVIDE = 14.0) then
      divide_type <= 28;
    elsif (CLKDV_DIVIDE = 15.0) then
      divide_type <= 30;
    elsif (CLKDV_DIVIDE = 16.0) then
      divide_type <= 32;
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLKDV_DIVIDE",
         EntityName => "DCM_ADV",
         InstanceName => InstancePath,
         GenericValue => CLKDV_DIVIDE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    if ((CLKFX_DIVIDE <= 0) or (32 < CLKFX_DIVIDE)) then
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLKFX_DIVIDE",
         EntityName => "DCM_ADV",
         InstanceName => InstancePath,
         GenericValue => CLKFX_DIVIDE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are 1....32",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;
    if ((CLKFX_MULTIPLY <= 1) or (32 < CLKFX_MULTIPLY)) then
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLKFX_MULTIPLY",
         EntityName => "DCM_ADV",
         InstanceName => InstancePath,
         GenericValue => CLKFX_MULTIPLY,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are 2....32",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;
    case CLKIN_DIVIDE_BY_2 is
      when false => clock_stopped_factor <= 2.0;
      when true => clock_stopped_factor <= 1.5;
      when others =>
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "CLKIN_DIVIDE_BY_2",
           EntityName => "DCM_ADV",
           InstanceName => InstancePath,
           GenericValue => CLKIN_DIVIDE_BY_2,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
    end case;


    if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then
      ps_type <= 0;
    elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then
      ps_type <= 1;
      if ((PHASE_SHIFT < -255) or (PHASE_SHIFT > 255)) then
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "PHASE_SHIFT",
           EntityName => "DCM_ADV",
           InstanceName => InstancePath,
           GenericValue => PHASE_SHIFT,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are -255 ... 255",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;      
    elsif ((CLKOUT_PHASE_SHIFT = "variable_positive") or (CLKOUT_PHASE_SHIFT = "VARIABLE_POSITIVE")) then
      ps_type <= 3;
      if ((PHASE_SHIFT < 0) or (PHASE_SHIFT > 255)) then
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "PHASE_SHIFT",
           EntityName => "DCM_ADV",
           InstanceName => InstancePath,
           GenericValue => PHASE_SHIFT,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are 0 ... 255",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
    elsif ((CLKOUT_PHASE_SHIFT = "variable_center") or (CLKOUT_PHASE_SHIFT = "VARIABLE_CENTER")) then
      ps_type <= 4;
      if ((PHASE_SHIFT < -255) or (PHASE_SHIFT > 255)) then
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "PHASE_SHIFT",
           EntityName => "DCM_ADV",
           InstanceName => InstancePath,
           GenericValue => PHASE_SHIFT,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are -255 ... 255",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;
    elsif ((CLKOUT_PHASE_SHIFT = "direct") or (CLKOUT_PHASE_SHIFT = "DIRECT")) then
      ps_type <= 5;
      if ((PHASE_SHIFT < 0) or (PHASE_SHIFT > 1023))then
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "PHASE_SHIFT",
           EntityName => "DCM_ADV",
           InstanceName => InstancePath,
           GenericValue => PHASE_SHIFT,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are 0 ... 1023",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;                        
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLKOUT_PHASE_SHIFT",
         EntityName => "DCM_ADV",
         InstanceName => InstancePath,
         GenericValue => CLKOUT_PHASE_SHIFT,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are NONE, FIXED, VARIABLE_POSITIVE, VARIABLE_CENTER OR DIRECT",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    if ((CLK_FEEDBACK = "none") or (CLK_FEEDBACK = "NONE")) then
      clkfb_type <= 0;
      Write ( Message, string'(" Attribute CLK_FEEDBACK is set to value NONE."));
      Write ( Message, string'(" In this mode, the output ports CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90 and  CLKDV can have any random phase relation w.r.t. input port CLKIN"));
      Write ( Message, '.' & LF );
      assert false report Message.all severity note;
      DEALLOCATE (Message);            
    elsif ((CLK_FEEDBACK = "1x") or (CLK_FEEDBACK = "1X")) then
      clkfb_type <= 1;
--    elsif ((CLK_FEEDBACK = "2x") or (CLK_FEEDBACK = "2X")) then
--      clkfb_type <= 2;
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLK_FEEDBACK",
         EntityName => "DCM_ADV",
         InstanceName => InstancePath,
         GenericValue => CLK_FEEDBACK,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are NONE or 1X",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    if (DCM_PERFORMANCE_MODE = "MAX_SPEED") then
      tap_delay_step <= 11 ps;
    elsif (DCM_PERFORMANCE_MODE = "MAX_RANGE") then
      tap_delay_step <= 18 ps;
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "DCM_PERFORMANCE_MODE",
         EntityName => "DCM_ADV",
         InstanceName => InstancePath,
         GenericValue => DCM_PERFORMANCE_MODE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are MAX_SPEED or MAX_RANGE",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );      
    end if;


    if ((DESKEW_ADJUST = "source_synchronous") or (DESKEW_ADJUST = "SOURCE_SYNCHRONOUS")) then
      DESKEW_ADJUST_mode <= 8;
    elsif ((DESKEW_ADJUST = "system_synchronous") or (DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS")) then
      DESKEW_ADJUST_mode <= 11;
    elsif ((DESKEW_ADJUST = "0")) then
      DESKEW_ADJUST_mode <= 0;
    elsif ((DESKEW_ADJUST = "1")) then
      DESKEW_ADJUST_mode <= 1;
    elsif ((DESKEW_ADJUST = "2")) then
      DESKEW_ADJUST_mode <= 2;
    elsif ((DESKEW_ADJUST = "3")) then
      DESKEW_ADJUST_mode <= 3;
    elsif ((DESKEW_ADJUST = "4")) then
      DESKEW_ADJUST_mode <= 4;
    elsif ((DESKEW_ADJUST = "5")) then
      DESKEW_ADJUST_mode <= 5;
    elsif ((DESKEW_ADJUST = "6")) then
      DESKEW_ADJUST_mode <= 6;
    elsif ((DESKEW_ADJUST = "7")) then
      DESKEW_ADJUST_mode <= 7;
    elsif ((DESKEW_ADJUST = "8")) then
      DESKEW_ADJUST_mode <= 8;
    elsif ((DESKEW_ADJUST = "9")) then
      DESKEW_ADJUST_mode <= 9;
    elsif ((DESKEW_ADJUST = "10")) then
      DESKEW_ADJUST_mode <= 10;
    elsif ((DESKEW_ADJUST = "11")) then
      DESKEW_ADJUST_mode <= 11;
    elsif ((DESKEW_ADJUST = "12")) then
      DESKEW_ADJUST_mode <= 12;
    elsif ((DESKEW_ADJUST = "13")) then
      DESKEW_ADJUST_mode <= 13;
    elsif ((DESKEW_ADJUST = "14")) then
      DESKEW_ADJUST_mode <= 14;
    elsif ((DESKEW_ADJUST = "15")) then
      DESKEW_ADJUST_mode <= 15;
    elsif ((DESKEW_ADJUST = "16")) then
      DESKEW_ADJUST_mode <= 16;
    elsif ((DESKEW_ADJUST = "17")) then
      DESKEW_ADJUST_mode <= 17;
    elsif ((DESKEW_ADJUST = "18")) then
      DESKEW_ADJUST_mode <= 18;
    elsif ((DESKEW_ADJUST = "19")) then
      DESKEW_ADJUST_mode <= 19;
    elsif ((DESKEW_ADJUST = "20")) then
      DESKEW_ADJUST_mode <= 20;
    elsif ((DESKEW_ADJUST = "21")) then
      DESKEW_ADJUST_mode <= 21;
    elsif ((DESKEW_ADJUST = "22")) then
      DESKEW_ADJUST_mode <= 22;
    elsif ((DESKEW_ADJUST = "23")) then
      DESKEW_ADJUST_mode <= 23;
    elsif ((DESKEW_ADJUST = "24")) then
      DESKEW_ADJUST_mode <= 24;
    elsif ((DESKEW_ADJUST = "25")) then
      DESKEW_ADJUST_mode <= 25;
    elsif ((DESKEW_ADJUST = "26")) then
      DESKEW_ADJUST_mode <= 26;
    elsif ((DESKEW_ADJUST = "27")) then
      DESKEW_ADJUST_mode <= 27;
    elsif ((DESKEW_ADJUST = "28")) then
      DESKEW_ADJUST_mode <= 28;
    elsif ((DESKEW_ADJUST = "29")) then
      DESKEW_ADJUST_mode <= 29;
    elsif ((DESKEW_ADJUST = "30")) then
      DESKEW_ADJUST_mode <= 30;
    elsif ((DESKEW_ADJUST = "31")) then
      DESKEW_ADJUST_mode <= 31;      
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "DESKEW_ADJUST_MODE",
         EntityName => "DCM_ADV",
         InstanceName => InstancePath,
         GenericValue => DESKEW_ADJUST_MODE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 1....15",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    if ((DFS_FREQUENCY_MODE /= "HIGH") and (DFS_FREQUENCY_MODE /= "LOW")) then
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "DFS_FREQUENCY_MODE",
         EntityName => "DCM_ADV",
         InstanceName => InstancePath,
         GenericValue => DFS_FREQUENCY_MODE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are HIGH or LOW",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    if ((DLL_FREQUENCY_MODE /= "HIGH") and  (DLL_FREQUENCY_MODE /= "LOW")) then
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "DLL_FREQUENCY_MODE",
         EntityName => "DCM_ADV",
         InstanceName => InstancePath,
         GenericValue => DLL_FREQUENCY_MODE,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are HIGH or LOW",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    case DUTY_CYCLE_CORRECTION is
      when false => if (SIM_DEVICE = "VIRTEX4") then
                       clk1x_type <= 0;
                    else 
                       clk1x_type <= 1;
                    end if;
      when true => clk1x_type <= 1;
      when others =>
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "DUTY_CYCLE_CORRECTION",
           EntityName => "DCM_ADV",
           InstanceName => InstancePath,
           GenericValue => DUTY_CYCLE_CORRECTION,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
    end case;

    if (FACTORY_JF = X"F0F0") then
    else
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Warning",
           GenericName => "FACTORY_JF",
           EntityName => "DCM_ADV",
           InstanceName => InstancePath,
           GenericValue => SLV_TO_STR(FACTORY_JF_slv),
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute is F0F0 hex",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => warning
           );                          
    end  if;    
    
    period_jitter <= SIM_CLKIN_PERIOD_JITTER;
    cycle_jitter <= SIM_CLKIN_CYCLE_JITTER;
    
    case STARTUP_WAIT is
      when false => null;
      when true => null;
      when others =>
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "STARTUP_WAIT",
           EntityName => "DCM_ADV",
           InstanceName => InstancePath,
           GenericValue => STARTUP_WAIT,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
    end case;

    case DCM_AUTOCALIBRATION is
      when false => null;
      when true => null;
      when others =>
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "DCM_AUTOCALIBRATION",
           EntityName => "DCM_ADV",
           InstanceName => InstancePath,
           GenericValue => DCM_AUTOCALIBRATION,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
    end case;

    if ( SIM_DEVICE = "VIRTEX4") then  
         sim_device_type <= '0';
    elsif (SIM_DEVICE = "VIRTEX5") then
         sim_device_type <= '1';
    else
      Write ( Message, string'("Attribute Syntax Error : The Attribute SIM_DEVICE on DCM_ADV is set to "));
      Write ( Message, SIM_DEVICE);
      Write ( Message, string'(".  Legal values for this attribute are VIRTEX4 or VIRTEX5") );
      Write ( Message, '.' & LF );
      assert false report Message.all severity error;
      DEALLOCATE (Message);
     end if;

    wait;
  end process INITPROC;

--
-- input wire delays
--  

   CLKFB_ipd <= CLKFB;
   CLKIN_ipd <= CLKIN;
   DADDR_dly(6 downto 0) <= DADDR(6 downto 0);
   DCLK_dly <= DCLK;
   DEN_dly <= DEN;
   DI_dly(15 downto 0) <= DI(15 downto 0);
   DWE_dly <= DWE;
   PSCLK_dly <= PSCLK;
   PSEN_dly <= PSEN;
   PSINCDEC_dly <= PSINCDEC;
   rst_input <= RST;

  rst_ipd <= rst_input;

  i_clock_divide_by_2 : dcm_adv_clock_divide_by_2
    port map (
      clock => clkin_ipd,
      clock_type => clkin_type,
      rst => rst_ipd,
      clock_out => clkin_div);

  i_max_clkin : dcm_adv_maximum_period_check
    generic map (
      clock_name => "CLKIN",
      maximum_period => MAXPERCLKIN)

    port map (
      clock => clkin_ipd,
      rst => rst_ipd );

  i_max_psclk : dcm_adv_maximum_period_check
    generic map (
      clock_name => "PSCLK",
      maximum_period => MAXPERPSCLK)

    port map (
      clock => PSCLK_dly,
      rst => rst_ipd );

  i_clkin_lost : dcm_adv_clock_lost
    port map (
      lost  => clkin_lost_out,
      clock => clkin_ipd,
      enable => first_time_locked,
      rst => rst_ipd      
      ); 

  i_clkfx_lost : dcm_adv_clock_lost
    port map (
      lost  => clkfx_lost_out,
      clock => clkfx_out,
      enable => first_time_locked,
      rst => rst_ipd
      );

  i_clkfb_lost : dcm_adv_clock_lost
    port map (
      lost  => clkfb_lost_out,
      clock => clkfb_ipd,
      enable => first_time_locked,
      rst => rst_ipd
      );   

  
  clkin_ps <= transport clkin_div after ps_delay;  

  clkin_fb <= transport  (clkin_ps and lock_fb);

  determine_period_div : process(clkin_div, rst_ipd)
    variable clkin_div_edge_previous : time := 0 ps; 
    variable clkin_div_edge_current : time := 0 ps;
  begin
    if (rst_ipd = '1') then
      clkin_div_edge_previous := 0 ps; 
      clkin_div_edge_current := 0 ps;
      period_div <= 0 ps;
    elsif (rising_edge(clkin_div)) then
        clkin_div_edge_previous := clkin_div_edge_current;
        clkin_div_edge_current := NOW;
        if ((clkin_div_edge_current - clkin_div_edge_previous) <= (1.5 * period_div)) then
          period_div <= clkin_div_edge_current - clkin_div_edge_previous;
        elsif ((period_div = 0 ps) and (clkin_div_edge_previous /= 0 ps)) then
          period_div <= clkin_div_edge_current - clkin_div_edge_previous;      
        end if;          
    end if;
  end process determine_period_div;

  determine_period_ps : process(clkin_ps, rst_ipd)
    variable clkin_ps_edge_previous : time := 0 ps; 
    variable clkin_ps_edge_current : time := 0 ps;    
  begin
    if  (rst_ipd = '1') then
      clkin_ps_edge_previous := 0 ps; 
      clkin_ps_edge_current := 0 ps;
      period_ps <= 0 ps;
    elsif (rising_edge(clkin_ps)) then
        clkin_ps_edge_previous := clkin_ps_edge_current;
        clkin_ps_edge_current := NOW;
        if ((clkin_ps_edge_current - clkin_ps_edge_previous) <= (1.5 * period_ps)) then
          period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous;
        elsif ((period_ps = 0 ps) and (clkin_ps_edge_previous /= 0 ps)) then
          period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous;      
        end if;
    end if;
  end process determine_period_ps;

  assign_lock_ps_fb : process(clkin_ps, rst_ipd)
  begin
    if  (rst_ipd = '1') then
      lock_fb <= '0';
      lock_ps <= '0';
      lock_ps_dly <= '0';                                                  
    elsif (rising_edge(clkin_ps)) then
        lock_ps <= lock_period;
        lock_ps_dly <= lock_ps;                
        lock_fb <= lock_ps_dly;            
    end if;
  end process assign_lock_ps_fb;

  calculate_clkout_delay : process(period, fb_delay, rst_ipd)
  begin
    if (rst_ipd = '1') then
      clkout_delay <= 0 ps;
    elsif (fb_delay = 0 ps) then
      clkout_delay <= 0 ps;                
    else
      clkout_delay <= period - fb_delay;        
    end if;
  end process calculate_clkout_delay;

--
--generate master reset signal
--  

  gen_master_rst : process(clkin_ipd)
  begin
    if (rising_edge(clkin_ipd)) then    
      rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst_input;    
      rst_reg(1) <= rst_reg(0) and rst_input;
      rst_reg(0) <= rst_input;
    end if;
  end process gen_master_rst;

  check_rst_width : process(rst_input)
    variable Message : line;    
    begin
      if (rst_input = '1') then
         rst_flag <= '0';
      end if;
      if (falling_edge(rst_input)) then
        if ((rst_reg(2) and rst_reg(1) and rst_reg(0)) = '0') then
          rst_flag <= '1';
        Write ( Message, string'(" Input Error : RST on instance "));
        Write ( Message, Instancepath );                    
          Write ( Message, string'(" must be asserted for 3 CLKIN clock cycles. "));          
          assert false report Message.all severity error;
          DEALLOCATE (Message);
        end if;        
      end if;
    end process check_rst_width;

--
--phase shift parameters
--  

  determine_phase_shift : process
    variable Message : line;
    variable FINE_SHIFT_RANGE : time;
    variable first_time : boolean := true;
    variable ps_in : integer;                
    variable single_step_lock : std_ulogic := '0';    
  begin
    if (first_time = true) then
      if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then
        ps_in := 256;        
      elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then
        ps_in := PHASE_SHIFT + 256;
        ps_max <= 255 + 256;
        ps_min <= -255 + 256;
        if (DCM_PERFORMANCE_MODE = "MAX_SPEED") then
          FINE_SHIFT_RANGE := 7000 ps;        
        elsif (DCM_PERFORMANCE_MODE = "MAX_RANGE") then
          FINE_SHIFT_RANGE := 10000 ps;        
        end if;        
      elsif ((CLKOUT_PHASE_SHIFT = "variable_positive") or (CLKOUT_PHASE_SHIFT = "VARIABLE_POSITIVE")) then
        ps_in := PHASE_SHIFT + 256;
        ps_max <= 255 + 256;
        ps_min <= 0 + 256;
        if (DCM_PERFORMANCE_MODE = "MAX_SPEED") then
          FINE_SHIFT_RANGE := 7000 ps;        
        elsif (DCM_PERFORMANCE_MODE = "MAX_RANGE") then
          FINE_SHIFT_RANGE := 10000 ps;        
        end if;        
      elsif ((CLKOUT_PHASE_SHIFT = "variable_center") or (CLKOUT_PHASE_SHIFT = "VARIABLE_CENTER")) then
        ps_in := PHASE_SHIFT + 256;
        ps_max <= 255 + 256;
        ps_min <= -255 + 256;
        if (DCM_PERFORMANCE_MODE = "MAX_SPEED") then
          FINE_SHIFT_RANGE := 3500 ps;        
        elsif (DCM_PERFORMANCE_MODE = "MAX_RANGE") then
          FINE_SHIFT_RANGE := 5000 ps;        
        end if;        
      elsif ((CLKOUT_PHASE_SHIFT = "direct") or (CLKOUT_PHASE_SHIFT = "DIRECT")) then
        ps_max <= 1023;
        ps_min <= 0;         
        if (DCM_PERFORMANCE_MODE = "MAX_SPEED") then
          FINE_SHIFT_RANGE := 7000 ps;        
        elsif (DCM_PERFORMANCE_MODE = "MAX_RANGE") then
          FINE_SHIFT_RANGE := 10000 ps;        
        end if;
        ps_in := PHASE_SHIFT;
      end if;
      first_time := false;
    end if;
    
    if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then
      if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then
        ps_in := 256;        
      elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then
        ps_in := PHASE_SHIFT + 256;
      elsif ((CLKOUT_PHASE_SHIFT = "variable_positive") or (CLKOUT_PHASE_SHIFT = "VARIABLE_POSITIVE")) then
        ps_in := PHASE_SHIFT + 256;
      elsif ((CLKOUT_PHASE_SHIFT = "variable_center") or (CLKOUT_PHASE_SHIFT = "VARIABLE_CENTER")) then
        ps_in := PHASE_SHIFT + 256;
      elsif ((CLKOUT_PHASE_SHIFT = "direct") or (CLKOUT_PHASE_SHIFT = "DIRECT")) then
        ps_in := PHASE_SHIFT;
      end if;
      ps_lock <= '0';
      ps_overflow_out <= '0';
      ps_delay <= 0 ps;      
    else
      if (rising_edge(lock_period_pulse)) then
        if ((ps_type = 0) or (ps_type = 1) or (ps_type = 3) or (ps_type = 4))  then        
          ps_delay <= (ps_in * period_div / 256);        
        elsif  (ps_type = 5) then 
          ps_delay <= ps_in * tap_delay_step;
        end if;
      end if;      
      if (rising_edge (lock_period)) then
        if ((ps_type = 0) or (ps_type = 1) or (ps_type = 3) or (ps_type = 4))  then
          if (PHASE_SHIFT > 0) then
            if (((ps_in * period_orig) / 256) > (period_orig + FINE_SHIFT_RANGE)) then
            Write ( Message, string'(" Function Error : Instance "));
            Write ( Message, Instancepath );          
              Write ( Message, string'(" Requested Phase Shift = "));

              Write ( Message, string'(" PHASE_SHIFT * PERIOD/256 = "));
              Write ( Message, PHASE_SHIFT);
              Write ( Message, string'(" * "));
              Write ( Message, period_orig /256);
              Write ( Message, string'(" = "));            
              Write ( Message, (PHASE_SHIFT) * period_orig / 256 );                      
              Write ( Message, string'(" This exceeds the FINE_SHIFT_RANGE of "));            
              Write ( Message, FINE_SHIFT_RANGE);
              assert false report Message.all severity error;
              DEALLOCATE (Message);          
            end if;
          elsif (PHASE_SHIFT < 0) then
            if ((period_orig > FINE_SHIFT_RANGE) and ((ps_in * period_orig / 256) < period_orig - FINE_SHIFT_RANGE)) then
          Write ( Message, string'(" Function Error : Instance "));
          Write ( Message, Instancepath );          
            Write ( Message, string'(" Requested Phase Shift = "));

            Write ( Message, string'(" PHASE_SHIFT * PERIOD/256 = "));
            Write ( Message, PHASE_SHIFT);
            Write ( Message, string'(" * "));
            Write ( Message, period_orig /256);
            Write ( Message, string'(" = "));            
            Write ( Message, (-PHASE_SHIFT) * period_orig / 256);                      
            Write ( Message, string'(" This exceeds the FINE_SHIFT_RANGE of "));            
            Write ( Message, FINE_SHIFT_RANGE);                                      
              assert false report Message.all severity error;
              DEALLOCATE (Message);                  
            end if;
          end if;          
        end if;
        if (ps_type = 5) then
            if ((ps_in * tap_delay_step) > FINE_SHIFT_RANGE) then
            Write ( Message, string'(" Functional Error : Allowed FINE_SHIFT_RANGE on instance "));
            Write ( Message, Instancepath );          
              Write ( Message, string'(" is between 0 to "));
              Write ( Message, FINE_SHIFT_RANGE/tap_delay_step);
              assert false report Message.all severity error;
              DEALLOCATE (Message);          
            end if;          
        end if;
      end if;
      
      if (rising_edge(PSCLK_dly)) then
        if ((ps_type = 3) or (ps_type = 4)) then
          if (PSEN_dly = '1') then
            if (ps_lock = '1') then
              Write ( Message, string'(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift. "));
              assert false report Message.all severity warning;
              DEALLOCATE (Message);              
            else
              if (PSINCDEC_dly = '1') then
                if (ps_in = ps_max) then
                  ps_overflow_out <= '1';
                elsif (((ps_in + 1) * period_orig / 256) > period_orig + FINE_SHIFT_RANGE) then
                  ps_overflow_out <= '1';
                else
                  ps_in := ps_in + 1;
                  ps_delay <= (ps_in * period_div / 256);
                  ps_overflow_out <= '0';
                end if;
                ps_lock <= '1';                
              elsif (PSINCDEC_dly = '0') then
                if (ps_in = ps_min) then
                  ps_overflow_out <= '1';
                elsif ((period_orig > FINE_SHIFT_RANGE) and (((ps_in - 1) * period_orig / 256) < period_orig - FINE_SHIFT_RANGE)) then
                  ps_overflow_out <= '1';
                else
                  ps_in := ps_in - 1;
                  ps_delay <= (ps_in * period_div / 256);
                  ps_overflow_out <= '0';
                end if;
                ps_lock <= '1';                                
              end if;
            end if;
          end if;
        end if;
      end if;

      if (rising_edge(PSCLK_dly)) then
        if (ps_type = 5) then
          if (PSEN_dly = '1') then
            if (ps_lock = '1') then
              Write ( Message, string'(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift. "));
              assert false report Message.all severity warning;
              DEALLOCATE (Message);              
            else
              if (PSINCDEC_dly = '1') then
                if (ps_in = ps_max) then
                  ps_overflow_out <= '1';
                elsif (ps_in * tap_delay_step > FINE_SHIFT_RANGE) then
                  ps_overflow_out <= '1';
                else
                  ps_in := ps_in + 1;
                  ps_delay <= ps_in * tap_delay_step;
                  ps_overflow_out <= '0';
                end if;
                ps_lock <= '1';                
              elsif (PSINCDEC_dly = '0') then
                if (ps_in = ps_min) then
                  ps_overflow_out <= '1';
                elsif (ps_in * tap_delay_step > FINE_SHIFT_RANGE) then
                  ps_overflow_out <= '1';
                else
                  ps_in := ps_in - 1;
                  ps_delay <= ps_in * tap_delay_step;
                  ps_overflow_out <= '0';
                end if;
                ps_lock <= '1';                                
              end if;
            end if;
          end if;
        end if;
      end if;

      if (rising_edge(clkin_ps)) then
        if (ps_type = 5) then      
          if (ps_drp_lock = '1') then
            if (inc_dec = '1') then
              if (ps_in < ps_in_drp) then
                if (single_step_lock = '0')  then                
                  single_step_lock := '1';
                  ps_in := ps_in + 1;
                  ps_delay <= ps_delay + tap_delay_step;            
                end if;
              elsif (ps_in = ps_in_drp) then
                ps_drp_lock <= '0';
              end if;
            elsif (inc_dec = '0') then
              if (ps_in > ps_in_drp) then              
                if (single_step_lock = '0')  then
                  single_step_lock := '1';
                  ps_in := ps_in - 1;
                  ps_delay <= ps_delay - tap_delay_step;            
                end if;
              elsif (ps_in = ps_in_drp) then
                ps_drp_lock <= '0';
              end if;                
            end if;  
          end if;
        end if;
      end if;
    end if;      

    ps_in_current <= ps_in;    
    if (falling_edge(psdone_out)) then
      ps_lock <= '0';
    end if;

    if (single_step_lock = '1') then
      wait until (rising_edge(clkin_ps));
      wait until (rising_edge(clkin_ps));
      wait until (rising_edge(clkin_ps));
      wait until (rising_edge(clkin_ps));
      single_step_lock := '0';         
    end if;

    if (rising_edge(ps_kick_off_cmd)) then
      wait until (rising_edge(DCLK_dly));
      wait until (rising_edge(DCLK_dly));
      wait until (rising_edge(clkin_ps));
      wait until (rising_edge(clkin_ps));
      wait until (rising_edge(clkin_ps));
      wait until (rising_edge(clkin_ps));
      wait until (rising_edge(clkin_ps));
      wait until (rising_edge(clkin_ps));
      ps_drp_lock <= '1';
    end if;
   wait on clkin_ps, lock_period, lock_period_pulse, PSCLK_dly, rst_ipd, ps_kick_off_cmd, psdone_out;
  end process determine_phase_shift;


  drive_psdone_out : process
  begin
   if (ps_type /= 0 and ps_type /= 1) then
    if (rising_edge(ps_lock)) then
      wait until (rising_edge(clkin_ps));
      wait until (rising_edge(clkin_ps));
      wait until (rising_edge(clkin_ps));      
      wait until (rising_edge(clkin_ps));
      wait until (rising_edge(psclk_dly));
      wait until (rising_edge(psclk_dly));
      psdone_out <= '1';
      wait until (rising_edge(psclk_dly));
      psdone_out <= '0';
    end if;    

    if (falling_edge(ps_drp_lock)) then
        if (ps_type = 5) then
          wait until (rising_edge(clkin_ps));
          wait until (rising_edge(clkin_ps));
          wait until (rising_edge(clkin_ps));
          wait until (rising_edge(clkin_ps));          
          wait until (rising_edge(PSCLK_dly));
          wait until (rising_edge(PSCLK_dly));
          psdone_out <= '1';
          wait until (rising_edge(PSCLK_dly));
          psdone_out <= '0';
        end if;
      end if;    
   end if;
   wait on ps_lock, ps_drp_lock;
  end process drive_psdone_out;

--
--determine clock period
--    
  process (period_orig) begin
     period_stop_ck <= period_orig * clock_stopped_factor;
  end process;

  determine_clock_period : process(clkin_div, rst_ipd)
    variable clkin_edge_previous : time := 0 ps; 
    variable clkin_edge_current : time := 0 ps;
  begin
    if  (rst_ipd = '1') then
      clkin_period_real(0) <= 0 ps;
      clkin_period_real(1) <= 0 ps;
      clkin_period_real(2) <= 0 ps;
      clkin_edge_previous := 0 ps;      
      clkin_edge_current := 0 ps;            
    elsif (rising_edge(clkin_div)) then
      clkin_edge_previous := clkin_edge_current;
      clkin_edge_current := NOW;
      clkin_period_real(2) <= clkin_period_real(1);
      clkin_period_real(1) <= clkin_period_real(0);      
      if (clkin_edge_previous /= 0 ps) then
	clkin_period_real(0) <= clkin_edge_current - clkin_edge_previous;
      end if;
    elsif (falling_edge(clkin_div) ) then
      if (lock_period = '1') then
        if (100000000 ps < clkin_period_real(0)/1000) then
        elsif ((period_stop_ck <= clkin_period_real(0)) and (clock_stopped = '0')) then
          clkin_period_real(0) <= clkin_period_real(1);              
        end if;
     end if;
    end if;
  end process determine_clock_period;
  
  evaluate_clock_period : process
    variable Message : line;
  begin
    if  (rst_ipd = '1') then
      lock_period <= '0';
      clock_stopped <= '1';
    elsif (falling_edge(clkin_div) ) then
        if (lock_period = '0') then
          if ((clkin_period_real(0) /= 0 ps ) and (clkin_period_real(0) - cycle_jitter <= clkin_period_real(1)) and (clkin_period_real(1) <= clkin_period_real(0) + cycle_jitter) and (clkin_period_real(1) - cycle_jitter <= clkin_period_real(2)) and (clkin_period_real(2) <= clkin_period_real(1) + cycle_jitter)) then
            lock_period <= '1';
            period_orig <= (clkin_period_real(0) + clkin_period_real(1) + clkin_period_real(2)) / 3;
            period <= clkin_period_real(0);
          end if;
        elsif (lock_period = '1') then
          if (100000000 ns < clkin_period_real(0)) then
            Write ( Message, string'(" Warning : CLKIN stopped toggling on instance "));
            Write ( Message, Instancepath );          
            Write ( Message, string'(" exceeds "));
            Write ( Message, string'(" 100 ms "));
            Write ( Message, string'(" Current CLKIN Period = "));
            Write ( Message,  clkin_period_real(0));
            assert false report Message.all severity warning;
            DEALLOCATE (Message);
            lock_period <= '0';
            wait until (falling_edge(rst_reg(2)));            
          elsif ((period_stop_ck <= clkin_period_real(0)) and (clock_stopped = '0')) then
              clock_stopped <= '1';
          elsif ((clkin_period_real(0) < period_orig - period_jitter) or (period_orig + period_jitter < clkin_period_real(0))) then
          Write ( Message, string'(" Warning : Input Clock Period Jitter on instance "));
          Write ( Message, Instancepath );          
            Write ( Message, string'(" exceeds "));
            Write ( Message, period_jitter );
            Write ( Message, string'(" Locked CLKIN Period =  "));
            Write ( Message, period_orig );
            Write ( Message, string'(" Current CLKIN Period =  "));
            Write ( Message, clkin_period_real(0) );
            assert false report Message.all severity warning;
            DEALLOCATE (Message);
            lock_period <= '0';
            wait until (falling_edge(rst_reg(2)));                                  
          elsif ((clkin_period_real(0) < clkin_period_real(1) - cycle_jitter) or (clkin_period_real(1) + cycle_jitter < clkin_period_real(0))) then
          Write ( Message, string'(" Warning : Input Clock Cycle Jitter on on instance "));
          Write ( Message, Instancepath );
            Write ( Message, string'(" exceeds "));
            Write ( Message, cycle_jitter );
            Write ( Message, string'(" Previous CLKIN Period =  "));
            Write ( Message, clkin_period_real(1) );
            Write ( Message, string'(" Current CLKIN Period =  "));
            Write ( Message, clkin_period_real(0) );                    
            assert false report Message.all severity warning;
            DEALLOCATE (Message);
            lock_period <= '0';
            wait until (falling_edge(rst_reg(2)));
          else           
            period <= clkin_period_real(0);
            clock_stopped <= '0';
          end if;
        end if;  
    end if;
    wait on clkin_div, rst_ipd;
  end process evaluate_clock_period;

  period_cal_p : process(period) 
        variable period_25_tmp : time := 0 ps;
  begin
        period_25_tmp := period / 4;
        period_50 <= 2 * period_25_tmp;
        period_25 <= period_25_tmp;
  end process;

  lock_period_dly <= transport lock_period after period_50;

  lock_period_pulse <= '1' when ((lock_period = '1') and (lock_period_dly = '0')) else '0';    

--
--determine clock delay
--  
  
  determine_clock_delay : process
    variable delay_edge : time := 0 ps;
    variable temp1 : integer := 0;
    variable temp2 : integer := 0;        
    variable temp : integer := 0;
    variable delay_edge_current : time := 0 ps;    
  begin
    if (rst_ipd = '1') then
      fb_delay <= 0 ps;      
      fb_delay_found <= '0';                        
    elsif (rising_edge(lock_ps_dly)) then
        if  ((lock_period = '1') and (clkfb_type /= 0)) then
          if (clkfb_type = 1) then
            wait until ((rising_edge(clk0_sig)) or (rst_ipd'event));                                
            delay_edge := NOW;
          elsif (clkfb_type = 2) then
            wait until ((rising_edge(clk2x_sig)) or (rst_ipd'event));            
            delay_edge := NOW;
          end if;
          wait until ((rising_edge(clkfb_ipd)) or (rst_ipd'event));          
          temp1 := ((NOW*1) - (delay_edge*1))/ (1 ps);
          temp2 := (period_orig * 1)/ (1 ps);
          temp := temp1 mod temp2;
          fb_delay <= temp * 1 ps;
          fb_delay_found <= '1';          
        end if;
    end if;
    wait on lock_ps_dly, rst_ipd;
  end process determine_clock_delay;
--
--  determine feedback lock
--  
  GEN_CLKFB_WINDOW : process
  begin
    if  (rst_ipd = '1') then
      clkfb_window <= '0';  
    elsif (rising_edge(CLKFB_ipd)) then
        wait for 0 ps;
        clkfb_window <= '1';
        wait for cycle_jitter;        
        clkfb_window <= '0';
    end if;      
    wait on clkfb_ipd, rst_ipd;
  end process GEN_CLKFB_WINDOW;

  GEN_CLKIN_WINDOW : process
  begin
    if  (rst_ipd = '1') then
      clkin_window <= '0';
    elsif (rising_edge(clkin_fb)) then
        wait for 0 ps;
        clkin_window <= '1';
        wait for cycle_jitter;        
        clkin_window <= '0';
    end if;      
    wait on clkin_fb, rst_ipd;
  end process GEN_CLKIN_WINDOW;  

  set_reset_lock_clkin : process
  begin
    if  (rst_ipd = '1') then
      lock_clkin <= '0';                  
    elsif (rising_edge(clkin_fb)) then
        wait for 1 ps;
        if (((clkfb_window = '1') and (fb_delay_found = '1')) or ((clkin_lost_out = '1') and (lock_out(0) = '1'))) then
          lock_clkin <= '1';
        else
--          if (chk_enable = '1') then          
          if (chk_enable = '1' and ps_lock = '0') then          
            lock_clkin <= '0';
          end if;
        end if;
    end if;
    wait on clkin_fb, rst_ipd;
  end process set_reset_lock_clkin;

  set_reset_lock_clkfb : process
  begin
    if  (rst_ipd = '1') then
      lock_clkfb <= '0';                  
    elsif (rising_edge(clkfb_ipd)) then
        wait for 1 ps;
        if (((clkin_window = '1') and (fb_delay_found = '1')) or ((clkin_lost_out = '1') and (lock_out(0) = '1'))) then
          lock_clkfb <= '1';
        else
--          if (chk_enable = '1') then                    
          if (chk_enable = '1' and ps_lock = '0') then                    
            lock_clkfb <= '0';
          end if;
        end if;
    end if;          
    wait on clkfb_ipd, rst_ipd;
  end process set_reset_lock_clkfb;

  assign_lock_delay : process(clkin_fb, rst_ipd)
  begin
    if (rst_ipd = '1') then
      lock_delay <= '0';          
    elsif (falling_edge(clkin_fb)) then
        lock_delay <= lock_clkin or lock_clkfb;
    end if;
  end process;

--
--generate lock signal
--  
  
  
  generate_lock : process(clkin_ps, rst_ipd)
  begin
    if (rst_ipd='1') then
      lock_out <= "00";
      locked_out <= '0';      
      lock_out1_neg <= '0';
    elsif (rising_edge(clkin_ps)) then
        if (clkfb_type = 0) then
          lock_out(0) <= lock_period;
        else
          lock_out(0) <= lock_period and lock_delay and lock_fb;
        end if;                           
        lock_out(1) <= lock_out(0);
        locked_out <= lock_out(1);          
    elsif (falling_edge(clkin_ps)) then
        lock_out1_neg <= lock_out(1);
    end if;
  end process generate_lock;

  locked_out_tmp <= locked_out after period_fx;
  locked_pulse <= '1' when ((locked_out = '1') and (locked_out_tmp = '0')) else '0';  


--
--generate the clk1x_out
--  
  
  gen_clk1x : process (clkin_ps, rst_ipd)
  begin
    if (rst_ipd = '1') then
        clk0_out <= '0';
    elsif (rising_edge(clkin_ps)) then
        if ((clk1x_type = 1) and (lock_out(0) = '1')) then
          clk0_out <= '1', '0' after period/2;
        else
          clk0_out <= '1';
        end if;
    elsif (falling_edge(clkin_ps)) then
        if ((((clk1x_type = 1) and (lock_out(0) = '1')) = false) or ((lock_out(0) = '1') and (lock_out(1) = '0'))) then        
          clk0_out <= '0';
        end if;
    end if;
  end process gen_clk1x;

--
--generate the clk2x_out
--    

  gen_clk2x : process 
  begin
    if (rst_ipd='1') then
       clk2x_out <= '0';
    elsif (rising_edge(clkin_ps)) then
      clk2x_out <= '1';
      wait for period_25;
      clk2x_out <= '0';
      if (lock_out(0) = '1') then
        wait for period_25;
        clk2x_out <= '1';
        wait for period_25;
        clk2x_out <= '0';
      else
        wait for period_50;
      end if;
    end if;
    wait on clkin_ps, rst_ipd;
  end process gen_clk2x;
  
-- 
--generate the clkdv_out
-- 

  gen_clkdv : process (clkin_ps, rst_ipd)
  begin
    if (rst_ipd='1') then
       clkdv_out <= '0';
       clkdv_cnt <= 0;
    elsif ((rising_edge(clkin_ps)) or (falling_edge(clkin_ps))) then
      if (lock_out1_neg = '1') then
         if (clkdv_cnt >= divide_type -1) then
           clkdv_cnt <= 0;
         else
           clkdv_cnt <= clkdv_cnt + 1;
         end if;

         if (clkdv_cnt < divide_type /2) then
            clkdv_out <= '1';
         else
           if ( ((divide_type rem (2)) > 0) and (dll_mode_type = "00")) then
             clkdv_out <= '0' after (period/4);
           else
            clkdv_out <= '0';
           end if;
         end if;
      end if;
    end if;
  end process;


  determine_clkfx_divide_multiply : process(rst_ipd, clkfx_multiply_drp, clkfx_divide_drp)
  begin
      if (rst_ipd = '1') then    
        numerator <= clkfx_multiply_drp;
        denominator <= clkfx_divide_drp;
      end if;
  end process determine_clkfx_divide_multiply;

--
-- generate fx output signal
--
  
  calculate_period_fx : process(lock_period, period)
  begin
    if (lock_period = '1') then
      period_fx <= (period * denominator) / (numerator * 2);
      remain_fx <= (((period/1 ps) * denominator) mod (numerator * 2)) * 1 ps;        
    end if;
  end process calculate_period_fx;

  
  generate_clkfx : process
     variable temp : integer;    
  begin
     if (rst_ipd = '1') then
       clkfx_out <= '0';
     elsif (clkin_lost_out_ext = '1') then
       if (locked_out = '1') then
         wait until (falling_edge(rst_reg(2)));  
       end if;
     elsif (rising_edge(clkin_ps)) then
       if (lock_out(1) = '1') then
         clkfx_out <= '1';
         temp := numerator * 2 - 1 - 1;
         for p in 0 to temp loop
           wait for (period_fx);
           clkfx_out <= not clkfx_out;
         end loop;
         if (period_fx > (period / 2)) then
           wait for (period_fx - (period / 2));
         end if;
       end if;
       if (clkin_lost_out_ext = '1') then
         wait until (rising_edge(rst_ipd));
         clkfx_out <= '0';      
         wait until (falling_edge(rst_reg(2)));
       end if;              
     end if;
     wait on clkin_lost_out_ext, clkin_ps, rst_ipd, rst_reg(2);
  end process generate_clkfx;

  detect_first_time_locked : process
    begin
      if (first_time_locked = false) then
        if (rising_edge(locked_out)) then
          first_time_locked <= true;
        end if;        
      end if;
      wait on locked_out;
  end process detect_first_time_locked;  

  control_status_bits: process(clkfb_lost_out, clkfx_lost_out, clkin_lost_out, en_status, ps_overflow_out, rst_ipd)
  begin  
    if ((rst_ipd = '1') or (en_status = false)) then
      ps_overflow_out_ext <= '0';
      clkin_lost_out_ext <= '0';
      clkfx_lost_out_ext <= '0';
      clkfb_lost_out_ext <= '0';      
    else
      ps_overflow_out_ext <= ps_overflow_out;
      clkin_lost_out_ext <= clkin_lost_out;
      clkfx_lost_out_ext <= clkfx_lost_out;
      clkfb_lost_out_ext <= clkfb_lost_out;      
    end if;
  end process  control_status_bits;      

  do_out_s(0) <= ps_overflow_out_ext;
  do_out_s(1) <= clkin_lost_out_ext;
  do_out_s(2) <= clkfx_lost_out_ext;
  do_out_s(3) <= clkfb_lost_out_ext;            

  set_reset_en_status : process (locked_out, rst_ipd)
  begin
    if (rst_ipd='1') then
      en_status <= false;
    elsif (rising_edge(locked_out)) then
      en_status <= true;
    end if;
  end process set_reset_en_status;

  set_reset_clkin_chkin : process (clkin_fb, chk_rst)
  begin
    if (chk_rst='1') then
       clkin_chkin <= '0';
    elsif (rising_edge(clkin_fb)) then
       clkin_chkin <= '1';
    end if;
  end process set_reset_clkin_chkin;

  set_reset_clkfb_chkin : process(clkfb_ipd, chk_rst)
  begin
    if (chk_rst='1') then
       clkfb_chkin <= '0';
    elsif (rising_edge(clkfb_ipd)) then
       clkfb_chkin <= '1';
    end if;
  end process set_reset_clkfb_chkin;

  chk_rst <= '1' when ((rst_ipd = '1') or (clock_stopped = '1')) else '0';
  chk_enable <= '1' when ((clkin_chkin = '1') and (clkfb_chkin = '1') and (lock_ps = '1') and (lock_fb = '1')) else '0';      


   do_out <= do_out_drp1 when (do_stat_en = '0') else do_out_s;

    drp : process
    variable first_time : boolean := true;
    variable address : integer;
    variable valid_daddr : boolean := false;
    variable ps_drp : integer := 0;
    variable  dfs_mode_type_i : std_ulogic;
    variable  clkin_type_i : std_ulogic;
    variable  dll_mode_type_i : std_logic_vector(1 downto 0);
    variable  clkfx_m_reg : std_logic_vector(7 downto 0);
    variable  clkfx_d_reg : std_logic_vector(7 downto 0);

    variable Message : line;    

  begin
      if (first_time = true) then
        clkfx_multiply_drp <= CLKFX_MULTIPLY;
        clkfx_divide_drp <= CLKFX_DIVIDE;
        clkfx_m_reg := STD_LOGIC_VECTOR(TO_UNSIGNED(CLKFX_MULTIPLY, 8));
        clkfx_d_reg := STD_LOGIC_VECTOR(TO_UNSIGNED(CLKFX_DIVIDE, 8));
        clkfx_md_reg <= (clkfx_m_reg & clkfx_d_reg);
        if (DFS_FREQUENCY_MODE = "HIGH") then
            dfs_mode_type_i := '1';
            dfs_mode_type <= '1';
        else
            dfs_mode_type_i := '0';
            dfs_mode_type <= '0';
        end if;
        if (DLL_FREQUENCY_MODE = "HIGH") then
            dll_mode_type_i := "11";
            dll_mode_type <= "11";
        else
            dll_mode_type_i := "00";
            dll_mode_type <= "00";
        end if;
        if (CLKIN_DIVIDE_BY_2 = TRUE) then
            clkin_type_i := '1';
            clkin_type <= '1';
        else
            clkin_type_i := '0';
            clkin_type <= '0';
        end if;
        dfs_mode_reg <= ("XXXXXXXXXXXXX" & dfs_mode_type_i & "XX");
        dll_mode_reg <= ("XXXXXXXXXXXX" & dll_mode_type_i & "XX");
        clkin_div2_reg <= ("XXXXX" & clkin_type_i & "XXXXXXXXXX");
        
        do_stat_en <= '1';
        first_time := false;
      end if;
    
    valid_daddr := addr_is_valid(DADDR_dly);
    if (valid_daddr) then
      address := slv_to_int(DADDR_dly);
    end if;
    
    if (GSR_dly = '1') then
       drp_lock <= '0';
       ps_in_drp <= 0;
       ps_kick_off_cmd <= '0';
       do_out_drp <= "0000000000000000";
       do_out_drp1 <= "0000000000000000";
       do_stat_en <= '1';
       drdy_out <= '0';
    elsif (rising_edge(DCLK_dly))  then
      if (DEN_dly = '1') then
        if (drp_lock = '1') then
          Write ( Message, string'(" Warning : DEN is high. Please wait for DRDY signal before next read/write operation through DRP. "));
          assert false report Message.all severity warning;
          DEALLOCATE (Message);              
        else
          drp_lock <= '1';
          if (DWE_dly = '0') then 
            if (valid_daddr) then
              if (SIM_DEVICE = "VIRTEX5") then
                 if (address = DCM_DEFAULT_STATUS_ADDR) then
                     do_stat_en <= '1';
                 else 
                     do_stat_en <= '0';
                     if (address  = DFS_FREQ_MODE_ADDR) then
                         do_out_drp <= dfs_mode_reg;
                     elsif (address  = DLL_FREQ_MODE_ADDR) then
                         do_out_drp <= dll_mode_reg;
                     elsif (address  = CLKFX_MULTIPLY_ADDR) then
                         do_out_drp <= clkfx_md_reg;
                     elsif (address  = CLKIN_DIV_BY2_ADDR) then
                         do_out_drp <= clkin_div2_reg;
                     else
                         do_out_drp <= "0000000000000000";
                     end if;
                 end if;
               end if;
             end if;
          end if;  -- DWE_dly = '0'

          if (DWE_dly = '1') then
            if (valid_daddr) then
              if (address = CLKFX_MULTIPLY_ADDR) then
                if (sim_device_type = '1') then
                  clkfx_divide_drp <= slv_to_int(DI_dly(7 downto 0)) + 1;
                  clkfx_multiply_drp <= slv_to_int(DI_dly(15 downto 8)) + 1;
                  clkfx_md_reg <= DI_dly;
                else 
                   clkfx_multiply_drp <= slv_to_int(DI_dly(4 downto 0)) + 1;
                end if;
              elsif (address = CLKFX_DIVIDE_ADDR and sim_device_type = '0') then
                clkfx_divide_drp <= slv_to_int(DI_dly(4 downto 0)) + 1;
              elsif (address = PHASE_SHIFT_ADDR) then
                ps_drp := slv_to_int(DI_dly(10 downto 0));
              elsif (address = PHASE_SHIFT_KICK_OFF_ADDR) then
                if (ps_kick_off_cmd = '0') then
                  ps_kick_off_cmd <= '1';
                  ps_in_drp <= ps_drp;
                  if (ps_in_current < ps_drp) then
                    inc_dec <= '1';
                  elsif (ps_in_current > ps_drp) then
                    inc_dec <= '0';
                  end if;
                end if;
             elsif ((address = DFS_FREQ_MODE_ADDR) and (sim_device_type = '1')) then
                  dfs_mode_reg <= DI_dly;
                  dfs_mode_type <= DI_dly(2);
             elsif ((address = DLL_FREQ_MODE_ADDR) and (sim_device_type = '1')) then
                  dll_mode_reg <= DI_dly;
                  dll_mode_type <= DI_dly(3 downto 2);
             elsif ((address = CLKIN_DIV_BY2_ADDR) and (sim_device_type = '1')) then
                  clkin_div2_reg <= DI_dly;
                  clkin_type <= DI_dly(10);
             else
      Write ( Message, string'(" Warning :  Address DADDR="));
      Write ( Message,  address);
      Write ( Message, string'(" on the DCM_ADV instance is unsupported") );
      Write ( Message, '.' & LF );
      assert false report Message.all severity warning;
      DEALLOCATE (Message);
              end if;
            end if;                          
          end if; -- DWE = 1
--        end if;
      end if;
    end if;        
    if (drp_lock = '1') then
         drp_lock1 <= '1';
    end if;
    if (drp_lock1 = '1') then
      drp_lock <= '0';      
      drp_lock1 <= '0';      
      drdy_out <= '1';
      do_out_drp1 <= do_out_drp;
      do_out_drp <= "0000000000000000";
    end if;
    
    if (drdy_out = '1') then
      drdy_out <= '0';
       do_out_drp1 <= "0000000000000000";
    end if;

    if (falling_edge(ps_drp_lock)) then
      if (ps_kick_off_cmd = '1') then
        ps_kick_off_cmd <= '0';  
      end if;
    end if;
  end if;  -- GSR_dly 

    wait on DCLK_dly, ps_drp_lock, GSR_dly;
    
    end process drp;


--   drive_drdy_out : process
--     begin
--     if (falling_edge(drp_lock)) then
--       wait until (rising_edge(DCLK_dly));       
--       drdy_out <= '1';
--       wait until (rising_edge(DCLK_dly));
--       drdy_out <= '0';
--     end if;      
--   wait on drp_lock;    
--   end process drive_drdy_out;

--
--generate all output signal
--

  schedule_clk0 : process(clk0_out, rst_ipd)
  begin
      if (rst_ipd = '1') then
        CLK180 <= '0';
        CLK270 <= '0';
        clk0_sig <= '0';
        CLK90 <= '0';
        CLK0 <= '0'; 
      elsif (CLK0_out'event) then
        CLK0 <= transport CLK0_out after clkout_delay;
        clk0_sig <= transport CLK0_out after clkout_delay;
        CLK90 <= transport clk0_out after (clkout_delay + period / 4);
        CLK180 <= transport clk0_out after (clkout_delay + period/2);
        CLK270 <= transport (not clk0_out) after (clkout_delay + period/4);
      end if;
  end process schedule_clk0;

  schedule_clk2x : process (CLK2X_out, rst_ipd)
  begin
    if (rst_ipd = '1') then
        CLK2X180 <= '0';
        CLK2X <= '0';
        clk2x_sig <= '0';
      elsif (clk2x_out'event) then
        CLK2X <= transport clk2x_out after clkout_delay;
        clk2x_sig <= transport clk2x_out after clkout_delay;
        CLK2X180 <= transport (not CLK2X_out) after clkout_delay;  
    end if;
  end process schedule_clk2x;

   CLKDV <= transport clkdv_out after clkout_delay;

  schedule_clkfx : process
  begin
      if (rst_ipd = '1') then
        CLKFX <= '0';
      elsif (clkfx_out'event) then
        CLKFX <= transport clkfx_out after clkout_delay;                          
      end if;

      if ((rst_ipd = '1') or (not first_time_locked)) then
        CLKFX180 <= '0';
      elsif (clkfx_out'event or (first_time_locked'event and first_time_locked = true)
             or locked_out'event) then
        CLKFX180 <= transport (not clkfx_out) after clkout_delay;  
      end if;
    wait on clkfx_out, rst_ipd, first_time_locked, locked_out;
  end process schedule_clkfx;

 
  DO <= do_out;
  locked_out_out <= 'X' when rst_flag = '1' else locked_out;

   DRDY <= drdy_out;
   LOCKED <= locked_out_out;
   PSDONE <= psdone_out;

  

end DCM_ADV_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/dcm_base.vhd,v 1.12 2007/06/01 23:03:01 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Digital Clock Manager with Basic Features
-- /___/   /\     Filename : DCM_BASE.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:03 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    08/08/05 - Add parameter DCM_AUTOCALIBRATION (CR 214040).
--    05/10/07 - Remove Vital timing.
-- End Revision

----- CELL DCM_BASE -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.VCOMPONENTS.all;
use unisim.VPKG.all;
library STD;
use STD.TEXTIO.all;

entity DCM_BASE is
generic (
  CLKDV_DIVIDE : real := 2.0;
  CLKFX_DIVIDE : integer := 1;
  CLKFX_MULTIPLY : integer := 4;                                
  CLKIN_DIVIDE_BY_2 : boolean := FALSE;
  CLKIN_PERIOD : real := 10.0;
  CLKOUT_PHASE_SHIFT : string := "NONE";
  CLK_FEEDBACK : string := "1X";
  DCM_AUTOCALIBRATION : boolean := TRUE;  
  DCM_PERFORMANCE_MODE : string := "MAX_SPEED";
  DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
  DFS_FREQUENCY_MODE : string := "LOW";                
  DLL_FREQUENCY_MODE : string := "LOW";
  DUTY_CYCLE_CORRECTION : boolean := TRUE;
  FACTORY_JF : bit_vector := X"F0F0";
  PHASE_SHIFT : integer := 0;
  STARTUP_WAIT : boolean := false
  );

port (
  CLK0 : out std_ulogic;
  CLK180 : out std_ulogic;
  CLK270 : out std_ulogic;
  CLK2X : out std_ulogic;
  CLK2X180 : out std_ulogic;
  CLK90 : out std_ulogic;
  CLKDV : out std_ulogic;
  CLKFX : out std_ulogic;
  CLKFX180 : out std_ulogic;
  LOCKED : out std_ulogic;
  
  CLKFB : in std_ulogic;
  CLKIN : in std_ulogic;
  RST : in std_ulogic
     );
end DCM_BASE;

-- Architecture body --

architecture DCM_BASE_V of DCM_BASE is

signal  OPEN_DRDY : std_ulogic;
signal  OPEN_PSDONE : std_ulogic;
signal  OPEN_DO : std_logic_vector(15 downto 0);

signal  GND_DADDR : std_logic_vector(6 downto 0) := "0000000";
signal  GND_DCLK : std_ulogic := '0';
signal  GND_DEN : std_ulogic := '0';
signal  GND_DI : std_logic_vector(15 downto 0) := "0000000000000000";
signal  GND_DWE : std_ulogic := '0';
signal  GND_PSCLK : std_ulogic := '0';
signal  GND_PSEN : std_ulogic := '0';
signal  GND_PSINCDEC : std_ulogic := '0';
signal  GND_RST : std_ulogic := '0';

begin

  INITPROC : process
    variable Message : line;    
  begin
    if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then
    elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLKOUT_PHASE_SHIFT",
         EntityName => "DCM_BASE",
--         InstanceName => InstancePath,
         GenericValue => CLKOUT_PHASE_SHIFT,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are NONE or FIXED",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;

    if ((CLK_FEEDBACK = "none") or (CLK_FEEDBACK = "NONE")) then
      Write ( Message, string'(" Attribute CLK_FEEDBACK is set to value NONE."));
      Write ( Message, string'(" In this mode, the output ports CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90 and  CLKDV can have any random phase relation w.r.t. input port CLKIN"));
      Write ( Message, '.' & LF );
      assert false report Message.all severity note;
      DEALLOCATE (Message);            
    elsif ((CLK_FEEDBACK = "1x") or (CLK_FEEDBACK = "1X")) then
--    elsif ((CLK_FEEDBACK = "2x") or (CLK_FEEDBACK = "2X")) then
--      clkfb_type <= 2;
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLK_FEEDBACK",
         EntityName => "DCM_BASE",
--         InstanceName => InstancePath,
         GenericValue => CLK_FEEDBACK,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are NONE or 1X",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;    
    wait;
  end process INITPROC;
  
-- DCM_ADV Instatiation (port map, generic map)
DCM_ADV_inst : DCM_ADV
  generic map (
    CLKDV_DIVIDE => CLKDV_DIVIDE,
    CLKFX_DIVIDE => CLKFX_DIVIDE,
    CLKFX_MULTIPLY => CLKFX_MULTIPLY,
    CLKIN_DIVIDE_BY_2 => CLKIN_DIVIDE_BY_2,
    CLKIN_PERIOD => CLKIN_PERIOD,
    CLKOUT_PHASE_SHIFT => CLKOUT_PHASE_SHIFT,                
    CLK_FEEDBACK => CLK_FEEDBACK,
    DCM_AUTOCALIBRATION => DCM_AUTOCALIBRATION,
    DCM_PERFORMANCE_MODE => DCM_PERFORMANCE_MODE,
    DESKEW_ADJUST => DESKEW_ADJUST,
    DFS_FREQUENCY_MODE => DFS_FREQUENCY_MODE,
    DLL_FREQUENCY_MODE => DLL_FREQUENCY_MODE,
    DUTY_CYCLE_CORRECTION => DUTY_CYCLE_CORRECTION,
    FACTORY_JF => FACTORY_JF,
    PHASE_SHIFT => PHASE_SHIFT,
    STARTUP_WAIT => STARTUP_WAIT
)
  port map (
    CLK0 => CLK0,
    CLK180 => CLK180,
    CLK270 => CLK270,
    CLK2X => CLK2X,
    CLK2X180 => CLK2X180,
    CLK90 => CLK90,
    CLKDV => CLKDV,
    CLKFX => CLKFX,
    CLKFX180 => CLKFX180,
    DO => OPEN_DO,
    DRDY => OPEN_DRDY,
    LOCKED => LOCKED,                
    PSDONE => OPEN_PSDONE,

    CLKFB => CLKFB,
    CLKIN => CLKIN,
    DADDR => GND_DADDR,
    DCLK => GND_DCLK,
    DEN => GND_DEN,
    DI => GND_DI,
    DWE => GND_DWE,
    PSCLK => GND_PSCLK,
    PSEN => GND_PSEN,
    PSINCDEC => GND_PSINCDEC,
    RST => RST
    );

end DCM_BASE_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/dcm_ps.vhd,v 1.12 2007/06/01 23:03:01 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Digital Clock Manager with Basic and Phase Shift Features
-- /___/   /\     Filename : DCM_PS.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:03 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    08/08/05 - Add parameter DCM_AUTOCALIBRATION (CR 214040).
--    05/10/07 - Remove Vital timing.
-- End Revision
----- CELL DCM_PS -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.VCOMPONENTS.all;
use unisim.VPKG.all;
library STD;
use STD.TEXTIO.all;

entity DCM_PS is
generic (
		CLKDV_DIVIDE : real := 2.0;
		CLKFX_DIVIDE : integer := 1;
		CLKFX_MULTIPLY : integer := 4;
		CLKIN_DIVIDE_BY_2 : boolean := FALSE;
		CLKIN_PERIOD : real := 10.0;
		CLKOUT_PHASE_SHIFT : string := "NONE";
		CLK_FEEDBACK : string := "1X";                
                DCM_AUTOCALIBRATION : boolean := TRUE;  
		DCM_PERFORMANCE_MODE : string := "MAX_SPEED";
		DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
		DFS_FREQUENCY_MODE : string := "LOW";
		DLL_FREQUENCY_MODE : string := "LOW";
		DUTY_CYCLE_CORRECTION : boolean := TRUE;
                FACTORY_JF : bit_vector := X"F0F0";                 --non-simulatable                
		PHASE_SHIFT : integer := 0;
		STARTUP_WAIT : boolean := FALSE
  );

port (
		CLK0 : out std_ulogic;
		CLK180 : out std_ulogic;
		CLK270 : out std_ulogic;
		CLK2X : out std_ulogic;
		CLK2X180 : out std_ulogic;
		CLK90 : out std_ulogic;
		CLKDV : out std_ulogic;
		CLKFX : out std_ulogic;
		CLKFX180 : out std_ulogic;
		DO : out std_logic_vector(15 downto 0);
		LOCKED : out std_ulogic;
		PSDONE : out std_ulogic;

		CLKFB : in std_ulogic;
		CLKIN : in std_ulogic;
		PSCLK : in std_ulogic;
		PSEN : in std_ulogic;
		PSINCDEC : in std_ulogic;
		RST : in std_ulogic
     );
end DCM_PS;

-- Architecture body --

architecture DCM_PS_V of DCM_PS is

signal  OPEN_DRDY : std_ulogic;

begin

  INITPROC : process
    variable Message : line;    
  begin


    if ((CLK_FEEDBACK = "none") or (CLK_FEEDBACK = "NONE")) then
      Write ( Message, string'(" Attribute CLK_FEEDBACK is set to value NONE."));
      Write ( Message, string'(" In this mode, the output ports CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90 and  CLKDV can have any random phase relation w.r.t. input port CLKIN"));
      Write ( Message, '.' & LF );
      assert false report Message.all severity note;
      DEALLOCATE (Message);            
    elsif ((CLK_FEEDBACK = "1x") or (CLK_FEEDBACK = "1X")) then
--    elsif ((CLK_FEEDBACK = "2x") or (CLK_FEEDBACK = "2X")) then
--      clkfb_type <= 2;
    else
      GenericValueCheckMessage
        (HeaderMsg => "Attribute Syntax Error",
         GenericName => "CLK_FEEDBACK",
         EntityName => "DCM_PS",
--         InstanceName => InstancePath,
         GenericValue => CLK_FEEDBACK,
         Unit => "",
         ExpectedValueMsg => "Legal Values for this attribute are NONE or 1X",
         ExpectedGenericValue => "",
         TailMsg => "",
         MsgSeverity => error
         );
    end if;    
    wait;
  end process INITPROC;
  
-- DCM_ADV Instatiation (port map, generic map)
DCM_ADV_inst : DCM_ADV
	generic map (
		CLKDV_DIVIDE => CLKDV_DIVIDE,
		CLKFX_DIVIDE => CLKFX_DIVIDE,
		CLKFX_MULTIPLY => CLKFX_MULTIPLY,
		CLKIN_DIVIDE_BY_2 => CLKIN_DIVIDE_BY_2,
		CLKIN_PERIOD => CLKIN_PERIOD,
		CLKOUT_PHASE_SHIFT => CLKOUT_PHASE_SHIFT,
		CLK_FEEDBACK => CLK_FEEDBACK,
                DCM_AUTOCALIBRATION => DCM_AUTOCALIBRATION,
		DCM_PERFORMANCE_MODE => DCM_PERFORMANCE_MODE,
		DESKEW_ADJUST => DESKEW_ADJUST,
		DFS_FREQUENCY_MODE => DFS_FREQUENCY_MODE,
		DLL_FREQUENCY_MODE => DLL_FREQUENCY_MODE,
		DUTY_CYCLE_CORRECTION => DUTY_CYCLE_CORRECTION,
                FACTORY_JF => FACTORY_JF,
		PHASE_SHIFT => PHASE_SHIFT,
		STARTUP_WAIT => STARTUP_WAIT
)
port map (
  		DRDY => OPEN_DRDY,
		CLKIN => CLKIN,
		CLKFB => CLKFB,
		RST => RST,
		PSINCDEC => PSINCDEC,
		PSEN => PSEN,
		PSCLK => PSCLK,                

		CLK0 => CLK0,
		CLK90 => CLK90,
		CLK180 => CLK180,
		CLK270 => CLK270,
		CLK2X => CLK2X,
		CLK2X180 => CLK2X180,
		CLKDV => CLKDV,
		CLKFX => CLKFX,
		CLKFX180 => CLKFX180,
		LOCKED => LOCKED,
		PSDONE => PSDONE,
		DO => DO
);

end DCM_PS_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                  18X18 Signed Multiplier Followed by Three-Input Adder with Pipeline Registers
-- /___/   /\     Filename : DSP48.vhd
-- \   \  /  \    Timestamp : Fri Mar 26 08:18:19 PST 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    05/25/05 - CR 204870 changed all bit_vector message calls to strings.
--    06/30/05 - CR 210790 fixed CheckEnabled in Vital so that timing.
--               violation are not reported when global GSR_dly = 1.
--    01/17/06 - CR 224235 CECARRYIN, CECINSUB fasle hold violation fix.
--    02/28/06 - CR 225886 -- LEGACY_MODE check updates.
--    06/30/06 - CR 234078 -- Fixed False Timing error on RSTCARRYIN
--    08/21/06 - CR 232521 -- fixed DRC check to allow "0010101_11"
--    02/06/08 - CR 455601 -- DRC relax for OPMODEREG/CARRYINSELREG
-- End Revision
----- CELL DSP48 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_SIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;

library STD;
use STD.TEXTIO.all;


library unisim;
use unisim.vpkg.all;

entity DSP48 is

  generic(

        AREG            : integer       := 1;
        B_INPUT         : string        := "DIRECT";
        BREG            : integer       := 1;
        CARRYINREG      : integer       := 1;
        CARRYINSELREG   : integer       := 1;
        CREG            : integer       := 1;
        LEGACY_MODE     : string        := "MULT18X18S";
        MREG            : integer       := 1;
        OPMODEREG       : integer       := 1;
        PREG            : integer       := 1;
        SUBTRACTREG     : integer       := 1
        );

  port(
        BCOUT                   : out std_logic_vector(17 downto 0);
        P                       : out std_logic_vector(47 downto 0);
        PCOUT                   : out std_logic_vector(47 downto 0);

        A                       : in  std_logic_vector(17 downto 0);
        B                       : in  std_logic_vector(17 downto 0);
        BCIN                    : in  std_logic_vector(17 downto 0);
        C                       : in  std_logic_vector(47 downto 0);
        CARRYIN                 : in  std_ulogic;
        CARRYINSEL              : in  std_logic_vector(1 downto 0);
        CEA                     : in  std_ulogic;
        CEB                     : in  std_ulogic;
        CEC                     : in  std_ulogic;
        CECARRYIN               : in  std_ulogic;
        CECINSUB                : in  std_ulogic;
        CECTRL                  : in  std_ulogic;
        CEM                     : in  std_ulogic;
        CEP                     : in  std_ulogic;
        CLK                     : in  std_ulogic;
        OPMODE                  : in  std_logic_vector(6 downto 0);
        PCIN                    : in  std_logic_vector(47 downto 0);
        RSTA                    : in  std_ulogic;
        RSTB                    : in  std_ulogic;
        RSTC                    : in  std_ulogic;
        RSTCARRYIN              : in  std_ulogic;
        RSTCTRL                 : in  std_ulogic;
        RSTM                    : in  std_ulogic;
        RSTP                    : in  std_ulogic;
        SUBTRACT                : in  std_ulogic
      );

end DSP48;

-- architecture body                    --

architecture DSP48_V of DSP48 is

    procedure invalid_opmode_preg_msg( OPMODE : IN string ; 
                                   CARRYINSEL : IN string ) is
    variable Message : line;
    begin
       Write ( Message, string'("OPMODE Input Warning : The OPMODE "));
       Write ( Message,  OPMODE);
       Write ( Message, string'(" with CARRYINSEL "));
       Write ( Message,  CARRYINSEL);
       Write ( Message, string'(" to DSP48 instance "));
       Write ( Message, string'("requires attribute PREG set to 1."));
       assert false report Message.all severity Warning;
       DEALLOCATE (Message);
    end invalid_opmode_preg_msg;

    procedure invalid_opmode_mreg_msg( OPMODE : IN string ; 
                                   CARRYINSEL : IN string ) is
    variable Message : line;
    begin
       Write ( Message, string'("OPMODE Input Warning : The OPMODE "));
       Write ( Message,  OPMODE);
       Write ( Message, string'(" with CARRYINSEL "));
       Write ( Message,  CARRYINSEL);
       Write ( Message, string'(" to DSP48 instance "));
       Write ( Message, string'("requires attribute MREG set to 1."));
       assert false report Message.all severity Warning;
       DEALLOCATE (Message);
    end invalid_opmode_mreg_msg;

    procedure invalid_opmode_no_mreg_msg( OPMODE : IN string ; 
                                      CARRYINSEL : IN string ) is
    variable Message : line;
    begin
       Write ( Message, string'("OPMODE Input Warning : The OPMODE "));
       Write ( Message,  OPMODE);
       Write ( Message, string'(" with CARRYINSEL "));
       Write ( Message,  CARRYINSEL);
       Write ( Message, string'(" to DSP48 instance "));
       Write ( Message, string'("requires attribute MREG set to 0."));
       assert false report Message.all severity Warning;
       DEALLOCATE (Message);
    end invalid_opmode_no_mreg_msg;




  constant SYNC_PATH_DELAY : time := 100 ps;

  constant MAX_P          : integer    := 48;
  constant MAX_PCIN       : integer    := 48;
  constant MAX_OPMODE     : integer    := 7;
  constant MAX_BCIN       : integer    := 18;
  constant MAX_B          : integer    := 18;
  constant MAX_A          : integer    := 18;
  constant MAX_C          : integer    := 48;

  constant MSB_PCIN       : integer    := 47;
  constant MSB_OPMODE     : integer    := 6;
  constant MSB_BCIN       : integer    := 17;
  constant MSB_B          : integer    := 17;
  constant MSB_A          : integer    := 17;
  constant MSB_C          : integer    := 47;
  constant MSB_CARRYINSEL : integer    := 1;

  constant MSB_P          : integer    := 47;
  constant MSB_PCOUT      : integer    := 47;
  constant MSB_BCOUT      : integer    := 17;

  constant SHIFT_MUXZ     : integer    := 17;

  signal 	A_ipd		: std_logic_vector(MSB_A downto 0) := (others => '0');
  signal 	B_ipd		: std_logic_vector(MSB_B downto 0) := (others => '0');
  signal 	BCIN_ipd	: std_logic_vector(MSB_BCIN downto 0) := (others => '0');
  signal 	C_ipd		: std_logic_vector(MSB_C downto 0)    := (others => '0');
  signal 	CARRYIN_ipd	: std_ulogic := '0';
  signal 	CARRYINSEL_ipd	: std_logic_vector(MSB_CARRYINSEL downto 0)  := (others => '0');
  signal 	CEA_ipd		: std_ulogic := '0';
  signal 	CEB_ipd		: std_ulogic := '0';
  signal 	CEC_ipd		: std_ulogic := '0';
  signal 	CECARRYIN_ipd	: std_ulogic := '0';
  signal 	CECINSUB_ipd	: std_ulogic := '0';
  signal 	CECTRL_ipd	: std_ulogic := '0';
  signal 	CEM_ipd		: std_ulogic := '0';
  signal 	CEP_ipd		: std_ulogic := '0';
  signal 	CLK_ipd		: std_ulogic := '0';
  signal GSR            : std_ulogic := '0';
  signal 	GSR_ipd		: std_ulogic := '0';
  signal 	OPMODE_ipd	: std_logic_vector(MSB_OPMODE downto 0)  := (others => '0');
  signal 	PCIN_ipd	: std_logic_vector(MSB_PCIN downto 0) := (others => '0');
  signal 	RSTA_ipd	: std_ulogic := '0';
  signal 	RSTB_ipd	: std_ulogic := '0';
  signal 	RSTC_ipd	: std_ulogic := '0';
  signal 	RSTCARRYIN_ipd	: std_ulogic := '0';
  signal 	RSTCTRL_ipd	: std_ulogic := '0';
  signal 	RSTM_ipd	: std_ulogic := '0';
  signal 	RSTP_ipd	: std_ulogic := '0';
  signal 	SUBTRACT_ipd	: std_ulogic := '0';

  signal 	A_dly		: std_logic_vector(MSB_A downto 0) := (others => '0');
  signal 	B_dly		: std_logic_vector(MSB_B downto 0) := (others => '0');
  signal 	BCIN_dly	: std_logic_vector(MSB_BCIN downto 0) := (others => '0');
  signal 	C_dly		: std_logic_vector(MSB_C downto 0) := (others => '0');
  signal 	CARRYIN_dly	: std_ulogic := '0';
  signal 	CARRYINSEL_dly	: std_logic_vector(MSB_CARRYINSEL downto 0)  := (others => '0');
  signal 	CEA_dly		: std_ulogic := '0';
  signal 	CEB_dly		: std_ulogic := '0';
  signal 	CEC_dly		: std_ulogic := '0';
  signal 	CECARRYIN_dly	: std_ulogic := '0';
  signal 	CECINSUB_dly	: std_ulogic := '0';
  signal 	CECTRL_dly	: std_ulogic := '0';
  signal 	CEM_dly		: std_ulogic := '0';
  signal 	CEP_dly		: std_ulogic := '0';
  signal 	CLK_dly		: std_ulogic := '0';
  signal 	GSR_dly		: std_ulogic := '0';
  signal 	OPMODE_dly	: std_logic_vector(MSB_OPMODE downto 0)  := (others => '0');
  signal 	PCIN_dly	: std_logic_vector(MSB_PCIN downto 0)     := (others => '0');
  signal 	RSTA_dly	: std_ulogic := '0';
  signal 	RSTB_dly	: std_ulogic := '0';
  signal 	RSTC_dly	: std_ulogic := '0';
  signal 	RSTCARRYIN_dly	: std_ulogic := '0';
  signal 	RSTCTRL_dly	: std_ulogic := '0';
  signal 	RSTM_dly	: std_ulogic := '0';
  signal 	RSTP_dly	: std_ulogic := '0';
  signal 	SUBTRACT_dly	: std_ulogic := '0';

  signal	BCOUT_zd	: std_logic_vector(MSB_BCOUT downto 0) := (others => '0');
  signal	P_zd		: std_logic_vector(MSB_P downto 0) := (others => '0');
  signal	PCOUT_zd		: std_logic_vector(MSB_PCOUT downto 0) := (others => '0');
  
  --- Internal Signal Declarations
  signal	qa_o_reg1	: std_logic_vector(MSB_A downto 0) := (others => '0');
  signal	qa_o_reg2	: std_logic_vector(MSB_A downto 0) := (others => '0');
  signal	qa_o_mux	: std_logic_vector(MSB_A downto 0) := (others => '0');

  signal	b_o_mux		: std_logic_vector(MSB_B downto 0) := (others => '0');
  signal	qb_o_reg1	: std_logic_vector(MSB_B downto 0) := (others => '0');
  signal	qb_o_reg2	: std_logic_vector(MSB_B downto 0) := (others => '0');
  signal	qb_o_mux	: std_logic_vector(MSB_B downto 0) := (others => '0');

  signal	qc_o_reg        : std_logic_vector(MSB_C downto 0) := (others => '0');
  signal	qc_o_mux	: std_logic_vector(MSB_C downto 0) := (others => '0');

  signal	mult_o_int	: std_logic_vector((MSB_A + MSB_B + 1) downto 0) := (others => '0');
  signal	mult_o_reg	: std_logic_vector((MSB_A + MSB_B + 1) downto 0) := (others => '0');
  signal	mult_o_mux	: std_logic_vector((MSB_A + MSB_B + 1) downto 0) := (others => '0');

  signal	opmode_o_reg	: std_logic_vector(MSB_OPMODE downto 0) := (others => '0');
  signal	opmode_o_mux	: std_logic_vector(MSB_OPMODE downto 0) := (others => '0');

  signal	muxx_o_mux	: std_logic_vector(MSB_P downto 0) := (others => '0');
  signal	muxy_o_mux	: std_logic_vector(MSB_P downto 0) := (others => '0');
  signal	muxz_o_mux	: std_logic_vector(MSB_P downto 0) := (others => '0');

  signal	subtract_o_reg	: std_ulogic := '0';
  signal	subtract_o_mux	: std_ulogic := '0';

  signal	carryinsel_o_reg	: std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0');
  signal	carryinsel_o_mux	: std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0');

  signal	qcarryin_o_reg1	: std_ulogic := '0';
  signal	carryin0_o_mux	: std_ulogic := '0';
  signal	carryin1_o_mux	: std_ulogic := '0';
  signal	carryin2_o_mux	: std_ulogic := '0';

  signal	qcarryin_o_reg2	: std_ulogic := '0';

  signal	carryin_o_mux	: std_ulogic := '0';

  signal	accum_o		: std_logic_vector(MSB_P downto 0) := (others => '0');
  signal	qp_o_reg	: std_logic_vector(MSB_P downto 0) := (others => '0');
  signal	qp_o_mux	: std_logic_vector(MSB_P downto 0) := (others => '0');

  signal	add_i_int      : std_logic_vector(47 downto 0) := (others => '0');
  signal	add_o_int      : std_logic_vector(47 downto 0) := (others => '0');

  signal	reg_p_int         : std_logic_vector(47 downto 0) := (others => '0');
  signal	p_o_int         : std_logic_vector(47 downto 0) := (others => '0');

  signal	subtract1_o_int : std_ulogic := '0';
  signal	carryinsel1_o_int : std_logic_vector(1 downto 0) := (others => '0');
  signal	carry1_o_int     : std_ulogic := '0';
  signal	carry2_o_int     : std_ulogic := '0';


  signal	output_x_sig	: std_ulogic := '0';

  signal   RST_META          : std_ulogic := '0';

  signal   DefDelay          : time := 10 ps;

begin

  ---------------------
  --  INPUT PATH DELAYs
  ---------------------

  A_dly          	 <= A              	after 0 ps;
  B_dly          	 <= B              	after 0 ps;
  BCIN_dly       	 <= BCIN           	after 0 ps;
  C_dly          	 <= C              	after 0 ps;
  CARRYIN_dly    	 <= CARRYIN        	after 0 ps;
  CARRYINSEL_dly 	 <= CARRYINSEL     	after 0 ps;
  CEA_dly        	 <= CEA            	after 0 ps;
  CEB_dly        	 <= CEB            	after 0 ps;
  CEC_dly        	 <= CEC            	after 0 ps;
  CECARRYIN_dly  	 <= CECARRYIN      	after 0 ps;
  CECINSUB_dly   	 <= CECINSUB       	after 0 ps;
  CECTRL_dly     	 <= CECTRL         	after 0 ps;
  CEM_dly        	 <= CEM            	after 0 ps;
  CEP_dly        	 <= CEP            	after 0 ps;
  CLK_dly        	 <= CLK            	after 0 ps;
  GSR_dly        	 <= GSR            	after 0 ps;
  OPMODE_dly     	 <= OPMODE         	after 0 ps;
  PCIN_dly       	 <= PCIN           	after 0 ps;
  RSTA_dly       	 <= RSTA           	after 0 ps;
  RSTB_dly       	 <= RSTB           	after 0 ps;
  RSTC_dly       	 <= RSTC           	after 0 ps;
  RSTCARRYIN_dly 	 <= RSTCARRYIN     	after 0 ps;
  RSTCTRL_dly    	 <= RSTCTRL        	after 0 ps;
  RSTM_dly       	 <= RSTM           	after 0 ps;
  RSTP_dly       	 <= RSTP           	after 0 ps;
  SUBTRACT_dly   	 <= SUBTRACT       	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                        Initialization                      ###
--####################################################################
 prcs_init:process
  begin
     if((LEGACY_MODE /="NONE") and (LEGACY_MODE /="MULT18X18") and 
        (LEGACY_MODE /="MULT18X18S")) then
        assert false
        report "Attribute Syntax Error: The allowed values for LEGACY_MODE are NONE, MULT18X18 or MULT18X18S."
        severity Failure;
     elsif((LEGACY_MODE ="MULT18X18") and (MREG /= 0)) then
        assert false
        report "Attribute Syntax Error: The attribute LEGACY_MODE on DSP48 is set to MULT18X18. This requires attribute MREG to be set to 0."
        severity Failure;
     elsif((LEGACY_MODE ="MULT18X18S") and (MREG /= 1)) then
        assert false
        report "Attribute Syntax Error: The attribute LEGACY_MODE on DSP48 is set to MULT18X18S. This requires attribute MREG to be set to 1."
        severity Failure;
     end if;

     wait; 
  end process prcs_init;
--####################################################################
--#####    Input Register A with two levels of registers and a mux ###
--####################################################################
  prcs_qa_2lvl:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
          qa_o_reg1 <= ( others => '0');
          qa_o_reg2 <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
--FP            if((RSTA_dly = '1') and (CEA_dly = '1')) then
            if(RSTA_dly = '1') then
               qa_o_reg1 <= ( others => '0');
               qa_o_reg2 <= ( others => '0');
            elsif ((RSTA_dly = '0') and  (CEA_dly = '1')) then
               qa_o_reg2 <= qa_o_reg1;
               qa_o_reg1 <= A_dly;
            end if;
         end if;
      end if;
  end process prcs_qa_2lvl;
------------------------------------------------------------------
  prcs_qa_o_mux:process(A_dly, qa_o_reg1, qa_o_reg2)
  begin
     case AREG is
       when 0 => qa_o_mux <= A_dly;
       when 1 => qa_o_mux <= qa_o_reg1;
       when 2 => qa_o_mux <= qa_o_reg2;
       when others =>
            assert false
            report "Attribute Syntax Error: The allowed values for AREG are 0 or 1 or 2"
            severity Failure;
     end case;
  end process prcs_qa_o_mux;

--####################################################################
--#####    Input Register B with two levels of registers and a mux ###
--####################################################################
 prcs_b_in:process(B_dly, BCIN_dly)
  begin
     if(B_INPUT ="DIRECT") then
        b_o_mux <= B_dly;
     elsif(B_INPUT ="CASCADE") then
        b_o_mux <= BCIN_dly;
     else
        assert false
        report "Attribute Syntax Error: The allowed values for B_INPUT are DIRECT or CASCADE."
        severity Failure;
     end if;
     
  end process prcs_b_in;
------------------------------------------------------------------
 prcs_qb_2lvl:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
          qb_o_reg1 <= ( others => '0');
          qb_o_reg2 <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
-- FP            if((RSTB_dly = '1') and (CEB_dly = '1')) then
            if(RSTB_dly = '1') then
               qb_o_reg1 <= ( others => '0');
               qb_o_reg2 <= ( others => '0');
            elsif ((RSTB_dly = '0') and  (CEB_dly = '1')) then
               qb_o_reg2 <= qb_o_reg1;
               qb_o_reg1 <= b_o_mux;
            end if;
         end if;
      end if;
  end process prcs_qb_2lvl;
------------------------------------------------------------------
  prcs_qb_o_mux:process(b_o_mux, qb_o_reg1, qb_o_reg2)
  begin
     case BREG is
       when 0 => qb_o_mux <= b_o_mux;
       when 1 => qb_o_mux <= qb_o_reg1;
       when 2 => qb_o_mux <= qb_o_reg2;
       when others =>
            assert false
            report "Attribute Syntax Error: The allowed values for BREG are 0 or 1 or 2 "
            severity Failure;
     end case;

  end process prcs_qb_o_mux;

--####################################################################
--#####    Input Register C with 0, 1, level of registers        #####
--####################################################################
  prcs_qc_1lvl:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         qc_o_reg <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
-- FP           if((RSTC_dly = '1') and (CEC_dly = '1'))then
            if(RSTC_dly = '1') then
               qc_o_reg <= ( others => '0');
            elsif ((RSTC_dly = '0') and (CEC_dly = '1')) then
               qc_o_reg <= C_dly;
            end if;
         end if;
      end if;
  end process prcs_qc_1lvl;
------------------------------------------------------------------
  prcs_qc_o_mux:process(C_dly, qc_o_reg)
  begin
     case CREG is
      when 0 => qc_o_mux <= C_dly;
      when 1 => qc_o_mux <= qc_o_reg;
      when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for CREG are 0 or 1"
           severity Failure;
      end case;
  end process prcs_qc_o_mux;

--####################################################################
--#####                     Mulitplier                           #####
--####################################################################
  prcs_mult:process(qa_o_mux, qb_o_mux)
  begin
     mult_o_int <=  qa_o_mux * qb_o_mux;
  end process prcs_mult;
------------------------------------------------------------------
  prcs_mult_reg:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         mult_o_reg <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
--FP            if((RSTM_dly = '1') and (CEM_dly = '1'))then
            if(RSTM_dly = '1') then
               mult_o_reg <= ( others => '0');
            elsif ((RSTM_dly = '0') and (CEM_dly = '1')) then
               mult_o_reg <= mult_o_int;
            end if;
         end if;
      end if;
  end process prcs_mult_reg;
------------------------------------------------------------------
  prcs_mult_mux:process(mult_o_reg, mult_o_int)
  begin
     case MREG is
      when 0 => mult_o_mux <= mult_o_int;
      when 1 => mult_o_mux <= mult_o_reg;
      when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for MREG are 0 or 1"
           severity Failure;
      end case;
  end process prcs_mult_mux;

--####################################################################
--#####                        OpMode                            #####
--####################################################################
  prcs_opmode_reg:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         opmode_o_reg <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
--FP            if((RSTCTRL_dly = '1') and (CECTRL_dly = '1'))then
            if(RSTCTRL_dly = '1') then
               opmode_o_reg <= ( others => '0');
            elsif ((RSTCTRL_dly = '0') and (CECTRL_dly = '1')) then
               opmode_o_reg <= OPMODE_dly;
            end if;
         end if;
      end if;
  end process prcs_opmode_reg;
------------------------------------------------------------------
  prcs_opmode_mux:process(opmode_o_reg, OPMODE_dly)
  begin
     case OPMODEREG is
      when 0 => opmode_o_mux <= OPMODE_dly;
      when 1 => opmode_o_mux <= opmode_o_reg;
      when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for OPMODEREG are 0 or 1"
           severity Failure;
      end case;
  end process prcs_opmode_mux;
--####################################################################
--#####                        MUX_XYZ                           #####
--####################################################################
--  prcs_mux_xyz:process(opmode_o_mux,,,, FP)
      -- FP ?? more (Z) should be added to sensitivity list
  prcs_mux_xyz:process(opmode_o_mux, qp_o_mux, qa_o_mux, qb_o_mux, mult_o_mux, 
                       qc_o_mux, PCIN_dly, output_x_sig)
  begin
    if(output_x_sig = '1') then
      muxx_o_mux(MSB_P downto 0) <= ( others => 'X');
      muxy_o_mux(MSB_P downto 0) <= ( others => 'X');
      muxz_o_mux(MSB_P downto 0) <= ( others => 'X');
    elsif(output_x_sig = '0') then
    --MUX_X -----
       case opmode_o_mux(1 downto 0) is
         when "00" => muxx_o_mux <= ( others => '0');
         -- FP ?? better way to concat ? and sign extend ?
         when "01" => muxx_o_mux((MAX_A + MAX_B - 1) downto 0) <= mult_o_mux;
                   if(mult_o_mux(MAX_A + MAX_B - 1) = '1') then
                     muxx_o_mux(MSB_PCIN downto (MAX_A + MAX_B)) <=  ( others => '1');
                   elsif (mult_o_mux(MSB_A + MSB_B + 1) = '0') then 
                     muxx_o_mux(MSB_PCIN downto (MAX_A + MAX_B)) <=  ( others => '0');
                   end if;

         when "10" => muxx_o_mux <= qp_o_mux;
         when "11" => if(qa_o_mux(MSB_A) = '0') then
                        muxx_o_mux(MSB_P downto 0)  <= ("000000000000" & qa_o_mux & qb_o_mux);
                      elsif(qa_o_mux(MSB_A) = '1') then
                        muxx_o_mux(MSB_P downto 0)  <= ("111111111111" & qa_o_mux & qb_o_mux);
                      end if;
--      when "11" => muxx_o_mux(MSB_B downto 0)  <= qb_o_mux;
--                   muxx_o_mux((MAX_A + MAX_B - 1) downto MAX_B) <= qa_o_mux;
--
--                  if(mult_o_mux(MAX_A + MAX_B - 1) = '1') then
--                     muxx_o_mux(MSB_PCIN downto (MAX_A + MAX_B)) <=  ( others => '1');
--                   elsif (mult_o_mux(MSB_A + MSB_B + 1) = '0') then
--                     muxx_o_mux(MSB_PCIN downto (MAX_A + MAX_B)) <=  ( others => '0');
--                   end if;
      when others => null;
--            assert false
--            report "Error: input signal OPMODE(1 downto 0) has unknown values"
--            severity Failure;
       end case;

    --MUX_Y -----
       case opmode_o_mux(3 downto 2) is
         when "00" => muxy_o_mux <= ( others => '0');
         when "01" => muxy_o_mux <= ( others => '0');
         when "10" => null;
         when "11" => muxy_o_mux <= qc_o_mux;
         when others => null;
--            assert false
--            report "Error: input signal OPMODE(3 downto 2) has unknown values"
--            severity Failure;
       end case;
    --MUX_Z -----
       case opmode_o_mux(6 downto 4) is
         when "000" => muxz_o_mux <= ( others => '0');
         when "001" => muxz_o_mux <= PCIN_dly;
         when "010" => muxz_o_mux <= qp_o_mux;
         when "011" => muxz_o_mux <= qc_o_mux;
         when "100" => null;
      -- FP ?? better shift possible ?
         when "101" => if(PCIN_dly(MSB_PCIN) = '0') then
                         muxz_o_mux  <= ( others => '0');
                       elsif(PCIN_dly(MSB_PCIN) = '1') then
                         muxz_o_mux  <= ( others => '1');
                       end if;
                       muxz_o_mux ((MSB_PCIN - SHIFT_MUXZ) downto 0) <= PCIN_dly(MSB_PCIN downto SHIFT_MUXZ ); 
         when "110" => if(qp_o_mux(MSB_P) = '0') then
                         muxz_o_mux  <= ( others => '0');
                       elsif(qp_o_mux(MSB_P) = '1') then
                         muxz_o_mux  <= ( others => '1');
                       end if;
--                    muxz_o_mux ((MAX_P - SHIFT_MUXZ) downto 0) <= qp_o_mux(MSB_P downto (SHIFT_MUXZ - 1)); 
                       muxz_o_mux ((MSB_P - SHIFT_MUXZ) downto 0) <= qp_o_mux(MSB_P downto SHIFT_MUXZ ); 
                      
         when "111" => null;
         when others => null;
--            assert false
--            report "Error: input signal OPMODE(6 downto 4) has unknown values"
--            severity Failure;
       end case;
    end if;
  end process prcs_mux_xyz;
--####################################################################
--#####                        Subtract                          #####
--####################################################################
  prcs_subtract_reg:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         subtract_o_reg <= '0';
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTCTRL_dly = '1') then
               subtract_o_reg <= '0';
            elsif ((RSTCTRL_dly = '0') and (CECINSUB_dly = '1'))then
               subtract_o_reg <= SUBTRACT_dly;
            end if;
         end if;
      end if;
  end process prcs_subtract_reg;
------------------------------------------------------------------
  prcs_subtract_mux:process(subtract_o_reg, SUBTRACT_dly)
  begin
     case SUBTRACTREG is
      when 0 => subtract_o_mux <= SUBTRACT_dly;
      when 1 => subtract_o_mux <= subtract_o_reg;
      when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for SUBTRACTREG are 0 or 1"
           severity Failure;
      end case;
  end process prcs_subtract_mux;

--####################################################################
--#####                     CarryInSel                           #####
--####################################################################
  prcs_carryinsel_reg:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         carryinsel_o_reg <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
--FP            if((RSTCTRL_dly = '1') and (CECTRL_dly = '1'))then
            if(RSTCTRL_dly = '1') then
               carryinsel_o_reg <= ( others => '0');
            elsif ((RSTCTRL_dly = '0') and (CECTRL_dly = '1')) then
               carryinsel_o_reg <= CARRYINSEL_dly;
            end if;
         end if;
      end if;
  end process prcs_carryinsel_reg;
------------------------------------------------------------------
  prcs_carryinsel_mux:process(carryinsel_o_reg, CARRYINSEL_dly)
  begin
     case CARRYINSELREG is
       when 0 => carryinsel_o_mux <= CARRYINSEL_dly;
       when 1 => carryinsel_o_mux <= carryinsel_o_reg;
       when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for CARRYINSELREG are 0 or 1"
           severity Failure;
     end case;
  end process prcs_carryinsel_mux;

--####################################################################
--#####                       CarryIn                            #####
--####################################################################
  prcs_carryin_reg1:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         qcarryin_o_reg1 <= '0';
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTCARRYIN_dly = '1') then
               qcarryin_o_reg1 <= '0';
            elsif((RSTCARRYIN_dly = '0') and (CECINSUB_dly = '1')) then
               qcarryin_o_reg1 <= CARRYIN_dly;
            end if;
         end if;
      end if;
  end process prcs_carryin_reg1;
------------------------------------------------------------------
  prcs_carryin0_mux:process(qcarryin_o_reg1, CARRYIN_dly)
  begin
     case CARRYINREG is
       when 0 => carryin0_o_mux <= CARRYIN_dly;
       when 1 => carryin0_o_mux <= qcarryin_o_reg1;
       when others =>
            assert false
            report "Attribute Syntax Error: The allowed values for CARRYINREG are 0 or 1"
            severity Failure;
     end case;
  end process prcs_carryin0_mux;
------------------------------------------------------------------
  prcs_carryin1_mux:process(opmode_o_mux(0), opmode_o_mux(1), qa_o_mux(17), qb_o_mux(17))
  begin
     case (opmode_o_mux(0) and opmode_o_mux(1)) is
       when '0' => carryin1_o_mux <= NOT(qa_o_mux(17) xor qb_o_mux(17));
       when '1' => carryin1_o_mux <= NOT qa_o_mux(17);
       when others => null;
--           assert false
--           report "Error: UNKOWN Value at PORT OPMODE(1) "
--           severity Failure;
     end case;
  end process prcs_carryin1_mux;
------------------------------------------------------------------
  prcs_carryin2_mux:process(opmode_o_mux(0), opmode_o_mux(1), qp_o_mux(47), PCIN_dly(47))
  begin
     if(((opmode_o_mux(1) = '1') and (opmode_o_mux(0) = '0')) or 
        (opmode_o_mux(5) = '1') or 
        (NOT ((opmode_o_mux(6) = '1') or (opmode_o_mux(4) = '1')))) then
        carryin2_o_mux <= NOT qp_o_mux(47);
     else
        carryin2_o_mux <= NOT PCIN_dly(47);
     end if;
  end process prcs_carryin2_mux;
------------------------------------------------------------------
  prcs_carryin_reg2:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         qcarryin_o_reg2 <= '0';
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTCARRYIN_dly = '1') then
               qcarryin_o_reg2 <= '0';
            elsif ((RSTCARRYIN_dly = '0') and (CECARRYIN_dly = '1'))then
               qcarryin_o_reg2 <= carryin1_o_mux;
            end if;
         end if;
      end if;
  end process prcs_carryin_reg2;
------------------------------------------------------------------
  prcs_carryin_mux:process(carryinsel_o_mux, carryin0_o_mux, carryin1_o_mux, carryin2_o_mux, qcarryin_o_reg2)
  begin
     case carryinsel_o_mux is
       when "00" => carryin_o_mux  <= carryin0_o_mux;
       when "01" => carryin_o_mux  <= carryin2_o_mux;
       when "10" => carryin_o_mux  <= carryin1_o_mux;
       when "11" => carryin_o_mux  <= qcarryin_o_reg2;
       when others => null;
--           assert false
--           report "Error: UNKOWN Value at carryinsel_o_mux"
--           severity Failure;
     end case;
  end process prcs_carryin_mux;
--####################################################################
--#####                       ACCUM                              #####
--####################################################################
--
--  NOTE :  moved it to the drc process
--
--  prcs_accum_xyz:process(muxx_o_mux, muxy_o_mux, muxz_o_mux, subtract_o_mux, carryin_o_mux )
--  variable carry_var : integer;
--  begin
--       if(carryin_o_mux = '1') then
--          carry_var := 1;
--       elsif (carryin_o_mux = '0') then 
--          carry_var := 0;
----       else
----          assert false
----          report "Error : CarryIn has Unknown value."
----          severity Failure;
--       end if;
          
--       if(subtract_o_mux = '0') then
--         accum_o <=  muxz_o_mux + (muxx_o_mux + muxy_o_mux + carryin_o_mux); 
--       elsif(subtract_o_mux = '1') then
--         accum_o <=  muxz_o_mux - (muxx_o_mux + muxy_o_mux + carryin_o_mux); 
----       else
----          assert false
----          report "Error : Subtract has Unknown value."
----          severity Failure;
--       end if;
--  end process prcs_accum_xyz;
--####################################################################
--#####                       PCOUT                               #####
--####################################################################
  prcs_qp_reg:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         qp_o_reg <=  ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTP_dly = '1') then
               qp_o_reg <= ( others => '0');
            elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then
               qp_o_reg <= accum_o;
            end if;
         end if;
      end if;
  end process prcs_qp_reg;
------------------------------------------------------------------
  prcs_qp_mux:process(accum_o, qp_o_reg)
  begin
     case PREG is
       when 0 => qp_o_mux <= accum_o;
       when 1 => qp_o_mux <= qp_o_reg;
       when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for PREG are 0 or 1"
           severity Failure;
     end case;
   
  end process prcs_qp_mux;
--####################################################################
--#####                   ZERO_DELAY_OUTPUTS                     #####
--####################################################################
  prcs_zero_delay_outputs:process(qb_o_mux, qp_o_mux)
  begin
    BCOUT_zd <= qb_o_mux;
    P_zd     <= qp_o_mux;
    PCOUT_zd <= qp_o_mux;
  end process prcs_zero_delay_outputs;

--####################################################################
--#####                 PMODE DRC                                #####
--####################################################################
  prcs_opmode_drc:process(opmode_o_mux, carryinsel_o_mux, subtract_o_mux,
                       muxx_o_mux, muxy_o_mux, muxz_o_mux, carryin_o_mux)
  variable Message : line;
  variable invalid_opmode_flg : boolean := true;
  variable add_flg : boolean := true;
  variable opmode_carryinsel_var : std_logic_vector(8 downto 0) := (others => '0');
  begin
--    if now > 100 ns then
--    The above line was cusing the intial values of A, B or C not trigger
      opmode_carryinsel_var := opmode_o_mux & carryinsel_o_mux;
      case opmode_carryinsel_var is


        when "000000000" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "000001000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;
-- CR 455601 eased the following drc 
        when "000001001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;
--

        when "000001100" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "000010100" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "000110000" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "000111000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "000111001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "000111100" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "000111110" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "001000000" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "001001000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "001001001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "001001100" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "001001101" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "001001110" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "001010100" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "001010101" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "001010110" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "001010111" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "001110000" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "001110001" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "001111000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "001111001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "001111100" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "001111101" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "001111110" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "010000000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "010001000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "010001100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "010001101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "010010100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "010010101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "010110000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "010110001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "010111000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "010111001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "010111100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "010111101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "010111110" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "011000000" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "011001000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "011001001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "011001100" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "011001110" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "011010100" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "011010110" => 
                          if (MREG /= 0) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_no_mreg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "011010111" => 
                          if (MREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_mreg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "011110000" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "011111000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "011111100" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';


        when "011111101" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "101000000" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "101001000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "101001100" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "101001101" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "101001110" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "101010100" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "101010101" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "101010110" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "101010111" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "101110000" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "101110001" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "101111000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "101111001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "101111100" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "101111101" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "101111110" => 
                          invalid_opmode_flg := true ;
                          add_flg := true ;
                          output_x_sig <= '0';

        when "110000000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "110001000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "110001100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "110001101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "110010100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "110010101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "110110000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "110110001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "110111000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "110111001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "110111100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "110111101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;

        when "110111110" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             add_flg := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             add_flg := true;
                             output_x_sig <= '0';
                          end if;
        when others    =>
                       if(invalid_opmode_flg = true) then
                          invalid_opmode_flg := false;
                          add_flg := false;
                          output_x_sig <= '1';
                          accum_o <= (others => 'X');
                          Write ( Message, string'("OPMODE Input Warning : The OPMODE "));
                          Write ( Message,  slv_to_str(opmode_o_mux));
                          Write ( Message, string'(" with CARRYINSEL  "));
                          Write ( Message,  slv_to_str(carryinsel_o_mux));
                          Write ( Message, string'(" to DSP48 instance"));
                          Write ( Message, string'(" is invalid."));
                          assert false report Message.all severity Warning;
                          DEALLOCATE (Message);
                        end if;
      end case;


      if(add_flg) then 
         if(subtract_o_mux = '0') then
            accum_o <=  muxz_o_mux + (muxx_o_mux + muxy_o_mux + carryin_o_mux);
         elsif(subtract_o_mux = '1') then
            accum_o <=  muxz_o_mux - (muxx_o_mux + muxy_o_mux + carryin_o_mux);
         end if;
      end if;
--    end if;
  end process prcs_opmode_drc;

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(BCOUT_zd, PCOUT_zd, P_zd)
  begin
      BCOUT  <= BCOUT_zd after SYNC_PATH_DELAY;
      P      <= P_zd     after SYNC_PATH_DELAY;
      PCOUT  <= PCOUT_zd after SYNC_PATH_DELAY;
  end process prcs_output;



end DSP48_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                  16K-Bit FIFO
-- /___/   /\     Filename : FIFO16.vhd
-- \   \  /  \    Timestamp : Fri Mar 26 08:18:20 PST 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    02/06/06 - Updated the reset requirement message.
--    05/31/06 - Added feature for invalid reset condition. (CR 223364).
-- End Revision
  
----- CELL FIFO16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;

library STD;
use STD.TEXTIO.ALL;


library unisim;
use unisim.vpkg.all;

entity FIFO16 is

  generic(

    ALMOST_FULL_OFFSET      : bit_vector := X"080";
    ALMOST_EMPTY_OFFSET     : bit_vector := X"080"; 
    DATA_WIDTH              : integer    := 36;
    FIRST_WORD_FALL_THROUGH : boolean    := false
    );

  port(
    ALMOSTEMPTY : out std_ulogic;
    ALMOSTFULL  : out std_ulogic;
    DO          : out std_logic_vector (31 downto 0);
    DOP         : out std_logic_vector (3 downto 0);
    EMPTY       : out std_ulogic;
    FULL        : out std_ulogic;
    RDCOUNT     : out std_logic_vector (11 downto 0);
    RDERR       : out std_ulogic;
    WRCOUNT     : out std_logic_vector (11 downto 0);
    WRERR       : out std_ulogic;

    DI          : in  std_logic_vector (31 downto 0);
    DIP         : in  std_logic_vector (3 downto 0);
    RDCLK       : in  std_ulogic;
    RDEN        : in  std_ulogic;
    RST         : in  std_ulogic;
    WRCLK       : in  std_ulogic;
    WREN        : in  std_ulogic
    );

end FIFO16;

-- architecture body                    --

architecture FIFO16_V of FIFO16 is


    constant SYNC_PATH_DELAY: time  := 100 ps;
    
    constant MAX_DO      : integer    := 32;
    constant MAX_DOP     : integer    := 4;
    constant MAX_RDCOUNT : integer    := 12;
    constant MAX_WRCOUNT : integer    := 12;
    constant MSB_MAX_DO  : integer    := 31;
    constant MSB_MAX_DOP : integer    := 3;
    constant MSB_MAX_RDCOUNT : integer    := 11;
    constant MSB_MAX_WRCOUNT : integer    := 11;

    constant MAX_DI      : integer    := 32;
    constant MAX_DIP     : integer    := 4;
    constant MSB_MAX_DI  : integer    := 31;
    constant MSB_MAX_DIP : integer    := 3;

    constant MAX_LATENCY_EMPTY : integer := 3;
    constant MAX_LATENCY_FULL  : integer := 3;

    signal MEM  : std_logic_vector( 16383 downto 0 ) := (others => 'X');
    signal MEMP : std_logic_vector( 2047 downto 0 )  := (others => 'X');

    signal DI_ipd    : std_logic_vector(MSB_MAX_DI downto 0)    := (others => 'X');
    signal DIP_ipd   : std_logic_vector(MSB_MAX_DIP downto 0)   := (others => 'X');
    signal GSR       : std_ulogic     :=    '0';
    signal GSR_ipd   : std_ulogic     :=    'X';
    signal RDCLK_ipd : std_ulogic     :=    'X';
    signal RDEN_ipd  : std_ulogic     :=    'X';
    signal RST_ipd   : std_ulogic     :=    'X';
    signal WRCLK_ipd : std_ulogic     :=    'X';
    signal WREN_ipd  : std_ulogic     :=    'X';

    signal DI_dly    : std_logic_vector(MSB_MAX_DI downto 0)    := (others => 'X');
    signal DIP_dly   : std_logic_vector(MSB_MAX_DIP downto 0)   := (others => 'X');
    signal GSR_dly   : std_ulogic     :=    'X';
    signal RDCLK_dly : std_ulogic     :=    'X';
    signal RDEN_dly  : std_ulogic     :=    'X';
    signal RST_dly   : std_ulogic     :=    'X';
    signal WRCLK_dly : std_ulogic     :=    'X';
    signal WREN_dly  : std_ulogic     :=    'X';

    signal DO_zd          : std_logic_vector(MSB_MAX_DO  downto 0)    := (others => '0');
    signal DOP_zd         : std_logic_vector(MSB_MAX_DOP downto 0)    := (others => '0');
    signal ALMOSTEMPTY_zd : std_ulogic     :=    '1';
    signal ALMOSTFULL_zd  : std_ulogic     :=    '0';
    signal EMPTY_zd       : std_ulogic     :=    '1';
    signal FULL_zd        : std_ulogic     :=    '0';
    signal RDCOUNT_zd     : std_logic_vector(MSB_MAX_RDCOUNT  downto 0)    := (others => '0');
    signal RDERR_zd       : std_ulogic     :=    '0';
    signal WRCOUNT_zd     : std_logic_vector(MSB_MAX_WRCOUNT  downto 0)    := (others => '0');
    signal WRERR_zd       : std_ulogic     :=    '0';
    signal RDCOUNT_OUT_zd : std_logic_vector(MSB_MAX_RDCOUNT  downto 0)    := (others => '1');
    signal WRCOUNT_OUT_zd : std_logic_vector(MSB_MAX_WRCOUNT  downto 0)    := (others => '1');
    signal DO_OUT_zd      : std_logic_vector(MSB_MAX_DO  downto 0)         := (others => 'X');
    signal DOP_OUT_zd     : std_logic_vector(MSB_MAX_DOP  downto 0)        := (others => 'X');
    
  --- Internal Signal Declarations

    signal RST_META    : std_ulogic := '0';

    signal DefDelay    : time := 10 ps;

    signal addr_limit    : integer := 0;
    signal wr_addr       : integer := 0;
    signal rd_addr       : integer := 0;
    signal rd_addr_range : integer := 0;
    signal wr_addr_range : integer := 0;

    signal rd_flag       : std_ulogic := '0';
    signal wr_flag       : std_ulogic := '0';

    signal rdcount_flag  : std_ulogic := '0';

    signal D_W           : integer := 32;
    signal P_W           : integer := 4;

    signal almostempty_limit : real := 0.0;
    signal almostfull_limit  : real := 0.0;

    signal violation : std_ulogic := '0'; 

    signal fwft      : std_ulogic := 'X';

    signal update_from_write_prcs      : std_ulogic := '0';
    signal update_from_read_prcs       : std_ulogic := '0';

    signal ae_empty   : integer := 0;

-- CR 182616 fix
   signal rst_rdckreg : std_logic_vector (2 downto 0) := (others => '0');
   signal rst_wrckreg : std_logic_vector (2 downto 0) := (others => '0');
   signal rst_rdclk_flag : std_ulogic := '0';
   signal rst_wrclk_flag : std_ulogic := '0';
    
begin

  ---------------------
  --  INPUT PATH DELAYs
  ---------------------

  DI_dly         	 <= DI             	after 0 ps;
  DIP_dly        	 <= DIP            	after 0 ps;
  GSR_dly        	 <= GSR            	after 0 ps;
  RDCLK_dly      	 <= RDCLK          	after 0 ps;
  RDEN_dly       	 <= RDEN           	after 0 ps;
  RST_dly        	 <= RST            	after 0 ps;
  WRCLK_dly      	 <= WRCLK          	after 0 ps;
  WREN_dly       	 <= WREN           	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------


--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_initialize:process
  variable first_time        : boolean    := true;
  variable addr_limit_var    : integer    := 0; 
  variable fwft_var          : std_ulogic := 'X';
  variable rd_offset_stdlogic : std_logic_vector (ALMOST_EMPTY_OFFSET'length-1 downto 0);
  variable rd_offset_int : integer := 0;
  variable wr_offset_stdlogic : std_logic_vector (ALMOST_FULL_OFFSET'length-1 downto 0);
  variable wr_offset_int : integer := 0;
  variable Message : LINE;
  variable ae_empty_var      : integer := 0;

  begin
     if (first_time) then
       case  DATA_WIDTH is
            when 4  => 
                      addr_limit_var := 4096;
                      D_W <= 4;
                      P_W <= 0;
            when 9  =>
                      addr_limit_var := 2048;
                      D_W <= 8;
                      P_W <= 1;
            when 18 => 
                      addr_limit_var := 1024;
                      D_W <= 16; 
                      P_W <= 2;
            when 36 => 
                      addr_limit_var := 512;
                      D_W <= 32;
                      P_W <= 4;
            when others =>
                    GenericValueCheckMessage
                      ( HeaderMsg            => " Attribute Syntax Error ",
                        GenericName          => " DATA_WIDTH ",
                        EntityName           => "FIFO16",
                        GenericValue         => DATA_WIDTH,
                        Unit                 => "",
                        ExpectedValueMsg     => " The Legal values for this attribute are ",
                        ExpectedGenericValue => " 4, 9, 18 and 36 ",
                        TailMsg              => "",
                        MsgSeverity          => error
                        );
       end case;

       rd_offset_stdlogic := To_StdLogicVector(ALMOST_EMPTY_OFFSET);
       rd_offset_int := SLV_TO_INT(rd_offset_stdlogic);

       wr_offset_stdlogic := To_StdLogicVector(ALMOST_FULL_OFFSET);
       wr_offset_int := SLV_TO_INT(wr_offset_stdlogic);

       case FIRST_WORD_FALL_THROUGH is
            when true  =>
                         fwft_var     := '1';
                         ae_empty_var := rd_offset_int - 2;
            when false =>
                         fwft_var     := '0';
                         ae_empty_var := rd_offset_int - 1;
            when others =>
                    GenericValueCheckMessage
                      ( HeaderMsg            => " Attribute Syntax Error ",
                        GenericName          => " FIRST_WORD_FALL_THROUGH ",
                        EntityName           => "FIFO16",
                        GenericValue         => FIRST_WORD_FALL_THROUGH,
                        Unit                 => "",
                        ExpectedValueMsg     => " The Legal values for this attribute are ",
                        ExpectedGenericValue => " true or false ",
                        TailMsg              => "",
                        MsgSeverity          => error
                        );
       end case;

       if ((fwft_var = '0') and ((rd_offset_int < 5) or (rd_offset_int > addr_limit_var - 4))) then
          write( Message, STRING'("Attribute Syntax Error : ") );
          write( Message, STRING'("The attribute ") );
          write( Message, STRING'("ALMOST_EMPTY_OFFSET on FIFO16 is set to ") );
          write( Message, rd_offset_int);
          write( Message, STRING'(". Legal values for this attribute are ") );
          write( Message, 5);
          write( Message, STRING'(" to ") );
          write( Message, addr_limit_var - 4 );
          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
          DEALLOCATE (Message);
       end if;
 
       if ((fwft_var = '0') and ((wr_offset_int < 4) or (wr_offset_int > addr_limit_var - 5))) then
          write( Message, STRING'("Attribute Syntax Error : ") );
          write( Message, STRING'("The attribute ") );
          write( Message, STRING'("ALMOST_FULL_OFFSET on FIFO16 is set to ") );
          write( Message, wr_offset_int);
          write( Message, STRING'(". Legal values for this attribute are ") );
          write( Message, 4);
          write( Message, STRING'(" to ") );
          write( Message, addr_limit_var - 5 );
          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
          DEALLOCATE (Message);
       end if;

       if ((fwft_var = '1') and ((rd_offset_int < 6) or (rd_offset_int > addr_limit_var - 3))) then
          write( Message, STRING'("Attribute Syntax Error : ") );
          write( Message, STRING'("The attribute ") );
          write( Message, STRING'("ALMOST_EMPTY_OFFSET on FIFO16 is set to ") );
          write( Message, rd_offset_int);
          write( Message, STRING'(". Legal values for this attribute are ") );
          write( Message, 6);
          write( Message, STRING'(" to ") );
          write( Message, addr_limit_var - 3 );
          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
          DEALLOCATE (Message);
       end if;

       if ((fwft_var = '1') and ((wr_offset_int < 4) or (wr_offset_int > addr_limit_var - 5))) then
          write( Message, STRING'("Attribute Syntax Error : ") );
          write( Message, STRING'("The attribute ") );
          write( Message, STRING'("ALMOST_FULL_OFFSET on FIFO16 is set to ") );
          write( Message, wr_offset_int);
          write( Message, STRING'(". Legal values for this attribute are ") );
          write( Message, 4);
          write( Message, STRING'(" to ") );
          write( Message, addr_limit_var - 5 );
          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
          DEALLOCATE (Message);
       end if;


       addr_limit <= addr_limit_var;
       fwft       <= fwft_var;
       ae_empty   <= ae_empty_var;
       first_time := false;
     end if;
     wait;
  end process prcs_initialize;

--####################################################################
--#####                         CR 182616                        #####
--####################################################################
  prcs_rst_rdin_wrin:process(RST_dly, RDEN_dly, WREN_dly)
  begin
     if(RST_dly = '1') then
       if(RDEN_dly = '1') then
          assert false
          report "Warning : RDEN on FIFO16  is high when RST is high. RDEN should be low during reset."
          severity Warning;
       end if;

       if(WREN_dly = '1') then
          assert false
          report "Warning : WREN on FIFO16  is high when RST is high. WREN should be low during reset."
          severity Warning;
       end if;
     end if;
  end process prcs_rst_rdin_wrin;
-------------------------------------------
  prcs_3clkrst_readwrite:process(RDCLK_dly, WRCLK_dly)
  variable  rst_rdckreg_var : std_logic_vector (2 downto 0) := (others => '0');
  variable  rst_wrckreg_var : std_logic_vector (2 downto 0) := (others => '0');
  begin
    if(rising_edge(RDCLK_dly)) then
      rst_rdckreg_var(2) := RST_dly and rst_rdckreg_var(1);
      rst_rdckreg_var(1) := RST_dly and rst_rdckreg_var(0);
      rst_rdckreg_var(0) := RST_dly;
    end if;   
           
    if(rising_edge(WRCLK_dly)) then
      rst_wrckreg_var(2) := RST_dly and rst_wrckreg_var(1);
      rst_wrckreg_var(1) := RST_dly and rst_wrckreg_var(0);
      rst_wrckreg_var(0) := RST_dly;
    end if;   

    rst_rdckreg <= rst_rdckreg_var;
    rst_wrckreg <= rst_wrckreg_var;
  end process prcs_3clkrst_readwrite;

  prcs_2clkrst:process(RST_dly)
  begin
    rst_rdclk_flag <= '0';
    rst_wrclk_flag <= '0';
        
      if(falling_edge(RST_dly)) then
         if((rst_rdckreg(2) ='0') or (rst_rdckreg(1) ='0') or (rst_rdckreg(0) ='0')) then  
             assert false
             report "Error : RST signal on FIFO16 stays high for less than three RDCLK clock cycles. RST has to stay high for more than three RDCLK clock cycles"
             severity Error;
             rst_rdclk_flag <= '1';
         end if;
         if((rst_wrckreg(2) ='0') or (rst_wrckreg(1) ='0') or (rst_wrckreg(0) ='0')) then  
             assert false
             report "Error : RST signal on FIFO16 stays high for less than three WRCLK clock cycles. RST has to stay high for more than three WRCLK clock cycles"
             severity Error;
             rst_wrclk_flag <= '1';
         end if;
      end if;
  end process prcs_2clkrst;

--####################################################################
--#####                         Read                             #####
--####################################################################
  prcs_read:process(RDCLK_dly, RST_dly, GSR_dly, update_from_write_prcs, rst_rdclk_flag, rst_wrclk_flag)
  variable first_time        : boolean    := true;
  variable rd_addr_var       : integer    := 0;
  variable wr_addr_var       : integer    := 0;
  variable rdcount_var       : integer    := 0;

  variable rd_flag_var       : std_ulogic := '0';
  variable wr_flag_var       : std_ulogic := '0';

  variable rdcount_flag_var  : std_ulogic := '0';

  variable rd_offset_stdlogic : std_logic_vector (ALMOST_EMPTY_OFFSET'length-1 downto 0);
  variable rd_offset_int : integer := 0;

  variable do_in             : std_logic_vector(MSB_MAX_DO  downto 0)    := (others => 'X');
  variable dop_in            : std_logic_vector(MSB_MAX_DOP downto 0)    := (others => 'X');

  variable almostempty_int   : std_ulogic_vector(3 downto 0) := (others => '1');
  variable empty_int         : std_ulogic_vector(3 downto 0) := (others => '1');
  variable empty_ram         : std_ulogic_vector(3 downto 0) := (others => '1');

  variable addr_limit_var    : integer    := 0;

  variable wr1_addr_var      : integer := 0;
  variable wr1_flag_var      : std_ulogic := '0';
  variable rd_prefetch_var   : integer := 0;
  variable rd_prefetch_flag_var  : std_ulogic := '0';

-- CR 195129  fix from verilog (may not be necessary for vhdl)
-- Added ren_var/wren_var to remember the old val of RDEN_dly/WREN_dly

  variable rden_var  : std_ulogic := '0';
  variable wren_var  : std_ulogic := '0';

  begin
     if((GSR_dly = '1') or (RST_dly = '1'))then
       rd_addr <= 0;
       rd_flag <= '0';

       rd_addr_var  := 0;
       wr_addr_var  := 0;
       wr1_addr_var := 0;
       rd_prefetch_var := 0;
   
       rdcount_var := 0;
       
       rd_flag_var  := '0';
       wr_flag_var  := '0';
       wr1_flag_var := '0';
       rd_prefetch_flag_var := '0';
  
       rdcount_flag_var := '0';

       empty_int       :=  (others => '1');
       almostempty_int :=  (others => '1');
       empty_ram       :=  (others => '1');

       ALMOSTEMPTY_zd <= '1';
       EMPTY_zd <= '1';
       RDERR_zd <= '0';
       RDCOUNT_zd <= (others => '0');

       if(GSR_dly = '1') then
          DO_zd((D_W -1) downto 0) <= (others => '0');
          DOP_zd((P_W -1) downto 0) <= (others => '0');
       end if;

     elsif ((rst_rdclk_flag = '1') or (rst_wrclk_flag = '1'))then

       rd_addr <= 0;
       rd_flag <= '0';

       rd_addr_var  := 0;
       wr_addr_var  := 0;
       wr1_addr_var := 0;
       rd_prefetch_var := 0;
   
       rdcount_var := 0;
       
       rd_flag_var  := '0';
       wr_flag_var  := '0';
       wr1_flag_var := '0';
       rd_prefetch_flag_var := '0';
  
       rdcount_flag_var := '0';

       empty_int       :=  (others => '1');
       almostempty_int :=  (others => '1');
       empty_ram       :=  (others => '1');

       ALMOSTEMPTY_zd <= 'X';
       EMPTY_zd <= 'X';
       RDERR_zd <= 'X';
       RDCOUNT_zd <= (others => 'X');

       DO_zd((D_W -1) downto 0) <= (others => 'X');
       DOP_zd((P_W -1) downto 0) <= (others => 'X');
       
     elsif ((GSR_dly = '0') and (RST_dly = '0'))then

       rden_var := RDEN_dly;
       wren_var := WREN_dly;

       if(rising_edge(RDCLK_dly)) then

         rd_offset_stdlogic := To_StdLogicVector(ALMOST_EMPTY_OFFSET);
         rd_offset_int := SLV_TO_INT(rd_offset_stdlogic);

         rd_flag_var := rd_flag;
         wr_flag_var := wr_flag;

         rd_addr_var := rd_addr;
         wr_addr_var := wr_addr;

         rdcount_var := SLV_TO_INT(RDCOUNT_zd);
         rdcount_flag_var := rdcount_flag;

         if(fwft = '0') then
           addr_limit_var := addr_limit;
           if((rden_var = '1') and (rd_addr_var /= rdcount_var)) then
              DO_zd   <= do_in;
              DOP_zd  <= dop_in;
              rd_addr_var  := (rd_addr_var + 1) mod addr_limit;
              if(rd_addr_var = 0) then 
                  rd_flag_var := NOT rd_flag_var;
              end if;
           end if;
           if (((rd_addr_var = rdcount_var) and (empty_ram(3) = '0')) or 
              ((rden_var = '1') and (empty_ram(1) = '0'))) then
              do_in((D_W-1) downto 0) := MEM((((rdcount_var)*D_W)+(D_W -1)) downto ((rdcount_var)*D_W));
              dop_in((P_W-1) downto 0) := MEMP((((rdcount_var)*P_W)+(P_W -1)) downto ((rdcount_var)*P_W));
              rdcount_var := (rdcount_var + 1) mod addr_limit;

              if(rdcount_var = 0) then
                 rdcount_flag_var := NOT rdcount_flag_var;
              end if;
           end if;
-----------------  FP --------------------------------
         elsif(fwft = '1') then
           if((rden_var = '1') and (rd_addr_var /= rd_prefetch_var)) then
              rd_prefetch_var := (rd_prefetch_var + 1) mod addr_limit;
              if(rd_prefetch_var = 0) then 
                  rd_prefetch_flag_var := NOT rd_prefetch_flag_var;
              end if;
           end if;
           if((rd_prefetch_var = rd_addr_var) and (rd_addr_var /= rdcount_var)) then
             DO_zd   <= do_in;
             DOP_zd <= dop_in;
             rd_addr_var  := (rd_addr_var + 1) mod addr_limit;
             if(rd_addr_var = 0) then 
                rd_flag_var := NOT rd_flag_var;
             end if;
           end if;
           if(((rd_addr_var = rdcount_var) and (empty_ram(3) = '0')) or
              ((rden_var = '1')  and (empty_ram(1) = '0')) or 
              ((rden_var = '0')  and (empty_ram(1) = '0') and (rd_addr_var = rdcount_var))) then 
              do_in((D_W-1) downto 0) := MEM((((rdcount_var)*D_W)+(D_W -1)) downto ((rdcount_var)*D_W));
              dop_in((P_W-1) downto 0) := MEMP((((rdcount_var)*P_W)+(P_W -1)) downto ((rdcount_var)*P_W));
              rdcount_var := (rdcount_var + 1) mod addr_limit;
              if(rdcount_var = 0) then 
                 rdcount_flag_var := NOT rdcount_flag_var;
              end if;
           end if;
         end if;  ---  end if(fwft = '1')


         ALMOSTEMPTY_zd <= almostempty_int(3);
         if((((rdcount_var + ae_empty) >= wr_addr_var) and (rdcount_flag_var = wr_flag_var)) or (((rdcount_var + ae_empty) >= (wr_addr_var + addr_limit)) and (rdcount_flag_var /= wr_flag_var))) then    
            almostempty_int(3) := '1';
            almostempty_int(2) := '1';
            almostempty_int(1) := '1';
            almostempty_int(0) := '1';
         elsif(almostempty_int(2)  = '0') then
            almostempty_int(3) :=  almostempty_int(0);
            almostempty_int(0) :=  '0';
         end if;

         if(fwft = '0') then
           if((rdcount_var = rd_addr_var) and (rdcount_flag_var = rd_flag_var)) then
              EMPTY_zd <= '1';
           else
             EMPTY_zd  <= '0';
           end if;
         elsif(fwft = '1') then
           if((rd_prefetch_var = rd_addr_var) and (rd_prefetch_flag_var = rd_flag_var)) then
             EMPTY_zd <=  '1';
           else
             EMPTY_zd  <= '0';
           end if;
         end if;   
          
         if((rdcount_var = wr_addr_var) and (rdcount_flag_var = wr_flag_var)) then
           empty_ram(2) := '1';
           empty_ram(1) := '1';
           empty_ram(0) := '1';
         else
           empty_ram(2) := empty_ram(1);
           empty_ram(1) := empty_ram(0);
           empty_ram(0) := '0';
         end if;
           
         if((rdcount_var = wr1_addr_var) and (rdcount_flag_var = wr1_flag_var)) then
           empty_ram(3) := '1';
         else
           empty_ram(3) := '0';
         end if;

         wr1_addr_var := wr_addr;
         wr1_flag_var := wr_flag;

         if (not (rst_rdclk_flag or rst_wrclk_flag) = '1') then
           RDCOUNT_zd <= CONV_STD_LOGIC_VECTOR(rdcount_var, MAX_RDCOUNT);       
         end if;

         if((rden_var = '1') and (EMPTY_zd = '1')) then
             RDERR_zd <= '1';
--         elsif(rden_var = '0') then
         else
             RDERR_zd <= '0';
         end if; -- end ((rden_var = '1') and (empty_int /= '1'))

        update_from_read_prcs <= NOT update_from_read_prcs;

       end if; -- end (rising_edge(RDCLK_dly))

     end if; -- end (GSR_dly = 1)

     if(update_from_write_prcs'event) then
       wr_addr_var := wr_addr;
       wr_flag_var := wr_flag;
       if((((rdcount_var + ae_empty) <  wr_addr_var)  and (rdcount_flag_var = wr_flag_var)) or 
          (((rdcount_var + ae_empty) <  ( wr_addr_var + addr_limit)) and (rdcount_flag_var /= wr_flag_var))) then    
          if(wren_var = '1') then
             almostempty_int(2) := almostempty_int(1);
             almostempty_int(1) := '0';
          end if;
       else
           almostempty_int(2) := '1';
           almostempty_int(1) := '1';
       end if;
     end if;

     rd_addr <= rd_addr_var;
     rd_flag <= rd_flag_var;
     rdcount_flag <= rdcount_flag_var;


  end process prcs_read;

--####################################################################
--#####                         Write                            #####
--####################################################################
  prcs_write:process(WRCLK_dly, RST_dly, GSR_dly, update_from_read_prcs, rst_rdclk_flag, rst_wrclk_flag)
  variable first_time        : boolean    := true;
  variable wr_addr_var       : integer := 0;
  variable rd_addr_var       : integer := 0;
  variable rdcount_var       : integer := 0;
  variable wrcount_var       : integer := 0;

  variable rd_flag_var       : std_ulogic := '0';
  variable wr_flag_var       : std_ulogic := '0';

  variable rdcount_flag_var  : std_ulogic := '0';

  variable wr_offset_stdlogic : std_logic_vector (ALMOST_FULL_OFFSET'length-1 downto 0);
  variable wr_offset_int : integer := 0;

  variable almostfull_int : std_ulogic_vector(3 downto 0) := (others => '0');
  variable full_int       : std_ulogic_vector(3 downto 0) := (others => '0');

-- CR 195129  fix from verilog (may not be necessary for vhdl)
-- Added ren_var/wren_var to remember the old val of RDEN_dly/WREN_dly

  variable rden_var  : std_ulogic := '0';
  variable wren_var  : std_ulogic := '0';

  begin
    if ((GSR_dly = '1') or (RST_dly = '1'))then
        wr_addr_var := 0;
        wr_addr <=  0;
        wr_flag <= '0';

        wr_addr_var := 0;
        rd_addr_var := 0;
        rdcount_var := 0;
        wrcount_var := 0;

        rd_flag_var := '0';
        wr_flag_var := '0';

        rdcount_flag_var  := '0';

        full_int       :=  (others => '0');
        almostfull_int :=  (others => '0');

        if ((GSR_dly = '1') or (RST_dly = '1'))then
          ALMOSTFULL_zd <= '0';      
          FULL_zd <= '0';            
          WRERR_zd <= '0';           
          WRCOUNT_zd <= (others => '0');
        else
          ALMOSTFULL_zd <= 'X';       
          FULL_zd <= 'X';             
          WRERR_zd <= 'X';            
          WRCOUNT_zd <= (others => 'X');
        end if;

    elsif((GSR_dly = '0') and (RST_dly = '0'))then
      rden_var := RDEN_dly;
      wren_var := WREN_dly;

      if(rising_edge(WRCLK_dly)) then

        wr_offset_stdlogic := To_StdLogicVector(ALMOST_FULL_OFFSET);
        wr_offset_int := SLV_TO_INT(wr_offset_stdlogic);

        rd_flag_var := rd_flag;
        wr_flag_var := wr_flag;

        rd_addr_var := rd_addr;
        wr_addr_var := wr_addr;

        rdcount_var := SLV_TO_INT(RDCOUNT_zd);
        rdcount_flag_var := rdcount_flag;

        if((wren_var = '1') and (full_int(1)= '0') and (RST_dly = '0'))then
          MEM((((wr_addr_var)*D_W) +(D_W-1)) downto ((wr_addr_var)*D_W)) <= DI_dly((D_W -1) downto 0);
          MEMP((((wr_addr_var)*P_W) +(P_W-1)) downto ((wr_addr_var)*P_W)) <= DIP_dly((P_W -1) downto 0);

          wr_addr_var := (wr_addr_var + 1) mod addr_limit;
         
          if(wr_addr_var = 0) then
            wr_flag_var := NOT wr_flag_var;
          end if;
        end if; -- if((wren_var = '1') and (FULL_zd = '0') ....      

        if((wren_var = '1') and (full_int(1) = '1')) then 
            WRERR_zd <= '1';
        else
            WRERR_zd <= '0';
        end if;

        ALMOSTFULL_zd <= almostfull_int(3);
        if((((rdcount_var + addr_limit) <= (wr_addr_var + wr_offset_int)) and (rdcount_flag_var = wr_flag_var)) or ((rdcount_var <= (wr_addr_var + wr_offset_int)) and (rdcount_flag_var /= wr_flag_var))) then    
          almostfull_int(3) := '1';
          almostfull_int(2) := '1';
          almostfull_int(1) := '1';
          almostfull_int(0) := '1';
        elsif(almostfull_int(2)  = '0') then
          almostfull_int(3) := almostfull_int(0);
          almostfull_int(0) :=  '0';
        end if;
            

        FULL_zd <= full_int(1);
        if((rdcount_var = wr_addr_var) and (rdcount_flag_var /= wr_flag_var)) then
          full_int(1) := '1';
          full_int(0) := '1';
        else
          full_int(1) := full_int(0);
          full_int(0) := '0';
        end if;

        update_from_write_prcs <= NOT update_from_write_prcs;

        WRCOUNT_zd <= CONV_STD_LOGIC_VECTOR( wr_addr_var, MAX_WRCOUNT);

        wr_addr <= wr_addr_var;
        wr_flag <= wr_flag_var;

      end if; -- if(rising(WRCLK_dly))

    end if; -- if(GSR_dly = '1'))


    if(update_from_read_prcs'event) then
       rdcount_var := SLV_TO_INT(RDCOUNT_zd);
       rdcount_flag_var := rdcount_flag;
       if((((rdcount_var + addr_limit) > (wr_addr_var + wr_offset_int)) and (rdcount_flag_var = wr_flag_var)) or ((rdcount_var > (wr_addr_var + wr_offset_int)) and (rdcount_flag_var /= wr_flag_var))) then    
--         if(rden_var = '1') then
-- replaced the above line with line below
-- fp -- 09_10_03

           if(((rden_var = '1') and (EMPTY_zd = '0')) or ((((rd_addr_var + 1) mod addr_limit) = rdcount_var) and (almostfull_int(1) = '1'))) then
              almostfull_int(2) := almostfull_int(1);
              almostfull_int(1) := '0';
           end if;
       else
           almostfull_int(2) := '1';
           almostfull_int(1) := '1';
       end if;
    end if;

  end process prcs_write;

  
  -- matching HW behavior to pull up the unused output bits
  prcs_x_1_output: process (WRCOUNT_zd, RDCOUNT_zd, DO_zd, DOP_zd)
  begin  -- process prcs_x_1_output

    case DATA_WIDTH is
      when 4  => 
                WRCOUNT_OUT_zd <= WRCOUNT_zd;
                RDCOUNT_OUT_zd <= RDCOUNT_zd;
                DO_OUT_zd(3 downto 0) <= DO_zd(3 downto 0);
      when 9  =>
                WRCOUNT_OUT_zd(10 downto 0) <= WRCOUNT_zd(10 downto 0);
                RDCOUNT_OUT_zd(10 downto 0) <= RDCOUNT_zd(10 downto 0);
                DO_OUT_zd(7 downto 0) <= DO_zd(7 downto 0);
                DOP_OUT_zd(0 downto 0) <= DOP_zd(0 downto 0);
      when 18 =>
                WRCOUNT_OUT_zd(9 downto 0) <= WRCOUNT_zd(9 downto 0);
                RDCOUNT_OUT_zd(9 downto 0) <= RDCOUNT_zd(9 downto 0);
                DO_OUT_zd(15 downto 0) <= DO_zd(15 downto 0);
                DOP_OUT_zd(1 downto 0) <= DOP_zd(1 downto 0);
      when 36 => 
                WRCOUNT_OUT_zd(8 downto 0) <= WRCOUNT_zd(8 downto 0);
                RDCOUNT_OUT_zd(8 downto 0) <= RDCOUNT_zd(8 downto 0);
                DO_OUT_zd(31 downto 0) <= DO_zd(31 downto 0);
                DOP_OUT_zd(3 downto 0) <= DOP_zd(3 downto 0);
      when others =>
                WRCOUNT_OUT_zd <= WRCOUNT_zd;
                RDCOUNT_OUT_zd <= RDCOUNT_zd;
                DO_OUT_zd <= DO_zd;
    end case;
  end process prcs_x_1_output;

  
--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(ALMOSTEMPTY_zd, ALMOSTFULL_zd, DO_OUT_zd, DOP_OUT_zd, 
                      EMPTY_zd, FULL_zd, RDCOUNT_OUT_zd, RDERR_zd, 
                      WRCOUNT_OUT_zd, WRERR_zd)
  begin
      ALMOSTEMPTY <= ALMOSTEMPTY_zd	after SYNC_PATH_DELAY;
      ALMOSTFULL  <= ALMOSTFULL_zd	after SYNC_PATH_DELAY;
      DO          <= DO_OUT_zd		after SYNC_PATH_DELAY;
      DOP         <= DOP_OUT_zd		after SYNC_PATH_DELAY;
      EMPTY       <= EMPTY_zd		after SYNC_PATH_DELAY;
      FULL        <= FULL_zd		after SYNC_PATH_DELAY;
      RDCOUNT     <= RDCOUNT_OUT_zd 	after SYNC_PATH_DELAY;
      RDERR       <= RDERR_zd		after SYNC_PATH_DELAY;
      WRCOUNT     <= WRCOUNT_OUT_zd	after SYNC_PATH_DELAY;
      WRERR       <= WRERR_zd		after SYNC_PATH_DELAY;
  end process prcs_output;
--####################################################################


end FIFO16_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/frame_ecc_virtex4.vhd,v 1.5 2004/07/26 18:37:21 fphillip Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  
-- /___/   /\     Filename : FRAME_ECC_VIRTEX4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:03 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL FRAME_ECC_VIRTEX4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FRAME_ECC_VIRTEX4 is
  port(
    ERROR		: out std_ulogic;
    SYNDROME		: out std_logic_vector(11 downto 0);
    SYNDROMEVALID	: out std_ulogic
    );

end FRAME_ECC_VIRTEX4;

architecture FRAME_ECC_VIRTEX4_V of FRAME_ECC_VIRTEX4 is

begin
end FRAME_ECC_VIRTEX4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/gt11clk_mgt.vhd,v 1.7 2004/08/31 13:40:21 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  11-Gigabit Transceiver Clock
-- /___/   /\     Filename : GT11CLK_MGT.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:03 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL GT11CLK_MGT -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity GT11CLK_MGT is
  generic (
    SYNCLK1OUTEN : string := "ENABLE";
    SYNCLK2OUTEN : string := "DISABLE"
    );

  port (
    SYNCLK1OUT : out std_ulogic;
    SYNCLK2OUT : out std_ulogic;
    
    MGTCLKN : in std_ulogic;
    MGTCLKP : in std_ulogic
    );
end GT11CLK_MGT;

architecture GT11CLK_MGT_V of GT11CLK_MGT is
signal mgtclk_out : std_ulogic;
begin
  gen_mgtclk_out : process
  begin
    if ((MGTCLKP = '1') and (MGTCLKN = '0')) then
      mgtclk_out <= MGTCLKP;
    elsif ((MGTCLKP = '0') and (MGTCLKN = '1')) then
      mgtclk_out <= MGTCLKP;       
    end if;
    wait on MGTCLKN, MGTCLKP;
  end process;
  
  VitalBehavior : process
    variable first_time : boolean := true;

     
  begin
    if (first_time = true) then
      if((SYNCLK1OUTEN = "ENABLE") or (SYNCLK1OUTEN = "enable")) then
      elsif((SYNCLK1OUTEN = "DISABLE") or (SYNCLK1OUTEN = "disable")) then
      else
        assert FALSE report "Error : SYNCLK1OUTEN = is not ENABLE, DISABLE." severity warning;
      end if;

      if((SYNCLK2OUTEN = "ENABLE") or (SYNCLK2OUTEN = "enable")) then
      elsif((SYNCLK2OUTEN = "DISABLE") or (SYNCLK2OUTEN = "disable")) then
      else
        assert FALSE report "Error : SYNCLK2OUTEN = is not ENABLE, DISABLE." severity warning;
      end if;
      first_time := false;
    end if;
    wait;
  end process VitalBehavior;  

  schedule_outputs : process
    begin
    if ((SYNCLK1OUTEN = "ENABLE") or (SYNCLK1OUTEN = "enable")) then
      SYNCLK1OUT <= mgtclk_out;
    elsif((SYNCLK1OUTEN = "DISABLE") or (SYNCLK1OUTEN = "disable")) then
      SYNCLK1OUT <= 'Z';      
    else
    end if;           
           
    if ((SYNCLK2OUTEN = "ENABLE") or (SYNCLK2OUTEN = "enable")) then
      SYNCLK2OUT <= mgtclk_out;
    elsif((SYNCLK2OUTEN = "DISABLE") or (SYNCLK2OUTEN = "disable")) then
      SYNCLK2OUT <= 'Z';      
    else
    end if;           
           
    wait on mgtclk_out;
  end process schedule_outputs;
end GT11CLK_MGT_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/gt11clk.vhd,v 1.3 2004/08/31 13:40:21 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  11-Gigabit Transceiver Clock
-- /___/   /\     Filename : GT11CLK.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:03 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL GT11CLK -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity GT11CLK is
generic (
		REFCLKSEL : string := "MGTCLK";
		SYNCLK1OUTEN : string := "ENABLE";
		SYNCLK2OUTEN : string := "DISABLE"
  );

port (
		SYNCLK1OUT : out std_ulogic;
		SYNCLK2OUT : out std_ulogic;

		MGTCLKN : in std_ulogic;
		MGTCLKP : in std_ulogic;
		REFCLK : in std_ulogic;
		RXBCLK : in std_ulogic;
		SYNCLK1IN : in std_ulogic;
		SYNCLK2IN : in std_ulogic
     );
end GT11CLK;

architecture GT11CLK_V of GT11CLK is
signal mgtclk_out : std_ulogic;
signal mux_out : std_ulogic;

begin

  gen_mgtclk_out : process
  begin
    if ((MGTCLKP = '1') and (MGTCLKN = '0')) then
      mgtclk_out <= MGTCLKP;
    elsif ((MGTCLKP = '0') and (MGTCLKN = '1')) then
      mgtclk_out <= MGTCLKP;       
    end if;
    wait on MGTCLKN, MGTCLKP;
  end process;  
 
  VitalBehavior : process
    variable first_time : boolean := true;     
  begin
    if (first_time = true) then
      if((REFCLKSEL = "MGTCLK") or (REFCLKSEL = "mgtclk")) then
      elsif((REFCLKSEL = "SYNCLK1IN") or (REFCLKSEL = "synclk1in")) then
      elsif((REFCLKSEL = "SYNCLK2IN") or (REFCLKSEL = "synclk2in")) then
      elsif((REFCLKSEL = "REFCLK") or (REFCLKSEL = "grefclk")) then
      elsif((REFCLKSEL = "RXBCLK") or (REFCLKSEL = "rxbclk")) then
      else
        assert FALSE report "Error : REFCLKSEL = is not MGTCLK, SYNCLK1IN, SYNCLK2IN, REFCLK, RXBCLK." severity error;
      end if;
      
      if((SYNCLK1OUTEN = "ENABLE") or (SYNCLK1OUTEN = "enable")) then
      elsif((SYNCLK1OUTEN = "DISABLE") or (SYNCLK1OUTEN = "disable")) then
      else
        assert FALSE report "Error : SYNCLK1OUTEN = is not ENABLE, DISABLE." severity error;
      end if;

      if((SYNCLK2OUTEN = "ENABLE") or (SYNCLK2OUTEN = "enable")) then
      elsif((SYNCLK2OUTEN = "DISABLE") or (SYNCLK2OUTEN = "disable")) then
      else
        assert FALSE report "Error : SYNCLK2OUTEN = is not ENABLE, DISABLE." severity error;
      end if;
      first_time := false;
    end if;
    
    if (mgtclk_out'event) then
      if((REFCLKSEL = "MGTCLK") or (REFCLKSEL = "mgtclk")) then
        mux_out <= mgtclk_out;
      end if;          
    end if;

    if (SYNCLK1IN'event) then
      if((REFCLKSEL = "SYNCLK1IN") or (REFCLKSEL = "synclk1in")) then
        mux_out <= SYNCLK1IN;
      end if;          
    end if;

    if (SYNCLK2IN'event) then
      if((REFCLKSEL = "SYNCLK2IN") or (REFCLKSEL = "synclk2in")) then
        mux_out <= SYNCLK2IN;
      end if;          
    end if;    

    if (REFCLK'event) then
      if((REFCLKSEL = "REFCLK") or (REFCLKSEL = "refclk")) then
        mux_out <= REFCLK;
      end if;      
    end if;

    if (RXBCLK'event) then
      if((REFCLKSEL = "RXBCLK") or (REFCLKSEL = "RXBCLK")) then
        mux_out <= RXBCLK;
      end if;          
    end if;        
    wait on mgtclk_out, SYNCLK1IN, SYNCLK2IN, REFCLK, RXBCLK;        
  end process VitalBehavior;

  schedule_outputs : process
    begin
    if ((SYNCLK1OUTEN = "ENABLE") or (SYNCLK1OUTEN = "enable")) then
      SYNCLK1OUT <= mux_out;
    elsif((SYNCLK1OUTEN = "DISABLE") or (SYNCLK1OUTEN = "disable")) then
      SYNCLK1OUT <= 'Z';      
    else
    end if;           
           
    if ((SYNCLK2OUTEN = "ENABLE") or (SYNCLK2OUTEN = "enable")) then
      SYNCLK2OUT <= mux_out;
    elsif((SYNCLK2OUTEN = "DISABLE") or (SYNCLK2OUTEN = "disable")) then
      SYNCLK2OUT <= 'Z';      
    else
    end if;           
           
    wait on mux_out;
  end process schedule_outputs;
end GT11CLK_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/icap_virtex4.vhd,v 1.5 2004/04/29 21:21:50 fphillip Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Internal Configuration Access Port for Virtex4
-- /___/   /\     Filename : ICAP_VIRTEX4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:04 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL ICAP_VIRTEX4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

entity ICAP_VIRTEX4 is
  generic(
    ICAP_WIDTH : string := "X8"
    );


  port(
    BUSY : out std_ulogic;
    O    : out std_logic_vector(31 downto 0);

    CE    : in std_ulogic;
    CLK   : in std_ulogic;
    I     : in std_logic_vector(31 downto 0);
    WRITE : in std_ulogic
    );

end ICAP_VIRTEX4;

architecture ICAP_VIRTEX4_V of ICAP_VIRTEX4 is

begin
end ICAP_VIRTEX4_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                  Dual Data Rate Input D Flip-Flop
-- /___/   /\     Filename : IDDR.vhd
-- \   \  /  \    Timestamp : Fri Mar 26 08:18:20 PST 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IDDR -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;


library unisim;
use unisim.vpkg.all;

entity IDDR is

  generic(

      DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
      INIT_Q1      : bit    := '0';
      INIT_Q2      : bit    := '0';
      SRTYPE       : string := "SYNC"
      );

  port(
      Q1          : out std_ulogic;
      Q2          : out std_ulogic;

      C           : in  std_ulogic;
      CE          : in  std_ulogic;
      D           : in  std_ulogic;
      R           : in  std_ulogic;
      S           : in  std_ulogic
    );

end IDDR;

architecture IDDR_V OF IDDR is


  constant SYNC_PATH_DELAY : time := 100 ps;

  signal C_ipd	        : std_ulogic := 'X';
  signal CE_ipd	        : std_ulogic := 'X';
  signal D_ipd	        : std_ulogic := 'X';
  signal GSR            : std_ulogic := '0';
  signal GSR_ipd	: std_ulogic := 'X';
  signal R_ipd		: std_ulogic := 'X';
  signal S_ipd		: std_ulogic := 'X';

  signal C_dly	        : std_ulogic := 'X';
  signal CE_dly	        : std_ulogic := 'X';
  signal D_dly	        : std_ulogic := 'X';
  signal GSR_dly	: std_ulogic := 'X';
  signal R_dly		: std_ulogic := 'X';
  signal S_dly		: std_ulogic := 'X';

  signal Q1_zd	        : std_ulogic := 'X';
  signal Q2_zd	        : std_ulogic := 'X';

  signal Q1_viol        : std_ulogic := 'X';
  signal Q2_viol        : std_ulogic := 'X';

  signal Q1_o_reg	: std_ulogic := 'X';
  signal Q2_o_reg	: std_ulogic := 'X';
  signal Q3_o_reg	: std_ulogic := 'X';
  signal Q4_o_reg	: std_ulogic := 'X';

  signal ddr_clk_edge_type	: integer := -999;
  signal sr_type		: integer := -999;
begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  C_dly          	 <= C              	after 0 ps;
  CE_dly         	 <= CE             	after 0 ps;
  D_dly          	 <= D              	after 0 ps;
  GSR_dly        	 <= GSR            	after 0 ps;
  R_dly          	 <= R              	after 0 ps;
  S_dly          	 <= S              	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process

  begin
      if((DDR_CLK_EDGE = "OPPOSITE_EDGE") or (DDR_CLK_EDGE = "opposite_edge")) then
         ddr_clk_edge_type <= 1;
      elsif((DDR_CLK_EDGE = "SAME_EDGE") or (DDR_CLK_EDGE = "same_edge")) then
         ddr_clk_edge_type <= 2;
      elsif((DDR_CLK_EDGE = "SAME_EDGE_PIPELINED") or (DDR_CLK_EDGE = "same_edge_pipelined")) then
         ddr_clk_edge_type <= 3;
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " DDR_CLK_EDGE ",
             EntityName => "/IDDR",
             GenericValue => DDR_CLK_EDGE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " OPPOSITE_EDGE or SAME_EDGE or  SAME_EDGE_PIPELINED.",
             TailMsg => "",
             MsgSeverity => ERROR 
         );
      end if;

      if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
         sr_type <= 1;
      elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
         sr_type <= 2;
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " SRTYPE ",
             EntityName => "/IDDR",
             GenericValue => SRTYPE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " ASYNC or SYNC. ",
             TailMsg => "",
             MsgSeverity => ERROR
         );
      end if;

     wait;
  end process prcs_init;
--####################################################################
--#####                    q1_q2_q3_q4 reg                       #####
--####################################################################
  prcs_q1q2q3q4_reg:process(C_dly, D_dly, GSR_dly, R_dly, S_dly)
  variable Q1_var : std_ulogic := TO_X01(INIT_Q1);
  variable Q2_var : std_ulogic := TO_X01(INIT_Q2);
  variable Q3_var : std_ulogic := TO_X01(INIT_Q1);
  variable Q4_var : std_ulogic := TO_X01(INIT_Q2);
  begin
     if(GSR_dly = '1') then
         Q1_var := TO_X01(INIT_Q1);
         Q3_var := TO_X01(INIT_Q1);
         Q2_var := TO_X01(INIT_Q2);
         Q4_var := TO_X01(INIT_Q2);
     elsif(GSR_dly = '0') then
        case sr_type is
           when 1 => 
                   if(R_dly = '1') then
                      Q1_var := '0';
                      Q2_var := '0';
                      Q3_var := '0';
                      Q4_var := '0';
                   elsif((R_dly = '0') and (S_dly = '1')) then
                      Q1_var := '1';
                      Q2_var := '1';
                      Q3_var := '1';
                      Q4_var := '1';
                   elsif((R_dly = '0') and (S_dly = '0')) then
                      if(CE_dly = '1') then
                         if(rising_edge(C_dly)) then
                            Q3_var := Q1_var;
                            Q1_var := D_dly;
                            Q4_var := Q2_var;
                         end if;
                         if(falling_edge(C_dly)) then
                            Q2_var := D_dly;
                         end if;
                      end if;
                   end if;

           when 2 => 
                   if(rising_edge(C_dly)) then
                      if(R_dly = '1') then
                         Q1_var := '0';
                         Q3_var := '0';
                         Q4_var := '0';
                      elsif((R_dly = '0') and (S_dly = '1')) then
                         Q1_var := '1';
                         Q3_var := '1';
                         Q4_var := '1';
                      elsif((R_dly = '0') and (S_dly = '0')) then
                         if(CE_dly = '1') then
                               Q3_var := Q1_var;
                               Q1_var := D_dly;
                               Q4_var := Q2_var;
                         end if;
                      end if;
                   end if;
                        
                   if(falling_edge(C_dly)) then
                      if(R_dly = '1') then
                         Q2_var := '0';
                      elsif((R_dly = '0') and (S_dly = '1')) then
                         Q2_var := '1';
                      elsif((R_dly = '0') and (S_dly = '0')) then
                         if(CE_dly = '1') then
                               Q2_var := D_dly;
                         end if;
                      end if;
                   end if;
 
           when others =>
                   null; 
        end case;
     end if;

     q1_o_reg <= Q1_var;
     q2_o_reg <= Q2_var;
     q3_o_reg <= Q3_var;
     q4_o_reg <= Q4_var;

  end process prcs_q1q2q3q4_reg;
--####################################################################
--#####                        q1 & q2  mux                      #####
--####################################################################
  prcs_q1q2_mux:process(q1_o_reg, q2_o_reg, q3_o_reg, q4_o_reg)
  begin
     case ddr_clk_edge_type is
        when 1 => 
                 Q1_zd <= q1_o_reg;
                 Q2_zd <= q2_o_reg;
        when 2 => 
                 Q1_zd <= q1_o_reg;
                 Q2_zd <= q4_o_reg;
       when 3 => 
                 Q1_zd <= q3_o_reg;
                 Q2_zd <= q4_o_reg;
       when others =>
                 null;
     end case;
  end process prcs_q1q2_mux;
--####################################################################

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(Q1_zd, Q2_zd)
  begin
      Q1 <= Q1_zd after SYNC_PATH_DELAY;
      Q2 <= Q2_zd after SYNC_PATH_DELAY;
  end process prcs_output;
--####################################################################


end IDDR_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                  Input Delay Controller
-- /___/   /\     Filename : IDELAYCTRL.vhd
-- \   \  /  \    Timestamp : Fri Mar 26 08:18:20 PST 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    09/12/06 - intialized output # 234140
--    04/10/07 - CR 436682 fix, disable activity when rst is high
-- End Revision

----- CELL IDELAYCTRL -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;


library unisim;
use unisim.vpkg.all;

entity IDELAYCTRL is

  port(
      RDY	: out std_ulogic;

      REFCLK	: in  std_ulogic;
      RST	: in  std_ulogic
  );

end IDELAYCTRL;

architecture IDELAYCTRL_V OF IDELAYCTRL is


  constant SYNC_PATH_DELAY : time := 100 ps;

  signal REFCLK_ipd	: std_ulogic := 'X';
  signal RST_ipd	: std_ulogic := 'X';

  signal GSR_dly	: std_ulogic := '0';
  signal REFCLK_dly	: std_ulogic := 'X';
  signal RST_dly	: std_ulogic := 'X';

  signal RDY_zd		: std_ulogic := '0';
  signal RDY_viol	: std_ulogic := 'X';

-- taken from DCM_adv
  signal period : time := 0 ps;
-- CR 234140
  signal lost   : std_ulogic := '1';
  signal lost_r : std_ulogic := '0';
  signal lost_f : std_ulogic := '0';
  signal clock_negedge, clock_posedge, clock : std_ulogic;
  signal temp1 : boolean := false;
  signal temp2 : boolean := false;
  signal clock_low, clock_high : std_ulogic := '0';


begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  REFCLK_dly     	 <= REFCLK         	after 0 ps;
  RST_dly        	 <= RST            	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                             RDY                          #####
--####################################################################
   prcs_rdy:process(RST_dly, lost)
   begin
      if((RST_dly = '1') or (lost = '1')) then
         RDY_zd <= '0';
--    CR 436682 fix
--      elsif((RST_dly'event) and (RST_dly = '0') and (lost = '0')) then
      elsif((RST_dly = '0') and (lost = '0')) then
         RDY_zd <= '1';
      end if;
   end process prcs_rdy;
--####################################################################
--#####                prcs_determine_period                     #####
--####################################################################
  prcs_determine_period : process
    variable clock_edge_previous : time := 0 ps;
    variable clock_edge_current  : time := 0 ps;
  begin
    if (RST_dly = '0' ) then
      if (rising_edge(REFCLK_dly)) then
        clock_edge_previous := clock_edge_current;
        clock_edge_current := NOW;
        if (period /= 0 ps and ((clock_edge_current - clock_edge_previous) <= (1.5 * period))) then
          period <= NOW - clock_edge_previous;
        elsif (period /= 0 ps and ((NOW - clock_edge_previous) > (1.5 * period))) then
          period <= 0 ps;
        elsif ((period = 0 ps) and (clock_edge_previous /= 0 ps)) then
          period <= NOW - clock_edge_previous;
        end if;
      end if;
    end if;
    wait on REFCLK_dly;
  end process prcs_determine_period;

--####################################################################
--#####                prcs_clock_lost_checker                   #####
--####################################################################
  prcs_clock_lost_checker : process
    variable clock_low, clock_high : std_ulogic := '0';

  begin
    if (rising_edge(REFCLK_dly)) then
      clock_low := '0';
      clock_high := '1';
      clock_posedge <= '0';
      clock_negedge <= '1';
    end if;

    if (falling_edge(REFCLK_dly)) then
      clock_high := '0';
      clock_low := '1';
      clock_posedge <= '1';
      clock_negedge <= '0';
    end if;
    wait on REFCLK_dly;
  end process prcs_clock_lost_checker;

--####################################################################
--#####                prcs_set_reset_lost_r                     #####
--####################################################################
  prcs_set_reset_lost_r : process
    begin
    if (rising_edge(REFCLK_dly)) then
      if (period /= 0 ps) then
        lost_r <= '0';
      end if;
      wait for (period * 9.1)/10;
      if ((clock_low /= '1') and (clock_posedge /= '1')) then
        lost_r <= '1';
      end if;
    end if;
    wait on REFCLK_dly;
  end process prcs_set_reset_lost_r;

--####################################################################
--#####                     prcs_assign_lost                     #####
--####################################################################
  prcs_assign_lost : process
    begin
      if (lost_r'event) then
        lost <= lost_r;
      end if;
      if (lost_f'event) then
        lost <= lost_f;
      end if;
      wait on lost_r, lost_f;
    end process prcs_assign_lost;

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(RDY_zd)
  begin
      RDY <= RDY_zd after SYNC_PATH_DELAY;
  end process prcs_output;
--####################################################################


end IDELAYCTRL_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                  Input Delay Line
-- /___/   /\     Filename : IDELAY.vhd
-- \   \  /  \    Timestamp : Thu Mar 17 16:56:02 PST 2005
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    03/17/05 - Changed SIM_TAPDELAY_VALUE to 75 ps from 78 ps -- CR 204824 --FP
--    06/14/05 - Fixed VitalPathDelay constructs  -- CR 209786 --FP
--    08/08/05 - Made tap count to wrap around  -- CR 213995 --FP
--    07/18/06 - CR 234556 fix. Added SIM_DELAY_D --FP
--    12/29/06 - CR 430648 Simprim fix. For fixed/default, delay is annotated via sdf.
-- End Revision
----- CELL IDELAY -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;


library unisim;
use unisim.vpkg.all;

entity IDELAY is

  generic(

      IOBDELAY_TYPE  : string := "DEFAULT";
      IOBDELAY_VALUE : integer := 0
      );

  port(
      O      : out std_ulogic;

      C      : in  std_ulogic;
      CE     : in  std_ulogic;
      I      : in  std_ulogic;
      INC    : in  std_ulogic;
      RST    : in  std_ulogic
      );

end IDELAY;

architecture IDELAY_V OF IDELAY is

  constant SIM_TAPDELAY_VALUE : integer := 75;

  ---------------------------------------------------------
  -- Function  str_2_int converts string to integer
  ---------------------------------------------------------
  function str_2_int(str: in string ) return integer is
  variable int : integer;
  variable val : integer := 0;
  variable neg_flg   : boolean := false;
  variable is_it_int : boolean := true;
  begin
    int := 0;
    val := 0;
    is_it_int := true;
    neg_flg   := false;

    for i in  1 to str'length loop
      case str(i) is
         when  '-'
           =>
             if(i = 1) then
                neg_flg := true;
                val := -1;
             end if;
         when  '1'
           =>  val := 1;
         when  '2'
           =>   val := 2;
         when  '3'
           =>   val := 3;
         when  '4'
           =>   val := 4;
         when  '5'
           =>   val := 5;
         when  '6'
           =>   val := 6;
         when  '7'
           =>   val := 7;
         when  '8'
           =>   val := 8;
         when  '9'
           =>   val := 9;
         when  '0'
           =>   val := 0;
         when others
           => is_it_int := false;
        end case;
        if(val /= -1) then
          int := int *10  + val;
        end if;
        val := 0;
    end loop;
    if(neg_flg) then
      int := int * (-1);
    end if;

    if(NOT is_it_int) then
      int := -9999;
    end if;
    return int;
  end;
-----------------------------------------------------------

  constant	SYNC_PATH_DELAY	: time := 0 ps;

  constant	MIN_TAP_COUNT	: integer := 0;
  constant	MAX_TAP_COUNT	: integer := 63;

  signal	C_ipd		: std_ulogic := 'X';
  signal	CE_ipd		: std_ulogic := 'X';
  signal	GSR_ipd		: std_ulogic := 'X';
  signal	I_ipd		: std_ulogic := 'X';
  signal	INC_ipd		: std_ulogic := 'X';
  signal	RST_ipd		: std_ulogic := 'X';

  signal	C_dly		: std_ulogic := 'X';
  signal	CE_dly		: std_ulogic := 'X';
  signal	GSR_dly		: std_ulogic := '0';
  signal	I_dly		: std_ulogic := 'X';
  signal	INC_dly		: std_ulogic := 'X';
  signal	RST_dly		: std_ulogic := 'X';

  signal	O_zd		: std_ulogic := 'X';
  signal	O_viol		: std_ulogic := 'X';

  signal	TapCount	: integer := 0;
  signal	IsTapDelay	: boolean := true; 
  signal	IsTapFixed	: boolean := false; 
  signal	IsTapDefault	: boolean := false; 
  signal	Delay		: time := 0 ps; 

begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  C_dly          	 <= C              	after 0 ps;
  CE_dly         	 <= CE             	after 0 ps;
  I_dly          	 <= I              	after 0 ps;
  INC_dly        	 <= INC            	after 0 ps;
  RST_dly        	 <= RST            	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process
  variable TapCount_var   : integer := 0;
  variable IsTapDelay_var : boolean := true; 
  variable IsTapFixed_var : boolean := false; 
  variable IsTapDefault_var : boolean := false; 
  begin
--     if((IOBDELAY_VALUE = "OFF") or (IOBDELAY_VALUE = "off")) then
--        IsTapDelay_var := false;
--     elsif((IOBDELAY_VALUE = "ON") or (IOBDELAY_VALUE = "on")) then
--        IsTapDelay_var := false;
--     else
--       TapCount_var := str_2_int(IOBDELAY_VALUE); 
       TapCount_var := IOBDELAY_VALUE; 
       If((TapCount_var >= 0) and (TapCount_var <= 63)) then 
         IsTapDelay_var := true;

       else
          GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " IOBDELAY_VALUE ",
             EntityName => "/IOBDELAY_VALUE",
             GenericValue => IOBDELAY_VALUE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " OFF, 1, 2, ..., 62, 63 ",
             TailMsg => "",
             MsgSeverity => failure 
          );
        end if;
--     end if;

     if(IsTapDelay_var) then
        if((IOBDELAY_TYPE = "FIXED") or (IOBDELAY_TYPE = "fixed")) then
           IsTapFixed_var := true;
        elsif((IOBDELAY_TYPE = "VARIABLE") or (IOBDELAY_TYPE = "variable")) then
           IsTapFixed_var := false;
        elsif((IOBDELAY_TYPE = "DEFAULT") or (IOBDELAY_TYPE = "default")) then
           IsTapDefault_var := true;
        else
          GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " IOBDELAY_TYPE ",
             EntityName => "/IOBDELAY_TYPE",
             GenericValue => IOBDELAY_TYPE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " FIXED or VARIABLE ",
             TailMsg => "",
             MsgSeverity => failure 
          );
        end if; 
     end if; 

     IsTapDelay   <= IsTapDelay_var;
     IsTapFixed   <= IsTapFixed_var;
     IsTapDefault <= IsTapDefault_var;
     TapCount     <= TapCount_var;

     wait;
  end process prcs_init;
--####################################################################
--#####                  CALCULATE DELAY                         #####
--####################################################################
  prcs_refclk:process(C_dly, GSR_dly, RST_dly)
  variable TapCount_var : integer :=0;
  variable FIRST_TIME   : boolean :=true;
  variable BaseTime_var : time    := 1 ps ;
  variable delay_var    : time    := 0 ps ;
  begin
     if(IsTapDelay) then
       if((GSR_dly = '1') or (FIRST_TIME))then
          TapCount_var := TapCount; 
          Delay        <= TapCount_var * SIM_TAPDELAY_VALUE * BaseTime_var; 
          FIRST_TIME   := false;
       elsif(GSR_dly = '0') then
          if(rising_edge(C_dly)) then
             if(RST_dly = '1') then
               TapCount_var := TapCount; 
             elsif((RST_dly = '0') and (CE_dly = '1')) then
-- CR fix CR 213995
                  if(INC_dly = '1') then
                     if (TapCount_var < MAX_TAP_COUNT) then
                        TapCount_var := TapCount_var + 1;
                     else 
                        TapCount_var := MIN_TAP_COUNT;
                     end if;
                  elsif(INC_dly = '0') then
                     if (TapCount_var > MIN_TAP_COUNT) then
                         TapCount_var := TapCount_var - 1;
                     else
                         TapCount_var := MAX_TAP_COUNT;
                     end if;
                         
                  end if; -- INC_dly
             end if; -- RST_dly
             Delay <= TapCount_var *  SIM_TAPDELAY_VALUE * BaseTime_var;
          end if; -- C_dly
       end if; -- GSR_dly

     end if; -- IsTapDelay 
  end process prcs_refclk;


--####################################################################
--#####                      DELAY INPUT                         #####
--####################################################################
  prcs_i:process(I_dly)
  begin
     if(IsTapFixed) then
       O_zd <= transport I_dly after (TapCount *SIM_TAPDELAY_VALUE * 1 ps);
     else
        O_zd <= transport I_dly after delay;
     end if;
  end process prcs_i;

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(O_zd)
  begin
      O <= O_zd after SYNC_PATH_DELAY;
  end process prcs_output;
--####################################################################


end IDELAY_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                  Source Synchronous Input Deserializer
-- /___/   /\     Filename : ISERDES.vhd
-- \   \  /  \    Timestamp : Fri Mar 26 08:18:20 PST 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    05/29/06 - CR 232324 -- Added  timing checks for SR/REV wrt negedge CLKDIV
--    07/19/06 - CR 234556 fix. Added sim_DELAY_D, sim_SETUP_D_CLK and sim_HOLD_D_CLK --FP
--    10/13/06 - CR 426606 fix
--    08/29/07 - CR 447556 Fixed attribute INTERFACE_TYPE to be case insensitive 
--    09/10/07 - CR 447760 Added Strict DRC for BITSLIP and INTERFACE_TYPE combinations
-- End Revision
----- CELL ISERDES -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;


library unisim;
use unisim.vpkg.all;
use unisim.vcomponents.all;

--//////////////////////////////////////////////////////////// 
--////////////////////////// BSCNTRL /////////////////////////
--//////////////////////////////////////////////////////////// 
entity bscntrl is
  generic(
      SRTYPE        : string;
      INIT_BITSLIPCNT	: bit_vector(3 downto 0)
      );
  port(
      CLKDIV_INT	: out std_ulogic;
      MUXC		: out std_ulogic;

      BITSLIP		: in std_ulogic;
      C23		: in std_ulogic;
      C45		: in std_ulogic;
      C67		: in std_ulogic;
      CLK		: in std_ulogic;
      CLKDIV		: in std_ulogic;
      DATA_RATE		: in std_ulogic;
      GSR		: in std_ulogic;
      R			: in std_ulogic;
      SEL		: in std_logic_vector (1 downto 0)
      );
           
end bscntrl;

architecture bscntrl_V of bscntrl is
--  constant DELAY_FFBSC		: time       := 300 ns;
--  constant DELAY_MXBSC		: time       := 60  ns;
  constant DELAY_FFBSC			: time       := 300 ps;
  constant DELAY_MXBSC			: time       := 60  ps;

  signal AttrSRtype		: integer := 0;

  signal q1			: std_ulogic := 'X';
  signal q2			: std_ulogic := 'X';
  signal q3			: std_ulogic := 'X';
  signal mux			: std_ulogic := 'X';
  signal qhc1			: std_ulogic := 'X';
  signal qhc2			: std_ulogic := 'X';
  signal qlc1			: std_ulogic := 'X';
  signal qlc2			: std_ulogic := 'X';
  signal qr1			: std_ulogic := 'X';
  signal qr2			: std_ulogic := 'X';
  signal mux1			: std_ulogic := 'X';
  signal clkdiv_zd		: std_ulogic := 'X';

begin
--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process
  begin

     if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
        AttrSrtype <= 0;
     elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
        AttrSrtype <= 1;
     end if;

     wait;
  end process prcs_init;
--####################################################################
--#####              Divide by 2 - 8 counter                     #####
--####################################################################
  prcs_div_2_8_cntr:process(qr2, CLK, GSR)
  variable clkdiv_int_var	:  std_ulogic := TO_X01(INIT_BITSLIPCNT(0));
  variable q1_var		:  std_ulogic := TO_X01(INIT_BITSLIPCNT(1));
  variable q2_var		:  std_ulogic := TO_X01(INIT_BITSLIPCNT(2));
  variable q3_var		:  std_ulogic := TO_X01(INIT_BITSLIPCNT(3));
  begin
     if(GSR = '1') then
         clkdiv_int_var	:= TO_X01(INIT_BITSLIPCNT(0));
         q1_var		:= TO_X01(INIT_BITSLIPCNT(1));
         q2_var		:= TO_X01(INIT_BITSLIPCNT(2));
         q3_var		:= TO_X01(INIT_BITSLIPCNT(3));
     elsif(GSR = '0') then
        case AttrSRtype is
           when 0 => 
           --------------- // async SET/RESET
                   if(qr2 = '1') then
                      clkdiv_int_var := '0';
                      q1_var := '0';
                      q2_var := '0';
                      q3_var := '0';
                   elsif (qhc1 = '1') then
                      clkdiv_int_var := clkdiv_int_var;
                      q1_var := q1_var;
                      q2_var := q2_var;
                      q3_var := q3_var;
                   else
                      if(rising_edge(CLK)) then
                         q3_var := q2_var;
                         q2_var :=( NOT((NOT clkdiv_int_var) and (NOT q2_var)) and q1_var);
                         q1_var := clkdiv_int_var;
                         clkdiv_int_var := mux;
                      end if;
                   end if;

           when 1 => 
           --------------- // sync SET/RESET
                   if(rising_edge(CLK)) then
                      if(qr2 = '1') then
                         clkdiv_int_var := '0';
                         q1_var := '0';
                         q2_var := '0';
                         q3_var := '0';
                      elsif (qhc1 = '1') then
                         clkdiv_int_var := clkdiv_int_var;
                         q1_var := q1_var;
                         q2_var := q2_var;
                         q3_var := q3_var;
                      else
                         q3_var := q2_var;
                         q2_var :=( NOT((NOT clkdiv_int_var) and (NOT q2_var)) and q1_var);
                         q1_var := clkdiv_int_var;
                         clkdiv_int_var := mux;
                      end if;
                   end if;

           when others => 
                   null;
           end case;


     end if;

     q1 <= q1_var after DELAY_FFBSC;
     q2 <= q2_var after DELAY_FFBSC;
     q3 <= q3_var after DELAY_FFBSC;
     clkdiv_zd <= clkdiv_int_var after DELAY_FFBSC;

  end process prcs_div_2_8_cntr;
--####################################################################
--#####          Divider selections and 4:1 selector mux         #####
--####################################################################
  prcs_mux_sel:process(sel, c23 , c45 , c67 , clkdiv_zd , q1 , q2 , q3)
  begin
    case sel is
        when "00" =>
              mux <= NOT (clkdiv_zd or  (c23 and q1)) after DELAY_MXBSC;
        when "01" =>
              mux <= NOT (q1 or (c45 and q2)) after DELAY_MXBSC;
        when "10" =>
              mux <= NOT (q2 or (c67 and q3)) after DELAY_MXBSC;
        when "11" =>
              mux <= NOT (q3) after DELAY_MXBSC;
        when others =>
              mux <= NOT (clkdiv_zd or  (c23 and q1)) after DELAY_MXBSC;
    end case;
  end process prcs_mux_sel;
--####################################################################
--#####                  Bitslip control logic                   #####
--####################################################################
  prcs_logictrl:process(qr1, clkdiv)
  begin
      case AttrSRtype is
          when 0 => 
           --------------- // async SET/RESET
               if(qr1 = '1') then
                 qlc1        <= '0' after DELAY_FFBSC;
                 qlc2        <= '0' after DELAY_FFBSC;
               elsif(bitslip = '0') then
                 qlc1        <= qlc1 after DELAY_FFBSC;
                 qlc2        <= '0'  after DELAY_FFBSC;
               else 
                   if(rising_edge(clkdiv)) then
                      qlc1      <= NOT qlc1 after DELAY_FFBSC;
                      qlc2      <= (bitslip and mux1) after DELAY_FFBSC;
                   end if;
               end if;

          when 1 => 
           --------------- // sync SET/RESET
               if(rising_edge(clkdiv)) then
                  if(qr1 = '1') then
                    qlc1        <= '0' after DELAY_FFBSC;
                    qlc2        <= '0' after DELAY_FFBSC;
                  elsif(bitslip = '0') then
                    qlc1        <= qlc1 after DELAY_FFBSC;
                    qlc2        <= '0'  after DELAY_FFBSC;
                  else 
                    qlc1      <= NOT qlc1 after DELAY_FFBSC;
                    qlc2      <= (bitslip and mux1) after DELAY_FFBSC;
                  end if;
               end if;
          when others => 
                  null;
      end case;
  end process  prcs_logictrl;

--####################################################################
--#####        Mux to select between sdr "0" and ddr "1"         #####
--####################################################################
  prcs_sdr_ddr_mux:process(qlc1, DATA_RATE)
  begin
    case DATA_RATE is
        when '0' =>
             mux1 <= qlc1 after DELAY_MXBSC;
        when '1' =>
             mux1 <= '1' after DELAY_MXBSC;
        when others =>
             null;
    end case;
  end process  prcs_sdr_ddr_mux;

--####################################################################
--#####                       qhc1 and qhc2                      #####
--####################################################################
  prcs_qhc1_qhc2:process(qr2, CLK)
  begin
-- FP TMP -- should CLK and q2 have to be rising_edge
     case AttrSRtype is
        when 0 => 
         --------------- // async SET/RESET
             if(qr2 = '1') then
                qhc1 <= '0' after DELAY_FFBSC;
                qhc2 <= '0' after DELAY_FFBSC;
             elsif(rising_edge(CLK)) then
                qhc1 <= (qlc2 and (NOT qhc2)) after DELAY_FFBSC;
                qhc2 <= qlc2 after DELAY_FFBSC;
             end if;

        when 1 => 
         --------------- // sync SET/RESET
             if(rising_edge(CLK)) then
                if(qr2 = '1') then
                   qhc1 <= '0' after DELAY_FFBSC;
                   qhc2 <= '0' after DELAY_FFBSC;
                else
                   qhc1 <= (qlc2 and (NOT qhc2)) after DELAY_FFBSC;
                   qhc2 <= qlc2 after DELAY_FFBSC;
                end if;
             end if;

        when others =>
             null;
     end case;

  end process  prcs_qhc1_qhc2;

--####################################################################
--#####     Mux drives ctrl lines of mux in front of 2nd rnk FFs  ####
--####################################################################
  prcs_muxc:process(mux1, DATA_RATE)
  begin
    case DATA_RATE is
        when '0' =>
             muxc <= mux1 after DELAY_MXBSC;
        when '1' =>
             muxc <= '0'  after DELAY_MXBSC;
        when others =>
             null;
    end case;
  end process  prcs_muxc;

--####################################################################
--#####                       Asynchronous set flops             #####
--####################################################################
  prcs_qr1:process(R, CLKDIV)
  begin
-- FP TMP -- should CLKDIV and R have to be rising_edge
     case AttrSRtype is
        when 0 => 
         --------------- // async SET/RESET
             if(R = '1') then
                qr1        <= '1' after DELAY_FFBSC;
             elsif(rising_edge(CLKDIV)) then
                qr1        <= '0' after DELAY_FFBSC;
             end if;

        when 1 => 
         --------------- // sync SET/RESET
             if(rising_edge(CLKDIV)) then
                if(R = '1') then
                   qr1        <= '1' after DELAY_FFBSC;
                else
                   qr1        <= '0' after DELAY_FFBSC;
                end if;
             end if;

        when others => 
             null;
     end case;
  end process  prcs_qr1;
----------------------------------------------------------------------
  prcs_qr2:process(R, CLK)
  begin
-- FP TMP -- should CLK and R have to be rising_edge
     case AttrSRtype is
        when 0 => 
         --------------- // async SET/RESET
             if(R = '1') then
                qr2        <= '1' after DELAY_FFBSC;
             elsif(rising_edge(CLK)) then
                qr2        <= qr1 after DELAY_FFBSC;
             end if;

        when 1 => 
         --------------- // sync SET/RESET
             if(rising_edge(CLK)) then
                if(R = '1') then
                   qr2        <= '1' after DELAY_FFBSC;
                else
                   qr2        <= qr1 after DELAY_FFBSC;
                end if;
             end if;

        when others => 
             null;
     end case;
  end process  prcs_qr2;
--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(clkdiv_zd)
  begin
      CLKDIV_INT <= clkdiv_zd;
  end process prcs_output;
--####################################################################
end bscntrl_V;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;


library unisim;
use unisim.vpkg.all;
use unisim.vcomponents.all;

--//////////////////////////////////////////////////////////// 
--//////////////////////// ICE MODULE ////////////////////////
--//////////////////////////////////////////////////////////// 

entity ice_module is
  generic(
      SRTYPE  : string;
      INIT_CE : bit_vector(1 downto 0)
      );
  port(
      ICE		: out std_ulogic;

      CE1		: in std_ulogic;
      CE2		: in std_ulogic;
      GSR		: in std_ulogic;
      NUM_CE		: in std_ulogic;
      CLKDIV		: in std_ulogic;
      R			: in std_ulogic
      );
end ice_module;

architecture ice_V of ice_module is
--  constant DELAY_FFICE		: time := 300 ns;
--  constant DELAY_MXICE		: time := 60 ns;
  constant DELAY_FFICE			: time := 300 ps;
  constant DELAY_MXICE			: time := 60 ps;

  signal AttrSRtype		: integer := 0;

  signal ce1r			: std_ulogic := 'X';
  signal ce2r			: std_ulogic := 'X';
  signal cesel			: std_logic_vector(1 downto 0) := (others => 'X');

  signal ice_zd			: std_ulogic := 'X';

begin

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process
  begin

     if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
        AttrSrtype <= 0;
     elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
        AttrSrtype <= 1;
     end if;

     wait;
  end process prcs_init;

--###################################################################
--#####                      update cesel                       #####
--###################################################################

  cesel  <= NUM_CE & CLKDIV; 

--####################################################################
--#####                         registers                        #####
--####################################################################
  prcs_reg:process(CLKDIV, GSR)
  variable ce1r_var		:  std_ulogic := TO_X01(INIT_CE(1));
  variable ce2r_var		:  std_ulogic := TO_X01(INIT_CE(0));
  begin
     if(GSR = '1') then
         ce1r_var		:= TO_X01(INIT_CE(1));
         ce2r_var		:= TO_X01(INIT_CE(0));
     elsif(GSR = '0') then
        case AttrSRtype is
           when 0 => 
            --------------- // async SET/RESET
                if(R = '1') then
                   ce1r_var := '0';
                   ce2r_var := '0';
                elsif(rising_edge(CLKDIV)) then
                   ce1r_var := ce1;
                   ce2r_var := ce2;
                end if;

           when 1 => 
            --------------- // sync SET/RESET
                if(rising_edge(CLKDIV)) then
                   if(R = '1') then
                      ce1r_var := '0';
                      ce2r_var := '0';
                   else
                      ce1r_var := ce1;
                      ce2r_var := ce2;
                   end if;
                end if;

           when others => 
                null;

        end case;
    end if;

   ce1r <= ce1r_var after DELAY_FFICE;
   ce2r <= ce2r_var after DELAY_FFICE;

  end process prcs_reg;
--####################################################################
--#####                        Output mux                        #####
--####################################################################
  prcs_mux:process(cesel, ce1, ce1r, ce2r)
  begin
    case cesel is
        when "00" =>
             ice_zd  <= ce1;
        when "01" =>
             ice_zd  <= ce1;
-- 426606
        when "10" =>
             ice_zd  <= ce2r;
        when "11" =>
             ice_zd  <= ce1r;
        when others =>
             null;
    end case;
  end process  prcs_mux;

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(ice_zd)
  begin
      ICE <= ice_zd;
  end process prcs_output;
end ice_V;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;


library unisim;
use unisim.vpkg.all;
use unisim.vcomponents.all;
use unisim.vcomponents.all;

----- CELL ISERDES -----
--//////////////////////////////////////////////////////////// 
--////////////////////////// ISERDES /////////////////////////
--//////////////////////////////////////////////////////////// 

entity ISERDES is

  generic(

      DDR_CLK_EDGE	: string	:= "SAME_EDGE_PIPELINED";
      INIT_BITSLIPCNT	: bit_vector(3 downto 0) := "0000";
      INIT_CE		: bit_vector(1 downto 0) := "00";
      INIT_RANK1_PARTIAL: bit_vector(4 downto 0) := "00000";
      INIT_RANK2	: bit_vector(5 downto 0) := "000000";
      INIT_RANK3	: bit_vector(5 downto 0) := "000000";
      SERDES		: boolean	:= TRUE;
      SRTYPE		: string	:= "ASYNC";

      BITSLIP_ENABLE	: boolean	:= false;
      DATA_RATE		: string	:= "DDR";
      DATA_WIDTH	: integer	:= 4;
      INIT_Q1		: bit		:= '0';
      INIT_Q2		: bit		:= '0';
      INIT_Q3		: bit		:= '0';
      INIT_Q4		: bit		:= '0';
      INTERFACE_TYPE	: string	:= "MEMORY";
      IOBDELAY		: string	:= "NONE";
      IOBDELAY_TYPE	: string	:= "DEFAULT";
      IOBDELAY_VALUE	: integer	:= 0;
      NUM_CE		: integer	:= 2;
      SERDES_MODE	: string	:= "MASTER";
      SRVAL_Q1		: bit		:= '0';
      SRVAL_Q2		: bit		:= '0';
      SRVAL_Q3		: bit		:= '0';
      SRVAL_Q4		: bit		:= '0'
      );

  port(
      O			: out std_ulogic;
      Q1		: out std_ulogic;
      Q2		: out std_ulogic;
      Q3		: out std_ulogic;
      Q4		: out std_ulogic;
      Q5		: out std_ulogic;
      Q6		: out std_ulogic;
      SHIFTOUT1		: out std_ulogic;
      SHIFTOUT2		: out std_ulogic;

      BITSLIP		: in std_ulogic;
      CE1		: in std_ulogic;
      CE2		: in std_ulogic;
      CLK		: in std_ulogic;
      CLKDIV		: in std_ulogic;
      D			: in std_ulogic;
      DLYCE		: in std_ulogic;
      DLYINC		: in std_ulogic;
      DLYRST		: in std_ulogic;
      OCLK		: in std_ulogic;
      REV		: in std_ulogic;
      SHIFTIN1		: in std_ulogic;
      SHIFTIN2		: in std_ulogic;
      SR		: in std_ulogic
    );

end ISERDES;

architecture ISERDES_V OF ISERDES is

component bscntrl
  generic (
      SRTYPE            : string;
      INIT_BITSLIPCNT	: bit_vector(3 downto 0)
    );
  port(
      CLKDIV_INT        : out std_ulogic;
      MUXC              : out std_ulogic;

      BITSLIP           : in std_ulogic;
      C23               : in std_ulogic;
      C45               : in std_ulogic;
      C67               : in std_ulogic;
      CLK               : in std_ulogic;
      CLKDIV            : in std_ulogic;
      DATA_RATE         : in std_ulogic;
      GSR               : in std_ulogic;
      R                 : in std_ulogic;
      SEL               : in std_logic_vector (1 downto 0)
      );
end component;

component ice_module
  generic(
      SRTYPE            : string;
      INIT_CE		: bit_vector(1 downto 0)
      );
  port(
      ICE		: out std_ulogic;

      CE1		: in std_ulogic;
      CE2		: in std_ulogic;
      GSR		: in std_ulogic;
      NUM_CE		: in std_ulogic;
      CLKDIV		: in std_ulogic;
      R			: in std_ulogic
      );
end component;

component IDELAY
  generic(
      IOBDELAY_VALUE : integer := 0;
      IOBDELAY_TYPE  : string  := "DEFAULT"
    );

  port(
      O      : out std_ulogic;

      C      : in  std_ulogic;
      CE     : in  std_ulogic;
       
      I      : in  std_ulogic;
      INC    : in  std_ulogic;
      RST    : in  std_ulogic
    );
end component;

--  constant DELAY_FFINP          : time       := 300 ns; 
--  constant DELAY_MXINP1         : time       := 60  ns;
--  constant DELAY_MXINP2         : time       := 120 ns;
--  constant DELAY_OCLKDLY        : time       := 750 ns;

  constant SYNC_PATH_DELAY      : time       := 100 ps; 

  constant DELAY_FFINP          : time       := 300 ps; 
  constant DELAY_MXINP1         : time       := 60  ps;
  constant DELAY_MXINP2         : time       := 120 ps;
  constant DELAY_OCLKDLY        : time       := 750 ps;

  constant MAX_DATAWIDTH	: integer    := 4;

  signal BITSLIP_ipd	        : std_ulogic := 'X';
  signal CE1_ipd	        : std_ulogic := 'X';
  signal CE2_ipd	        : std_ulogic := 'X';
  signal CLK_ipd	        : std_ulogic := 'X';
  signal CLKDIV_ipd		: std_ulogic := 'X';
  signal D_ipd			: std_ulogic := 'X';
  signal DLYCE_ipd		: std_ulogic := 'X';
  signal DLYINC_ipd		: std_ulogic := 'X';
  signal DLYRST_ipd		: std_ulogic := 'X';
  signal GSR			: std_ulogic := '0';
  signal GSR_ipd		: std_ulogic := 'X';
  signal OCLK_ipd		: std_ulogic := 'X';
  signal REV_ipd		: std_ulogic := 'X';
  signal SR_ipd			: std_ulogic := 'X';
  signal SHIFTIN1_ipd		: std_ulogic := 'X';
  signal SHIFTIN2_ipd		: std_ulogic := 'X';

  signal BITSLIP_dly	        : std_ulogic := 'X';
  signal CE1_dly	        : std_ulogic := 'X';
  signal CE2_dly	        : std_ulogic := 'X';
  signal CLK_dly	        : std_ulogic := 'X';
  signal CLKDIV_dly		: std_ulogic := 'X';
  signal D_dly			: std_ulogic := 'X';
  signal DLYCE_dly		: std_ulogic := 'X';
  signal DLYINC_dly		: std_ulogic := 'X';
  signal DLYRST_dly		: std_ulogic := 'X';
  signal GSR_dly		: std_ulogic := 'X';
  signal OCLK_dly		: std_ulogic := 'X';
  signal REV_dly		: std_ulogic := 'X';
  signal SR_dly			: std_ulogic := 'X';
  signal SHIFTIN1_dly		: std_ulogic := 'X';
  signal SHIFTIN2_dly		: std_ulogic := 'X';


  signal O_zd			: std_ulogic := 'X';
  signal Q1_zd			: std_ulogic := 'X';
  signal Q2_zd			: std_ulogic := 'X';
  signal Q3_zd			: std_ulogic := 'X';
  signal Q4_zd			: std_ulogic := 'X';
  signal Q5_zd			: std_ulogic := 'X';
  signal Q6_zd			: std_ulogic := 'X';
  signal SHIFTOUT1_zd		: std_ulogic := 'X';
  signal SHIFTOUT2_zd		: std_ulogic := 'X';

  signal O_viol			: std_ulogic := 'X';
  signal Q1_viol		: std_ulogic := 'X';
  signal Q2_viol		: std_ulogic := 'X';
  signal Q3_viol		: std_ulogic := 'X';
  signal Q4_viol		: std_ulogic := 'X';
  signal Q5_viol		: std_ulogic := 'X';
  signal Q6_viol		: std_ulogic := 'X';
  signal SHIFTOUT1_viol		: std_ulogic := 'X';
  signal SHIFTOUT2_viol		: std_ulogic := 'X';

  signal AttrSerdes		: std_ulogic := 'X';
  signal AttrMode		: std_ulogic := 'X';
  signal AttrDataRate		: std_ulogic := 'X';
  signal AttrDataWidth		: std_logic_vector(3 downto 0) := (others => 'X');
  signal AttrInterfaceType	: std_ulogic := 'X';
  signal AttrBitslipEnable	: std_ulogic := 'X';
  signal AttrNumCe		: std_ulogic := 'X';
  signal AttrDdrClkEdge		: std_logic_vector(1 downto 0) := (others => 'X');
  signal AttrSRtype		: integer := 0;
  signal AttrIobDelay		: integer := 0;

  signal sel1			: std_logic_vector(1 downto 0) := (others => 'X');
  signal selrnk3		: std_logic_vector(3 downto 0) := (others => 'X');
  signal bsmux			: std_logic_vector(2 downto 0) := (others => 'X');
  signal cntr			: std_logic_vector(4 downto 0) := (others => 'X');
  
  signal q1rnk1			: std_ulogic := 'X';
  signal q2nrnk1		: std_ulogic := 'X';
  signal q5rnk1			: std_ulogic := 'X';
  signal q6rnk1			: std_ulogic := 'X';
  signal q6prnk1		: std_ulogic := 'X';

  signal q1prnk1		: std_ulogic := 'X';
  signal q2prnk1		: std_ulogic := 'X';
  signal q3rnk1			: std_ulogic := 'X';
  signal q4rnk1			: std_ulogic := 'X';

  signal dataq5rnk1		: std_ulogic := 'X';
  signal dataq6rnk1		: std_ulogic := 'X';

  signal dataq3rnk1		: std_ulogic := 'X';
  signal dataq4rnk1		: std_ulogic := 'X';

  signal oclkmux		: std_ulogic := '0';
  signal memmux			: std_ulogic := '0';
  signal q2pmux			: std_ulogic := '0';

  signal clkdiv_int		: std_ulogic := '0';
  signal clkdivmux		: std_ulogic := '0';

  signal q1rnk2			: std_ulogic := 'X';
  signal q2rnk2			: std_ulogic := 'X';
  signal q3rnk2			: std_ulogic := 'X';
  signal q4rnk2			: std_ulogic := 'X';
  signal q5rnk2			: std_ulogic := 'X';
  signal q6rnk2			: std_ulogic := 'X';
  signal dataq1rnk2		: std_ulogic := 'X';
  signal dataq2rnk2		: std_ulogic := 'X';
  signal dataq3rnk2		: std_ulogic := 'X';
  signal dataq4rnk2		: std_ulogic := 'X';
  signal dataq5rnk2		: std_ulogic := 'X';
  signal dataq6rnk2		: std_ulogic := 'X';

  signal muxc			: std_ulogic := 'X';

  signal q1rnk3			: std_ulogic := 'X';
  signal q2rnk3			: std_ulogic := 'X';
  signal q3rnk3			: std_ulogic := 'X';
  signal q4rnk3			: std_ulogic := 'X';
  signal q5rnk3			: std_ulogic := 'X';
  signal q6rnk3			: std_ulogic := 'X';

  signal c23			: std_ulogic := 'X';
  signal c45			: std_ulogic := 'X';
  signal c67			: std_ulogic := 'X';
  signal sel			: std_logic_vector(1 downto 0) := (others => 'X');

  signal ice			: std_ulogic := 'X';
  signal datain			: std_ulogic := 'X';
  signal idelay_out		: std_ulogic := 'X';

  signal CLKN_dly		: std_ulogic := '0';

begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  BITSLIP_dly    	 <= BITSLIP        	after 0 ps;
  CE1_dly        	 <= CE1            	after 0 ps;
  CE2_dly        	 <= CE2            	after 0 ps;
  CLK_dly        	 <= CLK            	after 0 ps;
  CLKDIV_dly     	 <= CLKDIV         	after 0 ps;
  D_dly          	 <= D              	after 0 ps;
  DLYCE_dly      	 <= DLYCE          	after 0 ps;
  DLYINC_dly     	 <= DLYINC         	after 0 ps;
  DLYRST_dly     	 <= DLYRST         	after 0 ps;
  GSR_dly        	 <= GSR            	after 0 ps;
  OCLK_dly       	 <= OCLK           	after 0 ps;
  REV_dly        	 <= REV            	after 0 ps;
  SHIFTIN1_dly   	 <= SHIFTIN1       	after 0 ps;
  SHIFTIN2_dly   	 <= SHIFTIN2       	after 0 ps;
  SR_dly         	 <= SR             	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process
  variable AttrSerdes_var		: std_ulogic := 'X';
  variable AttrMode_var			: std_ulogic := 'X';
  variable AttrDataRate_var		: std_ulogic := 'X';
  variable AttrDataWidth_var		: std_logic_vector(3 downto 0) := (others => 'X');
  variable AttrInterfaceType_var	: std_ulogic := 'X';
  variable AttrBitslipEnable_var	: std_ulogic := 'X';
  variable AttrDdrClkEdge_var		: std_logic_vector(1 downto 0) := (others => 'X');
  variable AttrIobDelay_var		: integer := 0;

  begin

      --------CR 447760  DRC -- BITSLIP - INTERFACE_TYPE combination  ------------------

      if((INTERFACE_TYPE = "MEMORY") and (BITSLIP_ENABLE = TRUE)) then
        assert false
        report "Attribute Syntax Error: BITSLIP_ENABLE is currently set to TRUE when INTERFACE_TYPE is set to MEMORY. This is an invalid configuration."
        severity Failure;
     elsif((INTERFACE_TYPE = "NETWORKING") and (BITSLIP_ENABLE = FALSE)) then
        assert false
        report "Attribute Syntax Error: BITSLIP_ENABLE is currently set to FALSE when INTERFACE_TYPE is set to NETWORKING. If BITSLIP is not intended to be used, please set BITSLIP_ENABLE to TRUE and tie the BITSLIP port to ground."
        severity Failure;
     end if;

      -------------------- SERDES validity check --------------------
      if(SERDES = true) then
        AttrSerdes_var := '1';
      else
        AttrSerdes_var := '0';
      end if;

      ------------- SERDES_MODE validity check --------------------
      if((SERDES_MODE = "MASTER") or (SERDES_MODE = "master")) then
         AttrMode_var := '0';
      elsif((SERDES_MODE = "SLAVE") or (SERDES_MODE = "slave")) then
         AttrMode_var := '1';
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => "SERDES_MODE ",
             EntityName => "/ISERDES",
             GenericValue => SERDES_MODE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " MASTER or SLAVE.",
             TailMsg => "",
             MsgSeverity => FAILURE 
         );
      end if;

      ------------------ DATA_RATE validity check ------------------
      if((DATA_RATE = "DDR") or (DATA_RATE = "ddr")) then
         AttrDataRate_var := '0';
      elsif((DATA_RATE = "SDR") or (DATA_RATE = "sdr")) then
         AttrDataRate_var := '1';
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " DATA_RATE ",
             EntityName => "/ISERDES",
             GenericValue => DATA_RATE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " DDR or SDR. ",
             TailMsg => "",
             MsgSeverity => Failure
         );
      end if;

      ------------------ DATA_WIDTH validity check ------------------
      if((DATA_WIDTH = 2) or (DATA_WIDTH = 3) or  (DATA_WIDTH = 4) or
         (DATA_WIDTH = 5) or (DATA_WIDTH = 6) or  (DATA_WIDTH = 7) or
         (DATA_WIDTH = 8) or (DATA_WIDTH = 10)) then
         AttrDataWidth_var := CONV_STD_LOGIC_VECTOR(DATA_WIDTH, MAX_DATAWIDTH); 
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " DATA_WIDTH ",
             EntityName => "/ISERDES",
             GenericValue => DATA_WIDTH,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " 2, 3, 4, 5, 6, 7, 8, or 10 ",
             TailMsg => "",
             MsgSeverity => Failure
         );
      end if;
      ------------ DATA_WIDTH /DATA_RATE combination check ------------
      if((DATA_RATE = "DDR") or (DATA_RATE = "ddr")) then
         case (DATA_WIDTH) is
             when 4|6|8|10  => null;
             when others       =>
                GenericValueCheckMessage
                (  HeaderMsg  => " Attribute Syntax Warning ",
                   GenericName => " DATA_WIDTH ",
                   EntityName => "/ISERDES",
                   GenericValue => DATA_WIDTH,
                   Unit => "",
                   ExpectedValueMsg => " The Legal values for DDR mode are ",
                   ExpectedGenericValue => " 4, 6, 8, or 10 ",
                   TailMsg => "",
                   MsgSeverity => Failure
                );
          end case;
      end if;

      if((DATA_RATE = "SDR") or (DATA_RATE = "sdr")) then
         case (DATA_WIDTH) is
             when 2|3|4|5|6|7|8  => null;
             when others       =>
                GenericValueCheckMessage
                (  HeaderMsg  => " Attribute Syntax Warning ",
                   GenericName => " DATA_WIDTH ",
                   EntityName => "/ISERDES",
                   GenericValue => DATA_WIDTH,
                   Unit => "",
                   ExpectedValueMsg => " The Legal values for SDR mode are ",
                   ExpectedGenericValue => " 2, 3, 4, 5, 6, 7 or 8",
                   TailMsg => "",
                   MsgSeverity => Failure
                );
          end case;
      end if;
      ---------------- INTERFACE_TYPE validity check ---------------
      if((INTERFACE_TYPE = "MEMORY") or (INTERFACE_TYPE = "memory")) then
         AttrInterfaceType_var := '0';
      elsif((INTERFACE_TYPE = "NETWORKING") or (INTERFACE_TYPE = "networking")) then
         AttrInterfaceType_var := '1';
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => "INTERFACE_TYPE ",
             EntityName => "/ISERDES",
             GenericValue => INTERFACE_TYPE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " MEMORY or NETWORKING.",
             TailMsg => "",
             MsgSeverity => FAILURE 
         );
      end if;

      ---------------- BITSLIP_ENABLE validity check -------------------
      if(BITSLIP_ENABLE = false) then
         AttrBitslipEnable_var := '0';
      elsif(BITSLIP_ENABLE = true) then
         AttrBitslipEnable_var := '1';
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " BITSLIP_ENABLE ",
             EntityName => "/ISERDES",
             GenericValue => BITSLIP_ENABLE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " TRUE or FALSE ",
             TailMsg => "",
             MsgSeverity => Failure
         );
      end if;

      ----------------     NUM_CE validity check    -------------------
      case NUM_CE is
         when 1 =>
                AttrNumCe <= '0';
         when 2 =>
                AttrNumCe <= '1';
         when others =>
                GenericValueCheckMessage
                  (  HeaderMsg  => " Attribute Syntax Warning ",
                     GenericName => " NUM_CE ",
                     EntityName => "/ISERDES",
                     GenericValue => NUM_CE,
                     Unit => "",
                     ExpectedValueMsg => " The Legal values for this attribute are ",
                     ExpectedGenericValue => " 1 or 2 ",
                     TailMsg => "",
                     MsgSeverity => Failure
                  );
      end case;
      ----------------     IOBDELAY validity check  -------------------
      if((IOBDELAY = "NONE") or (IOBDELAY = "none")) then
         AttrIobDelay_var := 0;
      elsif((IOBDELAY = "IBUF") or (IOBDELAY = "ibuf")) then
         AttrIobDelay_var := 1;
      elsif((IOBDELAY = "IFD") or (IOBDELAY = "ifd")) then
         AttrIobDelay_var := 2;
      elsif((IOBDELAY = "BOTH") or (IOBDELAY = "both")) then
         AttrIobDelay_var := 3;
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " IOBDELAY ",
             EntityName => "/ISERDES",
             GenericValue => IOBDELAY,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " NONE or IBUF or IFD or BOTH ",
             TailMsg => "",
             MsgSeverity => Failure
         );
      end if;
      ------------     IOBDELAY_VALUE validity check  -----------------
      ------------     IOBDELAY_TYPE validity check   -----------------
--
--
--
      ------------------ DDR_CLK_EDGE validity check ------------------
      if((DDR_CLK_EDGE = "SAME_EDGE_PIPELINED") or (DDR_CLK_EDGE = "same_edge_pipelined")) then
         AttrDdrClkEdge_var := "00";
      elsif((DDR_CLK_EDGE = "SAME_EDGE") or (DDR_CLK_EDGE = "same_edge")) then
         AttrDdrClkEdge_var := "01";
      elsif((DDR_CLK_EDGE = "OPPOSITE_EDGE") or (DDR_CLK_EDGE = "opposite_edge")) then
         AttrDdrClkEdge_var := "10";
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " DDR_CLK_EDGE ",
             EntityName => "/ISERDES",
             GenericValue => DDR_CLK_EDGE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " SAME_EDGE_PIPELINED or SAME_EDGE or OPPOSITE_EDGE ",
             TailMsg => "",
             MsgSeverity => Failure
         );
      end if;
      ------------------ DATA_RATE validity check ------------------
      if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
         AttrSrtype <= 0;
      elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
         AttrSrtype <= 1;
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " SRTYPE ",
             EntityName => "/ISERDES",
             GenericValue => SRTYPE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " ASYNC or SYNC. ",
             TailMsg => "",
             MsgSeverity => ERROR
         );
      end if;
---------------------------------------------------------------------

     AttrSerdes		<= AttrSerdes_var;
     AttrMode		<= AttrMode_var;
     AttrDataRate	<= AttrDataRate_var;
     AttrDataWidth	<= AttrDataWidth_var;
     AttrInterfaceType	<= AttrInterfaceType_var;
     AttrBitslipEnable	<= AttrBitslipEnable_var;
     AttrDdrClkEdge	<= AttrDdrClkEdge_var;
     AttrIobDelay	<= AttrIobDelay_var;

     sel1     <= AttrMode_var & AttrDataRate_var; 
     selrnk3  <= AttrSerdes_var & AttrBitslipEnable_var & AttrDdrClkEdge_var; 
     cntr     <= AttrDataRate_var & AttrDataWidth_var;

     wait;
  end process prcs_init;

--###################################################################
--#####               SHIFTOUT1 and SHIFTOUT2                   #####
--###################################################################

  SHIFTOUT2_zd <= q5rnk1;
  SHIFTOUT1_zd <= q6rnk1;

--###################################################################
--#####                     q1rnk1 reg                          #####
--###################################################################
  prcs_Q1_rnk1:process(CLK_dly, GSR_dly, REV_dly, SR_dly)
  variable q1rnk1_var         : std_ulogic := TO_X01(INIT_Q1);
  begin
     if(GSR_dly = '1') then
         q1rnk1_var  :=  TO_X01(INIT_Q1);
     elsif(GSR_dly = '0') then
        case AttrSRtype is
           when 0 => 
           --------------- // async SET/RESET
                   if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q1) = '1')))) then
                      q1rnk1_var := TO_X01(SRVAL_Q1);
                   elsif(REV_dly = '1') then
                      q1rnk1_var := not TO_X01(SRVAL_Q1);
                   elsif((SR_dly = '0') and (REV_dly = '0')) then
                      if(ice = '1') then
                         if(rising_edge(CLK_dly)) then
                            q1rnk1_var := datain;
                         end if;
                      end if;
                   end if;

           when 1 => 
           --------------- // sync SET/RESET
                   if(rising_edge(CLK_dly)) then
                      if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q1) = '1')))) then
                         q1rnk1_var := TO_X01(SRVAL_Q1);
                      Elsif(REV_dly = '1') then
                         q1rnk1_var := not TO_X01(SRVAL_Q1);
                      elsif((SR_dly = '0') and (REV_dly = '0')) then
                         if(ice = '1') then
                            q1rnk1_var := datain;
                         end if;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     q1rnk1  <= q1rnk1_var  after DELAY_FFINP;

  end process prcs_Q1_rnk1;
--###################################################################
--#####              q5rnk1, q6rnk1 and q6prnk1 reg             #####
--###################################################################
  prcs_Q5Q6Q6p_rnk1:process(CLK_dly, GSR_dly, SR_dly)
  variable q5rnk1_var         : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(2));
  variable q6rnk1_var         : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(1));
  variable q6prnk1_var        : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(0));
  begin
     if(GSR_dly = '1') then
         q5rnk1_var  := TO_X01(INIT_RANK1_PARTIAL(2));
         q6rnk1_var  := TO_X01(INIT_RANK1_PARTIAL(1));
         q6prnk1_var := TO_X01(INIT_RANK1_PARTIAL(0));
     elsif(GSR_dly = '0') then
        case AttrSRtype is
           when 0 => 
           --------- // async SET/RESET  -- Not full featured FFs
                   if(SR_dly = '1') then
                      q5rnk1_var  := '0';
                      q6rnk1_var  := '0';
                      q6prnk1_var := '0';
                   elsif(SR_dly = '0') then
                      if(rising_edge(CLK_dly)) then
                         q5rnk1_var  := dataq5rnk1;
                         q6rnk1_var  := dataq6rnk1;
                         q6prnk1_var := q6rnk1;
                      end if;
                   end if;

           when 1 => 
           --------- // sync SET/RESET  -- Not full featured FFs
                   if(rising_edge(CLK_dly)) then
                      if(SR_dly = '1') then
                         q5rnk1_var  := '0';
                         q6rnk1_var  := '0';
                         q6prnk1_var := '0';
                      elsif(SR_dly = '0') then
                         q5rnk1_var  := dataq5rnk1;
                         q6rnk1_var  := dataq6rnk1;
                         q6prnk1_var := q6rnk1;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     q5rnk1  <= q5rnk1_var  after DELAY_FFINP;
     q6rnk1  <= q6rnk1_var  after DELAY_FFINP;
     q6prnk1 <= q6prnk1_var after DELAY_FFINP;

  end process prcs_Q5Q6Q6p_rnk1;
--###################################################################
--#####                     q2nrnk1 reg                          #####
--###################################################################
  prcs_Q2_rnk1:process(CLK_dly, GSR_dly, SR_dly, REV_dly)
  variable q2nrnk1_var         : std_ulogic := TO_X01(INIT_Q2);
  begin
     if(GSR_dly = '1') then
         q2nrnk1_var  := TO_X01(INIT_Q2);
     elsif(GSR_dly = '0') then
        case AttrSRtype is
           when 0 => 
           --------------- // async SET/RESET
                   if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q2) = '1')))) then
                      q2nrnk1_var  := TO_X01(SRVAL_Q2);
                   elsif(REV_dly = '1') then
                      q2nrnk1_var  := not TO_X01(SRVAL_Q2);
                   elsif((SR_dly = '0') and (REV_dly = '0')) then
                      if(ice = '1') then
                         if(falling_edge(CLK_dly)) then
                            q2nrnk1_var     := datain;
                         end if;
                      end if;
                   end if;

           when 1 => 
           --------------- // sync SET/RESET
                   if(falling_edge(CLK_dly)) then
                      if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q2) = '1')))) then
                         q2nrnk1_var  := TO_X01(SRVAL_Q2);
                      elsif(REV_dly = '1') then
                         q2nrnk1_var  := not TO_X01(SRVAL_Q2);
                      elsif((SR_dly = '0') and (REV_dly = '0')) then
                         if(ice = '1') then
                            q2nrnk1_var := datain;
                         end if;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     q2nrnk1  <= q2nrnk1_var after DELAY_FFINP;

  end process prcs_Q2_rnk1;
--###################################################################
--#####                       q2prnk1 reg                       #####
--###################################################################
  prcs_Q2p_rnk1:process(q2pmux, GSR_dly, REV_dly, SR_dly)
  variable q2prnk1_var        : std_ulogic := TO_X01(INIT_Q4);
  begin
     if(GSR_dly = '1') then
         q2prnk1_var := TO_X01(INIT_Q4);
     elsif(GSR_dly = '0') then
        case AttrSRtype is
           when 0 => 
           --------------- // async SET/RESET
                   if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q4) = '1')))) then
                      q2prnk1_var := TO_X01(SRVAL_Q4);
                   elsif(REV_dly = '1') then
                      q2prnk1_var := not TO_X01(SRVAL_Q4);
                   elsif((SR_dly = '0') and (REV_dly = '0')) then
                      if(ice = '1') then
                         if(rising_edge(q2pmux)) then
                            q2prnk1_var := q2nrnk1;
                         end if;
                      end if;
                   end if;

           when 1 => 
           --------------- // sync SET/RESET
                   if(rising_edge(q2pmux)) then
                      if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q4) = '1')))) then
                         q2prnk1_var := TO_X01(SRVAL_Q4);
                      elsif(REV_dly = '1') then
                         q2prnk1_var := not TO_X01(SRVAL_Q4);
                      elsif((SR_dly = '0') and (REV_dly = '0')) then
                         if(ice = '1') then
                              q2prnk1_var := q2nrnk1;
                         end if;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     q2prnk1  <= q2prnk1_var after DELAY_FFINP;

  end process prcs_Q2p_rnk1;
--###################################################################
--#####                      q1prnk1  reg                       #####
--###################################################################
  prcs_Q1p_rnk1:process(memmux, GSR_dly, REV_dly, SR_dly)
  variable q1prnk1_var        : std_ulogic := TO_X01(INIT_Q3);
  begin
     if(GSR_dly = '1') then
         q1prnk1_var := TO_X01(INIT_Q3);
     elsif(GSR_dly = '0') then
        case AttrSRtype is
           when 0 => 
           --------------- // async SET/RESET
                   if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q3) = '1')))) then
                      q1prnk1_var := TO_X01(SRVAL_Q3);
                   elsif(REV_dly = '1') then
                      q1prnk1_var := not TO_X01(SRVAL_Q3);
                   elsif((SR_dly = '0') and (REV_dly = '0')) then
                      if(ice = '1') then
                         if(rising_edge(memmux)) then
                            q1prnk1_var := q1rnk1;
                         end if;
                      end if;
                   end if;


           when 1 => 
           --------------- // sync SET/RESET
                   if(rising_edge(memmux)) then
                      if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q3) = '1')))) then
                         q1prnk1_var := TO_X01(SRVAL_Q3);
                      elsif(REV_dly = '1') then
                         q1prnk1_var := not TO_X01(SRVAL_Q3);
                      elsif((SR_dly = '0') and (REV_dly = '0')) then
                         if(ice = '1') then
                            q1prnk1_var := q1rnk1;
                         end if;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     q1prnk1  <= q1prnk1_var after DELAY_FFINP;

  end process prcs_Q1p_rnk1;
--###################################################################
--#####                  q3rnk1 and q4rnk1 reg                  #####
--###################################################################
  prcs_Q3Q4_rnk1:process(memmux, GSR_dly, SR_dly)
  variable q3rnk1_var         : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(4));
  variable q4rnk1_var         : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(3));
  begin
     if(GSR_dly = '1') then
         q3rnk1_var  := TO_X01(INIT_RANK1_PARTIAL(4));
         q4rnk1_var  := TO_X01(INIT_RANK1_PARTIAL(3));
     elsif(GSR_dly = '0') then
        case AttrSRtype is
           when 0 => 
           -------- // async SET/RESET  -- not fully featured FFs
                   if(SR_dly = '1') then
                      q3rnk1_var  := '0';
                      q4rnk1_var  := '0';
                   elsif(SR_dly = '0') then
                      if(rising_edge(memmux)) then
                         q3rnk1_var  := dataq3rnk1;
                         q4rnk1_var  := dataq4rnk1;
                      end if;
                   end if;

           when 1 => 
           -------- // sync SET/RESET -- not fully featured FFs
                   if(rising_edge(memmux)) then
                      if(SR_dly = '1') then
                         q3rnk1_var  := '0';
                         q4rnk1_var  := '0';
                      elsif(SR_dly = '0') then
                         q3rnk1_var  := dataq3rnk1;
                         q4rnk1_var  := dataq4rnk1;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     q3rnk1   <= q3rnk1_var after DELAY_FFINP;
     q4rnk1   <= q4rnk1_var after DELAY_FFINP;

  end process prcs_Q3Q4_rnk1;
--###################################################################
--#####        clock mux --  oclkmux with delay element         #####
--###################################################################
--  prcs_oclkmux:process(OCLK_dly)
--  begin
--     case AttrOclkDelay is
--           when '0' => 
--                    oclkmux <= OCLK_dly after DELAY_MXINP1;
--           when '1' => 
--                    oclkmux <= OCLK_dly after DELAY_OCLKDLY;
--           when others =>
--                    oclkmux <= OCLK_dly after DELAY_MXINP1;
--     end case;
--  end process prcs_oclkmux;
--
--
--
--///////////////////////////////////////////////////////////////////
--// Mux elements for the 1st Rank
--///////////////////////////////////////////////////////////////////
--###################################################################
--#####              memmux -- 4 clock muxes in first rank      #####
--###################################################################
  prcs_memmux:process(CLK_dly, OCLK_dly)
  begin
     case AttrInterfaceType is
           when '0' => 
                    memmux <= OCLK_dly after DELAY_MXINP1;
           when '1' => 
                    memmux <= CLK_dly after DELAY_MXINP1;
           when others =>
                    memmux <= OCLK_dly after DELAY_MXINP1;
     end case;
  end process prcs_memmux;

--###################################################################
--#####      q2pmux -- Optional inverter for q2p (4th flop in rank1)
--###################################################################
  prcs_q2pmux:process(memmux)
  begin
     case AttrInterfaceType is
           when '0' => 
                    q2pmux <= not memmux after DELAY_MXINP1;
           when '1' => 
                    q2pmux <= memmux after DELAY_MXINP1;
           when others =>
                    q2pmux <= memmux after DELAY_MXINP1;
     end case;
  end process prcs_q2pmux;
--###################################################################
--#####                data input muxes for q3q4  and q5q6      #####
--###################################################################
  prcs_Q3Q4_mux:process(q1prnk1, q2prnk1, q3rnk1, SHIFTIN1_dly, SHIFTIN2_dly)
  begin
     case sel1 is
           when "00" =>
                    dataq3rnk1 <= q1prnk1 after DELAY_MXINP1;
                    dataq4rnk1 <= q2prnk1 after DELAY_MXINP1;
           when "01" =>
                    dataq3rnk1 <= q1prnk1 after DELAY_MXINP1;
                    dataq4rnk1 <= q3rnk1  after DELAY_MXINP1;
           when "10" =>
                    dataq3rnk1 <= SHIFTIN2_dly after DELAY_MXINP1;
                    dataq4rnk1 <= SHIFTIN1_dly after DELAY_MXINP1;
           when "11" =>
                    dataq3rnk1 <= SHIFTIN1_dly after DELAY_MXINP1;
                    dataq4rnk1 <= q3rnk1   after DELAY_MXINP1;
           when others =>
                    dataq3rnk1 <= q1prnk1 after DELAY_MXINP1;
                    dataq4rnk1 <= q2prnk1 after DELAY_MXINP1;
     end case;

  end process prcs_Q3Q4_mux;
----------------------------------------------------------------------
  prcs_Q5Q6_mux:process(q3rnk1, q4rnk1, q5rnk1)
  begin
     case AttrDataRate is 
           when '0' =>
                    dataq5rnk1 <= q3rnk1 after DELAY_MXINP1;
                    dataq6rnk1 <= q4rnk1 after DELAY_MXINP1;
           when '1' =>
                    dataq5rnk1 <= q4rnk1 after DELAY_MXINP1;
                    dataq6rnk1 <= q5rnk1 after DELAY_MXINP1;
           when others =>
                    dataq5rnk1 <= q4rnk1 after DELAY_MXINP1;
                    dataq6rnk1 <= q5rnk1 after DELAY_MXINP1;
     end case;
  end process prcs_Q5Q6_mux;



---////////////////////////////////////////////////////////////////////
---                       2nd rank of registors
---////////////////////////////////////////////////////////////////////

--###################################################################
--#####    clkdivmux to choose between clkdiv_int or CLKDIV     #####
--###################################################################
  prcs_clkdivmux:process(clkdiv_int, CLKDIV_dly)
  begin
     case AttrBitslipEnable is
           when '0' =>
                    clkdivmux <= CLKDIV_dly after DELAY_MXINP1;
           when '1' =>
                    clkdivmux <= clkdiv_int after DELAY_MXINP1;
           when others =>
                    clkdivmux <= CLKDIV_dly after DELAY_MXINP1;
     end case;
  end process prcs_clkdivmux;

--###################################################################
--#####  q1rnk2, q2rnk2, q3rnk2,q4rnk2 ,q5rnk2 and q6rnk2 reg   #####
--###################################################################
  prcs_Q1Q2Q3Q4Q5Q6_rnk2:process(clkdivmux, GSR_dly, SR_dly)
  variable q1rnk2_var         : std_ulogic := TO_X01(INIT_RANK2(0));
  variable q2rnk2_var         : std_ulogic := TO_X01(INIT_RANK2(1));
  variable q3rnk2_var         : std_ulogic := TO_X01(INIT_RANK2(2));
  variable q4rnk2_var         : std_ulogic := TO_X01(INIT_RANK2(3));
  variable q5rnk2_var         : std_ulogic := TO_X01(INIT_RANK2(4));
  variable q6rnk2_var         : std_ulogic := TO_X01(INIT_RANK2(5));
  begin
     if(GSR_dly = '1') then
         q1rnk2_var := TO_X01(INIT_RANK2(0));
         q2rnk2_var := TO_X01(INIT_RANK2(1));
         q3rnk2_var := TO_X01(INIT_RANK2(2));
         q4rnk2_var := TO_X01(INIT_RANK2(3));
         q5rnk2_var := TO_X01(INIT_RANK2(4));
         q6rnk2_var := TO_X01(INIT_RANK2(5));
     elsif(GSR_dly = '0') then
        case AttrSRtype is
           when 0 => 
           --------------- // async SET/RESET
                   if(SR_dly = '1') then
                      q1rnk2_var := '0';
                      q2rnk2_var := '0';
                      q3rnk2_var := '0';
                      q4rnk2_var := '0';
                      q5rnk2_var := '0';
                      q6rnk2_var := '0';
                   elsif(SR_dly = '0') then
                       if(rising_edge(clkdivmux)) then
                           q1rnk2_var := dataq1rnk2;
                           q2rnk2_var := dataq2rnk2;
                           q3rnk2_var := dataq3rnk2;
                           q4rnk2_var := dataq4rnk2;
                           q5rnk2_var := dataq5rnk2;
                           q6rnk2_var := dataq6rnk2;
                       end if;
                   end if;

           when 1 => 
           --------------- // sync SET/RESET
                   if(rising_edge(clkdivmux)) then
                      if(SR_dly = '1') then
                         q1rnk2_var := '0';
                         q2rnk2_var := '0';
                         q3rnk2_var := '0';
                         q4rnk2_var := '0';
                         q5rnk2_var := '0';
                         q6rnk2_var := '0';
                      elsif(SR_dly = '0') then
                         q1rnk2_var := dataq1rnk2;
                         q2rnk2_var := dataq2rnk2;
                         q3rnk2_var := dataq3rnk2;
                         q4rnk2_var := dataq4rnk2;
                         q5rnk2_var := dataq5rnk2;
                         q6rnk2_var := dataq6rnk2;
                      end if;
                   end if;
           when others =>
                   null;
        end case;
     end if;

     q1rnk2  <= q1rnk2_var after DELAY_FFINP;
     q2rnk2  <= q2rnk2_var after DELAY_FFINP;
     q3rnk2  <= q3rnk2_var after DELAY_FFINP;
     q4rnk2  <= q4rnk2_var after DELAY_FFINP;
     q5rnk2  <= q5rnk2_var after DELAY_FFINP;
     q6rnk2  <= q6rnk2_var after DELAY_FFINP;

  end process prcs_Q1Q2Q3Q4Q5Q6_rnk2;

--###################################################################
--#####                    update bitslip mux                   #####
--###################################################################

  bsmux  <= AttrBitslipEnable & AttrDataRate & muxc; 

--###################################################################
--#####    Data mux for 2nd rank of registers                  ######
--###################################################################
  prcs_Q1Q2Q3Q4Q5Q6_rnk2_mux:process(bsmux, q1rnk1, q1prnk1, q2prnk1, 
                           q3rnk1, q4rnk1, q5rnk1, q6rnk1, q6prnk1)
  begin
     case bsmux is
        when "000" | "001" =>
                 dataq1rnk2 <= q2prnk1 after DELAY_MXINP2;
                 dataq2rnk2 <= q1prnk1 after DELAY_MXINP2;
                 dataq3rnk2 <= q4rnk1  after DELAY_MXINP2;
                 dataq4rnk2 <= q3rnk1  after DELAY_MXINP2;
                 dataq5rnk2 <= q6rnk1  after DELAY_MXINP2;
                 dataq6rnk2 <= q5rnk1  after DELAY_MXINP2;
        when "100"  =>
                 dataq1rnk2 <= q2prnk1 after DELAY_MXINP2;
                 dataq2rnk2 <= q1prnk1 after DELAY_MXINP2;
                 dataq3rnk2 <= q4rnk1  after DELAY_MXINP2;
                 dataq4rnk2 <= q3rnk1  after DELAY_MXINP2;
                 dataq5rnk2 <= q6rnk1  after DELAY_MXINP2;
                 dataq6rnk2 <= q5rnk1  after DELAY_MXINP2;
        when "101"  =>
                 dataq1rnk2 <= q1prnk1 after DELAY_MXINP2;
                 dataq2rnk2 <= q4rnk1  after DELAY_MXINP2;
                 dataq3rnk2 <= q3rnk1  after DELAY_MXINP2;
                 dataq4rnk2 <= q6rnk1  after DELAY_MXINP2;
                 dataq5rnk2 <= q5rnk1  after DELAY_MXINP2;
                 dataq6rnk2 <= q6prnk1 after DELAY_MXINP2;
        when "010" | "011" | "110" | "111" =>
                 dataq1rnk2 <= q1rnk1  after DELAY_MXINP2;
                 dataq2rnk2 <= q1prnk1 after DELAY_MXINP2;
                 dataq3rnk2 <= q3rnk1  after DELAY_MXINP2;
                 dataq4rnk2 <= q4rnk1  after DELAY_MXINP2;
                 dataq5rnk2 <= q5rnk1  after DELAY_MXINP2;
                 dataq6rnk2 <= q6rnk1  after DELAY_MXINP2;
        when others =>
                 dataq1rnk2 <= q2prnk1 after DELAY_MXINP2;
                 dataq2rnk2 <= q1prnk1 after DELAY_MXINP2;
                 dataq3rnk2 <= q4rnk1  after DELAY_MXINP2;
                 dataq4rnk2 <= q3rnk1  after DELAY_MXINP2;
                 dataq5rnk2 <= q6rnk1  after DELAY_MXINP2;
                 dataq6rnk2 <= q5rnk1  after DELAY_MXINP2;
     end case;
  end process prcs_Q1Q2Q3Q4Q5Q6_rnk2_mux;

---////////////////////////////////////////////////////////////////////
---                       3rd rank of registors
---////////////////////////////////////////////////////////////////////

--###################################################################
--#####  q1rnk3, q2rnk3, q3rnk3, q4rnk3, q5rnk3 and q6rnk3 reg   #####
--###################################################################
  prcs_Q1Q2Q3Q4Q5Q6_rnk3:process(CLKDIV_dly, GSR_dly, SR_dly)
  variable q1rnk3_var         : std_ulogic := TO_X01(INIT_RANK3(0));
  variable q2rnk3_var         : std_ulogic := TO_X01(INIT_RANK3(1));
  variable q3rnk3_var         : std_ulogic := TO_X01(INIT_RANK3(2));
  variable q4rnk3_var         : std_ulogic := TO_X01(INIT_RANK3(3));
  variable q5rnk3_var         : std_ulogic := TO_X01(INIT_RANK3(4));
  variable q6rnk3_var         : std_ulogic := TO_X01(INIT_RANK3(5));
  begin
     if(GSR_dly = '1') then
         q1rnk3_var := TO_X01(INIT_RANK3(0));
         q2rnk3_var := TO_X01(INIT_RANK3(1));
         q3rnk3_var := TO_X01(INIT_RANK3(2));
         q4rnk3_var := TO_X01(INIT_RANK3(3));
         q5rnk3_var := TO_X01(INIT_RANK3(4));
         q6rnk3_var := TO_X01(INIT_RANK3(5));
     elsif(GSR_dly = '0') then
        case AttrSRtype is
           when 0 => 
           --------------- // async SET/RESET
                   if(SR_dly = '1') then
                      q1rnk3_var := '0';
                      q2rnk3_var := '0';
                      q3rnk3_var := '0';
                      q4rnk3_var := '0';
                      q5rnk3_var := '0';
                      q6rnk3_var := '0';
                   elsif(SR_dly = '0') then
                       if(rising_edge(CLKDIV_dly)) then
                           q1rnk3_var := q1rnk2;
                           q2rnk3_var := q2rnk2;
                           q3rnk3_var := q3rnk2;
                           q4rnk3_var := q4rnk2;
                           q5rnk3_var := q5rnk2;
                           q6rnk3_var := q6rnk2;
                        end if;
                   end if;

           when 1 => 
           --------------- // sync SET/RESET
                   if(rising_edge(CLKDIV_dly)) then
                      if(SR_dly = '1') then
                         q1rnk3_var := '0';
                         q2rnk3_var := '0';
                         q3rnk3_var := '0';
                         q4rnk3_var := '0';
                         q5rnk3_var := '0';
                         q6rnk3_var := '0';
                      elsif(SR_dly = '0') then
                         q1rnk3_var := q1rnk2;
                         q2rnk3_var := q2rnk2;
                         q3rnk3_var := q3rnk2;
                         q4rnk3_var := q4rnk2;
                         q5rnk3_var := q5rnk2;
                         q6rnk3_var := q6rnk2;
                      end if;
                   end if;
           when others =>
                   null;
        end case;
     end if;

     q1rnk3  <= q1rnk3_var after DELAY_FFINP;
     q2rnk3  <= q2rnk3_var after DELAY_FFINP;
     q3rnk3  <= q3rnk3_var after DELAY_FFINP;
     q4rnk3  <= q4rnk3_var after DELAY_FFINP;
     q5rnk3  <= q5rnk3_var after DELAY_FFINP;
     q6rnk3  <= q6rnk3_var after DELAY_FFINP;

  end process prcs_Q1Q2Q3Q4Q5Q6_rnk3;

---////////////////////////////////////////////////////////////////////
---                       Outputs
---////////////////////////////////////////////////////////////////////
  prcs_Q1Q2_rnk3_mux:process(q1rnk1, q1prnk1, q1rnk2, q1rnk3,  
                           q2nrnk1, q2prnk1, q2rnk2, q2rnk3)
  begin
     case selrnk3 is
        when "0000" | "0100" | "0X00" =>
                 Q1_zd <= q1prnk1 after DELAY_MXINP1;
                 Q2_zd <= q2prnk1 after DELAY_MXINP1;
        when "0001" | "0101" | "0X01" =>
                 Q1_zd <= q1rnk1  after DELAY_MXINP1;
                 Q2_zd <= q2prnk1 after DELAY_MXINP1;
        when "0010" | "0110" | "0X10" =>
                 Q1_zd <= q1rnk1  after DELAY_MXINP1;
                 Q2_zd <= q2nrnk1 after DELAY_MXINP1;
        when "1000" | "1001" | "1010" | "1011" | "10X0" | "10X1" |
             "100X" | "101X" | "10XX" =>
                 Q1_zd <= q1rnk2 after DELAY_MXINP1;
                 Q2_zd <= q2rnk2 after DELAY_MXINP1;
        when "1100" | "1101" | "1110" | "1111" | "11X0" | "11X1" |
             "110X" | "111X" | "11XX" =>
                 Q1_zd <= q1rnk3 after DELAY_MXINP1;
                 Q2_zd <= q2rnk3 after DELAY_MXINP1;
        when others =>
                 Q1_zd <= q1rnk2 after DELAY_MXINP1;
                 Q2_zd <= q2rnk2 after DELAY_MXINP1;
     end case;
  end process prcs_Q1Q2_rnk3_mux;
--------------------------------------------------------------------
  prcs_Q3Q4Q5Q6_rnk3_mux:process(q3rnk2, q3rnk3, q4rnk2, q4rnk3,  
                                 q5rnk2, q5rnk3, q6rnk2, q6rnk3)
  begin
     case AttrBitslipEnable is
        when '0'  =>
                 Q3_zd <= q3rnk2 after DELAY_MXINP1;
                 Q4_zd <= q4rnk2 after DELAY_MXINP1;
                 Q5_zd <= q5rnk2 after DELAY_MXINP1;
                 Q6_zd <= q6rnk2 after DELAY_MXINP1;
        when '1'  =>
                 Q3_zd <= q3rnk3 after DELAY_MXINP1;
                 Q4_zd <= q4rnk3 after DELAY_MXINP1;
                 Q5_zd <= q5rnk3 after DELAY_MXINP1;
                 Q6_zd <= q6rnk3 after DELAY_MXINP1;
        when others =>
                 Q3_zd <= q3rnk2 after DELAY_MXINP1;
                 Q4_zd <= q4rnk2 after DELAY_MXINP1;
                 Q5_zd <= q5rnk2 after DELAY_MXINP1;
                 Q6_zd <= q6rnk2 after DELAY_MXINP1;
     end case;
  end process prcs_Q3Q4Q5Q6_rnk3_mux;
----------------------------------------------------------------------
-----------    Inverted CLK  -----------------------------------------
----------------------------------------------------------------------

  CLKN_dly <= not CLK_dly;

----------------------------------------------------------------------
-----------    Instant BSCNTRL  --------------------------------------
----------------------------------------------------------------------
  INST_BSCNTRL : BSCNTRL
  generic map (
      SRTYPE => SRTYPE,
      INIT_BITSLIPCNT => INIT_BITSLIPCNT
     )
  port map (
      CLKDIV_INT => clkdiv_int,
      MUXC       => muxc,

      BITSLIP    => BITSLIP_dly,
      C23        => c23,
      C45        => c45,
      C67        => c67,
      CLK        => CLKN_dly,
      CLKDIV     => CLKDIV_dly,
      DATA_RATE  => AttrDataRate,
      GSR        => GSR_dly,
      R          => SR_dly,
      SEL        => sel
      );

--###################################################################
--#####           Set value of the counter in BSCNTRL           ##### 
--###################################################################
  prcs_bscntrl_cntr:process
  begin
     wait for 10 ps;
     case cntr is
        when "00100" =>
                 c23<='0'; c45<='0'; c67<='0'; sel<="00";
        when "00110" =>
                 c23<='1'; c45<='0'; c67<='0'; sel<="00";
        when "01000" =>
                 c23<='0'; c45<='0'; c67<='0'; sel<="01";
        when "01010" =>
                 c23<='0'; c45<='1'; c67<='0'; sel<="01";
        when "10010" =>
                 c23<='0'; c45<='0'; c67<='0'; sel<="00";
        when "10011" =>
                 c23<='1'; c45<='0'; c67<='0'; sel<="00";
        when "10100" =>
                 c23<='0'; c45<='0'; c67<='0'; sel<="01";
        when "10101" =>
                 c23<='0'; c45<='1'; c67<='0'; sel<="01";
        when "10110" =>
                 c23<='0'; c45<='0'; c67<='0'; sel<="10";
        when "10111" =>
                 c23<='0'; c45<='0'; c67<='1'; sel<="10";
        when "11000" =>
                 c23<='0'; c45<='0'; c67<='0'; sel<="11";
        when others =>
                assert FALSE 
                report "Error : DATA_WIDTH or DATA_RATE has illegal values."
                severity failure;
     end case;
     wait on cntr, c23, c45, c67, sel;

  end process prcs_bscntrl_cntr;
         
----------------------------------------------------------------------
-----------    Instant Clock Enable Circuit  ------------------------- 
----------------------------------------------------------------------
  INST_ICE : ICE_MODULE 
  generic map (
      SRTYPE => SRTYPE,
      INIT_CE => INIT_CE
     )
  port map (
      ICE	=> ice,

      CE1	=> CE1_dly,
      CE2	=> CE2_dly,
      GSR	=> GSR_dly,
      NUM_CE	=> AttrNumCe,
      CLKDIV	=> CLKDIV_dly,
      R		=> SR_dly 
      );
----------------------------------------------------------------------
-----------    Instant IDELAY  --------------------------------------- 
----------------------------------------------------------------------
  INST_IDELAY : IDELAY 
  generic map (
      IOBDELAY_VALUE => IOBDELAY_VALUE,
      IOBDELAY_TYPE  => IOBDELAY_TYPE
     )
  port map (
      O		=> idelay_out,

      C		=> CLKDIV_dly,
      CE	=> DLYCE_dly,
      
      I		=> D_dly,
      INC	=> DLYINC_dly,
      RST	=> DLYRST_dly
      );

--###################################################################
--#####           IOBDELAY -- Delay input Data                  ##### 
--###################################################################
  prcs_d_delay:process(D_dly, idelay_out)
  begin
     case AttrIobDelay is
        when 0 =>
               O_zd   <= D_dly;
               datain <= D_dly;
        when 1 =>
               O_zd   <= idelay_out; 
               datain <= D_dly;
        when 2 =>
               O_zd   <= D_dly; 
               datain <= idelay_out;
        when 3 =>
               O_zd   <= idelay_out; 
               datain <= idelay_out;
        when others =>
               null;
     end case;
  end process prcs_d_delay;

--####################################################################

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(O_zd, Q1_zd, Q2_zd, Q3_zd, Q4_zd, Q5_zd, Q6_zd, 
                      SHIFTOUT1_zd, SHIFTOUT2_zd)
  begin
      O  <= O_zd;
      Q1 <= Q1_zd after SYNC_PATH_DELAY;
      Q2 <= Q2_zd after SYNC_PATH_DELAY;
      Q3 <= Q3_zd after SYNC_PATH_DELAY;
      Q4 <= Q4_zd after SYNC_PATH_DELAY;
      Q5 <= Q5_zd after SYNC_PATH_DELAY;
      Q6 <= Q6_zd after SYNC_PATH_DELAY;
      SHIFTOUT1 <= SHIFTOUT1_zd after SYNC_PATH_DELAY;
      SHIFTOUT2 <= SHIFTOUT2_zd after SYNC_PATH_DELAY;
  end process prcs_output;
--####################################################################


end ISERDES_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Jtag TAP contorller 
--  /   /         
-- /___/   /\     Filename : JTAG_SIM_VIRTEX4.vhd
-- \   \  /  \    Timestamp : Fri Mar 26 08:18:21 PST 2004
--  \___\/\___\
--
-- Revision:
--    08/26/04 - Initial version.
--    07/09/05 - CR 211337 BSCAN_VIRTEX4 Reset is active on the "+" TCK when in State TLRST
--    07/20/05 - CR 212040 Added Timing
-- End Revision

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Vital_Primitives.all;
use IEEE.Vital_Timing.all;


library unisim;
use unisim.vpkg.all;
use unisim.Vcomponents.all;

entity JTAG_SIM_VIRTEX4_SUBMOD is

  generic(
      PART_NAME : string;
      IRLength  : integer
      );

  port(
      TDO	: out std_ulogic;

      TCK	: in  std_ulogic;
      TDI	: in  std_ulogic;
      TMS	: in  std_ulogic
    );

end JTAG_SIM_VIRTEX4_SUBMOD;

architecture JTAG_SIM_VIRTEX4_SUBMOD_V OF JTAG_SIM_VIRTEX4_SUBMOD is


  TYPE JtagTapState is (TestLogicReset, RunTestIdle,SelectDRScan, CaptureDR,
                        ShiftDR, Exit1DR, PauseDR, Exit2DR, UPdateDR,
                        SelectIRScan, CaptureIR, ShiftIR, Exit1IR, PauseIR,
                        Exit2IR, UPdateIR);


-------------------------------------------------------------------------------
-----------------  Virtex4 Specific Constants ---------------------------------
-------------------------------------------------------------------------------

  TYPE JtagInstructionType is (UNKNOWN, IR_CAPTURE, BYPASS, IDCODE, USER1, USER2, USER3, USER4);                  

  TYPE PartType            is (LX15, LX25, LX40, LX60, LX80, LX100, LX160, LX200,
                               SX25, SX35, SX55,
                               FX12, FX20, FX40, FX60, FX100, FX140, FX200);

  constant IRLengthMax          : integer := 14;
  constant IDLength             : integer := 32;
  constant RevBitsLength        : integer := 4;

  constant IR_CAPTURE_VAL	: std_logic_vector ((IRLengthMax -1) downto 0) := "11111111010001";
  constant BYPASS_INSTR         : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111111111";
  constant IDCODE_INSTR         : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111001001";
  constant USER1_INSTR          : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111000010";
  constant USER2_INSTR          : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111000011";
  constant USER3_INSTR          : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111100010";
  constant USER4_INSTR          : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111100011";



--------------------------------------------------------

  constant DELAY_SIG     : time := 1 ps;

  constant Xon : boolean := true;
  constant MsgOn : boolean := true;

  signal ticd_TCK     : VitalDelayType := 0.0 ns;

  signal tisd_TDI_TCK : VitalDelayType := 0.0 ns;
  signal tisd_TMS_TCK : VitalDelayType := 0.0 ns;

  signal tsetup_TMS_TCK_posedge_posedge : VitalDelayType := 1.0 ns;
  signal tsetup_TMS_TCK_negedge_posedge : VitalDelayType := 1.0 ns;

  signal tsetup_TDI_TCK_posedge_posedge : VitalDelayType := 1.0 ns;
  signal tsetup_TDI_TCK_negedge_posedge : VitalDelayType := 1.0 ns;

  signal thold_TMS_TCK_posedge_posedge : VitalDelayType := 2.0 ns;
  signal thold_TMS_TCK_negedge_posedge : VitalDelayType := 2.0 ns;

  signal thold_TDI_TCK_posedge_posedge : VitalDelayType := 2.0 ns;
  signal thold_TDI_TCK_negedge_posedge : VitalDelayType := 2.0 ns;

  signal tpd_TCK_TDO : VitalDelayType01 := (6.0 ns, 6.0 ns);

  signal CurrentState    : JtagTapState := TestLogicReset;
  signal JtagInstruction : JtagInstructionType := IDCODE;

  signal jtag_state_name	: JtagTapState		:= TestLogicReset;
  signal jtag_instruction_name	: JtagInstructionType	:= IDCODE;

  signal TCK_ipd		: std_ulogic := 'X';
  signal TDI_ipd		: std_ulogic := 'X';
  signal TMS_ipd		: std_ulogic := 'X';
  signal TRST_ipd		: std_ulogic := 'X';


  signal TCK_dly		: std_ulogic := 'X';
  signal TDI_dly		: std_ulogic := 'X';
  signal TMS_dly		: std_ulogic := 'X';
  signal TRST_dly		: std_ulogic := '0';

  signal TDO_zd			: std_ulogic := 'X';
  signal TDO_viol		: std_ulogic := 'X';

-----------     signal declaration    -------------------

  signal CaptureDR_sig          : std_ulogic := '0';
  signal RESET_sig              : std_ulogic := '0';
  signal ShiftDR_sig            : std_ulogic := '0';
  signal UpdateDR_sig           : std_ulogic := '0';

  signal ClkIR_active           : std_ulogic := '0';

  signal ClkIR_sig		: std_ulogic := '0';
  signal ClkID_sig		: std_ulogic := '0';
  signal ShiftIR_sig		: std_ulogic := 'X';
  signal UpdateIR_sig		: std_ulogic := 'X';
  signal ClkUpdateIR_sig	: std_ulogic := '0';
  signal IRcontent_sig		: std_logic_vector ((IRLength -1) downto 0) := (others => 'X');
  signal IDCODEval_sig		: std_logic_vector ((IDLength -1) downto 0) := (others => 'X');

  signal BypassReg		: std_ulogic := '0';
  signal BYPASS_sig		: std_ulogic := '0';
  signal IDCODE_sig		: std_ulogic := '0';
  signal USER1_sig		: std_ulogic := '0';
  signal USER2_sig		: std_ulogic := '0';
  signal USER3_sig		: std_ulogic := '0';
  signal USER4_sig		: std_ulogic := '0';

  signal TDO_latch              : std_ulogic := 'Z';

  signal Tlrst_sig              : std_ulogic := '1';
  signal TlrstN_sig             : std_ulogic := '1';

  signal IRegLastBit_sig        : std_ulogic := '0';
  signal IDregLastBit_sig       : std_ulogic := '0';

begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  TCK_dly        	 <= TCK            	after 0 ps;
  TDI_dly        	 <= TDI            	after 0 ps;
  TMS_dly        	 <= TMS            	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process
  variable PartName_var        : PartType;
  variable IDCODE_str          : std_ulogic_vector ((IDLength -1) downto 0) := (others => 'X');
  begin
	if((PART_NAME   = "LX15") or (PART_NAME = "lx15")) then
	      PartName_var := LX15;
	      IDCODE_str((IDLength - RevBitsLength -1) downto 0)   := X"1658093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "LX25") or (PART_NAME = "lx25")) then
	      PartName_var := LX25;
	      IDCODE_str((IDLength - RevBitsLength -1) downto 0)   := X"167C093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "LX40") or (PART_NAME = "lx40")) then
	      PartName_var := LX40;
	      IDCODE_str((IDLength - RevBitsLength -1) downto 0)   := X"16A4093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "LX60") or (PART_NAME = "lx60")) then
	      PartName_var := LX60;
	      IDCODE_str((IDLength - RevBitsLength -1) downto 0)   := X"16B4093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "LX80") or (PART_NAME = "lx80")) then
	      PartName_var := LX80;
	      IDCODE_str((IDLength - RevBitsLength -1) downto 0)   := X"16D8093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "LX100") or (PART_NAME = "lx100")) then
	      PartName_var := LX100;
	      IDCODE_str((IDLength - RevBitsLength -1) downto 0)   := X"1700093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "LX160") or (PART_NAME = "lx160")) then
	      PartName_var := LX160;
	      IDCODE_str((IDLength - RevBitsLength -1) downto 0)   := X"1718093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "LX200") or (PART_NAME = "lx200")) then
	      PartName_var := LX200;
	      IDCODE_str((IDLength - RevBitsLength -1) downto 0)   := X"1734093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "SX25") or (PART_NAME = "sx25")) then
	      PartName_var := SX25;
	      IDCODE_str((IDLength - RevBitsLength -1) downto 0)   := X"2068093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "SX35") or (PART_NAME = "sx35")) then
	      PartName_var := SX35;
	      IDCODE_str((IDLength - RevBitsLength -1) downto 0)   := X"2088093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "SX55") or (PART_NAME = "sx55")) then
	      PartName_var := SX55;
	      IDCODE_str((IDLength - RevBitsLength -1) downto 0)   := X"20B0093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "FX12") or (PART_NAME = "fx12")) then
	      PartName_var := FX12;
	      IDCODE_str((IDLength - RevBitsLength -1) downto 0)   := X"1E58093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "FX20") or (PART_NAME = "fx20")) then
	      PartName_var := FX20;
	      IDCODE_str((IDLength - RevBitsLength -1) downto 0)   := X"1E64093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "FX40") or (PART_NAME = "fx40")) then
	      PartName_var := FX40;
	      IDCODE_str((IDLength - RevBitsLength -1) downto 0)   := X"1E8C093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "FX60") or (PART_NAME = "fx60")) then
	      PartName_var := FX60;
	      IDCODE_str((IDLength - RevBitsLength -1) downto 0)   := X"1EB4093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "FX100") or (PART_NAME = "fx100")) then
	      PartName_var := FX100;
	      IDCODE_str((IDLength - RevBitsLength -1) downto 0)   := X"1EE4093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "FX140") or (PART_NAME = "fx140")) then
	      PartName_var := FX140;
	      IDCODE_str((IDLength - RevBitsLength -1) downto 0)   := X"1F14093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "FX200") or (PART_NAME = "fx200")) then
	      PartName_var := FX200;
	      IDCODE_str((IDLength - RevBitsLength -1) downto 0)   := X"1F44093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
        else
           assert false
           report "Attribute Syntax Error: The allowed values for PART_NAME are LX15, LX25, LX40, LX60, LX80, LX100, LX160, LX200, SX25, SX35, SX55, FX12, FX20, FX40, FX60, FX100, FX140 or FX200"
           severity Failure;
        end if;

        wait;

  end process prcs_init;
--####################################################################
--#####                     JtagTapSM                            #####
--####################################################################
  prcs_JtagTapSM:process(TCK_dly, TRST_dly)
  begin

     if(TRST_dly = '1') then
         CurrentState <= TestLogicReset; 
     elsif(TRST_dly = '0') then
        if(rising_edge(TCK_dly)) then
           case CurrentState is
              -------------------------------
              ----  Reset path ---------------
              -------------------------------
              when TestLogicReset =>
                 if(TMS_dly = '0') then 
                    CurrentState <= RunTestIdle;
                 end if;
              when RunTestIdle => 
                 if(TMS_dly = '1') then 
                    CurrentState <= SelectDRScan;
                 end if;
              -------------------------------
              ------  DR path ---------------
              -------------------------------
              when SelectDRScan => 
                 if(TMS_dly = '0') then 
                    CurrentState <= CaptureDR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= SelectIRScan;
                 end if;
              when CaptureDR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= ShiftDR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= Exit1DR;
                 end if;
              when ShiftDR => 
                 if(TMS_dly = '1') then 
                    CurrentState <= Exit1DR;
                 end if;
              
                 if(IRcontent_sig = BYPASS_INSTR((IRLength -1) downto 0)) then
                    BypassReg <= TDI_dly;
                 end if;

              when Exit1DR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= PauseDR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= UpdateDR;
                 end if;
              when PauseDR => 
                 if(TMS_dly = '1') then 
                    CurrentState <= Exit2DR;
                 end if;
              when Exit2DR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= ShiftDR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= UpdateDR;
                 end if;
              when UpdateDR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= RunTestIdle;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= SelectDRScan;
                 end if;
              -------------------------------
              ------  IR path ---------------
              -------------------------------
              when SelectIRScan => 
                 if(TMS_dly = '0') then 
                    CurrentState <= CaptureIR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= TestLogicReset;
                 end if;
              when CaptureIR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= ShiftIR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= Exit1IR;
                 end if;
              when ShiftIR => 
                 if(TMS_dly = '1') then 
                    CurrentState <= Exit1IR;
                 end if;
              when Exit1IR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= PauseIR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= UpdateIR;
                 end if;
              when PauseIR => 
                 if(TMS_dly = '1') then 
                    CurrentState <= Exit2IR;
                 end if;
              when Exit2IR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= ShiftIR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= UpdateIR;
                 end if;
              when UpdateIR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= RunTestIdle;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= SelectDRScan;
                 end if;
           end case;
        end if;
     end if;
  end process  prcs_JtagTapSM;

--####################################################################
--#####                     CurrentState                         #####
--####################################################################

  prcs_CurrentState:process(TCK_dly, CurrentState, TRST_dly)
  begin

     ClkIR_sig <= '1';

     if(TRST_dly = '1') then
         CaptureDR_sig <= '0';
         ShiftDR_sig   <= '0';
         UpdateDR_sig  <= '0';
         ShiftIR_sig   <= '0';
         UpdateIR_sig  <= '0';
     elsif(TRST_dly = '0') then

         case CurrentState is

            when TestLogicReset =>
                          Tlrst_sig     <= '1' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;

            when CaptureDR =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '1' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;

            when ShiftDR  =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '1' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;
 
            when UpdateDR =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '1' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;

            when CaptureIR  =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;
                          ClkIR_sig     <= TCK_dly;

 
            when ShiftIR  =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '1' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;
                          ClkIR_sig     <= TCK_dly;

            when UpdateIR =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '1' after DELAY_SIG;

            when others   =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;
         end case;
     end if;
 
  end process  prcs_CurrentState;

------------- ?? TCK  NEGATIVE EDGE activities ----------

  prcs_ClkIR:process(TCK_dly)
  begin
--     ClkIR_sig <= ShiftIR_sig and TCK_dly;
     CLkUpdateIR_sig <= UpdateIR_sig and not TCK_dly;
  end process  prcs_ClkIR;

  prcs_ClkID:process(TCK_dly)
  begin
     ClkID_sig <= IDCODE_sig and TCK_dly;
  end process  prcs_ClkID;

  prcs_glblsigs:process(TCK_dly, UpdateDR_sig)
  begin
    if(falling_edge(TCK_dly)) then
       JTAG_CAPTURE_GLBL <= CaptureDR_sig;
       -- CR 211337 Reset should go high as soon as it gets to State Trlst
       --  JTAG_RESET_GLBL   <= Tlrst_sig;
       JTAG_SHIFT_GLBL   <= ShiftDR_sig;
       JTAG_UPDATE_GLBL  <= UpdateDR_sig;
       TlrstN_sig        <= Tlrst_sig;
    end if;
  
    if(falling_edge(UpdateDR_sig))then
      JTAG_UPDATE_GLBL  <= UpdateDR_sig;
    end if; 

  end process  prcs_glblsigs;

-- CR 211337
  prcs_reset:process(Tlrst_sig)
  begin
      JTAG_RESET_GLBL   <= Tlrst_sig;
  end process  prcs_reset;
--####################################################################
--#####                       JtagIR                             #####
--####################################################################
  prcs_JtagIR:process(ClkIR_sig, ClkUpdateIR_sig, ShiftIR_sig,  TlrstN_sig, TRST_dly)
  variable NextIRreg : std_logic_vector ((IRLength -1) downto 0) := IR_CAPTURE_VAL((IRLength -1) downto 0);
  variable ir_int    : std_logic_vector ((IRLength -1) downto 0) := IR_CAPTURE_VAL((IRLength -1) downto 0);
  begin
     NextIRreg((IRLength -1) downto 0) := (TDI_dly & ir_int((IRLength -1) downto 1)); 

     if((TRST_dly = '1') or (TlrstN_sig = '1'))then
        IRcontent_sig((IRLength -1) downto 0) <= IDCODE_INSTR((IRLength -1) downto 0);  -- IDCODE instruction is loaded into IR reg.
        IRegLastBit_sig <= ir_int(0);
     elsif((TRST_dly = '0') and (TlrstN_sig = '0')) then
        if(rising_edge(ClkIR_sig)) then
           if(ShiftIR_sig = '1') then
              ir_int((IRLength -1) downto 0) := NextIRreg((IRLength -1) downto 0);
              IRegLastBit_sig <= ir_int(0);
           else
               ir_int := IR_CAPTURE_VAL((IRLength -1) downto 0);
               IRegLastBit_sig <= ir_int(0);
           end if;
        end if;
        if(rising_edge(ClkUpdateIR_sig)) then
           if(UpdateIR_sig = '1') then
              IRcontent_sig <= ir_int;
           end if;
        end if;
     end if;
  end process  prcs_JtagIR;
--####################################################################
--#####                       JtagDecodeIR                       #####
--####################################################################
  prcs_JtagDecodeIR:process(IRcontent_sig)
  begin
     if(IRcontent_sig((IRLength -1) downto 0) = IR_CAPTURE_VAL((IRLength-1) downto 0)) then
        JTagInstruction <= IR_CAPTURE;

     elsif(IRcontent_sig((IRLength -1) downto 0) = BYPASS_INSTR((IRLength-1) downto 0)) then
        JTagInstruction <= BYPASS;
        BYPASS_sig <= '1';
        IDCODE_sig <= '0';
        USER1_sig  <= '0';
        USER2_sig  <= '0';
        USER3_sig  <= '0';
        USER4_sig  <= '0';

     elsif(IRcontent_sig((IRLength -1) downto 0) = IDCODE_INSTR((IRLength-1) downto 0)) then
        JTagInstruction <= IDCODE;
        BYPASS_sig <= '0';
        IDCODE_sig <= '1';
        USER1_sig  <= '0';
        USER2_sig  <= '0';
        USER3_sig  <= '0';
        USER4_sig  <= '0';

     elsif(IRcontent_sig((IRLength -1) downto 0) = USER1_INSTR((IRLength-1) downto 0)) then
        JTagInstruction <= USER1;
        BYPASS_sig <= '0';
        IDCODE_sig <= '0';
        USER1_sig  <= '1';
        USER2_sig  <= '0';
        USER3_sig  <= '0';
        USER4_sig  <= '0';

     elsif(IRcontent_sig((IRLength -1) downto 0) = USER2_INSTR((IRLength-1) downto 0)) then
        JTagInstruction <= USER2;
        BYPASS_sig <= '0';
        IDCODE_sig <= '0';
        USER1_sig  <= '0';
        USER2_sig  <= '1';
        USER3_sig  <= '0';
        USER4_sig  <= '0';

     elsif(IRcontent_sig((IRLength -1) downto 0) = USER3_INSTR((IRLength-1) downto 0)) then
        JTagInstruction <= USER3;
        BYPASS_sig <= '0';
        IDCODE_sig <= '0';
        USER1_sig  <= '0';
        USER2_sig  <= '0';
        USER3_sig  <= '1';
        USER4_sig  <= '0';

     elsif(IRcontent_sig((IRLength -1) downto 0) = USER4_INSTR((IRLength-1) downto 0)) then
        JTagInstruction <= USER4;
        BYPASS_sig <= '0';
        IDCODE_sig <= '0';
        USER1_sig  <= '0';
        USER2_sig  <= '0';
        USER3_sig  <= '0';
        USER4_sig  <= '1';

    else
        JTagInstruction <= UNKNOWN;
        NULL; 
     end if;
  end process prcs_JtagDecodeIR;
--####################################################################
--#####                       JtagIDCODE                         #####
--####################################################################
  prcs_JtagIDCODE:process(ClkID_sig)
  variable IDreg : bit_vector ((IDLength -1) downto 0);
  begin
     if(rising_edge(ClkID_sig)) then
        if(ShiftDR_sig = '1') then
          IDreg := IDreg sra 1;
          IDreg(IDLength -1) := TO_BIT(TDI_dly);
        else
          IDreg := TO_BITVECTOR(IDCODEval_sig);
        end if;
     end if;

     IDregLastBit_sig <= TO_STDULOGIC(IDreg(0));

  end process  prcs_JtagIDCODE;
--####################################################################
--####################################################################
--#####                    JtagSetGlobalSignals                  #####
--####################################################################
  prcs_JtagSetGlobalSignals:process(ClkUpdateIR_sig, Tlrst_sig, USER1_sig, USER2_sig, USER3_sig, USER4_sig)
  begin
     if(rising_edge(USER1_sig)) then
         JTAG_SEL1_GLBL     <= '1';
         JTAG_SEL2_GLBL     <= '0';
         JTAG_SEL3_GLBL     <= '0';
         JTAG_SEL4_GLBL     <= '0';
     elsif(rising_edge(USER2_sig)) then
         JTAG_SEL1_GLBL     <= '0';
         JTAG_SEL2_GLBL     <= '1';
         JTAG_SEL3_GLBL     <= '0';
         JTAG_SEL4_GLBL     <= '0';
     elsif(rising_edge(USER3_sig)) then
         JTAG_SEL1_GLBL     <= '0';
         JTAG_SEL2_GLBL     <= '0';
         JTAG_SEL3_GLBL     <= '1';
         JTAG_SEL4_GLBL     <= '0';
     elsif(rising_edge(USER4_sig)) then
         JTAG_SEL1_GLBL     <= '0';
         JTAG_SEL2_GLBL     <= '0';
         JTAG_SEL3_GLBL     <= '0';
         JTAG_SEL4_GLBL     <= '1';
     elsif(rising_edge(ClkUpdateIR_sig)) then
         JTAG_SEL1_GLBL     <= '0';
         JTAG_SEL2_GLBL     <= '0';
         JTAG_SEL3_GLBL     <= '0';
         JTAG_SEL4_GLBL     <= '0';
     elsif(rising_edge(Tlrst_sig)) then
         JTAG_SEL1_GLBL     <= '0';
         JTAG_SEL2_GLBL     <= '0';
         JTAG_SEL3_GLBL     <= '0';
         JTAG_SEL4_GLBL     <= '0';
     end if;

  end process prcs_JtagSetGlobalSignals;
      
--####################################################################

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################

  jtag_state_name       <= CurrentState;
  jtag_instruction_name <= JtagInstruction;

  JTAG_TCK_GLBL  <= TCK_dly;
  JTAG_TDI_GLBL  <= TDI_dly;
  JTAG_TMS_GLBL  <= TMS_dly;
  JTAG_TRST_GLBL <= TRST_dly;

  TDO_latch <= BypassReg
         when ((CurrentState = ShiftDR) and (IRcontent_sig=BYPASS_INSTR((IRLength -1) downto 0)))
       else IRegLastBit_sig
         when (CurrentState = ShiftIR)
       else IDregLastBit_sig
         when ((CurrentState = ShiftDR) and (IRcontent_sig=IDCODE_INSTR((IRLength -1) downto 0)))
       else JTAG_USER_TDO1_GLBL
         when ((CurrentState = ShiftDR) and (IRcontent_sig=USER1_INSTR((IRLength -1) downto 0)))
       else JTAG_USER_TDO2_GLBL
         when ((CurrentState = ShiftDR) and (IRcontent_sig=USER2_INSTR((IRLength -1) downto 0)))
       else JTAG_USER_TDO3_GLBL
         when ((CurrentState = ShiftDR) and (IRcontent_sig=USER3_INSTR((IRLength -1) downto 0)))
       else JTAG_USER_TDO4_GLBL
         when ((CurrentState = ShiftDR) and (IRcontent_sig=USER4_INSTR((IRLength -1) downto 0)))
       else 'Z';
 
-- CR 212040 -- added timing        
--  prcs_TDO:process(TCK_dly)
--  begin
--    if(falling_edge(TCK_dly)) then
--       TDO <= TDO_latch;
--    end if;
--  end process  prcs_TDO;

--####################################################################
--#####                         Timing                           #####
--####################################################################
  VITALBehavior                    : process (TCK_dly, TDI_dly, TMS_dly)

    variable PInfo_TCK           : VitalPeriodDataType := VitalPeriodDataInit;
    variable Pviol_TCK           : std_ulogic          := '0';

    variable Tmkr_TDI_TCK_posedge  : VitalTimingDataType := VitalTimingDataInit;   
    variable Tviol_TDI_TCK_posedge : std_ulogic          := '0';

    variable Tmkr_TMS_TCK_posedge  : VitalTimingDataType := VitalTimingDataInit;   
    variable Tviol_TMS_TCK_posedge : std_ulogic          := '0';

    variable Violation : std_ulogic := '0';

    variable TDO_GlitchData : VitalGlitchDataType;


  begin
      VitalSetupHoldCheck (
        Violation            => Tviol_TDI_TCK_posedge,
        TimingData           => Tmkr_TDI_TCK_posedge,
        TestSignal           => TDI_dly,
        TestSignalName       => "TDI",
        TestDelay            => tisd_TDI_TCK,
        RefSignal            => TCK_dly,
        RefSignalName        => "TCK",
        RefDelay             => ticd_TCK,
        SetupHigh            => tsetup_TDI_TCK_posedge_posedge,
        SetupLow             => tsetup_TDI_TCK_negedge_posedge,
        HoldLow              => thold_TDI_TCK_posedge_posedge,
        HoldHigh             => thold_TDI_TCK_negedge_posedge,
        CheckEnabled         => TO_X01(TRST_dly) = '0',
        RefTransition        => 'R',
        HeaderMsg            => "/X_JTAG_SIM_VIRTEX4",
        Xon                  => Xon,
        MsgOn                => MsgOn,
        MsgSeverity          => warning);

      VitalSetupHoldCheck (
        Violation            => Tviol_TMS_TCK_posedge,
        TimingData           => Tmkr_TMS_TCK_posedge,
        TestSignal           => TMS_dly,
        TestSignalName       => "TMS",
        TestDelay            => tisd_TMS_TCK,
        RefSignal            => TCK_dly,
        RefSignalName        => "TCK",
        RefDelay             => ticd_TCK,
        SetupHigh            => tsetup_TMS_TCK_posedge_posedge,
        SetupLow             => tsetup_TMS_TCK_negedge_posedge,
        HoldLow              => thold_TMS_TCK_posedge_posedge,
        HoldHigh             => thold_TMS_TCK_negedge_posedge,
        CheckEnabled         => TO_X01(TRST_dly) = '0',
        RefTransition        => 'R',
        HeaderMsg            => "/X_JTAG_SIM_VIRTEX4",
        Xon                  => Xon,
        MsgOn                => MsgOn,
        MsgSeverity          => warning);

    VitalPathDelay01 (
      OutSignal              => TDO,
      GlitchData             => TDO_GlitchData,
      OutSignalName          => "TDO",
      OutTemp                => TDO_latch,
      Paths                  => (0 => (TCK_dly'last_event, tpd_TCK_TDO, TRST_dly = '0')),
      Mode                   => VitalTransport,
      Xon                    => Xon,
      MsgOn                  => MsgOn,
      MsgSeverity            => warning);
  end process;



--####################################################################
--####################################################################


end JTAG_SIM_VIRTEX4_SUBMOD_V;


----- CELL JTAG_SIM_VIRTEX4  -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.vpkg.all;
use unisim.Vcomponents.all;

entity JTAG_SIM_VIRTEX4 is

  generic(
      PART_NAME : string := "LX15"
      );

  port(
      TDO	: out std_ulogic;

      TCK	: in  std_ulogic;
      TDI	: in  std_ulogic;
      TMS	: in  std_ulogic
    );

end JTAG_SIM_VIRTEX4;

architecture JTAG_SIM_VIRTEX4_V OF JTAG_SIM_VIRTEX4 is

  component JTAG_SIM_VIRTEX4_SUBMOD
     generic(
         PART_NAME : string;
         IRLength  : integer
         );

     port(
         TDO       : out std_ulogic;

         TCK       : in  std_ulogic;
         TDI       : in  std_ulogic;
         TMS       : in  std_ulogic
       );
  end component;

  signal TCK_ipd		: std_ulogic := 'X';
  signal TDI_ipd		: std_ulogic := 'X';
  signal TMS_ipd		: std_ulogic := 'X';
  signal TRST_ipd		: std_ulogic := 'X';


  signal TCK_dly		: std_ulogic := 'X';
  signal TDI_dly		: std_ulogic := 'X';
  signal TMS_dly		: std_ulogic := 'X';
  signal TRST_dly		: std_ulogic := '0';

  signal TDO_zd			: std_ulogic := 'X';
  signal TDO_viol		: std_ulogic := 'X';

  signal TDO1_zd                : std_ulogic := 'X';
  signal TDO2_zd                : std_ulogic := 'X';

  signal IRLen10, IRLen14       : boolean := false;




begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  TCK_dly        	 <= TCK            	after 0 ps;
  TDI_dly        	 <= TDI            	after 0 ps;
  TMS_dly        	 <= TMS            	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------


--####################################################################
--#####                   Initialization                         #####
--####################################################################
  prcs_init:process
  begin
      if((PART_NAME   = "LX15") or (PART_NAME = "lx15") or
         (PART_NAME   = "LX25") or (PART_NAME = "lx25") or
         (PART_NAME   = "LX40") or (PART_NAME = "lx40") or
         (PART_NAME   = "LX60") or (PART_NAME = "lx60") or
         (PART_NAME   = "LX80") or (PART_NAME = "lx80") or
         (PART_NAME   = "LX100") or (PART_NAME = "lx100") or
         (PART_NAME   = "LX200") or (PART_NAME = "lx200") or
         (PART_NAME   = "SX25") or (PART_NAME = "sx25") or
         (PART_NAME   = "SX35") or (PART_NAME = "sx35") or
         (PART_NAME   = "SX55") or (PART_NAME = "sx55") or
         (PART_NAME   = "FX12") or (PART_NAME = "fx12") or
         (PART_NAME   = "FX20") or (PART_NAME = "fx20")) then
          IRLen10 <= true;
      elsif((PART_NAME   = "FX40") or (PART_NAME = "fx40") or
         (PART_NAME   = "FX60") or (PART_NAME = "fx60") or
         (PART_NAME   = "FX100") or (PART_NAME = "fx100") or
         (PART_NAME   = "FX140") or (PART_NAME = "fx140") or
         (PART_NAME   = "FX200") or (PART_NAME = "fx200")) then
          IRLen14 <= true;
      end if;

      wait;

  end process prcs_init;

--####################################################################
--#####                       Generate                           #####
--####################################################################
  G1: if((PART_NAME   = "LX15") or (PART_NAME = "lx15") or
         (PART_NAME   = "LX25") or (PART_NAME = "lx25") or
         (PART_NAME   = "LX40") or (PART_NAME = "lx40") or
         (PART_NAME   = "LX60") or (PART_NAME = "lx60") or
         (PART_NAME   = "LX80") or (PART_NAME = "lx80") or
         (PART_NAME   = "LX100") or (PART_NAME = "lx100") or
         (PART_NAME   = "LX200") or (PART_NAME = "lx200") or
         (PART_NAME   = "SX25") or (PART_NAME = "sx25") or
         (PART_NAME   = "SX35") or (PART_NAME = "sx35") or
         (PART_NAME   = "SX55") or (PART_NAME = "sx55") or
         (PART_NAME   = "FX12") or (PART_NAME = "fx12") or
         (PART_NAME   = "FX20") or (PART_NAME = "fx20")) generate
          
        JTAG_INST : JTAG_SIM_VIRTEX4_SUBMOD
          generic map (
            PART_NAME => PART_NAME,
            IRLength  => 10
          )
          port map (
            TDO => TDO1_zd,
            TCK => TCK_dly,
            TDI => TDI_dly,
            TMS => TMS_dly
          );

  end generate;   

  G2: if((PART_NAME   = "FX40") or (PART_NAME = "fx40") or
         (PART_NAME   = "FX60") or (PART_NAME = "fx60") or
         (PART_NAME   = "FX100") or (PART_NAME = "fx100") or
         (PART_NAME   = "FX140") or (PART_NAME = "fx140") or
         (PART_NAME   = "FX200") or (PART_NAME = "fx200")) generate

        JTAG_INST : JTAG_SIM_VIRTEX4_SUBMOD
          generic map (
            PART_NAME => PART_NAME,
            IRLength  => 14
          )
          port map (
            TDO => TDO2_zd,
            TCK => TCK_dly,
            TDI => TDI_dly,
            TMS => TMS_dly
          );

  end generate;   


         
--####################################################################

  TDO <= TDO1_zd when IRLen10 else
         TDO2_zd when IRLen14;


end JTAG_SIM_VIRTEX4_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                  Dual Data Rate Output D Flip-Flop
-- /___/   /\     Filename : ODDR.vhd
-- \   \  /  \    Timestamp : Fri Mar 26 08:18:20 PST 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL ODDR -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;


library unisim;
use unisim.vpkg.all;

entity ODDR is

  generic(

      DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
      INIT         : bit    := '0';
      SRTYPE       : string := "SYNC"
      );

  port(
      Q           : out std_ulogic;

      C           : in  std_ulogic;
      CE          : in  std_ulogic;
      D1          : in  std_ulogic;
      D2          : in  std_ulogic;
      R           : in  std_ulogic;
      S           : in  std_ulogic
    );

end ODDR;

architecture ODDR_V OF ODDR is


  constant SYNC_PATH_DELAY : time := 100 ps;

  signal C_ipd	        : std_ulogic := 'X';
  signal CE_ipd	        : std_ulogic := 'X';
  signal D1_ipd	        : std_ulogic := 'X';
  signal D2_ipd	        : std_ulogic := 'X';
  signal GSR            : std_ulogic := '0';
  signal GSR_ipd	: std_ulogic := 'X';
  signal R_ipd		: std_ulogic := 'X';
  signal S_ipd		: std_ulogic := 'X';

  signal C_dly	        : std_ulogic := 'X';
  signal CE_dly	        : std_ulogic := 'X';
  signal D1_dly	        : std_ulogic := 'X';
  signal D2_dly	        : std_ulogic := 'X';
  signal GSR_dly	: std_ulogic := 'X';
  signal R_dly		: std_ulogic := 'X';
  signal S_dly		: std_ulogic := 'X';

  signal Q_zd		: std_ulogic := 'X';

  signal Q_viol		: std_ulogic := 'X';

  signal ddr_clk_edge_type	: integer := -999;
  signal sr_type		: integer := -999;

begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  C_dly          	 <= C              	after 0 ps;
  CE_dly         	 <= CE             	after 0 ps;
  D1_dly         	 <= D1             	after 0 ps;
  D2_dly         	 <= D2             	after 0 ps;
  GSR_dly        	 <= GSR            	after 0 ps;
  R_dly          	 <= R              	after 0 ps;
  S_dly          	 <= S              	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process

  begin
      if((DDR_CLK_EDGE = "OPPOSITE_EDGE") or (DDR_CLK_EDGE = "opposite_edge")) then
         ddr_clk_edge_type <= 1;
      elsif((DDR_CLK_EDGE = "SAME_EDGE") or (DDR_CLK_EDGE = "same_edge")) then
         ddr_clk_edge_type <= 2;
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " DDR_CLK_EDGE ",
             EntityName => "/ODDR",
             GenericValue => DDR_CLK_EDGE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " OPPOSITE_EDGE or SAME_EDGE.",
             TailMsg => "",
             MsgSeverity => ERROR 
         );
      end if;

      if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
         sr_type <= 1;
      elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
         sr_type <= 2;
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " SRTYPE ",
             EntityName => "/ODDR",
             GenericValue => SRTYPE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " ASYNC or SYNC. ",
             TailMsg => "",
             MsgSeverity => ERROR
         );
      end if;

     wait;
  end process prcs_init;
--####################################################################
--#####                       q1_q2_q3 reg                       #####
--####################################################################
  prcs_q1q2q3_reg:process(C_dly, GSR_dly, R_dly, S_dly)
  variable Q1_var         : std_ulogic := TO_X01(INIT);
  variable Q2_posedge_var : std_ulogic := TO_X01(INIT);
  begin
     if(GSR_dly = '1') then
         Q1_var         := TO_X01(INIT);
         Q2_posedge_var := TO_X01(INIT);
     elsif(GSR_dly = '0') then
        case sr_type is
           when 1 => 
                   if(R_dly = '1') then
                      Q1_var := '0';
                      Q2_posedge_var := '0';
                   elsif((R_dly = '0') and (S_dly = '1')) then
                      Q1_var := '1';
                      Q2_posedge_var := '1';
                   elsif((R_dly = '0') and (S_dly = '0')) then
                      if(CE_dly = '1') then
                         if(rising_edge(C_dly)) then
                            Q1_var         := D1_dly;
                            Q2_posedge_var := D2_dly;
                         end if;
                         if(falling_edge(C_dly)) then
                             case ddr_clk_edge_type is
                                when 1 => 
                                       Q1_var :=  D2_dly;
                                when 2 => 
                                       Q1_var :=  Q2_posedge_var;
                                when others =>
                                          null;
                              end case;
                         end if;
                      end if;
                   end if;

           when 2 => 
                   if(rising_edge(C_dly)) then
                      if(R_dly = '1') then
                         Q1_var := '0';
                         Q2_posedge_var := '0';
                      elsif((R_dly = '0') and (S_dly = '1')) then
                         Q1_var := '1';
                         Q2_posedge_var := '1';
                      elsif((R_dly = '0') and (S_dly = '0')) then
                         if(CE_dly = '1') then
                            Q1_var         := D1_dly;
                            Q2_posedge_var := D2_dly;
                         end if;
                      end if;
                   end if;
                        
                   if(falling_edge(C_dly)) then
                      if(R_dly = '1') then
                         Q1_var := '0';
                      elsif((R_dly = '0') and (S_dly = '1')) then
                         Q1_var := '1';
                      elsif((R_dly = '0') and (S_dly = '0')) then
                         if(CE_dly = '1') then
                             case ddr_clk_edge_type is
                                when 1 => 
                                       Q1_var :=  D2_dly;
                                when 2 => 
                                       Q1_var :=  Q2_posedge_var;
                                when others =>
                                          null;
                              end case;
                         end if;
                      end if;
                   end if;
 
           when others =>
                   null; 
        end case;
     end if;

     Q_zd <= Q1_var;

  end process prcs_q1q2q3_reg;
--####################################################################

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(Q_zd)
  begin
      Q <= Q_zd after SYNC_PATH_DELAY;
  end process prcs_output;
--####################################################################


end ODDR_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                  Source Synchronous Output Serializer
-- /___/   /\     Filename : OSERDES.vhd
-- \   \  /  \    Timestamp : Fri Mar 26 08:18:21 PST 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    01/23/06 - 223369 fixed Vital delays from CLK to OQ
--    05/29/06 - CR 232324 -- Added timing checks for REV/SR wrt negedge CLKDIV
--    08/08/06 - CR 225414 -- Added 100 ps delay to data inputs to resolve
--               race condition when data/clk change at the same time.
--    01/08/08 - CR 458156 -- enabled TRISTATE_WIDTH to be 1 in DDR mode.
-- End Revision

----- CELL OSERDES -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;


library unisim;
use unisim.vpkg.all;

entity PLG is

  generic(

         SRTYPE			: string;

         INIT_LOADCNT		: bit_vector(3 downto 0)
    );

  port(
      LOAD		: out std_ulogic;

      C23		: in std_ulogic;
      C45		: in std_ulogic;
      C67		: in std_ulogic;
      CLK		: in std_ulogic;
      CLKDIV		: in std_ulogic;
      RST		: in std_ulogic;
      SEL		: in std_logic_vector (1 downto 0)
    );

end PLG;

architecture PLG_V OF PLG is


  constant DELAY_FFDCNT		: time       := 1 ps;
  constant DELAY_MXDCNT		: time       := 1 ps;
  constant DELAY_FFRST		: time       := 145 ps;

  constant MSB_SEL		: integer    := 1;

  signal CLK_ipd                : std_ulogic := 'X';
  signal CLKDIV_ipd             : std_ulogic := 'X';
  signal C23_ipd                : std_ulogic := 'X';
  signal C45_ipd                : std_ulogic := 'X';
  signal C67_ipd                : std_ulogic := 'X';
  signal GSR            : std_ulogic := '0';
  signal GSR_ipd                : std_ulogic := 'X';
  signal RST_ipd                : std_ulogic := 'X';
  signal SEL_ipd                : std_logic_vector(1 downto 0) := (others => 'X');

  signal CLK_dly                : std_ulogic := 'X';
  signal CLKDIV_dly             : std_ulogic := 'X';
  signal C23_dly                : std_ulogic := 'X';
  signal C45_dly                : std_ulogic := 'X';
  signal C67_dly                : std_ulogic := 'X';
  signal GSR_dly                : std_ulogic := 'X';
  signal RST_dly                : std_ulogic := 'X';
  signal SEL_dly                : std_logic_vector(1 downto 0) := (others => 'X');

  signal q0			: std_ulogic := 'X';
  signal q1			: std_ulogic := 'X';
  signal q2			: std_ulogic := 'X';
  signal q3			: std_ulogic := 'X';

  signal qhr			: std_ulogic := 'X';
  signal qlr			: std_ulogic := 'X';

  signal mux			: std_ulogic := 'X';

  signal load_zd		: std_ulogic := 'X';

  signal AttrSRtype		: std_ulogic := 'X';

begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  C23_dly        	 <= C23            	after 0 ps;
  C45_dly        	 <= C45            	after 0 ps;
  C67_dly        	 <= C67            	after 0 ps;
  CLK_dly        	 <= CLK            	after 0 ps;
  CLKDIV_dly     	 <= CLKDIV         	after 0 ps;
  GSR_dly        	 <= GSR            	after 0 ps;
  RST_dly        	 <= RST            	after 0 ps;
  SEL_dly        	 <= SEL            	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------


--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process
  begin
     if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
        AttrSRtype <= '1';
     elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
        AttrSRtype <= '0';
     end if;

     wait;
  end process prcs_init;
--####################################################################
--#####                          Counter                         #####
--####################################################################
  prcs_ff_cntr:process(qhr, CLK, GSR)
  variable q3_var		:  std_ulogic := TO_X01(INIT_LOADCNT(3));
  variable q2_var		:  std_ulogic := TO_X01(INIT_LOADCNT(2));
  variable q1_var		:  std_ulogic := TO_X01(INIT_LOADCNT(1));
  variable q0_var		:  std_ulogic := TO_X01(INIT_LOADCNT(0));
  begin
     if(GSR = '1') then
         q3_var		:= TO_X01(INIT_LOADCNT(3));
         q2_var		:= TO_X01(INIT_LOADCNT(2));
         q1_var		:= TO_X01(INIT_LOADCNT(1));
         q0_var		:= TO_X01(INIT_LOADCNT(0));
     elsif(GSR = '0') then
        case AttrSRtype is
           when '1' => 
           --------------- // async SET/RESET
                   if(qhr = '1') then
                      q0_var := '0';
                      q1_var := '0';
                      q2_var := '0';
                      q3_var := '0';
                   else
                      if(rising_edge(CLK)) then
                         q3_var := q2_var;
                         q2_var :=( NOT((NOT q0_var) and (NOT q2_var)) and q1_var);
                         q1_var := q0_var;
                         q0_var := mux;
                      end if;
                   end if;

           when '0' => 
           --------------- // sync SET/RESET
                   if(rising_edge(CLK)) then
                      if(qhr = '1') then
                         q0_var := '0';
                         q1_var := '0';
                         q2_var := '0';
                         q3_var := '0';
                      else
                         q3_var := q2_var;
                         q2_var :=( NOT((NOT q0_var) and (NOT q2_var)) and q1_var);
                         q1_var := q0_var;
                         q0_var := mux;
                      end if;
                   end if;

           when others => 
                   null;
           end case;

           q0 <= q0_var after DELAY_FFDCNT;
           q1 <= q1_var after DELAY_FFDCNT;
           q2 <= q2_var after DELAY_FFDCNT;
           q3 <= q3_var after DELAY_FFDCNT;

     end if;
  end process prcs_ff_cntr;
--####################################################################
--#####                     mux signal                           #####
--####################################################################
  prcs_mux_sel:process(sel, c23, c45, c67, q0, q1, q2, q3)
  begin
    case sel is
        when "00" =>
              mux <=  ((not q0) and  (not(c23 and q1))) after DELAY_MXDCNT;
        when "01" =>
              mux <=  ((not q1) and  (not(c45 and q2))) after DELAY_MXDCNT;
        when "10" =>
              mux <=  ((not q2) and  (not(c67 and q3))) after DELAY_MXDCNT;
        when "11" =>
              mux <=  (not (q3)) after DELAY_MXDCNT;
        when others =>
              mux <=  '0' after DELAY_MXDCNT;
    end case;
  end process prcs_mux_sel;
--####################################################################
--#####                    load signal                           #####
--####################################################################
  prcs_load_sel:process(sel, c23, c45, c67, q0, q1, q2, q3)
  begin
    case sel is
        when "00" =>
              load_zd <=  q0 after DELAY_MXDCNT;
        when "01" =>
              load_zd <=  (q0 and q1) after DELAY_MXDCNT;
        when "10" =>
              load_zd <=  (q0 and q2) after DELAY_MXDCNT;
        when "11" =>
              load_zd <=  (q0 and q3) after DELAY_MXDCNT;
        when others =>
              load_zd <=  '0' after DELAY_MXDCNT;
    end case;
  end process prcs_load_sel;
--####################################################################
--#####                 Low/High speed  FFs                      #####
--####################################################################
  prcs_lowspeed:process(clkdiv, rst)
  begin
      case AttrSRtype is
          when '1' => 
           --------------- // async SET/RESET
               if(rst = '1') then
                  qlr        <= '1' after DELAY_FFRST;
               else 
                  if(rising_edge(clkdiv)) then
                     qlr      <= '0' after DELAY_FFRST;
                  end if;
               end if;

          when '0' => 
           --------------- // sync SET/RESET
               if(rising_edge(clkdiv)) then
                  if(rst = '1') then
                     qlr      <= '1' after DELAY_FFRST;
                  else 
                     qlr      <= '0' after DELAY_FFRST;
                  end if;
               end if;
          when others => 
                  null;
      end case;
  end process  prcs_lowspeed;
----------------------------------------------------------------------
  prcs_highspeed:process(clk, rst)
  begin
      case AttrSRtype is
          when '1' => 
           --------------- // async SET/RESET
               if(rst = '1') then
                  qhr <= '1' after DELAY_FFDCNT;
               else 
                  if(rising_edge(clk)) then
                     qhr <= qlr after DELAY_FFDCNT;
                  end if;
               end if;

          when '0' => 
           --------------- // sync SET/RESET
               if(rising_edge(clk)) then
                  if(rst = '1') then
                     qhr <= '1' after DELAY_FFDCNT;
                  else 
                     qhr <= qlr after DELAY_FFDCNT;
                  end if;
               end if;
          when others => 
                  null;
      end case;
  end process  prcs_highspeed;


--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(load_zd)
  begin
      load <= load_zd;
  end process prcs_output;
--####################################################################


end PLG_V;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;


library unisim;
use unisim.vpkg.all;

entity IOOUT is

  generic(

         SERDES			: boolean	:= TRUE;
         SERDES_MODE		: string	:= "MASTER";
         DATA_RATE_OQ		: string	:= "DDR";
         DATA_WIDTH		: integer	:= 4;
         DDR_CLK_EDGE		: string	:= "SAME_EDGE";
         INIT_OQ		: bit		:= '0';
         SRVAL_OQ		: bit		:= '1';
         INIT_ORANK1		: bit_vector(5 downto 0) := "000000";
         INIT_ORANK2_PARTIAL	: bit_vector(3 downto 0) := "0000";
         INIT_LOADCNT		: bit_vector(3 downto 0) := "0000";

         SRTYPE			: string	:= "ASYNC"
    );

  port(
      OQ		: out std_ulogic;
      LOAD		: out std_ulogic;
      SHIFTOUT1		: out std_ulogic;
      SHIFTOUT2		: out std_ulogic;

      C			: in std_ulogic;
      CLKDIV		: in std_ulogic;
      D1		: in std_ulogic;
      D2		: in std_ulogic;
      D3		: in std_ulogic;
      D4		: in std_ulogic;
      D5		: in std_ulogic;
      D6		: in std_ulogic;
      OCE		: in std_ulogic;
      REV	        : in std_ulogic;
      SR	        : in std_ulogic;
      SHIFTIN1		: in std_ulogic;
      SHIFTIN2		: in std_ulogic
    );

end IOOUT;

architecture IOOUT_V OF IOOUT is

component PLG
  generic(
      SRTYPE            : string;
      INIT_LOADCNT      : bit_vector(3 downto 0)
      );
  port(
      LOAD              : out std_ulogic;

      C23               : in std_ulogic;
      C45               : in std_ulogic;
      C67               : in std_ulogic;
      CLK               : in std_ulogic;
      CLKDIV            : in std_ulogic;
      RST               : in std_ulogic;
      SEL               : in std_logic_vector (1 downto 0)
      );

end component;

  constant DELAY_FFD            : time       := 1 ps; 
  constant DELAY_FFCD           : time       := 1 ps; 
  constant DELAY_MXD	        : time       := 1 ps;
  constant DELAY_MXR1	        : time       := 1 ps;

  constant SWALLOW_PULSE        : time       := 2 ps;

  constant MAX_DATAWIDTH	: integer    := 4;

  signal C_ipd		        : std_ulogic := 'X';
  signal CLKDIV_ipd		: std_ulogic := 'X';
  signal D1_ipd			: std_ulogic := 'X';
  signal D2_ipd			: std_ulogic := 'X';
  signal D3_ipd			: std_ulogic := 'X';
  signal D4_ipd			: std_ulogic := 'X';
  signal D5_ipd			: std_ulogic := 'X';
  signal D6_ipd			: std_ulogic := 'X';
  signal GSR            : std_ulogic := '0';
  signal GSR_ipd		: std_ulogic := 'X';
  signal OCE_ipd	        : std_ulogic := 'X';
  signal REV_ipd	        : std_ulogic := 'X';
  signal SR_ipd		        : std_ulogic := 'X';
  signal SHIFTIN1_ipd		: std_ulogic := 'X';
  signal SHIFTIN2_ipd		: std_ulogic := 'X';

  signal C_dly	                : std_ulogic := 'X';
  signal CLKDIV_dly		: std_ulogic := 'X';
  signal D1_dly			: std_ulogic := 'X';
  signal D2_dly			: std_ulogic := 'X';
  signal D3_dly			: std_ulogic := 'X';
  signal D4_dly			: std_ulogic := 'X';
  signal D5_dly			: std_ulogic := 'X';
  signal D6_dly			: std_ulogic := 'X';
  signal GSR_dly		: std_ulogic := 'X';
  signal OCE_dly	        : std_ulogic := 'X';
  signal REV_dly	        : std_ulogic := 'X';
  signal SR_dly		        : std_ulogic := 'X';
  signal SHIFTIN1_dly		: std_ulogic := 'X';
  signal SHIFTIN2_dly		: std_ulogic := 'X';

  signal OQ_zd			: std_ulogic := TO_X01(INIT_OQ);
  signal LOAD_zd		: std_ulogic := 'X';
  signal SHIFTOUT1_zd		: std_ulogic := 'X';
  signal SHIFTOUT2_zd		: std_ulogic := 'X';

  signal AttrDataRateOQ		: std_ulogic := 'X';
  signal AttrDataRateTQ		: std_logic_vector(1 downto 0) := (others => 'X');
  signal AttrDataWidth		: std_logic_vector(3 downto 0) := (others => 'X');
  signal AttrTriStateWidth	: std_logic_vector(1 downto 0) := (others => 'X');
  signal AttrMode		: std_ulogic := 'X';
  signal AttrDdrClkEdge		: std_ulogic := 'X';

  signal AttrSRtype		: std_logic_vector(5 downto 0) := (others => '1');

  signal AttrSerdes		: std_ulogic := 'X';

  signal d1r			: std_ulogic := 'X';
  signal d2r			: std_ulogic := 'X';
  signal d3r			: std_ulogic := 'X';
  signal d4r			: std_ulogic := 'X';
  signal d5r			: std_ulogic := 'X';
  signal d6r			: std_ulogic := 'X';

  signal d1rnk2			: std_ulogic := 'X';
  signal d2rnk2			: std_ulogic := 'X';
  signal d2nrnk2		: std_ulogic := 'X';
  signal d3rnk2			: std_ulogic := 'X';
  signal d4rnk2			: std_ulogic := 'X';
  signal d5rnk2			: std_ulogic := 'X';
  signal d6rnk2			: std_ulogic := 'X';

  signal data1			: std_ulogic := 'X';
  signal data2			: std_ulogic := 'X';
  signal data3			: std_ulogic := 'X';
  signal data4			: std_ulogic := 'X';
  signal data5			: std_ulogic := 'X';
  signal data6			: std_ulogic := 'X';

  signal ddr_data		: std_ulogic := 'X';
  signal odata_edge		: std_ulogic := 'X';
  signal sdata_edge		: std_ulogic := 'X';

  signal c23			: std_ulogic := 'X';
  signal c45			: std_ulogic := 'X';
  signal c67			: std_ulogic := 'X';

  signal sel			: std_logic_vector(1 downto 0) := (others => 'X');

  signal C2p			: std_ulogic := 'X';
  signal C3			: std_ulogic := 'X';

  signal loadint		: std_ulogic := 'X';

  signal seloq			: std_logic_vector(3 downto 0) := (others => 'X');

  signal oqsr			: std_ulogic := 'X';

  signal oqrev			: std_ulogic := 'X';

  signal sel1_4			: std_logic_vector(2 downto 0) := (others => 'X');
  signal sel5_6			: std_logic_vector(3 downto 0) := (others => 'X');

  signal plgcnt			: std_logic_vector(4 downto 0) := (others => 'X');

begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  C_dly          	 <= C              	after 0 ps;
  CLKDIV_dly     	 <= CLKDIV         	after 0 ps;
  D1_dly         	 <= D1             	after 0 ps;
  D2_dly         	 <= D2             	after 0 ps;
  D3_dly         	 <= D3             	after 0 ps;
  D4_dly         	 <= D4             	after 0 ps;
  D5_dly         	 <= D5             	after 0 ps;
  D6_dly         	 <= D6             	after 0 ps;
  GSR_dly        	 <= GSR            	after 0 ps;
  OCE_dly        	 <= OCE            	after 0 ps;
  REV_dly        	 <= REV            	after 0 ps;
  SR_dly         	 <= SR             	after 0 ps;
  SHIFTIN1_dly   	 <= SHIFTIN1       	after 0 ps;
  SHIFTIN2_dly   	 <= SHIFTIN2       	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process
  variable AttrDataRateOQ_var		: std_ulogic := 'X';
  variable AttrDataWidth_var		: std_logic_vector(3 downto 0) := (others => 'X');
  variable AttrMode_var			: std_ulogic := 'X';
  variable AttrDdrClkEdge_var		: std_ulogic := 'X';
  variable AttrSerdes_var		: std_ulogic := 'X';

  begin
      -------------------- SERDES validity check --------------------
      if(SERDES = true) then
        AttrSerdes_var := '1';
      else
        AttrSerdes_var := '0';
      end if;

      ------------ SERDES_MODE validity check --------------------
      if((SERDES_MODE = "MASTER") or (SERDES_MODE = "master")) then
         AttrMode_var := '0';
      elsif((SERDES_MODE = "SLAVE") or (SERDES_MODE = "slave")) then
         AttrMode_var := '1';
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => "SERDES_MODE ",
             EntityName => "/IOOUT",
             GenericValue => SERDES_MODE,
             Unit => "",
             ExpectedValueMsg => " The legal values for this attribute are ",
             ExpectedGenericValue => " MASTER or SLAVE.",
             TailMsg => "",
             MsgSeverity => FAILURE 
         );
      end if;

      ------------------ DATA_RATE validity check ------------------

      if((DATA_RATE_OQ = "DDR") or (DATA_RATE_OQ = "ddr")) then
         AttrDataRateOQ_var := '0';
      elsif((DATA_RATE_OQ = "SDR") or (DATA_RATE_OQ = "sdr")) then
         AttrDataRateOQ_var := '1';
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " DATA_RATE_OQ ",
             EntityName => "/IOOUT",
             GenericValue => DATA_RATE_OQ,
             Unit => "",
             ExpectedValueMsg => " The legal values for this attribute are ",
             ExpectedGenericValue => " DDR or SDR. ",
             TailMsg => "",
             MsgSeverity => Failure
         );
      end if;

      ------------------ DATA_WIDTH validity check ------------------
      if((DATA_WIDTH = 2) or (DATA_WIDTH = 3) or  (DATA_WIDTH = 4) or
         (DATA_WIDTH = 5) or (DATA_WIDTH = 6) or  (DATA_WIDTH = 7) or
         (DATA_WIDTH = 8) or (DATA_WIDTH = 10)) then
         AttrDataWidth_var := CONV_STD_LOGIC_VECTOR(DATA_WIDTH, MAX_DATAWIDTH); 
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " DATA_WIDTH ",
             EntityName => "/IOOUT",
             GenericValue => DATA_WIDTH,
             Unit => "",
             ExpectedValueMsg => " The legal values for this attribute are ",
             ExpectedGenericValue => " 2, 3, 4, 5, 6, 7, 8, or 10 ",
             TailMsg => "",
             MsgSeverity => Failure
         );
      end if;
      ------------ DATA_WIDTH /DATA_RATE combination check ------------
      if((DATA_RATE_OQ = "DDR") or (DATA_RATE_OQ = "ddr")) then
         case (DATA_WIDTH) is
             when 4|6|8|10  => null;
             when others       =>
                GenericValueCheckMessage
                (  HeaderMsg  => " Attribute Syntax Warning ",
                   GenericName => " DATA_WIDTH ",
                   EntityName => "/IOOUT",
                   GenericValue => DATA_WIDTH,
                   Unit => "",
                   ExpectedValueMsg => " The legal values for this attribute in DDR mode are ",
                   ExpectedGenericValue => " 4, 6, 8, or 10 ",
                   TailMsg => "",
                   MsgSeverity => Failure
                );
          end case;
      end if;

      if((DATA_RATE_OQ = "SDR") or (DATA_RATE_OQ = "sdr")) then
         case (DATA_WIDTH) is
             when 2|3|4|5|6|7|8  => null;
             when others       =>
                GenericValueCheckMessage
                (  HeaderMsg  => " Attribute Syntax Warning ",
                   GenericName => " DATA_WIDTH ",
                   EntityName => "/IOOUT",
                   GenericValue => DATA_WIDTH,
                   Unit => "",
                   ExpectedValueMsg => " The legal values for this attribute in SDR mode are ",
                   ExpectedGenericValue => " 2, 3, 4, 5, 6, 7 or 8.",
                   TailMsg => "",
                   MsgSeverity => Failure
                );
          end case;
      end if;

      ------------------ DDR_CLK_EDGE validity check ------------------

      if((DDR_CLK_EDGE = "SAME_EDGE") or (DDR_CLK_EDGE = "same_edge")) then
         AttrDdrClkEdge_var := '1';
      elsif((DDR_CLK_EDGE = "OPPOSITE_EDGE") or (DDR_CLK_EDGE = "opposite_edge")) then
         AttrDdrClkEdge_var := '0';
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " DDR_CLK_EDGE ",
             EntityName => "/IOOUT",
             GenericValue => DDR_CLK_EDGE,
             Unit => "",
             ExpectedValueMsg => " The legal values for this attribute are ",
             ExpectedGenericValue => " SAME_EDGE or OPPOSITE_EDGE ",
             TailMsg => "",
             MsgSeverity => Failure
         );
      end if;
      ------------------ DATA_RATE validity check ------------------
      if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
         AttrSRtype  <= (others => '1');
      elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
         AttrSRtype  <= (others => '0');
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " SRTYPE ",
             EntityName => "/IOOUT",
             GenericValue => SRTYPE,
             Unit => "",
             ExpectedValueMsg => " The legal values for this attribute are ",
             ExpectedGenericValue => " ASYNC or SYNC. ",
             TailMsg => "",
             MsgSeverity => ERROR
         );
      end if;

      AttrSerdes		<= AttrSerdes_var;
      AttrMode		<= AttrMode_var;
      AttrDataRateOQ	<= AttrDataRateOQ_var;
      AttrDataWidth	<= AttrDataWidth_var;
      AttrDdrClkEdge	<= AttrDdrClkEdge_var;

      plgcnt     <= AttrDataRateOQ_var & AttrDataWidth_var; 

      wait;
  end process prcs_init;
--###################################################################
--#####                   Concurrent exe                        #####
--###################################################################
   C2p    <= (C_dly and AttrDdrClkEdge) or 
             ((not C_dly) and (not AttrDdrClkEdge)); 
   C3     <= not C2p;
   sel1_4 <= AttrSerdes & loadint & AttrDataRateOQ;
   sel5_6 <= AttrSerdes & AttrMode & loadint & AttrDataRateOQ;
   LOAD_zd <= loadint;
   seloq   <= OCE_dly & AttrDataRateOQ & oqsr & oqrev;
   
   oqsr    <= ((AttrSRtype(1) and SR_dly and not (TO_X01(SRVAL_OQ)))
                               or
                (AttrSRtype(1) and REV_dly and (TO_X01(SRVAL_OQ))));

   oqrev   <= ((AttrSRtype(1) and SR_dly and (TO_X01(SRVAL_OQ)))
                               or
                (AttrSRtype(1) and REV_dly and not (TO_X01(SRVAL_OQ))));

   SHIFTOUT1_zd <= d3rnk2 and AttrMode;
   SHIFTOUT2_zd <= d4rnk2 and AttrMode;
--###################################################################
--#####                     q1rnk2 reg                          #####
--###################################################################
  prcs_D1_rnk2:process(C_dly, GSR_dly, REV_dly, SR_dly)
  variable d1rnk2_var         : std_ulogic := TO_X01(INIT_OQ);
  variable FIRST_TIME         : boolean    := true;
  begin
     if((GSR_dly = '1') or (FIRST_TIME)) then
         d1rnk2_var  :=  TO_X01(INIT_OQ);
         FIRST_TIME  := false;
     elsif(GSR_dly = '0') then
        case AttrSRtype(1) is
           when '1' => 
           --------------- // async SET/RESET
                   if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_OQ) = '1')))) then
                      d1rnk2_var := TO_X01(SRVAL_OQ);
                   elsif(REV_dly = '1') then
                      d1rnk2_var := not TO_X01(SRVAL_OQ);
                   elsif((SR_dly = '0') and (REV_dly = '0')) then
                      if(OCE = '1') then
                         if(rising_edge(C_dly)) then
                            d1rnk2_var := data1;
                         end if;
                      elsif(OCE = '0') then
                         if(rising_edge(C_dly)) then
                            d1rnk2_var := OQ_zd;
                         end if;
                      end if;
                   end if;

           when '0' => 
           --------------- // sync SET/RESET
                   if(rising_edge(C_dly)) then
                      if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_OQ) = '1')))) then
                         d1rnk2_var := TO_X01(SRVAL_OQ);
                      elsif(REV_dly = '1') then
                         d1rnk2_var := not TO_X01(SRVAL_OQ);
                      elsif((SR_dly = '0') and (REV_dly = '0')) then
                         if(OCE = '1') then
                            d1rnk2_var := data1;
                         elsif(OCE = '0') then
                            d1rnk2_var := OQ_zd;
                         end if;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     d1rnk2  <= d1rnk2_var  after DELAY_FFD;

  end process prcs_D1_rnk2;
--###################################################################
--#####                     d2rnk2 reg                          #####
--###################################################################
  prcs_D2_rnk2:process(C2p, GSR_dly, REV_dly, SR_dly)
  variable d2rnk2_var         : std_ulogic := TO_X01(INIT_OQ);
  variable FIRST_TIME         : boolean    := true;
  begin
     if((GSR_dly = '1') or (FIRST_TIME)) then
         d2rnk2_var  :=  TO_X01(INIT_OQ);
         FIRST_TIME  := false;
     elsif(GSR_dly = '0') then
        case AttrSRtype(1) is
           when '1' => 
           --------------- // async SET/RESET
                   if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_OQ) = '1')))) then
                      d2rnk2_var :=  TO_X01(SRVAL_OQ);
                   elsif(REV_dly = '1') then
                      d2rnk2_var :=  not TO_X01(SRVAL_OQ);
                   elsif((SR_dly = '0') and (REV_dly = '0')) then
                      if(OCE = '1') then
                         if(rising_edge(C2p)) then
                            d2rnk2_var := data2;
                         end if;
                      elsif(OCE = '0') then
                         if(rising_edge(C2p)) then
                            d2rnk2_var := OQ_zd;
                         end if;
                      end if;
                   end if;

           when '0' => 
           --------------- // sync SET/RESET
                   if(rising_edge(C2p)) then
                      if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_OQ) = '1')))) then
                         d2rnk2_var :=  TO_X01(SRVAL_OQ);
                      elsif(REV_dly = '1') then
                         d2rnk2_var :=  not TO_X01(SRVAL_OQ);
                      elsif((SR_dly = '0') and (REV_dly = '0')) then
                         if(OCE = '1') then
                            d2rnk2_var := data2;
                         elsif(OCE = '0') then
                            d2rnk2_var := OQ_zd;
                         end if;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     d2rnk2  <= d2rnk2_var  after DELAY_FFD;

  end process prcs_D2_rnk2;
--###################################################################
--#####                     d2nrnk2 reg                          #####
--###################################################################
  prcs_D2_nrnk2:process(C3, GSR_dly, REV_dly, SR_dly)
  variable d2nrnk2_var         : std_ulogic := TO_X01(INIT_OQ);
  variable FIRST_TIME          : boolean    := true;
  begin
     if((GSR_dly = '1') or (FIRST_TIME)) then
         d2nrnk2_var  := TO_X01(INIT_OQ);
         FIRST_TIME  := false;
     elsif(GSR_dly = '0') then
        case AttrSRtype(1) is
           when '1' => 
           --------------- // async SET/RESET
                   if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_OQ) = '1')))) then
                      d2nrnk2_var :=  TO_X01(SRVAL_OQ);
                   elsif(REV_dly = '1') then
                      d2nrnk2_var :=  not TO_X01(SRVAL_OQ);
                   elsif((SR_dly = '0') and (REV_dly = '0')) then
                      if(OCE = '1') then
                         if(rising_edge(C3)) then
                            d2nrnk2_var := d2rnk2;
                         end if;
                      elsif(OCE = '0') then
                         if(rising_edge(C3)) then
                            d2nrnk2_var := OQ_zd;
                         end if;
                      end if;
                   end if;

           when '0' => 
           --------------- // sync SET/RESET
                   if(rising_edge(C3)) then
                      if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_OQ) = '1')))) then
                         d2nrnk2_var :=  TO_X01(SRVAL_OQ);
                      elsif(REV_dly = '1') then
                         d2nrnk2_var :=  not TO_X01(SRVAL_OQ);
                      elsif((SR_dly = '0') and (REV_dly = '0')) then
                         if(OCE = '1') then
                            d2nrnk2_var := d2rnk2;
                         elsif(OCE = '0') then
                            d2nrnk2_var := OQ_zd;
                         end if;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     d2nrnk2  <= d2nrnk2_var  after DELAY_FFD;

  end process prcs_D2_nrnk2;
--###################################################################
--#####              d3rnk2, d4rnk2, d5rnk2 and d6rnk2          #####
--###################################################################
  prcs_D3D4D5D6_rnk2:process(C_dly, GSR_dly, SR_dly)
  variable d6rnk2_var         : std_ulogic := TO_X01(INIT_ORANK2_PARTIAL(3));
  variable d5rnk2_var         : std_ulogic := TO_X01(INIT_ORANK2_PARTIAL(2));
  variable d4rnk2_var         : std_ulogic := TO_X01(INIT_ORANK2_PARTIAL(1));
  variable d3rnk2_var         : std_ulogic := TO_X01(INIT_ORANK2_PARTIAL(0));
  variable FIRST_TIME         : boolean    := true;

  begin
     if((GSR_dly = '1') or (FIRST_TIME)) then
         d6rnk2_var  := TO_X01(INIT_ORANK2_PARTIAL(3));
         d5rnk2_var  := TO_X01(INIT_ORANK2_PARTIAL(2));
         d4rnk2_var  := TO_X01(INIT_ORANK2_PARTIAL(1));
         d3rnk2_var  := TO_X01(INIT_ORANK2_PARTIAL(0));
         FIRST_TIME  := false;
     elsif(GSR_dly = '0') then
        case AttrSRtype(2) is
           when '1' => 
           --------- // async SET/RESET  -- Not full featured FFs
                   if(SR_dly = '1') then
                      d6rnk2_var  := '0';
                      d5rnk2_var  := '0';
                      d4rnk2_var  := '0';
                      d3rnk2_var  := '0';
                   elsif(SR_dly = '0') then
                      if(rising_edge(C_dly)) then
                         d6rnk2_var  := data6;
                         d5rnk2_var  := data5;
                         d4rnk2_var  := data4;
                         d3rnk2_var  := data3;
                      end if;
                   end if;

           when '0' => 
           --------- // sync SET/RESET  -- Not full featured FFs
                   if(rising_edge(C_dly)) then
                      if(SR_dly = '1') then
                         d6rnk2_var  := '0';
                         d5rnk2_var  := '0';
                         d4rnk2_var  := '0';
                         d3rnk2_var  := '0';
                      elsif(SR_dly = '0') then
                         d6rnk2_var  := data6;
                         d5rnk2_var  := data5;
                         d4rnk2_var  := data4;
                         d3rnk2_var  := data3;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     d6rnk2  <= d6rnk2_var  after DELAY_FFD;
     d5rnk2  <= d5rnk2_var  after DELAY_FFD;
     d4rnk2  <= d4rnk2_var  after DELAY_FFD;
     d3rnk2  <= d3rnk2_var  after DELAY_FFD;

  end process prcs_D3D4D5D6_rnk2;

--//////////////////////////////////////////////////////////////////
--//                   First rank of FF for input data            //
--//////////////////////////////////////////////////////////////////

--###################################################################
--#####              d1r, d2r, d3r, d4r, d5r and d6r            #####
--###################################################################
  prcs_D1D2D3D4D5D6_r:process(CLKDIV_dly, GSR_dly, SR_dly)
  variable d6r_var            : std_ulogic := TO_X01(INIT_ORANK1(5));
  variable d5r_var            : std_ulogic := TO_X01(INIT_ORANK1(4));
  variable d4r_var            : std_ulogic := TO_X01(INIT_ORANK1(3));
  variable d3r_var            : std_ulogic := TO_X01(INIT_ORANK1(2));
  variable d2r_var            : std_ulogic := TO_X01(INIT_ORANK1(1));
  variable d1r_var            : std_ulogic := TO_X01(INIT_ORANK1(0));
  variable FIRST_TIME         : boolean    := true;

  begin
     if((GSR_dly = '1') or (FIRST_TIME)) then
         d6r_var     := TO_X01(INIT_ORANK1(5));
         d5r_var     := TO_X01(INIT_ORANK1(4));
         d4r_var     := TO_X01(INIT_ORANK1(3));
         d3r_var     := TO_X01(INIT_ORANK1(2));
         d2r_var     := TO_X01(INIT_ORANK1(1));
         d1r_var     := TO_X01(INIT_ORANK1(0));
         FIRST_TIME  := false;
     elsif(GSR_dly = '0') then
        case AttrSRtype(3) is
           when '1' => 
           --------- // async SET/RESET  -- Not full featured FFs
                   if(SR_dly = '1') then
                      d6r_var  := '0';
                      d5r_var  := '0';
                      d4r_var  := '0';
                      d3r_var  := '0';
                      d2r_var  := '0';
                      d1r_var  := '0';
                   elsif(SR_dly = '0') then
                      if(rising_edge(CLKDIV_dly)) then
                         d6r_var  := D6_dly;
                         d5r_var  := D5_dly;
                         d4r_var  := D4_dly;
                         d3r_var  := D3_dly;
                         d2r_var  := D2_dly;
                         d1r_var  := D1_dly;
                      end if;
                   end if;

           when '0' => 
           --------- // sync SET/RESET  -- Not full featured FFs
                   if(rising_edge(CLKDIV_dly)) then
                      if(SR_dly = '1') then
                         d6r_var  := '0';
                         d5r_var  := '0';
                         d4r_var  := '0';
                         d3r_var  := '0';
                         d2r_var  := '0';
                         d1r_var  := '0';
                      elsif(SR_dly = '0') then
                         d6r_var  := D6_dly;
                         d5r_var  := D5_dly;
                         d4r_var  := D4_dly;
                         d3r_var  := D3_dly;
                         d2r_var  := D2_dly;
                         d1r_var  := D1_dly;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     d6r  <= d6r_var  after DELAY_FFCD;
     d5r  <= d5r_var  after DELAY_FFCD;
     d4r  <= d4r_var  after DELAY_FFCD;
     d3r  <= d3r_var  after DELAY_FFCD;
     d2r  <= d2r_var  after DELAY_FFCD;
     d1r  <= d1r_var  after DELAY_FFCD;

  end process prcs_D1D2D3D4D5D6_r;

--###################################################################
--#####                Muxes for 2nd rank of FFS                #####
--###################################################################
  prcs_data1234_mux:process(sel1_4, d1r, d2r, d3r, d4r, d2rnk2,
                                d3rnk2, d4rnk2, d5rnk2, d6rnk2)

  begin
     case sel1_4 is
           when "100" =>
                    data1 <= d3rnk2 after DELAY_MXR1;
                    data2 <= d4rnk2 after DELAY_MXR1;
                    data3 <= d5rnk2 after DELAY_MXR1;
                    data4 <= d6rnk2 after DELAY_MXR1;
           when "110" =>
                    data1 <= d1r    after DELAY_MXR1;
                    data2 <= d2r    after DELAY_MXR1;
                    data3 <= d3r    after DELAY_MXR1;
                    data4 <= d4r    after DELAY_MXR1;
           when "101" =>
                    data1 <= d2rnk2 after DELAY_MXR1;
                    data2 <= d3rnk2 after DELAY_MXR1;
                    data3 <= d4rnk2 after DELAY_MXR1;
                    data4 <= d5rnk2 after DELAY_MXR1;
           when "111" =>
                    data1 <= d1r    after DELAY_MXR1;
                    data2 <= d2r    after DELAY_MXR1;
                    data3 <= d3r    after DELAY_MXR1;
                    data4 <= d4r    after DELAY_MXR1;
           when others =>
                    data1 <= d3rnk2 after DELAY_MXR1;
                    data2 <= d4rnk2 after DELAY_MXR1;
                    data3 <= d5rnk2 after DELAY_MXR1;
                    data4 <= d6rnk2 after DELAY_MXR1;
     end case;

  end process prcs_data1234_mux;

----------------------------------------------------------------------

  prcs_data56_mux:process(sel5_6, d5r, d6r, d6rnk2, SHIFTIN1_dly,
                                                    SHIFTIN2_dly )

  begin
     case sel5_6 is
           when "1000" =>
                    data5 <=  SHIFTIN1_dly after DELAY_MXR1;
                    data6 <=  SHIFTIN2_dly after DELAY_MXR1;
           when "1010" =>
                    data5 <=  d5r after DELAY_MXR1;
                    data6 <=  d6r after DELAY_MXR1;
           when "1001" =>
                    data5 <=  d6rnk2 after DELAY_MXR1;
                    data6 <=  SHIFTIN1_dly after DELAY_MXR1;
           when "1011" =>
                    data5 <=  d5r after DELAY_MXR1;
                    data6 <=  d6r after DELAY_MXR1;
           when "1100" =>
                    data5 <=  '0' after DELAY_MXR1;
                    data6 <=  '0' after DELAY_MXR1;
           when "1110" =>
                    data5 <=  d5r after DELAY_MXR1;
                    data6 <=  d6r after DELAY_MXR1;
           when "1101" =>
                    data5 <=  d6rnk2 after DELAY_MXR1;
                    data6 <=  '0' after DELAY_MXR1;
           when "1111" =>
                    data5 <=  d5r after DELAY_MXR1;
                    data6 <=  d6r after DELAY_MXR1;

           when others =>
                    data5 <=  SHIFTIN1_dly after DELAY_MXR1;
                    data6 <=  SHIFTIN2_dly after DELAY_MXR1;
     end case;

  end process prcs_data56_mux;
--###################################################################
--#####        sdata_edge                                      ######
--###################################################################
  prcs_sdata:process(C_dly, C3, d1rnk2, d2nrnk2)
  begin
     sdata_edge <= ((d1rnk2 and C_dly) or (d2nrnk2 and C3)) after DELAY_MXD;
  end process prcs_sdata;

--###################################################################
--#####             odata_edge                                  #####
--###################################################################
  prcs_odata:process(C_dly, d1rnk2, d2rnk2)
  begin
     case C_dly is
           when '0' => 
                    odata_edge <= d2rnk2 after DELAY_MXD;
           when '1' => 
                    odata_edge <= d1rnk2 after DELAY_MXD;
           when others =>
                    odata_edge <= d2rnk2 after DELAY_MXD;
     end case;
  end process prcs_odata;
--###################################################################
--#####                 ddr_data                               ######
--###################################################################
  prcs_ddrdata:process(ddr_data, sdata_edge, odata_edge, AttrDdrClkEdge)
  begin
     ddr_data <= ((odata_edge and (not AttrDdrClkEdge)) or 
                    (sdata_edge and AttrDdrClkEdge)) after DELAY_MXD;
  end process prcs_ddrdata;

---////////////////////////////////////////////////////////////////////
---                       Outputs
---////////////////////////////////////////////////////////////////////
  prcs_OQ_mux:process(seloq, d1rnk2, ddr_data, OQ_zd, GSR_dly)

  variable FIRST_TIME : boolean := true;

  begin
     if((GSR_dly = '1') or (FIRST_TIME)) then
       OQ_zd    <=  TO_X01(INIT_OQ);
       FIRST_TIME := false;
     elsif(GSR_dly = '0') then
        case seloq is
           when "0001" | "0101"| "1001" | "1101" |
                "0X01" | "1X01"| "XX01" | "X001" |
                "X101" 
                       => 
                       OQ_zd <= '1' after DELAY_MXD;

           when "0010" | "0110"| "1010" | "1110" |
                "0X10" | "1X10"| "XX10" | "X010" |
                "X110" 
                       => 
                       OQ_zd <= '0' after DELAY_MXD;
   
           when "0011" | "0111"| "1011" | "1111" |
                "0X11" | "1X11"| "XX11" | "X011" |
                "X111" 
                       => 
                       OQ_zd <= '0' after DELAY_MXD;
   
           when "0000" =>
                       OQ_zd <= OQ_zd after DELAY_MXD;
   
           when "0100" =>
                       OQ_zd <= OQ_zd after DELAY_MXD;
   
           when "1000" =>
                       OQ_zd <= ddr_data after DELAY_MXD;
   
           when "1100" =>
                       OQ_zd <= d1rnk2 after DELAY_MXD;
   
           when others =>
-- CR 192533 the below "now > DEALY_MXD" is added since 
-- the INIT value of OQ_zd is getting wiped off by ddr_data=X at time 0.
-- At time 0, seloq is XXXX
                       if(now > DELAY_MXD) then
                         OQ_zd <= ddr_data after DELAY_MXD;
                       end if;
   
        end case;

     end if; 

  end process prcs_OQ_mux;
----------------------------------------------------------------------
-----------    Instant PLG  --------------------------------------
----------------------------------------------------------------------
  INST_PLG : PLG
  generic map (
      SRTYPE => SRTYPE,
      INIT_LOADCNT => INIT_LOADCNT
     )
  port map (
      LOAD       => loadint,

      C23        => c23,
      C45        => c45,
      C67        => c67,
      CLK        => C_dly,
      CLKDIV     => CLKDIV_dly,
      RST        => SR_dly,
      SEL        => sel
      );

--###################################################################
--#####           Set value of the counter in PLG             ##### 
--###################################################################
  prcs_plg_plgcnt:process
  begin
     wait for 10 ps;
     case plgcnt is
        when "00100" =>
                 c23<='0'; c45<='0'; c67<='0'; sel<="00";
        when "00110" =>
                 c23<='1'; c45<='0'; c67<='0'; sel<="00";
        when "01000" =>
                 c23<='0'; c45<='0'; c67<='0'; sel<="01";
        when "01010" =>
                 c23<='0'; c45<='1'; c67<='0'; sel<="01";
        when "10010" =>
                 c23<='0'; c45<='0'; c67<='0'; sel<="00";
        when "10011" =>
                 c23<='1'; c45<='0'; c67<='0'; sel<="00";
        when "10100" =>
                 c23<='0'; c45<='0'; c67<='0'; sel<="01";
        when "10101" =>
                 c23<='0'; c45<='1'; c67<='0'; sel<="01";
        when "10110" =>
                 c23<='0'; c45<='0'; c67<='0'; sel<="10";
        when "10111" =>
                 c23<='0'; c45<='0'; c67<='1'; sel<="10";
        when "11000" =>
                 c23<='0'; c45<='0'; c67<='0'; sel<="11";
        when others =>
                assert FALSE 
                report "WARNING : DATA_WIDTH or DATA_RATE has illegal values."
                severity Warning;
     end case;
    wait;
  end process prcs_plg_plgcnt;
         

--####################################################################

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(OQ_zd, LOAD_zd, SHIFTOUT1_zd, SHIFTOUT2_zd)
  begin
      OQ   <= OQ_zd;
      LOAD <= LOAD_zd;
      SHIFTOUT1 <= SHIFTOUT1_zd;
      SHIFTOUT2 <= SHIFTOUT2_zd;
  end process prcs_output;
--####################################################################


end IOOUT_V;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;


library unisim;
use unisim.vpkg.all;

entity IOT is

  generic(

         DATA_RATE_TQ		: string;
         TRISTATE_WIDTH		: integer	:= 1;
         DDR_CLK_EDGE		: string	:= "SAME_EDGE";
         INIT_TQ		: bit		:= '0';
         INIT_TRANK1		: bit_vector(3 downto 0) := "0000";
         SRVAL_TQ		: bit		:= '1';

         SRTYPE			: string	:= "ASYNC"
    );

  port(
      TQ		: out std_ulogic;

      C			: in std_ulogic;
      CLKDIV		: in std_ulogic;
      LOAD		: in std_ulogic;
      REV	        : in std_ulogic;
      SR	        : in std_ulogic;
      T1		: in std_ulogic;
      T2		: in std_ulogic;
      T3		: in std_ulogic;
      T4		: in std_ulogic;
      TCE		: in std_ulogic
    );

end IOT;

architecture IOT_V OF IOT is


  constant GSR_PULSE_TIME       : time       := 1 ns; 

  constant DELAY_FFD            : time       := 1 ps; 
  constant DELAY_MXD	        : time       := 1  ps;
  constant DELAY_ZERO	        : time       := 0  ps;
  constant DELAY_ONE	        : time       := 1  ps;
  constant SWALLOW_PULSE	: time       := 2  ps;

  constant MAX_DATAWIDTH	: integer    := 4;

  signal C_ipd			: std_ulogic := 'X';
  signal CLKDIV_ipd		: std_ulogic := 'X';
  signal GSR            : std_ulogic := '0';
  signal GSR_ipd		: std_ulogic := 'X';
  signal LOAD_ipd		: std_ulogic := 'X';
  signal T1_ipd			: std_ulogic := 'X';
  signal T2_ipd			: std_ulogic := 'X';
  signal T3_ipd			: std_ulogic := 'X';
  signal T4_ipd			: std_ulogic := 'X';
  signal TCE_ipd	        : std_ulogic := 'X';
  signal REV_ipd	        : std_ulogic := 'X';
  signal SR_ipd		        : std_ulogic := 'X';

  signal C_dly			: std_ulogic := 'X';
  signal CLKDIV_dly		: std_ulogic := 'X';
  signal GSR_dly		: std_ulogic := 'X';
  signal LOAD_dly		: std_ulogic := 'X';
  signal T1_dly			: std_ulogic := 'X';
  signal T2_dly			: std_ulogic := 'X';
  signal T3_dly			: std_ulogic := 'X';
  signal T4_dly			: std_ulogic := 'X';
  signal TCE_dly	        : std_ulogic := 'X';
  signal REV_dly	        : std_ulogic := 'X';
  signal SR_dly		        : std_ulogic := 'X';

  signal TQ_zd			: std_ulogic := TO_X01(INIT_TQ);

  signal AttrDataRateTQ		: std_logic_vector(1 downto 0) := (others => 'X');
  signal AttrTriStateWidth	: std_logic_vector(1 downto 0) := (others => 'X');
  signal AttrDdrClkEdge		: std_ulogic := 'X';

  signal AttrSRtype		: std_logic_vector(1 downto 0) := (others => '1');

  signal t1r			: std_ulogic := 'X';
  signal t2r			: std_ulogic := 'X';
  signal t3r			: std_ulogic := 'X';
  signal t4r			: std_ulogic := 'X';

  signal qt1			: std_ulogic := 'X';
  signal qt2			: std_ulogic := 'X';
  signal qt2n			: std_ulogic := 'X';

  signal data1			: std_ulogic := 'X';
  signal data2			: std_ulogic := 'X';

  signal sdata_edge		: std_ulogic := 'X';
  signal odata_edge		: std_ulogic := 'X';
  signal ddr_data		: std_ulogic := 'X';

  signal C2p			: std_ulogic := 'X';
  signal C3			: std_ulogic := 'X';

  signal tqsel			: std_logic_vector(6 downto 0) := (others => 'X');
  signal tqsr			: std_ulogic := 'X';
  signal tqrev			: std_ulogic := 'X';

  signal sel			: std_logic_vector(4 downto 0) := (others => 'X');

begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  C_dly          	 <= C              	after 0 ps;
  CLKDIV_dly     	 <= CLKDIV         	after 0 ps;
  GSR_dly        	 <= GSR            	after 0 ps;
  LOAD_dly       	 <= LOAD           	after 0 ps;
  REV_dly        	 <= REV            	after 0 ps;
  SR_dly         	 <= SR             	after 0 ps;
  T1_dly         	 <= T1             	after 0 ps;
  T2_dly         	 <= T2             	after 0 ps;
  T3_dly         	 <= T3             	after 0 ps;
  T4_dly         	 <= T4             	after 0 ps;
  TCE_dly        	 <= TCE            	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process
  variable AttrDataRateTQ_var		: std_logic_vector(1 downto 0) := (others => 'X');
  variable AttrTriStateWidth_var	: std_logic_vector(1 downto 0) := (others => 'X');
  variable AttrDdrClkEdge_var		: std_ulogic := 'X';

  begin

      ------------------ DATA_RATE_TQ validity check ------------------
-- FP check with Paul
      if((DATA_RATE_TQ = "BUF") or (DATA_RATE_TQ = "buf")) then
         AttrDataRateTQ_var := "00";
      elsif((DATA_RATE_TQ = "SDR") or (DATA_RATE_TQ = "sdr")) then
         AttrDataRateTQ_var := "01";
      elsif((DATA_RATE_TQ = "DDR") or (DATA_RATE_TQ = "ddr")) then
         AttrDataRateTQ_var := "10";
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " DATA_RATE_TQ ",
             EntityName => "/X_IOOUT",
             GenericValue => DATA_RATE_TQ,
             Unit => "",
             ExpectedValueMsg => " The legal values for this attribute are ",
             ExpectedGenericValue => " BUF, SDR or DDR. ",
             TailMsg => "",
             MsgSeverity => Failure
         );
      end if;


      ------------------ TRISTATE_WIDTH validity check ------------------
      if((TRISTATE_WIDTH = 1) or (TRISTATE_WIDTH = 2) or  (TRISTATE_WIDTH = 4)) then
         case TRISTATE_WIDTH is
            when   1  =>  AttrTriStateWidth_var := "00";
            when   2  =>  AttrTriStateWidth_var := "01";
            when   4  =>  AttrTriStateWidth_var := "10";
            when others  =>
                   null;
         end case;
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " TRISTATE_WIDTH ",
             EntityName => "/IOT",
             GenericValue => TRISTATE_WIDTH,
             Unit => "",
             ExpectedValueMsg => " The legal values for this attribute are ",
             ExpectedGenericValue => " 1, 2 or 4 ",
             TailMsg => "",
             MsgSeverity => Failure
         );
      end if;

      ------------ TRISTATE_WIDTH /DATA_RATE combination check ------------
-- CR 458156 -- enabled TRISTATE_WIDTH to be 1 in DDR mode.
      if((DATA_RATE_TQ = "DDR") or (DATA_RATE_TQ = "ddr")) then
         case (TRISTATE_WIDTH) is
             when 1|2|4  => null;
             when others       =>
                GenericValueCheckMessage
                (  HeaderMsg  => " Attribute Syntax Warning ",
                   GenericName => " TRISTATE_WIDTH ",
                   EntityName => "/IOT",
                   GenericValue => TRISTATE_WIDTH,
                   Unit => "",
                   ExpectedValueMsg => " The legal values for this attribute in DDR mode are ",
                   ExpectedGenericValue => "1, 2 or 4",
                   TailMsg => "",
                   MsgSeverity => Failure
                );
          end case;
      end if;

      if((DATA_RATE_TQ = "SDR") or (DATA_RATE_TQ = "sdr")) then
         case (TRISTATE_WIDTH) is
             when 1  => null;
             when others       =>
                GenericValueCheckMessage
                (  HeaderMsg  => " Attribute Syntax Warning ",
                   GenericName => " TRISTATE_WIDTH ",
                   EntityName => "/IOT",
                   GenericValue => TRISTATE_WIDTH,
                   Unit => "",
                   ExpectedValueMsg => " The legal value for this attribute in SDR mode is",
                   ExpectedGenericValue => " 1. ",
                   TailMsg => "",
                   MsgSeverity => Failure
                );
          end case;
      end if;

      if((DATA_RATE_TQ = "BUF") or (DATA_RATE_TQ = "buf")) then
         case (TRISTATE_WIDTH) is
             when 1  => null;
             when others       =>
                GenericValueCheckMessage
                (  HeaderMsg  => " Attribute Syntax Warning ",
                   GenericName => " TRISTATE_WIDTH ",
                   EntityName => "/IOT",
                   GenericValue => TRISTATE_WIDTH,
                   Unit => "",
                   ExpectedValueMsg => " The legal value for this attribute in BUF mode is",
                   ExpectedGenericValue => " 1. ",
                   TailMsg => "",
                   MsgSeverity => Failure
                );
          end case;
      end if;

      ------------------ DDR_CLK_EDGE validity check ------------------

      if((DDR_CLK_EDGE = "SAME_EDGE") or (DDR_CLK_EDGE = "same_edge")) then
         AttrDdrClkEdge_var := '1';
      elsif((DDR_CLK_EDGE = "OPPOSITE_EDGE") or (DDR_CLK_EDGE = "opposite_edge")) then
         AttrDdrClkEdge_var := '0';
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " DDR_CLK_EDGE ",
             EntityName => "/IOT",
             GenericValue => DDR_CLK_EDGE,
             Unit => "",
             ExpectedValueMsg => " The legal values for this attribute are ",
             ExpectedGenericValue => " SAME_EDGE or OPPOSITE_EDGE ",
             TailMsg => "",
             MsgSeverity => Failure
         );
      end if;
      ------------------ DATA_RATE validity check ------------------
      if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
         AttrSRtype  <= (others => '1');
      elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
         AttrSRtype  <= (others => '0');
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " SRTYPE ",
             EntityName => "/IOT",
             GenericValue => SRTYPE,
             Unit => "",
             ExpectedValueMsg => " The legal values for this attribute are ",
             ExpectedGenericValue => " ASYNC or SYNC. ",
             TailMsg => "",
             MsgSeverity => ERROR
         );
      end if;
---------------------------------------------------------------------
     AttrDataRateTQ	<= AttrDataRateTQ_var;
     AttrTriStateWidth	<= AttrTriStateWidth_var;
     AttrDdrClkEdge	<= AttrDdrClkEdge_var;
     wait;
  end process prcs_init;
--###################################################################
--#####                   Concurrent exe                        #####
--###################################################################
   C2p    <= (C_dly and AttrDdrClkEdge) or 
             ((not C_dly) and (not AttrDdrClkEdge)); 
   C3     <= not C2p;

   tqsel  <= TCE & AttrDataRateTQ & AttrTriStateWidth & tqsr & tqrev;

   sel    <= load &  AttrDataRateTQ & AttrTriStateWidth;

   tqsr    <= ((AttrSRtype(1) and SR_dly and not (TO_X01(SRVAL_TQ)))
                               or
                (AttrSRtype(1) and REV_dly and (TO_X01(SRVAL_TQ))));

   tqrev   <= ((AttrSRtype(1) and SR_dly and (TO_X01(SRVAL_TQ)))
                               or
                (AttrSRtype(1) and REV_dly and not (TO_X01(SRVAL_TQ))));

--###################################################################
--#####                        qt1 reg                          #####
--###################################################################
  prcs_qt1_reg:process(C_dly, GSR_dly, REV_dly, SR_dly)
  variable qt1_var    : std_ulogic := TO_X01(INIT_TQ);
  variable FIRST_TIME : boolean    := true;
  begin
     if((GSR_dly = '1') or (FIRST_TIME)) then
         qt1_var    :=  TO_X01(INIT_TQ);
         FIRST_TIME := false;
     elsif(GSR_dly = '0') then
        case AttrSRtype(1) is
           when '1' => 
           --------------- // async SET/RESET
                   if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_TQ) = '1')))) then
                      qt1_var  :=  TO_X01(SRVAL_TQ);
                   elsif(REV_dly = '1') then
                      qt1_var  :=  not TO_X01(SRVAL_TQ);
                   elsif((SR_dly = '0') and (REV_dly = '0')) then
                      if(TCE_dly = '1') then
                         if(rising_edge(C_dly)) then
                            qt1_var := data1;
                         end if;
                      end if;
                   end if;

           when '0' => 
           --------------- // sync SET/RESET
                   if(rising_edge(C_dly)) then
                      if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_TQ) = '1')))) then
                         qt1_var  :=  TO_X01(SRVAL_TQ);
                      elsif(REV_dly = '1') then
                         qt1_var  :=  not TO_X01(SRVAL_TQ);
                      elsif((SR_dly = '0') and (REV_dly = '0')) then
                         if(TCE_dly = '1') then
                            qt1_var := data1;
                         end if;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     qt1  <= qt1_var  after DELAY_FFD;

  end process prcs_qt1_reg;
--###################################################################
--#####                        qt2 reg                          #####
--###################################################################
  prcs_qt2_reg:process(C2p, GSR_dly, REV_dly, SR_dly)
  variable qt2_var    : std_ulogic := TO_X01(INIT_TQ);
  variable FIRST_TIME : boolean    := true;
  begin
     if((GSR_dly = '1') or (FIRST_TIME)) then
         qt2_var    :=  TO_X01(INIT_TQ);
         FIRST_TIME := false;
     elsif(GSR_dly = '0') then
        case AttrSRtype(1) is
           when '1' => 
           --------------- // async SET/RESET
                   if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_TQ) = '1')))) then
                      qt2_var  :=  TO_X01(SRVAL_TQ);
                   elsif(REV_dly = '1') then
                      qt2_var  :=  not TO_X01(SRVAL_TQ);
                   elsif((SR_dly = '0') and (REV_dly = '0')) then
                      if(TCE_dly = '1') then
                         if(rising_edge(C2p)) then
                            qt2_var := data2;
                         end if;
                      end if;
                   end if;

           when '0' => 
           --------------- // sync SET/RESET
                   if(rising_edge(C2p)) then
                      if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_TQ) = '1')))) then
                         qt2_var  :=  TO_X01(SRVAL_TQ);
                      elsif(REV_dly = '1') then
                         qt2_var  :=  not TO_X01(SRVAL_TQ);
                      elsif((SR_dly = '0') and (REV_dly = '0')) then
                         if(TCE_dly = '1') then
                            qt2_var := data2;
                         end if;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     qt2  <= qt2_var  after DELAY_FFD;

  end process prcs_qt2_reg;

--###################################################################
--#####                        qt2n reg                          #####
--###################################################################
  prcs_qt2n_reg:process(C3, GSR_dly, REV_dly, SR_dly)
  variable qt2n_var   : std_ulogic := TO_X01(INIT_TQ);
  variable FIRST_TIME : boolean    := true;
  begin
     if((GSR_dly = '1') or (FIRST_TIME)) then
         qt2n_var    :=  TO_X01(INIT_TQ);
         FIRST_TIME := false;
     elsif(GSR_dly = '0') then
        case AttrSRtype(1) is
           when '1' => 
           --------------- // async SET/RESET
                   if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_TQ) = '1')))) then
                      qt2n_var  :=  TO_X01(SRVAL_TQ);
                   elsif(REV_dly = '1') then
                      qt2n_var  :=  not TO_X01(SRVAL_TQ);
                   elsif((SR_dly = '0') and (REV_dly = '0')) then
                      if(TCE_dly = '1') then
                         if(rising_edge(C3)) then
                            qt2n_var := qt2;
                         end if;
                      end if;
                   end if;

           when '0' => 
           --------------- // sync SET/RESET
                   if(rising_edge(C3)) then
                      if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_TQ) = '1')))) then
                         qt2n_var  :=  TO_X01(SRVAL_TQ);
                      elsif(REV_dly = '1') then
                         qt2n_var  :=  not TO_X01(SRVAL_TQ);
                      elsif((SR_dly = '0') and (REV_dly = '0')) then
                         if(TCE_dly = '1') then
                            qt2n_var := qt2;
                         end if;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     qt2n  <= qt2n_var  after DELAY_FFD;

  end process prcs_qt2n_reg;

--###################################################################
--#####               t1r, t2r, t3r and tr4                     #####
--###################################################################
  prcs_t1rt2rt3rt4r_rnk1:process(CLKDIV_dly, GSR_dly, SR_dly)
  variable t1r_var    : std_ulogic := TO_X01(INIT_TRANK1(0));
  variable t2r_var    : std_ulogic := TO_X01(INIT_TRANK1(1));
  variable t3r_var    : std_ulogic := TO_X01(INIT_TRANK1(2));
  variable t4r_var    : std_ulogic := TO_X01(INIT_TRANK1(3));
  variable FIRST_TIME : boolean    := true;

  begin
     if((GSR_dly = '1') or (FIRST_TIME)) then
         t1r_var    := TO_X01(INIT_TRANK1(0));
         t2r_var    := TO_X01(INIT_TRANK1(1));
         t3r_var    := TO_X01(INIT_TRANK1(2));
         t4r_var    := TO_X01(INIT_TRANK1(3));
         FIRST_TIME := false;
     elsif(GSR_dly = '0') then
        case AttrSRtype(1) is
           when '1' => 
           --------- // async SET/RESET  -- Not full featured FFs
                   if(SR_dly = '1') then
                      t1r_var  := '0';
                      t2r_var  := '0';
                      t3r_var  := '0';
                      t4r_var  := '0';
                   elsif(SR_dly = '0') then
                      if(rising_edge(CLKDIV_dly)) then
                         t1r_var  := T1_dly;
                         t2r_var  := T2_dly;
                         t3r_var  := T3_dly;
                         t4r_var  := T4_dly;
                      end if;
                   end if;

           when '0' => 
           --------- // sync SET/RESET  -- Not full featured FFs
                   if(rising_edge(C_dly)) then
                      if(SR_dly = '1') then
                         t1r_var  := '0';
                         t2r_var  := '0';
                         t3r_var  := '0';
                         t4r_var  := '0';
                      elsif(SR_dly = '0') then
                         t1r_var  := T1_dly;
                         t2r_var  := T2_dly;
                         t3r_var  := T3_dly;
                         t4r_var  := T4_dly;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     t1r  <= t1r_var  after DELAY_FFD;
     t2r  <= t2r_var  after DELAY_FFD;
     t3r  <= t3r_var  after DELAY_FFD;
     t4r  <= t4r_var  after DELAY_FFD;

  end process prcs_t1rt2rt3rt4r_rnk1;

--###################################################################
--#####                Muxes for tristate outputs               ##### 
--###################################################################
  prcs_data1_mux:process(sel, T1_dly, t1r, t3r)
  begin
    if (now > GSR_PULSE_TIME) then
       case sel is
          when "00000" | "10000" | "X0000" |
               "00100" | "10100" | "X0100" |
               "01001" | "11001" =>
                   data1 <= T1_dly after DELAY_MXD;
          when "01010" =>
                   data1 <= t3r after DELAY_MXD;
          when "11010" =>
                   data1 <= t1r after DELAY_MXD;
-- CR 458156 -- allow/enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings,
          when "01000" | "11000" | "X1000" => 
          when others =>
                  assert FALSE 
                  report "WARNING : DATA_RATE_TQ and/or  TRISTATE_WIDTH have illegal values."
                  severity Warning;
       end case;
    end if;
  end process prcs_data1_mux;
---------------------------------------------------------------
  prcs_data2_mux:process(sel, T2_dly, t2r, t4r)
  begin
    if (now > GSR_PULSE_TIME) then
       case sel is
          when "00000" | "00100" | "10000" |
               "10100" | "X0000" | "X0100" |
               "00X00" | "10X00" | "X0X00" |
               "01001" | "11001"  | "X1001"  =>
                   data2 <= T2_dly after DELAY_MXD;
          when "01010" =>
                   data2 <= t4r after DELAY_MXD;
          when "11010" =>
                   data2 <= t2r after DELAY_MXD;
-- CR 458156 -- allow/enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings,
          when "01000" | "11000" | "X1000" => 
          when others =>
                  assert FALSE 
                  report "WARNING : DATA_RATE_TQ and/or  TRISTATE_WIDTH have illegal values."
                  severity Warning;
       end case;
    end if;
  end process prcs_data2_mux;

--###################################################################
--#####        sdata_edge                                      ######
--###################################################################
  prcs_sdata:process(C_dly, C3, qt1, qt2n)
  begin
     sdata_edge <= ((qt1 and C_dly) or (qt2n and C3)) after DELAY_MXD;
  end process prcs_sdata;

--###################################################################
--#####             odata_edge                                  #####
--###################################################################
  prcs_odata:process(C_dly, qt1, qt2)
  begin
     case C_dly is
           when '0' => 
                    odata_edge <= qt2 after DELAY_MXD;
           when '1' => 
                    odata_edge <= qt1 after DELAY_MXD;
           when others =>
                    odata_edge <= '0' after DELAY_ZERO;
     end case;
  end process prcs_odata;
--###################################################################
--#####                 ddr_data                               ######
--###################################################################
  prcs_ddrdata:process(ddr_data, sdata_edge, odata_edge, AttrDdrClkEdge)
  begin
     ddr_data <= ((odata_edge and (not AttrDdrClkEdge)) or 
                    (sdata_edge and AttrDdrClkEdge)) after DELAY_ONE;
  end process prcs_ddrdata;

---////////////////////////////////////////////////////////////////////
---                       Outputs
---////////////////////////////////////////////////////////////////////
  prcs_TQ_mux:process(tqsel, data1, ddr_data, qt1, GSR_dly)

  variable FIRST_TIME : boolean := true;

  begin
     if((GSR_dly = '1') or (FIRST_TIME)) then
       TQ_zd    <=  TO_X01(INIT_TQ);
       FIRST_TIME := false;
     elsif(GSR_dly = '0') then
        if((tqsel(5 downto 4) = "01") and (tqsel(1 downto 0) = "01")) then
           TQ_zd <= '1' after DELAY_ONE;
        elsif((tqsel(5 downto 4) = "10") and (tqsel(1 downto 0) = "01")) then
           TQ_zd <= '1' after DELAY_ONE;
        elsif((tqsel(5 downto 4) = "01") and (tqsel(1 downto 0) = "10")) then
           TQ_zd <= '0' after DELAY_ONE;
        elsif((tqsel(5 downto 4) = "10") and (tqsel(1 downto 0) = "10")) then
           TQ_zd <= '0' after DELAY_ONE;
        elsif((tqsel(5 downto 4) = "01") and (tqsel(1 downto 0) = "11")) then
           TQ_zd <= '0' after DELAY_ONE;
        elsif((tqsel(5 downto 4) = "10") and (tqsel(1 downto 0) = "11")) then
           TQ_zd <= '0' after DELAY_ONE;
        elsif(tqsel(5 downto 2) = "0000") then
           TQ_zd <= data1 after DELAY_ONE;
        else

           case tqsel is
--              when "-01--01" | "-10--01" =>
--                    TQ_zd <= '1' after DELAY_ONE;
--              when "-01--10" | "-10--10" | "-01--11" | "-10--11" =>
--                    TQ_zd <= '0' after DELAY_ONE;
--              when "-----11" =>
--                    TQ_zd <= '0' after DELAY_ONE;
--              when "-0000--" =>
--                    TQ_zd <= data1 after DELAY_ONE;
              when "0010000" |  "0100100" |  "0101000" =>
                    TQ_zd <= TQ_zd after DELAY_ONE;
              when "1010000" =>
                    TQ_zd <= qt1 after DELAY_ONE;
              when "1100100" | "1101000" =>
                    TQ_zd <= ddr_data after DELAY_ONE;
              when others =>
                    TQ_zd <= ddr_data after DELAY_ONE;
           end case;
        end if;
     end if;
  end process prcs_TQ_mux;
--####################################################################

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(TQ_zd, GSR_dly)
  variable FIRST_TIME : boolean := true;
  begin
         TQ <= TQ_zd after SWALLOW_PULSE;
  end process prcs_output;
--####################################################################


end IOT_V;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;


library unisim;
use unisim.vpkg.all;

----- CELL OSERDES -----
-- //////////////////////////////////////////////////////////// 
-- //////////////////////// OSERDES /////////////////////////
-- //////////////////////////////////////////////////////////// 

entity OSERDES is

  generic(

      DDR_CLK_EDGE		: string	:= "SAME_EDGE";
      INIT_LOADCNT		: bit_vector(3 downto 0) := "0000";
      INIT_ORANK1		: bit_vector(5 downto 0) := "000000";
      INIT_ORANK2_PARTIAL	: bit_vector(3 downto 0) := "0000";
      INIT_TRANK1		: bit_vector(3 downto 0) := "0000";
      SERDES			: boolean	:= TRUE;
      SRTYPE			: string	:= "ASYNC";

      DATA_RATE_OQ	: string	:= "DDR";
      DATA_RATE_TQ	: string	:= "DDR";
      DATA_WIDTH	: integer	:= 4;
      INIT_OQ		: bit		:= '0';
      INIT_TQ		: bit		:= '0';
      SERDES_MODE	: string	:= "MASTER";
      SRVAL_OQ		: bit		:= '0';
      SRVAL_TQ		: bit		:= '0';
      TRISTATE_WIDTH	: integer	:= 4
      );


  port(
      OQ		: out std_ulogic;
      SHIFTOUT1		: out std_ulogic;
      SHIFTOUT2		: out std_ulogic;
      TQ		: out std_ulogic;

      CLK		: in std_ulogic;
      CLKDIV		: in std_ulogic;
      D1		: in std_ulogic;
      D2		: in std_ulogic;
      D3		: in std_ulogic;
      D4		: in std_ulogic;
      D5		: in std_ulogic;
      D6		: in std_ulogic;
      OCE		: in std_ulogic;
      REV	        : in std_ulogic;
      SHIFTIN1		: in std_ulogic;
      SHIFTIN2		: in std_ulogic;
      SR	        : in std_ulogic;
      T1		: in std_ulogic;
      T2		: in std_ulogic;
      T3		: in std_ulogic;
      T4		: in std_ulogic;
      TCE		: in std_ulogic
      );

end OSERDES;

architecture OSERDES_V OF OSERDES is


component IOOUT
  generic(
         SERDES                 : boolean;
         SERDES_MODE            : string;
         DATA_RATE_OQ           : string;
         DATA_WIDTH             : integer;
         DDR_CLK_EDGE           : string;
         INIT_OQ                : bit;
         SRVAL_OQ               : bit;
         INIT_ORANK1            : bit_vector(5 downto 0);
         INIT_ORANK2_PARTIAL    : bit_vector(3 downto 0);
         INIT_LOADCNT           : bit_vector(3 downto 0);
         SRTYPE                 : string

    );
  port(
      OQ                : out std_ulogic;
      LOAD              : out std_ulogic;
      SHIFTOUT1         : out std_ulogic;
      SHIFTOUT2         : out std_ulogic;

      C                 : in std_ulogic;
      CLKDIV            : in std_ulogic;
      D1                : in std_ulogic;
      D2                : in std_ulogic;
      D3                : in std_ulogic;
      D4                : in std_ulogic;
      D5                : in std_ulogic;
      D6                : in std_ulogic;
      OCE               : in std_ulogic;
      REV               : in std_ulogic;
      SR                : in std_ulogic;
      SHIFTIN1          : in std_ulogic;
      SHIFTIN2          : in std_ulogic
    );

end component;

component IOT
  generic(
      DATA_RATE_TQ           : string;
      TRISTATE_WIDTH         : integer;
      DDR_CLK_EDGE           : string;
      INIT_TQ                : bit;
      INIT_TRANK1            : bit_vector(3 downto 0);
      SRVAL_TQ               : bit;
      SRTYPE                 : string
    );
  port(
      TQ                : out std_ulogic;

      C                 : in std_ulogic;
      CLKDIV            : in std_ulogic;
      LOAD              : in std_ulogic;
      REV               : in std_ulogic;
      SR                 : in std_ulogic;
      T1                : in std_ulogic;
      T2                : in std_ulogic;
      T3                : in std_ulogic;
      T4                : in std_ulogic;
      TCE               : in std_ulogic
    );

end component;

  constant SYNC_PATH_DELAY	: time := 100 ps;

  signal load_int		: std_ulogic := 'X';

  signal CLK_ipd                : std_ulogic := 'X';
  signal CLKDIV_ipd             : std_ulogic := 'X';
  signal D1_ipd                 : std_ulogic := 'X';
  signal D2_ipd                 : std_ulogic := 'X';
  signal D3_ipd                 : std_ulogic := 'X';
  signal D4_ipd                 : std_ulogic := 'X';
  signal D5_ipd                 : std_ulogic := 'X';
  signal D6_ipd                 : std_ulogic := 'X';
  signal GSR            : std_ulogic := '0';
  signal GSR_ipd                : std_ulogic := 'X';
  signal OCE_ipd                : std_ulogic := 'X';
  signal REV_ipd                : std_ulogic := 'X';
  signal SR_ipd                  : std_ulogic := 'X';
  signal SHIFTIN1_ipd           : std_ulogic := 'X';
  signal SHIFTIN2_ipd           : std_ulogic := 'X';
  signal TCE_ipd                : std_ulogic := 'X';
  signal T1_ipd                 : std_ulogic := 'X';
  signal T2_ipd                 : std_ulogic := 'X';
  signal T3_ipd                 : std_ulogic := 'X';
  signal T4_ipd                 : std_ulogic := 'X';

  signal CLK_dly                : std_ulogic := 'X';
  signal CLKDIV_dly             : std_ulogic := 'X';
  signal D1_dly                 : std_ulogic := 'X';
  signal D2_dly                 : std_ulogic := 'X';
  signal D3_dly                 : std_ulogic := 'X';
  signal D4_dly                 : std_ulogic := 'X';
  signal D5_dly                 : std_ulogic := 'X';
  signal D6_dly                 : std_ulogic := 'X';
  signal GSR_dly                : std_ulogic := 'X';
  signal OCE_dly                : std_ulogic := 'X';
  signal REV_dly                : std_ulogic := 'X';
  signal SR_dly                  : std_ulogic := 'X';
  signal SHIFTIN1_dly           : std_ulogic := 'X';
  signal SHIFTIN2_dly           : std_ulogic := 'X';
  signal TCE_dly                : std_ulogic := 'X';
  signal T1_dly                 : std_ulogic := 'X';
  signal T2_dly                 : std_ulogic := 'X';
  signal T3_dly                 : std_ulogic := 'X';
  signal T4_dly                 : std_ulogic := 'X';

  signal CLKD                   : std_ulogic := 'X';
  signal CLKDIVD                : std_ulogic := 'X';

  signal OQ_zd                  : std_ulogic := 'X';
  signal SHIFTOUT1_zd           : std_ulogic := 'X';
  signal SHIFTOUT2_zd           : std_ulogic := 'X';
  signal TQ_zd                  : std_ulogic := 'X';

begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  CLK_dly        	 <= CLK            	after 0 ps;
  CLKDIV_dly     	 <= CLKDIV         	after 0 ps;
  D1_dly         	 <= D1             	after 100 ps;
  D2_dly         	 <= D2             	after 100 ps;
  D3_dly         	 <= D3             	after 100 ps;
  D4_dly         	 <= D4             	after 100 ps;
  D5_dly         	 <= D5             	after 100 ps;
  D6_dly         	 <= D6             	after 100 ps;
  GSR_dly        	 <= GSR            	after 0 ps;
  OCE_dly        	 <= OCE            	after 0 ps;
  REV_dly        	 <= REV            	after 0 ps;
  SHIFTIN1_dly   	 <= SHIFTIN1       	after 0 ps;
  SHIFTIN2_dly   	 <= SHIFTIN2       	after 0 ps;
  SR_dly         	 <= SR             	after 0 ps;
  T1_dly         	 <= T1             	after 100 ps;
  T2_dly         	 <= T2             	after 100 ps;
  T3_dly         	 <= T3             	after 100 ps;
  T4_dly         	 <= T4             	after 100 ps;
  TCE_dly        	 <= TCE            	after 0 ps;


--  Delay the clock 100 ps to match the HW
  CLKD    <= CLK_dly after 0 ps;
  CLKDIVD <= CLKDIV_dly after 0 ps;
------------------------------------------------------------------
-----------    Instant IOOUT  -----------------------------------
------------------------------------------------------------------
  INST_IOOUT: IOOUT
  generic map (
      SERDES			=> SERDES,
      SERDES_MODE		=> SERDES_MODE,
      DATA_RATE_OQ		=> DATA_RATE_OQ,
      DATA_WIDTH                => DATA_WIDTH,
      DDR_CLK_EDGE		=> DDR_CLK_EDGE,
      INIT_OQ			=> INIT_OQ,
      SRVAL_OQ			=> SRVAL_OQ,
      INIT_ORANK1		=> INIT_ORANK1,
      INIT_ORANK2_PARTIAL	=> INIT_ORANK2_PARTIAL,
      INIT_LOADCNT		=> INIT_LOADCNT,
      SRTYPE			=> SRTYPE
     )
  port map (
      OQ			=> OQ_zd,
      LOAD			=> LOAD_int,
      SHIFTOUT1			=> SHIFTOUT1_zd,
      SHIFTOUT2			=> SHIFTOUT2_zd,
      C				=> CLKD,
      CLKDIV			=> CLKDIVD,
      D1			=> D1_dly,
      D2			=> D2_dly,
      D3			=> D3_dly,
      D4			=> D4_dly,
      D5			=> D5_dly,
      D6			=> D6_dly,
      OCE			=> OCE_dly,
      REV			=> REV_dly,
      SR			=> SR_dly,
      SHIFTIN1			=> SHIFTIN1_dly,
      SHIFTIN2			=> SHIFTIN2_dly
      );
------------------------------------------------------------------
-----------    Instant TRI_OUT  ----------------------------------
------------------------------------------------------------------
  INST_IOT: IOT
  generic map (
      DATA_RATE_TQ		=> DATA_RATE_TQ,
      TRISTATE_WIDTH		=> TRISTATE_WIDTH,
      DDR_CLK_EDGE		=> DDR_CLK_EDGE,
      INIT_TQ			=> INIT_TQ,
      INIT_TRANK1		=> INIT_TRANK1,
      SRVAL_TQ			=> SRVAL_TQ,
      SRTYPE			=> SRTYPE
     )
  port map (
      TQ			=> TQ_zd,

      C				=> CLKD,
      CLKDIV			=> CLKDIVD,
      LOAD			=> LOAD_int,
      REV			=> REV_dly,
      SR			=> SR_dly,
      T1			=> T1_dly,
      T2			=> T2_dly,
      T3			=> T3_dly,
      T4			=> T4_dly,
      TCE			=> TCE_dly
      );

--####################################################################

  prcs_output:process
  begin
     OQ <= OQ_zd after SYNC_PATH_DELAY; 
     SHIFTOUT1 <= SHIFTOUT1_zd after SYNC_PATH_DELAY;
     SHIFTOUT2 <= SHIFTOUT2_zd after SYNC_PATH_DELAY;
     TQ <= TQ_zd after SYNC_PATH_DELAY; 
     wait on  OQ_zd, SHIFTOUT1_zd, SHIFTOUT2_zd, TQ_zd;
  end process prcs_output;

end OSERDES_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                  Phase-Matched Clock Divider
-- /___/   /\     Filename : PMCD.vhd
-- \   \  /  \    Timestamp : Fri Mar 26 08:18:21 PST 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    06/20/07 - generate clka1d2 clka1d4 clka1d8 in same block to remove delta delay (CR440337)
-- End Revision

----- CELL PMCD -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;


library unisim;
use unisim.vpkg.all;

entity PMCD is

  generic(
      EN_REL           : boolean := FALSE;
      RST_DEASSERT_CLK : string  := "CLKA"
      );

  port(
      CLKA1   : out std_ulogic;
      CLKA1D2 : out std_ulogic;
      CLKA1D4 : out std_ulogic;
      CLKA1D8 : out std_ulogic;
      CLKB1   : out std_ulogic;
      CLKC1   : out std_ulogic;
      CLKD1   : out std_ulogic;

      CLKA    : in  std_ulogic;
      CLKB    : in  std_ulogic;
      CLKC    : in  std_ulogic;
      CLKD    : in  std_ulogic;
      REL     : in  std_ulogic;
      RST     : in  std_ulogic
      );

end PMCD;

architecture PMCD_V OF PMCD is


  constant SYNC_PATH_DELAY	: time := 100 ps;

  signal CLKA_ipd		: std_ulogic := 'X';
  signal CLKB_ipd		: std_ulogic := 'X';
  signal CLKC_ipd		: std_ulogic := 'X';
  signal CLKD_ipd		: std_ulogic := 'X';

  signal REL_ipd		: std_ulogic := 'X';
  signal RST_ipd		: std_ulogic := 'X';

  signal CLKA_dly		: std_ulogic := 'X';
  signal CLKB_dly		: std_ulogic := 'X';
  signal CLKC_dly		: std_ulogic := 'X';
  signal CLKD_dly		: std_ulogic := 'X';

  signal REL_dly		: std_ulogic := 'X';
  signal RST_dly		: std_ulogic := 'X';

  signal CLKA1_zd		: std_ulogic := 'X';
  signal CLKA1D2_zd		: std_ulogic := 'X';
  signal CLKA1D4_zd		: std_ulogic := 'X';
  signal CLKA1D8_zd		: std_ulogic := 'X';
  signal CLKB1_zd		: std_ulogic := 'X';
  signal CLKC1_zd		: std_ulogic := 'X';
  signal CLKD1_zd		: std_ulogic := 'X';

  signal rel_clk_sel		: integer    := 0;
  signal rst_active    		: boolean    := true;
  signal r1_out        		: std_ulogic := '0';
  signal rdiv_out      		: std_ulogic := '0';
  signal active_clk    		: std_ulogic := 'X';

  signal Violation_CLKA1        : std_ulogic := '0';
  signal Violation_CLKB1        : std_ulogic := '0';
  signal Violation_CLKC1        : std_ulogic := '0';
  signal Violation_CLKD1        : std_ulogic := '0';

  signal GSR_dly		: std_ulogic := '0';

begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  CLKA_dly       	 <= CLKA           	after 0 ps;
  CLKB_dly       	 <= CLKB           	after 0 ps;
  CLKC_dly       	 <= CLKC           	after 0 ps;
  CLKD_dly       	 <= CLKD           	after 0 ps;
  REL_dly        	 <= REL            	after 0 ps;
  RST_dly        	 <= RST            	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process
  variable FIRST_TIME : boolean := true;
  begin
      if((RST_DEASSERT_CLK = "clka") or (RST_DEASSERT_CLK = "CLKA")) then
         rel_clk_sel <= 1;
      elsif((RST_DEASSERT_CLK = "clkb") or (RST_DEASSERT_CLK = "CLKB")) then
         rel_clk_sel <= 2;
      elsif((RST_DEASSERT_CLK = "clkc") or (RST_DEASSERT_CLK = "CLKC")) then
         rel_clk_sel <= 3;
      elsif((RST_DEASSERT_CLK = "clkd") or (RST_DEASSERT_CLK = "CLKD")) then
         rel_clk_sel <= 4;
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " RST_DEASSERT_CLK ",
             EntityName => "/PMCD",
             GenericValue => RST_DEASSERT_CLK,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " CLKA, CLKB, CLKC or CLKD ",
             TailMsg => "",
             MsgSeverity => ERROR
         );
      end if;

      if(EN_REL = true) then
         rst_active <= false;
      elsif(EN_REL = false) then
         rst_active <= true;
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " EN_REL ",
             EntityName => "/PMCD",
             GenericValue => EN_REL,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => "True or False",
             TailMsg => "",
             MsgSeverity => ERROR
         );
      end if;
     wait;
  end process prcs_init;
--####################################################################
--#####                           CLKA                           #####
--####################################################################
  prcs_clka:process(CLKA_dly, r1_out, rdiv_out, GSR_dly)
  variable first_time : boolean := true;
  begin
     if(GSR_dly = '1') then
         CLKA1_zd <= '0';
         CLKA1D2_zd <= '0';
         CLKA1D4_zd <= '0';
         CLKA1D8_zd <= '0';
     elsif(GSR_dly = '0') then

        if((first_time) and ((CLKA_dly = '0') or CLKA_dly = '1')) then
          CLKA1_zd <= CLKA_dly;
          CLKA1D2_zd <= CLKA_dly;
          CLKA1D4_zd <= CLKA_dly;
          CLKA1D8_zd <= CLKA_dly;
          first_time := false;
        end if;

        if(r1_out = '0') then
            CLKA1_zd <= CLKA_dly;
        elsif (r1_out = '1') then
          CLKA1_zd <= '0';
        end if;

        if(rdiv_out = '1') then
           CLKA1D2_zd <= '0';
           CLKA1D4_zd <= '0';
           CLKA1D8_zd <= '0';
        elsif(rdiv_out = '0') then
          if(rising_edge(CLKA_dly)) then
            CLKA1D2_zd <= NOT CLKA1D2_zd;
            if (CLKA1D2_zd = '0') then
                CLKA1D4_zd <= NOT CLKA1D4_zd;
                if (CLKA1D4_zd = '0') then
                    CLKA1D8_zd <= NOT CLKA1D8_zd;
                end if;
             end if;
          end if;
        end if;
     end if;
  end process prcs_clka;
--####################################################################
--#####                           CLKB                           #####
--####################################################################
 prcs_clkb:process(CLKB_dly, r1_out, GSR_dly)
  variable first_time : boolean := true;
  begin
     if((GSR_dly = '1') or (r1_out = '1')) then
          CLKB1_zd <= '0';
     elsif ((GSR_dly = '0') and (r1_out = '0')) then
           CLKB1_zd <= CLKB_dly;
     end if;
  end process prcs_clkb;
--####################################################################
--#####                           CLKC                           #####
--####################################################################
 prcs_clkc:process(CLKC_dly, r1_out, GSR_dly)
  variable first_time : boolean := true;
  begin
     if((GSR_dly = '1') or (r1_out = '1')) then
          CLKC1_zd <= '0';
     elsif ((GSR_dly = '0') and (r1_out = '0')) then
           CLKC1_zd <= CLKC_dly;
     end if;
  end process prcs_clkc;
--####################################################################
--#####                           CLKD                           #####
--####################################################################
 prcs_clkd:process(CLKD_dly, r1_out, GSR_dly)
  variable first_time : boolean := true;
  begin
     if((GSR_dly = '1') or (r1_out = '1')) then
          CLKD1_zd <= '0';
     elsif ((GSR_dly = '0') and (r1_out = '0')) then
           CLKD1_zd <= CLKD_dly;
     end if;
  end process prcs_clkd;
--####################################################################
--#####                       RST CLK SEL                        #####
--####################################################################
  prcs_rel_clk_mux:process(CLKA_dly, CLKB_dly, CLKC_dly, CLKD_dly)
  begin
      case rel_clk_sel is
             when 1 => active_clk <= CLKA_dly;
             when 2 => active_clk <= CLKB_dly;
             when 3 => active_clk <= CLKC_dly;
             when 4 => active_clk <= CLKD_dly;
             when others => null;
      end case;
  end process prcs_rel_clk_mux;

--####################################################################
--#####                     RELEASE SIGNAL                       #####
--####################################################################
  prcs_act_rel:process(active_clk, REL_dly, RST_dly, GSR_dly)
  variable released      : boolean := false;
  variable r1_released   : boolean := false;
  variable rdiv_released : boolean := false;
  variable start_rel_clk_count : boolean := false;
  variable rel_clk_count : integer := 0;
  variable path_1_clk_count : integer := 0;
  variable path_1        : std_ulogic := '0';
  variable path_2        : std_ulogic := '0';

  begin
      if((GSR_dly = '1') or (RST_dly = '1')) then
          released      := false;
          r1_released   := false;
          rdiv_released := false;
          rel_clk_count := 0;
          start_rel_clk_count := false;
          r1_out   <= '1';
          rdiv_out <= '1';
          path_1_clk_count := 0;
          path_1 := '1';
          path_2 := '1';
      elsif ((GSR_dly = '0') and (RST_dly = '0')) then
         if(rst_active) then
           if(not released) then
             if(rising_edge(active_clk)) then
              start_rel_clk_count := true;
             end if;
             if(active_clk'event and start_rel_clk_count) then
               rel_clk_count := rel_clk_count + 1;
             end if;
             if(rel_clk_count >= 1) then
                rdiv_out <= '0';
             end if;
             if(rel_clk_count >= 2) then
                r1_out   <= '0';
                released := true;
             end if;
           end if;
         elsif(not rst_active) then
           if(not r1_released) then
             if(rising_edge(active_clk)) then
              start_rel_clk_count := true;
             end if;
             if(active_clk'event and start_rel_clk_count) then
               rel_clk_count := rel_clk_count + 1;
             end if;
             if(rel_clk_count >= 2) then
                r1_out <= '0';
                r1_released := true;
             end if;
           end if;
           if(not rdiv_released) then
             if(rising_edge(active_clk)) then
               path_1_clk_count := path_1_clk_count + 1;
               if(path_1_clk_count >=  1) then
                path_1 := '0';
               end if;
             end if;

             if(rising_edge(REL_dly)) then
                path_2 := '0';
             end if;

             if((path_1 = '0') and (path_2 = '0')) then
                rdiv_out <= '0';
                rdiv_released := true;
             end if;
           end if;
         end if;
      end if;
  end process prcs_act_rel;
--####################################################################

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(CLKA1_zd, CLKA1D2_zd, CLKA1D4_zd, CLKA1D8_zd,
                      CLKB1_zd, CLKC1_zd, CLKD1_zd)
  begin
      CLKA1 <= CLKA1_zd after SYNC_PATH_DELAY;
      CLKA1D2 <= CLKA1D2_zd after SYNC_PATH_DELAY;
      CLKA1D4 <= CLKA1D4_zd after SYNC_PATH_DELAY;
      CLKA1D8 <= CLKA1D8_zd after SYNC_PATH_DELAY;

      CLKB1 <= CLKB1_zd after SYNC_PATH_DELAY;

      CLKC1 <= CLKC1_zd after SYNC_PATH_DELAY;

      CLKD1 <= CLKD1_zd after SYNC_PATH_DELAY;

  end process prcs_output;
--####################################################################


end PMCD_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Single Port Block RAM
-- /___/   /\     Filename : RAMB16.vhd
-- \   \  /  \    Timestamp : Thu Mar 17 16:56:02 PST 2005
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    03/17/05 - Added EN_ECC_READ/WRITE -- affects tim sim model only  -- CR 204627 --FP
--    05/24/05 - Fixed CR 200506 --FP
--    08/25/05 - Fixed CR 215294 --FP -- Added Message for unequal WEs in WF mode
--    11/15/05 - Fixed CR 219497 --FP -- made collision functions inout -- ncsim issue
--    01/05/06 - Fixed CR 223161 --FP -- propagated INIT values.
--    02/06/06 - Fixed CR 223097 --FP -- CASCADE/NO_CHANGE message.
--    05/19/06 - Fixed CR 231750 --FP -- Added timing arcs for Cascadein to output.
--    06/30/06 - Fixed CR 231750 --FP -- Added timing checks for CLK to Cascadein.
--    07/10/06 - Added 2 dimensional memory array feature.
--    01/24/07 - Added support of memory file to initialize memory and parity (CR 431584).  
--    02/13/07 - Fixed register output in cascaded mode (CR 433819).  
--    03/05/07 - Fixed inverted clock (CR 434198).
--    03/13/07 - Removed attribute INITP_FILE (CR 436003).
--    04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812). 
--    04/01/08 - Fixed delta delay problem on inputs (CR470144).
-- End Revision

----- CELL RAMB16 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library STD;
use STD.TEXTIO.all;

library unisim;
use unisim.vpkg.all;

entity RAMB16 is

  generic (

    DOA_REG : integer := 0 ;
    DOB_REG : integer := 0 ;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"000000000";
    INIT_B : bit_vector := X"000000000";
    INIT_FILE : string := "NONE";
    
    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    
    INVERT_CLK_DOA_REG : boolean := false;
    INVERT_CLK_DOB_REG : boolean := false;

    RAM_EXTENSION_A : string := "NONE";
    RAM_EXTENSION_B : string := "NONE";

    READ_WIDTH_A : integer := 0;
    READ_WIDTH_B : integer := 0;


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A  : bit_vector := X"000000000";
    SRVAL_B  : bit_vector := X"000000000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST";

    WRITE_WIDTH_A : integer := 0;
    WRITE_WIDTH_B : integer := 0
    );

  port(
    CASCADEOUTA  : out  std_ulogic;
    CASCADEOUTB  : out  std_ulogic;
    DOA          : out std_logic_vector (31 downto 0);
    DOB          : out std_logic_vector (31 downto 0);
    DOPA         : out std_logic_vector (3 downto 0);
    DOPB         : out std_logic_vector (3 downto 0);

    ADDRA        : in  std_logic_vector (14 downto 0);
    ADDRB        : in  std_logic_vector (14 downto 0);
    CASCADEINA   : in  std_ulogic;
    CASCADEINB   : in  std_ulogic;
    CLKA         : in  std_ulogic;
    CLKB         : in  std_ulogic;
    DIA          : in  std_logic_vector (31 downto 0);
    DIB          : in  std_logic_vector (31 downto 0);
    DIPA         : in  std_logic_vector (3 downto 0);
    DIPB         : in  std_logic_vector (3 downto 0);
    ENA          : in  std_ulogic;
    ENB          : in  std_ulogic;
    REGCEA       : in  std_ulogic;
    REGCEB       : in  std_ulogic;
    SSRA         : in  std_ulogic;
    SSRB         : in  std_ulogic;
    WEA          : in  std_logic_vector (3 downto 0);
    WEB          : in  std_logic_vector (3 downto 0)
    );

end RAMB16;

architecture RAMB16_V of RAMB16 is

  component ARAMB36_INTERNAL
	generic
	(
          BRAM_MODE : string := "TRUE_DUAL_PORT";
          BRAM_SIZE : integer := 36;
          DOA_REG : integer := 0;
          DOB_REG : integer := 0;
          INIT_A : bit_vector := X"000000000000000000";
          INIT_B : bit_vector := X"000000000000000000";
          RAM_EXTENSION_A : string := "NONE";
          RAM_EXTENSION_B : string := "NONE";
          READ_WIDTH_A : integer := 0;
          READ_WIDTH_B : integer := 0;
          SIM_COLLISION_CHECK : string := "ALL";
          SRVAL_A : bit_vector := X"000000000000000000";
          SRVAL_B : bit_vector := X"000000000000000000";
          WRITE_MODE_A : string := "WRITE_FIRST";
          WRITE_MODE_B : string := "WRITE_FIRST";
          WRITE_WIDTH_A : integer := 0;
          WRITE_WIDTH_B : integer := 0;
          EN_ECC_READ : boolean := FALSE;
          EN_ECC_SCRUB : boolean := FALSE;
          EN_ECC_WRITE : boolean := FALSE;
          INIT_FILE : string := "NONE";
                    
          INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
           );
	port
	(
          CASCADEOUTLATA : out std_ulogic;
          CASCADEOUTLATB : out std_ulogic;
          CASCADEOUTREGA : out std_ulogic;
          CASCADEOUTREGB : out std_ulogic;
          DBITERR : out std_ulogic;
          DOA : out std_logic_vector(63 downto 0);
          DOB : out std_logic_vector(63 downto 0);
          DOPA : out std_logic_vector(7 downto 0);
          DOPB : out std_logic_vector(7 downto 0);
          ECCPARITY : out std_logic_vector(7 downto 0);
          SBITERR : out std_ulogic;
    
          ADDRA : in std_logic_vector(15 downto 0);
          ADDRB : in std_logic_vector(15 downto 0);
          CASCADEINLATA : in std_ulogic;
          CASCADEINLATB : in std_ulogic;
          CASCADEINREGA : in std_ulogic;
          CASCADEINREGB : in std_ulogic;
          CLKA : in std_ulogic;
          CLKB : in std_ulogic;
          DIA : in std_logic_vector(63 downto 0);
          DIB : in std_logic_vector(63 downto 0);
          DIPA : in std_logic_vector(7 downto 0);
          DIPB : in std_logic_vector(7 downto 0);
          ENA : in std_ulogic;
          ENB : in std_ulogic;
          REGCEA : in std_ulogic;
          REGCEB : in std_ulogic;
          REGCLKA : in std_ulogic;
          REGCLKB : in std_ulogic;
          SSRA : in std_ulogic;
          SSRB : in std_ulogic;
          WEA : in std_logic_vector(7 downto 0);
          WEB : in std_logic_vector(7 downto 0)
 	);
  end component;

  
  constant SYNC_PATH_DELAY : time := 100 ps;
  signal GND_4 : std_logic_vector(3 downto 0) := (others => '0');
  signal GND_32 : std_logic_vector(31 downto 0) := (others => '0');
  signal OPEN_4 : std_logic_vector(3 downto 0);
  signal OPEN_32 : std_logic_vector(31 downto 0);
  signal doa_dly : std_logic_vector(31 downto 0) :=  (others => '0');
  signal dob_dly : std_logic_vector(31 downto 0) :=  (others => '0');
  signal dopa_dly : std_logic_vector(3 downto 0) :=  (others => '0');
  signal dopb_dly : std_logic_vector(3 downto 0) :=  (others => '0');
  signal cascadeouta_dly : std_ulogic := '0';
  signal cascadeoutb_dly : std_ulogic := '0';
  signal cascadeoutlata_out : std_ulogic := '0';
  signal cascadeoutlatb_out : std_ulogic := '0';
  signal cascadeoutrega_out : std_ulogic := '0';
  signal cascadeoutregb_out : std_ulogic := '0';
  signal addra_int : std_logic_vector(15 downto 0) := (others => '0');
  signal addrb_int : std_logic_vector(15 downto 0) := (others => '0');
  signal wea_int : std_logic_vector(7 downto 0) := (others => '0');
  signal web_int : std_logic_vector(7 downto 0) := (others => '0');
  signal clka_tmp : std_ulogic := '0';
  signal clkb_tmp : std_ulogic := '0';
  signal regclka_tmp : std_ulogic := '0';
  signal regclkb_tmp : std_ulogic := '0';
  signal dia_tmp : std_logic_vector(31 downto 0) :=  (others => '0');
  signal dib_tmp : std_logic_vector(31 downto 0) :=  (others => '0');
  signal dipa_tmp : std_logic_vector(3 downto 0) :=  (others => '0');
  signal dipb_tmp : std_logic_vector(3 downto 0) :=  (others => '0');
  signal ena_tmp : std_ulogic := '0';
  signal enb_tmp : std_ulogic := '0';
  signal ssra_tmp : std_ulogic := '0';
  signal ssrb_tmp : std_ulogic := '0';
  signal cascadeina_tmp : std_ulogic := '0';
  signal cascadeinb_tmp : std_ulogic := '0';
  signal regcea_tmp : std_ulogic := '0';
  signal regceb_tmp : std_ulogic := '0';
  
  
  function Invert_CLK (
    invert_clk_do_reg : boolean;
    do_reg : integer;
    clk : std_ulogic)
    return std_ulogic is variable out_clk : std_ulogic;
  begin

    if (do_reg = 1 and invert_clk_do_reg = TRUE) then
      out_clk := not clk;
    else
      out_clk := clk;
    end if;

    return out_clk;  
                         
  end;

  
  function Temp_BIT (
    clk : std_ulogic)
    return std_ulogic is variable out_clk : std_ulogic;
  begin

    out_clk := clk;
    return out_clk;  
    
  end;


  function Temp_BUS (
    d_in : std_logic_vector)
    return std_logic_vector is variable d_out : std_logic_vector(d_in'length-1 downto 0);
  begin

    d_out := d_in;
    return d_out;  
    
  end;

  
begin
  
  prcs_clk: process
    
    begin

        if((INVERT_CLK_DOA_REG = true) and (DOA_REG /= 1 )) then
          assert false
            report "Attribute Syntax Error:  When INVERT_CLK_DOA_REG is set to TRUE, then DOA_REG has to be set to 1."
          severity Failure;
        end if;

        if((INVERT_CLK_DOB_REG = true) and (DOB_REG /= 1 )) then
          assert false
            report "Attribute Syntax Error:  When INVERT_CLK_DOB_REG is set to TRUE, then DOB_REG has to be set to 1."
          severity Failure;
        end if;

        if((INVERT_CLK_DOA_REG /= TRUE) and (INVERT_CLK_DOA_REG /= FALSE)) then
          assert false
            report "Attribute Syntax Error : The allowed boolean values for INVERT_CLK_DOA_REG are TRUE or FALSE"
          severity Failure;
        end if;
        
        if((INVERT_CLK_DOB_REG /= TRUE) and (INVERT_CLK_DOB_REG /= FALSE)) then
          assert false
            report "Attribute Syntax Error : The allowed boolean values for INVERT_CLK_DOB_REG are TRUE or FALSE"
          severity Failure;
        end if;

        wait;
        
    end process prcs_clk;

  
    prcs_cascadea: process (cascadeoutrega_out, cascadeoutlata_out)

      begin
        
        if (DOA_REG = 1) then
          cascadeouta_dly <= cascadeoutrega_out;
        else
          cascadeouta_dly <= cascadeoutlata_out;  
        end if;

    end process prcs_cascadea;

    
    prcs_cascadeb: process (cascadeoutregb_out, cascadeoutlatb_out)

      begin
        if (DOB_REG = 1) then
          cascadeoutb_dly <= cascadeoutregb_out;
        else
          cascadeoutb_dly <= cascadeoutlatb_out;  
        end if;

    end process prcs_cascadeb;

            
    addra_int <= ADDRA(14) & '0' & ADDRA(13 downto 0);
    addrb_int <= ADDRB(14) & '0' & ADDRB(13 downto 0);
    wea_int <= WEA & WEA;
    web_int <= WEB & WEB;
    regclka_tmp <= Invert_CLK(INVERT_CLK_DOA_REG, DOA_REG, CLKA);
    regclkb_tmp <= Invert_CLK(INVERT_CLK_DOB_REG, DOB_REG, CLKB);
    clka_tmp <= Temp_BIT(CLKA);
    clkb_tmp <= Temp_BIT(CLKB);
    dia_tmp <= Temp_BUS(DIA);
    dib_tmp <= Temp_BUS(DIB);
    dipa_tmp <= Temp_BUS(DIPA);
    dipb_tmp <= Temp_BUS(DIPB); 
    cascadeina_tmp <= Temp_BIT(CASCADEINA);
    cascadeinb_tmp <= Temp_BIT(CASCADEINB);
    ena_tmp <= Temp_BIT(ENA);
    enb_tmp <= Temp_BIT(ENB);
    ssra_tmp <= Temp_BIT(SSRA);
    ssrb_tmp <= Temp_BIT(SSRB);
    regcea_tmp <= Temp_BIT(REGCEA);
    regceb_tmp <= Temp_BIT(REGCEB);
      
RAMB16_inst : ARAMB36_INTERNAL
	generic map (

                DOA_REG => DOA_REG,
                DOB_REG => DOB_REG,
		INIT_A  => INIT_A,
		INIT_B  => INIT_B,
                INIT_FILE => INIT_FILE,
                
		INIT_00 => INIT_00,
		INIT_01 => INIT_01,
		INIT_02 => INIT_02,
		INIT_03 => INIT_03,
		INIT_04 => INIT_04,
		INIT_05 => INIT_05,
		INIT_06 => INIT_06,
		INIT_07 => INIT_07,
		INIT_08 => INIT_08,
		INIT_09 => INIT_09,
		INIT_0A => INIT_0A,
		INIT_0B => INIT_0B,
		INIT_0C => INIT_0C,
		INIT_0D => INIT_0D,
		INIT_0E => INIT_0E,
		INIT_0F => INIT_0F,
		INIT_10 => INIT_10,
		INIT_11 => INIT_11,
		INIT_12 => INIT_12,
		INIT_13 => INIT_13,
		INIT_14 => INIT_14,
		INIT_15 => INIT_15,
		INIT_16 => INIT_16,
		INIT_17 => INIT_17,
		INIT_18 => INIT_18,
		INIT_19 => INIT_19,
		INIT_1A => INIT_1A,
		INIT_1B => INIT_1B,
		INIT_1C => INIT_1C,
		INIT_1D => INIT_1D,
		INIT_1E => INIT_1E,
		INIT_1F => INIT_1F,
		INIT_20 => INIT_20,
		INIT_21 => INIT_21,
		INIT_22 => INIT_22,
		INIT_23 => INIT_23,
		INIT_24 => INIT_24,
		INIT_25 => INIT_25,
		INIT_26 => INIT_26,
		INIT_27 => INIT_27,
		INIT_28 => INIT_28,
		INIT_29 => INIT_29,
		INIT_2A => INIT_2A,
		INIT_2B => INIT_2B,
		INIT_2C => INIT_2C,
		INIT_2D => INIT_2D,
		INIT_2E => INIT_2E,
		INIT_2F => INIT_2F,
		INIT_30 => INIT_30,
		INIT_31 => INIT_31,
		INIT_32 => INIT_32,
		INIT_33 => INIT_33,
		INIT_34 => INIT_34,
		INIT_35 => INIT_35,
		INIT_36 => INIT_36,
		INIT_37 => INIT_37,
		INIT_38 => INIT_38,
		INIT_39 => INIT_39,
		INIT_3A => INIT_3A,
		INIT_3B => INIT_3B,
		INIT_3C => INIT_3C,
		INIT_3D => INIT_3D,
		INIT_3E => INIT_3E,
		INIT_3F => INIT_3F,
                
		INITP_00 => INITP_00,
		INITP_01 => INITP_01,
		INITP_02 => INITP_02,
		INITP_03 => INITP_03,
		INITP_04 => INITP_04,
		INITP_05 => INITP_05,
		INITP_06 => INITP_06,
		INITP_07 => INITP_07,
                
		SIM_COLLISION_CHECK => SIM_COLLISION_CHECK,
		SRVAL_A => SRVAL_A,
		SRVAL_B => SRVAL_B,
		WRITE_MODE_A => WRITE_MODE_A,
		WRITE_MODE_B => WRITE_MODE_B,                
                BRAM_MODE => "TRUE_DUAL_PORT",
                BRAM_SIZE => 16,
                RAM_EXTENSION_A => RAM_EXTENSION_A,
                RAM_EXTENSION_B => RAM_EXTENSION_B,                
                READ_WIDTH_A => READ_WIDTH_A,
                READ_WIDTH_B => READ_WIDTH_B,                
                WRITE_WIDTH_A => WRITE_WIDTH_A,
                WRITE_WIDTH_B => WRITE_WIDTH_B          

                )
        port map (
                ADDRA => addra_int,
                ADDRB => addrb_int,
                CLKA => clka_tmp,
                CLKB => clkb_tmp,
                DIA(31 downto 0)  => dia_tmp,
                DIA(63 downto 32) => GND_32,
                DIB(31 downto 0) => dib_tmp,
                DIB(63 downto 32) => GND_32,
                DIPA(3 downto 0) => dipa_tmp,
                DIPA(7 downto 4) => GND_4,
                DIPB(3 downto 0) => dipb_tmp,
                DIPB(7 downto 4) => GND_4,
                ENA => ena_tmp,
                ENB => enb_tmp,
                SSRA => ssra_tmp,
                SSRB => ssrb_tmp,
                WEA => wea_int,
                WEB => web_int,
                DOA(31  downto 0) => doa_dly,
                DOA(63 downto 32) => OPEN_32,
                DOB(31 downto 0) => dob_dly,
                DOB(63 downto 32) => OPEN_32,
                DOPA(3 downto 0) => dopa_dly,
                DOPA(7 downto 4) => OPEN_4,
                DOPB(3 downto 0) => dopb_dly,
                DOPB(7 downto 4) => OPEN_4,
                CASCADEOUTLATA => cascadeoutlata_out,
                CASCADEOUTLATB => cascadeoutlatb_out,
                CASCADEOUTREGA => cascadeoutrega_out,
                CASCADEOUTREGB => cascadeoutregb_out,
                CASCADEINLATA => cascadeina_tmp,
                CASCADEINLATB => cascadeinb_tmp,
                CASCADEINREGA => cascadeina_tmp,
                CASCADEINREGB => cascadeinb_tmp,
                REGCLKA => regclka_tmp,
                REGCLKB => regclkb_tmp,
                REGCEA => regcea_tmp,
                REGCEB => regceb_tmp
        );


  prcs_output_wtiming: process (doa_dly, dob_dly, dopa_dly, dopb_dly, cascadeouta_dly, cascadeoutb_dly)
   begin  -- process prcs_output_wtiming

     CASCADEOUTA <= cascadeouta_dly after SYNC_PATH_DELAY;
     CASCADEOUTB <= cascadeoutb_dly after SYNC_PATH_DELAY;
     DOA <= doa_dly after SYNC_PATH_DELAY;
     DOPA <= dopa_dly after SYNC_PATH_DELAY;
     DOB <= dob_dly after SYNC_PATH_DELAY;
     DOPB <= dopb_dly after SYNC_PATH_DELAY;

   end process prcs_output_wtiming;

end RAMB16_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/ramb32_s64_ecc.vhd,v 1.8 2005/03/17 19:51:15 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                    Ramb32_s64_ecc 
-- /___/   /\     Filename : ramb32_s64_ecc.vhd
-- \   \  /  \    Timestamp : Tue Mar  1 14:57:54 PST 2005
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    03/04/05 - Add generic DO_REG and SIM_COLLISION_CHECK to pass to RAMB16.
--                    Add register to output for the latency. (CR 204569)
--    03/16/05 - Change parameter WRITE_MODE_A and WRITE_MODE_B to READ_FIRST.
-- End Revision

----- CELL RAMB32_S64_ECC -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.vpkg.all;
use unisim.VCOMPONENTS.all;

entity RAMB32_S64_ECC is

generic(
               DO_REG : integer := 0 ; 
               SIM_COLLISION_CHECK : string := "ALL" 
       );

port (
		DO : out std_logic_vector(63 downto 0);
		STATUS : out std_logic_vector(1 downto 0);

		DI : in std_logic_vector(63 downto 0);
		RDADDR : in std_logic_vector(8 downto 0);
		RDCLK : in std_ulogic;
		RDEN : in std_ulogic;
		SSR : in std_ulogic;
		WRADDR : in std_logic_vector(8 downto 0);
		WRCLK : in std_ulogic;
		WREN : in std_ulogic
     );
end RAMB32_S64_ECC;

-- Architecture body --

architecture RAMB32_S64_ECC_V of RAMB32_S64_ECC is


-- Input/Output Pin signals

        signal   do_ram16low  :  std_logic_vector(31 downto 0);
        signal   do_ram16up   :  std_logic_vector(31 downto 0);
        signal   dopa_ram16low  :  std_logic_vector(3 downto 0);
        signal   dopa_ram16up  :  std_logic_vector(3 downto 0);
        signal   STATUS_out  :  std_logic_vector(1 downto 0);
        signal   tmp41      :  std_logic_vector(3 downto 0) :="1111";
        signal   tmp640      :  std_logic_vector(63 downto 0) := (others=>'0');
        signal   tmp40      :  std_logic_vector(3 downto 0) :="0000";
        signal   tmp0       :  std_logic :='0';
        signal   tmp1       :  std_logic :='1';
        signal   ADDRA_tmp  :  std_logic_vector(14 downto 0) := "1XXXXXXXXX00000";
        signal   ADDRB_tmp  :  std_logic_vector(14 downto 0) := "1XXXXXXXXX00000";
        signal   DIB_up     :  std_logic_vector(31 downto 0);
        signal   DIB_low    :  std_logic_vector(31 downto 0);
        signal   DIPB_up     :  std_logic_vector(3 downto 0);
        signal   DIPB_low    :  std_logic_vector(3 downto 0);
        signal   DIA_tmp    :  std_logic_vector(31 downto 0) := (others=>'0');
        signal   DO_tmp    :  std_logic_vector(63 downto 0) := (others=>'0');


begin
 
  DO(63 downto 0) <= DO_tmp(63 downto 0);

  DO_OUT_P : process (RDCLK)
  begin
   if (RDCLK'event and RDCLK='1') then
     DO_tmp(13 downto 0) <= do_ram16low(13 downto 0);
     DO_tmp(14) <= dopa_ram16low(1);
     DO_tmp(15) <= dopa_ram16low(3);
     DO_tmp(29 downto 16) <= do_ram16low(29 downto 16);
     DO_tmp(30) <= dopa_ram16low(0);
     DO_tmp(31) <= dopa_ram16low(2);

     DO_tmp(32) <= dopa_ram16up(0);
     DO_tmp(33) <= dopa_ram16up(2);
     DO_tmp(47 downto 34) <= do_ram16up(15 downto 2);
     DO_tmp(48) <= dopa_ram16up(1);
     DO_tmp(49) <= dopa_ram16up(3);
     DO_tmp(63 downto 50) <= do_ram16up(31 downto 18);
   end if;
  end process DO_OUT_P;

  ADDR_IN_P : process (RDADDR, WRADDR)
  begin
    ADDRA_tmp(4 downto 0)       <=  "00000";
    ADDRA_tmp(13 downto 5)       <=  RDADDR(8 downto 0);
    ADDRA_tmp(14)              <= '1';
    ADDRB_tmp(4 downto 0)       <=  "00000";
    ADDRB_tmp(13 downto 5)       <=  WRADDR(8 downto 0);
    ADDRB_tmp(14)              <= '1';
  end process ADDR_IN_P;

  DATA_IN_P : process(DI)
  begin
     DIB_low(13 downto 0)         <=  DI(13 downto 0);
     DIB_low(15 downto 14)         <=  "00";
     DIPB_low(1)                  <=  DI(14);
     DIPB_low(3)                  <=  DI(15);
     DIB_low(29 downto 16)         <= DI(29 downto 16);
     DIB_low(31 downto 30)         <= "00";
     DIPB_low(0)                  <=  DI(30);
     DIPB_low(2)                  <=  DI(31);

     DIPB_up(0)                  <=  DI(32);
     DIPB_up(2)                  <=  DI(33);
     DIB_up(1 downto 0)          <=  "00";
     DIB_up(15 downto 2)         <=  DI(47 downto 34);
     DIPB_up(1)                  <=  DI(48);
     DIPB_up(3)                  <=  DI(49);
     DIB_up(17 downto 16)        <=  "00";
     DIB_up(31 downto 18)         <= DI(63 downto 50);
  end process DATA_IN_P;

  
  STATUS <= "00";


  RAMB16_LOWER : RAMB16
  generic map (
    READ_WIDTH_A  => 36,
    WRITE_WIDTH_A => 36,
    READ_WIDTH_B  => 36,
    WRITE_WIDTH_B => 36,
    WRITE_MODE_A  => "READ_FIRST",
    WRITE_MODE_B  => "READ_FIRST",
    INIT_A  => "000000000000000000000000000000000000",
    SRVAL_A => "000000000000000000000000000000000000",
    INIT_B  => "000000000000000000000000000000000000",
    SRVAL_B => "000000000000000000000000000000000000",
    DOA_REG => DO_REG,
    DOB_REG => 0,
    INVERT_CLK_DOA_REG => FALSE,
    INVERT_CLK_DOB_REG => FALSE,
    RAM_EXTENSION_A => "NONE",
    RAM_EXTENSION_B => "NONE",
    SIM_COLLISION_CHECK => SIM_COLLISION_CHECK
  )                                                         
  port map (
    ADDRA       => ADDRA_tmp,
    ADDRB       => ADDRB_tmp,
    DIA         => DIA_tmp,
    DIB         => DIB_low,
    DIPA        => tmp40,
    DIPB        => DIPB_low,
    ENA         => RDEN,
    ENB         => WREN,
    WEA         => tmp40,
    WEB         => tmp41,
    SSRA        => SSR,
    SSRB        => tmp0,
    CLKA        => RDCLK,
    CLKB        => WRCLK,
    REGCEA      => tmp1,
    REGCEB      => tmp0,
    CASCADEINA  => tmp0,
    CASCADEINB  => tmp0,
    DOA         => do_ram16low(31 downto 0),
    DOB         => open,
    DOPA        => dopa_ram16low(3 downto 0),
    DOPB        => open,
    CASCADEOUTA => open,
    CASCADEOUTB => open 

      );


  RAMB16_UPPER : RAMB16
  generic map (
    READ_WIDTH_A  => 36,
    WRITE_WIDTH_A => 36,
    READ_WIDTH_B  => 36,
    WRITE_WIDTH_B => 36,
    WRITE_MODE_A  => "READ_FIRST",
    WRITE_MODE_B  => "READ_FIRST",
    INIT_A  => "000000000000000000000000000000000000",
    SRVAL_A => "000000000000000000000000000000000000",
    INIT_B  => "000000000000000000000000000000000000",
    SRVAL_B => "000000000000000000000000000000000000",
    DOA_REG => DO_REG,
    DOB_REG => 0,
    INVERT_CLK_DOA_REG => FALSE,
    INVERT_CLK_DOB_REG => FALSE,
    RAM_EXTENSION_A => "NONE",
    RAM_EXTENSION_B => "NONE",
    SIM_COLLISION_CHECK => SIM_COLLISION_CHECK
  )                                                         
  port map (
    ADDRA       => ADDRA_tmp,
    ADDRB       => ADDRB_tmp,
    DIA         => DIA_tmp,
    DIB         => DIB_up,
    DIPA        => tmp40,
    DIPB        => DIPB_up,
    ENA         => RDEN,
    ENB         => WREN,
    WEA         => tmp40,
    WEB         => tmp41,
    SSRA        => SSR,
    SSRB        => tmp0,
    CLKA        => RDCLK,
    CLKB        => WRCLK,
    REGCEA      => tmp1,
    REGCEB      => tmp0,
    CASCADEINA  => tmp0,
    CASCADEINB  => tmp0,
    DOA         => do_ram16up(31 downto 0),
    DOB         => open,
    DOPA        => dopa_ram16up(3 downto 0),
    DOPB        => open,
    CASCADEOUTA => open,
    CASCADEOUTB => open 
      );

end RAMB32_S64_ECC_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/startbuf_virtex4.vhd,v 1.5 2004/04/08 18:46:30 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  User Interface to Global Clock, Reset and 3-State Controls for VIRTEX4
-- /___/   /\     Filename : STARTBUF_VIRTEX4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:05 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL STARTBUF_VIRTEX4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity STARTBUF_VIRTEX4 is
  port(
    EOSOUT	: out std_ulogic;
    GSROUT	: out std_ulogic;
    GTSOUT	: out std_ulogic;
    CLKIN	: in std_ulogic := 'X';          
    GSRIN	: in std_ulogic := 'X';
    GTSIN	: in std_ulogic := 'X';
    USRCCLKOIN	: in std_ulogic := 'X';
    USRCCLKTSIN	: in std_ulogic := 'X';
    USRDONEOIN	: in std_ulogic := 'X';
    USRDONETSIN	: in std_ulogic := 'X'

);

end STARTBUF_VIRTEX4;

architecture STARTBUF_VIRTEX4_V of STARTBUF_VIRTEX4 is

begin

   
   GSROUT <= GSRIN;
   GTSOUT <= GTSIN;
 

end STARTBUF_VIRTEX4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/startup_virtex4.vhd,v 1.5 2004/04/08 18:46:30 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  User Interface to Global Clock, Reset and 3-State Controls for VIRTEX4
-- /___/   /\     Filename : STARTUP_VIRTEX4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:05 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL STARTUP_VIRTEX4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity STARTUP_VIRTEX4 is
  port(
    EOS		: out std_ulogic;

    CLK		: in std_ulogic := 'X';
    GSR		: in std_ulogic := 'X';
    GTS		: in std_ulogic := 'X';
    USRCCLKO	: in std_ulogic := 'X';
    USRCCLKTS	: in std_ulogic := 'X';
    USRDONEO	: in std_ulogic := 'X';
    USRDONETS	: in std_ulogic := 'X'
    );

end STARTUP_VIRTEX4;

architecture STARTUP_VIRTEX4_V of STARTUP_VIRTEX4 is

begin
end STARTUP_VIRTEX4_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/usr_access_virtex4.vhd,v 1.5 2004/04/08 18:46:30 patrickp Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  
-- /___/   /\     Filename : USR_ACCESS_VIRTEX4.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:05 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL USR_ACCESS_VIRTEX4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity USR_ACCESS_VIRTEX4 is
  port(
    DATA	: out std_logic_vector(31 downto 0);
    DATAVALID	: out std_ulogic
    );

end USR_ACCESS_VIRTEX4;

architecture USR_ACCESS_VIRTEX4_V of USR_ACCESS_VIRTEX4 is

begin
end USR_ACCESS_VIRTEX4_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                  Dual Data Rate Input D Flip-Flop
-- /___/   /\     Filename : IDDR2.vhd
-- \   \  /  \    Timestamp : Fri Mar 26 08:18:20 PST 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL IDDR2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;


library unisim;
use unisim.vpkg.all;

entity IDDR2 is

  generic(

      DDR_ALIGNMENT : string := "NONE";
      INIT_Q0       : bit    := '0';
      INIT_Q1       : bit    := '0';
      SRTYPE        : string := "SYNC"
      );

  port(
      Q0          : out std_ulogic;
      Q1          : out std_ulogic;

      C0          : in  std_ulogic;
      C1          : in  std_ulogic;
      CE          : in  std_ulogic;
      D           : in  std_ulogic;
      R           : in  std_ulogic;
      S           : in  std_ulogic
    );

end IDDR2;

architecture IDDR2_V OF IDDR2 is


  constant SYNC_PATH_DELAY : time := 100 ps;

  signal C0_ipd	        : std_ulogic := 'X';
  signal C1_ipd	        : std_ulogic := 'X';
  signal CE_ipd	        : std_ulogic := 'X';
  signal D_ipd	        : std_ulogic := 'X';
  signal GSR            : std_ulogic := '0';
  signal GSR_ipd	: std_ulogic := 'X';
  signal R_ipd		: std_ulogic := 'X';
  signal S_ipd		: std_ulogic := 'X';

  signal C0_dly	        : std_ulogic := 'X';
  signal C1_dly	        : std_ulogic := 'X';
  signal CE_dly	        : std_ulogic := 'X';
  signal D_dly	        : std_ulogic := 'X';
  signal GSR_dly	: std_ulogic := 'X';
  signal R_dly		: std_ulogic := 'X';
  signal S_dly		: std_ulogic := 'X';

  signal Q0_zd	        : std_ulogic := 'X';
  signal Q1_zd	        : std_ulogic := 'X';

  signal Q0_viol        : std_ulogic := 'X';
  signal Q1_viol        : std_ulogic := 'X';

  signal q0_o_reg	: std_ulogic := 'X';
  signal q0_c1_o_reg	: std_ulogic := 'X';
  signal q1_o_reg	: std_ulogic := 'X';
  signal q1_c0_o_reg	: std_ulogic := 'X';

  signal ddr_alignment_type	: integer := -999;
  signal sr_type		: integer := -999;
  
begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  C0_dly         	 <= C0             	after 0 ps;
  C1_dly         	 <= C1             	after 0 ps;
  CE_dly         	 <= CE             	after 0 ps;
  D_dly          	 <= D              	after 0 ps;
  GSR_dly        	 <= GSR            	after 0 ps;
  R_dly          	 <= R              	after 0 ps;
  S_dly          	 <= S              	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process

  begin
      if((DDR_ALIGNMENT = "NONE") or (DDR_ALIGNMENT = "none")) then
         ddr_alignment_type <= 1;
      elsif((DDR_ALIGNMENT = "C0") or (DDR_ALIGNMENT = "c0")) then
         ddr_alignment_type <= 2;
      elsif((DDR_ALIGNMENT = "C1") or (DDR_ALIGNMENT = "c1")) then
         ddr_alignment_type <= 3;
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Error ",
             GenericName => " DDR_ALIGNMENT ",
             EntityName => "/IDDR2",
             GenericValue => DDR_ALIGNMENT,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " NONE or C0 or C1.",
             TailMsg => "",
             MsgSeverity => ERROR 
         );
      end if;

      if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
         sr_type <= 1;
      elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
         sr_type <= 2;
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Error ",
             GenericName => " SRTYPE ",
             EntityName => "/IDDR2",
             GenericValue => SRTYPE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " ASYNC or SYNC. ",
             TailMsg => "",
             MsgSeverity => ERROR
         );
      end if;

     wait;
  end process prcs_init;
--####################################################################
--#####                    functionality                         #####
--####################################################################
  prcs_func_reg:process(C0_dly, C1_dly, D_dly, GSR_dly, R_dly, S_dly)
  variable FIRST_TIME : boolean := true;
  variable q0_out_var : std_ulogic := TO_X01(INIT_Q0);
  variable q1_out_var : std_ulogic := TO_X01(INIT_Q1);
  variable q0_c1_out_var : std_ulogic := TO_X01(INIT_Q0);
  variable q1_c0_out_var : std_ulogic := TO_X01(INIT_Q1);
  begin
     if((GSR_dly = '1') or (FIRST_TIME)) then
       q0_out_var := TO_X01(INIT_Q0);
       q1_out_var := TO_X01(INIT_Q1);
       q0_c1_out_var := TO_X01(INIT_Q0);
       q1_c0_out_var := TO_X01(INIT_Q1);
       FIRST_TIME := false;
     else
        case sr_type is
           when 1 => 
                   if(R_dly = '1') then
                     q0_out_var := '0';
                     q1_out_var := '0';
                     q1_c0_out_var := '0';
                     q0_c1_out_var := '0';                     
                   elsif((R_dly = '0') and (S_dly = '1')) then
                     q0_out_var := '1';
                     q1_out_var := '1';
                     q1_c0_out_var := '1';
                     q0_c1_out_var := '1';
                   elsif((R_dly = '0') and (S_dly = '0')) then
                      if(CE_dly = '1') then
                         if(rising_edge(C0_dly)) then
                           q0_out_var := D_dly;
                           q1_c0_out_var := q1_out_var;
                         end if;
                         if(rising_edge(C1_dly)) then
                           q1_out_var := D_dly;
                           q0_c1_out_var := q0_out_var;
                         end if;
                      end if;
                   end if;

           when 2 => 
                   if(rising_edge(C0_dly)) then
                      if(R_dly = '1') then
                        q0_out_var := '0';
                        q1_c0_out_var := '0';
                      elsif((R_dly = '0') and (S_dly = '1')) then
                        q0_out_var := '1';
                        q1_c0_out_var := '1';
                      elsif((R_dly = '0') and (S_dly = '0')) then
                         if(CE_dly = '1') then
                           q0_out_var := D_dly;
                           q1_c0_out_var := q1_out_var;
                         end if;
                      end if;
                   end if;
                        
                   if(rising_edge(C1_dly)) then
                      if(R_dly = '1') then
                        q1_out_var := '0';
                        q0_c1_out_var := '0';
                      elsif((R_dly = '0') and (S_dly = '1')) then
                        q1_out_var := '1';
                        q0_c1_out_var := '1';
                      elsif((R_dly = '0') and (S_dly = '0')) then
                         if(CE_dly = '1') then
                           q1_out_var := D_dly;
                           q0_c1_out_var := q0_out_var;
                         end if;
                      end if;
                   end if;
 
           when others =>
                   null; 
        end case;
     end if;
         
     q0_o_reg <= q0_out_var;
     q1_o_reg <= q1_out_var;
     q0_c1_o_reg <= q0_c1_out_var;
     q1_c0_o_reg <= q1_c0_out_var;

  end process prcs_func_reg;
--####################################################################
--#####                        output mux                        #####
--####################################################################
  prcs_output_mux:process(q0_o_reg, q1_o_reg, q0_c1_o_reg, q1_c0_o_reg)
  begin
     case ddr_alignment_type is
       when 1 => 
                 Q0_zd <= q0_o_reg;
                 Q1_zd <= q1_o_reg;
       when 2 => 
                 Q0_zd <= q0_o_reg;
                 Q1_zd <= q1_c0_o_reg;
       when 3 => 
                 Q0_zd <= q0_c1_o_reg;
                 Q1_zd <= q1_o_reg;
       when others =>
                 null;
     end case;
  end process prcs_output_mux;
--####################################################################

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(Q0_zd, Q1_zd)
  begin
      Q0 <= Q0_zd after SYNC_PATH_DELAY;
      Q1 <= Q1_zd after SYNC_PATH_DELAY;
  end process prcs_output;
--####################################################################


end IDDR2_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                  18X18 Signed Multiplier 
-- /___/   /\     Filename : MULT18X18SIO.vhd
-- \   \  /  \    Timestamp : Fri Mar 26 08:18:19 PST 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    07/25/05 - Added CLK_dly to the sensitivity list
--    08/29/05 - Added rest of the signals to the sensitivity list to avoid false
--             - Setup/Hold violations at initial stages
-- End Revision

----- CELL MULT18X18SIO -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_SIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;


library unisim;
use unisim.vpkg.all;

entity MULT18X18SIO is

  generic (

	AREG            : integer       := 1;
	BREG            : integer       := 1;
	B_INPUT         : string        := "DIRECT";

	PREG            : integer       := 1
        );

  port (
	BCOUT	: out std_logic_vector (17 downto 0);
	P	: out std_logic_vector (35 downto 0);

	A	: in  std_logic_vector (17 downto 0);
	B	: in  std_logic_vector (17 downto 0);
	BCIN	: in  std_logic_vector (17 downto 0);
	CEA	: in  std_ulogic;
	CEB	: in  std_ulogic;
	CEP	: in  std_ulogic;
	CLK	: in  std_ulogic;
	RSTA	: in  std_ulogic;
	RSTB	: in  std_ulogic;
	RSTP	: in  std_ulogic
	);

end MULT18X18SIO;


architecture MULT18X18SIO_V of MULT18X18SIO is

  constant MAX_P          : integer    := 36;
  constant MAX_BCOUT      : integer    := 36;
  constant MAX_BCIN       : integer    := 18;
  constant MAX_B          : integer    := 18;
  constant MAX_A          : integer    := 18;

  constant MSB_P          : integer    := 35;
  constant MSB_BCOUT      : integer    := 17;
  constant MSB_BCIN       : integer    := 17;
  constant MSB_B          : integer    := 17;
  constant MSB_A          : integer    := 17;

  signal A_ipd    : std_logic_vector(MSB_A downto 0) := (others => '0' );
  signal B_ipd    : std_logic_vector(MSB_B downto 0) := (others => '0' );
  signal BCIN_ipd : std_logic_vector(MSB_BCIN downto 0) := (others => '0' );
  signal CEA_ipd  : std_ulogic := 'X';
  signal CEB_ipd  : std_ulogic := 'X';
  signal CEP_ipd  : std_ulogic := 'X';
  signal CLK_ipd  : std_ulogic := 'X';
  signal GSR            : std_ulogic := '0';
  signal GSR_ipd  : std_ulogic := 'X';
  signal RSTA_ipd : std_ulogic := 'X';
  signal RSTB_ipd : std_ulogic := 'X';
  signal RSTP_ipd : std_ulogic := 'X';

  signal A_dly    : std_logic_vector(MSB_A downto 0) := (others => '0' );
  signal B_dly    : std_logic_vector(MSB_B downto 0) := (others => '0' );
  signal BCIN_dly : std_logic_vector(MSB_BCIN downto 0) := (others => '0' );
  signal CEA_dly  : std_ulogic := 'X';
  signal CEB_dly  : std_ulogic := 'X';
  signal CEP_dly  : std_ulogic := 'X';
  signal CLK_dly  : std_ulogic := 'X';
  signal GSR_dly  : std_ulogic := 'X';
  signal RSTA_dly : std_ulogic := 'X';
  signal RSTB_dly : std_ulogic := 'X';
  signal RSTP_dly : std_ulogic := 'X';


  --- Internal Signal Declarations

  signal qa_o_reg1 : std_logic_vector(MSB_A downto 0) := (others => '0');
  signal qa_o_mux  : std_logic_vector(MSB_A downto 0) := (others => '0');

  signal b_o_mux   : std_logic_vector(MSB_B downto 0) := (others => '0');
  signal qb_o_reg1 : std_logic_vector(MSB_B downto 0) := (others => '0');
  signal qb_o_mux  : std_logic_vector(MSB_B downto 0) := (others => '0');

  signal mult_o_int : std_logic_vector((MSB_A + MSB_B + 1) downto 0) := (others => '0');

  signal qp_o_reg : std_logic_vector(MSB_P downto 0) := (others => '0');
  signal qp_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0');

  signal BCOUT_zd : std_logic_vector(MSB_BCOUT downto 0) := (others => '0');
  signal P_zd : std_logic_vector(MSB_P downto 0) := (others => '0');

begin

  A_dly          	 <= A              	after 0 ps;
  B_dly          	 <= B              	after 0 ps;
  BCIN_dly       	 <= BCIN           	after 0 ps;
  CEA_dly        	 <= CEA            	after 0 ps;
  CEB_dly        	 <= CEB            	after 0 ps;
  CEP_dly        	 <= CEP            	after 0 ps;
  CLK_dly        	 <= CLK            	after 0 ps;
  RSTA_dly       	 <= RSTA           	after 0 ps;
  RSTB_dly       	 <= RSTB           	after 0 ps;
  RSTP_dly       	 <= RSTP           	after 0 ps;
  GSR_dly                <= GSR                 after 0 ps;


--####################################################################
--#####    Input Register A with 1 level of registers and a mux  #####
--####################################################################
  prcs_qa_1lvl:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
          qa_o_reg1 <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTA_dly = '1') then
               qa_o_reg1 <= ( others => '0');
            elsif ((RSTA_dly = '0') and  (CEA_dly = '1')) then
               qa_o_reg1 <= A_dly;
            end if;
         end if;
      end if;
  end process prcs_qa_1lvl;

----------------------------------------------------------------------

  prcs_qa_o_mux:process(A_dly, qa_o_reg1)
  begin
     case AREG is
       when 0 => qa_o_mux <= A_dly;
       when 1 => qa_o_mux <= qa_o_reg1;
       when others =>
            assert false
            report "Attribute Syntax Error: The allowed values for AREG are 0 or 1"
            severity Failure;
     end case;
  end process prcs_qa_o_mux;

--####################################################################
--#####    Input Register B with two levels of registers and a mux ###
--####################################################################
  prcs_b_in:process(B_dly, BCIN_dly)
  begin
     if(B_INPUT ="DIRECT") then
        b_o_mux <= B_dly;
     elsif(B_INPUT ="CASCADE") then
        b_o_mux <= BCIN_dly;
     else
        assert false
        report "Attribute Syntax Error: The allowed values for B_INPUT are DIRECT or CASCADE."
        severity Failure;
     end if;
  end process prcs_b_in;
------------------------------------------------------------------
 prcs_qb_1lvl:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
          qb_o_reg1 <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTB_dly = '1') then
               qb_o_reg1 <= ( others => '0');
            elsif ((RSTB_dly = '0') and  (CEB_dly = '1')) then
               qb_o_reg1 <= b_o_mux;
            end if;
         end if;
      end if;
  end process prcs_qb_1lvl;
------------------------------------------------------------------
  prcs_qb_o_mux:process(b_o_mux, qb_o_reg1)
  begin
     case BREG is
       when 0 => qb_o_mux <= b_o_mux;
       when 1 => qb_o_mux <= qb_o_reg1;
       when others =>
            assert false
            report "Attribute Syntax Error: The allowed values for BREG are 0 or 1 "
            severity Failure;
     end case;

  end process prcs_qb_o_mux;
--####################################################################
--#####                     Multiply                             #####
--####################################################################
  prcs_mult:process(qa_o_mux, qb_o_mux)
  begin
     mult_o_int <=  qa_o_mux * qb_o_mux;
  end process prcs_mult;
--####################################################################
--#####                    Output  P                             #####
--####################################################################
  prcs_qp_reg:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         qp_o_reg <=  ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTP_dly = '1') then
               qp_o_reg <= ( others => '0');
            elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then
               qp_o_reg <= mult_o_int;
            end if;
         end if;
      end if;
  end process prcs_qp_reg;
------------------------------------------------------------------
  prcs_qp_mux:process(mult_o_int, qp_o_reg)
  begin
     case PREG is
       when 0 => qp_o_mux <= mult_o_int;
       when 1 => qp_o_mux <= qp_o_reg;
       when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for PREG are 0 or 1"
           severity Failure;
     end case;

  end process prcs_qp_mux;
--####################################################################
--#####                   ZERO_DELAY_OUTPUTS                     #####
--####################################################################
  prcs_zero_delay_outputs:process(qb_o_mux, qp_o_mux)
  begin
    BCOUT_zd <= qb_o_mux;
    P_zd     <= qp_o_mux;
  end process prcs_zero_delay_outputs;


--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_outputs:process(BCOUT_zd, P_zd)
  begin
    BCOUT <= BCOUT_zd;
    P     <= P_zd;
  end process prcs_outputs;

end MULT18X18SIO_V ;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                  Dual Data Rate Output D Flip-Flop
-- /___/   /\     Filename : ODDR2.vhd
-- \   \  /  \    Timestamp : Fri Mar 26 08:18:20 PST 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL ODDR2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;


library unisim;
use unisim.vpkg.all;

entity ODDR2 is

  generic(

      DDR_ALIGNMENT : string := "NONE";
      INIT          : bit    := '0';
      SRTYPE        : string := "SYNC"
      );

  port(
      Q           : out std_ulogic;

      C0          : in  std_ulogic;
      C1          : in  std_ulogic;
      CE          : in  std_ulogic;
      D0          : in  std_ulogic;
      D1          : in  std_ulogic;
      R           : in  std_ulogic;
      S           : in  std_ulogic
    );

end ODDR2;

architecture ODDR2_V OF ODDR2 is


  constant SYNC_PATH_DELAY : time := 100 ps;

  signal C0_ipd	        : std_ulogic := 'X';
  signal C1_ipd	        : std_ulogic := 'X';
  signal CE_ipd	        : std_ulogic := 'X';
  signal D0_ipd	        : std_ulogic := 'X';
  signal D1_ipd	        : std_ulogic := 'X';
  signal GSR            : std_ulogic := '0';
  signal GSR_ipd	: std_ulogic := 'X';
  signal R_ipd		: std_ulogic := 'X';
  signal S_ipd		: std_ulogic := 'X';

  signal C0_dly	        : std_ulogic := 'X';
  signal C1_dly	        : std_ulogic := 'X';
  signal CE_dly	        : std_ulogic := 'X';
  signal D0_dly	        : std_ulogic := 'X';
  signal D1_dly	        : std_ulogic := 'X';
  signal GSR_dly	: std_ulogic := 'X';
  signal R_dly		: std_ulogic := 'X';
  signal S_dly		: std_ulogic := 'X';

  signal Q_zd		: std_ulogic := 'X';

  signal Q_viol		: std_ulogic := 'X';

  signal ddr_alignment_type	: integer := -999;
  signal sr_type		: integer := -999;

begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  C0_dly         	 <= C0             	after 0 ps;
  C1_dly         	 <= C1             	after 0 ps;
  CE_dly         	 <= CE             	after 0 ps;
  D0_dly         	 <= D0             	after 0 ps;
  D1_dly         	 <= D1             	after 0 ps;
  GSR_dly        	 <= GSR            	after 0 ps;
  R_dly          	 <= R              	after 0 ps;
  S_dly          	 <= S              	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process

  begin
      if((DDR_ALIGNMENT = "NONE") or (DDR_ALIGNMENT = "none")) then
         ddr_alignment_type <= 1;
      elsif((DDR_ALIGNMENT = "C0") or (DDR_ALIGNMENT = "c0")) then
         ddr_alignment_type <= 2;
      elsif((DDR_ALIGNMENT = "C1") or (DDR_ALIGNMENT = "c1")) then
         ddr_alignment_type <= 3;
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Error :",
             GenericName => " DDR_ALIGNMENT ",
             EntityName => "/ODDR2",
             GenericValue => DDR_ALIGNMENT,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " NONE, C0 or C1.",
             TailMsg => "",
             MsgSeverity => failure
         );
      end if;

      if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
         sr_type <= 1;
      elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
         sr_type <= 2;
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Error :",
             GenericName => " SRTYPE ",
             EntityName => "/ODDR2",
             GenericValue => SRTYPE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " ASYNC or SYNC. ",
             TailMsg => "",
             MsgSeverity => failure
         );
      end if;

     wait;
  end process prcs_init;
--####################################################################
--#####                      functionality                       #####
--####################################################################
  prcs_func_reg:process(C0_dly, C1_dly, GSR_dly, R_dly, S_dly)
    variable FIRST_TIME : boolean := true;
    variable q_var         : std_ulogic := TO_X01(INIT);
    variable q_d0_c1_out_var : std_ulogic := TO_X01(INIT);
    variable q_d1_c0_out_var : std_ulogic := TO_X01(INIT);
  begin
     if((GSR_dly = '1') or (FIRST_TIME)) then
         q_var         := TO_X01(INIT);
         q_d0_c1_out_var := TO_X01(INIT);
         q_d1_c0_out_var := TO_X01(INIT);
         FIRST_TIME := false;
     else
        case sr_type is
           when 1 => 
                   if(R_dly = '1') then
                      q_var := '0';
                      q_d0_c1_out_var := '0';
                      q_d1_c0_out_var := '0';
                   elsif((R_dly = '0') and (S_dly = '1')) then
                      q_var := '1';
                      q_d0_c1_out_var := '1';
                      q_d1_c0_out_var := '1';
                   elsif((R_dly = '0') and (S_dly = '0')) then
                      if(CE_dly = '1') then
                         if(rising_edge(C0_dly)) then
                           if(ddr_alignment_type = 3) then
                             q_var := q_d0_c1_out_var;
                           else
                             q_var := D0_dly;
                             if(ddr_alignment_type = 2) then
                               q_d1_c0_out_var := D1_dly;
                             end if;
                           end if;
                         end if;
                         if(rising_edge(C1_dly)) then
                           if(ddr_alignment_type = 2) then
                             q_var := q_d1_c0_out_var;
                           else
                             q_var := D1_dly;
                             if(ddr_alignment_type = 3) then
                               q_d0_c1_out_var := D0_dly;
                             end if;
                           end if;
                         end if;
                      end if;
                   end if;

           when 2 => 
                   if(rising_edge(C0_dly)) then
                      if(R_dly = '1') then
                         q_var := '0';
                         q_d1_c0_out_var := '0';
                      elsif((R_dly = '0') and (S_dly = '1')) then
                         q_var := '1';
                         q_d1_c0_out_var := '1';
                      elsif((R_dly = '0') and (S_dly = '0')) then
                         if(CE_dly = '1') then
                           if(ddr_alignment_type = 3) then
                             q_var := q_d0_c1_out_var;
                           else
                             q_var := D0_dly;
                             if(ddr_alignment_type = 2) then
                               q_d1_c0_out_var := D1_dly;
                             end if;
                           end if;
                         end if;
                      end if;
                   end if;
                        
                   if(rising_edge(C1_dly)) then
                      if(R_dly = '1') then
                         q_var := '0';
                         q_d0_c1_out_var := '0';
                      elsif((R_dly = '0') and (S_dly = '1')) then
                         q_var := '1';
                         q_d0_c1_out_var := '1';
                      elsif((R_dly = '0') and (S_dly = '0')) then
                         if(CE_dly = '1') then
                           if(ddr_alignment_type = 2) then
                             q_var := q_d1_c0_out_var;
                           else
                             q_var := D1_dly;
                             if(ddr_alignment_type = 3) then
                               q_d0_c1_out_var := D0_dly;
                             end if;
                           end if;
                         end if;
                      end if;
                   end if;
 
           when others =>
                   null; 
        end case;
     end if;

     Q_zd <= q_var;

  end process prcs_func_reg;
--####################################################################

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(Q_zd)
  begin
      Q <= Q_zd after SYNC_PATH_DELAY;
  end process prcs_output;
--####################################################################


end ODDR2_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/spartan4/VITAL/Attic/startup_spartan3e.vhd,v 1.4 2004/09/10 06:25:13 fphillip Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  User Interface to Global Clock, Reset and 3-State Controls for SPARTAN3E
-- /___/   /\     Filename : STARTUP_SPARTAN3E.vhd
-- \   \  /  \    Timestamp : Tue Jul  27 21:56:59 PDT 2004
--  \___\/\___\
--
-- Revision:
--    07/27/04 - Initial version.

----- CELL STARTUP_SPARTAN3E -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity STARTUP_SPARTAN3E is
  port(
    CLK : in std_ulogic := 'X';
    GSR : in std_ulogic := 'X';
    GTS : in std_ulogic := 'X';
    MBT : in std_ulogic := 'X'
    );
end STARTUP_SPARTAN3E;

architecture STARTUP_SPARTAN3E_V of STARTUP_SPARTAN3E is
constant MINIMUM_PULSE_LOW : time := 300 ns;
begin
   prcs_mbt:process(MBT)
   variable disable_mbt : boolean := false;
   variable init_time, min_time : time := 0 ps;
   begin
       if(not disable_mbt) then
          if(MBT = '0') then
             if(now /= 0 ns ) then
                init_time := now;
             end if;
          elsif(MBT = '1') then
             min_time := now - init_time;
             if(min_time >= MINIMUM_PULSE_LOW) then
                assert false
                report "Soft Boot has been initiated."
                severity note;
                
                disable_mbt := true;
             end if;
          end if;
       end if;   -- if (not disable_mbt)
   end process prcs_mbt; 
end STARTUP_SPARTAN3E_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/afifo36_internal.vhd,v 1.16.6.1 2008/04/28 22:33:55 wloo Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2005 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : This is not an user primitive.
--  /   /                  Xilinx Functional Simulation Library Component 36K-Bit FIFO
-- /___/   /\     Filename : AFIFO36_INTERNAL.vhd
-- \   \  /  \    Timestamp : Tues October 18 08:18:20 PST 2005
--  \___\/\___\
--
-- Revision:
--    10/18/05 - Initial version.
--    06/13/06 - Fixed out of range error (CR 232285). Fixed almostfull flag in
--               sync mode (CR 232931).
--    10/16/06 - Fixed the unused bits of wrcount and rdcount to match the hardware (CR 426347).
--    11/15/06 - Fixed SBITERR and DBITERR in synchronous mode (CR 429311).
--    11/20/06 - Fixed WRCOUNT and RDCOUNT (CR 429310).
--    01/24/07 - Removed DRC warning for RST in ECC mode (CR 432367).
--    06/14/07 - Implemented high performace version of the model.
--    10/26/07 - Changed wren_dly to wren_var to fix FULL flag (CR 452554).
--    04/28/08 - Fixed sbiterr and dbiterr outputs deassertion (CR 470460).
-- End Revision
  
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;

library STD;
use STD.TEXTIO.ALL;

library unisim;
use unisim.vpkg.all;
use unisim.vcomponents.all;

entity AFIFO36_INTERNAL is

  generic(

    ALMOST_FULL_OFFSET      : bit_vector := X"0080";
    ALMOST_EMPTY_OFFSET     : bit_vector := X"0080"; 
    DATA_WIDTH              : integer    := 4;
    DO_REG                  : integer    := 1;
    EN_ECC_READ             : boolean    := FALSE;
    EN_ECC_WRITE            : boolean    := FALSE;    
    EN_SYN                  : boolean    := FALSE;
    FIFO_SIZE               : integer    := 36;
    FIRST_WORD_FALL_THROUGH : boolean    := FALSE;
    SIM_MODE                : string     := "SAFE"
    );

  port(
    ALMOSTEMPTY : out std_ulogic;
    ALMOSTFULL  : out std_ulogic;
    DBITERR       : out std_ulogic;
    DO          : out std_logic_vector (63 downto 0);
    DOP         : out std_logic_vector (7 downto 0);
    ECCPARITY   : out std_logic_vector (7 downto 0);
    EMPTY       : out std_ulogic;
    FULL        : out std_ulogic;
    RDCOUNT     : out std_logic_vector (12 downto 0);
    RDERR       : out std_ulogic;
    SBITERR     : out std_ulogic;
    WRCOUNT     : out std_logic_vector (12 downto 0);
    WRERR       : out std_ulogic;

    DI          : in  std_logic_vector (63 downto 0);
    DIP         : in  std_logic_vector (7 downto 0);
    RDCLK       : in  std_ulogic;
    RDRCLK      : in  std_ulogic;
    RDEN        : in  std_ulogic;
    RST         : in  std_ulogic;
    WRCLK       : in  std_ulogic;
    WREN        : in  std_ulogic
    );

end AFIFO36_INTERNAL;

-- architecture body                    --

architecture AFIFO36_INTERNAL_V of AFIFO36_INTERNAL is


  function GetMemoryDepth (
    rdwr_width : in integer;
    func_fifo_size : in integer
    ) return integer is
    variable func_mem_depth : integer;
  begin
    case rdwr_width is
      when 4 => if (func_fifo_size = 18) then
                  func_mem_depth := 4096;
                else
                  func_mem_depth := 8192;
                end if;
      when 9 => if (func_fifo_size = 18) then
                  func_mem_depth := 2048;
                else
                  func_mem_depth := 4096;
                end if;
      when 18 => if (func_fifo_size = 18) then
                   func_mem_depth := 1024;
                 else
                   func_mem_depth := 2048;
                 end if;
      when 36 => if (func_fifo_size = 18) then
                   func_mem_depth := 512;
                 else
                   func_mem_depth := 1024;
                 end if;
      when 72 => if (func_fifo_size = 18) then
                   func_mem_depth := 0;
                 else
                   func_mem_depth := 512;
                 end if;
      when others => func_mem_depth := 8192;
    end case;
    return func_mem_depth;
  end;

  function GetMemoryDepthP (
    rdwr_width : in integer;
    func_fifo_size : in integer
    ) return integer is
    variable func_memp_depth : integer;
  begin
    case rdwr_width is
      when 9 => if (func_fifo_size = 18) then
                  func_memp_depth := 2048;
                else
                  func_memp_depth := 4096;
                end if;
      when 18 => if (func_fifo_size = 18) then
                   func_memp_depth := 1024;
                 else
                   func_memp_depth := 2048;
                 end if;
      when 36 => if (func_fifo_size = 18) then
                   func_memp_depth := 512;
                 else
                   func_memp_depth := 1024;
                 end if;
      when 72 => if (func_fifo_size = 18) then
                   func_memp_depth := 0;
                 else
                   func_memp_depth := 512;
                 end if;
      when others => func_memp_depth := 8192;
    end case;
    return func_memp_depth;
  end;

  
  function GetWidth (
    rdwr_width : in integer
    ) return integer is
    variable func_width : integer;
  begin
    case rdwr_width is
      when 4 => func_width := 4;
      when 9 => func_width := 8;
      when 18 => func_width := 16;
      when 36 => func_width := 32;
      when 72 => func_width := 64;
      when others => func_width := 64;
    end case;
    return func_width;
  end;

  
  function GetWidthp (
    rdwr_widthp : in integer
    ) return integer is
    variable func_widthp : integer;
  begin
    case rdwr_widthp is
      when 9 => func_widthp := 1;
      when 18 => func_widthp := 2;
      when 36 => func_widthp := 4;
      when 72 => func_widthp := 8;
      when others => func_widthp := 8;
    end case;
    return func_widthp;
  end;
    
    constant MAX_DO      : integer    := 64;
    constant MAX_DOP     : integer    := 8;
    constant MAX_RDCOUNT : integer    := 13;
    constant MAX_WRCOUNT : integer    := 13;
    constant MSB_MAX_DO  : integer    := 63;
    constant MSB_MAX_DOP : integer    := 7;
    constant MSB_MAX_RDCOUNT : integer    := 12;
    constant MSB_MAX_WRCOUNT : integer    := 12;

    constant MAX_DI      : integer    := 64;
    constant MAX_DIP     : integer    := 8;
    constant MSB_MAX_DI  : integer    := 63;
    constant MSB_MAX_DIP : integer    := 7;

    constant MAX_LATENCY_EMPTY : integer := 3;
    constant MAX_LATENCY_FULL  : integer := 3;
  
    constant mem_depth : integer := GetMemoryDepth(DATA_WIDTH, FIFO_SIZE);
    constant memp_depth : integer := GetMemoryDepthP(DATA_WIDTH, FIFO_SIZE);
    constant mem_width : integer := GetWidth(DATA_WIDTH);
    constant memp_width : integer := GetWidthp(DATA_WIDTH); 

    type Two_D_array_type is array ((mem_depth -  1) downto 0) of std_logic_vector((mem_width - 1) downto 0);
    type Two_D_parity_array_type is array ((memp_depth - 1) downto 0) of std_logic_vector((memp_width -1) downto 0);
  
    signal mem : Two_D_array_type;
    signal memp : Two_D_parity_array_type;

    signal DI_ipd    : std_logic_vector(MSB_MAX_DI downto 0)    := (others => 'X');
    signal DIP_ipd   : std_logic_vector(MSB_MAX_DIP downto 0)   := (others => 'X');
    signal GSR_ipd   : std_ulogic     :=    'X';
    signal RDCLK_ipd : std_ulogic     :=    'X';
    signal RDEN_ipd  : std_ulogic     :=    'X';
    signal RST_ipd   : std_ulogic     :=    'X';
    signal WRCLK_ipd : std_ulogic     :=    'X';
    signal WREN_ipd  : std_ulogic     :=    'X';

    signal DI_dly    : std_logic_vector(MSB_MAX_DI downto 0)    := (others => 'X');
    signal DIP_dly   : std_logic_vector(MSB_MAX_DIP downto 0)   := (others => 'X');
    signal GSR_dly   : std_ulogic;
    signal RDCLK_dly : std_ulogic     :=    'X';
    signal RDEN_dly  : std_ulogic     :=    'X';
    signal RST_dly   : std_ulogic     :=    'X';
    signal WRCLK_dly : std_ulogic     :=    'X';
    signal WREN_dly  : std_ulogic     :=    'X';

    signal DO_zd          : std_logic_vector(MSB_MAX_DO  downto 0)    := (others => '0');
    signal DOP_zd         : std_logic_vector(MSB_MAX_DOP downto 0)    := (others => '0');
    signal ALMOSTEMPTY_zd : std_logic     :=    '1';
    signal ALMOSTFULL_zd  : std_logic     :=    '0';
    signal EMPTY_zd       : std_logic     :=    '1';
    signal FULL_zd        : std_logic     :=    '0';
    signal RDCOUNT_zd     : std_logic_vector(MSB_MAX_RDCOUNT  downto 0)    := (others => '0');
    signal RDERR_zd       : std_logic     :=    '0';
    signal WRCOUNT_zd     : std_logic_vector(MSB_MAX_WRCOUNT  downto 0)    := (others => '0');
    signal WRERR_zd       : std_logic     :=    '0';
    signal RDCOUNT_OUT_zd : std_logic_vector(MSB_MAX_RDCOUNT  downto 0)    := (others => '1');
    signal WRCOUNT_OUT_zd : std_logic_vector(MSB_MAX_WRCOUNT  downto 0)    := (others => '1');
    signal DO_OUT_zd      : std_logic_vector(MSB_MAX_DO  downto 0)         := (others => 'X');
    signal DOP_OUT_zd     : std_logic_vector(MSB_MAX_DOP  downto 0)        := (others => 'X');
    signal DO_OUTREG_zd          : std_logic_vector(MSB_MAX_DO  downto 0)    := (others => '0');
    signal DOP_OUTREG_zd         : std_logic_vector(MSB_MAX_DOP downto 0)    := (others => '0');
    signal DO_OUT_MUX_zd         : std_logic_vector(MSB_MAX_DO  downto 0)    := (others => '0');
    signal DOP_OUT_MUX_zd        : std_logic_vector(MSB_MAX_DOP downto 0)    := (others => '0');

  --- Internal Signal Declarations

    signal RST_META    : std_ulogic := '0';

    signal DefDelay    : time := 10 ps;

    signal addr_limit    : integer := 0;
    signal addr_limit_fast    : integer := 0;
    signal wr_addr       : integer := 0;
    signal wr_addr_fast       : integer := 0;
    signal rd_addr       : integer := 0;
    signal rd_addr_fast       : integer := 0;
    signal rd_addr_range : integer := 0;
    signal wr_addr_range : integer := 0;

    signal rd_flag       : std_logic := '0';
    signal wr_flag       : std_logic := '0';
    signal awr_flag      : std_logic := '0';

    signal rdcount_flag  : std_logic := '0';

    signal almostempty_limit : real := 0.0;
    signal almostfull_limit  : real := 0.0;

    signal violation : std_ulogic := '0'; 

    signal fwft      : std_logic := 'X';

    signal update_from_write_prcs      : std_logic := '0';
    signal update_from_read_prcs       : std_logic := '0';
    signal update_from_write_prcs_sync : std_logic := '0';
    signal update_from_read_prcs_sync  : std_logic := '0';
  
    signal ae_empty   : integer := 0;
    signal ae_full    : integer := 0;
    signal ae_empty_fast   : integer := 0;
    signal ae_full_fast    : integer := 0;

-- CR 182616 fix
   signal rst_rdckreg : std_logic_vector (2 downto 0) := (others => '0');
   signal rst_wrckreg : std_logic_vector (2 downto 0) := (others => '0');
   signal sync : std_logic := 'X';
   signal sbiterr_zd : std_logic := '0';
   signal dbiterr_zd : std_logic := '0';
--   signal sbiterr_out_out : std_ulogic := '0';
--   signal dbiterr_out_out : std_ulogic := '0';
   signal ECCPARITY_zd : std_logic_vector(MSB_MAX_DOP downto 0) := (others => 'X');
   signal rst_rdclk_flag : std_logic := '0';
   signal rst_wrclk_flag : std_logic := '0';
  
begin

  ---------------------
  --  INPUT PATH DELAYs
  ---------------------

  DI_dly         	 <= DI             	after 0 ps;
  DIP_dly        	 <= DIP            	after 0 ps;
  GSR_dly        	 <= GSR            	after 0 ps;
  RDCLK_dly      	 <= RDCLK          	after 0 ps;
  RDEN_dly       	 <= RDEN           	after 0 ps;
  RST_dly        	 <= RST            	after 0 ps;
  WRCLK_dly      	 <= WRCLK          	after 0 ps;
  WREN_dly       	 <= WREN           	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

  ---------------------------------------------------------------------------
  -- SAFE mode
  ---------------------------------------------------------------------------

  safe_mode : if (SIM_MODE = "SAFE") generate
    
--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_initialize:process
  variable first_time        : boolean    := true;
  variable addr_limit_var    : integer    := 0; 
  variable fwft_var          : std_ulogic := 'X';
  variable rd_offset_stdlogic : std_logic_vector (ALMOST_EMPTY_OFFSET'length-1 downto 0);
  variable rd_offset_int : integer := 0;
  variable wr_offset_stdlogic : std_logic_vector (ALMOST_FULL_OFFSET'length-1 downto 0);
  variable wr_offset_int : integer := 0;
  variable Message : LINE;
  variable ae_empty_var      : integer := 0;
  variable ae_full_var       : integer := 0;
  
  begin
     if (first_time) then

       if (SIM_MODE /= "FAST" and SIM_MODE /= "SAFE") then
        GenericValueCheckMessage
          ( HeaderMsg            => " Attribute Syntax Error : ",
            GenericName          => " SIM_MODE ",
            EntityName           => "AFIFO36_INTERNAL",
            GenericValue         => SIM_MODE,
            Unit                 => "",
            ExpectedValueMsg     => " The Legal values for this attribute are ",
            ExpectedGenericValue => " FAST or SAFE ",
            TailMsg              => "",
            MsgSeverity          => failure
            );
       end if;

      
       case EN_SYN is
            when TRUE  => sync <= '1';
            when FALSE => sync <= '0';
            when others =>
                    GenericValueCheckMessage
                      ( HeaderMsg            => " Attribute Syntax Error ",
                        GenericName          => " EN_SYN ",
                        EntityName           => "AFIFO36_INTERNAL",
                        GenericValue         => EN_SYN,
                        Unit                 => "",
                        ExpectedValueMsg     => " The Legal values for this attribute are ",
                        ExpectedGenericValue => " TRUE or FALSE ",
                        TailMsg              => "",
                        MsgSeverity          => failure
                        );
       end case;

       
       case DATA_WIDTH is
            when 4  => if (FIFO_SIZE = 36) then
                         addr_limit_var := 8192;
                       else                         
                         addr_limit_var := 4096;
                       end if;     
            when 9  => if (FIFO_SIZE = 36) then
                         addr_limit_var := 4096;
                       else                         
                         addr_limit_var := 2048;
                       end if;
            when 18 => if (FIFO_SIZE = 36) then
                         addr_limit_var := 2048;
                       else                         
                         addr_limit_var := 1024;
                       end if;
            when 36 => if (FIFO_SIZE = 36) then
                         addr_limit_var := 1024;
                       else                         
                         addr_limit_var := 512;
                       end if;
            when 72 =>
                       addr_limit_var := 512;

            when others =>
                    GenericValueCheckMessage
                      ( HeaderMsg            => " Attribute Syntax Error ",
                        GenericName          => " DATA_WIDTH ",
                        EntityName           => "AFIFO36_INTERNAL",
                        GenericValue         => DATA_WIDTH,
                        Unit                 => "",
                        ExpectedValueMsg     => " The Legal values for this attribute are ",
                        ExpectedGenericValue => " 4, 9, 18, 36 and 72 ",
                        TailMsg              => "",
                        MsgSeverity          => failure
                        );
       end case;

       rd_offset_stdlogic := To_StdLogicVector(ALMOST_EMPTY_OFFSET);
       rd_offset_int := SLV_TO_INT(rd_offset_stdlogic);

       wr_offset_stdlogic := To_StdLogicVector(ALMOST_FULL_OFFSET);
       wr_offset_int := SLV_TO_INT(wr_offset_stdlogic);

       case FIRST_WORD_FALL_THROUGH is
            when TRUE  =>
                         fwft_var     := '1';
                         ae_empty_var := rd_offset_int - 2;
                         ae_full_var := wr_offset_int;
            when FALSE =>
                         fwft_var     := '0';
                         if (EN_SYN = FALSE) then
                           ae_empty_var := rd_offset_int - 1;
                           ae_full_var := wr_offset_int;
                         else
                           ae_empty_var := rd_offset_int;
                           ae_full_var := wr_offset_int;
                         end if;
         when others =>
                    GenericValueCheckMessage
                      ( HeaderMsg            => " Attribute Syntax Error ",
                        GenericName          => " FIRST_WORD_FALL_THROUGH ",
                        EntityName           => "AFIFO36_INTERNAL",
                        GenericValue         => FIRST_WORD_FALL_THROUGH,
                        Unit                 => "",
                        ExpectedValueMsg     => " The Legal values for this attribute are ",
                        ExpectedGenericValue => " true or false ",
                        TailMsg              => "",
                        MsgSeverity          => failure
                        );
       end case;

       
       if (EN_SYN = FALSE) then

         if (fwft_var = '0') then
           
           if ((rd_offset_int < 5) or (rd_offset_int > addr_limit_var - 5)) then
             write( Message, STRING'("Attribute Syntax Error : ") );
             write( Message, STRING'("The attribute ") );
             write( Message, STRING'("ALMOST_EMPTY_OFFSET on AFIFO36_INTERNAL is set to ") );
             write( Message, rd_offset_int);
             write( Message, STRING'(". Legal values for this attribute are ") );
             write( Message, 5);
             write( Message, STRING'(" to ") );
             write( Message, addr_limit_var - 5 );
             ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
             DEALLOCATE (Message);
           end if;
 
           if ((wr_offset_int < 4) or (wr_offset_int > addr_limit_var - 5)) then
             write( Message, STRING'("Attribute Syntax Error : ") );
             write( Message, STRING'("The attribute ") );
             write( Message, STRING'("ALMOST_FULL_OFFSET on AFIFO36_INTERNAL is set to ") );
             write( Message, wr_offset_int);
             write( Message, STRING'(". Legal values for this attribute are ") );
             write( Message, 4);
             write( Message, STRING'(" to ") );
             write( Message, addr_limit_var - 5 );
             ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
             DEALLOCATE (Message);
           end if;

         else
           
           if ((rd_offset_int < 6) or (rd_offset_int > addr_limit_var - 4)) then
             write( Message, STRING'("Attribute Syntax Error : ") );
             write( Message, STRING'("The attribute ") );
             write( Message, STRING'("ALMOST_EMPTY_OFFSET on AFIFO36_INTERNAL is set to ") );
             write( Message, rd_offset_int);
             write( Message, STRING'(". Legal values for this attribute are ") );
             write( Message, 6);
             write( Message, STRING'(" to ") );
             write( Message, addr_limit_var - 4 );
             ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
             DEALLOCATE (Message);
           end if;
 
           if ((wr_offset_int < 4) or (wr_offset_int > addr_limit_var - 5)) then
             write( Message, STRING'("Attribute Syntax Error : ") );
             write( Message, STRING'("The attribute ") );
             write( Message, STRING'("ALMOST_FULL_OFFSET on AFIFO36_INTERNAL is set to ") );
             write( Message, wr_offset_int);
             write( Message, STRING'(". Legal values for this attribute are ") );
             write( Message, 4);
             write( Message, STRING'(" to ") );
             write( Message, addr_limit_var - 5 );
             ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
             DEALLOCATE (Message);
           end if;

         end if;

       else
           
         if ((fwft_var = '0') and ((rd_offset_int < 1) or (rd_offset_int > addr_limit_var - 2))) then
           write( Message, STRING'("Attribute Syntax Error : ") );
           write( Message, STRING'("The attribute ") );
           write( Message, STRING'("ALMOST_EMPTY_OFFSET on AFIFO36_INTERNAL is set to ") );
           write( Message, rd_offset_int);
           write( Message, STRING'(". Legal values for this attribute are ") );
           write( Message, 1);
           write( Message, STRING'(" to ") );
           write( Message, addr_limit_var - 2 );
           ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
           DEALLOCATE (Message);
         end if;

         if ((fwft_var = '0') and ((wr_offset_int < 1) or (wr_offset_int > addr_limit_var - 2))) then
           write( Message, STRING'("Attribute Syntax Error : ") );
           write( Message, STRING'("The attribute ") );
           write( Message, STRING'("ALMOST_FULL_OFFSET on AFIFO36_INTERNAL is set to ") );
           write( Message, wr_offset_int);
           write( Message, STRING'(". Legal values for this attribute are ") );
           write( Message, 1);
           write( Message, STRING'(" to ") );
           write( Message, addr_limit_var - 2 );
           ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
           DEALLOCATE (Message);
         end if;

       end if;

       
       if(fwft_var = '1' and EN_SYN = TRUE) then
          assert false
          report "DRC Error : First word fall through is not supported in synchronous mode on AFIFO36_INTERNAL."
          severity failure;
       end if;

       
       if(EN_SYN = FALSE and DO_REG = 0) then
          assert false
          report "DRC Error : DO_REG = 0 is invalid when EN_SYN is set to FALSE on AFIFO36_INTERNAL."
          severity failure;
       end if;

       
       if (not (EN_ECC_WRITE = TRUE or EN_ECC_WRITE = FALSE)) then
         GenericValueCheckMessage
           ( HeaderMsg            => " Attribute Syntax Error ",
             GenericName          => " EN_ECC_WRITE ",
             EntityName           => "AFIFO36_INTERNAL",
             GenericValue         => EN_ECC_WRITE,
             Unit                 => "",
             ExpectedValueMsg     => " The Legal values for this attribute are ",
             ExpectedGenericValue => " true or false ",
             TailMsg              => "",
             MsgSeverity          => failure
             );
       end if;

       
       if (not (EN_ECC_READ = TRUE or EN_ECC_READ = FALSE)) then
         GenericValueCheckMessage
           ( HeaderMsg            => " Attribute Syntax Error ",
             GenericName          => " EN_ECC_READ ",
             EntityName           => "AFIFO36_INTERNAL",
             GenericValue         => EN_ECC_READ,
             Unit                 => "",
             ExpectedValueMsg     => " The Legal values for this attribute are ",
             ExpectedGenericValue => " true or false ",
             TailMsg              => "",
             MsgSeverity          => failure
             );
       end if;


       if ((EN_ECC_WRITE = TRUE or EN_ECC_READ = TRUE) and DATA_WIDTH /= 72) then
          assert false
            report "DRC Error : The attribute DATA_WIDTH must be set to 72 when AFIFO36_INTERNAL is configured in the ECC mode."
          severity failure;
       end if;

       
       addr_limit <= addr_limit_var;
       fwft       <= fwft_var;
       ae_full    <= ae_full_var;
       ae_empty   <= ae_empty_var;
       first_time := false;
     end if;
     wait;
  end process prcs_initialize;

--####################################################################
--#####                         CR 182616                        #####
--####################################################################
  prcs_rst_rdin_wrin:process(RST_dly, RDEN_dly, WREN_dly)
  begin
     if(RST_dly = '1') then
       if(RDEN_dly = '1') then
          assert false
          report "Warning : RDEN on AFIFO36_INTERNAL  is high when RST is high. RDEN should be low during reset."
          severity Warning;
       end if;

       if(WREN_dly = '1') then
          assert false
          report "Warning : WREN on AFIFO36_INTERNAL  is high when RST is high. WREN should be low during reset."
          severity Warning;
       end if;
     end if;
  end process prcs_rst_rdin_wrin;
-------------------------------------------

  prcs_3clkrst_readwrite:process(RDCLK_dly, WRCLK_dly)
  variable  rst_rdckreg_var : std_logic_vector (2 downto 0) := (others => '0');
  variable  rst_wrckreg_var : std_logic_vector (2 downto 0) := (others => '0');
  begin
    if(rising_edge(RDCLK_dly)) then
      rst_rdckreg_var(2) := RST_dly and rst_rdckreg_var(1);
      rst_rdckreg_var(1) := RST_dly and rst_rdckreg_var(0);
      rst_rdckreg_var(0) := RST_dly;
    end if;   
           
    if(rising_edge(WRCLK_dly)) then
      rst_wrckreg_var(2) := RST_dly and rst_wrckreg_var(1);
      rst_wrckreg_var(1) := RST_dly and rst_wrckreg_var(0);
      rst_wrckreg_var(0) := RST_dly;
    end if;   

    rst_rdckreg <= rst_rdckreg_var;
    rst_wrckreg <= rst_wrckreg_var;
  end process prcs_3clkrst_readwrite;

  prcs_2clkrst:process(RST_dly)
  begin
    rst_rdclk_flag <= '0';
    rst_wrclk_flag <= '0';

       if(falling_edge(RST_dly)) then
         if((rst_rdckreg(2) ='0') or (rst_rdckreg(1) ='0') or (rst_rdckreg(0) ='0')) then  
             assert false
             report "Error : RST signal on AFIFO36_INTERNAL stays high for less than three RDCLK clock cycles. RST has to stay high for more than three RDCLK clock cycles"
             severity Error;
             rst_rdclk_flag <= '1';
         end if;
         
         if((rst_wrckreg(2) ='0') or (rst_wrckreg(1) ='0') or (rst_wrckreg(0) ='0')) then  
             assert false
             report "Error : RST signal on AFIFO36_INTERNAL stays high for less than three WRCLK clock cycles. RST has to stay high for more than three WRCLK clock cycles"
             severity Error;
             rst_wrclk_flag <= '1';
         end if;

      end if;

      
  end process prcs_2clkrst;

--####################################################################
--#####                         Read                             #####
--####################################################################
  prcs_read:process(RDCLK_dly, RST_dly, GSR_dly, update_from_write_prcs, update_from_write_prcs_sync, rst_rdclk_flag, rst_wrclk_flag)
  variable first_time        : boolean    := true;
  variable rd_addr_var       : integer    := 0;
  variable wr_addr_var       : integer    := 0;
  variable rdcount_var       : integer    := 0;

  variable rd_flag_var       : std_ulogic := '0';
  variable wr_flag_var       : std_ulogic := '0';
  variable awr_flag_var       : std_ulogic := '0';  

  variable rdcount_flag_var  : std_ulogic := '0';

  variable do_in             : std_logic_vector(MSB_MAX_DO  downto 0)    := (others => '0');
  variable dop_in            : std_logic_vector(MSB_MAX_DOP downto 0)    := (others => '0');

  variable almostempty_int   : std_ulogic_vector(3 downto 0) := (others => '1');
  variable empty_int         : std_ulogic_vector(3 downto 0) := (others => '1');
  variable empty_ram         : std_ulogic_vector(3 downto 0) := (others => '1');

  variable addr_limit_var    : integer    := 0;

  variable wr1_addr_var      : integer := 0;
  variable wr1_flag_var      : std_ulogic := '0';
  variable rd_prefetch_var   : integer := 0;
  variable rd_prefetch_flag_var  : std_ulogic := '0';

-- CR 195129  fix from verilog (may not be necessary for vhdl)
-- Added ren_var/wren_var to remember the old val of RDEN_dly/WREN_dly

  variable rden_var  : std_ulogic := '0';
  variable wren_var  : std_ulogic := '0';

  variable do_buf : std_logic_vector(MSB_MAX_DO downto 0) := (others => '0');
  variable dop_buf : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0');
  variable dopr_ecc : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0');
  variable tmp_syndrome_int : integer;    
  variable syndrome : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0');
  variable ecc_bit_position : std_logic_vector(71 downto 0) := (others => '0');
  variable di_dly_ecc_corrected : std_logic_vector(MSB_MAX_DO downto 0) := (others => '0');
  variable dip_dly_ecc_corrected : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0');
  variable sbiterr_out : std_ulogic := '0';
  variable dbiterr_out : std_ulogic := '0';
  variable sbiterr_out_out_var : std_ulogic := '0';
  variable dbiterr_out_out_var : std_ulogic := '0';
  variable DO_OUTREG_var: std_logic_vector(MSB_MAX_DO downto 0) := (others => '0');
  variable DOP_OUTREG_var : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0');

  begin
     if((GSR_dly = '1') or (RST_dly = '1')) then
       rd_addr <= 0;
       rd_flag <= '0';

       rd_addr_var  := 0;
       wr_addr_var  := 0;
       wr1_addr_var := 0;
       rd_prefetch_var := 0;
   
       rdcount_var := 0;
       
       rd_flag_var  := '0';
       wr_flag_var  := '0';
       awr_flag_var  := '0';       
       wr1_flag_var := '0';
       rd_prefetch_flag_var := '0';
  
       rdcount_flag_var := '0';

       empty_int       :=  (others => '1');
       almostempty_int :=  (others => '1');
       empty_ram       :=  (others => '1');

       sbiterr_zd <= '0';
       dbiterr_zd <= '0';
       
       ALMOSTEMPTY_zd <= '1';
       EMPTY_zd <= '1';
       RDERR_zd <= '0';
       RDCOUNT_zd <= (others => '0');
  
       if(GSR_dly = '1') then
         DO_zd((mem_width -1) downto 0) <= (others => '0');
         DO_OUTREG_zd((mem_width -1) downto 0) <= (others => '0');
         if (DATA_WIDTH /= 4) then
           DOP_zd((memp_width -1) downto 0) <= (others => '0');
           DOP_OUTREG_zd((memp_width -1) downto 0) <= (others => '0');
         end if;
       end if;

     elsif ((rst_rdclk_flag = '1') or (rst_wrclk_flag = '1'))then

       rd_addr <= 0;
       rd_flag <= '0';

       rd_addr_var  := 0;
       wr_addr_var  := 0;
       wr1_addr_var := 0;
       rd_prefetch_var := 0;
   
       rdcount_var := 0;
       
       rd_flag_var  := '0';
       wr_flag_var  := '0';
       awr_flag_var  := '0';       
       wr1_flag_var := '0';
       rd_prefetch_flag_var := '0';
  
       rdcount_flag_var := '0';

       empty_int       :=  (others => '1');
       almostempty_int :=  (others => '1');
       empty_ram       :=  (others => '1');

       ALMOSTEMPTY_zd <= 'X';
       EMPTY_zd <= 'X';
       RDERR_zd <= 'X';
       RDCOUNT_zd <= (others => 'X');
       
       sbiterr_zd <= 'X';
       dbiterr_zd <= 'X';

       DO_zd((mem_width -1) downto 0) <= (others => 'X');
       DO_OUTREG_zd((mem_width -1) downto 0) <= (others => 'X');

       if (DATA_WIDTH /= 4) then
         DOP_zd((memp_width -1) downto 0) <= (others => 'X');
         DOP_OUTREG_zd((memp_width -1) downto 0) <= (others => 'X');
       end if;
       
     elsif ((GSR_dly = '0') and (RST_dly = '0'))then

       rden_var := RDEN_dly;
       wren_var := WREN_dly;

       if(rising_edge(RDCLK_dly)) then

         rd_flag_var := rd_flag;
         wr_flag_var := wr_flag;
         awr_flag_var := awr_flag;

         rd_addr_var := rd_addr;
         wr_addr_var := wr_addr;

         rdcount_var := SLV_TO_INT(RDCOUNT_zd);
         rdcount_flag_var := rdcount_flag;


         if (sync = '1') then
           
           DO_OUTREG_var := DO_zd;
           DOP_OUTREG_var := DOP_zd;

           if (RDEN_dly = '1') then

             if (EMPTY_zd = '0') then

               do_buf(mem_width-1 downto 0) := mem(rdcount_var);
               dop_buf(memp_width-1 downto 0) := memp(rdcount_var);

               -- ECC decode
               if (EN_ECC_READ = TRUE) then
                 -- regenerate parity
                 dopr_ecc(0) := do_buf(0) xor do_buf(1) xor do_buf(3) xor do_buf(4) xor do_buf(6) xor do_buf(8)
		      xor do_buf(10) xor do_buf(11) xor do_buf(13) xor do_buf(15) xor do_buf(17) xor do_buf(19)
		      xor do_buf(21) xor do_buf(23) xor do_buf(25) xor do_buf(26) xor do_buf(28)
            	      xor do_buf(30) xor do_buf(32) xor do_buf(34) xor do_buf(36) xor do_buf(38)
		      xor do_buf(40) xor do_buf(42) xor do_buf(44) xor do_buf(46) xor do_buf(48)
		      xor do_buf(50) xor do_buf(52) xor do_buf(54) xor do_buf(56) xor do_buf(57) xor do_buf(59)
		      xor do_buf(61) xor do_buf(63);

                 dopr_ecc(1) := do_buf(0) xor do_buf(2) xor do_buf(3) xor do_buf(5) xor do_buf(6) xor do_buf(9)
                      xor do_buf(10) xor do_buf(12) xor do_buf(13) xor do_buf(16) xor do_buf(17)
                      xor do_buf(20) xor do_buf(21) xor do_buf(24) xor do_buf(25) xor do_buf(27) xor do_buf(28)
                      xor do_buf(31) xor do_buf(32) xor do_buf(35) xor do_buf(36) xor do_buf(39)
                      xor do_buf(40) xor do_buf(43) xor do_buf(44) xor do_buf(47) xor do_buf(48)
                      xor do_buf(51) xor do_buf(52) xor do_buf(55) xor do_buf(56) xor do_buf(58) xor do_buf(59)
                      xor do_buf(62) xor do_buf(63);

                 dopr_ecc(2) := do_buf(1) xor do_buf(2) xor do_buf(3) xor do_buf(7) xor do_buf(8) xor do_buf(9)
                      xor do_buf(10) xor do_buf(14) xor do_buf(15) xor do_buf(16) xor do_buf(17)
                      xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25) xor do_buf(29)
                      xor do_buf(30) xor do_buf(31) xor do_buf(32) xor do_buf(37) xor do_buf(38) xor do_buf(39)
                      xor do_buf(40) xor do_buf(45) xor do_buf(46) xor do_buf(47) xor do_buf(48)
                      xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56)
                      xor do_buf(60) xor do_buf(61) xor do_buf(62) xor do_buf(63);
	
                 dopr_ecc(3) := do_buf(4) xor do_buf(5) xor do_buf(6) xor do_buf(7) xor do_buf(8) xor do_buf(9)
		      xor do_buf(10) xor do_buf(18) xor do_buf(19)
                      xor do_buf(20) xor do_buf(21) xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25)
                      xor do_buf(33) xor do_buf(34) xor do_buf(35) xor do_buf(36) xor do_buf(37) xor do_buf(38) xor do_buf(39)
                      xor do_buf(40) xor do_buf(49)
                      xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56);

                 dopr_ecc(4) := do_buf(11) xor do_buf(12) xor do_buf(13) xor do_buf(14) xor do_buf(15) xor do_buf(16) xor do_buf(17) xor do_buf(18) xor do_buf(19)
                      xor do_buf(20) xor do_buf(21) xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25)
                      xor do_buf(41) xor do_buf(42) xor do_buf(43) xor do_buf(44) xor do_buf(45) xor do_buf(46) xor do_buf(47) xor do_buf(48) xor do_buf(49)
                      xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56);


                 dopr_ecc(5) := do_buf(26) xor do_buf(27) xor do_buf(28) xor do_buf(29)
                      xor do_buf(30) xor do_buf(31) xor do_buf(32) xor do_buf(33) xor do_buf(34) xor do_buf(35) xor do_buf(36) xor do_buf(37) xor do_buf(38)
	              xor do_buf(39) xor do_buf(40) xor do_buf(41) xor do_buf(42) xor do_buf(43) xor do_buf(44) xor do_buf(45) xor do_buf(46) xor do_buf(47)
                      xor do_buf(48) xor do_buf(49) xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56);

                 dopr_ecc(6) := do_buf(57) xor do_buf(58) xor do_buf(59)
                      xor do_buf(60) xor do_buf(61) xor do_buf(62) xor do_buf(63);

                 dopr_ecc(7) := dop_buf(0) xor dop_buf(1) xor dop_buf(2) xor dop_buf(3) xor dop_buf(4) xor dop_buf(5) xor dop_buf(6)
                      xor do_buf(0) xor do_buf(1) xor do_buf(2) xor do_buf(3) xor do_buf(4) xor do_buf(5) xor do_buf(6) xor do_buf(7) xor do_buf(8) xor do_buf(9)
                      xor do_buf(10) xor do_buf(11) xor do_buf(12) xor do_buf(13) xor do_buf(14) xor do_buf(15) xor do_buf(16) xor do_buf(17) xor do_buf(18)
                      xor do_buf(19) xor do_buf(20) xor do_buf(21) xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25) xor do_buf(26) xor do_buf(27)
                      xor do_buf(28) xor do_buf(29) xor do_buf(30) xor do_buf(31) xor do_buf(32) xor do_buf(33) xor do_buf(34) xor do_buf(35) xor do_buf(36)
                      xor do_buf(37) xor do_buf(38) xor do_buf(39) xor do_buf(40) xor do_buf(41) xor do_buf(42) xor do_buf(43) xor do_buf(44) xor do_buf(45)
                      xor do_buf(46) xor do_buf(47) xor do_buf(48) xor do_buf(49) xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54)
                      xor do_buf(55) xor do_buf(56) xor do_buf(57) xor do_buf(58) xor do_buf(59) xor do_buf(60) xor do_buf(61) xor do_buf(62) xor do_buf(63);

                 syndrome := dopr_ecc xor dop_buf;

                 if (syndrome /= "00000000") then

                   if (syndrome(7) = '1') then  -- dectect single bit error

                     ecc_bit_position := do_buf(63 downto 57) & dop_buf(6) & do_buf(56 downto 26) & dop_buf(5) & do_buf(25 downto 11) & dop_buf(4) & do_buf(10 downto 4) & dop_buf(3) & do_buf(3 downto 1) & dop_buf(2) & do_buf(0) & dop_buf(1 downto 0) & dop_buf(7);

                     tmp_syndrome_int := SLV_TO_INT(syndrome(6 downto 0));
                     ecc_bit_position(tmp_syndrome_int) := not ecc_bit_position(tmp_syndrome_int); -- correct single bit error in the output 

                     di_dly_ecc_corrected := ecc_bit_position(71 downto 65) & ecc_bit_position(63 downto 33) & ecc_bit_position(31 downto 17) & ecc_bit_position(15 downto 9) & ecc_bit_position(7 downto 5) & ecc_bit_position(3); -- correct single bit error in the memory

                     do_buf := di_dly_ecc_corrected;
			
                     dip_dly_ecc_corrected := ecc_bit_position(0) & ecc_bit_position(64) & ecc_bit_position(32) & ecc_bit_position(16) & ecc_bit_position(8) & ecc_bit_position(4) & ecc_bit_position(2 downto 1); -- correct single bit error in the parity memory
                
                     dop_buf := dip_dly_ecc_corrected;
                
                     dbiterr_out_out_var := '0';  -- latch out in sync mode
                     sbiterr_out_out_var := '1';

                   elsif (syndrome(7) = '0') then  -- double bit error
                     sbiterr_out_out_var := '0';
                     dbiterr_out_out_var := '1';
                   end if;
                 else
                   dbiterr_out_out_var := '0';
                   sbiterr_out_out_var := '0';
                 end if;              
               end if;
               
               DO_zd <= do_buf;
               DOP_zd <= dop_buf;

               rdcount_var := (rdcount_var + 1) mod addr_limit;

               if (rdcount_var = 0) then
                 rdcount_flag_var := not rdcount_flag_var;
               end if;

             end if;
           end if;


           if (RDEN_dly = '1' and EMPTY_zd = '1') then
             RDERR_zd <= '1';
           else
             RDERR_zd <= '0';
           end if;
           
           
           if (WREN_dly = '1') then
             EMPTY_zd <= '0';
           elsif (rdcount_var = wr_addr_var and rdcount_flag_var = wr_flag_var) then
             EMPTY_zd <= '1';
           end if;
             
           if((((rdcount_var + ae_empty) >= wr_addr_var) and (rdcount_flag_var = wr_flag_var)) or (((rdcount_var + ae_empty) >= (wr_addr_var + addr_limit)) and (rdcount_flag_var /= wr_flag_var))) then    
             ALMOSTEMPTY_zd <= '1';
           end if;

           update_from_read_prcs_sync <= not update_from_read_prcs_sync;

       elsif (sync = '0') then

         dbiterr_out_out_var := dbiterr_out; -- reg out in async mode
         sbiterr_out_out_var := sbiterr_out;
                    
         if(fwft = '0') then
           addr_limit_var := addr_limit;
           if((rden_var = '1') and (rd_addr_var /= rdcount_var)) then
              DO_zd   <= do_in;
              if (DATA_WIDTH /= 4) then
                DOP_zd  <= dop_in;
              end if;
              rd_addr_var  := (rd_addr_var + 1) mod addr_limit;
              if(rd_addr_var = 0) then 
                  rd_flag_var := NOT rd_flag_var;
              end if;
           end if;
           if (((rd_addr_var = rdcount_var) and (empty_ram(3) = '0')) or 
              ((rden_var = '1') and (empty_ram(1) = '0'))) then
                do_buf(mem_width-1 downto 0) := mem(rdcount_var);
                dop_buf(memp_width-1 downto 0) := memp(rdcount_var);

 
               -- ECC decode
               if (EN_ECC_READ = TRUE) then
                 -- regenerate parity
                 dopr_ecc(0) := do_buf(0) xor do_buf(1) xor do_buf(3) xor do_buf(4) xor do_buf(6) xor do_buf(8)
		      xor do_buf(10) xor do_buf(11) xor do_buf(13) xor do_buf(15) xor do_buf(17) xor do_buf(19)
		      xor do_buf(21) xor do_buf(23) xor do_buf(25) xor do_buf(26) xor do_buf(28)
            	      xor do_buf(30) xor do_buf(32) xor do_buf(34) xor do_buf(36) xor do_buf(38)
		      xor do_buf(40) xor do_buf(42) xor do_buf(44) xor do_buf(46) xor do_buf(48)
		      xor do_buf(50) xor do_buf(52) xor do_buf(54) xor do_buf(56) xor do_buf(57) xor do_buf(59)
		      xor do_buf(61) xor do_buf(63);

                 dopr_ecc(1) := do_buf(0) xor do_buf(2) xor do_buf(3) xor do_buf(5) xor do_buf(6) xor do_buf(9)
                      xor do_buf(10) xor do_buf(12) xor do_buf(13) xor do_buf(16) xor do_buf(17)
                      xor do_buf(20) xor do_buf(21) xor do_buf(24) xor do_buf(25) xor do_buf(27) xor do_buf(28)
                      xor do_buf(31) xor do_buf(32) xor do_buf(35) xor do_buf(36) xor do_buf(39)
                      xor do_buf(40) xor do_buf(43) xor do_buf(44) xor do_buf(47) xor do_buf(48)
                      xor do_buf(51) xor do_buf(52) xor do_buf(55) xor do_buf(56) xor do_buf(58) xor do_buf(59)
                      xor do_buf(62) xor do_buf(63);

                 dopr_ecc(2) := do_buf(1) xor do_buf(2) xor do_buf(3) xor do_buf(7) xor do_buf(8) xor do_buf(9)
                      xor do_buf(10) xor do_buf(14) xor do_buf(15) xor do_buf(16) xor do_buf(17)
                      xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25) xor do_buf(29)
                      xor do_buf(30) xor do_buf(31) xor do_buf(32) xor do_buf(37) xor do_buf(38) xor do_buf(39)
                      xor do_buf(40) xor do_buf(45) xor do_buf(46) xor do_buf(47) xor do_buf(48)
                      xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56)
                      xor do_buf(60) xor do_buf(61) xor do_buf(62) xor do_buf(63);
	
                 dopr_ecc(3) := do_buf(4) xor do_buf(5) xor do_buf(6) xor do_buf(7) xor do_buf(8) xor do_buf(9)
		      xor do_buf(10) xor do_buf(18) xor do_buf(19)
                      xor do_buf(20) xor do_buf(21) xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25)
                      xor do_buf(33) xor do_buf(34) xor do_buf(35) xor do_buf(36) xor do_buf(37) xor do_buf(38) xor do_buf(39)
                      xor do_buf(40) xor do_buf(49)
                      xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56);

                 dopr_ecc(4) := do_buf(11) xor do_buf(12) xor do_buf(13) xor do_buf(14) xor do_buf(15) xor do_buf(16) xor do_buf(17) xor do_buf(18) xor do_buf(19)
                      xor do_buf(20) xor do_buf(21) xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25)
                      xor do_buf(41) xor do_buf(42) xor do_buf(43) xor do_buf(44) xor do_buf(45) xor do_buf(46) xor do_buf(47) xor do_buf(48) xor do_buf(49)
                      xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56);


                 dopr_ecc(5) := do_buf(26) xor do_buf(27) xor do_buf(28) xor do_buf(29)
                      xor do_buf(30) xor do_buf(31) xor do_buf(32) xor do_buf(33) xor do_buf(34) xor do_buf(35) xor do_buf(36) xor do_buf(37) xor do_buf(38)
	              xor do_buf(39) xor do_buf(40) xor do_buf(41) xor do_buf(42) xor do_buf(43) xor do_buf(44) xor do_buf(45) xor do_buf(46) xor do_buf(47)
                      xor do_buf(48) xor do_buf(49) xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56);

                 dopr_ecc(6) := do_buf(57) xor do_buf(58) xor do_buf(59)
                      xor do_buf(60) xor do_buf(61) xor do_buf(62) xor do_buf(63);

                 dopr_ecc(7) := dop_buf(0) xor dop_buf(1) xor dop_buf(2) xor dop_buf(3) xor dop_buf(4) xor dop_buf(5) xor dop_buf(6)
                      xor do_buf(0) xor do_buf(1) xor do_buf(2) xor do_buf(3) xor do_buf(4) xor do_buf(5) xor do_buf(6) xor do_buf(7) xor do_buf(8) xor do_buf(9)
                      xor do_buf(10) xor do_buf(11) xor do_buf(12) xor do_buf(13) xor do_buf(14) xor do_buf(15) xor do_buf(16) xor do_buf(17) xor do_buf(18)
                      xor do_buf(19) xor do_buf(20) xor do_buf(21) xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25) xor do_buf(26) xor do_buf(27)
                      xor do_buf(28) xor do_buf(29) xor do_buf(30) xor do_buf(31) xor do_buf(32) xor do_buf(33) xor do_buf(34) xor do_buf(35) xor do_buf(36)
                      xor do_buf(37) xor do_buf(38) xor do_buf(39) xor do_buf(40) xor do_buf(41) xor do_buf(42) xor do_buf(43) xor do_buf(44) xor do_buf(45)
                      xor do_buf(46) xor do_buf(47) xor do_buf(48) xor do_buf(49) xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54)
                      xor do_buf(55) xor do_buf(56) xor do_buf(57) xor do_buf(58) xor do_buf(59) xor do_buf(60) xor do_buf(61) xor do_buf(62) xor do_buf(63);

                 syndrome := dopr_ecc xor dop_buf;

                 if (syndrome /= "00000000") then

                   if (syndrome(7) = '1') then  -- dectect single bit error

                     ecc_bit_position := do_buf(63 downto 57) & dop_buf(6) & do_buf(56 downto 26) & dop_buf(5) & do_buf(25 downto 11) & dop_buf(4) & do_buf(10 downto 4) & dop_buf(3) & do_buf(3 downto 1) & dop_buf(2) & do_buf(0) & dop_buf(1 downto 0) & dop_buf(7);

                     tmp_syndrome_int := SLV_TO_INT(syndrome(6 downto 0));
                     ecc_bit_position(tmp_syndrome_int) := not ecc_bit_position(tmp_syndrome_int); -- correct single bit error in the output 

                     di_dly_ecc_corrected := ecc_bit_position(71 downto 65) & ecc_bit_position(63 downto 33) & ecc_bit_position(31 downto 17) & ecc_bit_position(15 downto 9) & ecc_bit_position(7 downto 5) & ecc_bit_position(3); -- correct single bit error in the memory

                     do_buf := di_dly_ecc_corrected;
			
                     dip_dly_ecc_corrected := ecc_bit_position(0) & ecc_bit_position(64) & ecc_bit_position(32) & ecc_bit_position(16) & ecc_bit_position(8) & ecc_bit_position(4) & ecc_bit_position(2 downto 1); -- correct single bit error in the parity memory
                
                     dop_buf := dip_dly_ecc_corrected;
                
                     dbiterr_out := '0';  -- reg out in async mode
                     sbiterr_out := '1';

                   elsif (syndrome(7) = '0') then  -- double bit error
                     sbiterr_out := '0';
                     dbiterr_out := '1';
                   end if;
                 else
                   dbiterr_out := '0';
                   sbiterr_out := '0';
                 end if;              
               end if;

                
                do_in := do_buf;
                dop_in := dop_buf;
                 
                
             rdcount_var := (rdcount_var + 1) mod addr_limit;

              if(rdcount_var = 0) then
                 rdcount_flag_var := NOT rdcount_flag_var;
              end if;

         end if;
         
         elsif(fwft = '1') then
           if((rden_var = '1') and (rd_addr_var /= rd_prefetch_var)) then
              rd_prefetch_var := (rd_prefetch_var + 1) mod addr_limit;
              if(rd_prefetch_var = 0) then 
                  rd_prefetch_flag_var := NOT rd_prefetch_flag_var;
              end if;
           end if;
           if((rd_prefetch_var = rd_addr_var) and (rd_addr_var /= rdcount_var)) then
             DO_zd   <= do_in;
             if (DATA_WIDTH /= 4) then
               DOP_zd <= dop_in;
             end if;
             rd_addr_var  := (rd_addr_var + 1) mod addr_limit;
             if(rd_addr_var = 0) then 
                rd_flag_var := NOT rd_flag_var;
             end if;
           end if;
           if(((rd_addr_var = rdcount_var) and (empty_ram(3) = '0')) or
              ((rden_var = '1')  and (empty_ram(1) = '0')) or 
              ((rden_var = '0')  and (empty_ram(1) = '0') and (rd_addr_var = rdcount_var))) then 
                do_buf(mem_width-1 downto 0) := mem(rdcount_var);
                dop_buf(memp_width-1 downto 0) := memp(rdcount_var);

                -- ECC decode
               if (EN_ECC_READ = TRUE) then
                 -- regenerate parity
                 dopr_ecc(0) := do_buf(0) xor do_buf(1) xor do_buf(3) xor do_buf(4) xor do_buf(6) xor do_buf(8)
		      xor do_buf(10) xor do_buf(11) xor do_buf(13) xor do_buf(15) xor do_buf(17) xor do_buf(19)
		      xor do_buf(21) xor do_buf(23) xor do_buf(25) xor do_buf(26) xor do_buf(28)
            	      xor do_buf(30) xor do_buf(32) xor do_buf(34) xor do_buf(36) xor do_buf(38)
		      xor do_buf(40) xor do_buf(42) xor do_buf(44) xor do_buf(46) xor do_buf(48)
		      xor do_buf(50) xor do_buf(52) xor do_buf(54) xor do_buf(56) xor do_buf(57) xor do_buf(59)
		      xor do_buf(61) xor do_buf(63);

                 dopr_ecc(1) := do_buf(0) xor do_buf(2) xor do_buf(3) xor do_buf(5) xor do_buf(6) xor do_buf(9)
                      xor do_buf(10) xor do_buf(12) xor do_buf(13) xor do_buf(16) xor do_buf(17)
                      xor do_buf(20) xor do_buf(21) xor do_buf(24) xor do_buf(25) xor do_buf(27) xor do_buf(28)
                      xor do_buf(31) xor do_buf(32) xor do_buf(35) xor do_buf(36) xor do_buf(39)
                      xor do_buf(40) xor do_buf(43) xor do_buf(44) xor do_buf(47) xor do_buf(48)
                      xor do_buf(51) xor do_buf(52) xor do_buf(55) xor do_buf(56) xor do_buf(58) xor do_buf(59)
                      xor do_buf(62) xor do_buf(63);

                 dopr_ecc(2) := do_buf(1) xor do_buf(2) xor do_buf(3) xor do_buf(7) xor do_buf(8) xor do_buf(9)
                      xor do_buf(10) xor do_buf(14) xor do_buf(15) xor do_buf(16) xor do_buf(17)
                      xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25) xor do_buf(29)
                      xor do_buf(30) xor do_buf(31) xor do_buf(32) xor do_buf(37) xor do_buf(38) xor do_buf(39)
                      xor do_buf(40) xor do_buf(45) xor do_buf(46) xor do_buf(47) xor do_buf(48)
                      xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56)
                      xor do_buf(60) xor do_buf(61) xor do_buf(62) xor do_buf(63);
	
                 dopr_ecc(3) := do_buf(4) xor do_buf(5) xor do_buf(6) xor do_buf(7) xor do_buf(8) xor do_buf(9)
		      xor do_buf(10) xor do_buf(18) xor do_buf(19)
                      xor do_buf(20) xor do_buf(21) xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25)
                      xor do_buf(33) xor do_buf(34) xor do_buf(35) xor do_buf(36) xor do_buf(37) xor do_buf(38) xor do_buf(39)
                      xor do_buf(40) xor do_buf(49)
                      xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56);

                 dopr_ecc(4) := do_buf(11) xor do_buf(12) xor do_buf(13) xor do_buf(14) xor do_buf(15) xor do_buf(16) xor do_buf(17) xor do_buf(18) xor do_buf(19)
                      xor do_buf(20) xor do_buf(21) xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25)
                      xor do_buf(41) xor do_buf(42) xor do_buf(43) xor do_buf(44) xor do_buf(45) xor do_buf(46) xor do_buf(47) xor do_buf(48) xor do_buf(49)
                      xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56);


                 dopr_ecc(5) := do_buf(26) xor do_buf(27) xor do_buf(28) xor do_buf(29)
                      xor do_buf(30) xor do_buf(31) xor do_buf(32) xor do_buf(33) xor do_buf(34) xor do_buf(35) xor do_buf(36) xor do_buf(37) xor do_buf(38)
	              xor do_buf(39) xor do_buf(40) xor do_buf(41) xor do_buf(42) xor do_buf(43) xor do_buf(44) xor do_buf(45) xor do_buf(46) xor do_buf(47)
                      xor do_buf(48) xor do_buf(49) xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56);

                 dopr_ecc(6) := do_buf(57) xor do_buf(58) xor do_buf(59)
                      xor do_buf(60) xor do_buf(61) xor do_buf(62) xor do_buf(63);

                 dopr_ecc(7) := dop_buf(0) xor dop_buf(1) xor dop_buf(2) xor dop_buf(3) xor dop_buf(4) xor dop_buf(5) xor dop_buf(6)
                      xor do_buf(0) xor do_buf(1) xor do_buf(2) xor do_buf(3) xor do_buf(4) xor do_buf(5) xor do_buf(6) xor do_buf(7) xor do_buf(8) xor do_buf(9)
                      xor do_buf(10) xor do_buf(11) xor do_buf(12) xor do_buf(13) xor do_buf(14) xor do_buf(15) xor do_buf(16) xor do_buf(17) xor do_buf(18)
                      xor do_buf(19) xor do_buf(20) xor do_buf(21) xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25) xor do_buf(26) xor do_buf(27)
                      xor do_buf(28) xor do_buf(29) xor do_buf(30) xor do_buf(31) xor do_buf(32) xor do_buf(33) xor do_buf(34) xor do_buf(35) xor do_buf(36)
                      xor do_buf(37) xor do_buf(38) xor do_buf(39) xor do_buf(40) xor do_buf(41) xor do_buf(42) xor do_buf(43) xor do_buf(44) xor do_buf(45)
                      xor do_buf(46) xor do_buf(47) xor do_buf(48) xor do_buf(49) xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54)
                      xor do_buf(55) xor do_buf(56) xor do_buf(57) xor do_buf(58) xor do_buf(59) xor do_buf(60) xor do_buf(61) xor do_buf(62) xor do_buf(63);

                 syndrome := dopr_ecc xor dop_buf;

                 if (syndrome /= "00000000") then

                   if (syndrome(7) = '1') then  -- dectect single bit error

                     ecc_bit_position := do_buf(63 downto 57) & dop_buf(6) & do_buf(56 downto 26) & dop_buf(5) & do_buf(25 downto 11) & dop_buf(4) & do_buf(10 downto 4) & dop_buf(3) & do_buf(3 downto 1) & dop_buf(2) & do_buf(0) & dop_buf(1 downto 0) & dop_buf(7);

                     tmp_syndrome_int := SLV_TO_INT(syndrome(6 downto 0));
                     ecc_bit_position(tmp_syndrome_int) := not ecc_bit_position(tmp_syndrome_int); -- correct single bit error in the output 

                     di_dly_ecc_corrected := ecc_bit_position(71 downto 65) & ecc_bit_position(63 downto 33) & ecc_bit_position(31 downto 17) & ecc_bit_position(15 downto 9) & ecc_bit_position(7 downto 5) & ecc_bit_position(3); -- correct single bit error in the memory

                     do_buf := di_dly_ecc_corrected;
			
                     dip_dly_ecc_corrected := ecc_bit_position(0) & ecc_bit_position(64) & ecc_bit_position(32) & ecc_bit_position(16) & ecc_bit_position(8) & ecc_bit_position(4) & ecc_bit_position(2 downto 1); -- correct single bit error in the parity memory
                
                     dop_buf := dip_dly_ecc_corrected;
                
                     dbiterr_out := '0';
                     sbiterr_out := '1';

                   elsif (syndrome(7) = '0') then  -- double bit error
                     sbiterr_out := '0';
                     dbiterr_out := '1';
                   end if;

                 else
                   dbiterr_out := '0';
                   sbiterr_out := '0';
                 end if;              
               end if;


              do_in := do_buf;
              dop_in := dop_buf;
                 
                
              rdcount_var := (rdcount_var + 1) mod addr_limit;

              if(rdcount_var = 0) then
                 rdcount_flag_var := NOT rdcount_flag_var;
              end if;

         end if;

       end if;  ---  end if(fwft = '1')


         ALMOSTEMPTY_zd <= almostempty_int(3);

         if((((rdcount_var + ae_empty) >= wr_addr_var) and (rdcount_flag_var = awr_flag_var)) or (((rdcount_var + ae_empty) >= (wr_addr_var + addr_limit)) and (rdcount_flag_var /= awr_flag_var))) then    
            almostempty_int(3) := '1';
            almostempty_int(2) := '1';
            almostempty_int(1) := '1';
            almostempty_int(0) := '1';
         elsif(almostempty_int(2)  = '0') then
           -- added to match verilog
           if (rdcount_var <= rdcount_var + ae_empty or rdcount_flag_var /= awr_flag_var) then
            almostempty_int(3) :=  almostempty_int(0);
            almostempty_int(0) :=  '0';
           end if;
         end if;

         if(fwft = '0') then
           if((rdcount_var = rd_addr_var) and (rdcount_flag_var = rd_flag_var)) then
              EMPTY_zd <= '1';
           else
             EMPTY_zd  <= '0';
           end if;
         elsif(fwft = '1') then
           if((rd_prefetch_var = rd_addr_var) and (rd_prefetch_flag_var = rd_flag_var)) then
             EMPTY_zd <=  '1';
           else
             EMPTY_zd  <= '0';
           end if;
         end if;   
          
         if((rdcount_var = wr_addr_var) and (rdcount_flag_var = awr_flag_var)) then
           empty_ram(2) := '1';
           empty_ram(1) := '1';
           empty_ram(0) := '1';
         else
           empty_ram(2) := empty_ram(1);
           empty_ram(1) := empty_ram(0);
           empty_ram(0) := '0';
         end if;
           
         if((rdcount_var = wr1_addr_var) and (rdcount_flag_var = wr1_flag_var)) then
           empty_ram(3) := '1';
         else
           empty_ram(3) := '0';
         end if;

         wr1_addr_var := wr_addr;
         wr1_flag_var := awr_flag;

         if((rden_var = '1') and (EMPTY_zd = '1')) then
             RDERR_zd <= '1';
         else
             RDERR_zd <= '0';
         end if; -- end ((rden_var = '1') and (empty_int /= '1'))

        update_from_read_prcs <= NOT update_from_read_prcs;

       end if;
       
     end if; -- end (rising_edge(RDCLK_dly))

  end if; -- end (GSR_dly = 1)



     if(update_from_write_prcs_sync'event) then
       wr_addr_var := wr_addr;
       wr_flag_var := wr_flag;
       if((((rdcount_var + ae_empty) <  wr_addr_var)  and (rdcount_flag_var = wr_flag_var)) or 
          (((rdcount_var + ae_empty) < (wr_addr_var + addr_limit)) and (rdcount_flag_var /= wr_flag_var))) then    
          if(rdcount_var <= rdcount_var + ae_empty or rdcount_flag_var /= wr_flag_var) then
            almostempty_zd <= '0';
          end if;
       end if;
     end if;
  
     
     if(update_from_write_prcs'event) then
       wr_addr_var := wr_addr;
       wr_flag_var := wr_flag;
       awr_flag_var := awr_flag;

       if((((rdcount_var + ae_empty) <  wr_addr_var)  and (rdcount_flag_var = awr_flag_var)) or 
          (((rdcount_var + ae_empty) <  ( wr_addr_var + addr_limit)) and (rdcount_flag_var /= awr_flag_var))) then    
         if(wren_var = '1') then
             almostempty_int(2) := almostempty_int(1);
             almostempty_int(1) := '0';
          end if;
       else
           almostempty_int(2) := '1';
           almostempty_int(1) := '1';
       end if;
     end if;
  
  
     if (not (rst_rdclk_flag or rst_wrclk_flag) = '1') then
       RDCOUNT_zd <= CONV_STD_LOGIC_VECTOR(rdcount_var, MAX_RDCOUNT);       
       dbiterr_zd <= dbiterr_out_out_var; -- reg out in async mode
       sbiterr_zd <= sbiterr_out_out_var;
     end if;

     rd_addr <= rd_addr_var;
     rd_flag <= rd_flag_var;
     rdcount_flag <= rdcount_flag_var;
     DO_OUTREG_zd <= DO_OUTREG_var;
     DOP_OUTREG_zd <= DOP_OUTREG_var;

  end process prcs_read;

--####################################################################
--#####                         Write                            #####
--####################################################################
  prcs_write:process(WRCLK_dly, RST_dly, GSR_dly, update_from_read_prcs, update_from_read_prcs_sync, rst_rdclk_flag, rst_wrclk_flag)
  variable first_time        : boolean    := true;
  variable wr_addr_var       : integer := 0;
  variable rd_addr_var       : integer := 0;
  variable rdcount_var       : integer := 0;
  variable wrcount_var       : integer := 0;

  variable rd_flag_var       : std_ulogic := '0';
  variable wr_flag_var       : std_ulogic := '0';
  variable awr_flag_var       : std_ulogic := '0';

  variable rdcount_flag_var  : std_ulogic := '0';

  variable almostfull_int : std_ulogic_vector(3 downto 0) := (others => '0');
  variable full_int       : std_ulogic_vector(3 downto 0) := (others => '0');

-- CR 195129  fix from verilog (may not be necessary for vhdl)
-- Added ren_var/wren_var to remember the old val of RDEN_dly/WREN_dly

  variable rden_var  : std_ulogic := '0';
  variable wren_var  : std_ulogic := '0';
  variable dip_ecc : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0');
  variable dip_dly_ecc : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0');
  variable ALMOSTFULL_var : std_ulogic     :=    '0';

  begin
    if ((GSR_dly = '1') or (RST_dly = '1') or (rst_rdclk_flag = '1') or (rst_wrclk_flag = '1'))then
        wr_addr_var := 0;
        wr_addr <=  0;
        wr_flag <= '0';
        awr_flag <= '0';
        
        wr_addr_var := 0;
        rd_addr_var := 0;
        rdcount_var := 0;
        wrcount_var := 0;
        ALMOSTFULL_var := '0';
   
        rd_flag_var := '0';
        wr_flag_var := '0';
        awr_flag_var := '0';

        rdcount_flag_var  := '0';

        full_int       :=  (others => '0');
        almostfull_int :=  (others => '0');

        if ((GSR_dly = '1') or (RST_dly = '1'))then
          ALMOSTFULL_zd <= '0';      
          FULL_zd <= '0';            
          WRERR_zd <= '0';           
          WRCOUNT_zd <= (others => '0');
        else
          ALMOSTFULL_zd <= 'X';       
          FULL_zd <= 'X';             
          WRERR_zd <= 'X';            
          WRCOUNT_zd <= (others => 'X');
          eccparity_zd <= (others => 'X');
        end if;

    elsif((GSR_dly = '0') and (RST_dly = '0'))then
      rden_var := RDEN_dly;
      wren_var := WREN_dly;

      if(rising_edge(WRCLK_dly)) then

        rd_flag_var := rd_flag;
        wr_flag_var := wr_flag;
        awr_flag_var := awr_flag;        

        rd_addr_var := rd_addr;
        wr_addr_var := wr_addr;

        rdcount_var := SLV_TO_INT(RDCOUNT_zd);
        rdcount_flag_var := rdcount_flag;

	if (sync = '1') then
          if(wren_dly = '1') then
            if (full_zd= '0') then

            -- ECC encode
            if (EN_ECC_WRITE = TRUE) then

              -- regenerate parity
              dip_ecc(0) := di_dly(0) xor di_dly(1) xor di_dly(3) xor di_dly(4) xor di_dly(6) xor di_dly(8)
		      xor di_dly(10) xor di_dly(11) xor di_dly(13) xor di_dly(15) xor di_dly(17) xor di_dly(19)
		      xor di_dly(21) xor di_dly(23) xor di_dly(25) xor di_dly(26) xor di_dly(28)
            	      xor di_dly(30) xor di_dly(32) xor di_dly(34) xor di_dly(36) xor di_dly(38)
		      xor di_dly(40) xor di_dly(42) xor di_dly(44) xor di_dly(46) xor di_dly(48)
		      xor di_dly(50) xor di_dly(52) xor di_dly(54) xor di_dly(56) xor di_dly(57) xor di_dly(59)
		      xor di_dly(61) xor di_dly(63);

              dip_ecc(1) := di_dly(0) xor di_dly(2) xor di_dly(3) xor di_dly(5) xor di_dly(6) xor di_dly(9)
                      xor di_dly(10) xor di_dly(12) xor di_dly(13) xor di_dly(16) xor di_dly(17)
                      xor di_dly(20) xor di_dly(21) xor di_dly(24) xor di_dly(25) xor di_dly(27) xor di_dly(28)
                      xor di_dly(31) xor di_dly(32) xor di_dly(35) xor di_dly(36) xor di_dly(39)
                      xor di_dly(40) xor di_dly(43) xor di_dly(44) xor di_dly(47) xor di_dly(48)
                      xor di_dly(51) xor di_dly(52) xor di_dly(55) xor di_dly(56) xor di_dly(58) xor di_dly(59)
                      xor di_dly(62) xor di_dly(63);

              dip_ecc(2) := di_dly(1) xor di_dly(2) xor di_dly(3) xor di_dly(7) xor di_dly(8) xor di_dly(9)
                      xor di_dly(10) xor di_dly(14) xor di_dly(15) xor di_dly(16) xor di_dly(17)
                      xor di_dly(22) xor di_dly(23) xor di_dly(24) xor di_dly(25) xor di_dly(29)
                      xor di_dly(30) xor di_dly(31) xor di_dly(32) xor di_dly(37) xor di_dly(38) xor di_dly(39)
                      xor di_dly(40) xor di_dly(45) xor di_dly(46) xor di_dly(47) xor di_dly(48)
                      xor di_dly(53) xor di_dly(54) xor di_dly(55) xor di_dly(56)
                      xor di_dly(60) xor di_dly(61) xor di_dly(62) xor di_dly(63);
	
              dip_ecc(3) := di_dly(4) xor di_dly(5) xor di_dly(6) xor di_dly(7) xor di_dly(8) xor di_dly(9)
		      xor di_dly(10) xor di_dly(18) xor di_dly(19)
                      xor di_dly(20) xor di_dly(21) xor di_dly(22) xor di_dly(23) xor di_dly(24) xor di_dly(25)
                      xor di_dly(33) xor di_dly(34) xor di_dly(35) xor di_dly(36) xor di_dly(37) xor di_dly(38) xor di_dly(39)
                      xor di_dly(40) xor di_dly(49)
                      xor di_dly(50) xor di_dly(51) xor di_dly(52) xor di_dly(53) xor di_dly(54) xor di_dly(55) xor di_dly(56);

              dip_ecc(4) := di_dly(11) xor di_dly(12) xor di_dly(13) xor di_dly(14) xor di_dly(15) xor di_dly(16) xor di_dly(17) xor di_dly(18) xor di_dly(19)
                      xor di_dly(20) xor di_dly(21) xor di_dly(22) xor di_dly(23) xor di_dly(24) xor di_dly(25)
                      xor di_dly(41) xor di_dly(42) xor di_dly(43) xor di_dly(44) xor di_dly(45) xor di_dly(46) xor di_dly(47) xor di_dly(48) xor di_dly(49)
                      xor di_dly(50) xor di_dly(51) xor di_dly(52) xor di_dly(53) xor di_dly(54) xor di_dly(55) xor di_dly(56);


              dip_ecc(5) := di_dly(26) xor di_dly(27) xor di_dly(28) xor di_dly(29)
                      xor di_dly(30) xor di_dly(31) xor di_dly(32) xor di_dly(33) xor di_dly(34) xor di_dly(35) xor di_dly(36) xor di_dly(37) xor di_dly(38)
	              xor di_dly(39) xor di_dly(40) xor di_dly(41) xor di_dly(42) xor di_dly(43) xor di_dly(44) xor di_dly(45) xor di_dly(46) xor di_dly(47)
                      xor di_dly(48) xor di_dly(49) xor di_dly(50) xor di_dly(51) xor di_dly(52) xor di_dly(53) xor di_dly(54) xor di_dly(55) xor di_dly(56);

              dip_ecc(6) := di_dly(57) xor di_dly(58) xor di_dly(59)
                      xor di_dly(60) xor di_dly(61) xor di_dly(62) xor di_dly(63);

              dip_ecc(7) := dip_ecc(0) xor dip_ecc(1) xor dip_ecc(2) xor dip_ecc(3) xor dip_ecc(4) xor dip_ecc(5) xor dip_ecc(6)
                      xor di_dly(0) xor di_dly(1) xor di_dly(2) xor di_dly(3) xor di_dly(4) xor di_dly(5) xor di_dly(6) xor di_dly(7) xor di_dly(8) xor di_dly(9)
                      xor di_dly(10) xor di_dly(11) xor di_dly(12) xor di_dly(13) xor di_dly(14) xor di_dly(15) xor di_dly(16) xor di_dly(17) xor di_dly(18)
                      xor di_dly(19) xor di_dly(20) xor di_dly(21) xor di_dly(22) xor di_dly(23) xor di_dly(24) xor di_dly(25) xor di_dly(26) xor di_dly(27)
                      xor di_dly(28) xor di_dly(29) xor di_dly(30) xor di_dly(31) xor di_dly(32) xor di_dly(33) xor di_dly(34) xor di_dly(35) xor di_dly(36)
                      xor di_dly(37) xor di_dly(38) xor di_dly(39) xor di_dly(40) xor di_dly(41) xor di_dly(42) xor di_dly(43) xor di_dly(44) xor di_dly(45)
                      xor di_dly(46) xor di_dly(47) xor di_dly(48) xor di_dly(49) xor di_dly(50) xor di_dly(51) xor di_dly(52) xor di_dly(53) xor di_dly(54)
                      xor di_dly(55) xor di_dly(56) xor di_dly(57) xor di_dly(58) xor di_dly(59) xor di_dly(60) xor di_dly(61) xor di_dly(62) xor di_dly(63);

              ECCPARITY_zd <= dip_ecc;

              dip_dly_ecc := dip_ecc;  -- only 64 bits width

            else

              dip_dly_ecc := dip_dly; -- only 64 bits width

            end if;

            mem(wr_addr_var) <= DI_dly(mem_width-1 downto 0);
            memp(wr_addr_var) <= dip_dly_ecc(memp_width-1 downto 0);

            wr_addr_var := (wr_addr_var + 1) mod addr_limit;

            if(wr_addr_var = 0) then
              wr_flag_var := NOT wr_flag_var;
            end if;

          end if;
        end if;


        if ((WREN_dly = '1') and (FULL_zd = '1')) then
          WRERR_zd <= '1';
        else
          WRERR_zd <= '0';
        end if;

        
        if (rden_dly = '1') then
          full_zd <= '0';
        elsif (rdcount_var = wr_addr_var and rdcount_flag_var /= wr_flag_var) then
          full_zd <= '1';
        end if;

        update_from_write_prcs_sync <= NOT update_from_write_prcs_sync;

        if((((rdcount_var + addr_limit) <= (wr_addr_var + ae_full)) and (rdcount_flag_var = wr_flag_var)) or ((rdcount_var <= (wr_addr_var + ae_full)) and (rdcount_flag_var /= wr_flag_var))) then
          almostfull_zd <= '1';
        end if;
        

      elsif (sync = '0') then

        if((wren_var = '1') and (full_zd = '0'))then  

          -- ECC encode
            if (EN_ECC_WRITE = TRUE) then

              -- regenerate parity
              dip_ecc(0) := di_dly(0) xor di_dly(1) xor di_dly(3) xor di_dly(4) xor di_dly(6) xor di_dly(8)
		      xor di_dly(10) xor di_dly(11) xor di_dly(13) xor di_dly(15) xor di_dly(17) xor di_dly(19)
		      xor di_dly(21) xor di_dly(23) xor di_dly(25) xor di_dly(26) xor di_dly(28)
            	      xor di_dly(30) xor di_dly(32) xor di_dly(34) xor di_dly(36) xor di_dly(38)
		      xor di_dly(40) xor di_dly(42) xor di_dly(44) xor di_dly(46) xor di_dly(48)
		      xor di_dly(50) xor di_dly(52) xor di_dly(54) xor di_dly(56) xor di_dly(57) xor di_dly(59)
		      xor di_dly(61) xor di_dly(63);

              dip_ecc(1) := di_dly(0) xor di_dly(2) xor di_dly(3) xor di_dly(5) xor di_dly(6) xor di_dly(9)
                      xor di_dly(10) xor di_dly(12) xor di_dly(13) xor di_dly(16) xor di_dly(17)
                      xor di_dly(20) xor di_dly(21) xor di_dly(24) xor di_dly(25) xor di_dly(27) xor di_dly(28)
                      xor di_dly(31) xor di_dly(32) xor di_dly(35) xor di_dly(36) xor di_dly(39)
                      xor di_dly(40) xor di_dly(43) xor di_dly(44) xor di_dly(47) xor di_dly(48)
                      xor di_dly(51) xor di_dly(52) xor di_dly(55) xor di_dly(56) xor di_dly(58) xor di_dly(59)
                      xor di_dly(62) xor di_dly(63);

              dip_ecc(2) := di_dly(1) xor di_dly(2) xor di_dly(3) xor di_dly(7) xor di_dly(8) xor di_dly(9)
                      xor di_dly(10) xor di_dly(14) xor di_dly(15) xor di_dly(16) xor di_dly(17)
                      xor di_dly(22) xor di_dly(23) xor di_dly(24) xor di_dly(25) xor di_dly(29)
                      xor di_dly(30) xor di_dly(31) xor di_dly(32) xor di_dly(37) xor di_dly(38) xor di_dly(39)
                      xor di_dly(40) xor di_dly(45) xor di_dly(46) xor di_dly(47) xor di_dly(48)
                      xor di_dly(53) xor di_dly(54) xor di_dly(55) xor di_dly(56)
                      xor di_dly(60) xor di_dly(61) xor di_dly(62) xor di_dly(63);
	
              dip_ecc(3) := di_dly(4) xor di_dly(5) xor di_dly(6) xor di_dly(7) xor di_dly(8) xor di_dly(9)
		      xor di_dly(10) xor di_dly(18) xor di_dly(19)
                      xor di_dly(20) xor di_dly(21) xor di_dly(22) xor di_dly(23) xor di_dly(24) xor di_dly(25)
                      xor di_dly(33) xor di_dly(34) xor di_dly(35) xor di_dly(36) xor di_dly(37) xor di_dly(38) xor di_dly(39)
                      xor di_dly(40) xor di_dly(49)
                      xor di_dly(50) xor di_dly(51) xor di_dly(52) xor di_dly(53) xor di_dly(54) xor di_dly(55) xor di_dly(56);

              dip_ecc(4) := di_dly(11) xor di_dly(12) xor di_dly(13) xor di_dly(14) xor di_dly(15) xor di_dly(16) xor di_dly(17) xor di_dly(18) xor di_dly(19)
                      xor di_dly(20) xor di_dly(21) xor di_dly(22) xor di_dly(23) xor di_dly(24) xor di_dly(25)
                      xor di_dly(41) xor di_dly(42) xor di_dly(43) xor di_dly(44) xor di_dly(45) xor di_dly(46) xor di_dly(47) xor di_dly(48) xor di_dly(49)
                      xor di_dly(50) xor di_dly(51) xor di_dly(52) xor di_dly(53) xor di_dly(54) xor di_dly(55) xor di_dly(56);


              dip_ecc(5) := di_dly(26) xor di_dly(27) xor di_dly(28) xor di_dly(29)
                      xor di_dly(30) xor di_dly(31) xor di_dly(32) xor di_dly(33) xor di_dly(34) xor di_dly(35) xor di_dly(36) xor di_dly(37) xor di_dly(38)
	              xor di_dly(39) xor di_dly(40) xor di_dly(41) xor di_dly(42) xor di_dly(43) xor di_dly(44) xor di_dly(45) xor di_dly(46) xor di_dly(47)
                      xor di_dly(48) xor di_dly(49) xor di_dly(50) xor di_dly(51) xor di_dly(52) xor di_dly(53) xor di_dly(54) xor di_dly(55) xor di_dly(56);

              dip_ecc(6) := di_dly(57) xor di_dly(58) xor di_dly(59)
                      xor di_dly(60) xor di_dly(61) xor di_dly(62) xor di_dly(63);

              dip_ecc(7) := dip_ecc(0) xor dip_ecc(1) xor dip_ecc(2) xor dip_ecc(3) xor dip_ecc(4) xor dip_ecc(5) xor dip_ecc(6)
                      xor di_dly(0) xor di_dly(1) xor di_dly(2) xor di_dly(3) xor di_dly(4) xor di_dly(5) xor di_dly(6) xor di_dly(7) xor di_dly(8) xor di_dly(9)
                      xor di_dly(10) xor di_dly(11) xor di_dly(12) xor di_dly(13) xor di_dly(14) xor di_dly(15) xor di_dly(16) xor di_dly(17) xor di_dly(18)
                      xor di_dly(19) xor di_dly(20) xor di_dly(21) xor di_dly(22) xor di_dly(23) xor di_dly(24) xor di_dly(25) xor di_dly(26) xor di_dly(27)
                      xor di_dly(28) xor di_dly(29) xor di_dly(30) xor di_dly(31) xor di_dly(32) xor di_dly(33) xor di_dly(34) xor di_dly(35) xor di_dly(36)
                      xor di_dly(37) xor di_dly(38) xor di_dly(39) xor di_dly(40) xor di_dly(41) xor di_dly(42) xor di_dly(43) xor di_dly(44) xor di_dly(45)
                      xor di_dly(46) xor di_dly(47) xor di_dly(48) xor di_dly(49) xor di_dly(50) xor di_dly(51) xor di_dly(52) xor di_dly(53) xor di_dly(54)
                      xor di_dly(55) xor di_dly(56) xor di_dly(57) xor di_dly(58) xor di_dly(59) xor di_dly(60) xor di_dly(61) xor di_dly(62) xor di_dly(63);

              ECCPARITY_zd <= dip_ecc;

              dip_dly_ecc := dip_ecc;  -- only 64 bits width

            else

              dip_dly_ecc := dip_dly; -- only 64 bits width

            end if;

            mem(wr_addr_var) <= DI_dly(mem_width-1 downto 0);
            if (DATA_WIDTH >= 9) then
              memp(wr_addr_var) <= dip_dly_ecc(memp_width-1 downto 0);              
            end if;
                
            wr_addr_var := (wr_addr_var + 1) mod addr_limit;
         
            if(wr_addr_var = 0) then
              awr_flag_var := NOT awr_flag_var;
            end if;

            if(wr_addr_var = addr_limit - 1) then
              wr_flag_var := NOT wr_flag_var;
            end if;
            
        end if; -- if((wren_var = '1') and (FULL_zd = '0') ....      

        if((wren_var = '1') and (full_zd = '1')) then 
            WRERR_zd <= '1';
        else
            WRERR_zd <= '0';
        end if;

        ALMOSTFULL_var := almostfull_int(3);
        
        if((((rdcount_var + addr_limit) <= (wr_addr_var + ae_full)) and (rdcount_flag_var = awr_flag_var)) or ((rdcount_var <= (wr_addr_var + ae_full)) and (rdcount_flag_var /= awr_flag_var))) then    
          almostfull_int(3) := '1';
          almostfull_int(2) := '1';
          almostfull_int(1) := '1';
          almostfull_int(0) := '1';
        elsif(almostfull_int(2)  = '0') then
          if (wr_addr_var <= wr_addr_var + ae_full or rdcount_flag_var = awr_flag_var) then

            almostfull_int(3) := almostfull_int(0);
            almostfull_int(0) :=  '0';

          end if;
        end if;

        if (wren_var = '1' or full_zd = '1') then
          full_zd <= full_int(1);
        end if;

        if(((rdcount_var = wr_addr_var) or (rdcount_var - 1 = wr_addr_var or rdcount_var + addr_limit - 1 = wr_addr_var)) and ALMOSTFULL_var = '1') then
          full_int(1) := '1';
          full_int(0) := '1';
        else
          full_int(1) := full_int(0);
          full_int(0) := '0';
        end if;

        update_from_write_prcs <= NOT update_from_write_prcs;
        ALMOSTFULL_zd <= ALMOSTFULL_var;

      end if; -- if (sync)
  
        WRCOUNT_zd <= CONV_STD_LOGIC_VECTOR( wr_addr_var, MAX_WRCOUNT);

        wr_addr <= wr_addr_var;
        wr_flag <= wr_flag_var;
        awr_flag <= awr_flag_var;

    end if; -- if(rising(WRCLK_dly))

  end if; -- if(GSR_dly = '1'))


    if(update_from_read_prcs_sync'event) then
      rdcount_var := SLV_TO_INT(RDCOUNT_zd);
      rdcount_flag_var := rdcount_flag;
      if((((rdcount_var + addr_limit) > (wr_addr_var + ae_full)) and (rdcount_flag_var = wr_flag_var)) or ((rdcount_var > (wr_addr_var + ae_full)) and (rdcount_flag_var /= wr_flag_var))) then
        if (wr_addr_var <= wr_addr_var + ae_full or rdcount_flag_var = wr_flag_var) then
          ALMOSTFULL_zd <= '0';
        end if;
      end if;
    end if;

    if(update_from_read_prcs'event) then
       rdcount_var := SLV_TO_INT(RDCOUNT_zd);
       rdcount_flag_var := rdcount_flag;

       if((((rdcount_var + addr_limit) > (wr_addr_var + ae_full)) and (rdcount_flag_var = awr_flag_var)) or ((rdcount_var > (wr_addr_var + ae_full)) and (rdcount_flag_var /= awr_flag_var))) then    

           if(((rden_var = '1') and (EMPTY_zd = '0')) or ((((rd_addr_var + 1) mod addr_limit) = rdcount_var) and (almostfull_int(1) = '1'))) then
              almostfull_int(2) := almostfull_int(1);
              almostfull_int(1) := '0';
           end if;
       else
           almostfull_int(2) := '1';
           almostfull_int(1) := '1';
       end if;
    end if;

  end process prcs_write;

  
  outmux: process (DO_zd, DOP_zd, DO_OUTREG_zd, DOP_OUTREG_zd)
  begin  -- process outmux_clka

    if (sync = '1') then
      
      case DO_REG is
        when 0 =>
                  DO_OUT_MUX_zd <= DO_zd;
                  DOP_OUT_MUX_zd <= DOP_zd;
        when 1 =>
                  DO_OUT_MUX_zd <= DO_OUTREG_zd;
                  DOP_OUT_MUX_zd <= DOP_OUTREG_zd;
        when others => assert false
                       report "Attribute Syntax Error: The allowed integer values for DO_REG are 0 or 1."
                       severity Failure;
      end case;

    else
      DO_OUT_MUX_zd <= DO_zd;
      DOP_OUT_MUX_zd <= DOP_zd;
    end if;
    
  end process outmux;
  

  -- matching HW behavior to pull up and X the unused output bits
  prcs_x_1_output: process (WRCOUNT_zd, RDCOUNT_zd, DO_OUT_MUX_zd, DOP_OUT_MUX_zd, RST_dly, GSR_dly, rst_rdclk_flag, rst_wrclk_flag)
  begin  -- process prcs_x_1_output

    if((GSR_dly = '1') or (RST_dly = '1')) then
      RDCOUNT_OUT_zd <= (others => '0');
      WRCOUNT_OUT_zd <= (others => '0');
    elsif ((rst_rdclk_flag = '1') or (rst_wrclk_flag = '1'))then
      RDCOUNT_OUT_zd <= (others => 'X');
      WRCOUNT_OUT_zd <= (others => 'X');
    else
      
      if (FIFO_SIZE = 18) then
      
        case DATA_WIDTH is
          when 4  => 
                  WRCOUNT_OUT_zd(12 downto 0) <= '1' & WRCOUNT_zd(11 downto 0);
                  RDCOUNT_OUT_zd(12 downto 0) <= '1' & RDCOUNT_zd(11 downto 0);
                  DO_OUT_zd(3 downto 0) <= DO_OUT_MUX_zd(3 downto 0);
          when 9  =>
                  WRCOUNT_OUT_zd(12 downto 0) <= "11" & WRCOUNT_zd(10 downto 0);
                  RDCOUNT_OUT_zd(12 downto 0) <= "11" & RDCOUNT_zd(10 downto 0);
                  DO_OUT_zd(7 downto 0) <= DO_OUT_MUX_zd(7 downto 0);
                  DOP_OUT_zd(0 downto 0) <= DOP_OUT_MUX_zd(0 downto 0);
          when 18 =>
                  WRCOUNT_OUT_zd(12 downto 0) <= "111" & WRCOUNT_zd(9 downto 0);
                  RDCOUNT_OUT_zd(12 downto 0) <= "111" & RDCOUNT_zd(9 downto 0);
                  DO_OUT_zd(15 downto 0) <= DO_OUT_MUX_zd(15 downto 0);
                  DOP_OUT_zd(1 downto 0) <= DOP_OUT_MUX_zd(1 downto 0);
          when 36 => 
                  WRCOUNT_OUT_zd(12 downto 0) <= "1111" & WRCOUNT_zd(8 downto 0);
                  RDCOUNT_OUT_zd(12 downto 0) <= "1111" & RDCOUNT_zd(8 downto 0);
                  DO_OUT_zd(31 downto 0) <= DO_OUT_MUX_zd(31 downto 0);
                  DOP_OUT_zd(3 downto 0) <= DOP_OUT_MUX_zd(3 downto 0);
          when others =>
                  WRCOUNT_OUT_zd <= WRCOUNT_zd;
                  RDCOUNT_OUT_zd <= RDCOUNT_zd;
                  DO_OUT_zd <= DO_OUT_MUX_zd;
        end case;   

      else

        case DATA_WIDTH is
          when 4  => 
                  WRCOUNT_OUT_zd(12 downto 0) <= WRCOUNT_zd(12 downto 0);
                  RDCOUNT_OUT_zd(12 downto 0) <= RDCOUNT_zd(12 downto 0);
                  DO_OUT_zd(3 downto 0) <= DO_OUT_MUX_zd(3 downto 0);
          when 9  =>
                  WRCOUNT_OUT_zd(12 downto 0) <= '1' & WRCOUNT_zd(11 downto 0);
                  RDCOUNT_OUT_zd(12 downto 0) <= '1' & RDCOUNT_zd(11 downto 0);
                  DO_OUT_zd(7 downto 0) <= DO_OUT_MUX_zd(7 downto 0);
                  DOP_OUT_zd(0 downto 0) <= DOP_OUT_MUX_zd(0 downto 0);
          when 18 =>
                  WRCOUNT_OUT_zd(12 downto 0) <= "11" & WRCOUNT_zd(10 downto 0);
                  RDCOUNT_OUT_zd(12 downto 0) <= "11" & RDCOUNT_zd(10 downto 0);
                  DO_OUT_zd(15 downto 0) <= DO_OUT_MUX_zd(15 downto 0);
                  DOP_OUT_zd(1 downto 0) <= DOP_OUT_MUX_zd(1 downto 0);
          when 36 => 
                  WRCOUNT_OUT_zd(12 downto 0) <= "111" & WRCOUNT_zd(9 downto 0);
                  RDCOUNT_OUT_zd(12 downto 0) <= "111" & RDCOUNT_zd(9 downto 0);
                  DO_OUT_zd(31 downto 0) <= DO_OUT_MUX_zd(31 downto 0);
                  DOP_OUT_zd(3 downto 0) <= DOP_OUT_MUX_zd(3 downto 0);
          when 72 => 
                  WRCOUNT_OUT_zd(12 downto 0) <= "1111" & WRCOUNT_zd(8 downto 0);
                  RDCOUNT_OUT_zd(12 downto 0) <= "1111" & RDCOUNT_zd(8 downto 0);
                  DO_OUT_zd(63 downto 0) <= DO_OUT_MUX_zd(63 downto 0);
                  DOP_OUT_zd(7 downto 0) <= DOP_OUT_MUX_zd(7 downto 0);          
          when others =>
                  WRCOUNT_OUT_zd <= WRCOUNT_zd;
                  RDCOUNT_OUT_zd <= RDCOUNT_zd;
                  DO_OUT_zd <= DO_OUT_MUX_zd;
        end case;
         
      end if;

    end if;
    
  end process prcs_x_1_output;

  
  end generate;

-------------------------------------------------------------------------------
-- FAST mode
-------------------------------------------------------------------------------

  fast_mode : if (SIM_MODE = "FAST") generate


--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_initialize:process
  variable first_time        : boolean    := true;
  variable addr_limit_var    : integer    := 0; 
  variable fwft_var          : std_ulogic := 'X';
  variable rd_offset_stdlogic : std_logic_vector (ALMOST_EMPTY_OFFSET'length-1 downto 0);
  variable rd_offset_int : integer := 0;
  variable wr_offset_stdlogic : std_logic_vector (ALMOST_FULL_OFFSET'length-1 downto 0);
  variable wr_offset_int : integer := 0;
  variable Message : LINE;
  variable ae_empty_var      : integer := 0;
  variable ae_full_var       : integer := 0;
  
  begin
     if (first_time) then

       if (SIM_MODE /= "FAST" and SIM_MODE /= "SAFE") then
        GenericValueCheckMessage
          ( HeaderMsg            => " Attribute Syntax Error : ",
            GenericName          => " SIM_MODE ",
            EntityName           => "AFIFO36_INTERNAL",
            GenericValue         => SIM_MODE,
            Unit                 => "",
            ExpectedValueMsg     => " The Legal values for this attribute are ",
            ExpectedGenericValue => " FAST or SAFE ",
            TailMsg              => "",
            MsgSeverity          => failure
            );
       end if;

       
       case EN_SYN is
            when TRUE  => sync <= '1';
            when FALSE => sync <= '0';
            when others =>
       end case;

       
       case DATA_WIDTH is
            when 4  => if (FIFO_SIZE = 36) then
                         addr_limit_var := 8192;
                       else                         
                         addr_limit_var := 4096;
                       end if;     
            when 9  => if (FIFO_SIZE = 36) then
                         addr_limit_var := 4096;
                       else                         
                         addr_limit_var := 2048;
                       end if;
            when 18 => if (FIFO_SIZE = 36) then
                         addr_limit_var := 2048;
                       else                         
                         addr_limit_var := 1024;
                       end if;
            when 36 => if (FIFO_SIZE = 36) then
                         addr_limit_var := 1024;
                       else                         
                         addr_limit_var := 512;
                       end if;
            when 72 =>
                       addr_limit_var := 512;

            when others =>
        end case;

       rd_offset_stdlogic := To_StdLogicVector(ALMOST_EMPTY_OFFSET);
       rd_offset_int := SLV_TO_INT(rd_offset_stdlogic);

       wr_offset_stdlogic := To_StdLogicVector(ALMOST_FULL_OFFSET);
       wr_offset_int := SLV_TO_INT(wr_offset_stdlogic);

       case FIRST_WORD_FALL_THROUGH is
            when TRUE  =>
                         fwft_var     := '1';
                         ae_empty_var := rd_offset_int - 2;
                         ae_full_var := wr_offset_int;
            when FALSE =>
                         fwft_var     := '0';
                         if (EN_SYN = FALSE) then
                           ae_empty_var := rd_offset_int - 1;
                           ae_full_var := wr_offset_int;
                         else
                           ae_empty_var := rd_offset_int;
                           ae_full_var := wr_offset_int;
                         end if;
         when others =>
       end case;

       
       addr_limit_fast <= addr_limit_var;
       fwft       <= fwft_var;
       ae_full_fast    <= ae_full_var;
       ae_empty_fast   <= ae_empty_var;
       first_time := false;
     end if;
     wait;
  end process prcs_initialize;


--####################################################################
--#####                         Read                             #####
--####################################################################
  prcs_read:process(RDCLK_dly, RST_dly, GSR_dly, update_from_write_prcs, update_from_write_prcs_sync, rst_rdclk_flag, rst_wrclk_flag)
  variable first_time        : boolean    := true;
  variable rd_addr_var       : integer    := 0;
  variable wr_addr_var       : integer    := 0;
  variable rdcount_var       : integer    := 0;

  variable rd_flag_var       : std_ulogic := '0';
  variable wr_flag_var       : std_ulogic := '0';
  variable awr_flag_var       : std_ulogic := '0';  

  variable rdcount_flag_var  : std_ulogic := '0';

  variable do_in             : std_logic_vector(MSB_MAX_DO  downto 0)    := (others => '0');
  variable dop_in            : std_logic_vector(MSB_MAX_DOP downto 0)    := (others => '0');

  variable almostempty_int   : std_ulogic_vector(3 downto 0) := (others => '1');
  variable empty_int         : std_ulogic_vector(3 downto 0) := (others => '1');
  variable empty_ram         : std_ulogic_vector(3 downto 0) := (others => '1');

  variable addr_limit_var    : integer    := 0;

  variable wr1_addr_var      : integer := 0;
  variable wr1_flag_var      : std_ulogic := '0';
  variable rd_prefetch_var   : integer := 0;
  variable rd_prefetch_flag_var  : std_ulogic := '0';

-- CR 195129  fix from verilog (may not be necessary for vhdl)
-- Added ren_var/wren_var to remember the old val of RDEN_dly/WREN_dly

  variable rden_var  : std_ulogic := '0';
  variable wren_var  : std_ulogic := '0';

  variable do_buf : std_logic_vector(MSB_MAX_DO downto 0) := (others => '0');
  variable dop_buf : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0');
  variable dopr_ecc : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0');
  variable tmp_syndrome_int : integer;    
  variable syndrome : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0');
  variable ecc_bit_position : std_logic_vector(71 downto 0) := (others => '0');
  variable di_dly_ecc_corrected : std_logic_vector(MSB_MAX_DO downto 0) := (others => '0');
  variable dip_dly_ecc_corrected : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0');
  variable sbiterr_out : std_ulogic := '0';
  variable dbiterr_out : std_ulogic := '0';
  variable sbiterr_out_out_var : std_ulogic := '0';
  variable dbiterr_out_out_var : std_ulogic := '0';
  variable DO_OUTREG_var: std_logic_vector(MSB_MAX_DO downto 0) := (others => '0');
  variable DOP_OUTREG_var : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0');

  begin
     if((GSR_dly = '1') or (RST_dly = '1')) then
       rd_addr_fast <= 0;
       rd_flag <= '0';

       rd_addr_var  := 0;
       wr_addr_var  := 0;
       wr1_addr_var := 0;
       rd_prefetch_var := 0;
   
       rdcount_var := 0;
       
       rd_flag_var  := '0';
       wr_flag_var  := '0';
       awr_flag_var  := '0';       
       wr1_flag_var := '0';
       rd_prefetch_flag_var := '0';
  
       rdcount_flag_var := '0';

       empty_int       :=  (others => '1');
       almostempty_int :=  (others => '1');
       empty_ram       :=  (others => '1');

       sbiterr_zd <= '0';
       dbiterr_zd <= '0';
       
       ALMOSTEMPTY_zd <= '1';
       EMPTY_zd <= '1';
       RDERR_zd <= '0';
       RDCOUNT_zd <= (others => '0');
  
       if(GSR_dly = '1') then
         DO_zd((mem_width -1) downto 0) <= (others => '0');
         DO_OUTREG_zd((mem_width -1) downto 0) <= (others => '0');
         if (DATA_WIDTH /= 4) then
           DOP_zd((memp_width -1) downto 0) <= (others => '0');
           DOP_OUTREG_zd((memp_width -1) downto 0) <= (others => '0');
         end if;
       end if;

     elsif ((rst_rdclk_flag = '1') or (rst_wrclk_flag = '1'))then

       rd_addr_fast <= 0;
       rd_flag <= '0';

       rd_addr_var  := 0;
       wr_addr_var  := 0;
       wr1_addr_var := 0;
       rd_prefetch_var := 0;
   
       rdcount_var := 0;
       
       rd_flag_var  := '0';
       wr_flag_var  := '0';
       awr_flag_var  := '0';       
       wr1_flag_var := '0';
       rd_prefetch_flag_var := '0';
  
       rdcount_flag_var := '0';

       empty_int       :=  (others => '1');
       almostempty_int :=  (others => '1');
       empty_ram       :=  (others => '1');

       ALMOSTEMPTY_zd <= 'X';
       EMPTY_zd <= 'X';
       RDERR_zd <= 'X';
       RDCOUNT_zd <= (others => 'X');
       
       sbiterr_zd <= 'X';
       dbiterr_zd <= 'X';

       DO_zd((mem_width -1) downto 0) <= (others => 'X');
       DO_OUTREG_zd((mem_width -1) downto 0) <= (others => 'X');

       if (DATA_WIDTH /= 4) then
         DOP_zd((memp_width -1) downto 0) <= (others => 'X');
         DOP_OUTREG_zd((memp_width -1) downto 0) <= (others => 'X');
       end if;
       
     elsif ((GSR_dly = '0') and (RST_dly = '0'))then

       rden_var := RDEN_dly;
       wren_var := WREN_dly;

       if(rising_edge(RDCLK_dly)) then

         rd_flag_var := rd_flag;
         wr_flag_var := wr_flag;
         awr_flag_var := awr_flag;

         rd_addr_var := rd_addr_fast;
         wr_addr_var := wr_addr_fast;

         rdcount_var := SLV_TO_INT(RDCOUNT_zd);
         rdcount_flag_var := rdcount_flag;


         if (sync = '1') then
           
           DO_OUTREG_var := DO_zd;
           DOP_OUTREG_var := DOP_zd;

           if (RDEN_dly = '1') then

             if (EMPTY_zd = '0') then

               DO_zd(mem_width-1 downto 0) <= mem(rdcount_var);
               DOP_zd(memp_width-1 downto 0) <= memp(rdcount_var);
               
               rdcount_var := (rdcount_var + 1) mod addr_limit_fast;

               if (rdcount_var = 0) then
                 rdcount_flag_var := not rdcount_flag_var;
               end if;

             end if;
           end if;


           if (RDEN_dly = '1' and EMPTY_zd = '1') then
             RDERR_zd <= '1';
           else
             RDERR_zd <= '0';
           end if;
           
           
           if (WREN_dly = '1') then
             EMPTY_zd <= '0';
           elsif (rdcount_var = wr_addr_var and rdcount_flag_var = wr_flag_var) then
             EMPTY_zd <= '1';
           end if;
             
           if((((rdcount_var + ae_empty_fast) >= wr_addr_var) and (rdcount_flag_var = wr_flag_var)) or (((rdcount_var + ae_empty_fast) >= (wr_addr_var + addr_limit_fast)) and (rdcount_flag_var /= wr_flag_var))) then    
             ALMOSTEMPTY_zd <= '1';
           end if;

           update_from_read_prcs_sync <= not update_from_read_prcs_sync;

       elsif (sync = '0') then

         dbiterr_out_out_var := dbiterr_out; -- reg out in async mode
         sbiterr_out_out_var := sbiterr_out;
                    
         if(fwft = '0') then
           addr_limit_var := addr_limit_fast;
           if((rden_var = '1') and (rd_addr_var /= rdcount_var)) then
              DO_zd   <= do_in;
              if (DATA_WIDTH /= 4) then
                DOP_zd  <= dop_in;
              end if;
              rd_addr_var  := (rd_addr_var + 1) mod addr_limit_fast;
              if(rd_addr_var = 0) then 
                  rd_flag_var := NOT rd_flag_var;
              end if;
           end if;
           if (((rd_addr_var = rdcount_var) and (empty_ram(3) = '0')) or 
              ((rden_var = '1') and (empty_ram(1) = '0'))) then
                do_in(mem_width-1 downto 0) := mem(rdcount_var);
                dop_in(memp_width-1 downto 0) := memp(rdcount_var);
 
             rdcount_var := (rdcount_var + 1) mod addr_limit_fast;

              if(rdcount_var = 0) then
                 rdcount_flag_var := NOT rdcount_flag_var;
              end if;

         end if;
         
         elsif(fwft = '1') then
           if((rden_var = '1') and (rd_addr_var /= rd_prefetch_var)) then
              rd_prefetch_var := (rd_prefetch_var + 1) mod addr_limit_fast;
              if(rd_prefetch_var = 0) then 
                  rd_prefetch_flag_var := NOT rd_prefetch_flag_var;
              end if;
           end if;
           if((rd_prefetch_var = rd_addr_var) and (rd_addr_var /= rdcount_var)) then
             DO_zd   <= do_in;
             if (DATA_WIDTH /= 4) then
               DOP_zd <= dop_in;
             end if;
             rd_addr_var  := (rd_addr_var + 1) mod addr_limit_fast;
             if(rd_addr_var = 0) then 
                rd_flag_var := NOT rd_flag_var;
             end if;
           end if;
           if(((rd_addr_var = rdcount_var) and (empty_ram(3) = '0')) or
              ((rden_var = '1')  and (empty_ram(1) = '0')) or 
              ((rden_var = '0')  and (empty_ram(1) = '0') and (rd_addr_var = rdcount_var))) then 
                do_in(mem_width-1 downto 0) := mem(rdcount_var);
                dop_in(memp_width-1 downto 0) := memp(rdcount_var);

              rdcount_var := (rdcount_var + 1) mod addr_limit_fast;

              if(rdcount_var = 0) then
                 rdcount_flag_var := NOT rdcount_flag_var;
              end if;

         end if;

       end if;  ---  end if(fwft = '1')


         ALMOSTEMPTY_zd <= almostempty_int(3);

         if((((rdcount_var + ae_empty_fast) >= wr_addr_var) and (rdcount_flag_var = awr_flag_var)) or (((rdcount_var + ae_empty_fast) >= (wr_addr_var + addr_limit_fast)) and (rdcount_flag_var /= awr_flag_var))) then    
            almostempty_int(3) := '1';
            almostempty_int(2) := '1';
            almostempty_int(1) := '1';
            almostempty_int(0) := '1';
         elsif(almostempty_int(2)  = '0') then
           -- added to match verilog
           if (rdcount_var <= rdcount_var + ae_empty_fast or rdcount_flag_var /= awr_flag_var) then
            almostempty_int(3) :=  almostempty_int(0);
            almostempty_int(0) :=  '0';
           end if;
         end if;

         if(fwft = '0') then
           if((rdcount_var = rd_addr_var) and (rdcount_flag_var = rd_flag_var)) then
              EMPTY_zd <= '1';
           else
             EMPTY_zd  <= '0';
           end if;
         elsif(fwft = '1') then
           if((rd_prefetch_var = rd_addr_var) and (rd_prefetch_flag_var = rd_flag_var)) then
             EMPTY_zd <=  '1';
           else
             EMPTY_zd  <= '0';
           end if;
         end if;   
          
         if((rdcount_var = wr_addr_var) and (rdcount_flag_var = awr_flag_var)) then
           empty_ram(2) := '1';
           empty_ram(1) := '1';
           empty_ram(0) := '1';
         else
           empty_ram(2) := empty_ram(1);
           empty_ram(1) := empty_ram(0);
           empty_ram(0) := '0';
         end if;
           
         if((rdcount_var = wr1_addr_var) and (rdcount_flag_var = wr1_flag_var)) then
           empty_ram(3) := '1';
         else
           empty_ram(3) := '0';
         end if;

         wr1_addr_var := wr_addr_fast;
         wr1_flag_var := awr_flag;

         if((rden_var = '1') and (EMPTY_zd = '1')) then
             RDERR_zd <= '1';
         else
             RDERR_zd <= '0';
         end if; -- end ((rden_var = '1') and (empty_int /= '1'))

        update_from_read_prcs <= NOT update_from_read_prcs;

       end if;
       
     end if; -- end (rising_edge(RDCLK_dly))

  end if; -- end (GSR_dly = 1)



     if(update_from_write_prcs_sync'event) then
       wr_addr_var := wr_addr_fast;
       wr_flag_var := wr_flag;
       if((((rdcount_var + ae_empty_fast) <  wr_addr_var)  and (rdcount_flag_var = wr_flag_var)) or 
          (((rdcount_var + ae_empty_fast) < (wr_addr_var + addr_limit_fast)) and (rdcount_flag_var /= wr_flag_var))) then    
          if(rdcount_var <= rdcount_var + ae_empty_fast or rdcount_flag_var /= wr_flag_var) then
            almostempty_zd <= '0';
          end if;
       end if;
     end if;
  
     
     if(update_from_write_prcs'event) then
       wr_addr_var := wr_addr_fast;
       wr_flag_var := wr_flag;
       awr_flag_var := awr_flag;

       if((((rdcount_var + ae_empty_fast) <  wr_addr_var)  and (rdcount_flag_var = awr_flag_var)) or 
          (((rdcount_var + ae_empty_fast) <  ( wr_addr_var + addr_limit_fast)) and (rdcount_flag_var /= awr_flag_var))) then    
         if(wren_var = '1') then
             almostempty_int(2) := almostempty_int(1);
             almostempty_int(1) := '0';
          end if;
       else
           almostempty_int(2) := '1';
           almostempty_int(1) := '1';
       end if;
     end if;
  
  
     if (not (rst_rdclk_flag or rst_wrclk_flag) = '1') then
       RDCOUNT_zd <= CONV_STD_LOGIC_VECTOR(rdcount_var, MAX_RDCOUNT);       
       dbiterr_zd <= dbiterr_out_out_var; -- reg out in async mode
       sbiterr_zd <= sbiterr_out_out_var;
     end if;

     rd_addr_fast <= rd_addr_var;
     rd_flag <= rd_flag_var;
     rdcount_flag <= rdcount_flag_var;
     DO_OUTREG_zd <= DO_OUTREG_var;
     DOP_OUTREG_zd <= DOP_OUTREG_var;

  end process prcs_read;

--####################################################################
--#####                         Write                            #####
--####################################################################
  prcs_write:process(WRCLK_dly, RST_dly, GSR_dly, update_from_read_prcs, update_from_read_prcs_sync, rst_rdclk_flag, rst_wrclk_flag)
  variable first_time        : boolean    := true;
  variable wr_addr_var       : integer := 0;
  variable rd_addr_var       : integer := 0;
  variable rdcount_var       : integer := 0;
  variable wrcount_var       : integer := 0;

  variable rd_flag_var       : std_ulogic := '0';
  variable wr_flag_var       : std_ulogic := '0';
  variable awr_flag_var       : std_ulogic := '0';

  variable rdcount_flag_var  : std_ulogic := '0';

  variable almostfull_int : std_ulogic_vector(3 downto 0) := (others => '0');
  variable full_int       : std_ulogic_vector(3 downto 0) := (others => '0');

-- CR 195129  fix from verilog (may not be necessary for vhdl)
-- Added ren_var/wren_var to remember the old val of RDEN_dly/WREN_dly

  variable rden_var  : std_ulogic := '0';
  variable wren_var  : std_ulogic := '0';
  variable dip_ecc : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0');
  variable dip_dly_ecc : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0');
  variable ALMOSTFULL_var : std_ulogic     :=    '0';

  begin
    if ((GSR_dly = '1') or (RST_dly = '1') or (rst_rdclk_flag = '1') or (rst_wrclk_flag = '1'))then
        wr_addr_var := 0;
        wr_addr_fast <=  0;
        wr_flag <= '0';
        awr_flag <= '0';
        
        wr_addr_var := 0;
        rd_addr_var := 0;
        rdcount_var := 0;
        wrcount_var := 0;
        ALMOSTFULL_var := '0';
   
        rd_flag_var := '0';
        wr_flag_var := '0';
        awr_flag_var := '0';

        rdcount_flag_var  := '0';

        full_int       :=  (others => '0');
        almostfull_int :=  (others => '0');

        if ((GSR_dly = '1') or (RST_dly = '1'))then
          ALMOSTFULL_zd <= '0';      
          FULL_zd <= '0';            
          WRERR_zd <= '0';           
          WRCOUNT_zd <= (others => '0');
        else
          ALMOSTFULL_zd <= 'X';       
          FULL_zd <= 'X';             
          WRERR_zd <= 'X';            
          WRCOUNT_zd <= (others => 'X');
          eccparity_zd <= (others => 'X');
        end if;

    elsif((GSR_dly = '0') and (RST_dly = '0'))then
      rden_var := RDEN_dly;
      wren_var := WREN_dly;

      if(rising_edge(WRCLK_dly)) then

        rd_flag_var := rd_flag;
        wr_flag_var := wr_flag;
        awr_flag_var := awr_flag;        

        rd_addr_var := rd_addr_fast;
        wr_addr_var := wr_addr_fast;

        rdcount_var := SLV_TO_INT(RDCOUNT_zd);
        rdcount_flag_var := rdcount_flag;

	if (sync = '1') then
          if(wren_dly = '1') then
            if (full_zd= '0') then

            mem(wr_addr_var) <= DI_dly(mem_width-1 downto 0);
            memp(wr_addr_var) <= dip_dly_ecc(memp_width-1 downto 0);

            wr_addr_var := (wr_addr_var + 1) mod addr_limit_fast;

            if(wr_addr_var = 0) then
              wr_flag_var := NOT wr_flag_var;
            end if;

          end if;
        end if;


        if ((WREN_dly = '1') and (FULL_zd = '1')) then
          WRERR_zd <= '1';
        else
          WRERR_zd <= '0';
        end if;

        
        if (rden_dly = '1') then
          full_zd <= '0';
        elsif (rdcount_var = wr_addr_var and rdcount_flag_var /= wr_flag_var) then
          full_zd <= '1';
        end if;

        update_from_write_prcs_sync <= NOT update_from_write_prcs_sync;

        if((((rdcount_var + addr_limit_fast) <= (wr_addr_var + ae_full_fast)) and (rdcount_flag_var = wr_flag_var)) or ((rdcount_var <= (wr_addr_var + ae_full_fast)) and (rdcount_flag_var /= wr_flag_var))) then
          almostfull_zd <= '1';
        end if;
        

      elsif (sync = '0') then

        if((wren_var = '1') and (full_zd = '0'))then  

            mem(wr_addr_var) <= DI_dly(mem_width-1 downto 0);
            if (DATA_WIDTH >= 9) then
              memp(wr_addr_var) <= dip_dly_ecc(memp_width-1 downto 0);              
            end if;
                
            wr_addr_var := (wr_addr_var + 1) mod addr_limit_fast;
         
            if(wr_addr_var = 0) then
              awr_flag_var := NOT awr_flag_var;
            end if;

            if(wr_addr_var = addr_limit_fast - 1) then
              wr_flag_var := NOT wr_flag_var;
            end if;
            
        end if; -- if((wren_var = '1') and (FULL_zd = '0') ....      

        if((wren_var = '1') and (full_zd = '1')) then 
            WRERR_zd <= '1';
        else
            WRERR_zd <= '0';
        end if;

        ALMOSTFULL_var := almostfull_int(3);
        
        if((((rdcount_var + addr_limit_fast) <= (wr_addr_var + ae_full_fast)) and (rdcount_flag_var = awr_flag_var)) or ((rdcount_var <= (wr_addr_var + ae_full_fast)) and (rdcount_flag_var /= awr_flag_var))) then    
          almostfull_int(3) := '1';
          almostfull_int(2) := '1';
          almostfull_int(1) := '1';
          almostfull_int(0) := '1';
        elsif(almostfull_int(2)  = '0') then
          if (wr_addr_var <= wr_addr_var + ae_full_fast or rdcount_flag_var = awr_flag_var) then

            almostfull_int(3) := almostfull_int(0);
            almostfull_int(0) :=  '0';

          end if;
        end if;

        if (wren_var = '1' or full_zd = '1') then
          full_zd <= full_int(1);
        end if;

        if(((rdcount_var = wr_addr_var) or (rdcount_var - 1 = wr_addr_var or rdcount_var + addr_limit_fast - 1 = wr_addr_var)) and ALMOSTFULL_var = '1') then
          full_int(1) := '1';
          full_int(0) := '1';
        else
          full_int(1) := full_int(0);
          full_int(0) := '0';
        end if;

        update_from_write_prcs <= NOT update_from_write_prcs;
        ALMOSTFULL_zd <= ALMOSTFULL_var;

      end if; -- if (sync)
  
        WRCOUNT_zd <= CONV_STD_LOGIC_VECTOR( wr_addr_var, MAX_WRCOUNT);

        wr_addr_fast <= wr_addr_var;
        wr_flag <= wr_flag_var;
        awr_flag <= awr_flag_var;

    end if; -- if(rising(WRCLK_dly))

  end if; -- if(GSR_dly = '1'))


    if(update_from_read_prcs_sync'event) then
      rdcount_var := SLV_TO_INT(RDCOUNT_zd);
      rdcount_flag_var := rdcount_flag;
      if((((rdcount_var + addr_limit_fast) > (wr_addr_var + ae_full_fast)) and (rdcount_flag_var = wr_flag_var)) or ((rdcount_var > (wr_addr_var + ae_full_fast)) and (rdcount_flag_var /= wr_flag_var))) then
        if (wr_addr_var <= wr_addr_var + ae_full_fast or rdcount_flag_var = wr_flag_var) then
          ALMOSTFULL_zd <= '0';
        end if;
      end if;
    end if;

    if(update_from_read_prcs'event) then
       rdcount_var := SLV_TO_INT(RDCOUNT_zd);
       rdcount_flag_var := rdcount_flag;

       if((((rdcount_var + addr_limit_fast) > (wr_addr_var + ae_full_fast)) and (rdcount_flag_var = awr_flag_var)) or ((rdcount_var > (wr_addr_var + ae_full_fast)) and (rdcount_flag_var /= awr_flag_var))) then    

           if(((rden_var = '1') and (EMPTY_zd = '0')) or ((((rd_addr_var + 1) mod addr_limit_fast) = rdcount_var) and (almostfull_int(1) = '1'))) then
              almostfull_int(2) := almostfull_int(1);
              almostfull_int(1) := '0';
           end if;
       else
           almostfull_int(2) := '1';
           almostfull_int(1) := '1';
       end if;
    end if;

  end process prcs_write;

  
  outmux: process (DO_zd, DOP_zd, DO_OUTREG_zd, DOP_OUTREG_zd)
  begin  -- process outmux_clka

    if (sync = '1') then
      
      case DO_REG is
        when 0 =>
                  DO_OUT_zd <= DO_zd;
                  DOP_OUT_zd <= DOP_zd;
        when 1 =>
                  DO_OUT_zd <= DO_OUTREG_zd;
                  DOP_OUT_zd <= DOP_OUTREG_zd;
        when others =>
      end case;

    else
      DO_OUT_zd <= DO_zd;
      DOP_OUT_zd <= DOP_zd;
    end if;
    
  end process outmux;
  

  -- matching HW behavior to pull up and X the unused output bits
  prcs_x_1_output: process (WRCOUNT_zd, RDCOUNT_zd, RST_dly, GSR_dly)
  begin  -- process prcs_x_1_output

    if ((GSR_dly = '1') or (RST_dly = '1')) then
      RDCOUNT_OUT_zd <= (others => '0');
      WRCOUNT_OUT_zd <= (others => '0');
    else
      RDCOUNT_OUT_zd <= RDCOUNT_zd;
      WRCOUNT_OUT_zd <= WRCOUNT_zd;
    end if;
        
  end process prcs_x_1_output;

  
  end generate;


--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(ALMOSTEMPTY_zd, ALMOSTFULL_zd, DO_OUT_zd, DOP_OUT_zd, 
                      EMPTY_zd, FULL_zd, RDCOUNT_OUT_zd, RDERR_zd, 
                      WRCOUNT_OUT_zd, WRERR_zd, sbiterr_zd, dbiterr_zd)
  begin
      ALMOSTEMPTY <= ALMOSTEMPTY_zd;
      ALMOSTFULL  <= ALMOSTFULL_zd;
      DO          <= DO_OUT_zd;
      DOP         <= DOP_OUT_zd;
      EMPTY       <= EMPTY_zd;
      FULL        <= FULL_zd;
      RDCOUNT     <= RDCOUNT_OUT_zd;
      RDERR       <= RDERR_zd;
      WRCOUNT     <= WRCOUNT_OUT_zd;
      WRERR       <= WRERR_zd;
      ECCPARITY   <= ECCPARITY_zd;
      SBITERR     <= sbiterr_zd;
      DBITERR     <= dbiterr_zd;
  end process prcs_output;
--####################################################################


end AFIFO36_INTERNAL_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/aramb36_internal.vhd,v 1.28.12.1 2008/02/21 00:26:06 wloo Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2005 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : This is not an user primitive.
--  /   /                  Xilinx Functional Simulation Library Component 32K-Bit Data and 4K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : ARAMB36_INTERNAL.vhd
-- \   \  /  \    Timestamp : Tues October 18 16:43:59 PST 2005
--  \___\/\___\
--
-- Revision:
--    10/18/05 - Initial version.
--    12/14/05 - Clean up generic checking.
--    05/30/06 - Added collision feature support.
--    07/10/06 - Added 2 dimensional memory array support for Virtex 4 block ram.
--    08/21/06 - Fixed the collision error message when the address is unknown (CR 233726/344429).
--    10/09/06 - Fixed collision case when READ_WIDTH_A/B = 16 (CR 424558).
--    11/01/06 - Fixed collision (CR 427720).
--    11/02/06 - Fixed sbiterr and dbiterr of ECC (CR 427509).
--    12/06/06 - Added DRC to prevent usage of EN_ECC_SCRUB = TRUE (CR 427875).
--    12/07/06 - Updated functional warning for Virtex 4 byte write feature (CR 428207).
--    01/02/07 - Fixed parity bit for Virtex 4 byte write feature (CR 431583).
--    01/04/07 - Added support of memory file to initialize memory and parity (CR 431584).
--    02/21/07 - Added attribute check for SIM_COLLISION_CHECK (CR 433445).
--    03/01/07 - Fixed attribute check for SIM_COLLISION_CHECK (CR 435304).
--    03/14/07 - Removed attribute INITP_FILE (CR 436003).
--    03/28/07 - Disabled V4 byte write warning when READ_WIDTH_* = 0 (CR 429400).
--    04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812).
--    06/14/07 - Implemented high performace version of the model.
--    06/20/07 - Fixed collision address when cascaded block rams (CR 440250).
--    08/15/07 - Updated SSR as not supported feature in output register mode for ramb16 (CR 445314).
--    08/17/07 - Supported new memory file format (SLIB_M2.3).
--    09/18/07 - Fixed DRC check for V4 ramb16 (CR 448739).
--    10/01/07 - Added conditional statement for SSRA in cascade mode (CR 449340).
--    02/20/08 - Updated collison address when cascaded block rams (CR 451722).
-- End Revision

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_SIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_TEXTIO.all;

library STD;
use STD.TEXTIO.all;

library unisim;
use unisim.vcomponents.all;
use unisim.vpkg.all;

entity ARAMB36_INTERNAL is

  generic (

    BRAM_MODE : string := "TRUE_DUAL_PORT";
    BRAM_SIZE : integer := 36;
    DOA_REG : integer := 0;
    DOB_REG : integer := 0;
    EN_ECC_READ : boolean := FALSE;
    EN_ECC_SCRUB : boolean := FALSE;
    EN_ECC_WRITE : boolean := FALSE;    
    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_A : bit_vector := X"000000000000000000";
    INIT_B : bit_vector := X"000000000000000000";
    INIT_FILE : string := "NONE";
    RAM_EXTENSION_A : string := "NONE";
    RAM_EXTENSION_B : string := "NONE";
    READ_WIDTH_A : integer := 0;
    READ_WIDTH_B : integer := 0;
    SETUP_ALL : time := 1000 ps;
    SETUP_READ_FIRST : time := 3000 ps;
    SIM_COLLISION_CHECK : string := "ALL";
    SIM_MODE : string := "SAFE";
    SRVAL_A : bit_vector := X"000000000000000000";
    SRVAL_B : bit_vector := X"000000000000000000";
    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST";
    WRITE_WIDTH_A : integer := 0;
    WRITE_WIDTH_B : integer := 0

    );

  port (

    CASCADEOUTLATA : out std_ulogic;
    CASCADEOUTLATB : out std_ulogic;
    CASCADEOUTREGA : out std_ulogic;
    CASCADEOUTREGB : out std_ulogic;
    DBITERR : out std_ulogic;
    DOA : out std_logic_vector(63 downto 0);
    DOB : out std_logic_vector(63 downto 0);
    DOPA : out std_logic_vector(7 downto 0);
    DOPB : out std_logic_vector(7 downto 0);
    ECCPARITY : out std_logic_vector(7 downto 0);
    SBITERR : out std_ulogic;
    
    ADDRA : in std_logic_vector(15 downto 0);
    ADDRB : in std_logic_vector(15 downto 0);
    CASCADEINLATA : in std_ulogic;
    CASCADEINLATB : in std_ulogic;
    CASCADEINREGA : in std_ulogic;
    CASCADEINREGB : in std_ulogic;
    CLKA : in std_ulogic;
    CLKB : in std_ulogic;
    DIA : in std_logic_vector(63 downto 0);
    DIB : in std_logic_vector(63 downto 0);
    DIPA : in std_logic_vector(7 downto 0);
    DIPB : in std_logic_vector(7 downto 0);
    ENA : in std_ulogic;
    ENB : in std_ulogic;
    REGCEA : in std_ulogic;
    REGCEB : in std_ulogic;
    REGCLKA : in std_ulogic;
    REGCLKB : in std_ulogic;
    SSRA : in std_ulogic;
    SSRB : in std_ulogic;
    WEA : in std_logic_vector(7 downto 0);
    WEB : in std_logic_vector(7 downto 0)

  ); 
end ARAMB36_INTERNAL;

-- Architecture body --

architecture ARAMB36_INTERNAL_V of ARAMB36_INTERNAL is

    signal ADDRA_dly    : std_logic_vector(15 downto 0) := (others => 'X');
    signal CLKA_dly     : std_ulogic                    := 'X';
    signal DIA_dly      : std_logic_vector(63 downto 0) := (others => 'X');
    signal DIPA_dly     : std_logic_vector(7 downto 0)  := (others => 'X');
    signal ENA_dly      : std_ulogic                    := 'X';
    signal REGCEA_dly   : std_ulogic                    := 'X';
    signal SSRA_dly     : std_ulogic                    := 'X';
    signal WEA_dly      : std_logic_vector(7 downto 0)  := (others => 'X');
    signal CASCADEINLATA_dly      : std_ulogic          := 'X';
    signal CASCADEINREGA_dly      : std_ulogic          := 'X';
    signal ADDRB_dly    : std_logic_vector(15 downto 0) := (others => 'X');
    signal CLKB_dly     : std_ulogic                    := 'X';
    signal DIB_dly      : std_logic_vector(63 downto 0) := (others => 'X');
    signal DIPB_dly     : std_logic_vector(7 downto 0)  := (others => 'X');
    signal ENB_dly      : std_ulogic                    := 'X';
    signal REGCEB_dly   : std_ulogic                    := 'X';
    signal REGCLKA_dly   : std_ulogic                    := 'X';
    signal REGCLKB_dly   : std_ulogic                    := 'X';
    signal SSRB_dly     : std_ulogic                    := 'X';
    signal WEB_dly      : std_logic_vector(7 downto 0)  := (others => 'X');
    signal CASCADEINLATB_dly      : std_ulogic          := 'X';
    signal CASCADEINREGB_dly      : std_ulogic          := 'X';

    signal sbiterr_out : std_logic := '0';
    signal dbiterr_out : std_logic := '0';
    signal sbiterr_outreg : std_logic := '0';
    signal dbiterr_outreg : std_logic := '0';
    signal sbiterr_out_out : std_logic := '0';
    signal dbiterr_out_out : std_logic := '0';
    signal doa_out : std_logic_vector(63 downto 0) := (others => '0');
    signal dopa_out : std_logic_vector(7 downto 0) := (others => '0');
    signal doa_outreg : std_logic_vector(63 downto 0) := (others => '0');
    signal dopa_outreg : std_logic_vector(7 downto 0) := (others => '0');
    signal dob_outreg : std_logic_vector(63 downto 0) := (others => '0');
    signal dopb_outreg : std_logic_vector(7 downto 0) := (others => '0');
    signal dob_out : std_logic_vector(63 downto 0) := (others => '0');
    signal dopb_out : std_logic_vector(7 downto 0) := (others => '0');

    signal doa_out_mux : std_logic_vector(63 downto 0) := (others => '0');
    signal dopa_out_mux : std_logic_vector(7 downto 0) := (others => '0');
    signal doa_outreg_mux : std_logic_vector(63 downto 0) := (others => '0');
    signal dopa_outreg_mux : std_logic_vector(7 downto 0) := (others => '0');
    signal dob_outreg_mux : std_logic_vector(63 downto 0) := (others => '0');
    signal dopb_outreg_mux : std_logic_vector(7 downto 0) := (others => '0');
    signal dob_out_mux : std_logic_vector(63 downto 0) := (others => '0');
    signal dopb_out_mux : std_logic_vector(7 downto 0) := (others => '0');
    
    signal doa_out_out : std_logic_vector(63 downto 0) := (others => '0');
    signal dopa_out_out : std_logic_vector(7 downto 0) := (others => '0');
    signal dob_out_out : std_logic_vector(63 downto 0) := (others => '0');
    signal dopb_out_out : std_logic_vector(7 downto 0) := (others => '0');    
    signal addra_dly_15_reg : std_logic := '0';
    signal addrb_dly_15_reg : std_logic := '0';
    signal addra_dly_15_reg1 : std_logic := '0';
    signal addrb_dly_15_reg1 : std_logic := '0';
    signal cascade_a : std_logic_vector(1 downto 0) := (others => '0');
    signal cascade_b : std_logic_vector(1 downto 0) := (others => '0');
    signal GSR_dly : std_ulogic := 'X';
    signal eccparity_out : std_logic_vector(7 downto 0) := (others => 'X');
    signal SRVAL_A_STD : std_logic_vector(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A);
    signal SRVAL_B_STD : std_logic_vector(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B);
    signal INIT_A_STD : std_logic_vector(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A);
    signal INIT_B_STD : std_logic_vector(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B);
    signal di_x : std_logic_vector(63 downto 0) := (others => 'X');

  function GetWidestWidth (
    wr_width_a : in integer;
    rd_width_a : in integer;
    wr_width_b : in integer;
    rd_width_b : in integer
    ) return integer is
    variable func_widest_width : integer;
  begin
    if ((wr_width_a >= wr_width_b) and (wr_width_a >= rd_width_a) and (wr_width_a >= rd_width_b)) then
      func_widest_width := wr_width_a;
    elsif ((wr_width_b >= wr_width_a) and (wr_width_b >= rd_width_a) and (wr_width_b >= rd_width_b)) then
      func_widest_width := wr_width_b;
    elsif ((rd_width_a >= wr_width_a) and (rd_width_a >= wr_width_b) and (rd_width_a >= rd_width_b)) then
      func_widest_width := rd_width_a;
    elsif ((rd_width_b >= wr_width_a) and (rd_width_b >= wr_width_b) and (rd_width_b >= rd_width_a)) then
      func_widest_width := rd_width_b;
    end if;
    return func_widest_width;
  end;

    
  function GetWidth (
    rdwr_width : in integer
    ) return integer is
    variable func_width : integer;
  begin
    case rdwr_width is
      when 1 => func_width := 1;
      when 2 => func_width := 2;
      when 4 => func_width := 4;
      when 9 => func_width := 8;
      when 18 => func_width := 16;
      when 36 => func_width := 32;
      when 72 => func_width := 64;
      when others => func_width := 1;
    end case;
    return func_width;
  end;

    
  function GetWidthINITF (
    rdwr_width_initf : in integer
    ) return integer is
    variable func_width_initf : integer;
  begin
    case rdwr_width_initf is
      when 1 => func_width_initf := 4;
      when 2 => func_width_initf := 4;
      when 4 => func_width_initf := 4;
      when 9 => func_width_initf := 12;
      when 18 => func_width_initf := 20;
      when 36 => func_width_initf := 36;
      when 72 => func_width_initf := 72;
      when others => func_width_initf := 1;
    end case;
    return func_width_initf;
  end;

    
  function GetWidthp (
    rdwr_widthp : in integer
    ) return integer is
    variable func_widthp : integer;
  begin
    case rdwr_widthp is
      when 9 => func_widthp := 1;
      when 18 => func_widthp := 2;
      when 36 => func_widthp := 4;
      when 72 => func_widthp := 8;
--      when others => func_widthp := 1;
      when others => func_widthp := 0;
    end case;
    return func_widthp;
  end;

    
  function GetWidthpINITF (
    rdwr_widthp_initf : in integer
    ) return integer is
    variable func_widthp_initf : integer;
  begin
    case rdwr_widthp_initf is
      when 9 => func_widthp_initf := 4;
      when 18 => func_widthp_initf := 4;
      when 36 => func_widthp_initf := 4;
      when 72 => func_widthp_initf := 8;
      when others => func_widthp_initf := 1;
    end case;
    return func_widthp_initf;
  end;


  function GetWidthpTmpWidthp (
    rdwr_tmp_widthp : in integer
    ) return integer is
    variable func_widthp_tmp : integer;
  begin
    case rdwr_tmp_widthp is
      when 1 | 2 | 4 => func_widthp_tmp := 0;
      when 9 => func_widthp_tmp := 1;
      when 18 => func_widthp_tmp := 2;
      when 36 => func_widthp_tmp := 4;
      when 72 => func_widthp_tmp := 8;
      when others => func_widthp_tmp := 8;
    end case;
    return func_widthp_tmp;
  end;

    
  function GetMemoryDepth (
    rdwr_width : in integer;
    func_bram_size : in integer
    ) return integer is
    variable func_mem_depth : integer;
  begin
    case rdwr_width is
      when 1 => if (func_bram_size = 18) then
                  func_mem_depth := 16384;
                else
                  func_mem_depth := 32768;
                end if;
      when 2 => if (func_bram_size = 18) then
                  func_mem_depth := 8192;
                else
                  func_mem_depth := 16384;
                end if;
      when 4 => if (func_bram_size = 18) then
                  func_mem_depth := 4096;
                else
                  func_mem_depth := 8192;
                end if;
      when 9 => if (func_bram_size = 18) then
                  func_mem_depth := 2048;
                else
                  func_mem_depth := 4096;
                end if;
      when 18 => if (func_bram_size = 18) then
                   func_mem_depth := 1024;
                 else
                   func_mem_depth := 2048;
                 end if;
      when 36 => if (func_bram_size = 18) then
                   func_mem_depth := 512;
                 else
                   func_mem_depth := 1024;
                 end if;
      when 72 => if (func_bram_size = 18) then
                   func_mem_depth := 0;
                 else
                   func_mem_depth := 512;
                 end if;
      when others => func_mem_depth := 32768;
    end case;
    return func_mem_depth;
  end;

  
  function GetMemoryDepthP (
    rdwr_width : in integer;
    func_bram_size : in integer
    ) return integer is
    variable func_memp_depth : integer;
  begin
    case rdwr_width is
      when 9 => if (func_bram_size = 18) then
                  func_memp_depth := 2048;
                else
                  func_memp_depth := 4096;
                end if;
      when 18 => if (func_bram_size = 18) then
                   func_memp_depth := 1024;
                 else
                   func_memp_depth := 2048;
                 end if;
      when 36 => if (func_bram_size = 18) then
                   func_memp_depth := 512;
                 else
                   func_memp_depth := 1024;
                 end if;
      when 72 => if (func_bram_size = 18) then
                   func_memp_depth := 0;
                 else
                   func_memp_depth := 512;
                 end if;
      when others => func_memp_depth := 4096;
    end case;
    return func_memp_depth;
  end;

  
  function GetAddrBitLSB (
    rdwr_width : in integer
    ) return integer is
    variable func_lsb : integer;
  begin
    case rdwr_width is
      when 1 => func_lsb := 0;
      when 2 => func_lsb := 1;
      when 4 => func_lsb := 2;
      when 9 => func_lsb := 3;
      when 18 => func_lsb := 4;
      when 36 => func_lsb := 5;
      when 72 => func_lsb := 6;
      when others => func_lsb := 10;
    end case;
    return func_lsb;
  end;

    
  function GetAddrBit124 (
    rdwr_width : in integer;
    w_width : in integer
    ) return integer is
    variable func_widest_width : integer;
  begin
    case rdwr_width is
      when 1 => case w_width is
                  when 2 => func_widest_width := 0;
                  when 4 => func_widest_width := 1;
                  when 9 => func_widest_width := 2;
                  when 18 => func_widest_width := 3;
                  when 36 => func_widest_width := 4;
                  when 72 => func_widest_width := 5;
                  when others => func_widest_width := 10;
                end case;
      when 2 => case w_width is
                  when 4 => func_widest_width := 1;
                  when 9 => func_widest_width := 2;
                  when 18 => func_widest_width := 3;
                  when 36 => func_widest_width := 4;
                  when 72 => func_widest_width := 5;
                  when others => func_widest_width := 10;
                end case;
      when 4 => case w_width is
                  when 9 => func_widest_width := 2;
                  when 18 => func_widest_width := 3;
                  when 36 => func_widest_width := 4;
                  when 72 => func_widest_width := 5;
                  when others => func_widest_width := 10;
                end case;
      when others => func_widest_width := 10;
    end case;
    return func_widest_width;
  end;

  
  function GetAddrBit8 (
    rdwr_width : in integer;
    w_width : in integer
    ) return integer is
    variable func_widest_width : integer;
  begin
    case rdwr_width is
      when 9 => case w_width is
                  when 18 => func_widest_width := 3;
                  when 36 => func_widest_width := 4;
                  when 72 => func_widest_width := 5;
                  when others => func_widest_width := 10;
                end case;
      when others => func_widest_width := 10;
    end case;
    return func_widest_width;
  end;

  
  function GetAddrBit16 (
    rdwr_width : in integer;
    w_width : in integer
    ) return integer is
    variable func_widest_width : integer;
  begin
    case rdwr_width is
      when 18 => case w_width is
                  when 36 => func_widest_width := 4;
                  when 72 => func_widest_width := 5;
                  when others => func_widest_width := 10;
                end case;
      when others => func_widest_width := 10;
    end case;
    return func_widest_width;
  end;

  
  function GetAddrBit32 (
    rdwr_width : in integer;
    w_width : in integer
    ) return integer is
    variable func_widest_width : integer;
  begin
    case rdwr_width is
      when 36 => case w_width is
                  when 72 => func_widest_width := 5;
                  when others => func_widest_width := 10;
                end case;
      when others => func_widest_width := 10;
    end case;
    return func_widest_width;
  end;

  ---------------------------------------------------------------------------
  -- Function SLV_X_TO_HEX returns a hex string version of the std_logic_vector
  -- argument.
  ---------------------------------------------------------------------------
  function SLV_X_TO_HEX (
    SLV : in std_logic_vector;
    string_length : in integer
    ) return string is

    variable i : integer := 1;
    variable j : integer := 1;
    variable STR : string(string_length downto 1);
    variable nibble : std_logic_vector(3 downto 0) := "0000";
    variable full_nibble_count : integer := 0;
    variable remaining_bits : integer := 0;

  begin
    full_nibble_count := SLV'length/4;
    remaining_bits := SLV'length mod 4;
    for i in 1 to full_nibble_count loop
      nibble := SLV(((4*i) - 1) downto ((4*i) - 4));
      if (((nibble(0) xor nibble(1) xor nibble (2) xor nibble(3)) /= '1') and
          (nibble(0) xor nibble(1) xor nibble (2) xor nibble(3)) /= '0')  then
        STR(j) := 'x';
      elsif (nibble = "0000")  then
        STR(j) := '0';
      elsif (nibble = "0001")  then
        STR(j) := '1';
      elsif (nibble = "0010")  then
        STR(j) := '2';
      elsif (nibble = "0011")  then
        STR(j) := '3';
      elsif (nibble = "0100")  then
        STR(j) := '4';
      elsif (nibble = "0101")  then
        STR(j) := '5';
      elsif (nibble = "0110")  then
        STR(j) := '6';
      elsif (nibble = "0111")  then
        STR(j) := '7';
      elsif (nibble = "1000")  then
        STR(j) := '8';
      elsif (nibble = "1001")  then
        STR(j) := '9';
      elsif (nibble = "1010")  then
        STR(j) := 'a';
      elsif (nibble = "1011")  then
        STR(j) := 'b';
      elsif (nibble = "1100")  then
        STR(j) := 'c';
      elsif (nibble = "1101")  then
        STR(j) := 'd';
      elsif (nibble = "1110")  then
        STR(j) := 'e';
      elsif (nibble = "1111")  then
        STR(j) := 'f';
      end if;
      j := j + 1;
    end loop;
    
    if (remaining_bits /= 0) then
      nibble := "0000";
      nibble((remaining_bits -1) downto 0) := SLV((SLV'length -1) downto (SLV'length - remaining_bits));
      if (((nibble(0) xor nibble(1) xor nibble (2) xor nibble(3)) /= '1') and
          (nibble(0) xor nibble(1) xor nibble (2) xor nibble(3)) /= '0')  then
        STR(j) := 'x';
      elsif (nibble = "0000")  then
        STR(j) := '0';
      elsif (nibble = "0001")  then
        STR(j) := '1';
      elsif (nibble = "0010")  then
        STR(j) := '2';
      elsif (nibble = "0011")  then
        STR(j) := '3';
      elsif (nibble = "0100")  then
        STR(j) := '4';
      elsif (nibble = "0101")  then
        STR(j) := '5';
      elsif (nibble = "0110")  then
        STR(j) := '6';
      elsif (nibble = "0111")  then
        STR(j) := '7';
      elsif (nibble = "1000")  then
        STR(j) := '8';
      elsif (nibble = "1001")  then
        STR(j) := '9';
      elsif (nibble = "1010")  then
        STR(j) := 'a';
      elsif (nibble = "1011")  then
        STR(j) := 'b';
      elsif (nibble = "1100")  then
        STR(j) := 'c';
      elsif (nibble = "1101")  then
        STR(j) := 'd';
      elsif (nibble = "1110")  then
        STR(j) := 'e';
      elsif (nibble = "1111")  then
        STR(j) := 'f';
      end if;
    end if;    
    return STR;
  end SLV_X_TO_HEX;

  constant widest_width : integer := GetWidestWidth(WRITE_WIDTH_A, READ_WIDTH_A, WRITE_WIDTH_B, READ_WIDTH_B);
  constant mem_depth : integer := GetMemoryDepth(widest_width, BRAM_SIZE);
  constant memp_depth : integer := GetMemoryDepthP(widest_width, BRAM_SIZE);
  constant width : integer := GetWidth(widest_width);
  constant widthp : integer := GetWidthp(widest_width);
  constant width_initf : integer := GetWidthINITF(widest_width);
  constant widthp_initf : integer := GetWidthpINITF(widest_width);  
  constant wa_width : integer := GetWidth(WRITE_WIDTH_A);
  constant wb_width : integer := GetWidth(WRITE_WIDTH_B);
  constant ra_width : integer := GetWidth(READ_WIDTH_A);
  constant rb_width : integer := GetWidth(READ_WIDTH_B);
  constant wa_widthp : integer := GetWidthp(WRITE_WIDTH_A);
  constant wb_widthp : integer := GetWidthp(WRITE_WIDTH_B);
  constant ra_widthp : integer := GetWidthp(READ_WIDTH_A);
  constant rb_widthp : integer := GetWidthp(READ_WIDTH_B);
  constant r_addra_lbit_124 : integer := GetAddrBitLSB(READ_WIDTH_A);
  constant r_addrb_lbit_124 : integer := GetAddrBitLSB(READ_WIDTH_B);
  constant w_addra_lbit_124 : integer := GetAddrBitLSB(WRITE_WIDTH_A);
  constant w_addrb_lbit_124 : integer := GetAddrBitLSB(WRITE_WIDTH_B);
  constant w_addra_bit_124 : integer := GetAddrBit124(WRITE_WIDTH_A, widest_width);
  constant r_addra_bit_124 : integer := GetAddrBit124(READ_WIDTH_A, widest_width);
  constant w_addrb_bit_124 : integer := GetAddrBit124(WRITE_WIDTH_B, widest_width);
  constant r_addrb_bit_124 : integer := GetAddrBit124(READ_WIDTH_B, widest_width);
  constant w_addra_bit_8 : integer := GetAddrBit8(WRITE_WIDTH_A, widest_width);
  constant r_addra_bit_8 : integer := GetAddrBit8(READ_WIDTH_A, widest_width);
  constant w_addrb_bit_8 : integer := GetAddrBit8(WRITE_WIDTH_B, widest_width);
  constant r_addrb_bit_8 : integer := GetAddrBit8(READ_WIDTH_B, widest_width);
  constant w_addra_bit_16 : integer := GetAddrBit16(WRITE_WIDTH_A, widest_width);
  constant r_addra_bit_16 : integer := GetAddrBit16(READ_WIDTH_A, widest_width);
  constant w_addrb_bit_16 : integer := GetAddrBit16(WRITE_WIDTH_B, widest_width);
  constant r_addrb_bit_16 : integer := GetAddrBit16(READ_WIDTH_B, widest_width);
  constant w_addra_bit_32 : integer := GetAddrBit32(WRITE_WIDTH_A, widest_width);
  constant r_addra_bit_32 : integer := GetAddrBit32(READ_WIDTH_A, widest_width);
  constant w_addrb_bit_32 : integer := GetAddrBit32(WRITE_WIDTH_B, widest_width);
  constant r_addrb_bit_32 : integer := GetAddrBit32(READ_WIDTH_B, widest_width);
  constant col_addr_lsb : integer := GetAddrBitLSB(widest_width);
  constant tmp_widthp : integer := GetWidthpTmpWidthp(widest_width);

  type Two_D_array_type_tmp_mem is array ((mem_depth -  1) downto 0) of std_logic_vector((widest_width - 1) downto 0);
    
  type Two_D_array_type is array ((mem_depth -  1) downto 0) of std_logic_vector((width - 1) downto 0);
  type Two_D_parity_array_type is array ((memp_depth - 1) downto 0) of std_logic_vector((widthp -1) downto 0);

  type Two_D_array_type_initf is array ((mem_depth -  1) downto 0) of std_logic_vector((width_initf - 1) downto 0);
  type Two_D_parity_array_type_initf is array ((memp_depth - 1) downto 0) of std_logic_vector((widthp_initf -1) downto 0);

    
  function slv_to_two_D_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_array_type is
    variable two_D_array : two_D_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1) loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_array(i) := intermediate; 
    end loop;
    return two_D_array;
  end;


  function slv_to_two_D_parity_array(
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector
    )
    return two_D_parity_array_type is
    variable two_D_parity_array : two_D_parity_array_type;
    variable intermediate : std_logic_vector((slv_width - 1) downto 0);
  begin
    for i in 0 to (slv_length - 1)loop
      intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width));
      two_D_parity_array(i) := intermediate; 
    end loop;
    return two_D_parity_array;
  end;


  function two_D_mem_initf(
    slv_width : integer
    )
    return two_D_array_type_tmp_mem is

    variable input_initf_tmp : Two_D_array_type_initf;
    variable input_initf : Two_D_array_type_tmp_mem;
    file int_infile : text;
    variable data_line, data_line_tmp, out_data_line : line;
    variable i : integer := 0;
    variable good_data : boolean := false;
    variable ignore_line : boolean := false;
    variable char_tmp : character;
    variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
    variable open_status : file_open_status;
    
  begin

    if (INIT_FILE /= "NONE") then
      
      file_open(open_status, int_infile, INIT_FILE, read_mode);

      while not endfile(int_infile) loop
          
        readline(int_infile, data_line);

        while (data_line /= null and data_line'length > 0) loop
          
          if (data_line(data_line'low to data_line'low + 1) = "//") then
            deallocate(data_line);

          elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
            deallocate(data_line);
            ignore_line := true;

          elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
            deallocate(data_line);
            ignore_line := false;


          elsif (ignore_line = false and data_line(data_line'low) = '@') then
            read(data_line, char_tmp);
            hread(data_line, init_addr_slv, good_data);

            i := SLV_TO_INT(init_addr_slv);

          elsif (ignore_line = false) then

            hread(data_line, input_initf_tmp(i), good_data);
            input_initf(i)(slv_width - 1 downto 0) := input_initf_tmp(i)(slv_width - 1 downto 0);
          
            if (good_data = true) then
              i := i + 1;             
            end if;
          else
            deallocate(data_line);
                     
          end if;
        
        end loop;
        
      end loop;

    end if;
        
    return input_initf;

  end;


  function two_D_mem_init(  
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector;
    temp_mem : two_D_array_type_tmp_mem
    )
    return two_D_array_type is
    variable two_D_array_mem_init : two_D_array_type;
  begin
     if (INIT_FILE = "NONE") then
       two_D_array_mem_init := slv_to_two_D_array(slv_length, slv_width, SLV);
     else

       for i in 0 to (slv_length - 1) loop
         two_D_array_mem_init(i)(slv_width-1 downto 0) := temp_mem(i)(slv_width-1 downto 0);
       end loop;
                           
     end if;
     return two_D_array_mem_init;
  end;


  function two_D_mem_initp(  
    slv_length : integer;
    slv_width : integer;
    SLV : in std_logic_vector;
    temp_mem : two_D_array_type_tmp_mem;
    mem_width : integer
    )
    return two_D_parity_array_type is
    variable two_D_array_mem_initp : two_D_parity_array_type;
  begin
     if (INIT_FILE = "NONE") then
       two_D_array_mem_initp := slv_to_two_D_parity_array(slv_length, slv_width, SLV);
     else

       if (slv_width > 0) then
         
         for i in 0 to (slv_length - 1) loop
           two_D_array_mem_initp(i)(slv_width-1 downto 0) := temp_mem(i)(mem_width + slv_width - 1 downto mem_width);
         end loop;

       end if;
     end if;
     return two_D_array_mem_initp;
  end;

    

  function fn_dip_ecc (
    encode : in std_logic;
    di_in : in std_logic_vector (63 downto 0);
    dip_in : in std_logic_vector (7 downto 0)
    ) return std_logic_vector is
    variable fn_dip_ecc : std_logic_vector (7 downto 0);
  begin

    fn_dip_ecc(0) := di_in(0) xor di_in(1) xor di_in(3) xor di_in(4) xor di_in(6) xor di_in(8)
                  xor di_in(10) xor di_in(11) xor di_in(13) xor di_in(15) xor di_in(17) xor di_in(19)
                  xor di_in(21) xor di_in(23) xor di_in(25) xor di_in(26) xor di_in(28)
                  xor di_in(30) xor di_in(32) xor di_in(34) xor di_in(36) xor di_in(38)
                  xor di_in(40) xor di_in(42) xor di_in(44) xor di_in(46) xor di_in(48)
                  xor di_in(50) xor di_in(52) xor di_in(54) xor di_in(56) xor di_in(57) xor di_in(59)
                  xor di_in(61) xor di_in(63);

    fn_dip_ecc(1) := di_in(0) xor di_in(2) xor di_in(3) xor di_in(5) xor di_in(6) xor di_in(9)
                     xor di_in(10) xor di_in(12) xor di_in(13) xor di_in(16) xor di_in(17)
                     xor di_in(20) xor di_in(21) xor di_in(24) xor di_in(25) xor di_in(27) xor di_in(28)
                     xor di_in(31) xor di_in(32) xor di_in(35) xor di_in(36) xor di_in(39)
                     xor di_in(40) xor di_in(43) xor di_in(44) xor di_in(47) xor di_in(48)
                     xor di_in(51) xor di_in(52) xor di_in(55) xor di_in(56) xor di_in(58) xor di_in(59)
                     xor di_in(62) xor di_in(63);

    fn_dip_ecc(2) := di_in(1) xor di_in(2) xor di_in(3) xor di_in(7) xor di_in(8) xor di_in(9)
                     xor di_in(10) xor di_in(14) xor di_in(15) xor di_in(16) xor di_in(17)
                     xor di_in(22) xor di_in(23) xor di_in(24) xor di_in(25) xor di_in(29)
                     xor di_in(30) xor di_in(31) xor di_in(32) xor di_in(37) xor di_in(38) xor di_in(39)
                     xor di_in(40) xor di_in(45) xor di_in(46) xor di_in(47) xor di_in(48)
                     xor di_in(53) xor di_in(54) xor di_in(55) xor di_in(56)
                     xor di_in(60) xor di_in(61) xor di_in(62) xor di_in(63);
	
    fn_dip_ecc(3) := di_in(4) xor di_in(5) xor di_in(6) xor di_in(7) xor di_in(8) xor di_in(9)
                     xor di_in(10) xor di_in(18) xor di_in(19)
                     xor di_in(20) xor di_in(21) xor di_in(22) xor di_in(23) xor di_in(24) xor di_in(25)
                     xor di_in(33) xor di_in(34) xor di_in(35) xor di_in(36) xor di_in(37) xor di_in(38) xor di_in(39)
                     xor di_in(40) xor di_in(49)
                     xor di_in(50) xor di_in(51) xor di_in(52) xor di_in(53) xor di_in(54) xor di_in(55) xor di_in(56);

    fn_dip_ecc(4) := di_in(11) xor di_in(12) xor di_in(13) xor di_in(14) xor di_in(15) xor di_in(16) xor di_in(17)
                     xor di_in(18) xor di_in(19) xor di_in(20) xor di_in(21) xor di_in(22) xor di_in(23) xor di_in(24)
                     xor di_in(25) xor di_in(41) xor di_in(42) xor di_in(43) xor di_in(44) xor di_in(45) xor di_in(46)
                     xor di_in(47) xor di_in(48) xor di_in(49) xor di_in(50) xor di_in(51) xor di_in(52) xor di_in(53)
                     xor di_in(54) xor di_in(55) xor di_in(56);


    fn_dip_ecc(5) := di_in(26) xor di_in(27) xor di_in(28) xor di_in(29)
                     xor di_in(30) xor di_in(31) xor di_in(32) xor di_in(33) xor di_in(34) xor di_in(35) xor di_in(36)
                     xor di_in(37) xor di_in(38) xor di_in(39) xor di_in(40) xor di_in(41) xor di_in(42) xor di_in(43)
                     xor di_in(44) xor di_in(45) xor di_in(46) xor di_in(47) xor di_in(48) xor di_in(49) xor di_in(50)
                     xor di_in(51) xor di_in(52) xor di_in(53) xor di_in(54) xor di_in(55) xor di_in(56);

    fn_dip_ecc(6) := di_in(57) xor di_in(58) xor di_in(59)
                     xor di_in(60) xor di_in(61) xor di_in(62) xor di_in(63);

    if (encode = '1') then

      fn_dip_ecc(7) := fn_dip_ecc(0) xor fn_dip_ecc(1) xor fn_dip_ecc(2) xor fn_dip_ecc(3) xor fn_dip_ecc(4) xor fn_dip_ecc(5)
                       xor fn_dip_ecc(6) xor di_in(0) xor di_in(1) xor di_in(2) xor di_in(3) xor di_in(4) xor di_in(5)
                       xor di_in(6) xor di_in(7) xor di_in(8) xor di_in(9) xor di_in(10) xor di_in(11) xor di_in(12)
                       xor di_in(13) xor di_in(14) xor di_in(15) xor di_in(16) xor di_in(17) xor di_in(18) xor di_in(19)
                       xor di_in(20) xor di_in(21) xor di_in(22) xor di_in(23) xor di_in(24) xor di_in(25) xor di_in(26)
                       xor di_in(27) xor di_in(28) xor di_in(29) xor di_in(30) xor di_in(31) xor di_in(32) xor di_in(33)
                       xor di_in(34) xor di_in(35) xor di_in(36) xor di_in(37) xor di_in(38) xor di_in(39) xor di_in(40)
                       xor di_in(41) xor di_in(42) xor di_in(43) xor di_in(44) xor di_in(45) xor di_in(46) xor di_in(47)
                       xor di_in(48) xor di_in(49) xor di_in(50) xor di_in(51) xor di_in(52) xor di_in(53) xor di_in(54)
                       xor di_in(55) xor di_in(56) xor di_in(57) xor di_in(58) xor di_in(59) xor di_in(60) xor di_in(61)
                       xor di_in(62) xor di_in(63);

    else

      fn_dip_ecc(7) := dip_in(0) xor dip_in(1) xor dip_in(2) xor dip_in(3) xor dip_in(4) xor dip_in(5)
                       xor dip_in(6) xor di_in(0) xor di_in(1) xor di_in(2) xor di_in(3) xor di_in(4) xor di_in(5)
                       xor di_in(6) xor di_in(7) xor di_in(8) xor di_in(9) xor di_in(10) xor di_in(11) xor di_in(12)
                       xor di_in(13) xor di_in(14) xor di_in(15) xor di_in(16) xor di_in(17) xor di_in(18) xor di_in(19)
                       xor di_in(20) xor di_in(21) xor di_in(22) xor di_in(23) xor di_in(24) xor di_in(25) xor di_in(26)
                       xor di_in(27) xor di_in(28) xor di_in(29) xor di_in(30) xor di_in(31) xor di_in(32) xor di_in(33)
                       xor di_in(34) xor di_in(35) xor di_in(36) xor di_in(37) xor di_in(38) xor di_in(39) xor di_in(40)
                       xor di_in(41) xor di_in(42) xor di_in(43) xor di_in(44) xor di_in(45) xor di_in(46) xor di_in(47)
                       xor di_in(48) xor di_in(49) xor di_in(50) xor di_in(51) xor di_in(52) xor di_in(53) xor di_in(54)
                       xor di_in(55) xor di_in(56) xor di_in(57) xor di_in(58) xor di_in(59) xor di_in(60) xor di_in(61)
                       xor di_in(62) xor di_in(63);
    end if;

    return fn_dip_ecc;
    
  end fn_dip_ecc;

    
  procedure prcd_chk_for_col_msg (
    constant wea_tmp : in std_ulogic;
    constant web_tmp : in std_ulogic;
    constant addra_tmp : in std_logic_vector (15 downto 0);
    constant addrb_tmp : in std_logic_vector (15 downto 0);
    variable col_wr_wr_msg : inout std_ulogic;
    variable col_wra_rdb_msg : inout std_ulogic;
    variable col_wrb_rda_msg : inout std_ulogic
    ) is
    
    variable string_length_1 : integer;
    variable string_length_2 : integer;
    variable message : LINE;
    constant MsgSeverity : severity_level := Error;

  begin
    
    if ((SIM_COLLISION_CHECK = "ALL" or SIM_COLLISION_CHECK = "WARNING_ONLY")
        and (not(((WRITE_MODE_B = "READ_FIRST" and web_tmp = '1' and wea_tmp = '0') and (not(rising_edge(clka_dly) and (not(rising_edge(clkb_dly))))))
              or ((WRITE_MODE_A = "READ_FIRST" and wea_tmp = '1' and web_tmp = '0') and (not(rising_edge(clkb_dly) and (not(rising_edge(clka_dly))))))))) then

      if ((addra_tmp'length mod 4) = 0) then
        string_length_1 := addra_tmp'length/4;
      elsif ((addra_tmp'length mod 4) > 0) then
        string_length_1 := addra_tmp'length/4 + 1;      
      end if;
      if ((addrb_tmp'length mod 4) = 0) then
        string_length_2 := addrb_tmp'length/4;
      elsif ((addrb_tmp'length mod 4) > 0) then
        string_length_2 := addrb_tmp'length/4 + 1;      
      end if;

      if (wea_tmp = '1' and web_tmp = '1' and col_wr_wr_msg = '1') then
        Write ( message, STRING'(" Memory Collision Error on ARAMB36_INTERNAL :"));
        Write ( message, STRING'(ARAMB36_INTERNAL'path_name));
        Write ( message, STRING'(" at simulation time "));
        Write ( message, now);
        Write ( message, STRING'("."));
        Write ( message, LF );
        Write ( message, STRING'(" A write was requested to the same address simultaneously at both Port A and Port B of the RAM."));
        Write ( message, STRING'(" The contents written to the RAM at address location "));      
        Write ( message, SLV_X_TO_HEX(addra_tmp, string_length_1));
        Write ( message, STRING'(" (hex) "));            
        Write ( message, STRING'("of Port A and address location "));
        Write ( message, SLV_X_TO_HEX(addrb_tmp, string_length_2));
        Write ( message, STRING'(" (hex) "));            
        Write ( message, STRING'("of Port B are unknown. "));
        ASSERT FALSE REPORT message.ALL SEVERITY MsgSeverity;
        DEALLOCATE (message);
        col_wr_wr_msg := '0';
        
      elsif (wea_tmp = '1' and web_tmp = '0' and col_wra_rdb_msg = '1') then
        Write ( message, STRING'(" Memory Collision Error on ARAMB36_INTERNAL :"));
        Write ( message, STRING'(ARAMB36_INTERNAL'path_name));
        Write ( message, STRING'(" at simulation time "));
        Write ( message, now);
        Write ( message, STRING'("."));
        Write ( message, LF );            
        Write ( message, STRING'(" A read was performed on address "));
        Write ( message, SLV_X_TO_HEX(addrb_tmp, string_length_2));
        Write ( message, STRING'(" (hex) "));            
        Write ( message, STRING'("of port B while a write was requested to the same address on Port A. "));
        Write ( message, STRING'(" The write will be successful however the read value on port B is unknown until the next CLKB cycle. "));
        ASSERT FALSE REPORT message.ALL SEVERITY MsgSeverity;
        DEALLOCATE (message);
        col_wra_rdb_msg := '0';
        
      elsif (wea_tmp = '0' and web_tmp = '1' and col_wrb_rda_msg = '1') then
        Write ( message, STRING'(" Memory Collision Error on ARAMB36_INTERNAL :"));
        Write ( message, STRING'(ARAMB36_INTERNAL'path_name));
        Write ( message, STRING'(" at simulation time "));
        Write ( message, now);
        Write ( message, STRING'("."));
        Write ( message, LF );            
        Write ( message, STRING'(" A read was performed on address "));
        Write ( message, SLV_X_TO_HEX(addra_tmp, string_length_1));
        Write ( message, STRING'(" (hex) "));            
        Write ( message, STRING'("of port A while a write was requested to the same address on Port B. "));
        Write ( message, STRING'(" The write will be successful however the read value on port A is unknown until the next CLKA cycle. "));
        ASSERT FALSE REPORT message.ALL SEVERITY MsgSeverity;
        DEALLOCATE (message);
        col_wrb_rda_msg := '0';
        
      end if;      

    end if;
    
  end prcd_chk_for_col_msg;

    
  procedure prcd_write_ram (
    constant we : in std_logic;
    constant di : in std_logic_vector;
    constant dip : in std_logic;
    variable mem_proc : inout std_logic_vector;
    variable memp_proc : inout std_logic
    ) is
    
    alias di_tmp : std_logic_vector (di'length-1 downto 0) is di;
    alias mem_proc_tmp : std_logic_vector (mem_proc'length-1 downto 0) is mem_proc;

    begin
      if (we = '1') then
        mem_proc_tmp := di_tmp;

        if (width >= 8) then
          memp_proc := dip;
        end if;
      end if;
  end prcd_write_ram;

    
  procedure prcd_write_ram_col (
    constant we_o : in std_logic;
    constant we : in std_logic;
    constant di : in std_logic_vector;
    constant dip : in std_logic;
    variable mem_proc : inout std_logic_vector;
    variable memp_proc : inout std_logic
    ) is
    
    alias di_tmp : std_logic_vector (di'length-1 downto 0) is di;
    alias mem_proc_tmp : std_logic_vector (mem_proc'length-1 downto 0) is mem_proc;
    variable i : integer := 0;
    
    begin
      if (we = '1') then

        for i in 0 to di'length-1 loop
          if ((mem_proc_tmp(i) /= 'X') or (not(we = we_o and we = '1'))) then
            mem_proc_tmp(i) := di_tmp(i);
          end if;
        end loop;

        if (width >= 8 and ((memp_proc /= 'X') or (not(we = we_o and we = '1')))) then
          memp_proc := dip;
        end if;

      end if;
  end prcd_write_ram_col;

  
  procedure prcd_x_buf (
    constant wr_rd_mode : in std_logic_vector (1 downto 0);
    constant do_uindex : in integer;
    constant do_lindex : in integer;
    constant dop_index : in integer;
    constant do_ltmp : in std_logic_vector (63 downto 0);
    variable do_tmp : inout std_logic_vector (63 downto 0);
    constant dop_ltmp : in std_logic_vector (7 downto 0);
    variable dop_tmp : inout std_logic_vector (7 downto 0)
    ) is
    
    variable i : integer;

    begin
      if (wr_rd_mode = "01") then
        for i in do_lindex to do_uindex loop
          if (do_ltmp(i) = 'X') then
            do_tmp(i) := 'X';
          end if;
        end loop;
        
        if (dop_ltmp(dop_index) = 'X') then
          dop_tmp(dop_index) := 'X';
        end if;
          
      else
        do_tmp(do_lindex + 7 downto do_lindex) := do_ltmp(do_lindex + 7 downto do_lindex);
        dop_tmp(dop_index) := dop_ltmp(dop_index);
      end if;

  end prcd_x_buf;

    
  procedure prcd_rd_ram_a (
    constant addra_tmp : in std_logic_vector (15 downto 0);
    variable doa_tmp : inout std_logic_vector (63 downto 0);
    variable dopa_tmp : inout std_logic_vector (7 downto 0);
    constant mem : in Two_D_array_type;
    constant memp : in Two_D_parity_array_type     
    ) is
    variable prcd_tmp_addra_dly_depth : integer;
    variable prcd_tmp_addra_dly_width : integer;

  begin
    
    case ra_width is

      when 1 | 2 | 4 => if (ra_width >= width) then
                          prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_lbit_124));
                          doa_tmp(ra_width-1 downto 0) := mem(prcd_tmp_addra_dly_depth);
                        else
                          prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_124 + 1));
                          prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_124 downto r_addra_lbit_124));
                          doa_tmp(ra_width-1 downto 0) := mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * ra_width) + ra_width - 1 downto prcd_tmp_addra_dly_width * ra_width);
                        end if;

      when 8 => if (ra_width >= width) then
                  prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 3));
                  doa_tmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth);
                  dopa_tmp(0 downto 0) := memp(prcd_tmp_addra_dly_depth);
                else
                  prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_8 + 1));
                  prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_8 downto 3));
                  doa_tmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 8) + 7 downto prcd_tmp_addra_dly_width * 8);
                  dopa_tmp(0 downto 0) := memp(prcd_tmp_addra_dly_depth)(prcd_tmp_addra_dly_width downto prcd_tmp_addra_dly_width);
                end if;

      when 16 => if (ra_width >= width) then
                  prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4));
                  doa_tmp(15 downto 0) := mem(prcd_tmp_addra_dly_depth);
                  dopa_tmp(1 downto 0) := memp(prcd_tmp_addra_dly_depth);
                 else
                  prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_16 + 1));
                  prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_16 downto 4));
                  doa_tmp(15 downto 0) := mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 16) + 15 downto prcd_tmp_addra_dly_width * 16);
                  dopa_tmp(1 downto 0) := memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2) + 1 downto prcd_tmp_addra_dly_width * 2);
                 end if;

      when 32 => if (ra_width >= width) then
                  prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 5));
                  doa_tmp(31 downto 0) := mem(prcd_tmp_addra_dly_depth);
                  dopa_tmp(3 downto 0) := memp(prcd_tmp_addra_dly_depth);
                end if;

      when 64 => if (ra_width >= width) then
                  prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 6));
                  doa_tmp(63 downto 0) := mem(prcd_tmp_addra_dly_depth);
                  dopa_tmp(7 downto 0) := memp(prcd_tmp_addra_dly_depth);
                end if;
                 
      when others => null;

    end case;

  end prcd_rd_ram_a;

  
  procedure prcd_rd_ram_b (
    constant addrb_tmp : in std_logic_vector (15 downto 0);
    variable dob_tmp : inout std_logic_vector (63 downto 0);
    variable dopb_tmp : inout std_logic_vector (7 downto 0);
    constant mem : in Two_D_array_type;
    constant memp : in Two_D_parity_array_type     
    ) is
    variable prcd_tmp_addrb_dly_depth : integer;
    variable prcd_tmp_addrb_dly_width : integer;

  begin
    
    case rb_width is

      when 1 | 2 | 4 => if (rb_width >= width) then
                          prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_lbit_124));
                          dob_tmp(rb_width-1 downto 0) := mem(prcd_tmp_addrb_dly_depth);
                        else
                          prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_124 + 1));
                          prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_124 downto r_addrb_lbit_124));
                          dob_tmp(rb_width-1 downto 0) := mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * rb_width) + rb_width - 1 downto prcd_tmp_addrb_dly_width * rb_width);
                        end if;

      when 8 => if (rb_width >= width) then
                  prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 3));
                  dob_tmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth);
                  dopb_tmp(0 downto 0) := memp(prcd_tmp_addrb_dly_depth);
                else
                  prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_8 + 1));
                  prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_8 downto 3));
                  dob_tmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 8) + 7 downto prcd_tmp_addrb_dly_width * 8);
                  dopb_tmp(0 downto 0) := memp(prcd_tmp_addrb_dly_depth)(prcd_tmp_addrb_dly_width downto prcd_tmp_addrb_dly_width);
                end if;

      when 16 => if (rb_width >= width) then
                  prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4));
                  dob_tmp(15 downto 0) := mem(prcd_tmp_addrb_dly_depth);
                  dopb_tmp(1 downto 0) := memp(prcd_tmp_addrb_dly_depth);
                 else
                  prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_16 + 1));
                  prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_16 downto 4));
                  dob_tmp(15 downto 0) := mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 16) + 15 downto prcd_tmp_addrb_dly_width * 16);
                  dopb_tmp(1 downto 0) := memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2) + 1 downto prcd_tmp_addrb_dly_width * 2);
                 end if;

      when 32 => if (rb_width >= width) then
                  prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 5));
                  dob_tmp(31 downto 0) := mem(prcd_tmp_addrb_dly_depth);
                  dopb_tmp(3 downto 0) := memp(prcd_tmp_addrb_dly_depth);
                end if;

      when others => null;

    end case;

  end prcd_rd_ram_b;


  procedure prcd_col_wr_ram_a (
    constant seq : in std_logic_vector (1 downto 0);
    constant web_tmp : in std_logic_vector (7 downto 0);
    constant wea_tmp : in std_logic_vector (7 downto 0);
    constant dia_tmp : in std_logic_vector (63 downto 0);
    constant dipa_tmp : in std_logic_vector (7 downto 0);
    constant addrb_tmp : in std_logic_vector (15 downto 0);
    constant addra_tmp : in std_logic_vector (15 downto 0);
    variable mem : inout Two_D_array_type;
    variable memp : inout Two_D_parity_array_type;
    variable col_wr_wr_msg : inout std_ulogic;
    variable col_wra_rdb_msg : inout std_ulogic;
    variable col_wrb_rda_msg : inout std_ulogic
    ) is
    variable prcd_tmp_addra_dly_depth : integer;
    variable prcd_tmp_addra_dly_width : integer;
    variable junk : std_ulogic;

  begin
    
    case wa_width is

      when 1 | 2 | 4 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wa_width > wb_width) or seq = "10") then
                          if (wa_width >= width) then
                            prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_lbit_124));
                            prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(wa_width-1 downto 0), '0', mem(prcd_tmp_addra_dly_depth), junk);
                          else
                            prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_124 + 1));
                            prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_124 downto w_addra_lbit_124));
                            prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(wa_width-1 downto 0), '0', mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * wa_width) + wa_width - 1 downto (prcd_tmp_addra_dly_width * wa_width)), junk);
                          end if;

                          if (seq = "00") then
                            prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                          end if;
                        end if;
      
      when 8 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wa_width > wb_width) or seq = "10") then
                  if (wa_width >= width) then
                    prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 3));
                    prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth), memp(prcd_tmp_addra_dly_depth)(0));
                  else
                    prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_8 + 1));
                    prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_8 downto 3));
                    prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 8) + 7 downto (prcd_tmp_addra_dly_width * 8)), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width)));
                  end if;
  
                  if (seq = "00") then
                    prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                  end if;
                end if;

      when 16 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wa_width > wb_width) or seq = "10") then
                  if (wa_width >= width) then
                    prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4));
                    prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0));
                  else
                    prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_16 + 1));
                    prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_16 downto 4));
                    prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 16) + 7 downto (prcd_tmp_addra_dly_width * 16)), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2)));
                  end if;

                  if (seq = "00") then
                    prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                  end if;
                 
                  if (wa_width >= width) then
                    prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4));
                    prcd_write_ram_col (web_tmp(1), wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1));
                  else
                    prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_16 + 1));
                    prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_16 downto 4));
                    prcd_write_ram_col (web_tmp(1), wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 16) + 15 downto (prcd_tmp_addra_dly_width * 16) + 8), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2) + 1));
                  end if;

                  if (seq = "00") then
                    prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                  end if;
                 
                end if;

      when 32 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wa_width > wb_width) or seq = "10") then

                   prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 5));
                   prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0));

                   if (seq = "00") then
                     prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                   end if;

                   prcd_write_ram_col (web_tmp(1), wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1));

                   if (seq = "00") then
                     prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                   end if;
                   
                   prcd_write_ram_col (web_tmp(2), wea_tmp(2), dia_tmp(23 downto 16), dipa_tmp(2), mem(prcd_tmp_addra_dly_depth)(23 downto 16), memp(prcd_tmp_addra_dly_depth)(2));

                   if (seq = "00") then
                     prcd_chk_for_col_msg (wea_tmp(2), web_tmp(2), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                   end if;

                   prcd_write_ram_col (web_tmp(3), wea_tmp(3), dia_tmp(31 downto 24), dipa_tmp(3), mem(prcd_tmp_addra_dly_depth)(31 downto 24), memp(prcd_tmp_addra_dly_depth)(3));

                   if (seq = "00") then
                     prcd_chk_for_col_msg (wea_tmp(3), web_tmp(3), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                   end if;

                 end if;
      when 64 => null;
--                   prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 6));
--                   prcd_write_ram_col ('0', '1', dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0));
----                          if (seq = "00")
----                            prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp);
--
--                   prcd_write_ram_col ('0', '1', dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1));
----                          if (seq = "00")
----                            prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp);
--                   
--                   prcd_write_ram_col ('0', '1', dia_tmp(23 downto 16), dipa_tmp(2), mem(prcd_tmp_addra_dly_depth)(23 downto 16), memp(prcd_tmp_addra_dly_depth)(2));
----                          if (seq = "00")
----                            prcd_chk_for_col_msg (wea_tmp(2), web_tmp(2), addra_tmp, addrb_tmp);
--
--                   prcd_write_ram_col ('0', '1', dia_tmp(31 downto 24), dipa_tmp(3), mem(prcd_tmp_addra_dly_depth)(31 downto 24), memp(prcd_tmp_addra_dly_depth)(3));
----                          if (seq = "00")
----                            prcd_chk_for_col_msg (wea_tmp(3), web_tmp(3), addra_tmp, addrb_tmp);
--  
--                   prcd_write_ram_col ('0', '1', dia_tmp(39 downto 32), dipa_tmp(4), mem(prcd_tmp_addra_dly_depth)(39 downto 32), memp(prcd_tmp_addra_dly_depth)(4));
----                          if (seq = "00")
----                            prcd_chk_for_col_msg (wea_tmp(4), web_tmp(4), addra_tmp, addrb_tmp);
--
--                   prcd_write_ram_col ('0', '1', dia_tmp(47 downto 40), dipa_tmp(5), mem(prcd_tmp_addra_dly_depth)(47 downto 40), memp(prcd_tmp_addra_dly_depth)(5));
----                          if (seq = "00")
----                            prcd_chk_for_col_msg (wea_tmp(5), web_tmp(5), addra_tmp, addrb_tmp);
--
--                   prcd_write_ram_col ('0', '1', dia_tmp(55 downto 48), dipa_tmp(6), mem(prcd_tmp_addra_dly_depth)(55 downto 48), memp(prcd_tmp_addra_dly_depth)(6));
----                          if (seq = "00")
----                            prcd_chk_for_col_msg (wea_tmp(6), web_tmp(6), addra_tmp, addrb_tmp);
--
--                   prcd_write_ram_col ('0', '1', dia_tmp(63 downto 56), dipa_tmp(7), mem(prcd_tmp_addra_dly_depth)(63 downto 56), memp(prcd_tmp_addra_dly_depth)(7));
----                          if (seq = "00")
----                            prcd_chk_for_col_msg (wea_tmp(7), web_tmp(7), addra_tmp, addrb_tmp);  
--
      when others => null;

    end case;

  end prcd_col_wr_ram_a;

  
  procedure prcd_col_wr_ram_b (
    constant seq : in std_logic_vector (1 downto 0);
    constant wea_tmp : in std_logic_vector (7 downto 0);
    constant web_tmp : in std_logic_vector (7 downto 0);
    constant dib_tmp : in std_logic_vector (63 downto 0);
    constant dipb_tmp : in std_logic_vector (7 downto 0);
    constant addra_tmp : in std_logic_vector (15 downto 0);
    constant addrb_tmp : in std_logic_vector (15 downto 0);
    variable mem : inout Two_D_array_type;
    variable memp : inout Two_D_parity_array_type;
    variable col_wr_wr_msg : inout std_ulogic;
    variable col_wra_rdb_msg : inout std_ulogic;
    variable col_wrb_rda_msg : inout std_ulogic
    ) is
    variable prcd_tmp_addrb_dly_depth : integer;
    variable prcd_tmp_addrb_dly_width : integer;
    variable junk : std_ulogic;

  begin
    
    case wb_width is

      when 1 | 2 | 4 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wb_width > wa_width) or seq = "10") then
                          if (wb_width >= width) then
                            prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_lbit_124));
                            prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(wb_width-1 downto 0), '0', mem(prcd_tmp_addrb_dly_depth), junk);
                          else
                            prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_124 + 1));
                            prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_124 downto w_addrb_lbit_124));
                            prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(wb_width-1 downto 0), '0', mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * wb_width) + wb_width - 1 downto (prcd_tmp_addrb_dly_width * wb_width)), junk);
                          end if;

                          if (seq = "00") then
                            prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                          end if;
                        end if;

      when 8 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wb_width > wa_width) or seq = "10") then
                  if (wb_width >= width) then
                    prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 3));
                    prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth), memp(prcd_tmp_addrb_dly_depth)(0));
                  else
                    prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_8 + 1));
                    prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_8 downto 3));
                    prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 8) + 7 downto (prcd_tmp_addrb_dly_width * 8)), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width)));
                  end if;
    
                  if (seq = "00") then
                    prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                  end if; 
                end if;

      when 16 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wb_width > wa_width) or seq = "10") then
                  if (wb_width >= width) then
                    prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4));
                    prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0));
                  else
                    prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_16 + 1));
                    prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_16 downto 4));
                    prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 16) + 7 downto (prcd_tmp_addrb_dly_width * 16)), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2)));
                  end if;

                  if (seq = "00") then
                    prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                  end if;

                  if (wb_width >= width) then
                    prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4));
                    prcd_write_ram_col (wea_tmp(1), web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1));
                  else
                    prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_16 + 1));
                    prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_16 downto 4));
                    prcd_write_ram_col (wea_tmp(1), web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 16) + 15 downto (prcd_tmp_addrb_dly_width * 16) + 8), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2) + 1));
                  end if;

                  if (seq = "00") then
                    prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                  end if;

                end if;
      when 32 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wb_width > wa_width) or seq = "10") then

                   prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 5));
                   prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0));
                   if (seq = "00") then
                     prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                   end if;

                   prcd_write_ram_col (wea_tmp(1), web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1));
                   if (seq = "00") then
                     prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                   end if;
                   
                   prcd_write_ram_col (wea_tmp(2), web_tmp(2), dib_tmp(23 downto 16), dipb_tmp(2), mem(prcd_tmp_addrb_dly_depth)(23 downto 16), memp(prcd_tmp_addrb_dly_depth)(2));
                   if (seq = "00") then
                     prcd_chk_for_col_msg (wea_tmp(2), web_tmp(2), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                   end if;

                   prcd_write_ram_col (wea_tmp(3), web_tmp(3), dib_tmp(31 downto 24), dipb_tmp(3), mem(prcd_tmp_addrb_dly_depth)(31 downto 24), memp(prcd_tmp_addrb_dly_depth)(3));
                   if (seq = "00") then
                     prcd_chk_for_col_msg (wea_tmp(3), web_tmp(3), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                   end if;

                 end if;
      when 64 =>
                   prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 6));
                   prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0));
                   if (seq = "00") then
                     prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                   end if;

                   prcd_write_ram_col (wea_tmp(1), web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1));
                   if (seq = "00") then
                     prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                   end if;
                   
                   prcd_write_ram_col (wea_tmp(2), web_tmp(2), dib_tmp(23 downto 16), dipb_tmp(2), mem(prcd_tmp_addrb_dly_depth)(23 downto 16), memp(prcd_tmp_addrb_dly_depth)(2));
                   if (seq = "00") then
                     prcd_chk_for_col_msg (wea_tmp(2), web_tmp(2), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                   end if;

                   prcd_write_ram_col (wea_tmp(3), web_tmp(3), dib_tmp(31 downto 24), dipb_tmp(3), mem(prcd_tmp_addrb_dly_depth)(31 downto 24), memp(prcd_tmp_addrb_dly_depth)(3));
                   if (seq = "00") then
                     prcd_chk_for_col_msg (wea_tmp(3), web_tmp(3), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                   end if;
  
                   prcd_write_ram_col (wea_tmp(4), web_tmp(4), dib_tmp(39 downto 32), dipb_tmp(4), mem(prcd_tmp_addrb_dly_depth)(39 downto 32), memp(prcd_tmp_addrb_dly_depth)(4));
                   if (seq = "00") then
                     prcd_chk_for_col_msg (wea_tmp(4), web_tmp(4), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                   end if;

                   prcd_write_ram_col (wea_tmp(5), web_tmp(5), dib_tmp(47 downto 40), dipb_tmp(5), mem(prcd_tmp_addrb_dly_depth)(47 downto 40), memp(prcd_tmp_addrb_dly_depth)(5));
                   if (seq = "00") then
                     prcd_chk_for_col_msg (wea_tmp(5), web_tmp(5), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                   end if;

                   prcd_write_ram_col (wea_tmp(6), web_tmp(6), dib_tmp(55 downto 48), dipb_tmp(6), mem(prcd_tmp_addrb_dly_depth)(55 downto 48), memp(prcd_tmp_addrb_dly_depth)(6));
                   if (seq = "00") then
                     prcd_chk_for_col_msg (wea_tmp(6), web_tmp(6), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                   end if;

                   prcd_write_ram_col (wea_tmp(7), web_tmp(7), dib_tmp(63 downto 56), dipb_tmp(7), mem(prcd_tmp_addrb_dly_depth)(63 downto 56), memp(prcd_tmp_addrb_dly_depth)(7));
                   if (seq = "00") then
                     prcd_chk_for_col_msg (wea_tmp(7), web_tmp(7), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
                   end if;

      when others => null;

    end case;

  end prcd_col_wr_ram_b;


  procedure prcd_col_rd_ram_a (
    constant viol_type_tmp : in std_logic_vector (1 downto 0);
    constant seq : in std_logic_vector (1 downto 0);
    constant web_tmp : in std_logic_vector (7 downto 0);
    constant wea_tmp : in std_logic_vector (7 downto 0);
    constant addra_tmp : in std_logic_vector (15 downto 0);
    variable doa_tmp : inout std_logic_vector (63 downto 0);
    variable dopa_tmp : inout std_logic_vector (7 downto 0);
    constant mem : in Two_D_array_type;
    constant memp : in Two_D_parity_array_type;
    constant wr_mode_a_tmp : in std_logic_vector (1 downto 0)

    ) is
    variable prcd_tmp_addra_dly_depth : integer;
    variable prcd_tmp_addra_dly_width : integer;
    variable junk : std_ulogic;
    variable doa_ltmp : std_logic_vector (63 downto 0);
    variable dopa_ltmp : std_logic_vector (7 downto 0);
    
  begin

    doa_ltmp := (others => '0');
    dopa_ltmp := (others => '0');
    
    case ra_width is
      
      when 1 | 2 | 4 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and web_tmp(0) = '1' and wea_tmp(0) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(0) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(0) /= '1')) then

                          if (ra_width >= width) then
                            prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_lbit_124));
                            doa_ltmp(ra_width-1 downto 0) := mem(prcd_tmp_addra_dly_depth);
                          else
                            prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_124 + 1));
                            prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_124 downto r_addra_lbit_124));
                            doa_ltmp(ra_width-1 downto 0) := mem(prcd_tmp_addra_dly_depth)(((prcd_tmp_addra_dly_width * ra_width) + ra_width - 1) downto (prcd_tmp_addra_dly_width * ra_width));

                          end if;
                          prcd_x_buf (wr_mode_a_tmp, 3, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);
                        end if;

      when 8 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and web_tmp(0) = '1' and wea_tmp(0) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(0) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(0) /= '1')) then

                  if (ra_width >= width) then
                    prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 3));
                    doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth);
                    dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(0);
                  else
                    prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_8 + 1));
                    prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_8 downto 3));
                    doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)(((prcd_tmp_addra_dly_width * 8) + 7) downto (prcd_tmp_addra_dly_width * 8));
                    dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(prcd_tmp_addra_dly_width);
                  end if;
                  prcd_x_buf (wr_mode_a_tmp, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);

                end if;

      when 16 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and web_tmp(0) = '1' and wea_tmp(0) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(0) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(0) /= '1')) then

                  if (ra_width >= width) then
                    prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4));
                    doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)(7 downto 0);
                    dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(0);
                  else
                    prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_16 + 1));
                    prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_16 downto 4));

                    doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)(((prcd_tmp_addra_dly_width * 16) + 7) downto (prcd_tmp_addra_dly_width * 16));                    
                    dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(prcd_tmp_addra_dly_width * 2);
                  end if;
                  prcd_x_buf (wr_mode_a_tmp, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);

                end if;

                if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and web_tmp(1) = '1' and wea_tmp(1) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(1) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(1) /= '1')) then

                  if (ra_width >= width) then
                    prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4));
                    doa_ltmp(15 downto 8) := mem(prcd_tmp_addra_dly_depth)(15 downto 8);
                    dopa_ltmp(1) := memp(prcd_tmp_addra_dly_depth)(1);
                  else
                    prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_16 + 1));
                    prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_16 downto 4));

                    doa_ltmp(15 downto 8) := mem(prcd_tmp_addra_dly_depth)(((prcd_tmp_addra_dly_width * 16) + 15) downto ((prcd_tmp_addra_dly_width * 16) + 8));
                    dopa_ltmp(1) := memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2) + 1);
                  end if;
                  prcd_x_buf (wr_mode_a_tmp, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);
                  
                end if;

      when 32 => if (ra_width >= width) then

                   prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 5));

                   if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and web_tmp(0) = '1' and wea_tmp(0) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(0) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(0) /= '1')) then

                     doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)(7 downto 0);
                     dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(0);
                     prcd_x_buf (wr_mode_a_tmp, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);

                   end if;

                   if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and web_tmp(1) = '1' and wea_tmp(1) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(1) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(1) /= '1')) then

                     doa_ltmp(15 downto 8) := mem(prcd_tmp_addra_dly_depth)(15 downto 8);
                     dopa_ltmp(1) := memp(prcd_tmp_addra_dly_depth)(1);
                     prcd_x_buf (wr_mode_a_tmp, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);

                   end if;

                   if ((web_tmp(2) = '1' and wea_tmp(2) = '1') or (seq = "01" and web_tmp(2) = '1' and wea_tmp(2) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(2) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(2) /= '1')) then

                     doa_ltmp(23 downto 16) := mem(prcd_tmp_addra_dly_depth)(23 downto 16);
                     dopa_ltmp(2) := memp(prcd_tmp_addra_dly_depth)(2);
                     prcd_x_buf (wr_mode_a_tmp, 23, 16, 2, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);

                   end if;

                   if ((web_tmp(3) = '1' and wea_tmp(3) = '1') or (seq = "01" and web_tmp(3) = '1' and wea_tmp(3) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(3) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(3) /= '1')) then

                     doa_ltmp(31 downto 24) := mem(prcd_tmp_addra_dly_depth)(31 downto 24);
                     dopa_ltmp(3) := memp(prcd_tmp_addra_dly_depth)(3);
                     prcd_x_buf (wr_mode_a_tmp, 31, 24, 3, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);

                   end if;
  
                end if;
  
      when 64 =>
                   prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 6));

                   if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and web_tmp(0) = '1' and wea_tmp(0) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(0) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(0) /= '1')) then

                     doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)(7 downto 0);
                     dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(0);
                     prcd_x_buf (wr_mode_a_tmp, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);

                   end if;

                   if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and web_tmp(1) = '1' and wea_tmp(1) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(1) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(1) /= '1')) then

                     doa_ltmp(15 downto 8) := mem(prcd_tmp_addra_dly_depth)(15 downto 8);
                     dopa_ltmp(1) := memp(prcd_tmp_addra_dly_depth)(1);
                     prcd_x_buf (wr_mode_a_tmp, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);

                   end if;

                   if ((web_tmp(2) = '1' and wea_tmp(2) = '1') or (seq = "01" and web_tmp(2) = '1' and wea_tmp(2) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(2) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(2) /= '1')) then

                     doa_ltmp(23 downto 16) := mem(prcd_tmp_addra_dly_depth)(23 downto 16);
                     dopa_ltmp(2) := memp(prcd_tmp_addra_dly_depth)(2);
                     prcd_x_buf (wr_mode_a_tmp, 23, 16, 2, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);

                   end if;

                   if ((web_tmp(3) = '1' and wea_tmp(3) = '1') or (seq = "01" and web_tmp(3) = '1' and wea_tmp(3) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(3) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(3) /= '1')) then

                     doa_ltmp(31 downto 24) := mem(prcd_tmp_addra_dly_depth)(31 downto 24);
                     dopa_ltmp(3) := memp(prcd_tmp_addra_dly_depth)(3);
                     prcd_x_buf (wr_mode_a_tmp, 31, 24, 3, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);

                   end if;

                   if ((web_tmp(4) = '1' and wea_tmp(4) = '1') or (seq = "01" and web_tmp(4) = '1' and wea_tmp(4) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(4) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(4) /= '1')) then

                     doa_ltmp(39 downto 32) := mem(prcd_tmp_addra_dly_depth)(39 downto 32);
                     dopa_ltmp(4) := memp(prcd_tmp_addra_dly_depth)(4);
                     prcd_x_buf (wr_mode_a_tmp, 39, 32, 4, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);

                   end if;

                   if ((web_tmp(5) = '1' and wea_tmp(5) = '1') or (seq = "01" and web_tmp(5) = '1' and wea_tmp(5) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(5) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(5) /= '1')) then

                     doa_ltmp(47 downto 40) := mem(prcd_tmp_addra_dly_depth)(47 downto 40);
                     dopa_ltmp(5) := memp(prcd_tmp_addra_dly_depth)(5);
                     prcd_x_buf (wr_mode_a_tmp, 47, 40, 5, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);

                   end if;

                   if ((web_tmp(6) = '1' and wea_tmp(6) = '1') or (seq = "01" and web_tmp(6) = '1' and wea_tmp(6) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(6) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(6) /= '1')) then

                     doa_ltmp(55 downto 48) := mem(prcd_tmp_addra_dly_depth)(55 downto 48);
                     dopa_ltmp(6) := memp(prcd_tmp_addra_dly_depth)(6);
                     prcd_x_buf (wr_mode_a_tmp, 55, 48, 6, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);

                   end if;

                   if ((web_tmp(7) = '1' and wea_tmp(7) = '1') or (seq = "01" and web_tmp(7) = '1' and wea_tmp(7) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(7) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(7) /= '1')) then

                     doa_ltmp(63 downto 56) := mem(prcd_tmp_addra_dly_depth)(63 downto 56);
                     dopa_ltmp(7) := memp(prcd_tmp_addra_dly_depth)(7);
                     prcd_x_buf (wr_mode_a_tmp, 63, 56, 7, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp);

                   end if;
    
      when others => null;

    end case;

  end prcd_col_rd_ram_a;


  procedure prcd_col_rd_ram_b (
    constant viol_type_tmp : in std_logic_vector (1 downto 0);
    constant seq : in std_logic_vector (1 downto 0);
    constant wea_tmp : in std_logic_vector (7 downto 0);
    constant web_tmp : in std_logic_vector (7 downto 0);
    constant addrb_tmp : in std_logic_vector (15 downto 0);
    variable dob_tmp : inout std_logic_vector (63 downto 0);
    variable dopb_tmp : inout std_logic_vector (7 downto 0);
    constant mem : in Two_D_array_type;
    constant memp : in Two_D_parity_array_type;
    constant wr_mode_b_tmp : in std_logic_vector (1 downto 0)

    ) is
    variable prcd_tmp_addrb_dly_depth : integer;
    variable prcd_tmp_addrb_dly_width : integer;
    variable junk : std_ulogic;
    variable dob_ltmp : std_logic_vector (63 downto 0);
    variable dopb_ltmp : std_logic_vector (7 downto 0);
    
  begin

    dob_ltmp := (others => '0');
    dopb_ltmp := (others => '0');
    
    case rb_width is
      
      when 1 | 2 | 4 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and wea_tmp(0) = '1' and web_tmp(0) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(0) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(0) /= '1')) then

                          if (rb_width >= width) then
                            prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_lbit_124));
                            dob_ltmp(rb_width-1 downto 0) := mem(prcd_tmp_addrb_dly_depth);
                          else
                            prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_124 + 1));
                            prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_124 downto r_addrb_lbit_124));
                            dob_ltmp(rb_width-1 downto 0) := mem(prcd_tmp_addrb_dly_depth)(((prcd_tmp_addrb_dly_width * rb_width) + rb_width - 1) downto (prcd_tmp_addrb_dly_width * rb_width));
                          end if;
                          prcd_x_buf (wr_mode_b_tmp, 3, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);

                        end if;

      when 8 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and wea_tmp(0) = '1' and web_tmp(0) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(0) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(0) /= '1')) then

                  if (rb_width >= width) then
                    prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 3));
                    dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth);
                    dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(0);
                  else
                    prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_8 + 1));
                    prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_8 downto 3));
                    dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)(((prcd_tmp_addrb_dly_width * 8) + 7) downto (prcd_tmp_addrb_dly_width * 8));
                    dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(prcd_tmp_addrb_dly_width);
                  end if;
                  prcd_x_buf (wr_mode_b_tmp, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);

                end if;

      when 16 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and wea_tmp(0) = '1' and web_tmp(0) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(0) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(0) /= '1')) then

                  if (rb_width >= width) then
                    prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4));
                    dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)(7 downto 0);
                    dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(0);
                  else
                    prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_16 + 1));
                    prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_16 downto 4));

                    dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)(((prcd_tmp_addrb_dly_width * 16) + 7) downto (prcd_tmp_addrb_dly_width * 16));
                    dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(prcd_tmp_addrb_dly_width * 2);
                  end if;
                  prcd_x_buf (wr_mode_b_tmp, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);

                end if;


                if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and wea_tmp(1) = '1' and web_tmp(1) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(1) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(1) /= '1')) then

                  if (rb_width >= width) then
                    prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4));
                    dob_ltmp(15 downto 8) := mem(prcd_tmp_addrb_dly_depth)(15 downto 8);
                    dopb_ltmp(1) := memp(prcd_tmp_addrb_dly_depth)(1);
                  else
                    prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_16 + 1));
                    prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_16 downto 4));

                    dob_ltmp(15 downto 8) := mem(prcd_tmp_addrb_dly_depth)(((prcd_tmp_addrb_dly_width * 16) + 15) downto ((prcd_tmp_addrb_dly_width * 16) + 8));
                    dopb_ltmp(1) := memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2) + 1);
                  end if;
                  prcd_x_buf (wr_mode_b_tmp, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);

                end if;

      when 32 => if (rb_width >= width) then

                   prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 5));

                   if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and wea_tmp(0) = '1' and web_tmp(0) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(0) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(0) /= '1')) then

                     dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)(7 downto 0);
                     dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(0);
                     prcd_x_buf (wr_mode_b_tmp, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);

                   end if;

                   if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and wea_tmp(1) = '1' and web_tmp(1) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(1) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(1) /= '1')) then

                     dob_ltmp(15 downto 8) := mem(prcd_tmp_addrb_dly_depth)(15 downto 8);
                     dopb_ltmp(1) := memp(prcd_tmp_addrb_dly_depth)(1);
                     prcd_x_buf (wr_mode_b_tmp, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);

                   end if;

                   if ((web_tmp(2) = '1' and wea_tmp(2) = '1') or (seq = "01" and wea_tmp(2) = '1' and web_tmp(2) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(2) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(2) /= '1')) then

                     dob_ltmp(23 downto 16) := mem(prcd_tmp_addrb_dly_depth)(23 downto 16);
                     dopb_ltmp(2) := memp(prcd_tmp_addrb_dly_depth)(2);
                     prcd_x_buf (wr_mode_b_tmp, 23, 16, 2, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);

                   end if;
  
                   if ((web_tmp(3) = '1' and wea_tmp(3) = '1') or (seq = "01" and wea_tmp(3) = '1' and web_tmp(3) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(3) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(3) /= '1')) then

                     dob_ltmp(31 downto 24) := mem(prcd_tmp_addrb_dly_depth)(31 downto 24);
                     dopb_ltmp(3) := memp(prcd_tmp_addrb_dly_depth)(3);
                     prcd_x_buf (wr_mode_b_tmp, 31, 24, 3, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);

                   end if;
  
                end if;
  
      when 64 =>
                   prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 6));

                   if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and wea_tmp(0) = '1' and web_tmp(0) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(0) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(0) /= '1')) then

                     dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)(7 downto 0);
                     dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(0);
                     prcd_x_buf (wr_mode_b_tmp, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);

                   end if;

                   if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and wea_tmp(1) = '1' and web_tmp(1) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(1) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(1) /= '1')) then

                     dob_ltmp(15 downto 8) := mem(prcd_tmp_addrb_dly_depth)(15 downto 8);
                     dopb_ltmp(1) := memp(prcd_tmp_addrb_dly_depth)(1);
                     prcd_x_buf (wr_mode_b_tmp, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);

                   end if;

                   if ((web_tmp(2) = '1' and wea_tmp(2) = '1') or (seq = "01" and wea_tmp(2) = '1' and web_tmp(2) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(2) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(2) /= '1')) then

                     dob_ltmp(23 downto 16) := mem(prcd_tmp_addrb_dly_depth)(23 downto 16);
                     dopb_ltmp(2) := memp(prcd_tmp_addrb_dly_depth)(2);
                     prcd_x_buf (wr_mode_b_tmp, 23, 16, 2, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);

                   end if;

                   if ((web_tmp(3) = '1' and wea_tmp(3) = '1') or (seq = "01" and wea_tmp(3) = '1' and web_tmp(3) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(3) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(3) /= '1')) then

                     dob_ltmp(31 downto 24) := mem(prcd_tmp_addrb_dly_depth)(31 downto 24);
                     dopb_ltmp(3) := memp(prcd_tmp_addrb_dly_depth)(3);
                     prcd_x_buf (wr_mode_b_tmp, 31, 24, 3, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);

                   end if;

                   if ((web_tmp(4) = '1' and wea_tmp(4) = '1') or (seq = "01" and wea_tmp(4) = '1' and web_tmp(4) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(4) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(4) /= '1')) then

                     dob_ltmp(39 downto 32) := mem(prcd_tmp_addrb_dly_depth)(39 downto 32);
                     dopb_ltmp(4) := memp(prcd_tmp_addrb_dly_depth)(4);
                     prcd_x_buf (wr_mode_b_tmp, 39, 32, 4, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);

                   end if;
  
                   if ((web_tmp(5) = '1' and wea_tmp(5) = '1') or (seq = "01" and wea_tmp(5) = '1' and web_tmp(5) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(5) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(5) /= '1')) then

                     dob_ltmp(47 downto 40) := mem(prcd_tmp_addrb_dly_depth)(47 downto 40);
                     dopb_ltmp(5) := memp(prcd_tmp_addrb_dly_depth)(5);
                     prcd_x_buf (wr_mode_b_tmp, 47, 40, 5, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);

                   end if;

                   if ((web_tmp(6) = '1' and wea_tmp(6) = '1') or (seq = "01" and wea_tmp(6) = '1' and web_tmp(6) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(6) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(6) /= '1')) then

                     dob_ltmp(55 downto 48) := mem(prcd_tmp_addrb_dly_depth)(55 downto 48);
                     dopb_ltmp(6) := memp(prcd_tmp_addrb_dly_depth)(6);
                     prcd_x_buf (wr_mode_b_tmp, 55, 48, 6, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);

                   end if;
  
                   if ((web_tmp(7) = '1' and wea_tmp(7) = '1') or (seq = "01" and wea_tmp(7) = '1' and web_tmp(7) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(7) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(7) /= '1')) then

                     dob_ltmp(63 downto 56) := mem(prcd_tmp_addrb_dly_depth)(63 downto 56);
                     dopb_ltmp(7) := memp(prcd_tmp_addrb_dly_depth)(7);
                     prcd_x_buf (wr_mode_b_tmp, 63, 56, 7, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp);

                   end if;
    
      when others => null;

    end case;

  end prcd_col_rd_ram_b;


  procedure prcd_wr_ram_a (
    constant wea_tmp : in std_logic_vector (7 downto 0);
    constant dia_tmp : in std_logic_vector (63 downto 0);
    constant dipa_tmp : in std_logic_vector (7 downto 0);
    constant addra_tmp : in std_logic_vector (15 downto 0);
    variable mem : inout Two_D_array_type;
    variable memp : inout Two_D_parity_array_type;
    constant syndrome_tmp : in std_logic_vector (7 downto 0)
    ) is
    variable prcd_tmp_addra_dly_depth : integer;
    variable prcd_tmp_addra_dly_width : integer;
    variable junk : std_ulogic;

  begin
    
    case wa_width is

      when 1 | 2 | 4 =>
                          if (wa_width >= width) then
                            prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_lbit_124));
                            prcd_write_ram (wea_tmp(0), dia_tmp(wa_width-1 downto 0), '0', mem(prcd_tmp_addra_dly_depth), junk);
                          else
                            prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_124 + 1));
                            prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_124 downto w_addra_lbit_124));
                            prcd_write_ram (wea_tmp(0), dia_tmp(wa_width-1 downto 0), '0', mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * wa_width) + wa_width - 1 downto (prcd_tmp_addra_dly_width * wa_width)), junk);
                          end if;

      when 8 =>
                  if (wa_width >= width) then
                    prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 3));
                    prcd_write_ram (wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth), memp(prcd_tmp_addra_dly_depth)(0));
                  else
                    prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_8 + 1));
                    prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_8 downto 3));
                    prcd_write_ram (wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 8) + 7 downto (prcd_tmp_addra_dly_width * 8)), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width)));
                  end if;
  
      when 16 =>
                  if (wa_width >= width) then
                    prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4));
                    prcd_write_ram (wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0));
                    prcd_write_ram (wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1));
                  else
                    prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_16 + 1));
                    prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_16 downto 4));
                    prcd_write_ram (wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 16) + 7 downto (prcd_tmp_addra_dly_width * 16)), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2)));
                    prcd_write_ram (wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 16) + 15 downto (prcd_tmp_addra_dly_width * 16) + 8), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2) + 1));
                  end if;

      when 32 =>
                   prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 5));

                   prcd_write_ram (wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0));
                   prcd_write_ram (wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1));
                   prcd_write_ram (wea_tmp(2), dia_tmp(23 downto 16), dipa_tmp(2), mem(prcd_tmp_addra_dly_depth)(23 downto 16), memp(prcd_tmp_addra_dly_depth)(2));
                   prcd_write_ram (wea_tmp(3), dia_tmp(31 downto 24), dipa_tmp(3), mem(prcd_tmp_addra_dly_depth)(31 downto 24), memp(prcd_tmp_addra_dly_depth)(3));

      when 64 => if (syndrome_tmp /= "00000000" and syndrome_tmp(7) = '1' and EN_ECC_SCRUB = TRUE) then

                   prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 6));
                   prcd_write_ram ('1', dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0));
                   prcd_write_ram ('1', dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1));
                   prcd_write_ram ('1', dia_tmp(23 downto 16), dipa_tmp(2), mem(prcd_tmp_addra_dly_depth)(23 downto 16), memp(prcd_tmp_addra_dly_depth)(2));
                   prcd_write_ram ('1', dia_tmp(31 downto 24), dipa_tmp(3), mem(prcd_tmp_addra_dly_depth)(31 downto 24), memp(prcd_tmp_addra_dly_depth)(3));
                   prcd_write_ram ('1', dia_tmp(39 downto 32), dipa_tmp(4), mem(prcd_tmp_addra_dly_depth)(39 downto 32), memp(prcd_tmp_addra_dly_depth)(4));
                   prcd_write_ram ('1', dia_tmp(47 downto 40), dipa_tmp(5), mem(prcd_tmp_addra_dly_depth)(47 downto 40), memp(prcd_tmp_addra_dly_depth)(5));
                   prcd_write_ram ('1', dia_tmp(55 downto 48), dipa_tmp(6), mem(prcd_tmp_addra_dly_depth)(55 downto 48), memp(prcd_tmp_addra_dly_depth)(6));
                   prcd_write_ram ('1', dia_tmp(63 downto 56), dipa_tmp(7), mem(prcd_tmp_addra_dly_depth)(63 downto 56), memp(prcd_tmp_addra_dly_depth)(7));

                 end if;

      when others => null;

    end case;

  end prcd_wr_ram_a;


  procedure prcd_wr_ram_b (
    constant web_tmp : in std_logic_vector (7 downto 0);
    constant dib_tmp : in std_logic_vector (63 downto 0);
    constant dipb_tmp : in std_logic_vector (7 downto 0);
    constant addrb_tmp : in std_logic_vector (15 downto 0);
    variable mem : inout Two_D_array_type;
    variable memp : inout Two_D_parity_array_type     
    ) is
    variable prcd_tmp_addrb_dly_depth : integer;
    variable prcd_tmp_addrb_dly_width : integer;
    variable junk : std_ulogic;

  begin
    
    case wb_width is

      when 1 | 2 | 4 =>
                          if (wb_width >= width) then
                            prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_lbit_124));
                            prcd_write_ram (web_tmp(0), dib_tmp(wb_width-1 downto 0), '0', mem(prcd_tmp_addrb_dly_depth), junk);
                          else
                            prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_124 + 1));
                            prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_124 downto w_addrb_lbit_124));
                            prcd_write_ram (web_tmp(0), dib_tmp(wb_width-1 downto 0), '0', mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * wb_width) + wb_width - 1 downto (prcd_tmp_addrb_dly_width * wb_width)), junk);
                          end if;

      when 8 => 
                  if (wb_width >= width) then
                    prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 3));
                    prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth), memp(prcd_tmp_addrb_dly_depth)(0));
                  else
                    prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_8 + 1));
                    prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_8 downto 3));
                    prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 8) + 7 downto (prcd_tmp_addrb_dly_width * 8)), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width)));
                  end if;
  
      when 16 =>
                  if (wb_width >= width) then
                    prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4));
                    prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0));
                    prcd_write_ram (web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1));
                  else
                    prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_16 + 1));
                    prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_16 downto 4));
                    prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 16) + 7 downto (prcd_tmp_addrb_dly_width * 16)), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2)));
                    prcd_write_ram (web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 16) + 15 downto (prcd_tmp_addrb_dly_width * 16) + 8), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2) + 1));
                  end if;

      when 32 =>
                   prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 5));
                   prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0));
                   prcd_write_ram (web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1));
                   prcd_write_ram (web_tmp(2), dib_tmp(23 downto 16), dipb_tmp(2), mem(prcd_tmp_addrb_dly_depth)(23 downto 16), memp(prcd_tmp_addrb_dly_depth)(2));
                   prcd_write_ram (web_tmp(3), dib_tmp(31 downto 24), dipb_tmp(3), mem(prcd_tmp_addrb_dly_depth)(31 downto 24), memp(prcd_tmp_addrb_dly_depth)(3));

      when 64 =>
                   prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 6));
                   prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0));
                   prcd_write_ram (web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1));
                   prcd_write_ram (web_tmp(2), dib_tmp(23 downto 16), dipb_tmp(2), mem(prcd_tmp_addrb_dly_depth)(23 downto 16), memp(prcd_tmp_addrb_dly_depth)(2));
                   prcd_write_ram (web_tmp(3), dib_tmp(31 downto 24), dipb_tmp(3), mem(prcd_tmp_addrb_dly_depth)(31 downto 24), memp(prcd_tmp_addrb_dly_depth)(3));
                   prcd_write_ram (web_tmp(4), dib_tmp(39 downto 32), dipb_tmp(4), mem(prcd_tmp_addrb_dly_depth)(39 downto 32), memp(prcd_tmp_addrb_dly_depth)(4));
                   prcd_write_ram (web_tmp(5), dib_tmp(47 downto 40), dipb_tmp(5), mem(prcd_tmp_addrb_dly_depth)(47 downto 40), memp(prcd_tmp_addrb_dly_depth)(5));
                   prcd_write_ram (web_tmp(6), dib_tmp(55 downto 48), dipb_tmp(6), mem(prcd_tmp_addrb_dly_depth)(55 downto 48), memp(prcd_tmp_addrb_dly_depth)(6));
                   prcd_write_ram (web_tmp(7), dib_tmp(63 downto 56), dipb_tmp(7), mem(prcd_tmp_addrb_dly_depth)(63 downto 56), memp(prcd_tmp_addrb_dly_depth)(7));

      when others => null;

    end case;

  end prcd_wr_ram_b;
    
    
  procedure prcd_col_ecc_read (

    variable do_tmp : inout std_logic_vector (63 downto 0);
    variable dop_tmp : inout std_logic_vector (7 downto 0);
    constant addr_tmp : in std_logic_vector (15 downto 0);
    variable dbiterr_tmp : inout std_logic;
    variable sbiterr_tmp : inout std_logic;
    variable mem : inout Two_D_array_type;
    variable memp : inout Two_D_parity_array_type;
    variable prcd_syndrome : inout std_logic_vector (7 downto 0)
    ) is

    variable prcd_ecc_bit_position : std_logic_vector (71 downto 0);
    variable prcd_dopr_ecc : std_logic_vector (7 downto 0);
    variable prcd_di_dly_ecc_corrected : std_logic_vector (63 downto 0);
    variable prcd_dip_dly_ecc_corrected : std_logic_vector (7 downto 0);
    variable prcd_tmp_syndrome_int : integer := 0;
    
  begin

    prcd_dopr_ecc := fn_dip_ecc('0', do_tmp, dop_tmp);

    prcd_syndrome := prcd_dopr_ecc xor dop_tmp;

    if (prcd_syndrome /= "00000000") then

      if (prcd_syndrome(7) = '1') then  -- dectect single bit error

        prcd_ecc_bit_position := do_tmp(63 downto 57) & dop_tmp(6) & do_tmp(56 downto 26) & dop_tmp(5) & do_tmp(25 downto 11) & dop_tmp(4) & do_tmp(10 downto 4) & dop_tmp(3) & do_tmp(3 downto 1) & dop_tmp(2) & do_tmp(0) & dop_tmp(1 downto 0) & dop_tmp(7);

        prcd_tmp_syndrome_int := SLV_TO_INT(prcd_syndrome(6 downto 0));
        prcd_ecc_bit_position(prcd_tmp_syndrome_int) := not prcd_ecc_bit_position(prcd_tmp_syndrome_int); -- correct single bit error in the output 

        prcd_di_dly_ecc_corrected := prcd_ecc_bit_position(71 downto 65) & prcd_ecc_bit_position(63 downto 33) & prcd_ecc_bit_position(31 downto 17) & prcd_ecc_bit_position(15 downto 9) & prcd_ecc_bit_position(7 downto 5) & prcd_ecc_bit_position(3); -- correct single bit error in the memory

        do_tmp := prcd_di_dly_ecc_corrected;
			
        prcd_dip_dly_ecc_corrected := prcd_ecc_bit_position(0) & prcd_ecc_bit_position(64) & prcd_ecc_bit_position(32) & prcd_ecc_bit_position(16) & prcd_ecc_bit_position(8) & prcd_ecc_bit_position(4) & prcd_ecc_bit_position(2 downto 1); -- correct single bit error in the parity memory
                
        dop_tmp := prcd_dip_dly_ecc_corrected;
                
        dbiterr_tmp := '0';
        sbiterr_tmp := '1';

      elsif (prcd_syndrome(7) = '0') then  -- double bit error
        sbiterr_tmp := '0';
        dbiterr_tmp := '1';
      end if;
    else
      dbiterr_tmp := '0';
      sbiterr_tmp := '0';
    end if;
    
    if (ssra_dly = '1') then  -- ssra reset 
      dbiterr_tmp := '0';
      sbiterr_tmp := '0';    
    end if;
    
    if (prcd_syndrome /= "00000000" and prcd_syndrome(7) = '1' and EN_ECC_SCRUB = TRUE) then
      prcd_wr_ram_a ("11111111", prcd_di_dly_ecc_corrected, prcd_dip_dly_ecc_corrected, addr_tmp, mem, memp, prcd_syndrome);
    end if;
    
  end prcd_col_ecc_read;

  
  begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

    addra_dly      	 <= ADDRA          	after 0 ps;
    addrb_dly      	 <= ADDRB          	after 0 ps;
    cascadeinlata_dly 	 <= CASCADEINLATA     	after 0 ps;
    cascadeinlatb_dly 	 <= CASCADEINLATB     	after 0 ps;
    cascadeinrega_dly 	 <= CASCADEINREGA     	after 0 ps;
    cascadeinregb_dly 	 <= CASCADEINREGB     	after 0 ps;
    clka_dly       	 <= CLKA           	after 0 ps;
    clkb_dly       	 <= CLKB           	after 0 ps;
    dia_dly        	 <= DIA            	after 0 ps;
    dib_dly        	 <= DIB            	after 0 ps;
    dipa_dly       	 <= DIPA           	after 0 ps;
    dipb_dly       	 <= DIPB           	after 0 ps;
    ena_dly        	 <= ENA            	after 0 ps;
    enb_dly        	 <= ENB            	after 0 ps;
    regcea_dly     	 <= REGCEA         	after 0 ps;
    regceb_dly     	 <= REGCEB         	after 0 ps;
    ssra_dly       	 <= SSRA           	after 0 ps;
    ssrb_dly       	 <= SSRB           	after 0 ps;
    wea_dly        	 <= WEA            	after 0 ps;
    web_dly        	 <= WEB            	after 0 ps;
    gsr_dly        	 <= GSR            	after 0 ps;
    regclka_dly        	 <= REGCLKA            	after 0 ps;
    regclkb_dly        	 <= REGCLKB            	after 0 ps;    

  --------------------
  --  BEHAVIOR SECTION
  --------------------

  ---------------------------------------------------------------------------
  -- SAFE mode
  ---------------------------------------------------------------------------

  safe_mode : if (SIM_MODE = "SAFE") generate

    prcs_clk: process (clka_dly, clkb_dly, gsr_dly)

      variable mem_slv : std_logic_vector(32767 downto 0) := To_StdLogicVector(INIT_7F) &
                                                       To_StdLogicVector(INIT_7E) &
                                                       To_StdLogicVector(INIT_7D) &
                                                       To_StdLogicVector(INIT_7C) &
                                                       To_StdLogicVector(INIT_7B) &
                                                       To_StdLogicVector(INIT_7A) &
                                                       To_StdLogicVector(INIT_79) &
                                                       To_StdLogicVector(INIT_78) &
                                                       To_StdLogicVector(INIT_77) &
                                                       To_StdLogicVector(INIT_76) &
                                                       To_StdLogicVector(INIT_75) &
                                                       To_StdLogicVector(INIT_74) &
                                                       To_StdLogicVector(INIT_73) &
                                                       To_StdLogicVector(INIT_72) &
                                                       To_StdLogicVector(INIT_71) &
                                                       To_StdLogicVector(INIT_70) &
                                                       To_StdLogicVector(INIT_6F) &
                                                       To_StdLogicVector(INIT_6E) &
                                                       To_StdLogicVector(INIT_6D) &
                                                       To_StdLogicVector(INIT_6C) &
                                                       To_StdLogicVector(INIT_6B) &
                                                       To_StdLogicVector(INIT_6A) &
                                                       To_StdLogicVector(INIT_69) &
                                                       To_StdLogicVector(INIT_68) &
                                                       To_StdLogicVector(INIT_67) &
                                                       To_StdLogicVector(INIT_66) &
                                                       To_StdLogicVector(INIT_65) &
                                                       To_StdLogicVector(INIT_64) &
                                                       To_StdLogicVector(INIT_63) &
                                                       To_StdLogicVector(INIT_62) &
                                                       To_StdLogicVector(INIT_61) &
                                                       To_StdLogicVector(INIT_60) &
                                                       To_StdLogicVector(INIT_5F) &
                                                       To_StdLogicVector(INIT_5E) &
                                                       To_StdLogicVector(INIT_5D) &
                                                       To_StdLogicVector(INIT_5C) &
                                                       To_StdLogicVector(INIT_5B) &
                                                       To_StdLogicVector(INIT_5A) &
                                                       To_StdLogicVector(INIT_59) &
                                                       To_StdLogicVector(INIT_58) &
                                                       To_StdLogicVector(INIT_57) &
                                                       To_StdLogicVector(INIT_56) &
                                                       To_StdLogicVector(INIT_55) &
                                                       To_StdLogicVector(INIT_54) &
                                                       To_StdLogicVector(INIT_53) &
                                                       To_StdLogicVector(INIT_52) &
                                                       To_StdLogicVector(INIT_51) &
                                                       To_StdLogicVector(INIT_50) &
                                                       To_StdLogicVector(INIT_4F) &
                                                       To_StdLogicVector(INIT_4E) &
                                                       To_StdLogicVector(INIT_4D) &
                                                       To_StdLogicVector(INIT_4C) &
                                                       To_StdLogicVector(INIT_4B) &
                                                       To_StdLogicVector(INIT_4A) &
                                                       To_StdLogicVector(INIT_49) &
                                                       To_StdLogicVector(INIT_48) &
                                                       To_StdLogicVector(INIT_47) &
                                                       To_StdLogicVector(INIT_46) &
                                                       To_StdLogicVector(INIT_45) &
                                                       To_StdLogicVector(INIT_44) &
                                                       To_StdLogicVector(INIT_43) &
                                                       To_StdLogicVector(INIT_42) &
                                                       To_StdLogicVector(INIT_41) &
                                                       To_StdLogicVector(INIT_40) &
                                                       To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable memp_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INITP_0F) &
                                                       To_StdLogicVector(INITP_0E) &
                                                       To_StdLogicVector(INITP_0D) &
                                                       To_StdLogicVector(INITP_0C) &
                                                       To_StdLogicVector(INITP_0B) &
                                                       To_StdLogicVector(INITP_0A) &
                                                       To_StdLogicVector(INITP_09) &
                                                       To_StdLogicVector(INITP_08) &
                                                       To_StdLogicVector(INITP_07) &
                                                       To_StdLogicVector(INITP_06) &
                                                       To_StdLogicVector(INITP_05) &
                                                       To_StdLogicVector(INITP_04) &
                                                       To_StdLogicVector(INITP_03) &
                                                       To_StdLogicVector(INITP_02) &
                                                       To_StdLogicVector(INITP_01) &
                                                       To_StdLogicVector(INITP_00);

    variable tmp_mem : Two_D_array_type_tmp_mem := two_D_mem_initf(widest_width);
    variable mem : Two_D_array_type := two_D_mem_init(mem_depth, width, mem_slv, tmp_mem);
    variable memp : Two_D_parity_array_type := two_D_mem_initp(memp_depth, widthp, memp_slv, tmp_mem, width);
    variable tmp_addra_dly_depth : integer;
    variable tmp_addra_dly_width : integer;
    variable tmp_addrb_dly_depth : integer;
    variable tmp_addrb_dly_width : integer;
    variable junk1 : std_logic;
    variable wr_mode_a : std_logic_vector(1 downto 0) := "00";
    variable wr_mode_b : std_logic_vector(1 downto 0) := "00";
    variable tmp_syndrome_int : integer;    
    variable doa_buf : std_logic_vector(63 downto 0) := (others => '0');
    variable dob_buf : std_logic_vector(63 downto 0) := (others => '0');
    variable dopa_buf : std_logic_vector(7 downto 0) := (others => '0');
    variable dopb_buf : std_logic_vector(7 downto 0) := (others => '0');    
    variable syndrome : std_logic_vector(7 downto 0) := (others => '0');
    variable dopr_ecc : std_logic_vector(7 downto 0) := (others => '0');        
    variable dia_dly_ecc_corrected : std_logic_vector(63 downto 0) := (others => '0');
    variable dipa_dly_ecc_corrected : std_logic_vector(7 downto 0) := (others => '0');
    variable dip_ecc : std_logic_vector(7 downto 0) := (others => '0');
    variable dipb_dly_ecc : std_logic_vector(7 downto 0) := (others => '0');        
    variable ecc_bit_position : std_logic_vector(71 downto 0) := (others => '0');
    variable addra_dly_15_reg_var : std_logic := '0';
    variable addrb_dly_15_reg_var : std_logic := '0';
    variable addra_dly_15_reg_bram_var : std_logic := '0';
    variable addrb_dly_15_reg_bram_var : std_logic := '0';
    variable FIRST_TIME : boolean := true;

    variable curr_time : time := 0 ps;
    variable prev_time : time := 0 ps;
    variable viol_time : integer := 0;
    variable viol_type : std_logic_vector(1 downto 0) := (others => '0');
    variable message : line;
    variable dip_ecc_col : std_logic_vector (7 downto 0) := (others => '0');
    variable dbiterr_out_var : std_ulogic := '0';
    variable sbiterr_out_var : std_ulogic := '0';

    variable dia_reg_dly : std_logic_vector(63 downto 0) := (others => '0');
    variable dipa_reg_dly : std_logic_vector(7 downto 0) := (others => '0');
    variable wea_reg_dly : std_logic_vector(7 downto 0) := (others => '0');
    variable addra_reg_dly : std_logic_vector(15 downto 0) := (others => '0');
    variable dib_reg_dly : std_logic_vector(63 downto 0) := (others => '0');
    variable dipb_reg_dly : std_logic_vector(7 downto 0) := (others => '0');
    variable web_reg_dly : std_logic_vector(7 downto 0) := (others => '0');
    variable addrb_reg_dly : std_logic_vector(15 downto 0) := (others => '0');
    variable col_wr_wr_msg : std_ulogic := '1';
    variable col_wra_rdb_msg : std_ulogic := '1';
    variable col_wrb_rda_msg : std_ulogic := '1';
    variable addr_col : std_logic := '0';
    
  begin  -- process prcs_clka    

    if (FIRST_TIME) then

      if (SIM_MODE /= "FAST" and SIM_MODE /= "SAFE") then
        GenericValueCheckMessage
          ( HeaderMsg            => " Attribute Syntax Error : ",
            GenericName          => " SIM_MODE ",
            EntityName           => "ARAMB36_INTERNAL",
            GenericValue         => SIM_MODE,
            Unit                 => "",
            ExpectedValueMsg     => " The Legal values for this attribute are ",
            ExpectedGenericValue => " FAST or SAFE ",
            TailMsg              => "",
            MsgSeverity          => failure
            );
      end if;
      
      case READ_WIDTH_A is
        when 0 | 1 | 2 | 4 | 9 | 18 => null;
        when 36 => if (BRAM_SIZE = 18 and BRAM_MODE = "TRUE_DUAL_PORT") then
                       GenericValueCheckMessage
                        (  HeaderMsg            => " Attribute Syntax Error : ",
                           GenericName          => " READ_WIDTH_A ",
                           EntityName           => "ARAMB36_INTERNAL",
                           GenericValue         => READ_WIDTH_A,
                           Unit                 => "",
                           ExpectedValueMsg     => " The Legal values for this attribute are ",
                           ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
                           TailMsg              => "",
                           MsgSeverity          => failure
                           );
                   end if;
        when 72 => if (BRAM_SIZE = 18) then
                       GenericValueCheckMessage
                        (  HeaderMsg            => " Attribute Syntax Error : ",
                           GenericName          => " READ_WIDTH_A ",
                           EntityName           => "ARAMB36_INTERNAL",
                           GenericValue         => READ_WIDTH_A,
                           Unit                 => "",
                           ExpectedValueMsg     => " The Legal values for this attribute are ",
                           ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
                           TailMsg              => "",
                           MsgSeverity          => failure
                           );
                   elsif ((BRAM_SIZE = 16 or BRAM_SIZE = 36) and BRAM_MODE = "TRUE_DUAL_PORT") then
                       GenericValueCheckMessage
                        (  HeaderMsg            => " Attribute Syntax Error : ",
                           GenericName          => " READ_WIDTH_A ",
                           EntityName           => "ARAMB36_INTERNAL",
                           GenericValue         => READ_WIDTH_A,
                           Unit                 => "",
                           ExpectedValueMsg     => " The Legal values for this attribute are ",
                           ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.",
                           TailMsg              => "",
                           MsgSeverity          => failure
                           );
                   end if;
        when others => if (BRAM_SIZE = 18) then
                         GenericValueCheckMessage
                           (  HeaderMsg            => " Attribute Syntax Error : ",
                              GenericName          => " READ_WIDTH_A ",
                              EntityName           => "ARAMB36_INTERNAL",
                              GenericValue         => READ_WIDTH_A,
                              Unit                 => "",
                              ExpectedValueMsg     => " The Legal values for this attribute are ",
                              ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
                              TailMsg              => "",
                              MsgSeverity          => failure
                              );
                       elsif (BRAM_SIZE = 16 or BRAM_SIZE = 36) then
                         GenericValueCheckMessage
                           (  HeaderMsg            => " Attribute Syntax Error : ",
                              GenericName          => " READ_WIDTH_A ",
                              EntityName           => "ARAMB36_INTERNAL",
                              GenericValue         => READ_WIDTH_A,
                              Unit                 => "",
                              ExpectedValueMsg     => " The Legal values for this attribute are ",
                              ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.",
                              TailMsg              => "",
                              MsgSeverity          => failure
                              );
                       end if;
      end case;


      case READ_WIDTH_B is
        when 0 | 1 | 2 | 4 | 9 | 18 => null;
        when 36 => if (BRAM_SIZE = 18 and BRAM_MODE = "TRUE_DUAL_PORT") then
                       GenericValueCheckMessage
                        (  HeaderMsg            => " Attribute Syntax Error : ",
                           GenericName          => " READ_WIDTH_B ",
                           EntityName           => "ARAMB36_INTERNAL",
                           GenericValue         => READ_WIDTH_B,
                           Unit                 => "",
                           ExpectedValueMsg     => " The Legal values for this attribute are ",
                           ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
                           TailMsg              => "",
                           MsgSeverity          => failure
                           );
                   end if;
        when 72 => if (BRAM_SIZE = 18) then
                       GenericValueCheckMessage
                        (  HeaderMsg            => " Attribute Syntax Error : ",
                           GenericName          => " READ_WIDTH_B ",
                           EntityName           => "ARAMB36_INTERNAL",
                           GenericValue         => READ_WIDTH_B,
                           Unit                 => "",
                           ExpectedValueMsg     => " The Legal values for this attribute are ",
                           ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
                           TailMsg              => "",
                           MsgSeverity          => failure
                           );
                   elsif ((BRAM_SIZE = 16 or BRAM_SIZE = 36) and BRAM_MODE = "TRUE_DUAL_PORT") then
                       GenericValueCheckMessage
                        (  HeaderMsg            => " Attribute Syntax Error : ",
                           GenericName          => " READ_WIDTH_B ",
                           EntityName           => "ARAMB36_INTERNAL",
                           GenericValue         => READ_WIDTH_B,
                           Unit                 => "",
                           ExpectedValueMsg     => " The Legal values for this attribute are ",
                           ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.",
                           TailMsg              => "",
                           MsgSeverity          => failure
                           );
                   end if;
        when others => if (BRAM_SIZE = 18) then
                         GenericValueCheckMessage
                           (  HeaderMsg            => " Attribute Syntax Error : ",
                              GenericName          => " READ_WIDTH_B ",
                              EntityName           => "ARAMB36_INTERNAL",
                              GenericValue         => READ_WIDTH_B,
                              Unit                 => "",
                              ExpectedValueMsg     => " The Legal values for this attribute are ",
                              ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
                              TailMsg              => "",
                              MsgSeverity          => failure
                              );
                       elsif (BRAM_SIZE = 16 or BRAM_SIZE = 36) then
                         GenericValueCheckMessage
                           (  HeaderMsg            => " Attribute Syntax Error : ",
                              GenericName          => " READ_WIDTH_B ",
                              EntityName           => "ARAMB36_INTERNAL",
                              GenericValue         => READ_WIDTH_B,
                              Unit                 => "",
                              ExpectedValueMsg     => " The Legal values for this attribute are ",
                              ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.",
                              TailMsg              => "",
                              MsgSeverity          => failure
                              );
                       end if;
      end case;


      case WRITE_WIDTH_A is
        when 0 | 1 | 2 | 4 | 9 | 18 => null;
        when 36 => if (BRAM_SIZE = 18 and BRAM_MODE = "TRUE_DUAL_PORT") then
                       GenericValueCheckMessage
                        (  HeaderMsg            => " Attribute Syntax Error : ",
                           GenericName          => " WRITE_WIDTH_A ",
                           EntityName           => "ARAMB36_INTERNAL",
                           GenericValue         => WRITE_WIDTH_A,
                           Unit                 => "",
                           ExpectedValueMsg     => " The Legal values for this attribute are ",
                           ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
                           TailMsg              => "",
                           MsgSeverity          => failure
                           );
                   end if;
        when 72 => if (BRAM_SIZE = 18) then
                       GenericValueCheckMessage
                        (  HeaderMsg            => " Attribute Syntax Error : ",
                           GenericName          => " WRITE_WIDTH_A ",
                           EntityName           => "ARAMB36_INTERNAL",
                           GenericValue         => WRITE_WIDTH_A,
                           Unit                 => "",
                           ExpectedValueMsg     => " The Legal values for this attribute are ",
                           ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
                           TailMsg              => "",
                           MsgSeverity          => failure
                           );
                   elsif ((BRAM_SIZE = 16 or BRAM_SIZE = 36) and BRAM_MODE = "TRUE_DUAL_PORT") then
                       GenericValueCheckMessage
                        (  HeaderMsg            => " Attribute Syntax Error : ",
                           GenericName          => " WRITE_WIDTH_A ",
                           EntityName           => "ARAMB36_INTERNAL",
                           GenericValue         => WRITE_WIDTH_A,
                           Unit                 => "",
                           ExpectedValueMsg     => " The Legal values for this attribute are ",
                           ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.",
                           TailMsg              => "",
                           MsgSeverity          => failure
                           );
                   end if;
        when others => if (BRAM_SIZE = 18) then
                         GenericValueCheckMessage
                           (  HeaderMsg            => " Attribute Syntax Error : ",
                              GenericName          => " WRITE_WIDTH_A ",
                              EntityName           => "ARAMB36_INTERNAL",
                              GenericValue         => WRITE_WIDTH_A,
                              Unit                 => "",
                              ExpectedValueMsg     => " The Legal values for this attribute are ",
                              ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
                              TailMsg              => "",
                              MsgSeverity          => failure
                              );
                       elsif (BRAM_SIZE = 16 or BRAM_SIZE = 36) then
                         GenericValueCheckMessage
                           (  HeaderMsg            => " Attribute Syntax Error : ",
                              GenericName          => " WRITE_WIDTH_A ",
                              EntityName           => "ARAMB36_INTERNAL",
                              GenericValue         => WRITE_WIDTH_A,
                              Unit                 => "",
                              ExpectedValueMsg     => " The Legal values for this attribute are ",
                              ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.",
                              TailMsg              => "",
                              MsgSeverity          => failure
                              );
                       end if;
      end case;


      case WRITE_WIDTH_B is
        when 0 | 1 | 2 | 4 | 9 | 18 => null;
        when 36 => if (BRAM_SIZE = 18 and BRAM_MODE = "TRUE_DUAL_PORT") then
                       GenericValueCheckMessage
                        (  HeaderMsg            => " Attribute Syntax Error : ",
                           GenericName          => " WRITE_WIDTH_B ",
                           EntityName           => "ARAMB36_INTERNAL",
                           GenericValue         => WRITE_WIDTH_B,
                           Unit                 => "",
                           ExpectedValueMsg     => " The Legal values for this attribute are ",
                           ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
                           TailMsg              => "",
                           MsgSeverity          => failure
                           );
                   end if;
        when 72 => if (BRAM_SIZE = 18) then
                       GenericValueCheckMessage
                        (  HeaderMsg            => " Attribute Syntax Error : ",
                           GenericName          => " WRITE_WIDTH_B ",
                           EntityName           => "ARAMB36_INTERNAL",
                           GenericValue         => WRITE_WIDTH_B,
                           Unit                 => "",
                           ExpectedValueMsg     => " The Legal values for this attribute are ",
                           ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
                           TailMsg              => "",
                           MsgSeverity          => failure
                           );
                   elsif ((BRAM_SIZE = 16 or BRAM_SIZE = 36) and BRAM_MODE = "TRUE_DUAL_PORT") then
                       GenericValueCheckMessage
                        (  HeaderMsg            => " Attribute Syntax Error : ",
                           GenericName          => " WRITE_WIDTH_B ",
                           EntityName           => "ARAMB36_INTERNAL",
                           GenericValue         => WRITE_WIDTH_B,
                           Unit                 => "",
                           ExpectedValueMsg     => " The Legal values for this attribute are ",
                           ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.",
                           TailMsg              => "",
                           MsgSeverity          => failure
                           );
                   end if;
        when others => if (BRAM_SIZE = 18) then
                         GenericValueCheckMessage
                           (  HeaderMsg            => " Attribute Syntax Error : ",
                              GenericName          => " WRITE_WIDTH_B ",
                              EntityName           => "ARAMB36_INTERNAL",
                              GenericValue         => WRITE_WIDTH_B,
                              Unit                 => "",
                              ExpectedValueMsg     => " The Legal values for this attribute are ",
                              ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.",
                              TailMsg              => "",
                              MsgSeverity          => failure
                              );
                       elsif (BRAM_SIZE = 16 or BRAM_SIZE = 36) then
                         GenericValueCheckMessage
                           (  HeaderMsg            => " Attribute Syntax Error : ",
                              GenericName          => " WRITE_WIDTH_B ",
                              EntityName           => "ARAMB36_INTERNAL",
                              GenericValue         => WRITE_WIDTH_B,
                              Unit                 => "",
                              ExpectedValueMsg     => " The Legal values for this attribute are ",
                              ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.",
                              TailMsg              => "",
                              MsgSeverity          => failure
                              );
                       end if;
      end case;

      
      if (not(EN_ECC_READ = TRUE or EN_ECC_READ = FALSE)) then

        GenericValueCheckMessage
          ( HeaderMsg            => " Attribute Syntax Error : ",
            GenericName          => " EN_ECC_READ ",
            EntityName           => "ARAMB36_INTERNAL",
            GenericValue         => EN_ECC_READ,
            Unit                 => "",
            ExpectedValueMsg     => " The Legal values for this attribute are ",
            ExpectedGenericValue => " TRUE or FALSE ",
            TailMsg              => "",
            MsgSeverity          => failure
            );
      end if;

      if (not(EN_ECC_WRITE = TRUE or EN_ECC_WRITE = FALSE)) then

        GenericValueCheckMessage
          ( HeaderMsg            => " Attribute Syntax Error : ",
            GenericName          => " EN_ECC_WRITE ",
            EntityName           => "ARAMB36_INTERNAL",
            GenericValue         => EN_ECC_WRITE,
            Unit                 => "",
            ExpectedValueMsg     => " The Legal values for this attribute are ",
            ExpectedGenericValue => " TRUE or FALSE ",
            TailMsg              => "",
            MsgSeverity          => failure
            );
      end if;

      if (EN_ECC_SCRUB = TRUE) then
        assert false
          report "DRC Error : The attribute EN_ECC_SCRUB = TRUE is not supported on ARAMB36_INTERNAL instance."
          severity failure;
      end if;
      
      if (not(EN_ECC_SCRUB = TRUE or EN_ECC_SCRUB = FALSE)) then

        GenericValueCheckMessage
          ( HeaderMsg            => " Attribute Syntax Error : ",
            GenericName          => " EN_ECC_SCRUB ",
            EntityName           => "ARAMB36_INTERNAL",
            GenericValue         => EN_ECC_SCRUB,
            Unit                 => "",
            ExpectedValueMsg     => " The Legal values for this attribute are ",
            ExpectedGenericValue => " TRUE or FALSE ",
            TailMsg              => "",
            MsgSeverity          => failure
            );
      end if;

      
      if (EN_ECC_READ = FALSE and EN_ECC_SCRUB = TRUE) then
        assert false
        report "DRC Error : The attribute EN_ECC_SCRUB = TRUE is vaild only if the attribute EN_ECC_READ set to TRUE on ARAMB36_INTERNAL instance."
        severity failure;
      end if;

      
      if (READ_WIDTH_A = 0 and READ_WIDTH_B = 0) then
        assert false
        report "Attribute Syntax Error : Attributes READ_WIDTH_A and READ_WIDTH_B on ARAMB36_INTERNAL instance, both can not be 0."
        severity failure;
      end if;

      
      if (WRITE_MODE_A = "WRITE_FIRST") then
        wr_mode_a := "00";
      elsif (WRITE_MODE_A = "READ_FIRST") then
        wr_mode_a := "01";
      elsif (WRITE_MODE_A = "NO_CHANGE") then
        wr_mode_a := "10";
      else
        GenericValueCheckMessage
          ( HeaderMsg            => " Attribute Syntax Error : ",
            GenericName          => " WRITE_MODE_A ",
            EntityName           => "ARAMB36_INTERNAL",
            GenericValue         => WRITE_MODE_A,
            Unit                 => "",
            ExpectedValueMsg     => " The Legal values for this attribute are ",
            ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
            TailMsg              => "",
            MsgSeverity          => failure
            );
      end if;
    
      if (WRITE_MODE_B = "WRITE_FIRST") then
        wr_mode_b := "00";
      elsif (WRITE_MODE_B = "READ_FIRST") then
        wr_mode_b := "01";
      elsif (WRITE_MODE_B = "NO_CHANGE") then
        wr_mode_b := "10";
      else
        GenericValueCheckMessage
          ( HeaderMsg            => " Attribute Syntax Error : ",
            GenericName          => " WRITE_MODE_B ",
            EntityName           => "ARAMB36_INTERNAL",
            GenericValue         => WRITE_MODE_B,
            Unit                 => "",
            ExpectedValueMsg     => " The Legal values for this attribute are ",
            ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
            TailMsg              => "",
            MsgSeverity          => failure
            );
      end if;

    
      if (RAM_EXTENSION_A = "UPPER") then
        cascade_a <= "11";
      elsif (RAM_EXTENSION_A = "LOWER") then
        cascade_a <= "01";
      elsif (RAM_EXTENSION_A= "NONE") then
        cascade_a <= "00";
      else
        GenericValueCheckMessage
          ( HeaderMsg            => " Attribute Syntax Error : ",
            GenericName          => " RAM_EXTENSION_A ",
            EntityName           => "ARAMB36_INTERNAL",
            GenericValue         => RAM_EXTENSION_A,
            Unit                 => "",
            ExpectedValueMsg     => " The Legal values for this attribute are ",
            ExpectedGenericValue => " NONE, LOWER or UPPER ",
            TailMsg              => "",
            MsgSeverity          => failure
            );
      end if;

    
      if (RAM_EXTENSION_B = "UPPER") then
        cascade_b <= "11";
      elsif (RAM_EXTENSION_B = "LOWER") then
        cascade_b <= "01";
      elsif (RAM_EXTENSION_B= "NONE") then
        cascade_b <= "00";
      else
        GenericValueCheckMessage
          ( HeaderMsg            => " Attribute Syntax Error : ",
            GenericName          => " RAM_EXTENSION_B ",
            EntityName           => "ARAMB36_INTERNAL",
            GenericValue         => RAM_EXTENSION_A,
            Unit                 => "",
            ExpectedValueMsg     => " The Legal values for this attribute are ",
            ExpectedGenericValue => " NONE, LOWER or UPPER ",
            TailMsg              => "",
            MsgSeverity          => failure
            );
      end if;

      
      if( ((RAM_EXTENSION_A = "LOWER") or (RAM_EXTENSION_A = "UPPER")) and (READ_WIDTH_A /= 1)) then
        assert false
          report "Attribute Syntax Error: If RAM_EXTENSION_A is set to either LOWER or UPPER, then READ_WIDTH_A has to be set to 1."
          severity Failure;
      end if;
    
      if( ((RAM_EXTENSION_A = "LOWER") or (RAM_EXTENSION_A = "UPPER")) and (WRITE_WIDTH_A /= 1)) then
        assert false
          report "Attribute Syntax Error: If RAM_EXTENSION_A is set to either LOWER or UPPER, then WRITE_WIDTH_A has to be set to 1."
          severity Failure;
      end if;

      if( ((RAM_EXTENSION_B = "LOWER") or (RAM_EXTENSION_B = "UPPER")) and (READ_WIDTH_B /= 1)) then
        assert false
          report "Attribute Syntax Error: If RAM_EXTENSION_B is set to either LOWER or UPPER, then READ_WIDTH_B has to be set to 1."
          severity Failure;
      end if;
    
      if( ((RAM_EXTENSION_B = "LOWER") or (RAM_EXTENSION_B = "UPPER")) and (WRITE_WIDTH_B /= 1)) then
        assert false
          report "Attribute Syntax Error: If RAM_EXTENSION_B is set to either LOWER or UPPER, then WRITE_WIDTH_B has to be set to 1."
          severity Failure;
      end if;


      if (not ((SIM_COLLISION_CHECK = "NONE") or (SIM_COLLISION_CHECK = "WARNING_ONLY") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY") or (SIM_COLLISION_CHECK = "ALL"))) then
        GenericValueCheckMessage
          (HeaderMsg => "Attribute Syntax Error",
           GenericName => "SIM_COLLISION_CHECK",
           EntityName => "ARAMB36_INTERNAL",
           GenericValue => SIM_COLLISION_CHECK,
           Unit => "",
           ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY",
           ExpectedGenericValue => "",
           TailMsg => "",
           MsgSeverity => error
           );
      end if;

    end if;
    

    if (rising_edge(clka_dly)) then

      if (ena_dly = '1') then      
        prev_time := curr_time;
        curr_time := now;
        addra_reg_dly := addra_dly;
        wea_reg_dly := wea_dly;
        dia_reg_dly := dia_dly;
        dipa_reg_dly := dipa_dly;
      end if;
      
    end if;
    
    if (rising_edge(clkb_dly)) then

      if (enb_dly = '1') then
        prev_time := curr_time;
        curr_time := now;
        addrb_reg_dly := addrb_dly;
        web_reg_dly := web_dly;
        dib_reg_dly := dib_dly;
        dipb_reg_dly := dipb_dly;
      end if;
      
    end if;
    
    if (gsr_dly = '1' or FIRST_TIME) then

      doa_out(ra_width-1 downto 0) <= INIT_A_STD(ra_width-1 downto 0);

      if (ra_width >= 8) then
        dopa_out(ra_widthp-1 downto 0) <= INIT_A_STD((ra_width+ra_widthp)-1 downto ra_width);            
      end if;

      dob_out(rb_width-1 downto 0) <= INIT_B_STD(rb_width-1 downto 0);          

      if (rb_width >= 8) then
        dopb_out(rb_widthp-1 downto 0) <= INIT_B_STD((rb_width+rb_widthp)-1 downto rb_width);            
      end if;

      dbiterr_out <= '0';
      sbiterr_out <= '0';

      FIRST_TIME := false;
      
    elsif (gsr_dly = '0') then

      if (rising_edge(clka_dly)) then
       if (cascade_a(1) = '1') then
         addra_dly_15_reg_bram_var := not addra_dly(15);
       else
         addra_dly_15_reg_bram_var := addra_dly(15);
       end if;
      end if;

      if (rising_edge(clkb_dly)) then
       if (cascade_b(1) = '1') then
         addrb_dly_15_reg_bram_var := not addrb_dly(15);
       else
         addrb_dly_15_reg_bram_var := addrb_dly(15);
       end if;
      end if;
      
     if (rising_edge(clka_dly) or rising_edge(clkb_dly)) then

      if ((cascade_a = "00" or (addra_dly_15_reg_bram_var = '0' and cascade_a /= "00")) or (cascade_b = "00" or (addrb_dly_15_reg_bram_var = '0' and cascade_b /= "00"))) then
            
-------------------------------------------------------------------------------
-- Collision starts
-------------------------------------------------------------------------------

       if (SIM_COLLISION_CHECK /= "NONE") then

        
        if (curr_time - prev_time = 0 ps) then
          viol_time := 1;
        elsif (curr_time - prev_time <= SETUP_READ_FIRST) then
          viol_time := 2;
        end if;

        
        if (ena_dly = '0' or enb_dly = '0') then
          viol_time := 0;
        end if;

        
        if ((WRITE_WIDTH_A <= 9 and wea_dly(0) = '0') or (WRITE_WIDTH_A = 18 and wea_dly(1 downto 0) = "00") or ((WRITE_WIDTH_A = 36 or WRITE_WIDTH_A = 72) and wea_dly(3 downto 0) = "0000")) then
          if ((WRITE_WIDTH_B <= 9 and web_dly(0) = '0') or (WRITE_WIDTH_B = 18 and web_dly(1 downto 0) = "00") or (WRITE_WIDTH_B = 36 and web_dly(3 downto 0) = "0000") or (WRITE_WIDTH_B = 72 and web_dly(7 downto 0) = "00000000")) then
            viol_time := 0;
          end if;
        end if;

        
        if (viol_time /= 0) then
--lool
          if (cascade_a(0) = '1' or cascade_b(0) = '1') then
            if (addra_dly(15 downto col_addr_lsb) = addrb_dly(15 downto col_addr_lsb)) then
              addr_col := '1';
            else
              addr_col := '0';
            end if;
          else
            if (addra_dly(14 downto col_addr_lsb) = addrb_dly(14 downto col_addr_lsb)) then
              addr_col := '1';
            else
              addr_col := '0';
            end if;
          end if;
          
          
          if (rising_edge(clka_dly) and rising_edge(clkb_dly)) then
--            if (addra_dly(15 downto col_addr_lsb) = addrb_dly(15 downto col_addr_lsb)) then
            if (addr_col = '1') then
              
              viol_type := "01";

              prcd_rd_ram_a (addra_dly, doa_buf, dopa_buf, mem, memp);
              prcd_rd_ram_b (addrb_dly, dob_buf, dopb_buf, mem, memp);
              
              prcd_col_wr_ram_a ("00", web_dly, wea_dly, di_x, di_x(7 downto 0), addrb_dly, addra_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
              prcd_col_wr_ram_b ("00", wea_dly, web_dly, di_x, di_x(7 downto 0), addra_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);

              prcd_col_rd_ram_a (viol_type, "01", web_dly, wea_dly, addra_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a);
              prcd_col_rd_ram_b (viol_type, "01", wea_dly, web_dly, addrb_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b);

              prcd_col_wr_ram_a ("10", web_dly, wea_dly, dia_dly, dipa_dly, addrb_dly, addra_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);

              if (BRAM_MODE = "ECC" and EN_ECC_WRITE = TRUE and enb_dly = '1') then
                  
                dip_ecc_col := fn_dip_ecc('1', dib_dly, dipb_dly);				
                eccparity_out <= dip_ecc_col;
                prcd_col_wr_ram_b ("10", wea_dly, web_dly, dib_dly, dip_ecc_col, addra_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);

              else
                
                prcd_col_wr_ram_b ("10", wea_dly, web_dly, dib_dly, dipb_dly, addra_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);

              end if;
			    
              if (wr_mode_a /= "01") then
                prcd_col_rd_ram_a (viol_type, "11", web_dly, wea_dly, addra_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a);
              end if;

              if (wr_mode_b /= "01") then
                prcd_col_rd_ram_b (viol_type, "11", wea_dly, web_dly, addrb_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b);
              end if;

              if (BRAM_MODE = "ECC" and EN_ECC_READ = TRUE) then
                prcd_col_ecc_read (doa_buf, dopa_buf, addra_dly, dbiterr_out_var, sbiterr_out_var, mem, memp, syndrome);
              end if;
              
            else
              viol_time := 0;
              
            end if;

          elsif (rising_edge(clka_dly) and  (not(rising_edge(clkb_dly)))) then
--            if (addra_dly(15 downto col_addr_lsb) = addrb_dly(15 downto col_addr_lsb)) then
            if (addr_col = '1') then
              
              viol_type := "10";

              prcd_rd_ram_a (addra_dly, doa_buf, dopa_buf, mem, memp);

              prcd_col_wr_ram_a ("00", web_reg_dly, wea_dly, di_x, di_x(7 downto 0), addrb_reg_dly, addra_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
              prcd_col_wr_ram_b ("00", wea_dly, web_reg_dly, di_x, di_x(7 downto 0), addra_dly, addrb_reg_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);

              prcd_col_rd_ram_a (viol_type, "01", web_reg_dly, wea_dly, addra_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a);
              prcd_col_rd_ram_b (viol_type, "01", wea_dly, web_reg_dly, addrb_reg_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b);

              prcd_col_wr_ram_a ("10", web_reg_dly, wea_dly, dia_dly, dipa_dly, addrb_reg_dly, addra_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);

              if (BRAM_MODE = "ECC" and EN_ECC_WRITE = TRUE and enb_dly = '1') then
                  
                dip_ecc_col := fn_dip_ecc('1', dib_reg_dly, dipb_reg_dly);				
                eccparity_out <= dip_ecc_col;
                prcd_col_wr_ram_b ("10", wea_dly, web_reg_dly, dib_reg_dly, dip_ecc_col, addra_dly, addrb_reg_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);

              else
                
                prcd_col_wr_ram_b ("10", wea_dly, web_reg_dly, dib_reg_dly, dipb_reg_dly, addra_dly, addrb_reg_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);

              end if;
			    
              if (wr_mode_a /= "01") then
                prcd_col_rd_ram_a (viol_type, "11", web_reg_dly, wea_dly, addra_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a);
              end if;

              if (wr_mode_b /= "01") then
                prcd_col_rd_ram_b (viol_type, "11", wea_dly, web_reg_dly, addrb_reg_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b);
              end if;

              if (BRAM_MODE = "ECC" and EN_ECC_READ = TRUE) then
                prcd_col_ecc_read (doa_buf, dopa_buf, addra_dly, dbiterr_out_var, sbiterr_out_var, mem, memp, syndrome);
              end if;
              
            else
              viol_time := 0;
              
            end if;

          elsif ((not(rising_edge(clka_dly))) and rising_edge(clkb_dly)) then
--            if (addra_dly(15 downto col_addr_lsb) = addrb_dly(15 downto col_addr_lsb)) then
            if (addr_col = '1') then
                              
              viol_type := "11";

              prcd_rd_ram_b (addrb_dly, dob_buf, dopb_buf, mem, memp);

              prcd_col_wr_ram_a ("00", web_dly, wea_reg_dly, di_x, di_x(7 downto 0), addrb_dly, addra_reg_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);
              prcd_col_wr_ram_b ("00", wea_reg_dly, web_dly, di_x, di_x(7 downto 0), addra_reg_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);

              prcd_col_rd_ram_a (viol_type, "01", web_dly, wea_reg_dly, addra_reg_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a);
              prcd_col_rd_ram_b (viol_type, "01", wea_reg_dly, web_dly, addrb_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b);

              prcd_col_wr_ram_a ("10", web_dly, wea_reg_dly, dia_reg_dly, dipa_reg_dly, addrb_dly, addra_reg_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);

              if (BRAM_MODE = "ECC" and EN_ECC_WRITE = TRUE and enb_dly = '1') then
                  
                dip_ecc_col := fn_dip_ecc('1', dib_dly, dipb_dly);				
                eccparity_out <= dip_ecc_col;
                prcd_col_wr_ram_b ("10", wea_reg_dly, web_dly, dib_dly, dip_ecc_col, addra_reg_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);

              else
                
                prcd_col_wr_ram_b ("10", wea_reg_dly, web_dly, dib_dly, dipb_dly, addra_reg_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg);

              end if;
			    
              if (wr_mode_a /= "01") then
                prcd_col_rd_ram_a (viol_type, "11", web_dly, wea_reg_dly, addra_reg_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a);
              end if;

              if (wr_mode_b /= "01") then
                prcd_col_rd_ram_b (viol_type, "11", wea_reg_dly, web_dly, addrb_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b);
              end if;

              if (BRAM_MODE = "ECC" and EN_ECC_READ = TRUE) then
                prcd_col_ecc_read (doa_buf, dopa_buf, addra_reg_dly, dbiterr_out_var, sbiterr_out_var, mem, memp, syndrome);
              end if;
              
            else
              viol_time := 0;
              
            end if;
          end if;

          if (SIM_COLLISION_CHECK = "WARNING_ONLY") then
            viol_time := 0;
          end if;
          
        end if;
      end if;
-------------------------------------------------------------------------------
-- end collision
-------------------------------------------------------------------------------

    end if;
       
-------------------------------------------------------------------------------
-- Port A
-------------------------------------------------------------------------------        
    if (rising_edge(clka_dly)) then

      if (ssra_dly = '1' and BRAM_MODE = "ECC") then
        assert false
        report "DRC Warning : SET/RESET (SSR) is not supported in ECC mode."
        severity Warning;
      end if;

      if (ssra_dly = '1' and BRAM_SIZE = 16 and DOA_REG = 1) then
        assert false
        report "DRC Error : SET/RESET (SSR) is not supported when optional output registers are used."
        severity Failure;
      end if;
      
      -- registering addra_dly(15) the second time
      if (regcea_dly = '1') then
        addra_dly_15_reg1 <= addra_dly_15_reg_var;        
      end if;


      -- registering addra[15)
      if (ena_dly = '1' and (wr_mode_a /= "10" or wea_dly(0) = '0' or ssra_dly = '1')) then
        if (cascade_a(1) = '1') then
          addra_dly_15_reg_var :=  not addra_dly(15);
        else
          addra_dly_15_reg_var := addra_dly(15);
        end if;
      end if;

      
      addra_dly_15_reg <= addra_dly_15_reg_var;

      
      if (gsr_dly = '0' and ena_dly = '1' and (cascade_a = "00" or (addra_dly_15_reg_bram_var = '0' and cascade_a /= "00"))) then

        if (ssra_dly = '1' and DOA_REG = 0) then

          doa_buf(ra_width-1 downto 0) := SRVAL_A_STD(ra_width-1 downto 0);
          doa_out(ra_width-1 downto 0) <= SRVAL_A_STD(ra_width-1 downto 0);          

          if (ra_width >= 8) then
            dopa_buf(ra_widthp-1 downto 0) := SRVAL_A_STD((ra_width+ra_widthp)-1 downto ra_width);
            dopa_out(ra_widthp-1 downto 0) <= SRVAL_A_STD((ra_width+ra_widthp)-1 downto ra_width);            
          end if;

        end if;
      
        if (viol_time = 0) then
          -- read for rf
          if ((wr_mode_a = "01" and (ssra_dly = '0' or DOA_REG = 1)) or (BRAM_MODE = "ECC" and EN_ECC_READ = TRUE)) then
            prcd_rd_ram_a (addra_dly, doa_buf, dopa_buf, mem, memp);

          -- ECC decode  -- only port A
            if (BRAM_MODE = "ECC" and EN_ECC_READ = TRUE) then

              dopr_ecc := fn_dip_ecc('0', doa_buf, dopa_buf);

              syndrome := dopr_ecc xor dopa_buf;

              if (syndrome /= "00000000") then

                if (syndrome(7) = '1') then  -- dectect single bit error

                  ecc_bit_position := doa_buf(63 downto 57) & dopa_buf(6) & doa_buf(56 downto 26) & dopa_buf(5) & doa_buf(25 downto 11) & dopa_buf(4) & doa_buf(10 downto 4) & dopa_buf(3) & doa_buf(3 downto 1) & dopa_buf(2) & doa_buf(0) & dopa_buf(1 downto 0) & dopa_buf(7);

                  tmp_syndrome_int := SLV_TO_INT(syndrome(6 downto 0));
                  ecc_bit_position(tmp_syndrome_int) := not ecc_bit_position(tmp_syndrome_int); -- correct single bit error in the output 

                  dia_dly_ecc_corrected := ecc_bit_position(71 downto 65) & ecc_bit_position(63 downto 33) & ecc_bit_position(31 downto 17) & ecc_bit_position(15 downto 9) & ecc_bit_position(7 downto 5) & ecc_bit_position(3); -- correct single bit error in the memory

                  doa_buf := dia_dly_ecc_corrected;
			
                  dipa_dly_ecc_corrected := ecc_bit_position(0) & ecc_bit_position(64) & ecc_bit_position(32) & ecc_bit_position(16) & ecc_bit_position(8) & ecc_bit_position(4) & ecc_bit_position(2 downto 1); -- correct single bit error in the parity memory
                
                  dopa_buf := dipa_dly_ecc_corrected;
                
                  dbiterr_out_var := '0';
                  sbiterr_out_var := '1';

                elsif (syndrome(7) = '0') then  -- double bit error
                  sbiterr_out_var := '0';
                  dbiterr_out_var := '1';
                end if;
              else
                dbiterr_out_var := '0';
                sbiterr_out_var := '0';
              end if;

              if (ssra_dly = '1') then  -- ssra reset 
                dbiterr_out_var := '0';
                sbiterr_out_var := '0';    
              end if;

            end if;
          end if;

        

        if (syndrome /= "00000000" and syndrome(7) = '1' and EN_ECC_SCRUB = TRUE) then
          prcd_wr_ram_a ("11111111", dia_dly_ecc_corrected, dipa_dly_ecc_corrected, addra_dly, mem, memp, syndrome);
        else
          prcd_wr_ram_a (wea_dly, dia_dly, dipa_dly, addra_dly, mem, memp, syndrome);    
        end if;


        if ((wr_mode_a /= "01" and (ssra_dly = '0' or DOA_REG = 1)) and (not(BRAM_MODE = "ECC" and EN_ECC_READ = TRUE))) then
          prcd_rd_ram_a (addra_dly, doa_buf, dopa_buf, mem, memp);
        end if;

        
        end if;
      end if;
    end if;
    
-------------------------------------------------------------------------------
-- Port B
-------------------------------------------------------------------------------

    if (rising_edge(clkb_dly)) then

      -- DRC
      if (ssrb_dly = '1' and BRAM_MODE = "ECC") then
        assert false
        report "DRC Warning : SET/RESET (SSR) is not supported in ECC mode."
        severity Warning;
      end if;

      if (ssrb_dly = '1' and BRAM_SIZE = 16 and DOB_REG = 1) then
        assert false
        report "DRC Error : SET/RESET (SSR) is not supported when optional output registers are used."
        severity Failure;
      end if;

      
      -- registering addrb_dly(15) the second time
      if (regceb_dly = '1') then
        addrb_dly_15_reg1 <= addrb_dly_15_reg_var;        
      end if;


      -- registering addrb(15)
      if (enb_dly = '1' and (wr_mode_b /= "10" or web_dly(0) = '0' or ssrb_dly = '1')) then
        if (cascade_b(1) = '1') then
          addrb_dly_15_reg_var :=  not addrb_dly(15);
        else
          addrb_dly_15_reg_var := addrb_dly(15);
        end if;
      end if;

      
      addrb_dly_15_reg <= addrb_dly_15_reg_var;

      if (gsr_dly = '0' and enb_dly = '1' and (cascade_b = "00" or (addrb_dly_15_reg_bram_var = '0' and cascade_b /= "00"))) then

        if (ssrb_dly = '1' and DOB_REG = 0) then

          dob_buf(rb_width-1 downto 0) := SRVAL_B_STD(rb_width-1 downto 0);
          dob_out(rb_width-1 downto 0) <= SRVAL_B_STD(rb_width-1 downto 0);          

          if (rb_width >= 8) then
            dopb_buf(rb_widthp-1 downto 0) := SRVAL_B_STD((rb_width+rb_widthp)-1 downto rb_width);
            dopb_out(rb_widthp-1 downto 0) <= SRVAL_B_STD((rb_width+rb_widthp)-1 downto rb_width);            
          end if;

        end if;

        dip_ecc := fn_dip_ecc('1', dib_dly, dipb_dly);

        eccparity_out <= dip_ecc;
        
        if (BRAM_MODE = "ECC" and EN_ECC_WRITE = TRUE) then
            dipb_dly_ecc := dip_ecc;
        else
          dipb_dly_ecc := dipb_dly;
        end if;


        if (viol_time = 0) then
          
          if (wr_mode_b = "01" and (ssrb_dly = '0' or DOB_REG = 1)) then
            prcd_rd_ram_b (addrb_dly, dob_buf, dopb_buf, mem, memp);            
          end if;
          
          if (BRAM_MODE = "ECC" and EN_ECC_WRITE = TRUE) then
            prcd_wr_ram_b (web_dly, dib_dly, dipb_dly_ecc, addrb_dly, mem, memp);
          else
            prcd_wr_ram_b (web_dly, dib_dly, dipb_dly, addrb_dly, mem, memp);
          end if;
            

          if (wr_mode_b /= "01" and (ssrb_dly = '0' or DOB_REG = 1)) then
            prcd_rd_ram_b (addrb_dly, dob_buf, dopb_buf, mem, memp);
          end if;
          
        end if;
      end if;
    end if;
    

    if (ena_dly = '1' and (rising_edge(clka_dly) or viol_time /= 0)) then
      if ((ssra_dly = '0' or DOA_REG = 1) and (wr_mode_a /= "10" or (WRITE_WIDTH_A <= 9 and wea_dly(0) = '0') or (WRITE_WIDTH_A = 18 and wea_dly(1 downto 0) = "00") or ((WRITE_WIDTH_A = 36 or WRITE_WIDTH_A = 72) and wea_dly(3 downto 0) = "0000"))) then

        -- Virtex4 feature
        if (wr_mode_a = "00" and BRAM_SIZE = 16) then
          
          if ((WRITE_WIDTH_A = 18 and not(wea_dly(1 downto 0) = "00" or wea_dly(1 downto 0) = "11")) or (WRITE_WIDTH_A = 36 and not(wea_dly(3 downto 0) = "0000" or wea_dly(3 downto 0) = "1111"))) then
			
            if (WRITE_WIDTH_A /= READ_WIDTH_A) then
              
              doa_buf(ra_width-1 downto 0) := di_x(ra_width-1 downto 0);
			    
              if (READ_WIDTH_A >= 9) then
                dopa_buf(ra_widthp-1 downto 0) := di_x(ra_widthp-1 downto 0);
			    
              end if;

              if (READ_WIDTH_A /= 0) then
                
                Write ( Message, STRING'(" Functional warning at simulation time "));
                Write ( Message, STRING'("( "));
                Write ( Message, now);
                Write ( Message, STRING'(") : "));
                Write ( Message, STRING'("ARAMB36_INTERNAL "));    
                Write ( Message, STRING'("( "));
                Write ( Message, STRING'(ARAMB36_INTERNAL'path_name));
                Write ( Message, STRING'(") "));
                Write ( Message, STRING'(" port A is in WRITE_FIRST mode with parameter WRITE_WIDTH_A = "));
                Write ( Message, INTEGER'(WRITE_WIDTH_A));
                Write ( Message, STRING'(", which is different from READ_WIDTH_A = "));
                Write ( Message, INTEGER'(READ_WIDTH_A));
                Write ( Message, STRING'(". The write will be successful however the read value of all bits on port A"));
                Write ( Message, STRING'(" is unknown until the next CLKA cycle and all bits of WEA is set to all 1s or 0s. "));
                Write ( Message, LF );            
                ASSERT FALSE REPORT Message.ALL SEVERITY warning;
                DEALLOCATE (Message);

              end if;
              
            elsif (WRITE_WIDTH_A = 18) then

              for i in 0 to 1 loop
                
                if (wea_dly(i) = '0') then
                  doa_buf(((8*(i+1))-1) downto 8*i) := di_x(((8*(i+1))-1) downto 8*i);
                  dopa_buf(i downto i) := di_x(i downto i);
                end if;
                            
              end loop;

              if (READ_WIDTH_A /= 0) then

                Write ( Message, STRING'(" Functional warning at simulation time "));
                Write ( Message, STRING'("( "));
                Write ( Message, now);
                Write ( Message, STRING'(") : "));
                Write ( Message, STRING'("ARAMB36_INTERNAL "));    
                Write ( Message, STRING'("( "));
                Write ( Message, STRING'(ARAMB36_INTERNAL'path_name));
                Write ( Message, STRING'(") "));
                Write ( Message, STRING'(" port A is in WRITE_FIRST mode. The write will be successful,"));
                Write ( Message, STRING'(" however DOA shows only the enabled newly written byte(s)."));
                Write ( Message, STRING'(" The other byte values on DOA are unknown until the next CLKA cycle and"));
                Write ( Message, STRING'(" all bits of WEA is set to all 1s or 0s. "));
                Write ( Message, LF );            
                ASSERT FALSE REPORT Message.ALL SEVERITY warning;
                DEALLOCATE (Message);

              end if;
              
            elsif (WRITE_WIDTH_A = 36) then

              for i in 0 to 3 loop

                if (wea_dly(i) = '0') then
                  doa_buf(((8*(i+1))-1) downto 8*i) := di_x(((8*(i+1))-1) downto 8*i);
                  dopa_buf(i downto i) := di_x(i downto i);
                end if;
                            
              end loop;

              if (READ_WIDTH_A /= 0) then

                Write ( Message, STRING'(" Functional warning at simulation time "));
                Write ( Message, STRING'("( "));
                Write ( Message, now);
                Write ( Message, STRING'(") : "));
                Write ( Message, STRING'("ARAMB36_INTERNAL "));    
                Write ( Message, STRING'("( "));
                Write ( Message, STRING'(ARAMB36_INTERNAL'path_name));
                Write ( Message, STRING'(") "));
                Write ( Message, STRING'(" port A is in WRITE_FIRST mode. The write will be successful,"));
                Write ( Message, STRING'(" however DOA shows only the enabled newly written byte(s)."));
                Write ( Message, STRING'(" The other byte values on DOA are unknown until the next CLKA cycle and"));
                Write ( Message, STRING'(" all bits of WEA is set to all 1s or 0s. "));
                Write ( Message, LF );            
                ASSERT FALSE REPORT Message.ALL SEVERITY warning;
                DEALLOCATE (Message);

              end if;
              
            end if;
            
          end if;
        end if;

        doa_out <= doa_buf;
        dopa_out <= dopa_buf;
      end if;
    end if;

    if (enb_dly = '1' and (rising_edge(clkb_dly) or viol_time /= 0)) then
      if ((ssrb_dly = '0' or DOB_REG = 1) and (wr_mode_b /= "10" or (WRITE_WIDTH_B <= 9 and web_dly(0) = '0') or (WRITE_WIDTH_B = 18 and web_dly(1 downto 0) = "00") or (WRITE_WIDTH_B = 36 and web_dly(3 downto 0) = "0000") or (WRITE_WIDTH_B = 72 and web_dly(7 downto 0) = "00000000"))) then

        -- Virtex4 feature
        if (wr_mode_b = "00" and BRAM_SIZE = 16) then
          
          if ((WRITE_WIDTH_B = 18 and not(web_dly(1 downto 0) = "00" or web_dly(1 downto 0) = "11")) or (WRITE_WIDTH_B = 36 and not(web_dly(3 downto 0) = "0000" or web_dly(3 downto 0) = "1111"))) then
			
            if (WRITE_WIDTH_B /= READ_WIDTH_B) then
              
              dob_buf(rb_width-1 downto 0) := di_x(rb_width-1 downto 0);
			    
              if (READ_WIDTH_B >= 9) then
                dopb_buf(rb_widthp-1 downto 0) := di_x(rb_widthp-1 downto 0);
			    
              end if;

              if (READ_WIDTH_B /= 0) then

                Write ( Message, STRING'(" Functional warning at simulation time "));
                Write ( Message, STRING'("( "));
                Write ( Message, now);
                Write ( Message, STRING'(") : "));
                Write ( Message, STRING'("ARAMB36_INTERNAL "));    
                Write ( Message, STRING'("( "));
                Write ( Message, STRING'(ARAMB36_INTERNAL'path_name));
                Write ( Message, STRING'(") "));
                Write ( Message, STRING'(" port B is in WRITE_FIRST mode with parameter WRITE_WIDTH_B = "));
                Write ( Message, INTEGER'(WRITE_WIDTH_B));
                Write ( Message, STRING'(", which is different from READ_WIDTH_B = "));
                Write ( Message, INTEGER'(READ_WIDTH_B));
                Write ( Message, STRING'(". The write will be successful however the read value of all bits on port B"));
                Write ( Message, STRING'(" is unknown until the next CLKB cycle and all bits of WEB is set to all 1s or 0s. "));
                Write ( Message, LF );            
                ASSERT FALSE REPORT Message.ALL SEVERITY warning;
                DEALLOCATE (Message);

              end if;
              
            elsif (WRITE_WIDTH_B = 18) then

              for i in 0 to 1 loop
                
                if (web_dly(i) = '0') then
                  dob_buf(((8*(i+1))-1) downto 8*i) := di_x(((8*(i+1))-1) downto 8*i);
                  dopb_buf(i downto i) := di_x(i downto i);
                end if;
                            
              end loop;

              if (READ_WIDTH_B /= 0) then

                Write ( Message, STRING'(" Functional warning at simulation time "));
                Write ( Message, STRING'("( "));
                Write ( Message, now);
                Write ( Message, STRING'(") : "));
                Write ( Message, STRING'("ARAMB36_INTERNAL "));    
                Write ( Message, STRING'("( "));
                Write ( Message, STRING'(ARAMB36_INTERNAL'path_name));
                Write ( Message, STRING'(") "));
                Write ( Message, STRING'(" port B is in WRITE_FIRST mode. The write will be successful,"));
                Write ( Message, STRING'(" however DOB shows only the enabled newly written byte(s)."));
                Write ( Message, STRING'(" The other byte values on DOB are unknown until the next CLKB cycle and"));
                Write ( Message, STRING'(" all bits of WEB is set to all 1s or 0s. "));
                Write ( Message, LF );            
                ASSERT FALSE REPORT Message.ALL SEVERITY warning;
                DEALLOCATE (Message);

              end if;
              
            elsif (WRITE_WIDTH_B = 36) then

              for i in 0 to 3 loop

                if (web_dly(i) = '0') then
                  dob_buf(((8*(i+1))-1) downto 8*i) := di_x(((8*(i+1))-1) downto 8*i);
                  dopb_buf(i downto i) := di_x(i downto i);
                end if;
                            
              end loop;

              if (READ_WIDTH_B /= 0) then

                Write ( Message, STRING'(" Functional warning at simulation time "));
                Write ( Message, STRING'("( "));
                Write ( Message, now);
                Write ( Message, STRING'(") : "));
                Write ( Message, STRING'("ARAMB36_INTERNAL "));    
                Write ( Message, STRING'("( "));
                Write ( Message, STRING'(ARAMB36_INTERNAL'path_name));
                Write ( Message, STRING'(") "));
                Write ( Message, STRING'(" port B is in WRITE_FIRST mode. The write will be successful,"));
                Write ( Message, STRING'(" however DOB shows only the enabled newly written byte(s)."));
                Write ( Message, STRING'(" The other byte values on DOB are unknown until the next CLKB cycle and"));
                Write ( Message, STRING'(" all bits of WEB is set to all 1s or 0s. "));
                Write ( Message, LF );            
                ASSERT FALSE REPORT Message.ALL SEVERITY warning;
                DEALLOCATE (Message);

              end if;
              
            end if;

          end if;
        end if;
        
        dob_out <= dob_buf;
        dopb_out <= dopb_buf;
      end if;
    end if;

    viol_time := 0;
    viol_type := "00";
    col_wr_wr_msg := '1';
    col_wra_rdb_msg := '1';
    col_wrb_rda_msg := '1';
    dbiterr_out <= dbiterr_out_var;
    sbiterr_out <= sbiterr_out_var;

   end if;
  end if;

  end process prcs_clk;


  outreg_clka: process (regclka_dly, gsr_dly)
    variable FIRST_TIME : boolean := true;
    
  begin  -- process outreg_clka

    if (rising_edge(regclka_dly) or rising_edge(gsr_dly) or FIRST_TIME) then

      if (DOA_REG = 1) then
        
        if (gsr_dly = '1' or FIRST_TIME) then

          dbiterr_outreg <= '0';
          sbiterr_outreg <= '0';
          
          doa_outreg(ra_width-1 downto 0) <= INIT_A_STD(ra_width-1 downto 0);

          if (ra_width >= 8) then
            dopa_outreg(ra_widthp-1 downto 0) <= INIT_A_STD((ra_width+ra_widthp)-1 downto ra_width);
          end if;

          FIRST_TIME := false;
          
        elsif (gsr_dly = '0') then
          
          dbiterr_outreg <= dbiterr_out;
          sbiterr_outreg <= sbiterr_out;

          if (regcea_dly = '1') then
            if (ssra_dly = '1') then

              doa_outreg(ra_width-1 downto 0) <= SRVAL_A_STD(ra_width-1 downto 0);

              if (ra_width >= 8) then
                dopa_outreg(ra_widthp-1 downto 0) <= SRVAL_A_STD((ra_width+ra_widthp)-1 downto ra_width);
              end if;

            elsif (ssra_dly = '0') then

              doa_outreg <= doa_out;
              dopa_outreg <= dopa_out;

            end if;     
          end if;
        end if;
      end if;

    end if;
  end process outreg_clka;
  

  cascade_a_mux: process (clka_dly, cascadeinlata_dly, addra_dly_15_reg, doa_out, dopa_out)
  begin  -- process cascade_a_mux
    
    if (rising_edge(clka_dly) or cascadeinlata_dly'event or addra_dly_15_reg'event or doa_out'event or dopa_out'event) then
      if (cascade_a(1) = '1' and addra_dly_15_reg = '1') then 
        doa_out_mux(0) <= cascadeinlata_dly;
      else
        doa_out_mux <= doa_out;
        dopa_out_mux <= dopa_out;
      end if;
    end if;

  end process cascade_a_mux;
  
  cascade_a_muxreg: process (regclka_dly, cascadeinrega_dly, addra_dly_15_reg1, doa_outreg, dopa_outreg)
  begin  -- process cascade_a_muxreg
    
    if (rising_edge(regclka_dly) or cascadeinrega_dly'event or addra_dly_15_reg1'event or doa_outreg'event or dopa_outreg'event) then
      if (cascade_a(1) = '1' and addra_dly_15_reg1 = '1') then 
        doa_outreg_mux(0) <= cascadeinrega_dly;
      else
        doa_outreg_mux <= doa_outreg;
        dopa_outreg_mux <= dopa_outreg;
      end if;
    end if;

  end process cascade_a_muxreg;
  

  outmux_clka: process (doa_out_mux, dopa_out_mux, doa_outreg_mux, dopa_outreg_mux, dbiterr_out, dbiterr_outreg, sbiterr_out, sbiterr_outreg)
  begin  -- process outmux_clka

      case DOA_REG is
        when 0 =>
                  dbiterr_out_out <= dbiterr_out;
                  sbiterr_out_out <= sbiterr_out;
                  doa_out_out <= doa_out_mux;
                  dopa_out_out <= dopa_out_mux;
        when 1 =>
                  dbiterr_out_out <= dbiterr_outreg;
                  sbiterr_out_out <= sbiterr_outreg;
                  doa_out_out <= doa_outreg_mux;
                  dopa_out_out <= dopa_outreg_mux;
        when others => assert false
                       report "Attribute Syntax Error: The allowed integer values for DOA_REG are 0 or 1."
                       severity Failure;
      end case;

  end process outmux_clka;
  

  outreg_clkb: process (regclkb_dly, gsr_dly)
    variable FIRST_TIME : boolean := true;

  begin  -- process outreg_clkb

    if (rising_edge(regclkb_dly) or rising_edge(gsr_dly) or FIRST_TIME) then

      if (DOB_REG = 1) then
        
        if (gsr_dly = '1' or FIRST_TIME) then
          dob_outreg(rb_width-1 downto 0) <= INIT_B_STD(rb_width-1 downto 0);

          if (rb_width >= 8) then
            dopb_outreg(rb_widthp-1 downto 0) <= INIT_B_STD((rb_width+rb_widthp)-1 downto rb_width);
          end if;

          FIRST_TIME := false;
          
        elsif (gsr_dly = '0') then

          if (regceb_dly = '1') then
            if (ssrb_dly = '1') then

              dob_outreg(rb_width-1 downto 0) <= SRVAL_B_STD(rb_width-1 downto 0);

              if (rb_width >= 8) then
                dopb_outreg(rb_widthp-1 downto 0) <= SRVAL_B_STD((rb_width+rb_widthp)-1 downto rb_width);
              end if;

            elsif (ssrb_dly = '0') then

              dob_outreg <= dob_out;
              dopb_outreg <= dopb_out;

            end if;     
          end if;
        end if;
      end if;
      
    end if;
  end process outreg_clkb;

  
  cascade_b_mux: process (clkb_dly, cascadeinlatb_dly, addrb_dly_15_reg, dob_out, dopb_out)
  begin  -- process cascade_b_mux
    
    if (rising_edge(clkb_dly) or cascadeinlatb_dly'event or addrb_dly_15_reg'event or dob_out'event or dopb_out'event) then
      if (cascade_b(1) = '1' and addrb_dly_15_reg = '1') then 
        dob_out_mux(0) <= cascadeinlatb_dly;
      else
        dob_out_mux <= dob_out;
        dopb_out_mux <= dopb_out;
      end if;
    end if;

  end process cascade_b_mux;
  
  cascade_b_muxreg: process (regclkb_dly, cascadeinregb_dly, addrb_dly_15_reg1, dob_outreg, dopb_outreg)
  begin  -- process cascade_b_muxreg
    
    if (rising_edge(regclkb_dly) or cascadeinregb_dly'event or addrb_dly_15_reg1'event or dob_outreg'event or dopb_outreg'event) then
      if (cascade_b(1) = '1' and addrb_dly_15_reg1 = '1') then 
        dob_outreg_mux(0) <= cascadeinregb_dly;
      else
        dob_outreg_mux <= dob_outreg;
        dopb_outreg_mux <= dopb_outreg;
      end if;
    end if;

  end process cascade_b_muxreg;

  
  outmux_clkb: process (dob_out_mux, dopb_out_mux, dob_outreg_mux, dopb_outreg_mux)
  begin  -- process outmux_clkb

      case DOB_REG is
        when 0 =>
                  dob_out_out <= dob_out_mux;
                  dopb_out_out <= dopb_out_mux;
        when 1 =>
                  dob_out_out <= dob_outreg_mux;
                  dopb_out_out <= dopb_outreg_mux;
        when others => assert false
                       report "Attribute Syntax Error: The allowed integer values for DOB_REG are 0 or 1."
                       severity Failure;
      end case;

  end process outmux_clkb;


  end generate;

-------------------------------------------------------------------------------
-- FAST mode
-------------------------------------------------------------------------------

  fast_mode : if (SIM_MODE = "FAST") generate


    prcs_clk: process (clka_dly, clkb_dly, gsr_dly)

      variable mem_slv : std_logic_vector(32767 downto 0) := To_StdLogicVector(INIT_7F) &
                                                       To_StdLogicVector(INIT_7E) &
                                                       To_StdLogicVector(INIT_7D) &
                                                       To_StdLogicVector(INIT_7C) &
                                                       To_StdLogicVector(INIT_7B) &
                                                       To_StdLogicVector(INIT_7A) &
                                                       To_StdLogicVector(INIT_79) &
                                                       To_StdLogicVector(INIT_78) &
                                                       To_StdLogicVector(INIT_77) &
                                                       To_StdLogicVector(INIT_76) &
                                                       To_StdLogicVector(INIT_75) &
                                                       To_StdLogicVector(INIT_74) &
                                                       To_StdLogicVector(INIT_73) &
                                                       To_StdLogicVector(INIT_72) &
                                                       To_StdLogicVector(INIT_71) &
                                                       To_StdLogicVector(INIT_70) &
                                                       To_StdLogicVector(INIT_6F) &
                                                       To_StdLogicVector(INIT_6E) &
                                                       To_StdLogicVector(INIT_6D) &
                                                       To_StdLogicVector(INIT_6C) &
                                                       To_StdLogicVector(INIT_6B) &
                                                       To_StdLogicVector(INIT_6A) &
                                                       To_StdLogicVector(INIT_69) &
                                                       To_StdLogicVector(INIT_68) &
                                                       To_StdLogicVector(INIT_67) &
                                                       To_StdLogicVector(INIT_66) &
                                                       To_StdLogicVector(INIT_65) &
                                                       To_StdLogicVector(INIT_64) &
                                                       To_StdLogicVector(INIT_63) &
                                                       To_StdLogicVector(INIT_62) &
                                                       To_StdLogicVector(INIT_61) &
                                                       To_StdLogicVector(INIT_60) &
                                                       To_StdLogicVector(INIT_5F) &
                                                       To_StdLogicVector(INIT_5E) &
                                                       To_StdLogicVector(INIT_5D) &
                                                       To_StdLogicVector(INIT_5C) &
                                                       To_StdLogicVector(INIT_5B) &
                                                       To_StdLogicVector(INIT_5A) &
                                                       To_StdLogicVector(INIT_59) &
                                                       To_StdLogicVector(INIT_58) &
                                                       To_StdLogicVector(INIT_57) &
                                                       To_StdLogicVector(INIT_56) &
                                                       To_StdLogicVector(INIT_55) &
                                                       To_StdLogicVector(INIT_54) &
                                                       To_StdLogicVector(INIT_53) &
                                                       To_StdLogicVector(INIT_52) &
                                                       To_StdLogicVector(INIT_51) &
                                                       To_StdLogicVector(INIT_50) &
                                                       To_StdLogicVector(INIT_4F) &
                                                       To_StdLogicVector(INIT_4E) &
                                                       To_StdLogicVector(INIT_4D) &
                                                       To_StdLogicVector(INIT_4C) &
                                                       To_StdLogicVector(INIT_4B) &
                                                       To_StdLogicVector(INIT_4A) &
                                                       To_StdLogicVector(INIT_49) &
                                                       To_StdLogicVector(INIT_48) &
                                                       To_StdLogicVector(INIT_47) &
                                                       To_StdLogicVector(INIT_46) &
                                                       To_StdLogicVector(INIT_45) &
                                                       To_StdLogicVector(INIT_44) &
                                                       To_StdLogicVector(INIT_43) &
                                                       To_StdLogicVector(INIT_42) &
                                                       To_StdLogicVector(INIT_41) &
                                                       To_StdLogicVector(INIT_40) &
                                                       To_StdLogicVector(INIT_3F) &
                                                       To_StdLogicVector(INIT_3E) &
                                                       To_StdLogicVector(INIT_3D) &
                                                       To_StdLogicVector(INIT_3C) &
                                                       To_StdLogicVector(INIT_3B) &
                                                       To_StdLogicVector(INIT_3A) &
                                                       To_StdLogicVector(INIT_39) &
                                                       To_StdLogicVector(INIT_38) &
                                                       To_StdLogicVector(INIT_37) &
                                                       To_StdLogicVector(INIT_36) &
                                                       To_StdLogicVector(INIT_35) &
                                                       To_StdLogicVector(INIT_34) &
                                                       To_StdLogicVector(INIT_33) &
                                                       To_StdLogicVector(INIT_32) &
                                                       To_StdLogicVector(INIT_31) &
                                                       To_StdLogicVector(INIT_30) &
                                                       To_StdLogicVector(INIT_2F) &
                                                       To_StdLogicVector(INIT_2E) &
                                                       To_StdLogicVector(INIT_2D) &
                                                       To_StdLogicVector(INIT_2C) &
                                                       To_StdLogicVector(INIT_2B) &
                                                       To_StdLogicVector(INIT_2A) &
                                                       To_StdLogicVector(INIT_29) &
                                                       To_StdLogicVector(INIT_28) &
                                                       To_StdLogicVector(INIT_27) &
                                                       To_StdLogicVector(INIT_26) &
                                                       To_StdLogicVector(INIT_25) &
                                                       To_StdLogicVector(INIT_24) &
                                                       To_StdLogicVector(INIT_23) &
                                                       To_StdLogicVector(INIT_22) &
                                                       To_StdLogicVector(INIT_21) &
                                                       To_StdLogicVector(INIT_20) &
                                                       To_StdLogicVector(INIT_1F) &
                                                       To_StdLogicVector(INIT_1E) &
                                                       To_StdLogicVector(INIT_1D) &
                                                       To_StdLogicVector(INIT_1C) &
                                                       To_StdLogicVector(INIT_1B) &
                                                       To_StdLogicVector(INIT_1A) &
                                                       To_StdLogicVector(INIT_19) &
                                                       To_StdLogicVector(INIT_18) &
                                                       To_StdLogicVector(INIT_17) &
                                                       To_StdLogicVector(INIT_16) &
                                                       To_StdLogicVector(INIT_15) &
                                                       To_StdLogicVector(INIT_14) &
                                                       To_StdLogicVector(INIT_13) &
                                                       To_StdLogicVector(INIT_12) &
                                                       To_StdLogicVector(INIT_11) &
                                                       To_StdLogicVector(INIT_10) &
                                                       To_StdLogicVector(INIT_0F) &
                                                       To_StdLogicVector(INIT_0E) &
                                                       To_StdLogicVector(INIT_0D) &
                                                       To_StdLogicVector(INIT_0C) &
                                                       To_StdLogicVector(INIT_0B) &
                                                       To_StdLogicVector(INIT_0A) &
                                                       To_StdLogicVector(INIT_09) &
                                                       To_StdLogicVector(INIT_08) &
                                                       To_StdLogicVector(INIT_07) &
                                                       To_StdLogicVector(INIT_06) &
                                                       To_StdLogicVector(INIT_05) &
                                                       To_StdLogicVector(INIT_04) &
                                                       To_StdLogicVector(INIT_03) &
                                                       To_StdLogicVector(INIT_02) &
                                                       To_StdLogicVector(INIT_01) &
                                                       To_StdLogicVector(INIT_00);

    variable memp_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INITP_0F) &
                                                       To_StdLogicVector(INITP_0E) &
                                                       To_StdLogicVector(INITP_0D) &
                                                       To_StdLogicVector(INITP_0C) &
                                                       To_StdLogicVector(INITP_0B) &
                                                       To_StdLogicVector(INITP_0A) &
                                                       To_StdLogicVector(INITP_09) &
                                                       To_StdLogicVector(INITP_08) &
                                                       To_StdLogicVector(INITP_07) &
                                                       To_StdLogicVector(INITP_06) &
                                                       To_StdLogicVector(INITP_05) &
                                                       To_StdLogicVector(INITP_04) &
                                                       To_StdLogicVector(INITP_03) &
                                                       To_StdLogicVector(INITP_02) &
                                                       To_StdLogicVector(INITP_01) &
                                                       To_StdLogicVector(INITP_00);

    variable tmp_mem : Two_D_array_type_tmp_mem := two_D_mem_initf(widest_width);
    variable mem : Two_D_array_type := two_D_mem_init(mem_depth, width, mem_slv, tmp_mem);
    variable memp : Two_D_parity_array_type := two_D_mem_initp(memp_depth, widthp, memp_slv, tmp_mem, width);
    variable tmp_addra_dly_depth : integer;
    variable tmp_addra_dly_width : integer;
    variable tmp_addrb_dly_depth : integer;
    variable tmp_addrb_dly_width : integer;
    variable junk1 : std_logic;
    variable wr_mode_a : std_logic_vector(1 downto 0) := "00";
    variable wr_mode_b : std_logic_vector(1 downto 0) := "00";
    variable tmp_syndrome_int : integer;    
    variable doa_buf : std_logic_vector(63 downto 0) := (others => '0');
    variable dob_buf : std_logic_vector(63 downto 0) := (others => '0');
    variable dopa_buf : std_logic_vector(7 downto 0) := (others => '0');
    variable dopb_buf : std_logic_vector(7 downto 0) := (others => '0');    
    variable syndrome : std_logic_vector(7 downto 0) := (others => '0');
    variable dopr_ecc : std_logic_vector(7 downto 0) := (others => '0');        
    variable dia_dly_ecc_corrected : std_logic_vector(63 downto 0) := (others => '0');
    variable dipa_dly_ecc_corrected : std_logic_vector(7 downto 0) := (others => '0');
    variable dip_ecc : std_logic_vector(7 downto 0) := (others => '0');
    variable dipb_dly_ecc : std_logic_vector(7 downto 0) := (others => '0');        
    variable ecc_bit_position : std_logic_vector(71 downto 0) := (others => '0');
    variable addra_dly_15_reg_var : std_logic := '0';
    variable addrb_dly_15_reg_var : std_logic := '0';
    variable addra_dly_15_reg_bram_var : std_logic := '0';
    variable addrb_dly_15_reg_bram_var : std_logic := '0';
    variable FIRST_TIME : boolean := true;

    variable curr_time : time := 0 ps;
    variable prev_time : time := 0 ps;
    variable viol_time : integer := 0;
    variable viol_type : std_logic_vector(1 downto 0) := (others => '0');
    variable message : line;
    variable dip_ecc_col : std_logic_vector (7 downto 0) := (others => '0');
    variable dbiterr_out_var : std_ulogic := '0';
    variable sbiterr_out_var : std_ulogic := '0';

    variable dia_reg_dly : std_logic_vector(63 downto 0) := (others => '0');
    variable dipa_reg_dly : std_logic_vector(7 downto 0) := (others => '0');
    variable wea_reg_dly : std_logic_vector(7 downto 0) := (others => '0');
    variable addra_reg_dly : std_logic_vector(15 downto 0) := (others => '0');
    variable dib_reg_dly : std_logic_vector(63 downto 0) := (others => '0');
    variable dipb_reg_dly : std_logic_vector(7 downto 0) := (others => '0');
    variable web_reg_dly : std_logic_vector(7 downto 0) := (others => '0');
    variable addrb_reg_dly : std_logic_vector(15 downto 0) := (others => '0');
    variable col_wr_wr_msg : std_ulogic := '1';
    variable col_wra_rdb_msg : std_ulogic := '1';
    variable col_wrb_rda_msg : std_ulogic := '1';

    
  begin  -- process prcs_clka    

    
    if (FIRST_TIME) then

      
      if (SIM_MODE /= "FAST" and SIM_MODE /= "SAFE") then
        GenericValueCheckMessage
          ( HeaderMsg            => " Attribute Syntax Error : ",
            GenericName          => " SIM_MODE ",
            EntityName           => "ARAMB36_INTERNAL",
            GenericValue         => SIM_MODE,
            Unit                 => "",
            ExpectedValueMsg     => " The Legal values for this attribute are ",
            ExpectedGenericValue => " FAST or SAFE ",
            TailMsg              => "",
            MsgSeverity          => failure
            );
      end if;

      
      if (WRITE_MODE_A = "WRITE_FIRST") then
        wr_mode_a := "00";
      elsif (WRITE_MODE_A = "READ_FIRST") then
        wr_mode_a := "01";
      elsif (WRITE_MODE_A = "NO_CHANGE") then
        wr_mode_a := "10";
      end if;
    
      if (WRITE_MODE_B = "WRITE_FIRST") then
        wr_mode_b := "00";
      elsif (WRITE_MODE_B = "READ_FIRST") then
        wr_mode_b := "01";
      elsif (WRITE_MODE_B = "NO_CHANGE") then
        wr_mode_b := "10";
      end if;

    end if;

    
    if (gsr_dly = '1' or FIRST_TIME) then

      doa_out(ra_width-1 downto 0) <= INIT_A_STD(ra_width-1 downto 0);

      if (ra_width >= 8) then
        dopa_out(ra_widthp-1 downto 0) <= INIT_A_STD((ra_width+ra_widthp)-1 downto ra_width);            
      end if;

      dob_out(rb_width-1 downto 0) <= INIT_B_STD(rb_width-1 downto 0);          

      if (rb_width >= 8) then
        dopb_out(rb_widthp-1 downto 0) <= INIT_B_STD((rb_width+rb_widthp)-1 downto rb_width);            
      end if;

      dbiterr_out <= '0';
      sbiterr_out <= '0';

      FIRST_TIME := false;
      
    end if;

-------------------------------------------------------------------------------
-- Port A
-------------------------------------------------------------------------------        
    if (rising_edge(clka_dly)) then

      if (gsr_dly = '0' and ena_dly = '1') then

        if (ssra_dly = '1' and DOA_REG = 0) then

          doa_buf(ra_width-1 downto 0) := SRVAL_A_STD(ra_width-1 downto 0);
          doa_out(ra_width-1 downto 0) <= SRVAL_A_STD(ra_width-1 downto 0);          

          if (ra_width >= 8) then
            dopa_buf(ra_widthp-1 downto 0) := SRVAL_A_STD((ra_width+ra_widthp)-1 downto ra_width);
            dopa_out(ra_widthp-1 downto 0) <= SRVAL_A_STD((ra_width+ra_widthp)-1 downto ra_width);            
          end if;

        end if;
      
          -- read for rf
        if ((wr_mode_a = "01" and (ssra_dly = '0' or DOA_REG = 1))) then
            prcd_rd_ram_a (addra_dly, doa_buf, dopa_buf, mem, memp);
        end if;

        
        prcd_wr_ram_a (wea_dly, dia_dly, dipa_dly, addra_dly, mem, memp, syndrome);    


        if ((wr_mode_a /= "01" and (ssra_dly = '0' or DOA_REG = 1))) then
          prcd_rd_ram_a (addra_dly, doa_buf, dopa_buf, mem, memp);
        end if;


        if ((ssra_dly = '0' or DOA_REG = 1) and (wr_mode_a /= "10" or (WRITE_WIDTH_A <= 9 and wea_dly(0) = '0') or (WRITE_WIDTH_A = 18 and wea_dly(1 downto 0) = "00") or ((WRITE_WIDTH_A = 36 or WRITE_WIDTH_A = 72) and wea_dly(3 downto 0) = "0000"))) then

          doa_out <= doa_buf;
          dopa_out <= dopa_buf;

        end if;
      
      end if;
    end if;

    
-------------------------------------------------------------------------------
-- Port B
-------------------------------------------------------------------------------

    if (rising_edge(clkb_dly)) then


      if (gsr_dly = '0' and enb_dly = '1') then

        if (ssrb_dly = '1' and DOB_REG = 0) then

          dob_buf(rb_width-1 downto 0) := SRVAL_B_STD(rb_width-1 downto 0);
          dob_out(rb_width-1 downto 0) <= SRVAL_B_STD(rb_width-1 downto 0);          

          if (rb_width >= 8) then
            dopb_buf(rb_widthp-1 downto 0) := SRVAL_B_STD((rb_width+rb_widthp)-1 downto rb_width);
            dopb_out(rb_widthp-1 downto 0) <= SRVAL_B_STD((rb_width+rb_widthp)-1 downto rb_width);            
          end if;

        end if;

          
        if (wr_mode_b = "01" and (ssrb_dly = '0' or DOB_REG = 1)) then
          prcd_rd_ram_b (addrb_dly, dob_buf, dopb_buf, mem, memp);            
        end if;

        prcd_wr_ram_b (web_dly, dib_dly, dipb_dly, addrb_dly, mem, memp);

        if (wr_mode_b /= "01" and (ssrb_dly = '0' or DOB_REG = 1)) then
          prcd_rd_ram_b (addrb_dly, dob_buf, dopb_buf, mem, memp);
        end if;


        if ((ssrb_dly = '0' or DOB_REG = 1) and (wr_mode_b /= "10" or (WRITE_WIDTH_B <= 9 and web_dly(0) = '0') or (WRITE_WIDTH_B = 18 and web_dly(1 downto 0) = "00") or (WRITE_WIDTH_B = 36 and web_dly(3 downto 0) = "0000") or (WRITE_WIDTH_B = 72 and web_dly(7 downto 0) = "00000000"))) then

          dob_out <= dob_buf;
          dopb_out <= dopb_buf;
        end if;
        
      end if;
    end if;

  end process prcs_clk;


  outreg_clka: process (regclka_dly, gsr_dly)
    variable FIRST_TIME : boolean := true;
    
  begin  -- process outreg_clka

    if (rising_edge(regclka_dly) or rising_edge(gsr_dly) or FIRST_TIME) then

      if (DOA_REG = 1) then
        
        if (gsr_dly = '1' or FIRST_TIME) then

          dbiterr_outreg <= '0';
          sbiterr_outreg <= '0';
          
          doa_outreg(ra_width-1 downto 0) <= INIT_A_STD(ra_width-1 downto 0);

          if (ra_width >= 8) then
            dopa_outreg(ra_widthp-1 downto 0) <= INIT_A_STD((ra_width+ra_widthp)-1 downto ra_width);
          end if;

          FIRST_TIME := false;
          
        elsif (gsr_dly = '0') then

          if (regcea_dly = '1') then
            if (ssra_dly = '1') then

              doa_outreg(ra_width-1 downto 0) <= SRVAL_A_STD(ra_width-1 downto 0);

              if (ra_width >= 8) then
                dopa_outreg(ra_widthp-1 downto 0) <= SRVAL_A_STD((ra_width+ra_widthp)-1 downto ra_width);
              end if;

            elsif (ssra_dly = '0') then

              doa_outreg <= doa_out;
              dopa_outreg <= dopa_out;

            end if;     
          end if;
        end if;
      end if;

    end if;
  end process outreg_clka;
  

  outmux_clka: process (doa_out, dopa_out, doa_outreg, dopa_outreg)
  begin  -- process outmux_clka

      case DOA_REG is
        when 0 =>
                  doa_out_out <= doa_out;
                  dopa_out_out <= dopa_out;
        when 1 =>
                  doa_out_out <= doa_outreg_mux;
                  dopa_out_out <= dopa_outreg_mux;
        when others =>
      end case;

  end process outmux_clka;
  

  outreg_clkb: process (regclkb_dly, gsr_dly)
    variable FIRST_TIME : boolean := true;

  begin  -- process outreg_clkb

    if (rising_edge(regclkb_dly) or rising_edge(gsr_dly) or FIRST_TIME) then

      if (DOB_REG = 1) then
        
        if (gsr_dly = '1' or FIRST_TIME) then
          dob_outreg(rb_width-1 downto 0) <= INIT_B_STD(rb_width-1 downto 0);

          if (rb_width >= 8) then
            dopb_outreg(rb_widthp-1 downto 0) <= INIT_B_STD((rb_width+rb_widthp)-1 downto rb_width);
          end if;

          FIRST_TIME := false;
          
        elsif (gsr_dly = '0') then

          if (regceb_dly = '1') then
            if (ssrb_dly = '1') then

              dob_outreg(rb_width-1 downto 0) <= SRVAL_B_STD(rb_width-1 downto 0);

              if (rb_width >= 8) then
                dopb_outreg(rb_widthp-1 downto 0) <= SRVAL_B_STD((rb_width+rb_widthp)-1 downto rb_width);
              end if;

            elsif (ssrb_dly = '0') then

              dob_outreg <= dob_out;
              dopb_outreg <= dopb_out;

            end if;     
          end if;
        end if;
      end if;
      
    end if;
  end process outreg_clkb;

  
  outmux_clkb: process (dob_out, dopb_out, dob_outreg, dopb_outreg)
  begin  -- process outmux_clkb

      case DOB_REG is
        when 0 =>
                  dob_out_out <= dob_out;
                  dopb_out_out <= dopb_out;
        when 1 =>
                  dob_out_out <= dob_outreg;
                  dopb_out_out <= dopb_outreg;
        when others =>
      end case;

  end process outmux_clkb;


  end generate;


-------------------------------------------------------------------------------
-- Output
-------------------------------------------------------------------------------
    
  prcs_output: process (doa_out_out, dopa_out_out, dob_out_out, dopb_out_out, eccparity_out,
                        dbiterr_out_out, sbiterr_out_out, doa_out_mux(0), dob_out_mux(0),
                        doa_outreg_mux(0), dob_outreg_mux(0))
  begin  -- process prcs_output

    DOA <= doa_out_out;
    DOPA <= dopa_out_out;
    DOB <= dob_out_out;
    DOPB <= dopb_out_out;
    ECCPARITY <= eccparity_out;
    DBITERR <= dbiterr_out_out;
    SBITERR <= sbiterr_out_out;
    CASCADEOUTLATA <= doa_out_mux(0);
    CASCADEOUTLATB <= dob_out_mux(0);
    CASCADEOUTREGA <= doa_outreg_mux(0);
    CASCADEOUTREGB <= dob_outreg_mux(0);
    
  end process prcs_output;
  

end ARAMB36_INTERNAL_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Boundary Scan Logic Control Circuit for VIRTEX5
-- /___/   /\     Filename : BSCAN_VIRTEX5.v
-- \   \  /  \    Timestamp : Fri Jun 03 08:17:58 PST 2005
--  \___\/\___\
--
-- Revision:
--    06/03/05 - Initial version.

----- CELL BSCAN_VIRTEX5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.vcomponents.all;
entity BSCAN_VIRTEX5 is
  generic(
        JTAG_CHAIN : integer := 1
        );

  port(
    CAPTURE : out std_ulogic := 'H';
    DRCK    : out std_ulogic := 'H';
    RESET   : out std_ulogic := 'H';
    SEL     : out std_ulogic := 'L';
    SHIFT   : out std_ulogic := 'L';
    TDI     : out std_ulogic := 'L';
    UPDATE  : out std_ulogic := 'L';

    TDO     : in std_ulogic := 'X'
    );

end BSCAN_VIRTEX5;

architecture BSCAN_VIRTEX5_V of BSCAN_VIRTEX5 is

signal SEL_zd : std_ulogic := '0';
signal UPDATE_zd : std_ulogic := '0';

begin

--####################################################################
--#####                        Initialization                      ###
--####################################################################
  prcs_init:process
  begin
     if((JTAG_CHAIN /= 1) and (JTAG_CHAIN /= 2)  and (JTAG_CHAIN /= 3)
                                           and (JTAG_CHAIN /= 4)) then
        assert false
        report "Attribute Syntax Error: The allowed values for JTAG_CHAIN are 1, 2, 3 or 4"
        severity Failure;
     end if;
     wait;
  end process prcs_init;

-- synopsys translate_off

--####################################################################
--#####                        jtag_select                         ###
--####################################################################
  prcs_jtag_select:process (JTAG_SEL1_GLBL, JTAG_SEL2_GLBL, JTAG_SEL3_GLBL, JTAG_SEL4_GLBL)
  begin
      if(JTAG_CHAIN = 1) then
        SEL_zd <= JTAG_SEL1_GLBL;
      elsif(JTAG_CHAIN = 2) then
        SEL_zd <= JTAG_SEL2_GLBL;
      elsif(JTAG_CHAIN = 3) then
        SEL_zd <= JTAG_SEL3_GLBL;
      elsif(JTAG_CHAIN = 4) then
        SEL_zd <= JTAG_SEL4_GLBL;
     end if;

  end process prcs_jtag_select;

--####################################################################
--#####                        USER_TDO                            ###
--####################################################################
  prcs_jtag_UserTDO:process (TDO)
  begin
      if(JTAG_CHAIN = 1) then
        JTAG_USER_TDO1_GLBL <= TDO;
      elsif(JTAG_CHAIN = 2) then
        JTAG_USER_TDO2_GLBL <= TDO;
      elsif(JTAG_CHAIN = 3) then
        JTAG_USER_TDO3_GLBL <= TDO;
      elsif(JTAG_CHAIN = 4) then
        JTAG_USER_TDO4_GLBL <= TDO;
     end if;

  end process prcs_jtag_UserTDO;
--####################################################################

  CAPTURE <= JTAG_CAPTURE_GLBL;
  DRCK  <= ((SEL_zd and not JTAG_SHIFT_GLBL and not JTAG_CAPTURE_GLBL) or
            (SEL_zd and JTAG_SHIFT_GLBL and JTAG_TCK_GLBL) or
            (SEL_zd and JTAG_CAPTURE_GLBL and JTAG_TCK_GLBL));
  TDI     <= JTAG_TDI_GLBL;
  SEL     <= SEL_zd;
  SHIFT   <= JTAG_SHIFT_GLBL;
  UPDATE  <= JTAG_UPDATE_GLBL;
  RESET   <= JTAG_RESET_GLBL;

-- synopsys translate_on

end BSCAN_VIRTEX5_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/bufgmux_ctrl.vhd,v 1.2 2006/03/11 00:19:54 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Global Clock Mux Buffer
-- /___/   /\     Filename : BUFGMUX_CTRL.vhd
-- \   \  /  \    Timestamp : Fri Mar 26 08:17:58 PST 2004
--  \___\/\___\
--
-- Revision:
--    03/10/06 - Initial version.
-- end Revision

----- CELL BUFGMUX_CTRL -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;

library unisim;
use unisim.vpkg.all;
use unisim.vcomponents.all;

entity BUFGMUX_CTRL is

  port(
      O			: out std_ulogic;

      I0		: in std_ulogic;
      I1		: in std_ulogic;
      S			: in std_ulogic
    );

end BUFGMUX_CTRL;


architecture BUFGMUX_CTRL_V OF BUFGMUX_CTRL is


  signal SigPullUp		: std_ulogic := '1';
  signal SigPullDown		: std_ulogic := '0';
  signal NOT_S			: std_ulogic := 'X';

begin

  NOT_S <= NOT S;

----------------------------------------------------------------------
-----------    Instant BUFGCTRL  -------------------------------------
----------------------------------------------------------------------
  INST_BUFGCTRL : BUFGCTRL
  generic map (
      INIT_OUT => 0,
      PRESELECT_I0 => true,
      PRESELECT_I1 => false
     )
  port map (
      O		=> O,

      CE0	=> SigPullUp,
      CE1	=> SigPullUp,
      I0	=> I0,
      I1	=> I1,
      IGNORE0	=> SigPullDown,
      IGNORE1	=> SigPullDown,
      S0	=> NOT_S,
      S1	=> S
      );
end BUFGMUX_CTRL_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Register State Capture for Bitstream Readback for VIRTEX5
-- /___/   /\     Filename : CAPTURE_VIRTEX5.vhd
-- \   \  /  \    Timestamp : Thu Jun  2 10:57:03 PDT 2005
--  \___\/\___\
--
-- Revision:
--    06/03/05 - Initial version.

----- CELL CAPTURE_VIRTEX5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CAPTURE_VIRTEX5 is
  generic(
    ONESHOT : boolean := true
    );  
  port(
    CAP : in std_ulogic;
    CLK : in std_ulogic
    );

end CAPTURE_VIRTEX5;

architecture CAPTURE_VIRTEX5_V of CAPTURE_VIRTEX5 is

begin
end CAPTURE_VIRTEX5_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Function Simulation Library Component
--  /   /                  Fast Carry Logic with Look Ahead
-- /___/   /\     Filename : CARRY4.vhd
-- \   \  /  \    Timestamp : Fri Mar 26 08:18:19 PST 2004
--  \___\/\___\
-- Revision:
--    04/11/05 - Initial version.
--    05/06/05 - Unused CYINT or CI pin need grounded instead of open (CR207752)
--    05/31/05 - Change pin order, remove connection check for CYINT and CI.
-- End Revision

----- CELL CARRY4 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CARRY4 is

  port(
      CO          : out std_logic_vector(3 downto 0);
      O           : out std_logic_vector(3 downto 0);
    
      CI          : in  std_ulogic;
      CYINIT      : in  std_ulogic;
      DI          : in std_logic_vector(3 downto 0);
      S           : in std_logic_vector(3 downto 0)
      );

end CARRY4;

architecture CARRY4_V OF CARRY4 is

  signal ci_or_cyinit : std_ulogic;
  signal CO_out : std_logic_vector(3 downto 0);
begin

  O <= S xor ( CO_out(2 downto 0) & ci_or_cyinit );
  CO <= CO_out;

  CO_out(0) <= ci_or_cyinit when S(0) = '1' else DI(0); 
  CO_out(1) <= CO_out(0) when S(1) = '1' else DI(1); 
  CO_out(2) <= CO_out(1) when S(2) = '1' else DI(2); 
  CO_out(3) <= CO_out(2) when S(3) = '1' else DI(3); 
  ci_or_cyinit <= CI or CYINIT;

--  ci_sel : process (CYINIT , CI)
--  begin
--      if(CYINIT = 'U' or CYINIT = 'Z' or CYINIT = 'X') then
--         assert FALSE report
--            "Error : CARRY4 instance detects CYINIT unconnected. Only one of CI and CYINIT inputs can be used and other one need grounded."
--             severity failure;
--      elsif (CI = 'U' or CI = 'Z' or CI = 'X') then
--         assert FALSE report
--            "Error : CARRY4 instance detects CI unconnected. Only one of CI and CYINIT inputs can be used and other one need grounded."
--             severity failure;
--      else
--         ci_or_cyinit <= CI or CYINIT;
--      end if;
--
--   end process ci_sel;

end CARRY4_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/cfglut5.vhd,v 1.3 2006/04/21 23:37:23 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                 5-input Dynamically Reconfigurable Look-Up-Table with Carry and Clock Enable 
-- /___/   /\     Filename : CFGLUT5.vhd
-- \   \  /  \    Timestamp : 
--  \___\/\___\
--
-- Revision:
--    12/28/05 - Initial version.
--    04/13/06 - Add address declaration. (CR229735)
-- End Revision

----- CELL CFGLUT5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity CFGLUT5 is

  generic (
       INIT : bit_vector := X"00000000"
  );

  port (
        CDO : out STD_ULOGIC;
        O5  : out STD_ULOGIC;
        O6  : out STD_ULOGIC;

        CDI : in STD_ULOGIC;
        CE  : in STD_ULOGIC;
        CLK : in STD_ULOGIC;        
        I0  : in STD_ULOGIC;
        I1  : in STD_ULOGIC;
        I2  : in STD_ULOGIC;
        I3  : in STD_ULOGIC;
        I4  : in STD_ULOGIC
       ); 
end CFGLUT5;

architecture CFGLUT5_V of CFGLUT5 is
  signal SHIFT_REG : std_logic_vector (31 downto 0) :=  To_StdLogicVector(INIT);
  signal o6_slv : std_logic_vector (4 downto 0) ;
  signal o5_slv : std_logic_vector (3 downto 0) ;
  signal o6_addr : integer := 0;
  signal o5_addr : integer := 0;
begin

    o6_slv <= I4 & I3 & I2 & I1 & I0;
    o5_slv <= I3 & I2 & I1 & I0;
    o6_addr <= SLV_TO_INT(o6_slv(4 downto 0));
    o5_addr <= SLV_TO_INT(o5_slv(3 downto 0));
    O6 <= SHIFT_REG(o6_addr);
    O5 <= SHIFT_REG(o5_addr);
    CDO <= SHIFT_REG(31);

  WriteBehavior : process
    variable FIRST_TIME : boolean := TRUE;
  begin

    if (FIRST_TIME) then
        wait until ((CE = '1' or CE = '0') and
                   (CLK'last_value = '0' or CLK'last_value = '1') and
                   (CLK = '0' or CLK = '1'));
        FIRST_TIME := FALSE;
    end if;

    if (CLK'event AND CLK = '1') then
        if (CE = '1') then
           SHIFT_REG(31 downto 0) <= (SHIFT_REG(30 downto 0) & CDI) after 100 ps;
        end if ;
    end if;

    wait on CLK;

  end process WriteBehavior;

end CFGLUT5_V;


-------------------------------------------------------------------------------
-- Copyright (c) 1995/2006 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Cyclic Redundancy Check 32-bit Input Simulation Model
-- /___/   /\     Filename : CRC32.vhd
-- \   \  /  \    Timestamp : Fri Jun 18 10:57:01 PDT 2004
--  \___\/\___\
--
-- Revision:
--  12/20/05 - Initial version.
--  12/20/05 - Added functionality
--  01/09/06  - Added Timing
--  08/02/06 - CR#233833 - Remove GSR declaration
--  08/18/06 - CR#421781 - CRCOUT initialized to 0 when GSR is high
--  07/24/07 - CR#442758 - Use CRCCLK instead of crcclk_int in always block
--  08/16/07 - CR#446564 - Add data_width as part of process block sensitivity list
--  10/22/07 - CR#452418 - Add all to process sensitivity list
--  11/21/07 - CR#454853 - POLYNOMIAL is not a user attribute
-- End Revision
-------------------------------------------------------------------------------

----- CELL CRC32 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_SIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;

library STD;
use STD.TEXTIO.all;


library unisim;
use unisim.vcomponents.all;
use unisim.vpkg.all;

entity CRC32 is
  generic (
    CRC_INIT   : bit_vector := X"FFFFFFFF"
     );    
  port (
    CRCOUT : out std_logic_vector(31 downto 0);
  
    CRCCLK : in std_ulogic;
    CRCDATAVALID : in std_ulogic;
    CRCDATAWIDTH : in std_logic_vector(2 downto 0);
    CRCIN : in std_logic_vector(31 downto 0);
    CRCRESET : in std_ulogic
  );
end CRC32;
  
  architecture CRC32_V of CRC32 is
    
    signal   data_in_32 :  std_logic_vector(7 downto 0);
    signal   data_in_24 :  std_logic_vector(7 downto 0);
    signal   data_in_16 :  std_logic_vector(7 downto 0);
    signal   data_in_8  :  std_logic_vector(7 downto 0);
    signal   data_width :  std_logic_vector(2 downto 0);
    signal   data_valid :  std_logic;
    signal   crcd       :  std_logic_vector(31 downto 0);
    signal   crcreg     :  std_logic_vector(31 downto 0);
    
    signal   crcgen_out_32 :  std_logic_vector(31 downto 0);
    signal   crcgen_out_24 :  std_logic_vector(31 downto 0);
    signal   crcgen_out_16 :  std_logic_vector(31 downto 0);
    signal   crcgen_out_8  :  std_logic_vector(31 downto 0);
    
--    signal   crcclk_int    :  std_logic;
    signal   crcreset_int  :  std_logic;

    signal   crc_initial : std_logic_vector(31 downto 0);
    signal   poly_val    : std_logic_vector(31 downto 0);

    signal   zero_24     : std_logic_vector(23 downto 0);
    signal   zero_16     : std_logic_vector(15 downto 0);
    signal   zero_8     : std_logic_vector(7 downto 0);

    signal   GSR_dly     : std_logic;
    signal   CRCOUT_zd : std_logic_vector(31 downto 0) := ( others => '0');

    constant POLYNOMIAL : bit_vector := X"04C11DB7";

  begin

  GSR_dly  <= GSR  after 0 ps;
    
  crcreset_int <= CRCRESET;
--  crcclk_int <= CRCCLK;

  crc_initial <= To_StdLogicVector(CRC_INIT); 
  poly_val <= To_StdLogicVector(POLYNOMIAL);

  zero_24 <= "000000000000000000000000";
  zero_16 <= "0000000000000000";
  zero_8 <= "00000000";

  
  OUTPUT_CALC: process(GSR_dly,crcreg)
    begin
      if(GSR_dly = '1') then
         CRCOUT_zd <=  (others => '0');
      elsif(GSR_dly = '0') then
         CRCOUT_zd <= (not(crcreg(24)) & not(crcreg(25)) & not(crcreg(26)) & not(crcreg(27)) & not(crcreg(28)) & not(crcreg(29)) & not(crcreg(30)) & not(crcreg(31)) & not(crcreg(16)) & not(crcreg(17)) & not(crcreg(18)) & not(crcreg(19)) & not(crcreg(20)) & not(crcreg(21)) & not(crcreg(22)) & not(crcreg(23)) & not(crcreg(8)) & not(crcreg(9)) & not(crcreg(10)) & not(crcreg(11)) & not(crcreg(12)) & not(crcreg(13)) & not(crcreg(14)) & not(crcreg(15)) & not(crcreg(0)) & not(crcreg(1)) & not(crcreg(2)) & not(crcreg(3)) & not(crcreg(4)) & not(crcreg(5)) & not(crcreg(6)) & not(crcreg(7)));
      end if;
  end process;

  LOCK_DATA_IN: process(CRCCLK)
    begin
      if (rising_edge(CRCCLK)) then
        data_in_8  <= CRCIN(31 downto 24);	
        data_in_16 <= CRCIN(23 downto 16);	
        data_in_24 <= CRCIN(15 downto 8);
        data_in_32 <= CRCIN(7 downto 0);
        data_valid <= CRCDATAVALID;
        data_width <= CRCDATAWIDTH;
      end if;
  end process;
  
   
   -- Select between CRC8, CRC16, CRC24, CRC32 based on CRCDATAWIDTH
      
      SELECT_DATA_IN: process(crcgen_out_8,crcgen_out_16,crcgen_out_24,crcgen_out_32,crcd,data_width)
	 begin
	  case data_width is
 	   when  "000" => crcd <= crcgen_out_8;
	   when  "001" => crcd <= crcgen_out_16;
	   when  "010" => crcd <= crcgen_out_24;
	   when  "011" => crcd <= crcgen_out_32;
	   when others => crcd <= crcgen_out_8;
	end case;
     end process;
   
   -- 32-bit CRC internal register
   
   INT_REG: process(CRCCLK)
    begin
      if (rising_edge(CRCCLK)) then
        if (crcreset_int = '1') then
          crcreg <= crc_initial;
        elsif (data_valid /= '1') then 
          crcreg <= crcreg;
        else
          crcreg <= crcd;
        end if;
      end if;
   end process;   

   --CRC Generator Logic
   
  CRC_GEN: process(crcreg, CRCIN, data_width,data_in_8,data_in_16, data_in_24,data_in_32)
    variable   msg        :  std_logic_vector(40 downto 0);

    variable   concat_data_8 :  std_logic_vector(31 downto 0);
    variable   concat_data_16 :  std_logic_vector(31 downto 0);
    variable   concat_data_24 :  std_logic_vector(31 downto 0);
    variable   concat_data_32 :  std_logic_vector(31 downto 0);
    

    begin

      --CRC-8
        
      if (data_width = "000") then
        
        concat_data_8 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & zero_24;
      
        msg(31 downto 0) := crcreg xor concat_data_8;
        msg(40 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8);
      
        for i in 0 to 7 loop
          msg(40 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1);
          if (msg(40) = '1') then
            msg(39 downto 8) := msg(39 downto 8) xor poly_val;
          end if;
        end loop;
        crcgen_out_8 <= msg(39 downto 8);
       
        --CRC-16
    
      elsif (data_width = "001") then

        concat_data_16 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & data_in_16(0)& data_in_16(1) & data_in_16(2) & data_in_16(3) & data_in_16(4) & data_in_16(5) & data_in_16(6) & data_in_16(7) & zero_16;

        msg(31 downto 0) := crcreg xor concat_data_16;
        msg(40 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8);
	   
        for i in 0 to 15 loop
          msg(40 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1);
          if (msg(40) = '1') then
            msg(39 downto 8) := msg(39 downto 8) xor poly_val;
          end if;
        end loop;
        crcgen_out_16 <= msg(39 downto 8);

    --CRC-24
	
      elsif (data_width = "010") then 

        concat_data_24 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & data_in_16(0) & data_in_16(1) & data_in_16(2) & data_in_16(3) & data_in_16(4) & data_in_16(5) & data_in_16(6) & data_in_16(7) & data_in_24(0) & data_in_24(1) & data_in_24(2) & data_in_24(3) & data_in_24(4) & data_in_24(5) & data_in_24(6) & data_in_24(7) & zero_8;

        msg(31 downto 0) := crcreg xor concat_data_24;
        msg(40 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8);
	   
        for i in 0 to 23 loop
          msg(40 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1);
          if (msg(40) = '1') then
            msg(39 downto 8) := msg(39 downto 8) xor poly_val;
          end if;
        end loop;
        crcgen_out_24 <= msg(39 downto 8);


    --CRC-32
	
      elsif (data_width = "011") then
        concat_data_32 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & data_in_16(0) & data_in_16(1) & data_in_16(2) & data_in_16(3) & data_in_16(4) & data_in_16(5) & data_in_16(6) & data_in_16(7) & data_in_24(0) & data_in_24(1) & data_in_24(2) & data_in_24(3) & data_in_24(4) & data_in_24(5) & data_in_24(6) & data_in_24(7) & data_in_32(0) & data_in_32(1) & data_in_32(2) & data_in_32(3) & data_in_32(4) & data_in_32(5) & data_in_32(6) & data_in_32(7);
     
        msg(31 downto 0) := crcreg xor concat_data_32;
        msg(40 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8);

        for i in 0 to 31 loop
          msg(40 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1);
          if (msg(40) = '1') then
            msg(39 downto 8) := msg(39 downto 8) xor poly_val;
          end if;
        end loop;
        crcgen_out_32 <= msg(39 downto 8);
     
      end if;
    end process;
         
    UNISIM_OUT: process (CRCOUT_zd)
    begin 
      CRCOUT <= CRCOUT_zd after 100 ps;
    end process;
  
end CRC32_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2005 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Cyclic Redundancy Check 64-bit Input Simulation Model
-- /___/   /\     Filename : CRC64.vhd
-- \   \  /  \    Timestamp : Fri Jun 18 10:57:01 PDT 2004
--  \___\/\___\
--
-- Revision:
--  12/20/05 - Initial version.
--  12/20/05 - Added functionality
--  08/02/06 - CR#233833 - Remove GSR declaration
--  08/18/06 - CR#421781 - CRCOUT initialized to 0 when GSR is high
--  07/24/07 - CR#442758 - Use CRCCLK instead of crcclk_int in always block
--  08/16/07 - CR#446564 - Add data_width as part of process block sensitivity list
--  10/22/07 - CR#452418 - Add all to process sensitivity list
--  11/21/07 - CR#454853 - POLYNOMIAL is not a user attribute
-- End Revision
-------------------------------------------------------------------------------

----- CELL CRC64 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_SIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;

library STD;
use STD.TEXTIO.all;


library unisim;
use unisim.vcomponents.all;
use unisim.vpkg.all;

entity CRC64 is
  generic (
    CRC_INIT   : bit_vector := X"FFFFFFFF"
  );    
  port (
    CRCOUT : out std_logic_vector(31 downto 0);
  
    CRCCLK : in std_ulogic;
    CRCDATAVALID : in std_ulogic;
    CRCDATAWIDTH : in std_logic_vector(2 downto 0);
    CRCIN : in std_logic_vector(63 downto 0);
    CRCRESET : in std_ulogic
  );
end CRC64;
  
  architecture CRC64_V of CRC64 is

    signal   data_in_64 :  std_logic_vector(7 downto 0);
    signal   data_in_56 :  std_logic_vector(7 downto 0);
    signal   data_in_48 :  std_logic_vector(7 downto 0);
    signal   data_in_40  :  std_logic_vector(7 downto 0);

    signal   data_in_32 :  std_logic_vector(7 downto 0);
    signal   data_in_24 :  std_logic_vector(7 downto 0);
    signal   data_in_16 :  std_logic_vector(7 downto 0);
    signal   data_in_8  :  std_logic_vector(7 downto 0);
    
    signal   data_width :  std_logic_vector(2 downto 0);
    signal   data_valid :  std_ulogic;
    signal   crcd       :  std_logic_vector(31 downto 0);
    signal   crcreg     :  std_logic_vector(31 downto 0);

    signal   crcgen_out_64 :  std_logic_vector(31 downto 0);
    signal   crcgen_out_56 :  std_logic_vector(31 downto 0);
    signal   crcgen_out_48 :  std_logic_vector(31 downto 0);
    signal   crcgen_out_40 :  std_logic_vector(31 downto 0);

    signal   crcgen_out_32 :  std_logic_vector(31 downto 0);
    signal   crcgen_out_24 :  std_logic_vector(31 downto 0);
    signal   crcgen_out_16 :  std_logic_vector(31 downto 0);
    signal   crcgen_out_8  :  std_logic_vector(31 downto 0);
    
--    signal   crcclk_int    :  std_ulogic;
    signal   crcreset_int  :  std_ulogic;

    signal   crc_initial : std_logic_vector(31 downto 0);
    signal   poly_val    : std_logic_vector(31 downto 0);

    signal   zero_56     : std_logic_vector(55 downto 0);
    signal   zero_48     : std_logic_vector(47 downto 0);
    signal   zero_40     : std_logic_vector(39 downto 0);
    signal   zero_32     : std_logic_vector(31 downto 0);
    signal   zero_24     : std_logic_vector(23 downto 0);
    signal   zero_16     : std_logic_vector(15 downto 0);
    signal   zero_8      : std_logic_vector(7 downto 0);

    signal   GSR_dly     : std_ulogic;
    signal   CRCOUT_zd   : std_logic_vector(31 downto 0) := ( others => '0');
      
    constant POLYNOMIAL  : bit_vector := X"04C11DB7";

    begin

  GSR_dly  <= GSR  after 0 ps;

  crcreset_int <= CRCRESET;
--  crcclk_int <= CRCCLK;

  crc_initial <= To_StdLogicVector(CRC_INIT); 
  poly_val <= To_StdLogicVector(POLYNOMIAL);

  zero_56 <= "00000000000000000000000000000000000000000000000000000000";
  zero_48 <= "000000000000000000000000000000000000000000000000";
  zero_40 <= "0000000000000000000000000000000000000000";
  zero_32 <= "00000000000000000000000000000000";
  zero_24 <= "000000000000000000000000";
  zero_16 <= "0000000000000000";
  zero_8 <=  "00000000";
    
   
 OUTPUT_CALC: process(GSR_dly,crcreg)
   begin
      if(GSR_dly = '1') then
         CRCOUT_zd <=  (others => '0');
      elsif(GSR_dly = '0') then
          CRCOUT_zd <= (not(crcreg(24)) & not(crcreg(25)) & not(crcreg(26)) & not(crcreg(27)) & not(crcreg(28)) & not(crcreg(29)) & not(crcreg(30)) & not(crcreg(31)) & not(crcreg(16)) & not(crcreg(17)) & not(crcreg(18)) & not(crcreg(19)) & not(crcreg(20)) & not(crcreg(21)) & not(crcreg(22)) & not(crcreg(23)) & not(crcreg(8)) & not(crcreg(9)) & not(crcreg(10)) & not(crcreg(11)) & not(crcreg(12)) & not(crcreg(13)) & not(crcreg(14)) & not(crcreg(15)) & not(crcreg(0)) & not(crcreg(1)) & not(crcreg(2)) & not(crcreg(3)) & not(crcreg(4)) & not(crcreg(5)) & not(crcreg(6)) & not(crcreg(7)));
     end if;
  end process;

   LOCK_DATA_IN: process(CRCCLK)
    begin
      if (rising_edge(CRCCLK)) then
        data_in_8  <= CRCIN(63 downto 56);	
        data_in_16 <= CRCIN(55 downto 48);	
        data_in_24 <= CRCIN(47 downto 40);
        data_in_32 <= CRCIN(39 downto 32);
        data_in_40 <= CRCIN(31 downto 24);	
        data_in_48 <= CRCIN(23 downto 16);	
        data_in_56 <= CRCIN(15 downto 8);
        data_in_64 <= CRCIN(7 downto 0);
        data_valid <= CRCDATAVALID;
        data_width <= CRCDATAWIDTH;
      end if;
  end process;

   -- Select between CRC8, CRC16, CRC24, CRC32, CRC40, CRC48, CRC56, CRC64  based on CRCDATAWIDTH
      
      SELECT_DATA_IN: process(crcgen_out_8,crcgen_out_16,crcgen_out_24,crcgen_out_32,crcgen_out_40,crcgen_out_48,crcgen_out_56,crcgen_out_64,crcd,data_width)
	 begin
	  case data_width is
 	   when  "000" => crcd <= crcgen_out_8;
	   when  "001" => crcd <= crcgen_out_16;
	   when  "010" => crcd <= crcgen_out_24;
	   when  "011" => crcd <= crcgen_out_32;
           when  "100" => crcd <= crcgen_out_40;
	   when  "101" => crcd <= crcgen_out_48;
	   when  "110" => crcd <= crcgen_out_56;
	   when  "111" => crcd <= crcgen_out_64;               
	   when others => crcd <= crcgen_out_8;
	end case;
     end process;
   
   -- 32-bit CRC internal register
   
   INT_REG: process(CRCCLK)
    begin
      if (rising_edge(CRCCLK)) then
        if (crcreset_int = '1') then
          crcreg <= crc_initial;
        elsif (data_valid /= '1') then 
          crcreg <= crcreg;
        else
          crcreg <= crcd;
        end if;
      end if;
   end process;   

   --CRC Generator Logic
   
  CRC_GEN: process(crcreg, CRCIN, data_width,data_in_8,data_in_16, data_in_24,data_in_32,data_in_40, data_in_48, data_in_56, data_in_64)
    variable   msg        :  std_logic_vector(72 downto 0);

    variable   concat_data_8  :  std_logic_vector(63 downto 0);
    variable   concat_data_16 :  std_logic_vector(63 downto 0);
    variable   concat_data_24 :  std_logic_vector(63 downto 0);
    variable   concat_data_32 :  std_logic_vector(63 downto 0);
    
    variable   concat_data_40 :  std_logic_vector(63 downto 0);
    variable   concat_data_48 :  std_logic_vector(63 downto 0);
    variable   concat_data_56 :  std_logic_vector(63 downto 0);
    variable   concat_data_64 :  std_logic_vector(63 downto 0);
    
    begin

      --CRC-8
        
      if (data_width = "000") then
        
        concat_data_8 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & zero_56;
      
        msg(63 downto 0) := (crcreg & zero_32) xor concat_data_8;
        msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8);
      
        for i in 0 to 7 loop
          msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1);
          if (msg(72) = '1') then
            msg(71 downto 40) := msg(71 downto 40) xor poly_val;
          end if;
        end loop;
        crcgen_out_8 <= msg(71 downto 40);
       
        --CRC-16
    
      elsif (data_width = "001") then

        concat_data_16 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & data_in_16(0)& data_in_16(1) & data_in_16(2) & data_in_16(3) & data_in_16(4) & data_in_16(5) & data_in_16(6) & data_in_16(7) & zero_48;

        msg(63 downto 0) := (crcreg & zero_32) xor concat_data_16;
        msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8);
	   
        for i in 0 to 15 loop
          msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1);
          if (msg(72) = '1') then
            msg(71 downto 40) := msg(71 downto 40) xor poly_val;
          end if;
        end loop;
        crcgen_out_16 <= msg(71 downto 40);

    --CRC-24
	
      elsif (data_width = "010") then 

        concat_data_24 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & data_in_16(0) & data_in_16(1) & data_in_16(2) & data_in_16(3) & data_in_16(4) & data_in_16(5) & data_in_16(6) & data_in_16(7) & data_in_24(0) & data_in_24(1) & data_in_24(2) & data_in_24(3) & data_in_24(4) & data_in_24(5) & data_in_24(6) & data_in_24(7) & zero_40;

        msg(63 downto 0) := (crcreg & zero_32) xor concat_data_24;
        msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8);
	   
        for i in 0 to 23 loop
          msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1);
          if (msg(72) = '1') then
            msg(71 downto 40) := msg(71 downto 40) xor poly_val;
          end if;
        end loop;
        crcgen_out_24 <= msg(71 downto 40);


    --CRC-32
	
      elsif (data_width = "011") then
        concat_data_32 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & data_in_16(0) & data_in_16(1) & data_in_16(2) & data_in_16(3) & data_in_16(4) & data_in_16(5) & data_in_16(6) & data_in_16(7) & data_in_24(0) & data_in_24(1) & data_in_24(2) & data_in_24(3) & data_in_24(4) & data_in_24(5) & data_in_24(6) & data_in_24(7) & data_in_32(0) & data_in_32(1) & data_in_32(2) & data_in_32(3) & data_in_32(4) & data_in_32(5) & data_in_32(6) & data_in_32(7) & zero_32;
     
        msg(63 downto 0) := (crcreg & zero_32) xor concat_data_32;
        msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8);

        for i in 0 to 31 loop
          msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1);
          if (msg(72) = '1') then
            msg(71 downto 40) := msg(71 downto 40) xor poly_val;
          end if;
        end loop;
        crcgen_out_32 <= msg(71 downto 40);

        -- CRC-40
        
      elsif (data_width = "100") then
        concat_data_40 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & data_in_16(0) & data_in_16(1) & data_in_16(2) & data_in_16(3) & data_in_16(4) & data_in_16(5) & data_in_16(6) & data_in_16(7) & data_in_24(0) & data_in_24(1) & data_in_24(2) & data_in_24(3) & data_in_24(4) & data_in_24(5) & data_in_24(6) & data_in_24(7) & data_in_32(0) & data_in_32(1) & data_in_32(2) & data_in_32(3) & data_in_32(4) & data_in_32(5) & data_in_32(6) & data_in_32(7) & data_in_40(0) & data_in_40(1) & data_in_40(2) & data_in_40(3) & data_in_40(4) & data_in_40(5) & data_in_40(6) & data_in_40(7) & zero_24;

        msg(63 downto 0) := (crcreg & zero_32) xor concat_data_40;
        msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8);
        
        for i in 0 to 39 loop
          msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1);
          if (msg(72) = '1') then
            msg(71 downto 40) := msg(71 downto 40) xor poly_val;
          end if;
        end loop;
        crcgen_out_40 <= msg(71 downto 40);
        
        --CRC-48
	
      elsif (data_width = "101") then

        concat_data_48 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & data_in_16(0) & data_in_16(1) & data_in_16(2) & data_in_16(3) & data_in_16(4) & data_in_16(5) & data_in_16(6) & data_in_16(7) & data_in_24(0) & data_in_24(1) & data_in_24(2) & data_in_24(3) & data_in_24(4) & data_in_24(5) & data_in_24(6) & data_in_24(7) & data_in_32(0) & data_in_32(1) & data_in_32(2) & data_in_32(3) & data_in_32(4) & data_in_32(5) & data_in_32(6) & data_in_32(7) & data_in_40(0) & data_in_40(1) & data_in_40(2) & data_in_40(3) & data_in_40(4) & data_in_40(5) & data_in_40(6) & data_in_40(7) & data_in_48(0) & data_in_48(1) & data_in_48(2) & data_in_48(3) & data_in_48(4) & data_in_48(5) & data_in_48(6) & data_in_48(7) & zero_16;
        
        msg(63 downto 0) := (crcreg & zero_32) xor concat_data_48;
        msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8);
        
        for i in 0 to 47 loop
          msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1);
          if (msg(72) = '1') then
            msg(71 downto 40) := msg(71 downto 40) xor poly_val;
          end if;
        end loop;
        crcgen_out_48 <= msg(71 downto 40);

        --CRC-56
	
	elsif (data_width = "110") then

        concat_data_56 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & data_in_16(0) & data_in_16(1) & data_in_16(2) & data_in_16(3) & data_in_16(4) & data_in_16(5) & data_in_16(6) & data_in_16(7) & data_in_24(0) & data_in_24(1) & data_in_24(2) & data_in_24(3) & data_in_24(4) & data_in_24(5) & data_in_24(6) & data_in_24(7) & data_in_32(0) & data_in_32(1) & data_in_32(2) & data_in_32(3) & data_in_32(4) & data_in_32(5) & data_in_32(6) & data_in_32(7) & data_in_40(0) & data_in_40(1) & data_in_40(2) & data_in_40(3) & data_in_40(4) & data_in_40(5) & data_in_40(6) & data_in_40(7) & data_in_48(0) & data_in_48(1) & data_in_48(2) & data_in_48(3) & data_in_48(4) & data_in_48(5) & data_in_48(6) & data_in_48(7) & data_in_56(0) & data_in_56(1) & data_in_56(2) & data_in_56(3) & data_in_56(4) & data_in_56(5) & data_in_56(6) & data_in_56(7) & zero_8;
      
        msg(63 downto 0) := (crcreg & zero_32) xor concat_data_56;
        msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8);
        
        for i in 0 to 55 loop
          msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1);
          if (msg(72) = '1') then
            msg(71 downto 40) := msg(71 downto 40) xor poly_val;
          end if;
        end loop;
        crcgen_out_56 <= msg(71 downto 40);

        --CRC-64
	
	elsif (data_width = "111")then
          concat_data_64 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & data_in_16(0) & data_in_16(1) & data_in_16(2) & data_in_16(3) & data_in_16(4) & data_in_16(5) & data_in_16(6) & data_in_16(7) & data_in_24(0) & data_in_24(1) & data_in_24(2) & data_in_24(3) & data_in_24(4) & data_in_24(5) & data_in_24(6) & data_in_24(7) & data_in_32(0) & data_in_32(1) & data_in_32(2) & data_in_32(3) & data_in_32(4) & data_in_32(5) & data_in_32(6) & data_in_32(7) & data_in_40(0) & data_in_40(1) & data_in_40(2) & data_in_40(3) & data_in_40(4) & data_in_40(5) & data_in_40(6) & data_in_40(7) & data_in_48(0) & data_in_48(1) & data_in_48(2) & data_in_48(3) & data_in_48(4) & data_in_48(5) & data_in_48(6) & data_in_48(7) & data_in_56(0) & data_in_56(1) & data_in_56(2) & data_in_56(3) & data_in_56(4) & data_in_56(5) & data_in_56(6) & data_in_56(7) & data_in_64(0) & data_in_64(1) & data_in_64(2) & data_in_64(3) & data_in_64(4) & data_in_64(5) & data_in_64(6) &  data_in_64(7);
          
          msg(63 downto 0) := (crcreg & zero_32) xor concat_data_64;
          msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8);
        
          for i in 0 to 63 loop
            msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1);
            if (msg(72) = '1') then
              msg(71 downto 40) := msg(71 downto 40) xor poly_val;
            end if;
          end loop;
          crcgen_out_64 <= msg(71 downto 40);

          
      end if;

      
    end process;
         
    UNISIM_OUT: process (CRCOUT_zd)
    begin 
      CRCOUT <= CRCOUT_zd after 100 ps;
    end process;
    
end CRC64_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                  18X18 Signed Multiplier Followed by Three-Input Adder plus ALU with Pipeline Registers
-- /___/   /\     Filename : DSP48E.vhd
-- \   \  /  \    Timestamp : Mon Mar 28 22:50:04 PST 2005
--  \___\/\___\
--
-- Revision:
--    03/28/05 - Initial version.
--    05/26/05 - BTrack 191 mult not valid in TWO24/FOUR12/USE_MULT=NONE.
--    06/16/05 - Added MULTSIGNIN/OUT pins and functionality
--    09/29/05 - Made xyz muxes to be sensitive to carryinsel when recovering from invalid opmode/carryinsel
--    10/05/05 - Added more valid DRC check entries.
--    10/25/05 - CR 219047
--    11/03/05 - Added two DRC checks -- ARITHMETIC and LOGIC
--    11/07/05 - 'X'ed out carrycascout in LOGIC modes (like the carryout)
--    11/21/05 - 'X'ed out pattern detect signals when in illegal opmodes.
--    02/28/06 - CR 225886 -- USE_MULT check updates. 
--    02/28/06 - CR 226267 -- Changed USE_MULT default to MULT_S.
--    05/20/06 - CR 230656 -- Disabled RSTP timing check during GSR.
--    05/29/06 - CR 232187 -- Corrected multcarryinreg CASE statement 
--    05/29/06 - CR 232275 -- Corrected PREG/multsignout_o_mux
--    10/29/06 - CR 424959 -- Corrected unisim false violation warnings
--    12/10/06 - CR 429825 -- Added Timing Checks for CARRYCASCIN.
--    02/20/07 - CR 434192 -- Fixed RSTALUMODE issue
--    06/11/07 - Added SIM_MODE -- FAST/SAFE feature
--    06/29/07 - CR 438456 -- Added DRC to output X when USE_MULT=MULT_S is set and not using the multiplier opmode through muxX 
--    08/06/07 - CR 445673 -- Fixed CARRYCASCOUT registered mode issue
--    10/01/07 - CR 448147 -- Fixed error introduced by 438456
--    10/10/07 - CR 451453 -- DRC warning
--    10/15/07 - CR 444150 -- DRC check enhancements for OPMODEREG/CARRYINSELREG 
--    11/06/07 - CR 451178 -- DRC warning enhancement
--    02/06/08 - CR 455601 -- DRC relax for OPMODEREG/CARRYINSELREG
-- End Revision
----- CELL DSP48E -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_SIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;

library STD;
use STD.TEXTIO.all;


library unisim;
use unisim.vpkg.all;

entity DSP48E is

  generic(

        SIM_MODE	: string		:= "SAFE";

        ACASCREG	: integer		:= 1;
        ALUMODEREG	: integer		:= 1;
        AREG		: integer		:= 1;
        AUTORESET_PATTERN_DETECT		: boolean		:= FALSE;
        AUTORESET_PATTERN_DETECT_OPTINV		: string		:= "MATCH";
        A_INPUT		: string		:= "DIRECT";
        BCASCREG	: integer		:= 1;
        BREG		: integer		:= 1;
        B_INPUT		: string		:= "DIRECT";
        CARRYINREG	: integer		:= 1;
        CARRYINSELREG	: integer		:= 1;
        CREG		: integer		:= 1;
        MASK            : bit_vector            := X"3FFFFFFFFFFF";
        MREG		: integer		:= 1;
        MULTCARRYINREG	: integer		:= 1;
        OPMODEREG	: integer		:= 1;
        PATTERN         : bit_vector            := X"000000000000";
        PREG		: integer		:= 1;
        SEL_MASK	: string		:= "MASK";
        SEL_PATTERN	: string		:= "PATTERN";
        SEL_ROUNDING_MASK	: string	:= "SEL_MASK";
        USE_MULT	: string		:= "MULT_S";
        USE_PATTERN_DETECT	: string	:= "NO_PATDET";
        USE_SIMD	: string		:= "ONE48"
        );

  port(
        ACOUT                   : out std_logic_vector(29 downto 0);
        BCOUT                   : out std_logic_vector(17 downto 0);
        CARRYCASCOUT            : out std_ulogic;
        CARRYOUT                : out std_logic_vector(3 downto 0);
        MULTSIGNOUT             : out std_ulogic;
        OVERFLOW                : out std_ulogic;
        P                       : out std_logic_vector(47 downto 0);
        PATTERNBDETECT          : out std_ulogic;
        PATTERNDETECT           : out std_ulogic;
        PCOUT                   : out std_logic_vector(47 downto 0);
        UNDERFLOW               : out std_ulogic;

        A                       : in  std_logic_vector(29 downto 0);
        ACIN                    : in  std_logic_vector(29 downto 0);
        ALUMODE                 : in  std_logic_vector(3 downto 0);
        B                       : in  std_logic_vector(17 downto 0);
        BCIN                    : in  std_logic_vector(17 downto 0);
        C                       : in  std_logic_vector(47 downto 0);
        CARRYCASCIN             : in  std_ulogic;
        CARRYIN                 : in  std_ulogic;
        CARRYINSEL              : in  std_logic_vector(2 downto 0);
        CEA1                    : in  std_ulogic;
        CEA2                    : in  std_ulogic;
        CEALUMODE               : in  std_ulogic;
        CEB1                    : in  std_ulogic;
        CEB2                    : in  std_ulogic;
        CEC                     : in  std_ulogic;
        CECARRYIN               : in  std_ulogic;
        CECTRL                  : in  std_ulogic;
        CEM                     : in  std_ulogic;
        CEMULTCARRYIN           : in  std_ulogic;
        CEP                     : in  std_ulogic;
        CLK                     : in  std_ulogic;
        MULTSIGNIN              : in std_ulogic;
        OPMODE                  : in  std_logic_vector(6 downto 0);
        PCIN                    : in  std_logic_vector(47 downto 0);
        RSTA                    : in  std_ulogic;
        RSTALLCARRYIN           : in  std_ulogic;
        RSTALUMODE              : in  std_ulogic;
        RSTB                    : in  std_ulogic;
        RSTC                    : in  std_ulogic;
        RSTCTRL                 : in  std_ulogic;
        RSTM                    : in  std_ulogic;
        RSTP                    : in  std_ulogic
      );

end DSP48E;

-- architecture body                    --

architecture DSP48E_V of DSP48E is

    procedure invalid_opmode_preg_msg( OPMODE : IN string ; 
                                   CARRYINSEL : IN string ) is
    variable Message : line;
    begin
       Write ( Message, string'("OPMODE Input Warning : The OPMODE "));
       Write ( Message,  OPMODE);
       Write ( Message, string'(" with CARRYINSEL "));
       Write ( Message,  CARRYINSEL);
       Write ( Message, string'(" to DSP48E instance "));
       Write ( Message, string'("requires attribute PREG set to 1."));
       assert false report Message.all severity Warning;
       DEALLOCATE (Message);
    end invalid_opmode_preg_msg;

    procedure invalid_opmode_preg_msg_logic( OPMODE : IN string ) is
    variable Message : line;
    begin
       Write ( Message, string'("OPMODE Input Warning : The OPMODE "));
       Write ( Message,  OPMODE);
       Write ( Message, string'(" to DSP48E instance "));
       Write ( Message, string'("requires attribute PREG set to 1."));
       assert false report Message.all severity Warning;
       DEALLOCATE (Message);
    end invalid_opmode_preg_msg_logic;

    procedure invalid_opmode_mreg_msg( OPMODE : IN string ; 
                                   CARRYINSEL : IN string ) is
    variable Message : line;
    begin
       Write ( Message, string'("OPMODE Input Warning : The OPMODE "));
       Write ( Message,  OPMODE);
       Write ( Message, string'(" with CARRYINSEL "));
       Write ( Message,  CARRYINSEL);
       Write ( Message, string'(" to DSP48E instance "));
       Write ( Message, string'("requires attribute MREG set to 1."));
       assert false report Message.all severity Warning;
       DEALLOCATE (Message);
    end invalid_opmode_mreg_msg;

    procedure invalid_opmode_no_mreg_msg( OPMODE : IN string ; 
                                      CARRYINSEL : IN string ) is
    variable Message : line;
    begin
       Write ( Message, string'("OPMODE Input Warning : The OPMODE "));
       Write ( Message,  OPMODE);
       Write ( Message, string'(" with CARRYINSEL "));
       Write ( Message,  CARRYINSEL);
       Write ( Message, string'(" to DSP48E instance "));
       Write ( Message, string'("requires attribute MREG set to 0."));
       assert false report Message.all severity Warning;
       DEALLOCATE (Message);
    end invalid_opmode_no_mreg_msg;



  TYPE AluFuntionType is (INVALID_ALU, ADD_ALU, ADD_XY_NOTZ_ALU, NOT_XYZC_ALU, SUBTRACT_ALU, NOT_ALU, 
                          AND_ALU, OR_ALU, XOR_ALU, NAND_ALU, NOR_ALU, 
                          XNOR_ALU, X_AND_NOT_Z_ALU, NOT_X_OR_Z_ALU, X_OR_NOT_Z_ALU,
                          X_NOR_Z_ALU, NOT_X_AND_Z_ALU);

  constant SYNC_PATH_DELAY : time := 100 ps;

  constant MAX_ACOUT      : integer    := 30;
  constant MAX_BCOUT      : integer    := 18;
  constant MAX_CARRYOUT   : integer    := 4;
  constant MAX_P          : integer    := 48;
  constant MAX_PCOUT      : integer    := 48;

  constant MAX_A          : integer    := 30;
  constant MAX_ACIN       : integer    := 30;
  constant MAX_ALUMODE    : integer    := 4;
  constant MAX_A_MULT     : integer    := 25;
  constant MAX_B          : integer    := 18;
  constant MAX_B_MULT     : integer    := 18;
  constant MAX_BCIN       : integer    := 18;
  constant MAX_C          : integer    := 48;
  constant MAX_CARRYINSEL : integer    := 3;
  constant MAX_OPMODE     : integer    := 7;
  constant MAX_PCIN       : integer    := 48;

  constant MAX_ALU_FULL   : integer    := 48;
  constant MAX_ALU_HALF   : integer    := 24;
  constant MAX_ALU_QUART  : integer    := 12;

  constant MSB_ACOUT      : integer    := MAX_ACOUT - 1;
  constant MSB_BCOUT      : integer    := MAX_BCOUT - 1;
  constant MSB_CARRYOUT   : integer    := MAX_CARRYOUT - 1;
  constant MSB_P          : integer    := MAX_P - 1;
  constant MSB_PCOUT      : integer    := MAX_PCOUT - 1;


  constant MSB_A          : integer    := MAX_A - 1;
  constant MSB_ACIN       : integer    := MAX_ACIN - 1;
  constant MSB_ALUMODE    : integer    := MAX_ALUMODE - 1;
  constant MSB_A_MULT     : integer    := MAX_A_MULT - 1;
  constant MSB_B          : integer    := MAX_B - 1;
  constant MSB_B_MULT     : integer    := MAX_B_MULT - 1;
  constant MSB_BCIN       : integer    := MAX_BCIN - 1;
  constant MSB_C          : integer    := MAX_C - 1;
  constant MSB_CARRYINSEL : integer    := MAX_CARRYINSEL - 1;
  constant MSB_OPMODE     : integer    := MAX_OPMODE - 1;
  constant MSB_PCIN       : integer    := MAX_PCIN - 1;

  constant MSB_ALU_FULL   : integer    := MAX_ALU_FULL - 1;
  constant MSB_ALU_HALF   : integer    := MAX_ALU_HALF - 1;
  constant MSB_ALU_QUART  : integer    := MAX_ALU_QUART - 1;

  constant SHIFT_MUXZ     : integer    := 17;

  signal 	A_ipd		: std_logic_vector(MSB_A downto 0) := (others => '0');
  signal 	ACIN_ipd	: std_logic_vector(MSB_ACIN downto 0) := (others => '0');
  signal 	ALUMODE_ipd	: std_logic_vector(MSB_ALUMODE downto 0) := (others => '0');
  signal 	B_ipd		: std_logic_vector(MSB_B downto 0) := (others => '0');
  signal 	BCIN_ipd	: std_logic_vector(MSB_BCIN downto 0) := (others => '0');
  signal 	C_ipd		: std_logic_vector(MSB_C downto 0)    := (others => '0');
  signal 	CARRYCASCIN_ipd	: std_logic := '0';
  signal 	CARRYIN_ipd	: std_logic := '0';
  signal 	CARRYINSEL_ipd	: std_logic_vector(MSB_CARRYINSEL downto 0)  := (others => '0');
  signal 	CEA1_ipd	: std_logic := '0';
  signal 	CEA2_ipd	: std_logic := '0';
  signal 	CEALUMODE_ipd	: std_logic := '0';
  signal 	CEB1_ipd	: std_logic := '0';
  signal 	CEB2_ipd	: std_logic := '0';
  signal 	CEC_ipd		: std_logic := '0';
  signal 	CECARRYIN_ipd	: std_logic := '0';
  signal 	CECTRL_ipd	: std_logic := '0';
  signal 	CEM_ipd		: std_logic := '0';
  signal 	CEMULTCARRYIN_ipd	: std_logic := '0';
  signal 	CEP_ipd		: std_logic := '0';
  signal 	CLK_ipd		: std_logic := '0';
  signal GSR            : std_ulogic := '0';
  signal 	GSR_ipd		: std_ulogic := '0';
  signal 	MULTSIGNIN_ipd		: std_logic := '0';
  signal 	OPMODE_ipd	: std_logic_vector(MSB_OPMODE downto 0)  := (others => '0');
  signal 	PCIN_ipd	: std_logic_vector(MSB_PCIN downto 0) := (others => '0');
  signal 	RSTA_ipd	: std_logic := '0';
  signal 	RSTALLCARRYIN_ipd	: std_logic := '0';
  signal 	RSTALUMODE_ipd	: std_logic := '0';
  signal 	RSTB_ipd	: std_logic := '0';
  signal 	RSTC_ipd	: std_logic := '0';
  signal 	RSTCTRL_ipd	: std_logic := '0';
  signal 	RSTM_ipd	: std_logic := '0';
  signal 	RSTP_ipd	: std_logic := '0';

  signal 	A_dly		: std_logic_vector(MSB_A downto 0) := (others => '0');
  signal 	ACIN_dly	: std_logic_vector(MSB_ACIN downto 0) := (others => '0');
  signal 	ALUMODE_dly	: std_logic_vector(MSB_ALUMODE downto 0) := (others => '0');
  signal 	B_dly		: std_logic_vector(MSB_B downto 0) := (others => '0');
  signal 	BCIN_dly	: std_logic_vector(MSB_BCIN downto 0) := (others => '0');
  signal 	C_dly		: std_logic_vector(MSB_C downto 0)    := (others => '0');
  signal 	CARRYCASCIN_dly	: std_logic := '0';
  signal 	CARRYIN_dly	: std_logic := '0';
  signal 	CARRYINSEL_dly	: std_logic_vector(MSB_CARRYINSEL downto 0)  := (others => '0');
  signal 	CEA1_dly	: std_logic := '0';
  signal 	CEA2_dly	: std_logic := '0';
  signal 	CEALUMODE_dly	: std_logic := '0';
  signal 	CEB1_dly	: std_logic := '0';
  signal 	CEB2_dly	: std_logic := '0';
  signal 	CEC_dly		: std_logic := '0';
  signal 	CECARRYIN_dly	: std_logic := '0';
  signal 	CECTRL_dly	: std_logic := '0';
  signal 	CEM_dly		: std_logic := '0';
  signal 	CEMULTCARRYIN_dly	: std_logic := '0';
  signal 	CEP_dly		: std_logic := '0';
  signal 	CLK_dly		: std_logic := '0';
  signal 	GSR_dly		: std_logic := '0';
  signal 	MULTSIGNIN_dly	: std_logic := '0';
  signal 	OPMODE_dly	: std_logic_vector(MSB_OPMODE downto 0)  := (others => '0');
  signal 	PCIN_dly	: std_logic_vector(MSB_PCIN downto 0) := (others => '0');
  signal 	RSTA_dly	: std_logic := '0';
  signal 	RSTALLCARRYIN_dly	: std_logic := '0';
  signal 	RSTALUMODE_dly	: std_logic := '0';
  signal 	RSTB_dly	: std_logic := '0';
  signal 	RSTC_dly	: std_logic := '0';
  signal 	RSTCTRL_dly	: std_logic := '0';
  signal 	RSTM_dly	: std_logic := '0';
  signal 	RSTP_dly	: std_logic := '0';


  signal	ACOUT_zd	: std_logic_vector(MSB_ACOUT downto 0) := (others => '0');
  signal	BCOUT_zd	: std_logic_vector(MSB_BCOUT downto 0) := (others => '0');
  signal 	CARRYCASCOUT_zd	: std_logic := '0';
  signal	CARRYOUT_zd	: std_logic_vector(MSB_CARRYOUT downto 0) := (others => '0');
  signal 	OVERFLOW_zd	: std_logic := '0';
  signal	P_zd		: std_logic_vector(MSB_P downto 0) := (others => '0');
  signal 	PATTERNBDETECT_zd	: std_logic := '0';
  signal 	PATTERNDETECT_zd	: std_logic := '0';
  signal	PCOUT_zd	: std_logic_vector(MSB_PCOUT downto 0) := (others => '0');
  signal 	UNDERFLOW_zd	: std_logic := '0';
  signal 	MULTSIGNOUT_zd	: std_logic;
  
  --- Internal Signal Declarations
  signal	a_o_mux		: std_logic_vector(MSB_A downto 0) := (others => '0');
  signal	qa_o_reg1	: std_logic_vector(MSB_A downto 0) := (others => '0');
  signal	qa_o_reg2	: std_logic_vector(MSB_A downto 0) := (others => '0');
  signal	qa_o_mux	: std_logic_vector(MSB_A downto 0) := (others => '0');
  signal	qacout_o_mux	: std_logic_vector(MSB_ACOUT downto 0) := (others => '0');

  signal	b_o_mux		: std_logic_vector(MSB_B downto 0) := (others => '0');
  signal	qb_o_reg1	: std_logic_vector(MSB_B downto 0) := (others => '0');
  signal	qb_o_reg2	: std_logic_vector(MSB_B downto 0) := (others => '0');
  signal	qb_o_mux	: std_logic_vector(MSB_B downto 0) := (others => '0');
  signal	qbcout_o_mux	: std_logic_vector(MSB_BCOUT downto 0) := (others => '0');

  signal	qc_o_reg        : std_logic_vector(MSB_C downto 0) := (others => '0');
  signal	qc_o_mux	: std_logic_vector(MSB_C downto 0) := (others => '0');

  signal	mult_o_int	: std_logic_vector((MSB_A_MULT + MSB_B_MULT + 1) downto 0) := (others => '0');
  signal	mult_o_reg	: std_logic_vector((MSB_A_MULT + MSB_B_MULT + 1) downto 0) := (others => '0');
  signal	mult_o_mux	: std_logic_vector((MSB_A_MULT + MSB_B_MULT + 1) downto 0) := (others => '0');

  signal	opmode_o_reg	: std_logic_vector(MSB_OPMODE downto 0) := (others => '0');
  signal	opmode_o_mux	: std_logic_vector(MSB_OPMODE downto 0) := (others => '0');

  signal	muxx_o_mux	: std_logic_vector(MSB_P downto 0) := (others => '0');
  signal	muxy_o_mux	: std_logic_vector(MSB_P downto 0) := (others => '0');
  signal	muxz_o_mux	: std_logic_vector(MSB_P downto 0) := (others => '0');

  signal	carryinsel_o_reg	: std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0');
  signal	carryinsel_o_mux	: std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0');

  signal	qcarryin_o_reg0	: std_logic := '0';
  signal	carryin_o_mux0	: std_logic := '0';
  signal	qcarryin_o_reg7	: std_logic := '0';
  signal	carryin_o_mux7	: std_logic := '0';

  signal	carryin_o_mux	: std_logic := '0';

  signal	qp_o_reg	: std_logic_vector(MSB_P downto 0) := (others => '0');
  signal	qp_o_mux	: std_logic_vector(MSB_P downto 0) := (others => '0');

  signal	reg_p_int       : std_logic_vector(47 downto 0) := (others => '0');
  signal	p_o_int         : std_logic_vector(47 downto 0) := (others => '0');

  signal	output_x_sig	: std_logic := '0';

  signal	RST_META          : std_logic := '0';

  signal	DefDelay          : time := 10 ps;

  signal	opmode_valid_flg   : boolean := true;
  signal	alumode_valid_flg  : boolean := true;

  signal	AluFunction	: AluFuntionType := INVALID_ALU;

  signal	alumode_o_reg	: std_logic_vector(MSB_ALUMODE downto 0) := (others => '0');
  signal	alumode_o_mux	: std_logic_vector(MSB_ALUMODE downto 0) := (others => '0');

  signal	carrycascout_o  : std_logic := '0';
  signal	carrycascout_o_reg  : std_logic := '0';
  signal	carrycascout_o_mux  : std_logic := '0';
  signal	carryout_o	: std_logic_vector(MSB_CARRYOUT downto 0) := (others => '0');
  signal	carryout_o_reg	: std_logic_vector(MSB_CARRYOUT downto 0) := (others => '0');
  signal	carryout_o_mux	: std_logic_vector(MSB_CARRYOUT downto 0) := (others => '0');
  signal        carryout_x_o    : std_logic_vector(MSB_CARRYOUT downto 0) := (others => 'X');
  signal	overflow_o      : std_logic := '0';
  signal	pdetb_o         : std_logic := '0';
  signal	pdetb_o_reg1    : std_logic := '0';
  signal	pdetb_o_reg2    : std_logic := '0';
  signal	pdet_o          : std_logic := '0';
  signal	pdet_o_reg1     : std_logic := '0';
  signal	pdet_o_reg2     : std_logic := '0';
  signal	underflow_o     : std_logic := '0';

  signal	alu_o		: std_logic_vector(MSB_P downto 0) := (others => '0');
  signal	pattern_qp	: std_logic_vector(MSB_P downto 0) := (others => '0');
  signal	mask_qp		: std_logic_vector(MSB_P downto 0) := (others => '0');

  signal        multsignout_o_reg : std_logic;
  signal        multsignout_o_mux : std_logic;
  signal        multsignout_o_opmode : std_logic;

  signal	OPMODE_NUMBER	: integer		:= -1;

  signal	ping_opmode_drc_check : std_logic := '0';

begin

  ---------------------
  --  INPUT PATH DELAYs
  ---------------------

  A_dly          	 <= A              	after 0 ps;
  ACIN_dly       	 <= ACIN           	after 0 ps;
  ALUMODE_dly    	 <= ALUMODE        	after 0 ps;
  B_dly          	 <= B              	after 0 ps;
  BCIN_dly       	 <= BCIN           	after 0 ps;
  C_dly          	 <= C              	after 0 ps;
  CARRYCASCIN_dly	 <= CARRYCASCIN    	after 0 ps;
  CARRYIN_dly    	 <= CARRYIN        	after 0 ps;
  CARRYINSEL_dly 	 <= CARRYINSEL     	after 0 ps;
  CEA1_dly       	 <= CEA1           	after 0 ps;
  CEA2_dly       	 <= CEA2           	after 0 ps;
  CEALUMODE_dly  	 <= CEALUMODE      	after 0 ps;
  CEB1_dly       	 <= CEB1           	after 0 ps;
  CEB2_dly       	 <= CEB2           	after 0 ps;
  CEC_dly        	 <= CEC            	after 0 ps;
  CECARRYIN_dly  	 <= CECARRYIN      	after 0 ps;
  CECTRL_dly     	 <= CECTRL         	after 0 ps;
  CEM_dly        	 <= CEM            	after 0 ps;
  CEMULTCARRYIN_dly	 <= CEMULTCARRYIN  	after 0 ps;
  CEP_dly        	 <= CEP            	after 0 ps;
  CLK_dly        	 <= CLK            	after 0 ps;
  MULTSIGNIN_dly 	 <= MULTSIGNIN     	after 0 ps;
  OPMODE_dly     	 <= OPMODE         	after 0 ps;
  PCIN_dly       	 <= PCIN           	after 0 ps;
  RSTA_dly       	 <= RSTA           	after 0 ps;
  RSTALLCARRYIN_dly	 <= RSTALLCARRYIN  	after 0 ps;
  RSTALUMODE_dly 	 <= RSTALUMODE     	after 0 ps;
  RSTB_dly       	 <= RSTB           	after 0 ps;
  RSTC_dly       	 <= RSTC           	after 0 ps;
  RSTCTRL_dly    	 <= RSTCTRL        	after 0 ps;
  RSTM_dly       	 <= RSTM           	after 0 ps;
  RSTP_dly       	 <= RSTP           	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

standard_model : if (SIM_MODE = "SAFE") generate 
--####################################################################
--#####                        Initialization                      ###
--####################################################################
 prcs_init:process
  begin

----------- Checks for AREG ----------------------
    case AREG is
      when 0|1|2 =>
      when others =>
         assert false
         report "Attribute Syntax Error: The allowed values for AREG are 0 or 1 or 2"
         severity Failure;
    end case;

----------- Checks for ACASCREG and (ACASCREG vs AREG) ----------------------
      
    case AREG is
      when 0 => if(AREG /= ACASCREG) then
              assert false
              report "Attribute Syntax Error : The attribute ACASCREG on DSP48E has to be set to 0 when attribute AREG = 0."
              severity Failure;
           end if;
      when 1 => if(AREG /= ACASCREG) then
              assert false
              report "Attribute Syntax Error : The attribute ACASCREG on DSP48E has to be set to 1 when attribute AREG = 1."
              severity Failure;
           end if;
      when 2 => if((AREG /= ACASCREG) and ((AREG-1) /= ACASCREG))then
              assert false
              report "Attribute Syntax Error : The attribute ACASCREG on DSP48E has to be set to either 2 or 1 when attribute AREG = 2."
              severity Failure;
           end if;
      when others => null;
    end case;

----------- Checks for BREG ----------------------
    case BREG is
      when 0|1|2 =>
      when others =>
         assert false
         report "Attribute Syntax Error: The allowed values for BREG are 0 or 1 or 2"
         severity Failure;
    end case;

----------- Checks for BCASCREG and (BCASCREG vs BREG) ----------------------

    case BREG is
      when 0 => if(BREG /= BCASCREG) then
              assert false
              report "Attribute Syntax Error : The attribute BCASCREG on DSP48E has to be set to 0 when attribute BREG = 0."
              severity Failure;
           end if;
      when 1 => if(BREG /= BCASCREG) then
              assert false
              report "Attribute Syntax Error : The attribute BCASCREG on DSP48E has to be set to 1 when attribute BREG = 1."
              severity Failure;
           end if;
      when 2 => if((BREG /= BCASCREG) and ((BREG-1) /= BCASCREG))then
              assert false
              report "Attribute Syntax Error : The attribute BCASCREG on DSP48E has to be set to either 2 or 1 when attribute BREG = 2."
              severity Failure;
           end if;
      when others => null;
    end case;

----------- Check for AUTORESET_OVER_UNDER_FLOW ----------------------

--   case AUTORESET_OVER_UNDER_FLOW is
--      when true | false => null;
--      when others =>
--         assert false
--         report "Attribute Syntax Error: The allowed values for AUTORESET_OVER_UNDER_FLOW are true or fasle"
--         severity Failure;
--    end case;
         
----------- Check for AUTORESET_PATTERN_DETECT ----------------------

    case AUTORESET_PATTERN_DETECT is
      when true | false => null;
      when others =>
         assert false
         report "Attribute Syntax Error: The allowed values for AUTORESET_PATTERN_DETECT are true or fasle"
         severity Failure;
    end case;
         
----------- Check for AUTORESET_PATTERN_DETECT_OPTINV ----------------------

    if((AUTORESET_PATTERN_DETECT_OPTINV /="MATCH") and (AUTORESET_PATTERN_DETECT_OPTINV /="NOT_MATCH")) then
        assert false
        report "Attribute Syntax Error: The allowed values for AUTORESET_PATTERN_DETECT_OPTINV are MATCH or NOT_MATCH."
        severity Failure;
    end if;

----------- Check for USE_MULT ----------------------

     if((USE_MULT /="NONE") and (USE_MULT /="MULT") and
        (USE_MULT /="MULT_S")) then
        assert false
        report "Attribute Syntax Error: The allowed values for USE_MULT are NONE, MULT or MULT_S."
        severity Failure;
     elsif((USE_MULT ="MULT") and (MREG /= 0)) then
        assert false
        report "Attribute Syntax Error: The attribute USE_MULT on DSP48 is set to MULT. This requires attribute MREG to be set to 0."
        severity Failure;
     elsif((USE_MULT ="MULT_S") and (MREG /= 1)) then
        assert false
        report "Attribute Syntax Error: The attribute USE_MULT on DSP48 is set to MULT_S. This requires attribute MREG to be set to 1."
        severity Failure;
     end if;

----------- Check for USE_PATTERN_DETECT ----------------------

    if((USE_PATTERN_DETECT /="PATDET") and (USE_PATTERN_DETECT /="NO_PATDET")) then
        assert false
        report "Attribute Syntax Error: The allowed values for USE_PATTERN_DETECT are PATDET or NO_PATDET."
        severity Failure;
    end if;

--*********************************************************
--*** ADDITIONAL DRC
--*********************************************************
-- CR 219407  --  (1)
    if((AUTORESET_PATTERN_DETECT = TRUE) and (USE_PATTERN_DETECT = "NO_PATDET")) then
        assert false
        report "Attribute Syntax Error : The attribute USE_PATTERN_DETECT on DSP48E instance must be set to PATDET in order to use AUTORESET_PATTERN_DETECT equals TRUE. Failure to do so could make timing reports inaccurate. "
        severity Warning;
    end if;
------------------------------------------------------------
    ping_opmode_drc_check   <= '1' after 100010 ps;
------------------------------------------------------------

    wait;
  end process prcs_init;
--####################################################################
--#####    Input Register A with two levels of registers and a mux ###
--####################################################################
  prcs_a_in:process(A_dly, ACIN_dly)
  begin
     if(A_INPUT ="DIRECT") then
        a_o_mux <= A_dly;
     elsif(A_INPUT ="CASCADE") then
        a_o_mux <= ACIN_dly;
     else
        assert false
        report "Attribute Syntax Error: The allowed values for A_INPUT are DIRECT or CASCADE."
        severity Failure;
     end if;
  end process prcs_a_in;
------------------------------------------------------------------
  prcs_qa_2lvl:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
          qa_o_reg1 <= ( others => '0');
          qa_o_reg2 <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTA_dly = '1') then
               qa_o_reg1 <= ( others => '0');
               qa_o_reg2 <= ( others => '0');
            elsif (RSTA_dly = '0') then
               case AREG is
                    when 1 =>
                       if(CEA2_dly = '1') then
                          qa_o_reg2 <= a_o_mux;
                       end if;
                    when 2 =>
                       if(CEA1_dly = '1') then
                          qa_o_reg1 <= a_o_mux;
                       end if;
                       if(CEA2_dly = '1') then
                          qa_o_reg2 <= qa_o_reg1;
                       end if;
                    when others => null;
               end case;
            end if;
         end if;
      end if;
  end process prcs_qa_2lvl;
------------------------------------------------------------------
  prcs_qa_o_mux:process(a_o_mux, qa_o_reg2)
  begin
     case AREG is
       when 0   => qa_o_mux <= a_o_mux;
       when 1|2 => qa_o_mux <= qa_o_reg2;
       when others =>
            assert false
            report "Attribute Syntax Error: The allowed values for AREG are 0 or 1 or 2"
            severity Failure;
     end case;
  end process prcs_qa_o_mux;
------------------------------------------------------------------
  prcs_qacout_o_mux:process(qa_o_mux, qa_o_reg1)
  begin
     case ACASCREG is
       when 1 => case AREG is
                   when 2 => qacout_o_mux <= qa_o_reg1;
                   when others =>  qacout_o_mux <= qa_o_mux;
                 end case;
       when others =>  qacout_o_mux <= qa_o_mux;
     end case;

  end process prcs_qacout_o_mux;
--####################################################################
--#####    Input Register B with two levels of registers and a mux ###
--####################################################################
 prcs_b_in:process(B_dly, BCIN_dly)
  begin
     if(B_INPUT ="DIRECT") then
        b_o_mux <= B_dly;
     elsif(B_INPUT ="CASCADE") then
        b_o_mux <= BCIN_dly;
     else
        assert false
        report "Attribute Syntax Error: The allowed values for B_INPUT are DIRECT or CASCADE."
        severity Failure;
     end if;
     
  end process prcs_b_in;
------------------------------------------------------------------
 prcs_qb_2lvl:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
          qb_o_reg1 <= ( others => '0');
          qb_o_reg2 <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTB_dly = '1') then
               qb_o_reg1 <= ( others => '0');
               qb_o_reg2 <= ( others => '0');
            elsif (RSTB_dly = '0') then
               case BREG is
                    when 1 =>
                       if(CEB2_dly = '1') then
                          qb_o_reg2 <= b_o_mux;
                       end if;
                    when 2 =>
                       if(CEB1_dly = '1') then
                          qb_o_reg1 <= b_o_mux;
                       end if;
                       if(CEB2_dly = '1') then
                          qb_o_reg2 <= qb_o_reg1;
                       end if;
                    when others => null;
               end case;
            end if;
         end if;
      end if;
  end process prcs_qb_2lvl;
------------------------------------------------------------------
  prcs_qb_o_mux:process(b_o_mux, qb_o_reg2)
  begin
     case BREG is
       when 0   => qb_o_mux <= b_o_mux;
       when 1|2 => qb_o_mux <= qb_o_reg2;
       when others =>
            assert false
            report "Attribute Syntax Error: The allowed values for BREG are 0 or 1 or 2 "
            severity Failure;
     end case;

  end process prcs_qb_o_mux;
------------------------------------------------------------------
  prcs_qbcout_o_mux:process(qb_o_mux, qb_o_reg1)
  begin
     case BCASCREG is
       when 1 => case BREG is
                   when 2 => qbcout_o_mux <= qb_o_reg1;
                   when others =>  qbcout_o_mux <= qb_o_mux;
                 end case;
       when others =>  qbcout_o_mux <= qb_o_mux;
     end case;
  end process prcs_qbcout_o_mux;

--####################################################################
--#####    Input Register C with 0, 1, level of registers        #####
--####################################################################
  prcs_qc_1lvl:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         qc_o_reg <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTC_dly = '1') then
               qc_o_reg <= ( others => '0');
            elsif ((RSTC_dly = '0') and (CEC_dly = '1')) then
               qc_o_reg <= C_dly;
            end if;
         end if;
      end if;
  end process prcs_qc_1lvl;
------------------------------------------------------------------
  prcs_qc_o_mux:process(C_dly, qc_o_reg)
  begin
     case CREG is
      when 0 => qc_o_mux <= C_dly;
      when 1 => qc_o_mux <= qc_o_reg;
      when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for CREG are 0 or 1"
           severity Failure;
      end case;
  end process prcs_qc_o_mux;

--####################################################################
--###################      25x18 Multiplier     ######################
--####################################################################
--
-- 05/26/05 -- FP -- Added warning for invalid mult when USE_MULT=NONE
-- SIMD=FOUR12 and SIMD=TWO24
-- Made mult_o to be "X"
--
  prcs_mult:process(qa_o_mux, qb_o_mux)
  begin
     if(USE_MULT /= "NONE") then
        mult_o_int <=  qa_o_mux(MSB_A_MULT downto 0) * qb_o_mux (MSB_B_MULT downto 0);
     end if;
  end process prcs_mult;
------------------------------------------------------------------
  prcs_mult_reg:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         mult_o_reg <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTM_dly = '1') then
               mult_o_reg <= ( others => '0');
            elsif ((RSTM_dly = '0') and (CEM_dly = '1')) then
               mult_o_reg <= mult_o_int;
            end if;
         end if;
      end if;
  end process prcs_mult_reg;
------------------------------------------------------------------
  prcs_mult_mux:process(mult_o_reg, mult_o_int)
  begin
     case MREG is
      when 0 => mult_o_mux <= mult_o_int;
      when 1 => mult_o_mux <= mult_o_reg;
      when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for MREG are 0 or 1"
           severity Failure;
      end case;
  end process prcs_mult_mux;

--####################################################################
--#####                        OpMode                            #####
--####################################################################
  prcs_opmode_reg:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         opmode_o_reg <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTCTRL_dly = '1') then
               opmode_o_reg <= ( others => '0');
            elsif ((RSTCTRL_dly = '0') and (CECTRL_dly = '1')) then
               opmode_o_reg <= OPMODE_dly;
            end if;
         end if;
      end if;
  end process prcs_opmode_reg;
------------------------------------------------------------------
  prcs_opmode_mux:process(opmode_o_reg, OPMODE_dly)
  begin
     case OPMODEREG is
      when 0 => opmode_o_mux <= OPMODE_dly;
      when 1 => opmode_o_mux <= opmode_o_reg;
      when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for OPMODEREG are 0 or 1"
           severity Failure;
      end case;
  end process prcs_opmode_mux;
--####################################################################
--#####                        MUX_XYZ                           #####
--####################################################################
  prcs_mux_xyz:process(opmode_o_mux, qp_o_mux, qa_o_mux, qb_o_mux, mult_o_mux, 
                       qc_o_mux, PCIN_dly, output_x_sig)
  begin
    if(output_x_sig = '1') then
      muxx_o_mux(MSB_P downto 0) <= ( others => 'X');
      muxy_o_mux(MSB_P downto 0) <= ( others => 'X');
      muxz_o_mux(MSB_P downto 0) <= ( others => 'X');
    elsif(output_x_sig = '0') then
    --MUX_X -----
       case opmode_o_mux(1 downto 0) is
         when "00" => muxx_o_mux <= ( others => '0');
         -- FP ?? sign extend needed from 43rd bit to 48th bit 
         when "01" => muxx_o_mux((MSB_A_MULT + MSB_B_MULT +1) downto 0) <= mult_o_mux;
                   if(mult_o_mux(MSB_A_MULT + MSB_B_MULT + 1) = '1') then
                     muxx_o_mux(MSB_PCIN downto (MAX_A_MULT + MAX_B_MULT)) <=  ( others => '1');
                   elsif (mult_o_mux(MSB_A_MULT + MSB_B_MULT + 1) = '0') then
                     muxx_o_mux(MSB_PCIN downto (MAX_A_MULT + MAX_B_MULT)) <=  ( others => '0');
                   end if;
         when "10" => muxx_o_mux <= qp_o_mux;

-- CR 438456  & CR 448147 & CR 451453
         when "11" => if((USE_MULT = "MULT_S") and (AREG=0 or BREG=0)) then 
                          muxx_o_mux(MSB_P downto 0) <=  ( others => 'X');  
                          assert false
                          report "DRC warning: When attribute USE_MULT on DSP48E instance %m is set to MULT_S, the A:B opmode selection is not permitted when AREG or BREG=0. If the multiplier is not used, set USE_MULT = NONE. For dynamic switching between multiply and add operation, set AREG and BREG=1 or MREG=0 and USE_MULT=MULT."
                          severity Warning;
                      else
                          muxx_o_mux(MSB_P downto 0)  <= (qa_o_mux & qb_o_mux);
                      end if;

         when others => null;
       end case;

    --MUX_Y -----
       case opmode_o_mux(3 downto 2) is
         when "00" => muxy_o_mux <= ( others => '0');
         when "01" => muxy_o_mux <= ( others => '0');
         when "10" => 
                     if(opmode_o_mux(6 downto 4) = "100") then
                        muxy_o_mux <= ( others => MULTSIGNIN_dly);
                     else
                        muxy_o_mux <= ( others => '1');
                     end if;
         when "11" => muxy_o_mux <= qc_o_mux;
         when others => null;
       end case;
    --MUX_Z -----
       case opmode_o_mux(6 downto 4) is
         when "000" => muxz_o_mux <= ( others => '0');
         when "001" => muxz_o_mux <= PCIN_dly;
         when "010" => muxz_o_mux <= qp_o_mux;
         when "011" => muxz_o_mux <= qc_o_mux;
         when "100" => muxz_o_mux <= qp_o_mux; -- Used for MACC extend -- multsignin
      -- FP ?? better shift possible ?
         when "101" => if(PCIN_dly(MSB_PCIN) = '0') then
                         muxz_o_mux  <= ( others => '0');
                       elsif(PCIN_dly(MSB_PCIN) = '1') then
                         muxz_o_mux  <= ( others => '1');
                       end if;
                       muxz_o_mux ((MSB_PCIN - SHIFT_MUXZ) downto 0) <= PCIN_dly(MSB_PCIN downto SHIFT_MUXZ ); 
         when "110" => if(qp_o_mux(MSB_P) = '0') then
                         muxz_o_mux  <= ( others => '0');
                       elsif(qp_o_mux(MSB_P) = '1') then
                         muxz_o_mux  <= ( others => '1');
                       end if;
                       muxz_o_mux ((MSB_P - SHIFT_MUXZ) downto 0) <= qp_o_mux(MSB_P downto SHIFT_MUXZ ); 
                      
         when "111" => null;
         when others => null;
       end case;
    end if;
  end process prcs_mux_xyz;
--####################################################################
--#####                        Alumode                          #####
--####################################################################
  prcs_alumode_reg:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         alumode_o_reg <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTALUMODE_dly = '1') then
               alumode_o_reg <= ( others => '0');
            elsif ((RSTALUMODE_dly = '0') and (CEALUMODE_dly = '1'))then
               alumode_o_reg <= ALUMODE_dly;
            end if;
         end if;
      end if;
  end process prcs_alumode_reg;
------------------------------------------------------------------
  prcs_alumode_mux:process(alumode_o_reg, ALUMODE_dly)
  begin
     case ALUMODEREG is
      when 0 => alumode_o_mux <= ALUMODE_dly;
      when 1 => alumode_o_mux <= alumode_o_reg;
      when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for ALUMODEREG are 0 or 1"
           severity Failure;
      end case;
  end process prcs_alumode_mux;

--####################################################################
--#####                     CarryInSel                           #####
--####################################################################
  prcs_carryinsel_reg:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         carryinsel_o_reg <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTCTRL_dly = '1') then
               carryinsel_o_reg <= ( others => '0');
            elsif ((RSTCTRL_dly = '0') and (CECTRL_dly = '1')) then
               carryinsel_o_reg <= CARRYINSEL_dly;
            end if;
         end if;
      end if;
  end process prcs_carryinsel_reg;
------------------------------------------------------------------
  prcs_carryinsel_mux:process(carryinsel_o_reg, CARRYINSEL_dly)
  begin
     case CARRYINSELREG is
       when 0 => carryinsel_o_mux <= CARRYINSEL_dly;
       when 1 => carryinsel_o_mux <= carryinsel_o_reg;
       when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for CARRYINSELREG are 0 or 1"
           severity Failure;
     end case;
  end process prcs_carryinsel_mux;

------------------------------------------------------------------
-- CR 219047 (3)

  prcs_carryinsel_drc:process(carryinsel_o_mux, MULTSIGNIN_dly, opmode_o_mux)
  begin
     if(carryinsel_o_mux = "010") then
        if(not((MULTSIGNIN_dly = 'X') or ((opmode_o_mux = "1001000") and (MULTSIGNIN_dly /= 'X')) 
                                 or ((MULTSIGNIN_dly = '0') and (CARRYCASCIN_dly = '0')))) then
           assert false
-- CR 451178 -- DRC warning Enhancement
           report "DRC warning : CARRYCASCIN can only be used in the current DSP48E instance if the previous DSP48E  is performing a two input ADD operation, or the current DSP48E is configured in the MAC extend opmode(6:0) equals 1001000. This warning can be also triggered if OPMODEREG is set to 1 and CARRYINSELREG is set to 0 - in which case please set CARRYINSELREG to 1."
           severity Warning;
        end if;
     end if;
  end process prcs_carryinsel_drc;

-- CR 219047 (4)
  prcs_carryinsel_mac_drc:process(carryinsel_o_mux)
  begin
     if((carryinsel_o_mux = "110")  and (MULTCARRYINREG /= MREG)) then
        assert false
        report "Attribute Syntax Warning : It is recommended that MREG and MULTCARRYINREG on DSP48E instance be set to the same value when using CARRYINSEL = 110 for multiply rounding. "
        severity Warning;
     end if;
  end process prcs_carryinsel_mac_drc;


--####################################################################
--#####                       CarryIn                            #####
--####################################################################

-------  input 0

  prcs_carryin_reg0:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         qcarryin_o_reg0 <= '0';
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTALLCARRYIN_dly = '1') then
               qcarryin_o_reg0 <= '0';
            elsif((RSTALLCARRYIN_dly = '0') and (CECARRYIN_dly = '1')) then
               qcarryin_o_reg0 <= CARRYIN_dly;
            end if;
         end if;
      end if;
  end process prcs_carryin_reg0;

  prcs_carryin_mux0:process(qcarryin_o_reg0, CARRYIN_dly)
  begin
     case CARRYINREG is
       when 0 => carryin_o_mux0 <= CARRYIN_dly;
       when 1 => carryin_o_mux0 <= qcarryin_o_reg0;
       when others =>
            assert false
            report "Attribute Syntax Error: The allowed values for CARRYINREG are 0 or 1"
            severity Failure;
     end case;
  end process prcs_carryin_mux0;

------------------------------------------------------------------
-------  input 7

  prcs_carryin_reg7:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         qcarryin_o_reg7 <= '0';
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTALLCARRYIN_dly = '1') then
               qcarryin_o_reg7 <= '0';
            elsif((RSTALLCARRYIN_dly = '0') and (CEMULTCARRYIN_dly = '1')) then
               qcarryin_o_reg7 <= qa_o_mux(24) XNOR qb_o_mux(17);
            end if;
         end if;
      end if;
  end process prcs_carryin_reg7;

  prcs_carryin_mux7:process(qa_o_mux(24), qb_o_mux(17), qcarryin_o_reg7)
  begin
     case MULTCARRYINREG is
       when 0 => carryin_o_mux7 <= qa_o_mux(24) XNOR qb_o_mux(17);
-- CR 232187
       when 1 => carryin_o_mux7 <= qcarryin_o_reg7;
       when others =>
            assert false
            report "Attribute Syntax Error: The allowed values for MULTCARRYINREG are 0 or 1"
            severity Failure;
     end case;
  end process prcs_carryin_mux7;

------------------------------------------------------------------
-- FP Check this with VV 
------------------------------------------------------------------
-- 
  prcs_carryin_mux:process(carryin_o_mux0, PCIN_dly(47), CARRYCASCIN_dly, carrycascout_o_mux, qp_o_mux(47), carryin_o_mux7, carryinsel_o_mux)
  begin
     case carryinsel_o_mux is
       when "000" => carryin_o_mux  <= carryin_o_mux0;
       when "001" => carryin_o_mux  <= NOT PCIN_dly(47);
       when "010" => carryin_o_mux  <= CARRYCASCIN_dly;
       when "011" => carryin_o_mux  <= PCIN_dly(47);
       when "100" => carryin_o_mux  <= carrycascout_o_mux;
       when "101" => carryin_o_mux  <= NOT qp_o_mux(47);
       when "110" => carryin_o_mux  <= carryin_o_mux7;
       when "111" => carryin_o_mux  <= qp_o_mux(47);
       when others => null;
     end case;
  end process prcs_carryin_mux;
--####################################################################
--#####                         ALU                              #####
--####################################################################
  prcs_alu:process(muxx_o_mux, muxy_o_mux, muxz_o_mux, alumode_o_mux, opmode_o_mux, carryin_o_mux, output_x_sig)

  variable opmode_alu_var : std_logic_vector(5 downto 0) := (others => '0');
  variable alu_full_tmp   : std_logic_vector(MAX_ALU_FULL downto 0) := (others => '0');
  variable alu_hlf1_tmp, alu_hlf2_tmp  : std_logic_vector(MAX_ALU_HALF downto 0) := (others => '0');
  variable alu_qrt1_tmp, alu_qrt2_tmp, alu_qrt3_tmp, alu_qrt4_tmp : std_logic_vector(MAX_ALU_QUART downto 0) := (others => '0');

  begin
     if(output_x_sig = '1') then
       alu_o <= (others => 'X');

     elsif(opmode_valid_flg) then
        opmode_alu_var := opmode_o_mux(3 downto 2) & alumode_o_mux;
        case opmode_alu_var is
           ---------------------------------
           ------------- ADD ---------------
           ---------------------------------
           when "000000" | "010000" | "100000" | "110000" => 

               AluFunction <= ADD_ALU;
               alumode_valid_flg <= true;

               if((USE_SIMD = "ONE48") or (USE_SIMD = "one48")) then
                  alu_full_tmp := (('0'&muxz_o_mux) + 
                                   ('0'&muxx_o_mux) + 
                                   ('0'&muxy_o_mux) + carryin_o_mux); 
                  alu_o <= alu_full_tmp(MSB_ALU_FULL downto 0);

                  carrycascout_o               <=  alu_full_tmp(MAX_ALU_FULL);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  alu_full_tmp(MAX_ALU_FULL);
                     carryout_o(MSB_CARRYOUT - 1) <=  'X';
                     carryout_o(MSB_CARRYOUT - 2) <=  'X';
                     carryout_o(MSB_CARRYOUT - 3) <=  'X';
                  end if;

               elsif((USE_SIMD = "TWO24") or (USE_SIMD = "two24")) then
                  alu_hlf1_tmp := (('0'&muxz_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  ('0'&muxx_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  ('0'&muxy_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  carryin_o_mux);
                  alu_hlf2_tmp := (('0'&muxz_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) +
                                  ('0'&muxx_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) +
                                  ('0'&muxy_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF)))); 
                  alu_o <= (alu_hlf2_tmp(MSB_ALU_HALF downto 0) & alu_hlf1_tmp(MSB_ALU_HALF downto 0)) ;

                  carrycascout_o               <=  alu_hlf2_tmp(MAX_ALU_HALF);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  alu_hlf2_tmp(MAX_ALU_HALF);
                     carryout_o(MSB_CARRYOUT - 1) <=  'X';
                     carryout_o(MSB_CARRYOUT - 2) <=  alu_hlf1_tmp(MAX_ALU_HALF);
                     carryout_o(MSB_CARRYOUT - 3) <=  'X';
                  end if;

               elsif((USE_SIMD = "FOUR12") or (USE_SIMD = "four12")) then
                  alu_qrt1_tmp := (('0'&muxz_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  ('0'&muxx_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  ('0'&muxy_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  carryin_o_mux);
                  alu_qrt2_tmp := (('0'&muxz_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) +
                                  ('0'&muxx_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))));
                  alu_qrt3_tmp := (('0'&muxz_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) +
                                  ('0'&muxx_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))));
                  alu_qrt4_tmp := (('0'&muxz_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) +
                                  ('0'&muxx_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))));

                  alu_o <= (alu_qrt4_tmp(MSB_ALU_QUART downto 0) & alu_qrt3_tmp(MSB_ALU_QUART downto 0) &
                              alu_qrt2_tmp(MSB_ALU_QUART downto 0) & alu_qrt1_tmp(MSB_ALU_QUART downto 0));

                  carrycascout_o               <=  alu_qrt4_tmp(MAX_ALU_QUART);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  alu_qrt4_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 1) <=  alu_qrt3_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 2) <=  alu_qrt2_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 3) <=  alu_qrt1_tmp(MAX_ALU_QUART);
                  end if;

               else
                  assert false
                  report "Attribute Syntax Error: The legal values for USE_SIMD are ONE48 or TWO24 or FOUR12."
                  severity Failure;
               end if;

           ---------------------------------
           ------ SUBTRACT (X + ~Z ) ---- carryin must be 1 ---------------
           ---------------------------------
           when "000001" | "010001" | "100001" | "110001" => 

               AluFunction <= ADD_XY_NOTZ_ALU;
               alumode_valid_flg <= true;

               if((USE_SIMD = "ONE48") or (USE_SIMD = "one48")) then
                  alu_full_tmp := NOT('0'&muxz_o_mux) + 
                                   ('0'&muxx_o_mux) + 
                                   ('0'&muxy_o_mux) + carryin_o_mux; 
                  alu_o <= alu_full_tmp(MSB_ALU_FULL downto 0);

                  carrycascout_o               <=  NOT alu_full_tmp(MAX_ALU_FULL);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  NOT alu_full_tmp(MAX_ALU_FULL);
                     carryout_o(MSB_CARRYOUT - 1) <=  'X';
                     carryout_o(MSB_CARRYOUT - 2) <=  'X';
                     carryout_o(MSB_CARRYOUT - 3) <=  'X';
                  end if;

               elsif((USE_SIMD = "TWO24") or (USE_SIMD = "two24")) then
                  alu_hlf1_tmp := NOT('0'&muxz_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  ('0'&muxx_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  ('0'&muxy_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  carryin_o_mux;
                  alu_hlf2_tmp := NOT('0'&muxz_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) +
                                  ('0'&muxx_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) +
                                  ('0'&muxy_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF)));

                  alu_o <= (alu_hlf2_tmp(MSB_ALU_HALF downto 0) & alu_hlf1_tmp(MSB_ALU_HALF downto 0)) ;

                  carrycascout_o               <=  NOT alu_hlf2_tmp(MAX_ALU_HALF);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  NOT alu_hlf2_tmp(MAX_ALU_HALF);
                     carryout_o(MSB_CARRYOUT - 1) <=  'X';
                     carryout_o(MSB_CARRYOUT - 2) <=  NOT alu_hlf1_tmp(MAX_ALU_HALF);
                     carryout_o(MSB_CARRYOUT - 3) <=  'X';
                  end if;

               elsif((USE_SIMD = "FOUR12") or (USE_SIMD = "four12")) then
                  alu_qrt1_tmp := NOT('0'&muxz_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  ('0'&muxx_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  ('0'&muxy_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  carryin_o_mux;
                  alu_qrt2_tmp := NOT('0'&muxz_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) +
                                  ('0'&muxx_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART)));
                  alu_qrt3_tmp := NOT('0'&muxz_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) +
                                  ('0'&muxx_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART)));
                  alu_qrt4_tmp := NOT('0'&muxz_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) +
                                  ('0'&muxx_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART)));

                  alu_o <= (alu_qrt4_tmp(MSB_ALU_QUART downto 0) & alu_qrt3_tmp(MSB_ALU_QUART downto 0) &
                              alu_qrt2_tmp(MSB_ALU_QUART downto 0) & alu_qrt1_tmp(MSB_ALU_QUART downto 0));

                  carrycascout_o               <=  NOT alu_qrt4_tmp(MAX_ALU_QUART);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  NOT alu_qrt4_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 1) <=  NOT alu_qrt3_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 2) <=  NOT alu_qrt2_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 3) <=  NOT alu_qrt1_tmp(MAX_ALU_QUART);
                  end if;

               else
                  assert false
                  report "Attribute Syntax Error: The legal values for USE_SIMD are ONE48 or TWO24 or FOUR12."
                  severity Failure;
               end if;

           ---------------------------------
           ---------- NOT (X + Y + Z + C) ----------
           ---------------------------------
           when "000010" | "010010" | "100010" | "110010" => 

               AluFunction <= NOT_XYZC_ALU;
               alumode_valid_flg <= true;

               if((USE_SIMD = "ONE48") or (USE_SIMD = "one48")) then
                  alu_full_tmp := NOT((('0'&muxz_o_mux) + 
                                   ('0'&muxx_o_mux) + 
                                   ('0'&muxy_o_mux) + carryin_o_mux)); 

                  alu_o <= alu_full_tmp(MSB_ALU_FULL downto 0);

                  carrycascout_o               <=  NOT alu_full_tmp(MAX_ALU_FULL);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  NOT alu_full_tmp(MAX_ALU_FULL);
                     carryout_o(MSB_CARRYOUT - 1) <=  'X';
                     carryout_o(MSB_CARRYOUT - 2) <=  'X';
                     carryout_o(MSB_CARRYOUT - 3) <=  'X';
                  end if;

               elsif((USE_SIMD = "TWO24") or (USE_SIMD = "two24")) then
                  alu_hlf1_tmp := NOT((('0'&muxz_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  ('0'&muxx_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  ('0'&muxy_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  carryin_o_mux));
                  alu_hlf2_tmp := NOT((('0'&muxz_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) +
                                  ('0'&muxx_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) +
                                  ('0'&muxy_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF)))));

                  alu_o <= (alu_hlf2_tmp(MSB_ALU_HALF downto 0) & alu_hlf1_tmp(MSB_ALU_HALF downto 0)) ;

                  carrycascout_o               <=  NOT alu_hlf2_tmp(MAX_ALU_HALF);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  NOT alu_hlf2_tmp(MAX_ALU_HALF);
                     carryout_o(MSB_CARRYOUT - 1) <=  'X';
                     carryout_o(MSB_CARRYOUT - 2) <=  NOT alu_hlf1_tmp(MAX_ALU_HALF);
                     carryout_o(MSB_CARRYOUT - 3) <=  'X';
                  end if;

               elsif((USE_SIMD = "FOUR12") or (USE_SIMD = "four12")) then
                  alu_qrt1_tmp := NOT((('0'&muxz_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  ('0'&muxx_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  ('0'&muxy_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  carryin_o_mux));
                  alu_qrt2_tmp := NOT((('0'&muxz_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) +
                                  ('0'&muxx_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART)))));
                  alu_qrt3_tmp := NOT((('0'&muxz_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) +
                                  ('0'&muxx_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART)))));
                  alu_qrt4_tmp := NOT((('0'&muxz_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) +
                                  ('0'&muxx_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART)))));

                  alu_o <= (alu_qrt4_tmp(MSB_ALU_QUART downto 0) & alu_qrt3_tmp(MSB_ALU_QUART downto 0) &
                              alu_qrt2_tmp(MSB_ALU_QUART downto 0) & alu_qrt1_tmp(MSB_ALU_QUART downto 0));

                  carrycascout_o               <=  NOT alu_qrt4_tmp(MAX_ALU_QUART);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  NOT alu_qrt4_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 1) <=  NOT alu_qrt3_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 2) <=  NOT alu_qrt2_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 3) <=  NOT alu_qrt1_tmp(MAX_ALU_QUART);
                  end if;

               else
                  assert false
                  report "Attribute Syntax Error: The legal values for USE_SIMD are ONE48 or TWO24 or FOUR12."
                  severity Failure;
               end if;

           ---------------------------------
           ------- SUBTRACT (Z - X ) -------
           ---------------------------------
           when "000011" | "010011" | "100011" | "110011"=> 
               AluFunction <= SUBTRACT_ALU;
               alumode_valid_flg <= true;

               if((USE_SIMD = "ONE48") or (USE_SIMD = "one48")) then
                  alu_full_tmp := (('0'&muxz_o_mux) - 
                                   (('0'&muxx_o_mux) + 
                                   ('0'&muxy_o_mux) + carryin_o_mux)); 

                  alu_o <= alu_full_tmp(MSB_ALU_FULL downto 0);

                  carrycascout_o               <=  alu_full_tmp(MAX_ALU_FULL);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  NOT alu_full_tmp(MAX_ALU_FULL);
                     carryout_o(MSB_CARRYOUT - 1) <=  'X';
                     carryout_o(MSB_CARRYOUT - 2) <=  'X';
                     carryout_o(MSB_CARRYOUT - 3) <=  'X';
                  end if;

               elsif((USE_SIMD = "TWO24") or (USE_SIMD = "two24")) then
                  alu_hlf1_tmp := (('0'&muxz_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) -
                                  (('0'&muxx_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  ('0'&muxy_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  carryin_o_mux));
                  alu_hlf2_tmp := (('0'&muxz_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) -
                                  (('0'&muxx_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) +
                                  ('0'&muxy_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF)))));

                  alu_o <= (alu_hlf2_tmp(MSB_ALU_HALF downto 0) & alu_hlf1_tmp(MSB_ALU_HALF downto 0)) ;

                  carrycascout_o               <=  alu_hlf2_tmp(MAX_ALU_HALF);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  NOT alu_hlf2_tmp(MAX_ALU_HALF);
                     carryout_o(MSB_CARRYOUT - 1) <=  'X';
                     carryout_o(MSB_CARRYOUT - 2) <=  NOT alu_hlf1_tmp(MAX_ALU_HALF);
                     carryout_o(MSB_CARRYOUT - 3) <=  'X';
                  end if;

               elsif((USE_SIMD = "FOUR12") or (USE_SIMD = "four12")) then
                  alu_qrt1_tmp := (('0'&muxz_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) -
                                  (('0'&muxx_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  ('0'&muxy_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  carryin_o_mux));
                  alu_qrt2_tmp := (('0'&muxz_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) -
                                  (('0'&muxx_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART)))));
                  alu_qrt3_tmp := (('0'&muxz_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) -
                                  (('0'&muxx_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART)))));
                  alu_qrt4_tmp := (('0'&muxz_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) -
                                  (('0'&muxx_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART)))));

                  alu_o <= (alu_qrt4_tmp(MSB_ALU_QUART downto 0) & alu_qrt3_tmp(MSB_ALU_QUART downto 0) &
                              alu_qrt2_tmp(MSB_ALU_QUART downto 0) & alu_qrt1_tmp(MSB_ALU_QUART downto 0));

                  carrycascout_o               <=  alu_qrt4_tmp(MAX_ALU_QUART);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  NOT alu_qrt4_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 1) <=  NOT alu_qrt3_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 2) <=  NOT alu_qrt2_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 3) <=  NOT alu_qrt1_tmp(MAX_ALU_QUART);
                  end if;

               else
                  assert false
                  report "Attribute Syntax Error: The legal values for USE_SIMD are ONE48 or TWO24 or FOUR12."
                  severity Failure;
               end if;

           ---------------------------------
           ------------- XOR ---------------
           ---------------------------------
           when "000100" | "000111" | "100101" | "100110" =>
                AluFunction <= XOR_ALU;
                alumode_valid_flg <= true;
                alu_o <= muxx_o_mux xor muxz_o_mux; 
                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';

           ---------------------------------
           ------------- XNOR ---------------
           ---------------------------------
           when "000101" | "000110" | "100100" | "100111" =>
                AluFunction <= XNOR_ALU;
                alumode_valid_flg <= true;
                alu_o <= muxx_o_mux xnor muxz_o_mux; 
                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';

           ---------------------------------
           ------------- AND ---------------
           ---------------------------------
           when "001100" =>
                AluFunction <= AND_ALU;
                alumode_valid_flg <= true;
                alu_o <= muxx_o_mux and muxz_o_mux; 
                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';

           ---------------------------------
           --------- X AND (NOT Z) ---------
           ---------------------------------
           when "001101" =>
                AluFunction <= X_AND_NOT_Z_ALU;
                alumode_valid_flg <= true;
                alu_o <= muxx_o_mux and (not muxz_o_mux); 
                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';

           ---------------------------------
           ------------- NAND ---------------
           ---------------------------------
           when "001110" =>
                AluFunction <= NAND_ALU;
                alumode_valid_flg <= true;
                alu_o <= muxx_o_mux nand muxz_o_mux; 
                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';

           ---------------------------------
           -------- - (NOT X) OR Z ---------
           ---------------------------------
           when "001111" =>
                AluFunction <= NOT_X_OR_Z_ALU;
                alumode_valid_flg <= true;
                alu_o <= (not muxx_o_mux) or  muxz_o_mux; 
                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';

           ---------------------------------
           -------------- OR ---------------
           ---------------------------------
           when "101100" =>
                AluFunction <= OR_ALU;
                alumode_valid_flg <= true;
                alu_o <= muxx_o_mux or muxz_o_mux; 
                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';

           ---------------------------------
           --------- X OR (NOT Z) ---------
           ---------------------------------
           when "101101" =>
                AluFunction <= X_OR_NOT_Z_ALU;
                alumode_valid_flg <= true;
                alu_o <= muxx_o_mux or (not muxz_o_mux); 
                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';

           ---------------------------------
           ------------ X NOR Z ------------
           ---------------------------------
           when "101110" =>
                AluFunction <= X_NOR_Z_ALU;
                alumode_valid_flg <= true;
                alu_o <= muxx_o_mux nor  muxz_o_mux; 
                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';

           ---------------------------------
           --------- (NOT X) and Z ---------
           ---------------------------------
           when "101111" =>
                AluFunction <= NOT_X_AND_Z_ALU;
                alumode_valid_flg <= true;
                alu_o <= (not muxx_o_mux) and  muxz_o_mux; 
                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';


           when others => 
                AluFunction <= INVALID_ALU;
                alumode_valid_flg <= false;

                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';

        end case;
    end if;
  end process prcs_alu;
--####################################################################
--#####                CARRYOUT and CARRYCASCOUT                 #####
--####################################################################
  prcs_carry_reg:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         carryout_o_reg     <=  ( others => '0');
         carrycascout_o_reg <=  '0';
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if((RSTP_dly = '1') or 
               ((AUTORESET_PATTERN_DETECT) and (
                ((AUTORESET_PATTERN_DETECT_OPTINV = "MATCH") and pdet_o_reg1 = '1') or 
                ((AUTORESET_PATTERN_DETECT_OPTINV = "NOT_MATCH") and (pdet_o_reg2 = '1' and pdet_o_reg1 = '0')))
               )
              ) then
               carryout_o_reg     <= ( others => '0');
               carrycascout_o_reg <=  '0';
            elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then
               carryout_o_reg <= carryout_o;
               carrycascout_o_reg <= carrycascout_o;
            end if;
         end if;
      end if;
  end process prcs_carry_reg;
------------------------------------------------------------------
  prcs_carryout_mux:process(carryout_o, carryout_o_reg)
  begin
     case PREG is
       when 0 => carryout_o_mux <= carryout_o;
       when 1 => carryout_o_mux <= carryout_o_reg;
       when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for PREG are 0 or 1"
           severity Failure;
     end case;
   
  end process prcs_carryout_mux;

------------------------------------------------------------------
  prcs_carryout_x_o:process(carryout_o_mux)
  begin
     if(USE_SIMD = "ONE48") then
        carryout_x_o(3) <= carryout_o_mux(3);
     elsif(USE_SIMD = "TWO24") then
        carryout_x_o(3) <= carryout_o_mux(3);
        carryout_x_o(1) <= carryout_o_mux(1);
     elsif(USE_SIMD = "FOUR12") then
        carryout_x_o(3) <= carryout_o_mux(3);
        carryout_x_o(2) <= carryout_o_mux(2);
        carryout_x_o(1) <= carryout_o_mux(1);
        carryout_x_o(0) <= carryout_o_mux(0);
     end if;
  end process prcs_carryout_x_o;

------------------------------------------------------------------
  prcs_carrycascout_mux:process(carrycascout_o, carrycascout_o_reg)
  begin
     case PREG is
       when 0 => carrycascout_o_mux <= carrycascout_o;
       when 1 => carrycascout_o_mux <= carrycascout_o_reg;
       when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for PREG are 0 or 1"
           severity Failure;
     end case;
   
  end process prcs_carrycascout_mux;
------------------------------------------------------------------
-- CR 219047 (2)
  prcs_multsignout_o_opmode:process(mult_o_mux(MSB_A_MULT+MSB_B_MULT+1), opmode_o_mux(3 downto 0))
  begin
    if(opmode_o_mux(3 downto 0) = "0101") then
       multsignout_o_opmode <= mult_o_mux(MSB_A_MULT+MSB_B_MULT+1);
    else
       multsignout_o_opmode <= 'X';
    end if;
  end process prcs_multsignout_o_opmode;

  prcs_multsignout_o_mux:process(multsignout_o_opmode, multsignout_o_reg)
  begin
     case PREG is
       when 0 => multsignout_o_mux <= multsignout_o_opmode;
-- CR 232275
       when 1 => multsignout_o_mux <= multsignout_o_reg;
       when others => null;
--           assert false
--           report "Attribute Syntax Error: The allowed values for PREG are 0 or 1"
--           severity Failure;
     end case;
   
  end process prcs_multsignout_o_mux;
--####################################################################
--####################################################################
--####################################################################
--#####                 PCOUT and MULTSIGNOUT                    #####
--####################################################################
  prcs_qp_reg:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         qp_o_reg <=  ( others => '0');
         multsignout_o_reg <= '0';
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if((RSTP_dly = '1') or 
               ((AUTORESET_PATTERN_DETECT) and (
                ((AUTORESET_PATTERN_DETECT_OPTINV = "MATCH") and pdet_o_reg1 = '1') or 
                ((AUTORESET_PATTERN_DETECT_OPTINV = "NOT_MATCH") and (pdet_o_reg2 = '1' and pdet_o_reg1 = '0')))
               )
              ) then
               qp_o_reg <= ( others => '0');
               multsignout_o_reg <= '0';
            elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then
               qp_o_reg <= alu_o;
               multsignout_o_reg <= mult_o_reg((MSB_A_MULT+MSB_B_MULT+1));
            end if;
         end if;
      end if;
  end process prcs_qp_reg;
------------------------------------------------------------------
  prcs_qp_mux:process(alu_o, qp_o_reg)
  begin
     case PREG is
       when 0 => qp_o_mux <= alu_o;
       when 1 => qp_o_mux <= qp_o_reg;
       when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for PREG are 0 or 1"
           severity Failure;
     end case;
   
  end process prcs_qp_mux;
--####################################################################
--#####                    Pattern Detector                      #####
--####################################################################
  prcs_sel_pattern_detect:process(alu_o, qc_o_mux)
  begin

     -- Select the pattern
     if((SEL_PATTERN = "PATTERN") or (SEL_PATTERN = "pattern")) then
         pattern_qp <= To_StdLogicVector(PATTERN);
     elsif((SEL_PATTERN = "C") or (SEL_PATTERN = "c")) then
         pattern_qp <= qc_o_mux;
     else 
         assert false
         report "Attribute Syntax Error: The attribute SEL_PATTERN on DSP48_ALU is incorrect. Legal values for this attribute are PATTERN or C"
         severity Failure;
     end if;

     -- Select the mask  -- if ROUNDING MASK set, use rounding mode, else use SEL_MASK
     if((SEL_ROUNDING_MASK = "SEL_MASK") or (SEL_ROUNDING_MASK = "sel_mask")) then
         if((SEL_MASK = "MASK") or (SEL_MASK = "mask")) then
             mask_qp <= To_StdLogicVector(MASK);
         elsif((SEL_MASK = "C") or (SEL_MASK = "c")) then
             mask_qp <= qc_o_mux;
         else
           assert false
           report "Attribute Syntax Error: The attribute SEL_MASK on DSP48_ALU is incorrect. Legal values for this attribute are MASK or C"
           severity Failure;
         end if;
     elsif((SEL_ROUNDING_MASK = "MODE1") or (SEL_ROUNDING_MASK = "mode1")) then
         mask_qp <=   To_StdLogicVector((To_bitvector( not qc_o_mux)) sla 1) ;
         mask_qp (0) <= '0';
     elsif((SEL_ROUNDING_MASK = "MODE2") or (SEL_ROUNDING_MASK = "mode2")) then
         mask_qp <=   To_StdLogicVector((To_bitvector( not qc_o_mux)) sla 2) ;
         mask_qp (1 downto 0) <= (others => '0');
     else
         assert false
         report "Attribute Syntax Error: The attribute SEL_ROUNDING_MASK on DSP48_ALU is incorrect. Legal values for this attribute are SEL_MASK or MODE1 or MODE2."
         severity Failure;
     end if;
     
  end process prcs_sel_pattern_detect;


---------------------------------------------------------------

  prcs_pdet:process(alu_o, mask_qp, pattern_qp, GSR_dly )
  begin
       if(((alu_o or mask_qp) = (pattern_qp or mask_qp)) and (GSR_dly = '0'))then 
          pdet_o <= '1';
       else
          pdet_o <= '0';
       end if;

       if(((alu_o or mask_qp) = ((NOT pattern_qp) or mask_qp)) and (GSR_dly = '0')) then 
          pdetb_o <= '1';
       else
          pdetb_o <= '0';
       end if;

  end process prcs_pdet;

---------------------------------------------------------------

  prcs_pdet_reg:process(CLK_dly, GSR_dly)
  variable pdetb_reg1_var, pdetb_reg2_var, pdet_reg1_var, pdet_reg2_var : std_ulogic := '0';  
  begin
      if(GSR_dly = '1') then
         pdetb_o_reg1 <= '0';
         pdetb_o_reg2 <= '0';
         pdet_o_reg1  <= '0';
         pdet_o_reg2  <= '0';

         pdetb_reg1_var := '0';
         pdetb_reg2_var := '0';
         pdet_reg1_var  := '0';
         pdet_reg2_var  := '0';
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if((RSTP_dly = '1') or 
               ((AUTORESET_PATTERN_DETECT) and (
                ((AUTORESET_PATTERN_DETECT_OPTINV = "MATCH") and pdet_o_reg1 = '1') or 
                ((AUTORESET_PATTERN_DETECT_OPTINV = "NOT_MATCH") and (pdet_o_reg2 = '1' and pdet_o_reg1 = '0')))
               )
              ) then
               pdetb_o_reg1 <= '0';
               pdetb_o_reg2 <= '0';
               pdet_o_reg1  <= '0';
               pdet_o_reg2  <= '0';

               pdetb_reg1_var := '0';
               pdetb_reg2_var := '0';
               pdet_reg1_var  := '0';
               pdet_reg2_var  := '0';
            elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then
               pdetb_reg2_var := pdetb_reg1_var;
               pdetb_reg1_var := pdetb_o;

               pdet_reg2_var := pdet_reg1_var;
               pdet_reg1_var := pdet_o;

               pdetb_o_reg1 <= pdetb_reg1_var;
               pdetb_o_reg2 <= pdetb_reg2_var;
               pdet_o_reg1  <= pdet_reg1_var;
               pdet_o_reg2  <= pdet_reg2_var;

            end if;
         end if;
      end if;
  end process prcs_pdet_reg;

--####################################################################
--#####                 Underflow / Overflow                     #####
--####################################################################
  prcs_uflow_oflow:process(pdet_o_reg1 , pdet_o_reg2 , pdetb_o_reg1 , pdetb_o_reg2)
  begin
--    if(((AUTORESET_PATTERN_DETECT) and (
--       ((AUTORESET_PATTERN_DETECT_OPTINV = "MATCH") and (pdet_o_reg1 = '1'))  or
--       ((AUTORESET_PATTERN_DETECT_OPTINV = "NOT_MATCH") and ((pdet_o_reg2 = '1') and (pdet_o_reg1 = '0'))))
--      )) then
--       underflow_o <= '0';
--       overflow_o  <= '0';
--    else
--       overflow_o  <= pdet_o_reg2   AND  (NOT pdet_o_reg1)  AND  (NOT pdetb_o_reg1);
--       underflow_o <= pdetb_o_reg2  AND  (NOT pdet_o_reg1)  AND (NOT pdetb_o_reg1);
--    end if;
    if(GSR_dly = '1') then
        overflow_o  <= '0';
        underflow_o <= '0';
    elsif(USE_PATTERN_DETECT = "NO_PATDET") then
        overflow_o  <= 'X';
        underflow_o <= 'X';
    elsif(PREG = 0) then
          overflow_o  <= 'X';
          underflow_o <= 'X';
    elsif(PREG = 1) then
          overflow_o  <= pdet_o_reg2   AND  (NOT pdet_o_reg1)  AND  (NOT pdetb_o_reg1);
          underflow_o <= pdetb_o_reg2  AND  (NOT pdet_o_reg1)  AND (NOT pdetb_o_reg1);
    end if;

  end process prcs_uflow_oflow;
--####################################################################
--#####                 OPMODE DRC                               #####
--####################################################################
  prcs_opmode_drc:process(ping_opmode_drc_check, alumode_o_mux, opmode_o_mux, carryinsel_o_mux)
  variable Message : line;
  variable invalid_opmode_flg : boolean := true;
  variable opmode_valid_var : boolean := true;
  variable opmode_carryinsel_var : std_logic_vector(9 downto 0) := (others => '0');
  begin
      opmode_carryinsel_var := opmode_o_mux & carryinsel_o_mux(MSB_CARRYINSEL downto 0);
      case alumode_o_mux(3 downto 2) is
-----------------------------------------
--        ARITHMETIC MODES DRC         --
-----------------------------------------
         when "00" => 
            case opmode_carryinsel_var is
               when "0000000000" => 
                          OPMODE_NUMBER <= 1;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0000010000" => 
                          OPMODE_NUMBER <= 3;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0000010010" => 
                          OPMODE_NUMBER <= 4;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
-- CR 455601 eased the following two 
               when "0000010101" => 
                          OPMODE_NUMBER <= 50;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0000010111" => 
                          OPMODE_NUMBER <= 50;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
--
               when "0000011000" => 
                          OPMODE_NUMBER <= 7;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0000011010" => 
                          OPMODE_NUMBER <= 8;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0000011100" => 
                          OPMODE_NUMBER <= 9;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0000101000" => 
                          OPMODE_NUMBER <= 13;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0001000000" => 
                          OPMODE_NUMBER <= 15;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0001010000" => 
                          OPMODE_NUMBER <= 17;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0001010010" => 
                          OPMODE_NUMBER <= 18;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0001011000" => 
                          OPMODE_NUMBER <= 21;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0001011010" => 
                          OPMODE_NUMBER <= 22;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0001011100" => 
                          OPMODE_NUMBER <= 23;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0001100000" => 
                          OPMODE_NUMBER <= 27;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0001100010" => 
                          OPMODE_NUMBER <= 28;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0001100100" => 
                          OPMODE_NUMBER <= 29;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0001110000" => 
                          OPMODE_NUMBER <= 33;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0001110010" => 
                          OPMODE_NUMBER <= 34;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0001110101" => 
                          OPMODE_NUMBER <= 37;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0001110111" => 
                          OPMODE_NUMBER <= 37;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0001111000" => 
                          OPMODE_NUMBER <= 38;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0001111010" => 
                          OPMODE_NUMBER <= 39;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0001111100" => 
                          OPMODE_NUMBER <= 40;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0010000000" => 
                          OPMODE_NUMBER <= 46;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0010010000" => 
                          OPMODE_NUMBER <= 48;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0010010101" => 
                          OPMODE_NUMBER <= 50;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0010010111" => 
                          OPMODE_NUMBER <= 50;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0010011000" => 
                          OPMODE_NUMBER <= 51;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0010011001" => 
                          OPMODE_NUMBER <= 53;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0010011011" => 
                          OPMODE_NUMBER <= 53;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0010101000" => 
                          OPMODE_NUMBER <= 55;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0010101001" => 
                          OPMODE_NUMBER <= 57;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0010101011" => 
                          OPMODE_NUMBER <= 57;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0010101110" => 
                          OPMODE_NUMBER <= 58;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0011000000" => 
                          OPMODE_NUMBER <= 59;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0011010000" => 
                          OPMODE_NUMBER <= 61;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0011010101" => 
                          OPMODE_NUMBER <= 63;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0011010111" => 
                          OPMODE_NUMBER <= 63;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0011011000" => 
                          OPMODE_NUMBER <= 64;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0011011001" => 
                          OPMODE_NUMBER <= 66;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0011011011" => 
                          OPMODE_NUMBER <= 66;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0011100000" => 
                          OPMODE_NUMBER <= 68;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0011100001" => 
                          OPMODE_NUMBER <= 70;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0011100011" => 
                          OPMODE_NUMBER <= 70;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0011110000" => 
                          OPMODE_NUMBER <= 72;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0011110101" => 
                          OPMODE_NUMBER <= 74;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0011110111" => 
                          OPMODE_NUMBER <= 74;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0011110001" => 
                          OPMODE_NUMBER <= 75;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0011110011" => 
                          OPMODE_NUMBER <= 75;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0011111000" => 
                          OPMODE_NUMBER <= 77;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0011111001" => 
                          OPMODE_NUMBER <= 79;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0011111011" => 
                          OPMODE_NUMBER <= 79;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0100000000" => 
                          OPMODE_NUMBER <= 82;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0100000010" => 
                          OPMODE_NUMBER <= 83;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0100010000" => 
                          OPMODE_NUMBER <= 86;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0100010010" => 
                          OPMODE_NUMBER <= 87;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0100011000" => 
                          OPMODE_NUMBER <= 90;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0100011010" => 
                          OPMODE_NUMBER <= 91;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0100011101" => 
                          OPMODE_NUMBER <= 94;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0100011111" => 
                          OPMODE_NUMBER <= 94;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0100101000" => 
                          OPMODE_NUMBER <= 95;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0100101101" => 
                          OPMODE_NUMBER <= 97;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0100101111" => 
                          OPMODE_NUMBER <= 97;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0101000000" => 
                          OPMODE_NUMBER <= 98;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0101000010" => 
                          OPMODE_NUMBER <= 99;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0101010000" => 
                          OPMODE_NUMBER <= 102;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0101011000" => 
                          OPMODE_NUMBER <= 104;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0101011101" => 
                          OPMODE_NUMBER <= 106;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0101011111" => 
                          OPMODE_NUMBER <= 106;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0101100000" => 
                          OPMODE_NUMBER <= 107;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0101100010" => 
                          OPMODE_NUMBER <= 108;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0101100101" => 
                          OPMODE_NUMBER <= 111;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0101100111" => 
                          OPMODE_NUMBER <= 111;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0101110000" => 
                          OPMODE_NUMBER <= 112;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0101110101" => 
                          OPMODE_NUMBER <= 114;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0101110111" => 
                          OPMODE_NUMBER <= 114;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0101111000" => 
                          OPMODE_NUMBER <= 115;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0101111101" => 
                          OPMODE_NUMBER <= 117;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0101111111" => 
                          OPMODE_NUMBER <= 117;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0110000000" => 
                          OPMODE_NUMBER <= 120;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0110000010" => 
                          OPMODE_NUMBER <= 121;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0110000100" => 
                          OPMODE_NUMBER <= 122;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0110010000" => 
                          OPMODE_NUMBER <= 126;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0110010010" => 
                          OPMODE_NUMBER <= 127;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0110010101" => 
                          OPMODE_NUMBER <= 130;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0110010111" => 
                          OPMODE_NUMBER <= 130;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0110011000" => 
                          OPMODE_NUMBER <= 131;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0110011010" => 
                          OPMODE_NUMBER <= 132;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0110011100" => 
                          OPMODE_NUMBER <= 133;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0110101000" => 
                          OPMODE_NUMBER <= 139;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0110101110" => 
                          OPMODE_NUMBER <= 141;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0111000000" => 
                          OPMODE_NUMBER <= 143;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0111000010" => 
                          OPMODE_NUMBER <= 144;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0111000100" => 
                          OPMODE_NUMBER <= 145;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0111010000" => 
                          OPMODE_NUMBER <= 149;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0111010101" => 
                          OPMODE_NUMBER <= 151;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0111010111" => 
                          OPMODE_NUMBER <= 151;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0111011000" => 
                          OPMODE_NUMBER <= 152;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0111100000" => 
                          OPMODE_NUMBER <= 156;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0111100010" => 
                          OPMODE_NUMBER <= 157;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0111110000" => 
                          OPMODE_NUMBER <= 160;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0111111000" => 
                          OPMODE_NUMBER <= 162;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1001000010" => 
                          OPMODE_NUMBER <= 165;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1010000000" => 
                          OPMODE_NUMBER <= 167;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1010010000" => 
                          OPMODE_NUMBER <= 169;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1010010101" => 
                          OPMODE_NUMBER <= 171;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1010010111" => 
                          OPMODE_NUMBER <= 171;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1010011000" => 
                          OPMODE_NUMBER <= 172;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1010011001" => 
                          OPMODE_NUMBER <= 174;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1010011011" => 
                          OPMODE_NUMBER <= 174;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1010101000" => 
                          OPMODE_NUMBER <= 176;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1010101001" => 
                          OPMODE_NUMBER <= 178;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1010101011" => 
                          OPMODE_NUMBER <= 178;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1010101110" => 
                          OPMODE_NUMBER <= 179;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1011000000" => 
                          OPMODE_NUMBER <= 180;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1011010000" => 
                          OPMODE_NUMBER <= 182;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1011010101" => 
                          OPMODE_NUMBER <= 184;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1011010111" => 
                          OPMODE_NUMBER <= 184;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1011011000" => 
                          OPMODE_NUMBER <= 185;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1011011001" => 
                          OPMODE_NUMBER <= 187;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1011011011" => 
                          OPMODE_NUMBER <= 187;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1011100000" => 
                          OPMODE_NUMBER <= 189;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1011100001" => 
                          OPMODE_NUMBER <= 191;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1011100011" => 
                          OPMODE_NUMBER <= 191;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1011110000" => 
                          OPMODE_NUMBER <= 193;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1011110101" => 
                          OPMODE_NUMBER <= 195;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1011110111" => 
                          OPMODE_NUMBER <= 195;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1011110001" => 
                          OPMODE_NUMBER <= 197;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1011110011" => 
                          OPMODE_NUMBER <= 197;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1011111000" => 
                          OPMODE_NUMBER <= 198;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1011111001" => 
                          OPMODE_NUMBER <= 200;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1011111011" => 
                          OPMODE_NUMBER <= 200;
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1100000000" => 
                          OPMODE_NUMBER <= 203;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1100010000" => 
                          OPMODE_NUMBER <= 205;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1100011000" => 
                          OPMODE_NUMBER <= 207;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1100011101" => 
                          OPMODE_NUMBER <= 209;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1100011111" => 
                          OPMODE_NUMBER <= 209;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1100101000" => 
                          OPMODE_NUMBER <= 210;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1100101101" => 
                          OPMODE_NUMBER <= 212;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1100101111" => 
                          OPMODE_NUMBER <= 212;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1101000000" => 
                          OPMODE_NUMBER <= 213;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1101010000" => 
                          OPMODE_NUMBER <= 215;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1101011000" => 
                          OPMODE_NUMBER <= 217;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1101011101" => 
                          OPMODE_NUMBER <= 219;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1101011111" => 
                          OPMODE_NUMBER <= 219;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1101100000" => 
                          OPMODE_NUMBER <= 220;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1101100101" => 
                          OPMODE_NUMBER <= 222;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1101100111" => 
                          OPMODE_NUMBER <= 222;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1101110000" => 
                          OPMODE_NUMBER <= 223;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1101110101" => 
                          OPMODE_NUMBER <= 225;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1101110111" => 
                          OPMODE_NUMBER <= 225;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1101111000" => 
                          OPMODE_NUMBER <= 226;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1101111101" => 
                          OPMODE_NUMBER <= 228;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1101111111" => 
                          OPMODE_NUMBER <= 228;
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when others    =>
                          OPMODE_NUMBER <= -1;
                          if(invalid_opmode_flg = true) then
                             invalid_opmode_flg := false;
                             opmode_valid_var := false;
                             output_x_sig <= '1';
-- CR 444150
                             if((opmode_carryinsel_var = "0000000010") and ((OPMODEREG = 1) and (CARRYINSELREG = 0))) then
                                Write ( Message, string'("DRC Warning : The attribute CARRYINSELREG on DSP48E instance is set to 0. "));
                                Write ( Message, string'("It is required to have CARRYINSELREG be set to 1 to match OPMODEREG, "));
                                Write ( Message, string'("in order to ensure that the simulation model will match the hardware "));
                                Write ( Message, string'("behavior in all use cases."));
                                assert false report Message.all severity Warning;
                                DEALLOCATE (Message);
                             end if;

                             Write ( Message, string'("OPMODE Input Warning : The OPMODE "));
                             Write ( Message,  slv_to_str(opmode_o_mux));
                             Write ( Message, string'(" to DSP48E instance"));
                             Write ( Message, string'(" is either invalid or the CARRYINSEL "));
                             Write ( Message,  slv_to_str(carryinsel_o_mux));
                             Write ( Message, string'(" for that specific OPMODE is invalid. "));
                             Write ( Message, string'(" This error may be due to mismatch in the OPMODEREG "));
                             Write ( Message, string'(" and CARRYINSELREG attribute settings."));
                             Write ( Message, string'(" It is recommended that OPMODEREG and CARRYINSELREG always be set to the same value."));
                             assert false report Message.all severity Warning;
                             DEALLOCATE (Message);
                           end if;
            end case;
         when "01" | "11" => 
-----------------------------------------
--          LOGIC MODES DRC            --
-----------------------------------------
            case opmode_o_mux is
               when "0000000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0000010" => 
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0000011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0010000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0010010" => 
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0010011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0100000" => 
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0100010" => 
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0100011" => 
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0110000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0110010" => 
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0110011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1010000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1010010" => 
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1010011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1100000" => 
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1100010" => 
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1100011" => 
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0001000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0001010" => 
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0001011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0011000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0011010" => 
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0011011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0101000" => 
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0101010" => 
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0101011" => 
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0111000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "0111010" => 
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "0111011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1011000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1011010" => 
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1011011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "1101000" => 
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1101010" => 
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "1101011" => 
                          if (PREG /= 1) then
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux));
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
                when others    =>
                          OPMODE_NUMBER <= -1;
                          if(invalid_opmode_flg = true) then
                             invalid_opmode_flg := false;
                             opmode_valid_var := false;
                             output_x_sig <= '1';
                             Write ( Message, string'("OPMODE Input Warning : The OPMODE "));
                             Write ( Message,  slv_to_str(opmode_o_mux));
                             Write ( Message, string'(" to DSP48E instance"));
                             Write ( Message, string'(" is invalid for ALU LOGIC modes."));
                             assert false report Message.all severity Warning;
                             DEALLOCATE (Message);
                           end if;
            end case;
         when others => null;
      end case;

      opmode_valid_flg <= opmode_valid_var;

  end process prcs_opmode_drc;
--####################################################################
--#####                   ZERO_DELAY_OUTPUTS                     #####
--####################################################################
  prcs_zero_delay_outputs:process(qacout_o_mux, qbcout_o_mux, carryout_x_o, carrycascout_o_mux,
                                  overflow_o, qp_o_mux, pdet_o, pdetb_o,
                                  pdet_o_reg1, pdetb_o_reg1,
                                  pdet_o_reg2, pdetb_o_reg2,
                                  underflow_o, multsignout_o_mux, opmode_valid_flg, alumode_valid_flg)
  begin
    ACOUT_zd          <= qacout_o_mux;
    BCOUT_zd          <= qbcout_o_mux;
    OVERFLOW_zd       <= overflow_o;
    UNDERFLOW_zd      <= underflow_o;
    P_zd              <= qp_o_mux;
    PCOUT_zd          <= qp_o_mux;
    MULTSIGNOUT_zd    <= multsignout_o_mux;

    if(((AUTORESET_PATTERN_DETECT) and (
       ((AUTORESET_PATTERN_DETECT_OPTINV = "MATCH") and (pdet_o_reg1 = '1'))  or
       ((AUTORESET_PATTERN_DETECT_OPTINV = "NOT_MATCH") and ((pdet_o_reg2 = '1') and (pdet_o_reg1 = '0'))))
      )) then
      CARRYCASCOUT_zd   <= '0';
      CARRYOUT_zd       <= (others => '0');
    else
      CARRYCASCOUT_zd   <= carrycascout_o_mux;   
      CARRYOUT_zd       <= carryout_x_o; 
    end if;

    if((USE_PATTERN_DETECT = "NO_PATDET") or (not opmode_valid_flg) or (not alumode_valid_flg)) then
       PATTERNBDETECT_zd <= 'X';
       PATTERNDETECT_zd  <= 'X';
    elsif (PREG = 0) then
          PATTERNBDETECT_zd <= pdetb_o;
          PATTERNDETECT_zd  <= pdet_o;
    elsif(PREG = 1) then
          PATTERNBDETECT_zd <= pdetb_o_reg1;
          PATTERNDETECT_zd  <= pdet_o_reg1;
    end if;

  end process prcs_zero_delay_outputs;

end generate; 
fast_model : if (SIM_MODE = "FAST") generate 
--####################################################################
--#####                        Initialization                      ###
--####################################################################
 prcs_init:process
  begin

----------- Checks for AREG ----------------------
    case AREG is
      when 0|1|2 =>
      when others =>
         assert false
         report "Attribute Syntax Error: The allowed values for AREG are 0 or 1 or 2"
         severity Failure;
    end case;

----------- Checks for ACASCREG and (ACASCREG vs AREG) ----------------------
      
    case AREG is
      when 0 => if(AREG /= ACASCREG) then
              assert false
              report "Attribute Syntax Error : The attribute ACASCREG on DSP48E has to be set to 0 when attribute AREG = 0."
              severity Failure;
           end if;
      when 1 => if(AREG /= ACASCREG) then
              assert false
              report "Attribute Syntax Error : The attribute ACASCREG on DSP48E has to be set to 1 when attribute AREG = 1."
              severity Failure;
           end if;
      when 2 => if((AREG /= ACASCREG) and ((AREG-1) /= ACASCREG))then
              assert false
              report "Attribute Syntax Error : The attribute ACASCREG on DSP48E has to be set to either 2 or 1 when attribute AREG = 2."
              severity Failure;
           end if;
      when others => null;
    end case;

----------- Checks for BREG ----------------------
    case BREG is
      when 0|1|2 =>
      when others =>
         assert false
         report "Attribute Syntax Error: The allowed values for BREG are 0 or 1 or 2"
         severity Failure;
    end case;

----------- Checks for BCASCREG and (BCASCREG vs BREG) ----------------------

    case BREG is
      when 0 => if(BREG /= BCASCREG) then
              assert false
              report "Attribute Syntax Error : The attribute BCASCREG on DSP48E has to be set to 0 when attribute BREG = 0."
              severity Failure;
           end if;
      when 1 => if(BREG /= BCASCREG) then
              assert false
              report "Attribute Syntax Error : The attribute BCASCREG on DSP48E has to be set to 1 when attribute BREG = 1."
              severity Failure;
           end if;
      when 2 => if((BREG /= BCASCREG) and ((BREG-1) /= BCASCREG))then
              assert false
              report "Attribute Syntax Error : The attribute BCASCREG on DSP48E has to be set to either 2 or 1 when attribute BREG = 2."
              severity Failure;
           end if;
      when others => null;
    end case;

----------- Check for AUTORESET_OVER_UNDER_FLOW ----------------------

--   case AUTORESET_OVER_UNDER_FLOW is
--      when true | false => null;
--      when others =>
--         assert false
--         report "Attribute Syntax Error: The allowed values for AUTORESET_OVER_UNDER_FLOW are true or fasle"
--         severity Failure;
--    end case;
         
----------- Check for AUTORESET_PATTERN_DETECT ----------------------

    case AUTORESET_PATTERN_DETECT is
      when true | false => null;
      when others =>
         assert false
         report "Attribute Syntax Error: The allowed values for AUTORESET_PATTERN_DETECT are true or fasle"
         severity Failure;
    end case;
         
----------- Check for AUTORESET_PATTERN_DETECT_OPTINV ----------------------

    if((AUTORESET_PATTERN_DETECT_OPTINV /="MATCH") and (AUTORESET_PATTERN_DETECT_OPTINV /="NOT_MATCH")) then
        assert false
        report "Attribute Syntax Error: The allowed values for AUTORESET_PATTERN_DETECT_OPTINV are MATCH or NOT_MATCH."
        severity Failure;
    end if;

----------- Check for USE_MULT ----------------------

     if((USE_MULT /="NONE") and (USE_MULT /="MULT") and
        (USE_MULT /="MULT_S")) then
        assert false
        report "Attribute Syntax Error: The allowed values for USE_MULT are NONE, MULT or MULT_S."
        severity Failure;
     elsif((USE_MULT ="MULT") and (MREG /= 0)) then
        assert false
        report "Attribute Syntax Error: The attribute USE_MULT on DSP48 is set to MULT. This requires attribute MREG to be set to 0."
        severity Failure;
     elsif((USE_MULT ="MULT_S") and (MREG /= 1)) then
        assert false
        report "Attribute Syntax Error: The attribute USE_MULT on DSP48 is set to MULT_S. This requires attribute MREG to be set to 1."
        severity Failure;
     end if;

----------- Check for USE_PATTERN_DETECT ----------------------

    if((USE_PATTERN_DETECT /="PATDET") and (USE_PATTERN_DETECT /="NO_PATDET")) then
        assert false
        report "Attribute Syntax Error: The allowed values for USE_PATTERN_DETECT are PATDET or NO_PATDET."
        severity Failure;
    end if;

--*********************************************************
--*** ADDITIONAL DRC
--*********************************************************
-- CR 219407  --  (1)
    if((AUTORESET_PATTERN_DETECT = TRUE) and (USE_PATTERN_DETECT = "NO_PATDET")) then
        assert false
        report "Attribute Syntax Error : The attribute USE_PATTERN_DETECT on DSP48E instance must be set to PATDET in order to use AUTORESET_PATTERN_DETECT equals TRUE. Failure to do so could make timing reports inaccurate. "
        severity Warning;
    end if;
------------------------------------------------------------
    ping_opmode_drc_check   <= '1' after 100010 ps;
------------------------------------------------------------

    wait;
  end process prcs_init;
--####################################################################
--#####    Input Register A with two levels of registers and a mux ###
--####################################################################
  prcs_a_in:process(A_dly, ACIN_dly)
  begin
     if(A_INPUT ="DIRECT") then
        a_o_mux <= A_dly;
     elsif(A_INPUT ="CASCADE") then
        a_o_mux <= ACIN_dly;
     else
        assert false
        report "Attribute Syntax Error: The allowed values for A_INPUT are DIRECT or CASCADE."
        severity Failure;
     end if;
  end process prcs_a_in;
------------------------------------------------------------------
  prcs_qa_2lvl:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
          qa_o_reg1 <= ( others => '0');
          qa_o_reg2 <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTA_dly = '1') then
               qa_o_reg1 <= ( others => '0');
               qa_o_reg2 <= ( others => '0');
            elsif (RSTA_dly = '0') then
               case AREG is
                    when 1 =>
                       if(CEA2_dly = '1') then
                          qa_o_reg2 <= a_o_mux;
                       end if;
                    when 2 =>
                       if(CEA1_dly = '1') then
                          qa_o_reg1 <= a_o_mux;
                       end if;
                       if(CEA2_dly = '1') then
                          qa_o_reg2 <= qa_o_reg1;
                       end if;
                    when others => null;
               end case;
            end if;
         end if;
      end if;
  end process prcs_qa_2lvl;
------------------------------------------------------------------
  prcs_qa_o_mux:process(a_o_mux, qa_o_reg2)
  begin
     case AREG is
       when 0   => qa_o_mux <= a_o_mux;
       when 1|2 => qa_o_mux <= qa_o_reg2;
       when others =>
            assert false
            report "Attribute Syntax Error: The allowed values for AREG are 0 or 1 or 2"
            severity Failure;
     end case;
  end process prcs_qa_o_mux;
------------------------------------------------------------------
  prcs_qacout_o_mux:process(qa_o_mux, qa_o_reg1)
  begin
     case ACASCREG is
       when 1 => case AREG is
                   when 2 => qacout_o_mux <= qa_o_reg1;
                   when others =>  qacout_o_mux <= qa_o_mux;
                 end case;
       when others =>  qacout_o_mux <= qa_o_mux;
     end case;

  end process prcs_qacout_o_mux;
--####################################################################
--#####    Input Register B with two levels of registers and a mux ###
--####################################################################
 prcs_b_in:process(B_dly, BCIN_dly)
  begin
     if(B_INPUT ="DIRECT") then
        b_o_mux <= B_dly;
     elsif(B_INPUT ="CASCADE") then
        b_o_mux <= BCIN_dly;
     else
        assert false
        report "Attribute Syntax Error: The allowed values for B_INPUT are DIRECT or CASCADE."
        severity Failure;
     end if;
     
  end process prcs_b_in;
------------------------------------------------------------------
 prcs_qb_2lvl:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
          qb_o_reg1 <= ( others => '0');
          qb_o_reg2 <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTB_dly = '1') then
               qb_o_reg1 <= ( others => '0');
               qb_o_reg2 <= ( others => '0');
            elsif (RSTB_dly = '0') then
               case BREG is
                    when 1 =>
                       if(CEB2_dly = '1') then
                          qb_o_reg2 <= b_o_mux;
                       end if;
                    when 2 =>
                       if(CEB1_dly = '1') then
                          qb_o_reg1 <= b_o_mux;
                       end if;
                       if(CEB2_dly = '1') then
                          qb_o_reg2 <= qb_o_reg1;
                       end if;
                    when others => null;
               end case;
            end if;
         end if;
      end if;
  end process prcs_qb_2lvl;
------------------------------------------------------------------
  prcs_qb_o_mux:process(b_o_mux, qb_o_reg2)
  begin
     case BREG is
       when 0   => qb_o_mux <= b_o_mux;
       when 1|2 => qb_o_mux <= qb_o_reg2;
       when others =>
            assert false
            report "Attribute Syntax Error: The allowed values for BREG are 0 or 1 or 2 "
            severity Failure;
     end case;

  end process prcs_qb_o_mux;
------------------------------------------------------------------
  prcs_qbcout_o_mux:process(qb_o_mux, qb_o_reg1)
  begin
     case BCASCREG is
       when 1 => case BREG is
                   when 2 => qbcout_o_mux <= qb_o_reg1;
                   when others =>  qbcout_o_mux <= qb_o_mux;
                 end case;
       when others =>  qbcout_o_mux <= qb_o_mux;
     end case;
  end process prcs_qbcout_o_mux;

--####################################################################
--#####    Input Register C with 0, 1, level of registers        #####
--####################################################################
  prcs_qc_1lvl:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         qc_o_reg <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTC_dly = '1') then
               qc_o_reg <= ( others => '0');
            elsif ((RSTC_dly = '0') and (CEC_dly = '1')) then
               qc_o_reg <= C_dly;
            end if;
         end if;
      end if;
  end process prcs_qc_1lvl;
------------------------------------------------------------------
  prcs_qc_o_mux:process(C_dly, qc_o_reg)
  begin
     case CREG is
      when 0 => qc_o_mux <= C_dly;
      when 1 => qc_o_mux <= qc_o_reg;
      when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for CREG are 0 or 1"
           severity Failure;
      end case;
  end process prcs_qc_o_mux;

--####################################################################
--###################      25x18 Multiplier     ######################
--####################################################################
--
-- 05/26/05 -- FP -- Added warning for invalid mult when USE_MULT=NONE
-- SIMD=FOUR12 and SIMD=TWO24
-- Made mult_o to be "X"
--
  prcs_mult:process(qa_o_mux, qb_o_mux)
  begin
     if(USE_MULT /= "NONE") then
        mult_o_int <=  qa_o_mux(MSB_A_MULT downto 0) * qb_o_mux (MSB_B_MULT downto 0);
     end if;
  end process prcs_mult;
------------------------------------------------------------------
  prcs_mult_reg:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         mult_o_reg <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTM_dly = '1') then
               mult_o_reg <= ( others => '0');
            elsif ((RSTM_dly = '0') and (CEM_dly = '1')) then
               mult_o_reg <= mult_o_int;
            end if;
         end if;
      end if;
  end process prcs_mult_reg;
------------------------------------------------------------------
  prcs_mult_mux:process(mult_o_reg, mult_o_int)
  begin
     case MREG is
      when 0 => mult_o_mux <= mult_o_int;
      when 1 => mult_o_mux <= mult_o_reg;
      when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for MREG are 0 or 1"
           severity Failure;
      end case;
  end process prcs_mult_mux;

--####################################################################
--#####                        OpMode                            #####
--####################################################################
  prcs_opmode_reg:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         opmode_o_reg <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTCTRL_dly = '1') then
               opmode_o_reg <= ( others => '0');
            elsif ((RSTCTRL_dly = '0') and (CECTRL_dly = '1')) then
               opmode_o_reg <= OPMODE_dly;
            end if;
         end if;
      end if;
  end process prcs_opmode_reg;
------------------------------------------------------------------
  prcs_opmode_mux:process(opmode_o_reg, OPMODE_dly)
  begin
     case OPMODEREG is
      when 0 => opmode_o_mux <= OPMODE_dly;
      when 1 => opmode_o_mux <= opmode_o_reg;
      when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for OPMODEREG are 0 or 1"
           severity Failure;
      end case;
  end process prcs_opmode_mux;
--####################################################################
--#####                        MUX_XYZ                           #####
--####################################################################
  prcs_mux_xyz:process(opmode_o_mux, qp_o_mux, qa_o_mux, qb_o_mux, mult_o_mux, 
                       qc_o_mux, PCIN_dly, output_x_sig)
  begin
    if(output_x_sig = '1') then
      muxx_o_mux(MSB_P downto 0) <= ( others => 'X');
      muxy_o_mux(MSB_P downto 0) <= ( others => 'X');
      muxz_o_mux(MSB_P downto 0) <= ( others => 'X');
    elsif(output_x_sig = '0') then
    --MUX_X -----
       case opmode_o_mux(1 downto 0) is
         when "00" => muxx_o_mux <= ( others => '0');
         -- FP ?? sign extend needed from 43rd bit to 48th bit 
         when "01" => muxx_o_mux((MSB_A_MULT + MSB_B_MULT +1) downto 0) <= mult_o_mux;
                   if(mult_o_mux(MSB_A_MULT + MSB_B_MULT + 1) = '1') then
                     muxx_o_mux(MSB_PCIN downto (MAX_A_MULT + MAX_B_MULT)) <=  ( others => '1');
                   elsif (mult_o_mux(MSB_A_MULT + MSB_B_MULT + 1) = '0') then
                     muxx_o_mux(MSB_PCIN downto (MAX_A_MULT + MAX_B_MULT)) <=  ( others => '0');
                   end if;

         when "10" => muxx_o_mux <= qp_o_mux;

-- CR 438456  & CR 448147 & CR 451453
         when "11" => if((USE_MULT = "MULT_S") and (AREG=0 or BREG=0)) then 
                          muxx_o_mux(MSB_P downto 0) <=  ( others => 'X');  
                          assert false
                          report "DRC warning: When attribute USE_MULT on DSP48E instance %m is set to MULT_S, the A:B opmode selection is not permitted when AREG or BREG=0. If the multiplier is not used, set USE_MULT = NONE. For dynamic switching between multiply and add operation, set AREG and BREG=1 or MREG=0 and USE_MULT=MULT."
                          severity Warning;
                      else
                          muxx_o_mux(MSB_P downto 0)  <= (qa_o_mux & qb_o_mux);
                      end if;

         when others => null;
       end case;

    --MUX_Y -----
       case opmode_o_mux(3 downto 2) is
         when "00" => muxy_o_mux <= ( others => '0');
         when "01" => muxy_o_mux <= ( others => '0');
         when "10" => 
                     if(opmode_o_mux(6 downto 4) = "100") then
                        muxy_o_mux <= ( others => MULTSIGNIN_dly);
                     else
                        muxy_o_mux <= ( others => '1');
                     end if;
         when "11" => muxy_o_mux <= qc_o_mux;
         when others => null;
       end case;
    --MUX_Z -----
       case opmode_o_mux(6 downto 4) is
         when "000" => muxz_o_mux <= ( others => '0');
         when "001" => muxz_o_mux <= PCIN_dly;
         when "010" => muxz_o_mux <= qp_o_mux;
         when "011" => muxz_o_mux <= qc_o_mux;
         when "100" => muxz_o_mux <= qp_o_mux; -- Used for MACC extend -- multsignin
      -- FP ?? better shift possible ?
         when "101" => if(PCIN_dly(MSB_PCIN) = '0') then
                         muxz_o_mux  <= ( others => '0');
                       elsif(PCIN_dly(MSB_PCIN) = '1') then
                         muxz_o_mux  <= ( others => '1');
                       end if;
                       muxz_o_mux ((MSB_PCIN - SHIFT_MUXZ) downto 0) <= PCIN_dly(MSB_PCIN downto SHIFT_MUXZ ); 
         when "110" => if(qp_o_mux(MSB_P) = '0') then
                         muxz_o_mux  <= ( others => '0');
                       elsif(qp_o_mux(MSB_P) = '1') then
                         muxz_o_mux  <= ( others => '1');
                       end if;
                       muxz_o_mux ((MSB_P - SHIFT_MUXZ) downto 0) <= qp_o_mux(MSB_P downto SHIFT_MUXZ ); 
                      
         when "111" => null;
         when others => null;
       end case;
    end if;
  end process prcs_mux_xyz;
--####################################################################
--#####                        Alumode                          #####
--####################################################################
  prcs_alumode_reg:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         alumode_o_reg <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTALUMODE_dly = '1') then
               alumode_o_reg <= ( others => '0');
            elsif ((RSTALUMODE_dly = '0') and (CEALUMODE_dly = '1'))then
               alumode_o_reg <= ALUMODE_dly;
            end if;
         end if;
      end if;
  end process prcs_alumode_reg;
------------------------------------------------------------------
  prcs_alumode_mux:process(alumode_o_reg, ALUMODE_dly)
  begin
     case ALUMODEREG is
      when 0 => alumode_o_mux <= ALUMODE_dly;
      when 1 => alumode_o_mux <= alumode_o_reg;
      when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for ALUMODEREG are 0 or 1"
           severity Failure;
      end case;
  end process prcs_alumode_mux;

--####################################################################
--#####                     CarryInSel                           #####
--####################################################################
  prcs_carryinsel_reg:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         carryinsel_o_reg <= ( others => '0');
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTCTRL_dly = '1') then
               carryinsel_o_reg <= ( others => '0');
            elsif ((RSTCTRL_dly = '0') and (CECTRL_dly = '1')) then
               carryinsel_o_reg <= CARRYINSEL_dly;
            end if;
         end if;
      end if;
  end process prcs_carryinsel_reg;
------------------------------------------------------------------
  prcs_carryinsel_mux:process(carryinsel_o_reg, CARRYINSEL_dly)
  begin
     case CARRYINSELREG is
       when 0 => carryinsel_o_mux <= CARRYINSEL_dly;
       when 1 => carryinsel_o_mux <= carryinsel_o_reg;
       when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for CARRYINSELREG are 0 or 1"
           severity Failure;
     end case;
  end process prcs_carryinsel_mux;

------------------------------------------------------------------
-- CR 219047 (3)
  prcs_carryinsel_drc:process(carryinsel_o_mux, MULTSIGNIN_dly, opmode_o_mux)
  begin
     if(carryinsel_o_mux = "010") then
        if(not((MULTSIGNIN_dly = 'X') or ((opmode_o_mux = "1001000") and (MULTSIGNIN_dly /= 'X')) 
                                 or ((MULTSIGNIN_dly = '0') and (CARRYCASCIN_dly = '0')))) then
           assert false
-- CR 451178 -- DRC warning Enhancement
           report "DRC warning : CARRYCASCIN can only be used in the current DSP48E instance if the previous DSP48E  is performing a two input ADD operation, or the current DSP48E is configured in the MAC extend opmode(6:0) equals 1001000. This warning can be also triggered if OPMODEREG is set to 1 and CARRYINSELREG is set to 0 - in which case please set CARRYINSELREG to 1."
           severity Warning;
        end if;
     end if;
  end process prcs_carryinsel_drc;

-- CR 219047 (4)
  prcs_carryinsel_mac_drc:process(carryinsel_o_mux)
  begin
     if((carryinsel_o_mux = "110")  and (MULTCARRYINREG /= MREG)) then
        assert false
        report "Attribute Syntax Warning : It is recommended that MREG and MULTCARRYINREG on DSP48E instance be set to the same value when using CARRYINSEL = 110 for multiply rounding. "
        severity Warning;
     end if;
  end process prcs_carryinsel_mac_drc;


--####################################################################
--#####                       CarryIn                            #####
--####################################################################

-------  input 0

  prcs_carryin_reg0:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         qcarryin_o_reg0 <= '0';
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTALLCARRYIN_dly = '1') then
               qcarryin_o_reg0 <= '0';
            elsif((RSTALLCARRYIN_dly = '0') and (CECARRYIN_dly = '1')) then
               qcarryin_o_reg0 <= CARRYIN_dly;
            end if;
         end if;
      end if;
  end process prcs_carryin_reg0;

  prcs_carryin_mux0:process(qcarryin_o_reg0, CARRYIN_dly)
  begin
     case CARRYINREG is
       when 0 => carryin_o_mux0 <= CARRYIN_dly;
       when 1 => carryin_o_mux0 <= qcarryin_o_reg0;
       when others =>
            assert false
            report "Attribute Syntax Error: The allowed values for CARRYINREG are 0 or 1"
            severity Failure;
     end case;
  end process prcs_carryin_mux0;

------------------------------------------------------------------
-------  input 7

  prcs_carryin_reg7:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         qcarryin_o_reg7 <= '0';
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if(RSTALLCARRYIN_dly = '1') then
               qcarryin_o_reg7 <= '0';
            elsif((RSTALLCARRYIN_dly = '0') and (CEMULTCARRYIN_dly = '1')) then
               qcarryin_o_reg7 <= qa_o_mux(24) XNOR qb_o_mux(17);
            end if;
         end if;
      end if;
  end process prcs_carryin_reg7;

  prcs_carryin_mux7:process(qa_o_mux(24), qb_o_mux(17), qcarryin_o_reg7)
  begin
     case MULTCARRYINREG is
       when 0 => carryin_o_mux7 <= qa_o_mux(24) XNOR qb_o_mux(17);
-- CR 232187
       when 1 => carryin_o_mux7 <= qcarryin_o_reg7;
       when others =>
            assert false
            report "Attribute Syntax Error: The allowed values for MULTCARRYINREG are 0 or 1"
            severity Failure;
     end case;
  end process prcs_carryin_mux7;

------------------------------------------------------------------
-- FP Check this with VV 
------------------------------------------------------------------
-- 
  prcs_carryin_mux:process(carryin_o_mux0, PCIN_dly(47), CARRYCASCIN_dly, carrycascout_o_mux, qp_o_mux(47), carryin_o_mux7, carryinsel_o_mux)
  begin
     case carryinsel_o_mux is
       when "000" => carryin_o_mux  <= carryin_o_mux0;
       when "001" => carryin_o_mux  <= NOT PCIN_dly(47);
       when "010" => carryin_o_mux  <= CARRYCASCIN_dly;
       when "011" => carryin_o_mux  <= PCIN_dly(47);
       when "100" => carryin_o_mux  <= carrycascout_o_mux;
       when "101" => carryin_o_mux  <= NOT qp_o_mux(47);
       when "110" => carryin_o_mux  <= carryin_o_mux7;
       when "111" => carryin_o_mux  <= qp_o_mux(47);
       when others => null;
     end case;
  end process prcs_carryin_mux;
--####################################################################
--#####                         ALU                              #####
--####################################################################
  prcs_alu:process(muxx_o_mux, muxy_o_mux, muxz_o_mux, alumode_o_mux, opmode_o_mux, carryin_o_mux, output_x_sig)

  variable opmode_alu_var : std_logic_vector(5 downto 0) := (others => '0');
  variable alu_full_tmp   : std_logic_vector(MAX_ALU_FULL downto 0) := (others => '0');
  variable alu_hlf1_tmp, alu_hlf2_tmp  : std_logic_vector(MAX_ALU_HALF downto 0) := (others => '0');
  variable alu_qrt1_tmp, alu_qrt2_tmp, alu_qrt3_tmp, alu_qrt4_tmp : std_logic_vector(MAX_ALU_QUART downto 0) := (others => '0');

  begin
     if(output_x_sig = '1') then
       alu_o <= (others => 'X');

     elsif(opmode_valid_flg) then
        opmode_alu_var := opmode_o_mux(3 downto 2) & alumode_o_mux;
        case opmode_alu_var is
           ---------------------------------
           ------------- ADD ---------------
           ---------------------------------
           when "000000" | "010000" | "100000" | "110000" => 

               if((USE_SIMD = "ONE48") or (USE_SIMD = "one48")) then
                  alu_full_tmp := (('0'&muxz_o_mux) + 
                                   ('0'&muxx_o_mux) + 
                                   ('0'&muxy_o_mux) + carryin_o_mux); 
                  alu_o <= alu_full_tmp(MSB_ALU_FULL downto 0);

                  carrycascout_o               <=  alu_full_tmp(MAX_ALU_FULL);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  alu_full_tmp(MAX_ALU_FULL);
                     carryout_o(MSB_CARRYOUT - 1) <=  'X';
                     carryout_o(MSB_CARRYOUT - 2) <=  'X';
                     carryout_o(MSB_CARRYOUT - 3) <=  'X';
                  end if;

               elsif((USE_SIMD = "TWO24") or (USE_SIMD = "two24")) then
                  alu_hlf1_tmp := (('0'&muxz_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  ('0'&muxx_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  ('0'&muxy_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  carryin_o_mux);
                  alu_hlf2_tmp := (('0'&muxz_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) +
                                  ('0'&muxx_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) +
                                  ('0'&muxy_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF)))); 
                  alu_o <= (alu_hlf2_tmp(MSB_ALU_HALF downto 0) & alu_hlf1_tmp(MSB_ALU_HALF downto 0)) ;

                  carrycascout_o               <=  alu_hlf2_tmp(MAX_ALU_HALF);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  alu_hlf2_tmp(MAX_ALU_HALF);
                     carryout_o(MSB_CARRYOUT - 1) <=  'X';
                     carryout_o(MSB_CARRYOUT - 2) <=  alu_hlf1_tmp(MAX_ALU_HALF);
                     carryout_o(MSB_CARRYOUT - 3) <=  'X';
                  end if;

               elsif((USE_SIMD = "FOUR12") or (USE_SIMD = "four12")) then
                  alu_qrt1_tmp := (('0'&muxz_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  ('0'&muxx_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  ('0'&muxy_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  carryin_o_mux);
                  alu_qrt2_tmp := (('0'&muxz_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) +
                                  ('0'&muxx_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))));
                  alu_qrt3_tmp := (('0'&muxz_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) +
                                  ('0'&muxx_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))));
                  alu_qrt4_tmp := (('0'&muxz_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) +
                                  ('0'&muxx_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))));

                  alu_o <= (alu_qrt4_tmp(MSB_ALU_QUART downto 0) & alu_qrt3_tmp(MSB_ALU_QUART downto 0) &
                              alu_qrt2_tmp(MSB_ALU_QUART downto 0) & alu_qrt1_tmp(MSB_ALU_QUART downto 0));

                  carrycascout_o               <=  alu_qrt4_tmp(MAX_ALU_QUART);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  alu_qrt4_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 1) <=  alu_qrt3_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 2) <=  alu_qrt2_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 3) <=  alu_qrt1_tmp(MAX_ALU_QUART);
                  end if;

               else
                  assert false
                  report "Attribute Syntax Error: The legal values for USE_SIMD are ONE48 or TWO24 or FOUR12."
                  severity Failure;
               end if;

           ---------------------------------
           ------ SUBTRACT (X + ~Z ) ---- carryin must be 1 ---------------
           ---------------------------------
           when "000001" | "010001" | "100001" | "110001" => 

               if((USE_SIMD = "ONE48") or (USE_SIMD = "one48")) then
                  alu_full_tmp := NOT('0'&muxz_o_mux) + 
                                   ('0'&muxx_o_mux) + 
                                   ('0'&muxy_o_mux) + carryin_o_mux; 
                  alu_o <= alu_full_tmp(MSB_ALU_FULL downto 0);

                  carrycascout_o               <=  NOT alu_full_tmp(MAX_ALU_FULL);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  NOT alu_full_tmp(MAX_ALU_FULL);
                     carryout_o(MSB_CARRYOUT - 1) <=  'X';
                     carryout_o(MSB_CARRYOUT - 2) <=  'X';
                     carryout_o(MSB_CARRYOUT - 3) <=  'X';
                  end if;

               elsif((USE_SIMD = "TWO24") or (USE_SIMD = "two24")) then
                  alu_hlf1_tmp := NOT('0'&muxz_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  ('0'&muxx_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  ('0'&muxy_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  carryin_o_mux;
                  alu_hlf2_tmp := NOT('0'&muxz_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) +
                                  ('0'&muxx_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) +
                                  ('0'&muxy_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF)));

                  alu_o <= (alu_hlf2_tmp(MSB_ALU_HALF downto 0) & alu_hlf1_tmp(MSB_ALU_HALF downto 0)) ;

                  carrycascout_o               <=  NOT alu_hlf2_tmp(MAX_ALU_HALF);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  NOT alu_hlf2_tmp(MAX_ALU_HALF);
                     carryout_o(MSB_CARRYOUT - 1) <=  'X';
                     carryout_o(MSB_CARRYOUT - 2) <=  NOT alu_hlf1_tmp(MAX_ALU_HALF);
                     carryout_o(MSB_CARRYOUT - 3) <=  'X';
                  end if;

               elsif((USE_SIMD = "FOUR12") or (USE_SIMD = "four12")) then
                  alu_qrt1_tmp := NOT('0'&muxz_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  ('0'&muxx_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  ('0'&muxy_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  carryin_o_mux;
                  alu_qrt2_tmp := NOT('0'&muxz_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) +
                                  ('0'&muxx_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART)));
                  alu_qrt3_tmp := NOT('0'&muxz_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) +
                                  ('0'&muxx_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART)));
                  alu_qrt4_tmp := NOT('0'&muxz_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) +
                                  ('0'&muxx_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART)));

                  alu_o <= (alu_qrt4_tmp(MSB_ALU_QUART downto 0) & alu_qrt3_tmp(MSB_ALU_QUART downto 0) &
                              alu_qrt2_tmp(MSB_ALU_QUART downto 0) & alu_qrt1_tmp(MSB_ALU_QUART downto 0));

                  carrycascout_o               <=  NOT alu_qrt4_tmp(MAX_ALU_QUART);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  NOT alu_qrt4_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 1) <=  NOT alu_qrt3_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 2) <=  NOT alu_qrt2_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 3) <=  NOT alu_qrt1_tmp(MAX_ALU_QUART);
                  end if;

               else
                  assert false
                  report "Attribute Syntax Error: The legal values for USE_SIMD are ONE48 or TWO24 or FOUR12."
                  severity Failure;
               end if;

           ---------------------------------
           ---------- NOT (X + Y + Z + C) ----------
           ---------------------------------
           when "000010" | "010010" | "100010" | "110010" => 

               if((USE_SIMD = "ONE48") or (USE_SIMD = "one48")) then
                  alu_full_tmp := NOT((('0'&muxz_o_mux) + 
                                   ('0'&muxx_o_mux) + 
                                   ('0'&muxy_o_mux) + carryin_o_mux)); 

                  alu_o <= alu_full_tmp(MSB_ALU_FULL downto 0);

                  carrycascout_o               <=  NOT alu_full_tmp(MAX_ALU_FULL);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  NOT alu_full_tmp(MAX_ALU_FULL);
                     carryout_o(MSB_CARRYOUT - 1) <=  'X';
                     carryout_o(MSB_CARRYOUT - 2) <=  'X';
                     carryout_o(MSB_CARRYOUT - 3) <=  'X';
                  end if;

               elsif((USE_SIMD = "TWO24") or (USE_SIMD = "two24")) then
                  alu_hlf1_tmp := NOT((('0'&muxz_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  ('0'&muxx_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  ('0'&muxy_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  carryin_o_mux));
                  alu_hlf2_tmp := NOT((('0'&muxz_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) +
                                  ('0'&muxx_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) +
                                  ('0'&muxy_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF)))));

                  alu_o <= (alu_hlf2_tmp(MSB_ALU_HALF downto 0) & alu_hlf1_tmp(MSB_ALU_HALF downto 0)) ;

                  carrycascout_o               <=  NOT alu_hlf2_tmp(MAX_ALU_HALF);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  NOT alu_hlf2_tmp(MAX_ALU_HALF);
                     carryout_o(MSB_CARRYOUT - 1) <=  'X';
                     carryout_o(MSB_CARRYOUT - 2) <=  NOT alu_hlf1_tmp(MAX_ALU_HALF);
                     carryout_o(MSB_CARRYOUT - 3) <=  'X';
                  end if;

               elsif((USE_SIMD = "FOUR12") or (USE_SIMD = "four12")) then
                  alu_qrt1_tmp := NOT((('0'&muxz_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  ('0'&muxx_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  ('0'&muxy_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  carryin_o_mux));
                  alu_qrt2_tmp := NOT((('0'&muxz_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) +
                                  ('0'&muxx_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART)))));
                  alu_qrt3_tmp := NOT((('0'&muxz_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) +
                                  ('0'&muxx_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART)))));
                  alu_qrt4_tmp := NOT((('0'&muxz_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) +
                                  ('0'&muxx_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART)))));

                  alu_o <= (alu_qrt4_tmp(MSB_ALU_QUART downto 0) & alu_qrt3_tmp(MSB_ALU_QUART downto 0) &
                              alu_qrt2_tmp(MSB_ALU_QUART downto 0) & alu_qrt1_tmp(MSB_ALU_QUART downto 0));

                  carrycascout_o               <=  NOT alu_qrt4_tmp(MAX_ALU_QUART);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  NOT alu_qrt4_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 1) <=  NOT alu_qrt3_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 2) <=  NOT alu_qrt2_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 3) <=  NOT alu_qrt1_tmp(MAX_ALU_QUART);
                  end if;

               else
                  assert false
                  report "Attribute Syntax Error: The legal values for USE_SIMD are ONE48 or TWO24 or FOUR12."
                  severity Failure;
               end if;

           ---------------------------------
           ------- SUBTRACT (Z - X ) -------
           ---------------------------------
           when "000011" | "010011" | "100011" | "110011"=> 

               if((USE_SIMD = "ONE48") or (USE_SIMD = "one48")) then
                  alu_full_tmp := (('0'&muxz_o_mux) - 
                                   (('0'&muxx_o_mux) + 
                                   ('0'&muxy_o_mux) + carryin_o_mux)); 

                  alu_o <= alu_full_tmp(MSB_ALU_FULL downto 0);

                  carrycascout_o               <=  alu_full_tmp(MAX_ALU_FULL);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  NOT alu_full_tmp(MAX_ALU_FULL);
                     carryout_o(MSB_CARRYOUT - 1) <=  'X';
                     carryout_o(MSB_CARRYOUT - 2) <=  'X';
                     carryout_o(MSB_CARRYOUT - 3) <=  'X';
                  end if;

               elsif((USE_SIMD = "TWO24") or (USE_SIMD = "two24")) then
                  alu_hlf1_tmp := (('0'&muxz_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) -
                                  (('0'&muxx_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  ('0'&muxy_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) +
                                  carryin_o_mux));
                  alu_hlf2_tmp := (('0'&muxz_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) -
                                  (('0'&muxx_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) +
                                  ('0'&muxy_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF)))));

                  alu_o <= (alu_hlf2_tmp(MSB_ALU_HALF downto 0) & alu_hlf1_tmp(MSB_ALU_HALF downto 0)) ;

                  carrycascout_o               <=  alu_hlf2_tmp(MAX_ALU_HALF);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  NOT alu_hlf2_tmp(MAX_ALU_HALF);
                     carryout_o(MSB_CARRYOUT - 1) <=  'X';
                     carryout_o(MSB_CARRYOUT - 2) <=  NOT alu_hlf1_tmp(MAX_ALU_HALF);
                     carryout_o(MSB_CARRYOUT - 3) <=  'X';
                  end if;

               elsif((USE_SIMD = "FOUR12") or (USE_SIMD = "four12")) then
                  alu_qrt1_tmp := (('0'&muxz_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) -
                                  (('0'&muxx_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  ('0'&muxy_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) +
                                  carryin_o_mux));
                  alu_qrt2_tmp := (('0'&muxz_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) -
                                  (('0'&muxx_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART)))));
                  alu_qrt3_tmp := (('0'&muxz_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) -
                                  (('0'&muxx_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART)))));
                  alu_qrt4_tmp := (('0'&muxz_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) -
                                  (('0'&muxx_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) +
                                  ('0'&muxy_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART)))));

                  alu_o <= (alu_qrt4_tmp(MSB_ALU_QUART downto 0) & alu_qrt3_tmp(MSB_ALU_QUART downto 0) &
                              alu_qrt2_tmp(MSB_ALU_QUART downto 0) & alu_qrt1_tmp(MSB_ALU_QUART downto 0));

                  carrycascout_o               <=  alu_qrt4_tmp(MAX_ALU_QUART);
                  --  if multiply operation then "X"out the carryout
                  if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then
                     carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                  else
                     carryout_o(MSB_CARRYOUT - 0) <=  NOT alu_qrt4_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 1) <=  NOT alu_qrt3_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 2) <=  NOT alu_qrt2_tmp(MAX_ALU_QUART);
                     carryout_o(MSB_CARRYOUT - 3) <=  NOT alu_qrt1_tmp(MAX_ALU_QUART);
                  end if;

               else
                  assert false
                  report "Attribute Syntax Error: The legal values for USE_SIMD are ONE48 or TWO24 or FOUR12."
                  severity Failure;
               end if;

           ---------------------------------
           ------------- XOR ---------------
           ---------------------------------
           when "000100" | "000111" | "100101" | "100110" =>
                alu_o <= muxx_o_mux xor muxz_o_mux; 
                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';

           ---------------------------------
           ------------- XNOR ---------------
           ---------------------------------
           when "000101" | "000110" | "100100" | "100111" =>
                alu_o <= muxx_o_mux xnor muxz_o_mux; 
                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';

           ---------------------------------
           ------------- AND ---------------
           ---------------------------------
           when "001100" =>
                alu_o <= muxx_o_mux and muxz_o_mux; 
                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';

           ---------------------------------
           --------- X AND (NOT Z) ---------
           ---------------------------------
           when "001101" =>
                alu_o <= muxx_o_mux and (not muxz_o_mux); 
                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';

           ---------------------------------
           ------------- NAND ---------------
           ---------------------------------
           when "001110" =>
                alu_o <= muxx_o_mux nand muxz_o_mux; 
                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';

           ---------------------------------
           -------- - (NOT X) OR Z ---------
           ---------------------------------
           when "001111" =>
                alu_o <= (not muxx_o_mux) or  muxz_o_mux; 
                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';

           ---------------------------------
           -------------- OR ---------------
           ---------------------------------
           when "101100" =>
                alu_o <= muxx_o_mux or muxz_o_mux; 
                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';

           ---------------------------------
           --------- X OR (NOT Z) ---------
           ---------------------------------
           when "101101" =>
                alu_o <= muxx_o_mux or (not muxz_o_mux); 
                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';

           ---------------------------------
           ------------ X NOR Z ------------
           ---------------------------------
           when "101110" =>
                alu_o <= muxx_o_mux nor  muxz_o_mux; 
                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';

           ---------------------------------
           --------- (NOT X) and Z ---------
           ---------------------------------
           when "101111" =>
                alu_o <= (not muxx_o_mux) and  muxz_o_mux; 
                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';


           when others => 

                carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X');
                carrycascout_o <= 'X';

        end case;
    end if;
  end process prcs_alu;
--####################################################################
--#####                CARRYOUT and CARRYCASCOUT                 #####
--####################################################################
  prcs_carry_reg:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         carryout_o_reg     <=  ( others => '0');
         carrycascout_o_reg <=  '0';
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if((RSTP_dly = '1') or 
               ((AUTORESET_PATTERN_DETECT) and (
                ((AUTORESET_PATTERN_DETECT_OPTINV = "MATCH") and pdet_o_reg1 = '1') or 
                ((AUTORESET_PATTERN_DETECT_OPTINV = "NOT_MATCH") and (pdet_o_reg2 = '1' and pdet_o_reg1 = '0')))
               )
              ) then
               carryout_o_reg     <= ( others => '0');
               carrycascout_o_reg <=  '0';
            elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then
               carryout_o_reg <= carryout_o;
               carrycascout_o_reg <= carrycascout_o;
            end if;
         end if;
      end if;
  end process prcs_carry_reg;
------------------------------------------------------------------
  prcs_carryout_mux:process(carryout_o, carryout_o_reg)
  begin
     case PREG is
       when 0 => carryout_o_mux <= carryout_o;
       when 1 => carryout_o_mux <= carryout_o_reg;
       when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for PREG are 0 or 1"
           severity Failure;
     end case;
   
  end process prcs_carryout_mux;

------------------------------------------------------------------
  prcs_carryout_x_o:process(carryout_o_mux)
  begin
     if(USE_SIMD = "ONE48") then
        carryout_x_o(3) <= carryout_o_mux(3);
     elsif(USE_SIMD = "TWO24") then
        carryout_x_o(3) <= carryout_o_mux(3);
        carryout_x_o(1) <= carryout_o_mux(1);
     elsif(USE_SIMD = "FOUR12") then
        carryout_x_o(3) <= carryout_o_mux(3);
        carryout_x_o(2) <= carryout_o_mux(2);
        carryout_x_o(1) <= carryout_o_mux(1);
        carryout_x_o(0) <= carryout_o_mux(0);
     end if;
  end process prcs_carryout_x_o;

------------------------------------------------------------------
  prcs_carrycascout_mux:process(carrycascout_o, carrycascout_o_reg)
  begin
     case PREG is
       when 0 => carrycascout_o_mux <= carrycascout_o;
       when 1 => carrycascout_o_mux <= carrycascout_o_reg;
       when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for PREG are 0 or 1"
           severity Failure;
     end case;
   
  end process prcs_carrycascout_mux;
------------------------------------------------------------------
-- CR 219047 (2)
  prcs_multsignout_o_opmode:process(mult_o_mux(MSB_A_MULT+MSB_B_MULT+1), opmode_o_mux(3 downto 0))
  begin
    if(opmode_o_mux(3 downto 0) = "0101") then
       multsignout_o_opmode <= mult_o_mux(MSB_A_MULT+MSB_B_MULT+1);
    else
       multsignout_o_opmode <= 'X';
    end if;
  end process prcs_multsignout_o_opmode;

  prcs_multsignout_o_mux:process(multsignout_o_opmode, multsignout_o_reg)
  begin
     case PREG is
       when 0 => multsignout_o_mux <= multsignout_o_opmode;
-- CR 232275
       when 1 => multsignout_o_mux <= multsignout_o_reg;
       when others => null;
--           assert false
--           report "Attribute Syntax Error: The allowed values for PREG are 0 or 1"
--           severity Failure;
     end case;
   
  end process prcs_multsignout_o_mux;
--####################################################################
--####################################################################
--####################################################################
--#####                 PCOUT and MULTSIGNOUT                    #####
--####################################################################
  prcs_qp_reg:process(CLK_dly, GSR_dly)
  begin
      if(GSR_dly = '1') then
         qp_o_reg <=  ( others => '0');
         multsignout_o_reg <= '0';
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if((RSTP_dly = '1') or 
               ((AUTORESET_PATTERN_DETECT) and (
                ((AUTORESET_PATTERN_DETECT_OPTINV = "MATCH") and pdet_o_reg1 = '1') or 
                ((AUTORESET_PATTERN_DETECT_OPTINV = "NOT_MATCH") and (pdet_o_reg2 = '1' and pdet_o_reg1 = '0')))
               )
              ) then
               qp_o_reg <= ( others => '0');
               multsignout_o_reg <= '0';
            elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then
               qp_o_reg <= alu_o;
               multsignout_o_reg <= mult_o_reg((MSB_A_MULT+MSB_B_MULT+1));
            end if;
         end if;
      end if;
  end process prcs_qp_reg;
------------------------------------------------------------------
  prcs_qp_mux:process(alu_o, qp_o_reg)
  begin
     case PREG is
       when 0 => qp_o_mux <= alu_o;
       when 1 => qp_o_mux <= qp_o_reg;
       when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for PREG are 0 or 1"
           severity Failure;
     end case;
   
  end process prcs_qp_mux;
--####################################################################
--#####                    Pattern Detector                      #####
--####################################################################
  prcs_sel_pattern_detect:process(alu_o, qc_o_mux)
  begin

     -- Select the pattern
     if((SEL_PATTERN = "PATTERN") or (SEL_PATTERN = "pattern")) then
         pattern_qp <= To_StdLogicVector(PATTERN);
     elsif((SEL_PATTERN = "C") or (SEL_PATTERN = "c")) then
         pattern_qp <= qc_o_mux;
     else 
         assert false
         report "Attribute Syntax Error: The attribute SEL_PATTERN on DSP48_ALU is incorrect. Legal values for this attribute are PATTERN or C"
         severity Failure;
     end if;

     -- Select the mask  -- if ROUNDING MASK set, use rounding mode, else use SEL_MASK
     if((SEL_ROUNDING_MASK = "SEL_MASK") or (SEL_ROUNDING_MASK = "sel_mask")) then
         if((SEL_MASK = "MASK") or (SEL_MASK = "mask")) then
             mask_qp <= To_StdLogicVector(MASK);
         elsif((SEL_MASK = "C") or (SEL_MASK = "c")) then
             mask_qp <= qc_o_mux;
         else
           assert false
           report "Attribute Syntax Error: The attribute SEL_MASK on DSP48_ALU is incorrect. Legal values for this attribute are MASK or C"
           severity Failure;
         end if;
     elsif((SEL_ROUNDING_MASK = "MODE1") or (SEL_ROUNDING_MASK = "mode1")) then
         mask_qp <=   To_StdLogicVector((To_bitvector( not qc_o_mux)) sla 1) ;
         mask_qp (0) <= '0';
     elsif((SEL_ROUNDING_MASK = "MODE2") or (SEL_ROUNDING_MASK = "mode2")) then
         mask_qp <=   To_StdLogicVector((To_bitvector( not qc_o_mux)) sla 2) ;
         mask_qp (1 downto 0) <= (others => '0');
     else
         assert false
         report "Attribute Syntax Error: The attribute SEL_ROUNDING_MASK on DSP48_ALU is incorrect. Legal values for this attribute are SEL_MASK or MODE1 or MODE2."
         severity Failure;
     end if;
     
  end process prcs_sel_pattern_detect;


---------------------------------------------------------------

  prcs_pdet:process(alu_o, mask_qp, pattern_qp, GSR_dly )
  begin
       if(((alu_o or mask_qp) = (pattern_qp or mask_qp)) and (GSR_dly = '0'))then 
          pdet_o <= '1';
       else
          pdet_o <= '0';
       end if;

       if(((alu_o or mask_qp) = ((NOT pattern_qp) or mask_qp)) and (GSR_dly = '0')) then 
          pdetb_o <= '1';
       else
          pdetb_o <= '0';
       end if;

  end process prcs_pdet;

---------------------------------------------------------------

  prcs_pdet_reg:process(CLK_dly, GSR_dly)
  variable pdetb_reg1_var, pdetb_reg2_var, pdet_reg1_var, pdet_reg2_var : std_ulogic := '0';  
  begin
      if(GSR_dly = '1') then
         pdetb_o_reg1 <= '0';
         pdetb_o_reg2 <= '0';
         pdet_o_reg1  <= '0';
         pdet_o_reg2  <= '0';

         pdetb_reg1_var := '0';
         pdetb_reg2_var := '0';
         pdet_reg1_var  := '0';
         pdet_reg2_var  := '0';
      elsif (GSR_dly = '0') then
         if(rising_edge(CLK_dly)) then
            if((RSTP_dly = '1') or 
               ((AUTORESET_PATTERN_DETECT) and (
                ((AUTORESET_PATTERN_DETECT_OPTINV = "MATCH") and pdet_o_reg1 = '1') or 
                ((AUTORESET_PATTERN_DETECT_OPTINV = "NOT_MATCH") and (pdet_o_reg2 = '1' and pdet_o_reg1 = '0')))
               )
              ) then
               pdetb_o_reg1 <= '0';
               pdetb_o_reg2 <= '0';
               pdet_o_reg1  <= '0';
               pdet_o_reg2  <= '0';

               pdetb_reg1_var := '0';
               pdetb_reg2_var := '0';
               pdet_reg1_var  := '0';
               pdet_reg2_var  := '0';
            elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then
               pdetb_reg2_var := pdetb_reg1_var;
               pdetb_reg1_var := pdetb_o;

               pdet_reg2_var := pdet_reg1_var;
               pdet_reg1_var := pdet_o;

               pdetb_o_reg1 <= pdetb_reg1_var;
               pdetb_o_reg2 <= pdetb_reg2_var;
               pdet_o_reg1  <= pdet_reg1_var;
               pdet_o_reg2  <= pdet_reg2_var;

            end if;
         end if;
      end if;
  end process prcs_pdet_reg;

--####################################################################
--#####                 Underflow / Overflow                     #####
--####################################################################
  prcs_uflow_oflow:process(pdet_o_reg1 , pdet_o_reg2 , pdetb_o_reg1 , pdetb_o_reg2)
  begin
--    if(((AUTORESET_PATTERN_DETECT) and (
--       ((AUTORESET_PATTERN_DETECT_OPTINV = "MATCH") and (pdet_o_reg1 = '1'))  or
--       ((AUTORESET_PATTERN_DETECT_OPTINV = "NOT_MATCH") and ((pdet_o_reg2 = '1') and (pdet_o_reg1 = '0'))))
--      )) then
--       underflow_o <= '0';
--       overflow_o  <= '0';
--    else
--       overflow_o  <= pdet_o_reg2   AND  (NOT pdet_o_reg1)  AND  (NOT pdetb_o_reg1);
--       underflow_o <= pdetb_o_reg2  AND  (NOT pdet_o_reg1)  AND (NOT pdetb_o_reg1);
--    end if;
    if(GSR_dly = '1') then
        overflow_o  <= '0';
        underflow_o <= '0';
    elsif(USE_PATTERN_DETECT = "NO_PATDET") then
        overflow_o  <= 'X';
        underflow_o <= 'X';
    elsif(PREG = 0) then
          overflow_o  <= 'X';
          underflow_o <= 'X';
    elsif(PREG = 1) then
          overflow_o  <= pdet_o_reg2   AND  (NOT pdet_o_reg1)  AND  (NOT pdetb_o_reg1);
          underflow_o <= pdetb_o_reg2  AND  (NOT pdet_o_reg1)  AND (NOT pdetb_o_reg1);
    end if;

  end process prcs_uflow_oflow;
--####################################################################
--#####                 OPMODE DRC                               #####
--####################################################################
--  prcs_opmode_drc:process(ping_opmode_drc_check, alumode_o_mux, opmode_o_mux, carryinsel_o_mux)

--      opmode_valid_flg <= opmode_valid_var;

--  end process prcs_opmode_drc;
--####################################################################
--#####                   ZERO_DELAY_OUTPUTS                     #####
--####################################################################
  prcs_zero_delay_outputs:process(qacout_o_mux, qbcout_o_mux, carryout_x_o, carrycascout_o_mux,
                                  overflow_o, qp_o_mux, pdet_o, pdetb_o,
                                  pdet_o_reg1, pdetb_o_reg1,
                                  pdet_o_reg2, pdetb_o_reg2,
                                  underflow_o, multsignout_o_mux, opmode_valid_flg, alumode_valid_flg)
  begin
    ACOUT_zd          <= qacout_o_mux;
    BCOUT_zd          <= qbcout_o_mux;
    OVERFLOW_zd       <= overflow_o;
    UNDERFLOW_zd      <= underflow_o;
    P_zd              <= qp_o_mux;
    PCOUT_zd          <= qp_o_mux;
    MULTSIGNOUT_zd    <= multsignout_o_mux;

    if(((AUTORESET_PATTERN_DETECT) and (
       ((AUTORESET_PATTERN_DETECT_OPTINV = "MATCH") and (pdet_o_reg1 = '1'))  or
       ((AUTORESET_PATTERN_DETECT_OPTINV = "NOT_MATCH") and ((pdet_o_reg2 = '1') and (pdet_o_reg1 = '0'))))
      )) then
      CARRYCASCOUT_zd   <= '0';
      CARRYOUT_zd       <= (others => '0');
    else
      CARRYCASCOUT_zd   <= carrycascout_o_mux;   
      CARRYOUT_zd       <= carryout_x_o; 
    end if;

    if((USE_PATTERN_DETECT = "NO_PATDET") or (not opmode_valid_flg) or (not alumode_valid_flg)) then
       PATTERNBDETECT_zd <= 'X';
       PATTERNDETECT_zd  <= 'X';
    elsif (PREG = 0) then
          PATTERNBDETECT_zd <= pdetb_o;
          PATTERNDETECT_zd  <= pdet_o;
    elsif(PREG = 1) then
          PATTERNBDETECT_zd <= pdetb_o_reg1;
          PATTERNDETECT_zd  <= pdet_o_reg1;
    end if;

  end process prcs_zero_delay_outputs;

end generate; 
--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(ACOUT_zd, BCOUT_zd, CARRYCASCOUT_zd, CARRYOUT_zd,
                      OVERFLOW_zd, P_zd, PATTERNBDETECT_zd, PATTERNDETECT_zd,
                      PCOUT_zd, UNDERFLOW_zd, MULTSIGNOUT_zd)
  begin
      ACOUT             <= ACOUT_zd after SYNC_PATH_DELAY;
      BCOUT             <= BCOUT_zd after SYNC_PATH_DELAY;
      CARRYCASCOUT      <= CARRYCASCOUT_zd after SYNC_PATH_DELAY;
      CARRYOUT          <= CARRYOUT_zd after SYNC_PATH_DELAY;
      OVERFLOW          <= OVERFLOW_zd after SYNC_PATH_DELAY;
      P                 <= P_zd after SYNC_PATH_DELAY;
      PATTERNBDETECT    <= PATTERNBDETECT_zd after SYNC_PATH_DELAY;
      PATTERNDETECT     <= PATTERNDETECT_zd after SYNC_PATH_DELAY;
      PCOUT             <= PCOUT_zd after SYNC_PATH_DELAY;
      UNDERFLOW         <= UNDERFLOW_zd after SYNC_PATH_DELAY;

      MULTSIGNOUT       <= MULTSIGNOUT_zd after SYNC_PATH_DELAY;
  end process prcs_output;



end DSP48E_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/fifo18_36.vhd,v 1.7 2007/06/15 21:01:09 wloo Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2005 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  18K-Bit FIFO
-- /___/   /\     Filename : FIFO18_36.vhd
-- \   \  /  \    Timestamp : Tues October 18 16:43:59 PST 2005
--  \___\/\___\
--
-- Revision:
--    10/18/05 - Initial version.
--    06/14/07 - Implemented high performace version of the model.
-- End Revision

----- CELL FIFO18_36 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity FIFO18_36 is
generic (

    ALMOST_FULL_OFFSET      : bit_vector := X"080";
    ALMOST_EMPTY_OFFSET     : bit_vector := X"080"; 
    DO_REG                  : integer    := 1;
    EN_SYN                  : boolean    := FALSE;
    FIRST_WORD_FALL_THROUGH : boolean    := FALSE;
    SIM_MODE                : string     := "SAFE"
    
  );

port (

    ALMOSTEMPTY : out std_ulogic;
    ALMOSTFULL  : out std_ulogic;
    DO          : out std_logic_vector (31 downto 0);
    DOP         : out std_logic_vector (3 downto 0);
    EMPTY       : out std_ulogic;
    FULL        : out std_ulogic;
    RDCOUNT     : out std_logic_vector (8 downto 0);
    RDERR       : out std_ulogic;
    WRCOUNT     : out std_logic_vector (8 downto 0);
    WRERR       : out std_ulogic;

    DI          : in  std_logic_vector (31 downto 0);
    DIP         : in  std_logic_vector (3 downto 0);
    RDCLK       : in  std_ulogic;
    RDEN        : in  std_ulogic;
    RST         : in  std_ulogic;
    WRCLK       : in  std_ulogic;
    WREN        : in  std_ulogic    
  );
end FIFO18_36;
                                                                        
architecture FIFO18_36_V of FIFO18_36 is

  component AFIFO36_INTERNAL

      generic(
        ALMOST_FULL_OFFSET      : bit_vector := X"0080";
        ALMOST_EMPTY_OFFSET     : bit_vector := X"0080"; 
        DATA_WIDTH              : integer    := 4;
        DO_REG                  : integer    := 1;
        EN_ECC_READ : boolean := FALSE;
        EN_ECC_WRITE : boolean := FALSE;    
        EN_SYN                  : boolean    := FALSE;
        FIFO_SIZE               : integer    := 36;
        FIRST_WORD_FALL_THROUGH : boolean    := FALSE;
        SIM_MODE                : string     := "SAFE"
        );

      port(
        ALMOSTEMPTY : out std_ulogic;
        ALMOSTFULL  : out std_ulogic;
        DBITERR       : out std_ulogic;
        DO          : out std_logic_vector (63 downto 0);
        DOP         : out std_logic_vector (7 downto 0);
        ECCPARITY   : out std_logic_vector (7 downto 0);
        EMPTY       : out std_ulogic;
        FULL        : out std_ulogic;
        RDCOUNT     : out std_logic_vector (12 downto 0);
        RDERR       : out std_ulogic;
        SBITERR     : out std_ulogic;
        WRCOUNT     : out std_logic_vector (12 downto 0);
        WRERR       : out std_ulogic;

        DI          : in  std_logic_vector (63 downto 0);
        DIP         : in  std_logic_vector (7 downto 0);
        RDCLK       : in  std_ulogic;
        RDRCLK       : in  std_ulogic;
        RDEN        : in  std_ulogic;
        RST         : in  std_ulogic;
        WRCLK       : in  std_ulogic;
        WREN        : in  std_ulogic
        );
  end component;

    
  constant SYNC_PATH_DELAY : time := 100 ps;
  signal GND_4 : std_logic_vector(3 downto 0) := (others => '0');
  signal GND_32 : std_logic_vector(31 downto 0) := (others => '0');
  signal OPEN_4 : std_logic_vector(3 downto 0);
  signal OPEN_32 : std_logic_vector(31 downto 0);
  signal OPEN_8 : std_logic_vector(7 downto 0);
  signal do_dly : std_logic_vector(31 downto 0) :=  (others => '0');
  signal dop_dly : std_logic_vector(3 downto 0) :=  (others => '0');
  signal almostfull_dly : std_ulogic := '0';
  signal almostempty_dly : std_ulogic := '0';
  signal empty_dly : std_ulogic := '0';
  signal full_dly : std_ulogic := '0';
  signal rderr_dly : std_ulogic := '0';
  signal wrerr_dly : std_ulogic := '0';
  signal rdcount_dly : std_logic_vector(8 downto 0) :=  (others => '0');
  signal wrcount_dly : std_logic_vector(8 downto 0) :=  (others => '0');


begin

FIFO18_36_inst : AFIFO36_INTERNAL
  generic map (
    ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
    ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
    DATA_WIDTH => 36,
    DO_REG => DO_REG,
    EN_SYN => EN_SYN,
    FIFO_SIZE => 18,
    SIM_MODE => SIM_MODE,
    FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH
    )

  port map (
    DO(31 downto 0) => do_dly,
    DO(63 downto 32) => OPEN_32,
    DOP(3 downto 0) => dop_dly,
    DOP(7 downto 4) => OPEN_4,
    ALMOSTEMPTY => almostempty_dly,
    ALMOSTFULL => almostfull_dly,
    ECCPARITY => OPEN_8,
    EMPTY => empty_dly,
    FULL => full_dly,
    RDCOUNT(8 downto 0) => rdcount_dly,
    RDCOUNT(12 downto 9) => OPEN_4,
    WRCOUNT(8 downto 0) => wrcount_dly,
    WRCOUNT(12 downto 9) => OPEN_4,
    RDERR => rderr_dly,
    SBITERR => OPEN,
    DBITERR => OPEN,
    WRERR => wrerr_dly,
    DI(31 downto 0) => DI,
    DI(63 downto 32) => GND_32,
    DIP(3 downto 0) => DIP,
    DIP(7 downto 4) => GND_4,
    WREN => WREN,
    RDEN => RDEN,
    RDCLK => RDCLK,
    RDRCLK => RDCLK,
    WRCLK => WRCLK,
    RST => RST
    );

   prcs_output_wtiming: process (do_dly, dop_dly, almostempty_dly, almostfull_dly, empty_dly, full_dly, rdcount_dly, wrcount_dly, rderr_dly, wrerr_dly)
   begin  -- process prcs_output_wtiming

     ALMOSTEMPTY <= almostempty_dly after SYNC_PATH_DELAY;
     ALMOSTFULL <= almostfull_dly after SYNC_PATH_DELAY;
     empty <= empty_dly after SYNC_PATH_DELAY;
     full <= full_dly after SYNC_PATH_DELAY;
     DO <= do_dly after SYNC_PATH_DELAY;
     DOP <= dop_dly after SYNC_PATH_DELAY;
     RDCOUNT <= rdcount_dly after SYNC_PATH_DELAY;
     WRCOUNT <= wrcount_dly after SYNC_PATH_DELAY;
     RDERR <= rderr_dly after SYNC_PATH_DELAY;
     WRERR <= wrerr_dly after SYNC_PATH_DELAY;
     
   end process prcs_output_wtiming;

end FIFO18_36_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/fifo18.vhd,v 1.7 2007/06/15 21:01:09 wloo Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2005 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  18K-Bit FIFO
-- /___/   /\     Filename : FIFO18.vhd
-- \   \  /  \    Timestamp : Tues October 18 16:43:59 PST 2005
--  \___\/\___\
--
-- Revision:
--    10/18/05 - Initial version.
--    06/14/07 - Implemented high performace version of the model.
-- End Revision

----- CELL FIFO18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.VCOMPONENTS.all;
use unisim.vpkg.all;

entity FIFO18 is
generic (

    ALMOST_FULL_OFFSET      : bit_vector := X"080";
    ALMOST_EMPTY_OFFSET     : bit_vector := X"080"; 
    DATA_WIDTH              : integer    := 4;
    DO_REG                  : integer    := 1;
    EN_SYN                  : boolean    := FALSE;
    FIRST_WORD_FALL_THROUGH : boolean    := FALSE;
    SIM_MODE                : string     := "SAFE"
    
  );

port (

    ALMOSTEMPTY : out std_ulogic;
    ALMOSTFULL  : out std_ulogic;
    DO          : out std_logic_vector (15 downto 0);
    DOP         : out std_logic_vector (1 downto 0);
    EMPTY       : out std_ulogic;
    FULL        : out std_ulogic;
    RDCOUNT     : out std_logic_vector (11 downto 0);
    RDERR       : out std_ulogic;
    WRCOUNT     : out std_logic_vector (11 downto 0);
    WRERR       : out std_ulogic;

    DI          : in  std_logic_vector (15 downto 0);
    DIP         : in  std_logic_vector (1 downto 0);
    RDCLK       : in  std_ulogic;
    RDEN        : in  std_ulogic;
    RST         : in  std_ulogic;
    WRCLK       : in  std_ulogic;
    WREN        : in  std_ulogic    
  );
end FIFO18;
                                                                        
architecture FIFO18_V of FIFO18 is

  component AFIFO36_INTERNAL

      generic(
        ALMOST_FULL_OFFSET      : bit_vector := X"0080";
        ALMOST_EMPTY_OFFSET     : bit_vector := X"0080"; 
        DATA_WIDTH              : integer    := 4;
        DO_REG                  : integer    := 1;
        EN_ECC_READ : boolean := FALSE;
        EN_ECC_WRITE : boolean := FALSE;    
        EN_SYN                  : boolean    := FALSE;
        FIFO_SIZE               : integer    := 36;
        FIRST_WORD_FALL_THROUGH : boolean    := FALSE;
        SIM_MODE                : string     := "SAFE"
        );

      port(
        ALMOSTEMPTY : out std_ulogic;
        ALMOSTFULL  : out std_ulogic;
        DBITERR       : out std_ulogic;
        DO          : out std_logic_vector (63 downto 0);
        DOP         : out std_logic_vector (7 downto 0);
        ECCPARITY   : out std_logic_vector (7 downto 0);
        EMPTY       : out std_ulogic;
        FULL        : out std_ulogic;
        RDCOUNT     : out std_logic_vector (12 downto 0);
        RDERR       : out std_ulogic;
        SBITERR     : out std_ulogic;
        WRCOUNT     : out std_logic_vector (12 downto 0);
        WRERR       : out std_ulogic;

        DI          : in  std_logic_vector (63 downto 0);
        DIP         : in  std_logic_vector (7 downto 0);
        RDCLK       : in  std_ulogic;
        RDRCLK       : in  std_ulogic;
        RDEN        : in  std_ulogic;
        RST         : in  std_ulogic;
        WRCLK       : in  std_ulogic;
        WREN        : in  std_ulogic
        );
  end component;

    
  constant SYNC_PATH_DELAY : time := 100 ps;
  signal GND_6 : std_logic_vector(5 downto 0) := (others => '0');
  signal GND_48 : std_logic_vector(47 downto 0) := (others => '0');
  signal OPEN_1 : std_logic_vector(0 downto 0);
  signal OPEN_6 : std_logic_vector(5 downto 0);
  signal OPEN_48 : std_logic_vector(47 downto 0);
  signal OPEN_8 : std_logic_vector(7 downto 0);
  signal do_dly : std_logic_vector(15 downto 0) :=  (others => '0');
  signal dop_dly : std_logic_vector(1 downto 0) :=  (others => '0');
  signal almostfull_dly : std_ulogic := '0';
  signal almostempty_dly : std_ulogic := '0';
  signal empty_dly : std_ulogic := '0';
  signal full_dly : std_ulogic := '0';
  signal rderr_dly : std_ulogic := '0';
  signal wrerr_dly : std_ulogic := '0';
  signal rdcount_dly : std_logic_vector(11 downto 0) :=  (others => '0');
  signal wrcount_dly : std_logic_vector(11 downto 0) :=  (others => '0');


begin

FIFO18_inst : AFIFO36_INTERNAL
  generic map (
    ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
    ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
    DATA_WIDTH => DATA_WIDTH,
    DO_REG => DO_REG,
    EN_SYN => EN_SYN,
    FIFO_SIZE => 18,
    SIM_MODE => SIM_MODE,
    FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH
    )

  port map (
    DO(15 downto 0) => do_dly,
    DO(63 downto 16) => OPEN_48,
    DOP(1 downto 0) => dop_dly,
    DOP(7 downto 2) => OPEN_6,
    ALMOSTEMPTY => almostempty_dly,
    ALMOSTFULL => almostfull_dly,
    ECCPARITY => OPEN_8,
    EMPTY => empty_dly,
    FULL => full_dly,
    RDCOUNT(11 downto 0) => rdcount_dly,
    RDCOUNT(12 downto 12) => OPEN_1,
    WRCOUNT(11 downto 0) => wrcount_dly,
    WRCOUNT(12 downto 12) => OPEN_1,
    RDERR => rderr_dly,
    SBITERR => OPEN,
    DBITERR => OPEN,
    WRERR => wrerr_dly,
    DI(15 downto 0) => DI,
    DI(63 downto 16) => GND_48,
    DIP(1 downto 0) => DIP,
    DIP(7 downto 2) => GND_6,
    WREN => WREN,
    RDEN => RDEN,
    RDCLK => RDCLK,
    RDRCLK => RDCLK,
    WRCLK => WRCLK,
    RST => RST
    );


   prcs_initialize:process
     variable first_time        : boolean    := true;

     begin
       if (first_time) then
         case DATA_WIDTH is
            when 4 | 9 | 18 => null;
            when others =>
                    GenericValueCheckMessage
                      ( HeaderMsg            => " Attribute Syntax Error ",
                        GenericName          => " DATA_WIDTH ",
                        EntityName           => "FIFO18",
                        GenericValue         => DATA_WIDTH,
                        Unit                 => "",
                        ExpectedValueMsg     => " The Legal values for this attribute are ",
                        ExpectedGenericValue => " 4, 9 and 18 ",
                        TailMsg              => "",
                        MsgSeverity          => error
                        );
         end case;
         first_time := false;
       end if;
       wait;
     end process prcs_initialize;




   prcs_output_wtiming: process (do_dly, dop_dly, almostempty_dly, almostfull_dly, empty_dly, full_dly, rdcount_dly, wrcount_dly, rderr_dly, wrerr_dly)
   begin  -- process prcs_output_wtiming

     ALMOSTEMPTY <= almostempty_dly after SYNC_PATH_DELAY;
     ALMOSTFULL <= almostfull_dly after SYNC_PATH_DELAY;
     empty <= empty_dly after SYNC_PATH_DELAY;
     full <= full_dly after SYNC_PATH_DELAY;
     DO <= do_dly after SYNC_PATH_DELAY;
     DOP <= dop_dly after SYNC_PATH_DELAY;
     RDCOUNT <= rdcount_dly after SYNC_PATH_DELAY;
     WRCOUNT <= wrcount_dly after SYNC_PATH_DELAY;
     RDERR <= rderr_dly after SYNC_PATH_DELAY;
     WRERR <= wrerr_dly after SYNC_PATH_DELAY;
     
   end process prcs_output_wtiming;

end FIFO18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/fifo36_72_exp.vhd,v 1.7 2007/06/15 21:01:09 wloo Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2005 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  36K-Bit FIFO
-- /___/   /\     Filename : FIFO36_72_EXP.vhd
-- \   \  /  \    Timestamp : Tues October 18 16:43:59 PST 2005
--  \___\/\___\
--
-- Revision:
--    10/18/05 - Initial version.
--    06/14/07 - Implemented high performace version of the model.
-- End Revision

----- CELL FIFO36_72_EXP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity FIFO36_72_EXP is
generic (

    ALMOST_FULL_OFFSET      : bit_vector := X"080";
    ALMOST_EMPTY_OFFSET     : bit_vector := X"080"; 
    DO_REG                  : integer    := 1;
    EN_ECC_READ             : boolean    := FALSE;
    EN_ECC_WRITE            : boolean    := FALSE;  
    EN_SYN                  : boolean    := FALSE;
    FIRST_WORD_FALL_THROUGH : boolean    := FALSE;
    SIM_MODE                : string     := "SAFE"
    
  );

port (

    ALMOSTEMPTY : out std_ulogic;
    ALMOSTFULL  : out std_ulogic;
    DBITERR     : out std_ulogic;
    DO          : out std_logic_vector (63 downto 0);
    DOP         : out std_logic_vector (7 downto 0);
    ECCPARITY   : out std_logic_vector (7 downto 0);
    EMPTY       : out std_ulogic;
    FULL        : out std_ulogic;
    RDCOUNT     : out std_logic_vector (12 downto 0);
    RDERR       : out std_ulogic;
    SBITERR     : out std_ulogic;
    WRCOUNT     : out std_logic_vector (12 downto 0);
    WRERR       : out std_ulogic;

    DI          : in  std_logic_vector (63 downto 0);
    DIP         : in  std_logic_vector (7 downto 0);
    RDCLKL      : in  std_ulogic;
    RDCLKU      : in  std_ulogic;
    RDEN        : in  std_ulogic;
    RDRCLKL     : in  std_ulogic;
    RDRCLKU     : in  std_ulogic;
    RST         : in  std_ulogic;
    WRCLKL      : in  std_ulogic;
    WRCLKU      : in  std_ulogic;    
    WREN        : in  std_ulogic    
  );
end FIFO36_72_EXP;
                                                                        
architecture FIFO36_72_EXP_V of FIFO36_72_EXP is

  component AFIFO36_INTERNAL

      generic(
        ALMOST_FULL_OFFSET      : bit_vector := X"0080";
        ALMOST_EMPTY_OFFSET     : bit_vector := X"0080"; 
        DATA_WIDTH              : integer    := 4;
        DO_REG                  : integer    := 1;
        EN_ECC_READ : boolean := FALSE;
        EN_ECC_WRITE : boolean := FALSE;    
        EN_SYN                  : boolean    := FALSE;
        FIFO_SIZE               : integer    := 36;
        FIRST_WORD_FALL_THROUGH : boolean    := FALSE;
        SIM_MODE                : string     := "SAFE"
        );

      port(
        ALMOSTEMPTY : out std_ulogic;
        ALMOSTFULL  : out std_ulogic;
        DBITERR       : out std_ulogic;
        DO          : out std_logic_vector (63 downto 0);
        DOP         : out std_logic_vector (7 downto 0);
        ECCPARITY   : out std_logic_vector (7 downto 0);
        EMPTY       : out std_ulogic;
        FULL        : out std_ulogic;
        RDCOUNT     : out std_logic_vector (12 downto 0);
        RDERR       : out std_ulogic;
        SBITERR     : out std_ulogic;
        WRCOUNT     : out std_logic_vector (12 downto 0);
        WRERR       : out std_ulogic;

        DI          : in  std_logic_vector (63 downto 0);
        DIP         : in  std_logic_vector (7 downto 0);
        RDCLK       : in  std_ulogic;
        RDRCLK       : in  std_ulogic;
        RDEN        : in  std_ulogic;
        RST         : in  std_ulogic;
        WRCLK       : in  std_ulogic;
        WREN        : in  std_ulogic
        );
  end component;

    
  constant SYNC_PATH_DELAY : time := 100 ps;
  signal do_dly : std_logic_vector(63 downto 0) :=  (others => '0');
  signal dop_dly : std_logic_vector(7 downto 0) :=  (others => '0');
  signal almostfull_dly : std_ulogic := '0';
  signal almostempty_dly : std_ulogic := '0';
  signal empty_dly : std_ulogic := '0';
  signal full_dly : std_ulogic := '0';
  signal rderr_dly : std_ulogic := '0';
  signal wrerr_dly : std_ulogic := '0';
  signal rdcount_dly : std_logic_vector(12 downto 0) :=  (others => '0');
  signal wrcount_dly : std_logic_vector(12 downto 0) :=  (others => '0');
  signal sbiterr_dly : std_ulogic := '0';
  signal dbiterr_dly : std_ulogic := '0';
  signal eccparity_dly : std_logic_vector(7 downto 0) :=  (others => '0');
  
begin

FIFO36_72_EXP_inst : AFIFO36_INTERNAL
  generic map (
    ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
    ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
    DATA_WIDTH => 72,
    DO_REG => DO_REG,
    EN_ECC_READ => EN_ECC_READ, 
    EN_ECC_WRITE => EN_ECC_WRITE,
    EN_SYN => EN_SYN,
    SIM_MODE => SIM_MODE,
    FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH
    )

  port map (
    DO => do_dly,
    DOP => dop_dly,
    ALMOSTEMPTY => almostempty_dly,
    ALMOSTFULL => almostfull_dly,
    ECCPARITY => eccparity_dly,
    EMPTY => empty_dly,
    FULL => full_dly,
    RDCOUNT => rdcount_dly,
    WRCOUNT => wrcount_dly,
    RDERR => rderr_dly,
    SBITERR => sbiterr_dly,
    DBITERR => dbiterr_dly,
    WRERR => wrerr_dly,
    DI => DI,
    DIP => DIP,
    WREN => WREN,
    RDEN => RDEN,
    RDCLK => RDCLKL,
    RDRCLK => RDRCLKL,
    WRCLK => WRCLKL,
    RST => RST
    );

   prcs_output_wtiming: process (do_dly, dop_dly, almostempty_dly, almostfull_dly,
                                 empty_dly, full_dly, rdcount_dly, wrcount_dly, rderr_dly,
                                 wrerr_dly, eccparity_dly, sbiterr_dly, dbiterr_dly)
   begin  -- process prcs_output_wtiming

     ALMOSTEMPTY <= almostempty_dly after SYNC_PATH_DELAY;
     ALMOSTFULL <= almostfull_dly after SYNC_PATH_DELAY;
     empty <= empty_dly after SYNC_PATH_DELAY;
     full <= full_dly after SYNC_PATH_DELAY;
     DO <= do_dly after SYNC_PATH_DELAY;
     DOP <= dop_dly after SYNC_PATH_DELAY;
     RDCOUNT <= rdcount_dly after SYNC_PATH_DELAY;
     WRCOUNT <= wrcount_dly after SYNC_PATH_DELAY;
     RDERR <= rderr_dly after SYNC_PATH_DELAY;
     WRERR <= wrerr_dly after SYNC_PATH_DELAY;
     ECCPARITY <= eccparity_dly after SYNC_PATH_DELAY;
     SBITERR <= sbiterr_dly after SYNC_PATH_DELAY;
     DBITERR <= dbiterr_dly after SYNC_PATH_DELAY;

   end process prcs_output_wtiming;

end FIFO36_72_EXP_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/fifo36_72.vhd,v 1.9 2007/06/15 21:01:09 wloo Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2005 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  36K-Bit FIFO
-- /___/   /\     Filename : FIFO36_72.vhd
-- \   \  /  \    Timestamp : Tues October 18 16:43:59 PST 2005
--  \___\/\___\
--
-- Revision:
--    10/18/05 - Initial version.
--    06/14/07 - Implemented high performace version of the model.
-- End Revision

----- CELL FIFO36_72 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity FIFO36_72 is
generic (

    ALMOST_FULL_OFFSET      : bit_vector := X"080";
    ALMOST_EMPTY_OFFSET     : bit_vector := X"080"; 
    DO_REG                  : integer    := 1;
    EN_ECC_READ             : boolean    := FALSE;
    EN_ECC_WRITE            : boolean    := FALSE;  
    EN_SYN                  : boolean    := FALSE;
    FIRST_WORD_FALL_THROUGH : boolean    := FALSE;
    SIM_MODE                : string     := "SAFE"
    
  );

port (

    ALMOSTEMPTY : out std_ulogic;
    ALMOSTFULL  : out std_ulogic;
    DBITERR     : out std_ulogic;
    DO          : out std_logic_vector (63 downto 0);
    DOP         : out std_logic_vector (7 downto 0);
    ECCPARITY   : out std_logic_vector (7 downto 0);
    EMPTY       : out std_ulogic;
    FULL        : out std_ulogic;
    RDCOUNT     : out std_logic_vector (8 downto 0);
    RDERR       : out std_ulogic;
    SBITERR     : out std_ulogic;
    WRCOUNT     : out std_logic_vector (8 downto 0);
    WRERR       : out std_ulogic;

    DI          : in  std_logic_vector (63 downto 0);
    DIP         : in  std_logic_vector (7 downto 0);
    RDCLK       : in  std_ulogic;
    RDEN        : in  std_ulogic;
    RST         : in  std_ulogic;
    WRCLK       : in  std_ulogic;
    WREN        : in  std_ulogic    
  );
end FIFO36_72;
                                                                        
architecture FIFO36_72_V of FIFO36_72 is

  component AFIFO36_INTERNAL

      generic(
        ALMOST_FULL_OFFSET      : bit_vector := X"0080";
        ALMOST_EMPTY_OFFSET     : bit_vector := X"0080"; 
        DATA_WIDTH              : integer    := 4;
        DO_REG                  : integer    := 1;
        EN_ECC_READ             : boolean    := FALSE;
        EN_ECC_WRITE            : boolean    := FALSE;    
        EN_SYN                  : boolean    := FALSE;
        FIFO_SIZE               : integer    := 36;
        FIRST_WORD_FALL_THROUGH : boolean    := FALSE;
        SIM_MODE                : string     := "SAFE"
        );

      port(
        ALMOSTEMPTY : out std_ulogic;
        ALMOSTFULL  : out std_ulogic;
        DBITERR       : out std_ulogic;
        DO          : out std_logic_vector (63 downto 0);
        DOP         : out std_logic_vector (7 downto 0);
        ECCPARITY   : out std_logic_vector (7 downto 0);
        EMPTY       : out std_ulogic;
        FULL        : out std_ulogic;
        RDCOUNT     : out std_logic_vector (12 downto 0);
        RDERR       : out std_ulogic;
        SBITERR     : out std_ulogic;
        WRCOUNT     : out std_logic_vector (12 downto 0);
        WRERR       : out std_ulogic;

        DI          : in  std_logic_vector (63 downto 0);
        DIP         : in  std_logic_vector (7 downto 0);
        RDCLK       : in  std_ulogic;
        RDRCLK       : in  std_ulogic;
        RDEN        : in  std_ulogic;
        RST         : in  std_ulogic;
        WRCLK       : in  std_ulogic;
        WREN        : in  std_ulogic
        );
  end component;

    
  constant SYNC_PATH_DELAY : time := 100 ps;
  signal do_dly : std_logic_vector(63 downto 0) :=  (others => '0');
  signal dop_dly : std_logic_vector(7 downto 0) :=  (others => '0');
  signal almostfull_dly : std_ulogic := '0';
  signal almostempty_dly : std_ulogic := '0';
  signal empty_dly : std_ulogic := '0';
  signal full_dly : std_ulogic := '0';
  signal rderr_dly : std_ulogic := '0';
  signal wrerr_dly : std_ulogic := '0';
  signal rdcount_dly : std_logic_vector(8 downto 0) :=  (others => '0');
  signal wrcount_dly : std_logic_vector(8 downto 0) :=  (others => '0');
  signal sbiterr_dly : std_ulogic := '0';
  signal dbiterr_dly : std_ulogic := '0';
  signal eccparity_dly : std_logic_vector(7 downto 0) :=  (others => '0');
  signal OPEN_4 : std_logic_vector(3 downto 0);
  signal OPEN_4_1 : std_logic_vector(3 downto 0);
  
begin

FIFO36_72_inst : AFIFO36_INTERNAL
  generic map (
    ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
    ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
    DATA_WIDTH => 72,
    DO_REG => DO_REG,
    EN_ECC_READ => EN_ECC_READ, 
    EN_ECC_WRITE => EN_ECC_WRITE,
    EN_SYN => EN_SYN,
    SIM_MODE => SIM_MODE,
    FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH
    )

  port map (
    DO => do_dly,
    DOP => dop_dly,
    ALMOSTEMPTY => almostempty_dly,
    ALMOSTFULL => almostfull_dly,
    ECCPARITY => eccparity_dly,
    EMPTY => empty_dly,
    FULL => full_dly,
    RDCOUNT(8 downto 0) => rdcount_dly,
    RDCOUNT(12 downto 9) => OPEN_4,
    WRCOUNT(8 downto 0) => wrcount_dly,
    WRCOUNT(12 downto 9) => OPEN_4_1,
    RDERR => rderr_dly,
    SBITERR => sbiterr_dly,
    DBITERR => dbiterr_dly,
    WRERR => wrerr_dly,
    DI => DI,
    DIP => DIP,
    WREN => WREN,
    RDEN => RDEN,
    RDCLK => RDCLK,
    RDRCLK => RDCLK,
    WRCLK => WRCLK,
    RST => RST
    );

   prcs_output_wtiming: process (do_dly, dop_dly, almostempty_dly, almostfull_dly,
                                 empty_dly, full_dly, rdcount_dly, wrcount_dly, rderr_dly,
                                 wrerr_dly, eccparity_dly, sbiterr_dly, dbiterr_dly)
   begin  -- process prcs_output_wtiming

     ALMOSTEMPTY <= almostempty_dly after SYNC_PATH_DELAY;
     ALMOSTFULL <= almostfull_dly after SYNC_PATH_DELAY;
     empty <= empty_dly after SYNC_PATH_DELAY;
     full <= full_dly after SYNC_PATH_DELAY;
     DO <= do_dly after SYNC_PATH_DELAY;
     DOP <= dop_dly after SYNC_PATH_DELAY;
     RDCOUNT <= rdcount_dly after SYNC_PATH_DELAY;
     WRCOUNT <= wrcount_dly after SYNC_PATH_DELAY;
     RDERR <= rderr_dly after SYNC_PATH_DELAY;
     WRERR <= wrerr_dly after SYNC_PATH_DELAY;
     ECCPARITY <= eccparity_dly after SYNC_PATH_DELAY;
     SBITERR <= sbiterr_dly after SYNC_PATH_DELAY;
     DBITERR <= dbiterr_dly after SYNC_PATH_DELAY;

   end process prcs_output_wtiming;

end FIFO36_72_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/fifo36_exp.vhd,v 1.7 2007/06/15 21:01:09 wloo Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2005 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  36K-Bit FIFO
-- /___/   /\     Filename : FIFO36_EXP.vhd
-- \   \  /  \    Timestamp : Tues October 18 16:43:59 PST 2005
--  \___\/\___\
--
-- Revision:
--    10/18/05 - Initial version.
--    06/14/07 - Implemented high performace version of the model.
-- End Revision

----- CELL FIFO36_EXP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity FIFO36_EXP is
generic (

    ALMOST_EMPTY_OFFSET     : bit_vector := X"0080"; 
    ALMOST_FULL_OFFSET      : bit_vector := X"0080";
    DATA_WIDTH              : integer    := 4;
    DO_REG                  : integer    := 1;
    EN_SYN                  : boolean    := FALSE;
    FIRST_WORD_FALL_THROUGH : boolean    := FALSE;
    SIM_MODE                : string     := "SAFE"
    
  );

port (

    ALMOSTEMPTY : out std_ulogic;
    ALMOSTFULL  : out std_ulogic;
    DO          : out std_logic_vector (31 downto 0);
    DOP         : out std_logic_vector (3 downto 0);
    EMPTY       : out std_ulogic;
    FULL        : out std_ulogic;
    RDCOUNT     : out std_logic_vector (12 downto 0);
    RDERR       : out std_ulogic;
    WRCOUNT     : out std_logic_vector (12 downto 0);
    WRERR       : out std_ulogic;

    DI          : in  std_logic_vector (31 downto 0);
    DIP         : in  std_logic_vector (3 downto 0);
    RDCLKL      : in  std_ulogic;
    RDCLKU      : in  std_ulogic;
    RDEN        : in  std_ulogic;
    RDRCLKL     : in  std_ulogic;
    RDRCLKU     : in  std_ulogic;
    RST         : in  std_ulogic;
    WRCLKL      : in  std_ulogic;
    WRCLKU      : in  std_ulogic;
    WREN        : in  std_ulogic    
  );
end FIFO36_EXP;
                                                                        
architecture FIFO36_EXP_V of FIFO36_EXP is

  component AFIFO36_INTERNAL

      generic(
        ALMOST_FULL_OFFSET      : bit_vector := X"0080";
        ALMOST_EMPTY_OFFSET     : bit_vector := X"0080"; 
        DATA_WIDTH              : integer    := 4;
        DO_REG                  : integer    := 1;
        EN_ECC_READ : boolean := FALSE;
        EN_ECC_WRITE : boolean := FALSE;    
        EN_SYN                  : boolean    := FALSE;
        FIFO_SIZE               : integer    := 36;
        FIRST_WORD_FALL_THROUGH : boolean    := FALSE;
        SIM_MODE                : string     := "SAFE"
        );

      port(
        ALMOSTEMPTY : out std_ulogic;
        ALMOSTFULL  : out std_ulogic;
        DBITERR       : out std_ulogic;
        DO          : out std_logic_vector (63 downto 0);
        DOP         : out std_logic_vector (7 downto 0);
        ECCPARITY   : out std_logic_vector (7 downto 0);
        EMPTY       : out std_ulogic;
        FULL        : out std_ulogic;
        RDCOUNT     : out std_logic_vector (12 downto 0);
        RDERR       : out std_ulogic;
        SBITERR     : out std_ulogic;
        WRCOUNT     : out std_logic_vector (12 downto 0);
        WRERR       : out std_ulogic;

        DI          : in  std_logic_vector (63 downto 0);
        DIP         : in  std_logic_vector (7 downto 0);
        RDCLK       : in  std_ulogic;
        RDRCLK       : in  std_ulogic;
        RDEN        : in  std_ulogic;
        RST         : in  std_ulogic;
        WRCLK       : in  std_ulogic;
        WREN        : in  std_ulogic
        );
  end component;

    
  constant SYNC_PATH_DELAY : time := 100 ps;
  signal GND_4 : std_logic_vector(3 downto 0) := (others => '0');
  signal GND_32 : std_logic_vector(31 downto 0) := (others => '0');
  signal OPEN_4 : std_logic_vector(3 downto 0);
  signal OPEN_32 : std_logic_vector(31 downto 0);
  signal OPEN_8 : std_logic_vector(7 downto 0);
  signal do_dly : std_logic_vector(31 downto 0) :=  (others => '0');
  signal dop_dly : std_logic_vector(3 downto 0) :=  (others => '0');
  signal almostfull_dly : std_ulogic := '0';
  signal almostempty_dly : std_ulogic := '0';
  signal empty_dly : std_ulogic := '0';
  signal full_dly : std_ulogic := '0';
  signal rderr_dly : std_ulogic := '0';
  signal wrerr_dly : std_ulogic := '0';
  signal rdcount_dly : std_logic_vector(12 downto 0) :=  (others => '0');
  signal wrcount_dly : std_logic_vector(12 downto 0) :=  (others => '0');


begin

FIFO36_EXP_inst : AFIFO36_INTERNAL
  generic map (
    ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
    ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
    DATA_WIDTH => DATA_WIDTH,
    DO_REG => DO_REG,
    EN_SYN => EN_SYN,
    SIM_MODE => SIM_MODE,
    FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH
    )

  port map (
    DO(31 downto 0) => do_dly,
    DO(63 downto 32) => OPEN_32,
    DOP(3 downto 0) => dop_dly,
    DOP(7 downto 4) => OPEN_4,
    ALMOSTEMPTY => almostempty_dly,
    ALMOSTFULL => almostfull_dly,
    ECCPARITY => OPEN_8,
    EMPTY => empty_dly,
    FULL => full_dly,
    RDCOUNT => rdcount_dly,
    WRCOUNT => wrcount_dly,
    RDERR => rderr_dly,
    SBITERR => OPEN,
    DBITERR => OPEN,
    WRERR => wrerr_dly,
    DI(31 downto 0) => DI,
    DI(63 downto 32) => GND_32,
    DIP(3 downto 0) => DIP,
    DIP(7 downto 4) => GND_4,
    WREN => WREN,
    RDEN => RDEN,
    RDCLK => RDCLKL,
    RDRCLK => RDRCLKL,
    WRCLK => WRCLKL,
    RST => RST
    );

   prcs_output_wtiming: process (do_dly, dop_dly, almostempty_dly, almostfull_dly, empty_dly, full_dly, rdcount_dly, wrcount_dly, rderr_dly, wrerr_dly)
   begin  -- process prcs_output_wtiming

     ALMOSTEMPTY <= almostempty_dly after SYNC_PATH_DELAY;
     ALMOSTFULL <= almostfull_dly after SYNC_PATH_DELAY;
     empty <= empty_dly after SYNC_PATH_DELAY;
     full <= full_dly after SYNC_PATH_DELAY;
     DO <= do_dly after SYNC_PATH_DELAY;
     DOP <= dop_dly after SYNC_PATH_DELAY;
     RDCOUNT <= rdcount_dly after SYNC_PATH_DELAY;
     WRCOUNT <= wrcount_dly after SYNC_PATH_DELAY;
     RDERR <= rderr_dly after SYNC_PATH_DELAY;
     WRERR <= wrerr_dly after SYNC_PATH_DELAY;
     
   end process prcs_output_wtiming;

end FIFO36_EXP_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/fifo36.vhd,v 1.7 2007/06/15 21:01:09 wloo Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2005 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  36K-Bit FIFO
-- /___/   /\     Filename : FIFO36.vhd
-- \   \  /  \    Timestamp : Tues October 18 16:43:59 PST 2005
--  \___\/\___\
--
-- Revision:
--    10/18/05 - Initial version.
--    06/14/07 - Implemented high performace version of the model.
-- End Revision

----- CELL FIFO36 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.VCOMPONENTS.all;
use unisim.vpkg.all;

entity FIFO36 is
generic (

    ALMOST_FULL_OFFSET      : bit_vector := X"0080";
    ALMOST_EMPTY_OFFSET     : bit_vector := X"0080"; 
    DATA_WIDTH              : integer    := 4;
    DO_REG                  : integer    := 1;
    EN_SYN                  : boolean    := FALSE;
    FIRST_WORD_FALL_THROUGH : boolean    := FALSE;
    SIM_MODE                : string     := "SAFE"
    
  );

port (

    ALMOSTEMPTY : out std_ulogic;
    ALMOSTFULL  : out std_ulogic;
    DO          : out std_logic_vector (31 downto 0);
    DOP         : out std_logic_vector (3 downto 0);
    EMPTY       : out std_ulogic;
    FULL        : out std_ulogic;
    RDCOUNT     : out std_logic_vector (12 downto 0);
    RDERR       : out std_ulogic;
    WRCOUNT     : out std_logic_vector (12 downto 0);
    WRERR       : out std_ulogic;

    DI          : in  std_logic_vector (31 downto 0);
    DIP         : in  std_logic_vector (3 downto 0);
    RDCLK       : in  std_ulogic;
    RDEN        : in  std_ulogic;
    RST         : in  std_ulogic;
    WRCLK       : in  std_ulogic;
    WREN        : in  std_ulogic    
  );
end FIFO36;
                                                                        
architecture FIFO36_V of FIFO36 is

  component AFIFO36_INTERNAL

      generic(
        ALMOST_FULL_OFFSET      : bit_vector := X"0080";
        ALMOST_EMPTY_OFFSET     : bit_vector := X"0080"; 
        DATA_WIDTH              : integer    := 4;
        DO_REG                  : integer    := 1;
        EN_ECC_READ : boolean := FALSE;
        EN_ECC_WRITE : boolean := FALSE;    
        EN_SYN                  : boolean    := FALSE;
        FIFO_SIZE               : integer    := 36;
        FIRST_WORD_FALL_THROUGH : boolean    := FALSE;
        SIM_MODE                : string     := "SAFE"
        );

      port(
        ALMOSTEMPTY : out std_ulogic;
        ALMOSTFULL  : out std_ulogic;
        DBITERR       : out std_ulogic;
        DO          : out std_logic_vector (63 downto 0);
        DOP         : out std_logic_vector (7 downto 0);
        ECCPARITY   : out std_logic_vector (7 downto 0);
        EMPTY       : out std_ulogic;
        FULL        : out std_ulogic;
        RDCOUNT     : out std_logic_vector (12 downto 0);
        RDERR       : out std_ulogic;
        SBITERR     : out std_ulogic;
        WRCOUNT     : out std_logic_vector (12 downto 0);
        WRERR       : out std_ulogic;

        DI          : in  std_logic_vector (63 downto 0);
        DIP         : in  std_logic_vector (7 downto 0);
        RDCLK       : in  std_ulogic;
        RDRCLK       : in  std_ulogic;
        RDEN        : in  std_ulogic;
        RST         : in  std_ulogic;
        WRCLK       : in  std_ulogic;
        WREN        : in  std_ulogic
        );
  end component;

    
  constant SYNC_PATH_DELAY : time := 100 ps;
  signal GND_4 : std_logic_vector(3 downto 0) := (others => '0');
  signal GND_32 : std_logic_vector(31 downto 0) := (others => '0');
  signal OPEN_4 : std_logic_vector(3 downto 0);
  signal OPEN_32 : std_logic_vector(31 downto 0);
  signal OPEN_8 : std_logic_vector(7 downto 0);
  signal do_dly : std_logic_vector(31 downto 0) :=  (others => '0');
  signal dop_dly : std_logic_vector(3 downto 0) :=  (others => '0');
  signal almostfull_dly : std_ulogic := '0';
  signal almostempty_dly : std_ulogic := '0';
  signal empty_dly : std_ulogic := '0';
  signal full_dly : std_ulogic := '0';
  signal rderr_dly : std_ulogic := '0';
  signal wrerr_dly : std_ulogic := '0';
  signal rdcount_dly : std_logic_vector(12 downto 0) :=  (others => '0');
  signal wrcount_dly : std_logic_vector(12 downto 0) :=  (others => '0');


begin

FIFO36_inst : AFIFO36_INTERNAL
  generic map (
    ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
    ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
    DATA_WIDTH => DATA_WIDTH,
    DO_REG => DO_REG,
    EN_SYN => EN_SYN,
    SIM_MODE => SIM_MODE,
    FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH
    )

  port map (
    DO(31 downto 0) => do_dly,
    DO(63 downto 32) => OPEN_32,
    DOP(3 downto 0) => dop_dly,
    DOP(7 downto 4) => OPEN_4,
    ALMOSTEMPTY => almostempty_dly,
    ALMOSTFULL => almostfull_dly,
    ECCPARITY => OPEN_8,
    EMPTY => empty_dly,
    FULL => full_dly,
    RDCOUNT => rdcount_dly,
    WRCOUNT => wrcount_dly,
    RDERR => rderr_dly,
    SBITERR => OPEN,
    DBITERR => OPEN,
    WRERR => wrerr_dly,
    DI(31 downto 0) => DI,
    DI(63 downto 32) => GND_32,
    DIP(3 downto 0) => DIP,
    DIP(7 downto 4) => GND_4,
    WREN => WREN,
    RDEN => RDEN,
    RDCLK => RDCLK,
    RDRCLK => RDCLK,
    WRCLK => WRCLK,
    RST => RST
    );

   prcs_initialize:process
     variable first_time        : boolean    := true;

     begin
       if (first_time) then
         case DATA_WIDTH is
            when 4 | 9 | 18 | 36 => null;
            when others =>
                    GenericValueCheckMessage
                      ( HeaderMsg            => " Attribute Syntax Error ",
                        GenericName          => " DATA_WIDTH ",
                        EntityName           => "FIFO36",
                        GenericValue         => DATA_WIDTH,
                        Unit                 => "",
                        ExpectedValueMsg     => " The Legal values for this attribute are ",
                        ExpectedGenericValue => " 4, 9, 18 and 36 ",
                        TailMsg              => "",
                        MsgSeverity          => error
                        );
         end case;
         first_time := false;
       end if;
       wait;
   end process prcs_initialize;

     
   prcs_output_wtiming: process (do_dly, dop_dly, almostempty_dly, almostfull_dly, empty_dly, full_dly, rdcount_dly, wrcount_dly, rderr_dly, wrerr_dly)
   begin  -- process prcs_output_wtiming

     ALMOSTEMPTY <= almostempty_dly after SYNC_PATH_DELAY;
     ALMOSTFULL <= almostfull_dly after SYNC_PATH_DELAY;
     empty <= empty_dly after SYNC_PATH_DELAY;
     full <= full_dly after SYNC_PATH_DELAY;
     DO <= do_dly after SYNC_PATH_DELAY;
     DOP <= dop_dly after SYNC_PATH_DELAY;
     RDCOUNT <= rdcount_dly after SYNC_PATH_DELAY;
     WRCOUNT <= wrcount_dly after SYNC_PATH_DELAY;
     RDERR <= rderr_dly after SYNC_PATH_DELAY;
     WRERR <= wrerr_dly after SYNC_PATH_DELAY;
     
   end process prcs_output_wtiming;

end FIFO36_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  
-- /___/   /\     Filename : FRAME_ECC_VIRTEX5.vhd
-- \   \  /  \    Timestamp : Thu Jun  2 10:57:03 PDT 2005
--  \___\/\___\
--
-- Revision:
--    06/03/05 - Initial version.

----- CELL FRAME_ECC_VIRTEX5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FRAME_ECC_VIRTEX5 is
  port(
    CRCERROR		: out std_ulogic;
    ECCERROR		: out std_ulogic;
    SYNDROME		: out std_logic_vector(11 downto 0);
    SYNDROMEVALID	: out std_ulogic
    );

end FRAME_ECC_VIRTEX5;

architecture FRAME_ECC_VIRTEX5_V of FRAME_ECC_VIRTEX5 is

begin
end FRAME_ECC_VIRTEX5_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Internal Configuration Access Port for VIRTEX5
-- /___/   /\     Filename : ICAP_VIRTEX5.vhd
-- \   \  /  \    Timestamp : Thu Jun  03 10:57:04 PDT 2005
--  \___\/\___\
--
-- Revision:
--    06/03/05 - Initial version.

----- CELL ICAP_VIRTEX5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

entity ICAP_VIRTEX5 is
  generic(
    ICAP_WIDTH : string := "X8"
    );


  port(
    BUSY : out std_ulogic;
    O    : out std_logic_vector(31 downto 0);

    CE    : in std_ulogic;
    CLK   : in std_ulogic;
    I     : in std_logic_vector(31 downto 0);
    WRITE : in std_ulogic
    );

end ICAP_VIRTEX5;

architecture ICAP_VIRTEX5_V of ICAP_VIRTEX5 is

begin
--####################################################################
--#####                        Initialization                      ###
--####################################################################
  prcs_init:process
  begin
     if((ICAP_WIDTH /="X8") and (ICAP_WIDTH /="X16") and (ICAP_WIDTH /="X32")) then
        assert false
        report "Attribute Syntax Error: The allowed values for ICAP_WIDTH are X8, X16 or X32."
        severity Failure;
     end if;
    
     wait;
  end process prcs_init;
end ICAP_VIRTEX5_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                  Input Dual Data-Rate Register with Dual Clock inputs.
-- /___/   /\     Filename : IDDR_2CLK.vhd
-- \   \  /  \    Timestamp : Mon Jun 26 08:18:20 PST 2006
--  \___\/\___\
--
-- Revision:
--    06/26/06 - Initial version.
--    05/15/07 - CR 438883 fix
-- End Revision


----- CELL IDDR_2CLK -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;


library unisim;
use unisim.vpkg.all;

entity IDDR_2CLK is

  generic(

      DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
      INIT_Q1      : bit    := '0';
      INIT_Q2      : bit    := '0';
      SRTYPE       : string := "SYNC"
      );

  port(
      Q1          : out std_ulogic;
      Q2          : out std_ulogic;

      C           : in  std_ulogic;
      CB          : in  std_ulogic;
      CE          : in  std_ulogic;
      D           : in  std_ulogic;
      R           : in  std_ulogic;
      S           : in  std_ulogic
    );

end IDDR_2CLK;

architecture IDDR_2CLK_V OF IDDR_2CLK is


  constant SYNC_PATH_DELAY : time := 100 ps;

  signal C_ipd	        : std_ulogic := 'X';
  signal CB_ipd	        : std_ulogic := 'X';
  signal CE_ipd	        : std_ulogic := 'X';
  signal D_ipd	        : std_ulogic := 'X';
  signal GSR_ipd	: std_ulogic := '0';
  signal R_ipd		: std_ulogic := 'X';
  signal S_ipd		: std_ulogic := 'X';

  signal C_dly	        : std_ulogic := 'X';
  signal CB_dly	        : std_ulogic := 'X';
  signal CE_C_dly       : std_ulogic := 'X';
  signal CE_CB_dly      : std_ulogic := 'X';
  signal D_C_dly        : std_ulogic := 'X';
  signal D_CB_dly       : std_ulogic := 'X';
  signal GSR_dly	: std_ulogic := '0';
  signal R_dly		: std_ulogic := 'X';
  signal S_dly		: std_ulogic := 'X';
  signal R_C_dly	: std_ulogic := 'X';
  signal R_CB_dly	: std_ulogic := 'X';
  signal S_C_dly	: std_ulogic := 'X';
  signal S_CB_dly	: std_ulogic := 'X';

  signal Q1_zd	        : std_ulogic := 'X';
  signal Q2_zd	        : std_ulogic := 'X';

  signal Q1_viol        : std_ulogic := 'X';
  signal Q2_viol        : std_ulogic := 'X';

  signal Q1_o_reg	: std_ulogic := 'X';
  signal Q2_o_reg	: std_ulogic := 'X';
  signal Q3_o_reg	: std_ulogic := 'X';
  signal Q4_o_reg	: std_ulogic := 'X';

  signal ddr_clk_edge_type	: integer := -999;
  signal sr_type		: integer := -999;
begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  C_dly          	 <= C              	after 0 ps;
  CB_dly         	 <= CB             	after 0 ps;
  CE_C_dly       	 <= CE             	after 0 ps;
  CE_CB_dly      	 <= CE             	after 0 ps;
  D_C_dly        	 <= D              	after 0 ps;
  D_CB_dly       	 <= D              	after 0 ps;
  GSR_dly        	 <= '0'            	after 0 ps;
  R_dly          	 <= R              	after 0 ps;
  R_C_dly        	 <= R              	after 0 ps;
  R_CB_dly       	 <= R              	after 0 ps;
  S_dly          	 <= S              	after 0 ps;
  S_C_dly        	 <= S              	after 0 ps;
  S_CB_dly       	 <= S              	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process

  begin
      if((DDR_CLK_EDGE = "OPPOSITE_EDGE") or (DDR_CLK_EDGE = "opposite_edge")) then
         ddr_clk_edge_type <= 1;
      elsif((DDR_CLK_EDGE = "SAME_EDGE") or (DDR_CLK_EDGE = "same_edge")) then
         ddr_clk_edge_type <= 2;
      elsif((DDR_CLK_EDGE = "SAME_EDGE_PIPELINED") or (DDR_CLK_EDGE = "same_edge_pipelined")) then
         ddr_clk_edge_type <= 3;
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " DDR_CLK_EDGE ",
             EntityName => "/IDDR_2CLK",
             GenericValue => DDR_CLK_EDGE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " OPPOSITE_EDGE or SAME_EDGE or  SAME_EDGE_PIPELINED.",
             TailMsg => "",
             MsgSeverity => ERROR 
         );
      end if;

      if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
         sr_type <= 1;
      elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
         sr_type <= 2;
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " SRTYPE ",
             EntityName => "/IDDR_2CLK",
             GenericValue => SRTYPE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " ASYNC or SYNC. ",
             TailMsg => "",
             MsgSeverity => ERROR
         );
      end if;

     wait;
  end process prcs_init;
--####################################################################
--#####                    q1_q2_q3_q4 reg                       #####
--####################################################################
  prcs_q1q2q3q4_reg:process(C_dly, CB_dly, GSR_dly, R_dly, S_dly)
  variable Q1_var : std_ulogic := TO_X01(INIT_Q1);
  variable Q2_var : std_ulogic := TO_X01(INIT_Q2);
  variable Q3_var : std_ulogic := TO_X01(INIT_Q1);
  variable Q4_var : std_ulogic := TO_X01(INIT_Q2);
  begin
     if(GSR_dly = '1') then
         Q1_var := TO_X01(INIT_Q1);
         Q3_var := TO_X01(INIT_Q1);
         Q2_var := TO_X01(INIT_Q2);
         Q4_var := TO_X01(INIT_Q2);
     elsif(GSR_dly = '0') then
        case sr_type is
           when 1 => 
                   if(R_dly = '1') then
                      Q1_var := '0';
                      Q2_var := '0';
                      Q3_var := '0';
                      Q4_var := '0';
                   elsif((R_dly = '0') and (S_dly = '1')) then
                      Q1_var := '1';
                      Q2_var := '1';
                      Q3_var := '1';
                      Q4_var := '1';
                   elsif((R_dly = '0') and (S_dly = '0')) then
                      if(rising_edge(C_dly)) then
                         if(CE_C_dly = '1') then
                            Q3_var := Q1_var;
                            Q1_var := D_C_dly;
                            Q4_var := Q2_var;
                         end if;
                      end if;
                      if(rising_edge(CB_dly)) then
                        if(CE_CB_dly = '1') then
                            Q2_var := D_CB_dly;
                        end if;
                      end if;
                   end if;

           when 2 => 
                   if(rising_edge(C_dly)) then
                      if(R_C_dly = '1') then
                         Q1_var := '0';
                         Q3_var := '0';
                         Q4_var := '0';
                      elsif((R_C_dly = '0') and (S_C_dly = '1')) then
                         Q1_var := '1';
                         Q3_var := '1';
                         Q4_var := '1';
                      elsif((R_C_dly = '0') and (S_C_dly = '0')) then
                         if(CE_C_dly = '1') then
                               Q3_var := Q1_var;
                               Q1_var := D_C_dly;
                               Q4_var := Q2_var;
                         end if;
                      end if;
                   end if;
                        
                   if(rising_edge(CB_dly)) then
                      if(R_CB_dly = '1') then
                         Q2_var := '0';
                      elsif((R_CB_dly = '0') and (S_CB_dly = '1')) then
                         Q2_var := '1';
                      elsif((R_CB_dly = '0') and (S_CB_dly = '0')) then
                         if(CE_CB_dly = '1') then
                               Q2_var := D_CB_dly;
                         end if;
                      end if;
                   end if;
 
           when others =>
                   null; 
        end case;
     end if;

     q1_o_reg <= Q1_var;
     q2_o_reg <= Q2_var;
     q3_o_reg <= Q3_var;
     q4_o_reg <= Q4_var;

  end process prcs_q1q2q3q4_reg;
--####################################################################
--#####                        q1 & q2  mux                      #####
--####################################################################
  prcs_q1q2_mux:process(q1_o_reg, q2_o_reg, q3_o_reg, q4_o_reg)
  begin
     case ddr_clk_edge_type is
        when 1 => 
                 Q1_zd <= q1_o_reg;
                 Q2_zd <= q2_o_reg;
        when 2 => 
                 Q1_zd <= q1_o_reg;
                 Q2_zd <= q4_o_reg;
       when 3 => 
                 Q1_zd <= q3_o_reg;
                 Q2_zd <= q4_o_reg;
       when others =>
                 null;
     end case;
  end process prcs_q1q2_mux;
--####################################################################

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(Q1_zd, Q2_zd)
  begin
      Q1 <= Q1_zd after SYNC_PATH_DELAY;
      Q2 <= Q2_zd after SYNC_PATH_DELAY;
  end process prcs_output;
--####################################################################


end IDDR_2CLK_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                  Input and/or Output Fixed or Variable Delay Element
-- /___/   /\     Filename : IODELAY.vhd
-- \   \  /  \    Timestamp : Wed Aug 10 16:51:05 PDT 2005
--  \___\/\___\
--
-- Revision:
--    08/10/05 - Initial version.
--    01/11/06 - Changed Equation for CALC_TAPDELAY -- FP
--    03/10/06 - CR 227041 -- Added path delays -- FP
--    06/04/06 - Made the model independent of T pin (except in DELAY_SRC=IO mode) -- FP
--    07/21/06 - CR 234556 fix. Added SIM_DELAY_D to Simprims -- FP
--    01/03/07 - For unisims, the fixed Delay value is taken from the sdf.
--    03/26/07 - CR 436199 HIGH_PERFORMANCE_MODE default change -- FP
--    05/03/07 - CR 438921 SIGNAL_PATTERN addition  -- FP
--    06/11/07 - CR 437230 -- added delay buffer chain
--    08/29/07 - CR 445561 -- Replaced D_IOBDELAY_OFFSET with D_IODELAY_OFFSET
-- End Revision

----- CELL IODELAY -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;


library unisim;
use unisim.vpkg.all;

entity IODELAY is

  generic(

      DELAY_SRC		: string	:= "I";
      HIGH_PERFORMANCE_MODE		: boolean	:= true;
      IDELAY_TYPE	: string	:= "DEFAULT";
      IDELAY_VALUE	: integer	:= 0;
      ODELAY_VALUE	: integer	:= 0;
      REFCLK_FREQUENCY	: real		:= 200.0;
      SIGNAL_PATTERN	: string	:= "DATA"
      );

  port(
      DATAOUT	: out std_ulogic;

      C		: in  std_ulogic;
      CE	: in  std_ulogic;
      DATAIN	: in  std_ulogic;
      IDATAIN	: in  std_ulogic;
      INC	: in  std_ulogic;
      ODATAIN	: in  std_ulogic;
      RST	: in  std_ulogic;
      T		: in  std_ulogic
      );

end IODELAY;

architecture IODELAY_V OF IODELAY is

  constant	ILEAK_ADJUST		: real := 1.0;
  constant	D_IODELAY_OFFSET	: real := 0.0;

-----------------------------------------------------------

  constant	MAX_IDELAY_COUNT	: integer := 63;
  constant	MIN_IDELAY_COUNT	: integer := 0;
  constant	MAX_ODELAY_COUNT	: integer := 63;
  constant	MIN_ODELAY_COUNT	: integer := 0;

  constant	MAX_REFCLK_FREQUENCY	: real := 225.0;
  constant	MIN_REFCLK_FREQUENCY	: real := 175.0;


  signal	C_ipd		: std_ulogic := 'X';
  signal	CE_ipd		: std_ulogic := 'X';
  signal GSR            : std_ulogic := '0';
  signal	GSR_ipd		: std_ulogic := 'X';
  signal	DATAIN_ipd	: std_ulogic := 'X';
  signal	IDATAIN_ipd	: std_ulogic := 'X';
  signal	INC_ipd		: std_ulogic := 'X';
  signal	ODATAIN_ipd	: std_ulogic := 'X';
  signal	RST_ipd		: std_ulogic := 'X';
  signal	T_ipd		: std_ulogic := 'X';

  signal	C_dly		: std_ulogic := 'X';
  signal	CE_dly		: std_ulogic := 'X';
  signal	GSR_dly		: std_ulogic := '0';
  signal	DATAIN_dly	: std_ulogic := 'X';
  signal	IDATAIN_dly	: std_ulogic := 'X';
  signal	INC_dly		: std_ulogic := 'X';
  signal	ODATAIN_dly	: std_ulogic := 'X';
  signal	RST_dly		: std_ulogic := 'X';
  signal	T_dly		: std_ulogic := 'X';

  signal	IDATAOUT_delayed	: std_ulogic := 'X';
--  signal	IDATAOUT_zd		: std_ulogic := 'X';
--  signal	IDATAOUT_viol		: std_ulogic := 'X';

  signal	ODATAOUT_delayed	: std_ulogic := 'X';
--  signal	ODATAOUT_zd		: std_ulogic := 'X';
--  signal	ODATAOUT_viol		: std_ulogic := 'X';

  signal	DATAOUT_zd		: std_ulogic := 'X';
--  signal	DATAOUT_viol		: std_ulogic := 'X';

  signal	iDelay		: time := 0.0 ps; 
  signal	oDelay		: time := 0.0 ps; 

  signal	data_mux	: std_ulogic := 'X';
  signal	Violation	: std_ulogic := '0';

  signal	OneTapDelay	: time := 0.0 ps; 
  signal	idelay_count	: integer := IDELAY_VALUE;
  signal	odelay_count	: integer := 0;
  signal	tap_out		: std_ulogic := 'X';

  signal   delay_chain_0,  delay_chain_1,  delay_chain_2,  delay_chain_3,
           delay_chain_4,  delay_chain_5,  delay_chain_6,  delay_chain_7,
           delay_chain_8,  delay_chain_9,  delay_chain_10, delay_chain_11,
           delay_chain_12, delay_chain_13, delay_chain_14, delay_chain_15,
           delay_chain_16, delay_chain_17, delay_chain_18, delay_chain_19,
           delay_chain_20, delay_chain_21, delay_chain_22, delay_chain_23,
           delay_chain_24, delay_chain_25, delay_chain_26, delay_chain_27,
           delay_chain_28, delay_chain_29, delay_chain_30, delay_chain_31,
           delay_chain_32, delay_chain_33, delay_chain_34, delay_chain_35,
           delay_chain_36, delay_chain_37, delay_chain_38, delay_chain_39,
           delay_chain_40, delay_chain_41, delay_chain_42, delay_chain_43,
           delay_chain_44, delay_chain_45, delay_chain_46, delay_chain_47,
           delay_chain_48, delay_chain_49, delay_chain_50, delay_chain_51,
           delay_chain_52, delay_chain_53, delay_chain_54, delay_chain_55,
           delay_chain_56, delay_chain_57, delay_chain_58, delay_chain_59,
           delay_chain_60, delay_chain_61, delay_chain_62, delay_chain_63 : std_ulogic;

begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  C_dly          	 <= C              	after 0 ps;
  CE_dly         	 <= CE             	after 0 ps;
  DATAIN_dly     	 <= DATAIN         	after 0 ps;
  IDATAIN_dly    	 <= IDATAIN        	after 0 ps;
  INC_dly        	 <= INC            	after 0 ps;
  ODATAIN_dly    	 <= ODATAIN        	after 0 ps;
  RST_dly        	 <= RST            	after 0 ps;
  T_dly          	 <= T              	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process
  variable TapCount_var   : integer := 0;
  variable IsTapDelay_var : boolean := true; 
  variable idelaytypefixed_var  : boolean := false; 
  variable idelaytypedefault_var : boolean := false; 
  variable CALC_TAPDELAY : real := 0.0;
  begin
     -------- SIGNAL_PATTERN check
     if((SIGNAL_PATTERN /= "CLOCK") and (SIGNAL_PATTERN /= "DATA"))then
         assert false
         report "Attribute Syntax Error: Legal values for SIGNAL_PATTERN are DATA or CLOCK"
         severity Failure;
     end if;

     -------- HIGH_PERFORMANCE_MODE check

     case HIGH_PERFORMANCE_MODE is
       when true | false => null;
       when others =>
          assert false
          report "Attribute Syntax Error: The attribute HIGH_PERFORMANCE_MODE on IODELAY must be set to either true or false."
          severity Failure;
     end case;

     -------- IDELAY_TYPE check

     if(IDELAY_TYPE = "FIXED") then
        idelaytypefixed_var := true;
     elsif(IDELAY_TYPE = "VARIABLE") then
        idelaytypefixed_var := false;
     elsif(IDELAY_TYPE = "DEFAULT") then
        idelaytypedefault_var := true;
        idelaytypefixed_var := false;
     else
       GenericValueCheckMessage
       (  HeaderMsg  => " Attribute Syntax Warning ",
          GenericName => " IDELAY_TYPE ",
          EntityName => "/IODELAY",
          GenericValue => IDELAY_TYPE,
          Unit => "",
          ExpectedValueMsg => " The Legal values for this attribute are ",
          ExpectedGenericValue => " DEFAULT, FIXED or VARIABLE ",
          TailMsg => "",
          MsgSeverity => failure 
       );
     end if;

     -------- IDELAY_VALUE check

     if((IDELAY_VALUE < MIN_IDELAY_COUNT) or (ODELAY_VALUE > MAX_IDELAY_COUNT)) then 
        GenericValueCheckMessage
        (  HeaderMsg  => " Attribute Syntax Warning ",
           GenericName => " IDELAY_VALUE ",
           EntityName => "/IODELAY",
           GenericValue => IDELAY_VALUE,
           Unit => "",
           ExpectedValueMsg => " The Legal values for this attribute are ",
           ExpectedGenericValue => " 0, 1, 2, ..., 62, 63 ",
           TailMsg => "",
           MsgSeverity => failure 
        );
     end if;

     -------- ODELAY_VALUE check

     if((ODELAY_VALUE < MIN_ODELAY_COUNT) or (ODELAY_VALUE > MAX_ODELAY_COUNT)) then 
        GenericValueCheckMessage
        (  HeaderMsg  => " Attribute Syntax Warning ",
           GenericName => " ODELAY_VALUE ",
           EntityName => "/IODELAY",
           GenericValue => ODELAY_VALUE,
           Unit => "",
           ExpectedValueMsg => " The Legal values for this attribute are ",
           ExpectedGenericValue => " 0, 1, 2, ..., 62, 63 ",
           TailMsg => "",
           MsgSeverity => failure 
        );
     end if;

     -------- REFCLK_FREQUENCY check

     if((REFCLK_FREQUENCY < MIN_REFCLK_FREQUENCY) or (REFCLK_FREQUENCY > MAX_REFCLK_FREQUENCY)) then 
         assert false
         report "Attribute Syntax Error: Legal values for REFCLK_FREQUENCY are 175.0 to 225.0"
         severity Failure;
     end if;

     odelay_count <= ODELAY_VALUE;
     CALC_TAPDELAY := ((1.0/REFCLK_FREQUENCY) * (1.0/64.0) * ILEAK_ADJUST * 1000000.0) + D_IODELAY_OFFSET ;
     OneTapDelay   <= CALC_TAPDELAY * 1.0 ps; 
     wait;
  end process prcs_init;
--####################################################################
--#####                  CALCULATE iDelay                        #####
--####################################################################
  prcs_calc_idelay:process(C_dly, GSR_dly, RST_dly)
  variable idelay_count_var : integer :=0;
  variable FIRST_TIME   : boolean :=true;
  variable BaseTime_var : time    := 1 ps ;
--  variable CALC_TAPDELAY : real := 0.0;
  begin
     if(IDELAY_TYPE = "VARIABLE") then
       if((GSR_dly = '1') or (FIRST_TIME))then
          idelay_count_var := IDELAY_VALUE; 
--          CALC_TAPDELAY := ((1.0/REFCLK_FREQUENCY) * (1.0/64.0) * ILEAK_ADJUST * 1000000.0) + D_IODELAY_OFFSET ;
--          iDelay        <= real(idelay_count_var) * CALC_TAPDELAY * BaseTime_var; 
          FIRST_TIME   := false;
       elsif(GSR_dly = '0') then
          if(rising_edge(C_dly)) then
             if(RST_dly = '1') then
               idelay_count_var := IDELAY_VALUE; 
             elsif((RST_dly = '0') and (CE_dly = '1')) then
                  if(INC_dly = '1') then
                     if (idelay_count_var < MAX_IDELAY_COUNT) then
                        idelay_count_var := idelay_count_var + 1;
                     else 
                        idelay_count_var := MIN_IDELAY_COUNT;
                     end if;
                  elsif(INC_dly = '0') then
                     if (idelay_count_var > MIN_IDELAY_COUNT) then
                         idelay_count_var := idelay_count_var - 1;
                     else
                         idelay_count_var := MAX_IDELAY_COUNT;
                     end if;
                         
                  end if; -- INC_dly
             end if; -- RST_dly
--             iDelay <= real(idelay_count_var) *  CALC_TAPDELAY * BaseTime_var;
             idelay_count  <= idelay_count_var;
          end if; -- C_dly
       end if; -- GSR_dly

     end if; -- IDELAY_TYPE 
  end process prcs_calc_idelay;
--####################################################################
--#####                      SELECT IDATA_MUX                    #####
--####################################################################
  prcs_data_mux:process(DATAIN_dly, IDATAIN_dly, ODATAIN_dly, T_dly)
  begin
      if(DELAY_SRC = "I") then 
            data_mux <= IDATAIN_dly;
      elsif(DELAY_SRC = "O") then
            data_mux <= ODATAIN_dly;
      elsif(DELAY_SRC = "IO") then
            data_mux <= (IDATAIN_dly and T_dly) or (ODATAIN_dly and (not T_dly));
      elsif(DELAY_SRC = "DATAIN") then
            data_mux <= DATAIN_dly;
      else
         assert false
         report "Attribute Syntax Error : Legal values for DELAY_SRC on IODELAY instance are I, O, IO or DATAIN."
         severity Failure;
      end if;
  end process prcs_data_mux;
--####################################################################
--#####                      DELAY BUFFERS                       #####
--####################################################################
delay_chain_0  <= transport data_mux;
delay_chain_1  <= transport delay_chain_0  after OneTapDelay;
delay_chain_2  <= transport delay_chain_1  after OneTapDelay;
delay_chain_3  <= transport delay_chain_2  after OneTapDelay;
delay_chain_4  <= transport delay_chain_3  after OneTapDelay;
delay_chain_5  <= transport delay_chain_4  after OneTapDelay;
delay_chain_6  <= transport delay_chain_5  after OneTapDelay;
delay_chain_7  <= transport delay_chain_6  after OneTapDelay;
delay_chain_8  <= transport delay_chain_7  after OneTapDelay;
delay_chain_9  <= transport delay_chain_8  after OneTapDelay;
delay_chain_10 <= transport delay_chain_9  after OneTapDelay;
delay_chain_11 <= transport delay_chain_10  after OneTapDelay;
delay_chain_12 <= transport delay_chain_11  after OneTapDelay;
delay_chain_13 <= transport delay_chain_12  after OneTapDelay;
delay_chain_14 <= transport delay_chain_13  after OneTapDelay;
delay_chain_15 <= transport delay_chain_14  after OneTapDelay;
delay_chain_16 <= transport delay_chain_15  after OneTapDelay;
delay_chain_17 <= transport delay_chain_16  after OneTapDelay;
delay_chain_18 <= transport delay_chain_17  after OneTapDelay;
delay_chain_19 <= transport delay_chain_18  after OneTapDelay;
delay_chain_20 <= transport delay_chain_19  after OneTapDelay;
delay_chain_21 <= transport delay_chain_20  after OneTapDelay;
delay_chain_22 <= transport delay_chain_21  after OneTapDelay;
delay_chain_23 <= transport delay_chain_22  after OneTapDelay;
delay_chain_24 <= transport delay_chain_23  after OneTapDelay;
delay_chain_25 <= transport delay_chain_24  after OneTapDelay;
delay_chain_26 <= transport delay_chain_25  after OneTapDelay;
delay_chain_27 <= transport delay_chain_26  after OneTapDelay;
delay_chain_28 <= transport delay_chain_27  after OneTapDelay;
delay_chain_29 <= transport delay_chain_28  after OneTapDelay;
delay_chain_30 <= transport delay_chain_29  after OneTapDelay;
delay_chain_31 <= transport delay_chain_30  after OneTapDelay;
delay_chain_32 <= transport delay_chain_31  after OneTapDelay;
delay_chain_33 <= transport delay_chain_32  after OneTapDelay;
delay_chain_34 <= transport delay_chain_33  after OneTapDelay;
delay_chain_35 <= transport delay_chain_34  after OneTapDelay;
delay_chain_36 <= transport delay_chain_35  after OneTapDelay;
delay_chain_37 <= transport delay_chain_36  after OneTapDelay;
delay_chain_38 <= transport delay_chain_37  after OneTapDelay;
delay_chain_39 <= transport delay_chain_38  after OneTapDelay;
delay_chain_40 <= transport delay_chain_39  after OneTapDelay;
delay_chain_41 <= transport delay_chain_40  after OneTapDelay;
delay_chain_42 <= transport delay_chain_41  after OneTapDelay;
delay_chain_43 <= transport delay_chain_42  after OneTapDelay;
delay_chain_44 <= transport delay_chain_43  after OneTapDelay;
delay_chain_45 <= transport delay_chain_44  after OneTapDelay;
delay_chain_46 <= transport delay_chain_45  after OneTapDelay;
delay_chain_47 <= transport delay_chain_46  after OneTapDelay;
delay_chain_48 <= transport delay_chain_47  after OneTapDelay;
delay_chain_49 <= transport delay_chain_48  after OneTapDelay;
delay_chain_50 <= transport delay_chain_49  after OneTapDelay;
delay_chain_51 <= transport delay_chain_50  after OneTapDelay;
delay_chain_52 <= transport delay_chain_51  after OneTapDelay;
delay_chain_53 <= transport delay_chain_52  after OneTapDelay;
delay_chain_54 <= transport delay_chain_53  after OneTapDelay;
delay_chain_55 <= transport delay_chain_54  after OneTapDelay;
delay_chain_56 <= transport delay_chain_55  after OneTapDelay;
delay_chain_57 <= transport delay_chain_56  after OneTapDelay;
delay_chain_58 <= transport delay_chain_57  after OneTapDelay;
delay_chain_59 <= transport delay_chain_58  after OneTapDelay;
delay_chain_60 <= transport delay_chain_59  after OneTapDelay;
delay_chain_61 <= transport delay_chain_60  after OneTapDelay;
delay_chain_62 <= transport delay_chain_61  after OneTapDelay;
delay_chain_63 <= transport delay_chain_62  after OneTapDelay;

--####################################################################
--#####                Assign Tap Delays                         #####
--####################################################################
  prcs_AssignDelays:process
  begin
        if(((DELAY_SRC = "IO") and (T_dly = '1')) or (DELAY_SRC = "I")  or  (DELAY_SRC = "DATAIN")) then
             case idelay_count is
                when 0 =>    tap_out <= delay_chain_0;
                when 1 =>    tap_out <= delay_chain_1;
                when 2 =>    tap_out <= delay_chain_2;
                when 3 =>    tap_out <= delay_chain_3;
                when 4 =>    tap_out <= delay_chain_4;
                when 5 =>    tap_out <= delay_chain_5;
                when 6 =>    tap_out <= delay_chain_6;
                when 7 =>    tap_out <= delay_chain_7;
                when 8 =>    tap_out <= delay_chain_8;
                when 9 =>    tap_out <= delay_chain_9;
                when 10 =>   tap_out <= delay_chain_10;
                when 11 =>   tap_out <= delay_chain_11;
                when 12 =>   tap_out <= delay_chain_12;
                when 13 =>   tap_out <= delay_chain_13;
                when 14 =>   tap_out <= delay_chain_14;
                when 15 =>   tap_out <= delay_chain_15;
                when 16 =>   tap_out <= delay_chain_16;
                when 17 =>   tap_out <= delay_chain_17;
                when 18 =>   tap_out <= delay_chain_18;
                when 19 =>   tap_out <= delay_chain_19;
                when 20 =>   tap_out <= delay_chain_20;
                when 21 =>   tap_out <= delay_chain_21;
                when 22 =>   tap_out <= delay_chain_22;
                when 23 =>   tap_out <= delay_chain_23;
                when 24 =>   tap_out <= delay_chain_24;
                when 25 =>   tap_out <= delay_chain_25;
                when 26 =>   tap_out <= delay_chain_26;
                when 27 =>   tap_out <= delay_chain_27;
                when 28 =>   tap_out <= delay_chain_28;
                when 29 =>   tap_out <= delay_chain_29;
                when 30 =>   tap_out <= delay_chain_30;
                when 31 =>   tap_out <= delay_chain_31;
                when 32 =>   tap_out <= delay_chain_32;
                when 33 =>   tap_out <= delay_chain_33;
                when 34 =>   tap_out <= delay_chain_34;
                when 35 =>   tap_out <= delay_chain_35;
                when 36 =>   tap_out <= delay_chain_36;
                when 37 =>   tap_out <= delay_chain_37;
                when 38 =>   tap_out <= delay_chain_38;
                when 39 =>   tap_out <= delay_chain_39;
                when 40 =>   tap_out <= delay_chain_40;
                when 41 =>   tap_out <= delay_chain_41;
                when 42 =>   tap_out <= delay_chain_42;
                when 43 =>   tap_out <= delay_chain_43;
                when 44 =>   tap_out <= delay_chain_44;
                when 45 =>   tap_out <= delay_chain_45;
                when 46 =>   tap_out <= delay_chain_46;
                when 47 =>   tap_out <= delay_chain_47;
                when 48 =>   tap_out <= delay_chain_48;
                when 49 =>   tap_out <= delay_chain_49;
                when 50 =>   tap_out <= delay_chain_50;
                when 51 =>   tap_out <= delay_chain_51;
                when 52 =>   tap_out <= delay_chain_52;
                when 53 =>   tap_out <= delay_chain_53;
                when 54 =>   tap_out <= delay_chain_54;
                when 55 =>   tap_out <= delay_chain_55;
                when 56 =>   tap_out <= delay_chain_56;
                when 57 =>   tap_out <= delay_chain_57;
                when 58 =>   tap_out <= delay_chain_58;
                when 59 =>   tap_out <= delay_chain_59;
                when 60 =>   tap_out <= delay_chain_60;
                when 61 =>   tap_out <= delay_chain_61;
                when 62 =>   tap_out <= delay_chain_62;
                when 63 =>   tap_out <= delay_chain_63;
                when others =>
                    tap_out <= delay_chain_0;
             end case;
        elsif(((DELAY_SRC = "IO") and (T_dly = '0')) or (DELAY_SRC = "O")) then
             case odelay_count is
                when 0 =>    tap_out <= delay_chain_0;
                when 1 =>    tap_out <= delay_chain_1;
                when 2 =>    tap_out <= delay_chain_2;
                when 3 =>    tap_out <= delay_chain_3;
                when 4 =>    tap_out <= delay_chain_4;
                when 5 =>    tap_out <= delay_chain_5;
                when 6 =>    tap_out <= delay_chain_6;
                when 7 =>    tap_out <= delay_chain_7;
                when 8 =>    tap_out <= delay_chain_8;
                when 9 =>    tap_out <= delay_chain_9;
                when 10 =>   tap_out <= delay_chain_10;
                when 11 =>   tap_out <= delay_chain_11;
                when 12 =>   tap_out <= delay_chain_12;
                when 13 =>   tap_out <= delay_chain_13;
                when 14 =>   tap_out <= delay_chain_14;
                when 15 =>   tap_out <= delay_chain_15;
                when 16 =>   tap_out <= delay_chain_16;
                when 17 =>   tap_out <= delay_chain_17;
                when 18 =>   tap_out <= delay_chain_18;
                when 19 =>   tap_out <= delay_chain_19;
                when 20 =>   tap_out <= delay_chain_20;
                when 21 =>   tap_out <= delay_chain_21;
                when 22 =>   tap_out <= delay_chain_22;
                when 23 =>   tap_out <= delay_chain_23;
                when 24 =>   tap_out <= delay_chain_24;
                when 25 =>   tap_out <= delay_chain_25;
                when 26 =>   tap_out <= delay_chain_26;
                when 27 =>   tap_out <= delay_chain_27;
                when 28 =>   tap_out <= delay_chain_28;
                when 29 =>   tap_out <= delay_chain_29;
                when 30 =>   tap_out <= delay_chain_30;
                when 31 =>   tap_out <= delay_chain_31;
                when 32 =>   tap_out <= delay_chain_32;
                when 33 =>   tap_out <= delay_chain_33;
                when 34 =>   tap_out <= delay_chain_34;
                when 35 =>   tap_out <= delay_chain_35;
                when 36 =>   tap_out <= delay_chain_36;
                when 37 =>   tap_out <= delay_chain_37;
                when 38 =>   tap_out <= delay_chain_38;
                when 39 =>   tap_out <= delay_chain_39;
                when 40 =>   tap_out <= delay_chain_40;
                when 41 =>   tap_out <= delay_chain_41;
                when 42 =>   tap_out <= delay_chain_42;
                when 43 =>   tap_out <= delay_chain_43;
                when 44 =>   tap_out <= delay_chain_44;
                when 45 =>   tap_out <= delay_chain_45;
                when 46 =>   tap_out <= delay_chain_46;
                when 47 =>   tap_out <= delay_chain_47;
                when 48 =>   tap_out <= delay_chain_48;
                when 49 =>   tap_out <= delay_chain_49;
                when 50 =>   tap_out <= delay_chain_50;
                when 51 =>   tap_out <= delay_chain_51;
                when 52 =>   tap_out <= delay_chain_52;
                when 53 =>   tap_out <= delay_chain_53;
                when 54 =>   tap_out <= delay_chain_54;
                when 55 =>   tap_out <= delay_chain_55;
                when 56 =>   tap_out <= delay_chain_56;
                when 57 =>   tap_out <= delay_chain_57;
                when 58 =>   tap_out <= delay_chain_58;
                when 59 =>   tap_out <= delay_chain_59;
                when 60 =>   tap_out <= delay_chain_60;
                when 61 =>   tap_out <= delay_chain_61;
                when 62 =>   tap_out <= delay_chain_62;
                when 63 =>   tap_out <= delay_chain_63;
                when others =>
                    tap_out <= delay_chain_0;
             end case;
        end if;
  wait on  T_dly, idelay_count, odelay_count, delay_chain_0,  delay_chain_1,  delay_chain_2,  delay_chain_3,
           delay_chain_4,  delay_chain_5,  delay_chain_6,  delay_chain_7,
           delay_chain_8,  delay_chain_9,  delay_chain_10, delay_chain_11,
           delay_chain_12, delay_chain_13, delay_chain_14, delay_chain_15,
           delay_chain_16, delay_chain_17, delay_chain_18, delay_chain_19,
           delay_chain_20, delay_chain_21, delay_chain_22, delay_chain_23,
           delay_chain_24, delay_chain_25, delay_chain_26, delay_chain_27,
           delay_chain_28, delay_chain_29, delay_chain_30, delay_chain_31,
           delay_chain_32, delay_chain_33, delay_chain_34, delay_chain_35,
           delay_chain_36, delay_chain_37, delay_chain_38, delay_chain_39,
           delay_chain_40, delay_chain_41, delay_chain_42, delay_chain_43,
           delay_chain_44, delay_chain_45, delay_chain_46, delay_chain_47,
           delay_chain_48, delay_chain_49, delay_chain_50, delay_chain_51,
           delay_chain_52, delay_chain_53, delay_chain_54, delay_chain_55,
           delay_chain_56, delay_chain_57, delay_chain_58, delay_chain_59,
           delay_chain_60, delay_chain_61, delay_chain_62, delay_chain_63;

  end process prcs_AssignDelays;

--####################################################################
--#####                  CALCULATE oDelay                         #####
--####################################################################
  prcs_calc_odelay:process(C_dly, GSR_dly, RST_dly)
  variable odelay_count_var : integer :=0;
  variable FIRST_TIME   : boolean :=true;
  variable BaseTime_var : time    := 1 ps ;
  variable CALC_TAPDELAY : real := 0.0;
  begin
     if((GSR_dly = '1') or (FIRST_TIME))then
        odelay_count_var := ODELAY_VALUE; 
        CALC_TAPDELAY := ((1.0/REFCLK_FREQUENCY) * (1.0/64.0) * ILEAK_ADJUST * 1000000.0) + D_IODELAY_OFFSET ;
        oDelay        <= real(odelay_count_var) * CALC_TAPDELAY * BaseTime_var; 
        FIRST_TIME   := false;
     end if;

  end process prcs_calc_odelay;

--####################################################################
--#####                      OUTPUT  TAP                         #####
--####################################################################
  prcs_tapout:process(tap_out)
  begin
      DATAOUT_zd <= tap_out ;
  end process prcs_tapout;

--####################################################################
--#####                           OUTPUT                         #####
--####################################################################
  prcs_output:process(DATAOUT_zd)
  begin
      DATAOUT <= DATAOUT_zd ;
  end process prcs_output;


end IODELAY_V;

-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                  Source Synchronous Input Deserializer
-- /___/   /\     Filename : ISERDES_NODELAY.vhd
-- \   \  /  \    Timestamp : Fri Oct 21 16:11:37 PDT 2005
--  \___\/\___\
--
-- Revision:
--    10/21/05 - Initial version.
--    05/29/06 - CR 232324 -- Added Rec/Rem RST wrt negedge CLKDIV
--    06/16/06 - Added new port CLKB
--    10/13/06 - CR 426606 
--    03/02/07 - CR 435001 changed module names to bscntrl_nodelay and ice_module_nodelay_nodelay  
--    08/29/07 - CR 447556 Fixed attribute INTERFACE_TYPE to be case insensitive 
--    09/10/07 - CR 447760 Added Strict DRC for BITSLIP and INTERFACE_TYPE combinations
--    12/03/07 - CR 454107 Added DRC warnings for INTERFACE_TYPE, DATA_RATE and DATA_WIDTH combinations
-- End Revision
----- CELL ISERDES_NODELAY -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;


library unisim;
use unisim.vpkg.all;
use unisim.vcomponents.all;

--//////////////////////////////////////////////////////////// 
--////////////////////////// BSCNTRL_NODELAY /////////////////////////
--//////////////////////////////////////////////////////////// 
entity bscntrl_nodelay is
  generic(
      SRTYPE        : string;
      INIT_BITSLIPCNT	: bit_vector(3 downto 0)
      );
  port(
      CLKDIV_INT	: out std_ulogic;
      MUXC		: out std_ulogic;

      BITSLIP		: in std_ulogic;
      C23		: in std_ulogic;
      C45		: in std_ulogic;
      C67		: in std_ulogic;
      CLK		: in std_ulogic;
      CLKDIV		: in std_ulogic;
      DATA_RATE		: in std_ulogic;
      GSR		: in std_ulogic;
      R			: in std_ulogic;
      SEL		: in std_logic_vector (1 downto 0)
      );
           
end bscntrl_nodelay;

architecture bscntrl_nodelay_V of bscntrl_nodelay is
--  constant DELAY_FFBSC		: time       := 300 ns;
--  constant DELAY_MXBSC		: time       := 60  ns;
  constant DELAY_FFBSC			: time       := 300 ps;
  constant DELAY_MXBSC			: time       := 60  ps;

  signal AttrSRtype		: integer := 0;

  signal q1			: std_ulogic := 'X';
  signal q2			: std_ulogic := 'X';
  signal q3			: std_ulogic := 'X';
  signal mux			: std_ulogic := 'X';
  signal qhc1			: std_ulogic := 'X';
  signal qhc2			: std_ulogic := 'X';
  signal qlc1			: std_ulogic := 'X';
  signal qlc2			: std_ulogic := 'X';
  signal qr1			: std_ulogic := 'X';
  signal qr2			: std_ulogic := 'X';
  signal mux1			: std_ulogic := 'X';
  signal clkdiv_zd		: std_ulogic := 'X';

begin
--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process
  begin

     if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
        AttrSrtype <= 0;
     elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
        AttrSrtype <= 1;
     end if;

     wait;
  end process prcs_init;
--####################################################################
--#####              Divide by 2 - 8 counter                     #####
--####################################################################
  prcs_div_2_8_cntr:process(qr2, CLK, GSR)
  variable clkdiv_int_var	:  std_ulogic := TO_X01(INIT_BITSLIPCNT(0));
  variable q1_var		:  std_ulogic := TO_X01(INIT_BITSLIPCNT(1));
  variable q2_var		:  std_ulogic := TO_X01(INIT_BITSLIPCNT(2));
  variable q3_var		:  std_ulogic := TO_X01(INIT_BITSLIPCNT(3));
  begin
     if(GSR = '1') then
         clkdiv_int_var	:= TO_X01(INIT_BITSLIPCNT(0));
         q1_var		:= TO_X01(INIT_BITSLIPCNT(1));
         q2_var		:= TO_X01(INIT_BITSLIPCNT(2));
         q3_var		:= TO_X01(INIT_BITSLIPCNT(3));
     elsif(GSR = '0') then
        case AttrSRtype is
           when 0 => 
           --------------- // async SET/RESET
                   if(qr2 = '1') then
                      clkdiv_int_var := '0';
                      q1_var := '0';
                      q2_var := '0';
                      q3_var := '0';
                   elsif (qhc1 = '1') then
                      clkdiv_int_var := clkdiv_int_var;
                      q1_var := q1_var;
                      q2_var := q2_var;
                      q3_var := q3_var;
                   else
                      if(rising_edge(CLK)) then
                         q3_var := q2_var;
                         q2_var :=( NOT((NOT clkdiv_int_var) and (NOT q2_var)) and q1_var);
                         q1_var := clkdiv_int_var;
                         clkdiv_int_var := mux;
                      end if;
                   end if;

           when 1 => 
           --------------- // sync SET/RESET
                   if(rising_edge(CLK)) then
                      if(qr2 = '1') then
                         clkdiv_int_var := '0';
                         q1_var := '0';
                         q2_var := '0';
                         q3_var := '0';
                      elsif (qhc1 = '1') then
                         clkdiv_int_var := clkdiv_int_var;
                         q1_var := q1_var;
                         q2_var := q2_var;
                         q3_var := q3_var;
                      else
                         q3_var := q2_var;
                         q2_var :=( NOT((NOT clkdiv_int_var) and (NOT q2_var)) and q1_var);
                         q1_var := clkdiv_int_var;
                         clkdiv_int_var := mux;
                      end if;
                   end if;

           when others => 
                   null;
           end case;


     end if;

     q1 <= q1_var after DELAY_FFBSC;
     q2 <= q2_var after DELAY_FFBSC;
     q3 <= q3_var after DELAY_FFBSC;
     clkdiv_zd <= clkdiv_int_var after DELAY_FFBSC;

  end process prcs_div_2_8_cntr;
--####################################################################
--#####          Divider selections and 4:1 selector mux         #####
--####################################################################
  prcs_mux_sel:process(sel, c23 , c45 , c67 , clkdiv_zd , q1 , q2 , q3)
  begin
    case sel is
        when "00" =>
              mux <= NOT (clkdiv_zd or  (c23 and q1)) after DELAY_MXBSC;
        when "01" =>
              mux <= NOT (q1 or (c45 and q2)) after DELAY_MXBSC;
        when "10" =>
              mux <= NOT (q2 or (c67 and q3)) after DELAY_MXBSC;
        when "11" =>
              mux <= NOT (q3) after DELAY_MXBSC;
        when others =>
              mux <= NOT (clkdiv_zd or  (c23 and q1)) after DELAY_MXBSC;
    end case;
  end process prcs_mux_sel;
--####################################################################
--#####                  Bitslip control logic                   #####
--####################################################################
  prcs_logictrl:process(qr1, clkdiv)
  begin
      case AttrSRtype is
          when 0 => 
           --------------- // async SET/RESET
               if(qr1 = '1') then
                 qlc1        <= '0' after DELAY_FFBSC;
                 qlc2        <= '0' after DELAY_FFBSC;
               elsif(bitslip = '0') then
                 qlc1        <= qlc1 after DELAY_FFBSC;
                 qlc2        <= '0'  after DELAY_FFBSC;
               else 
                   if(rising_edge(clkdiv)) then
                      qlc1      <= NOT qlc1 after DELAY_FFBSC;
                      qlc2      <= (bitslip and mux1) after DELAY_FFBSC;
                   end if;
               end if;

          when 1 => 
           --------------- // sync SET/RESET
               if(rising_edge(clkdiv)) then
                  if(qr1 = '1') then
                    qlc1        <= '0' after DELAY_FFBSC;
                    qlc2        <= '0' after DELAY_FFBSC;
                  elsif(bitslip = '0') then
                    qlc1        <= qlc1 after DELAY_FFBSC;
                    qlc2        <= '0'  after DELAY_FFBSC;
                  else 
                    qlc1      <= NOT qlc1 after DELAY_FFBSC;
                    qlc2      <= (bitslip and mux1) after DELAY_FFBSC;
                  end if;
               end if;
          when others => 
                  null;
      end case;
  end process  prcs_logictrl;

--####################################################################
--#####        Mux to select between sdr "0" and ddr "1"         #####
--####################################################################
  prcs_sdr_ddr_mux:process(qlc1, DATA_RATE)
  begin
    case DATA_RATE is
        when '0' =>
             mux1 <= qlc1 after DELAY_MXBSC;
        when '1' =>
             mux1 <= '1' after DELAY_MXBSC;
        when others =>
             null;
    end case;
  end process  prcs_sdr_ddr_mux;

--####################################################################
--#####                       qhc1 and qhc2                      #####
--####################################################################
  prcs_qhc1_qhc2:process(qr2, CLK)
  begin
-- FP TMP -- should CLK and q2 have to be rising_edge
     case AttrSRtype is
        when 0 => 
         --------------- // async SET/RESET
             if(qr2 = '1') then
                qhc1 <= '0' after DELAY_FFBSC;
                qhc2 <= '0' after DELAY_FFBSC;
             elsif(rising_edge(CLK)) then
                qhc1 <= (qlc2 and (NOT qhc2)) after DELAY_FFBSC;
                qhc2 <= qlc2 after DELAY_FFBSC;
             end if;

        when 1 => 
         --------------- // sync SET/RESET
             if(rising_edge(CLK)) then
                if(qr2 = '1') then
                   qhc1 <= '0' after DELAY_FFBSC;
                   qhc2 <= '0' after DELAY_FFBSC;
                else
                   qhc1 <= (qlc2 and (NOT qhc2)) after DELAY_FFBSC;
                   qhc2 <= qlc2 after DELAY_FFBSC;
                end if;
             end if;

        when others =>
             null;
     end case;

  end process  prcs_qhc1_qhc2;

--####################################################################
--#####     Mux drives ctrl lines of mux in front of 2nd rnk FFs  ####
--####################################################################
  prcs_muxc:process(mux1, DATA_RATE)
  begin
    case DATA_RATE is
        when '0' =>
             muxc <= mux1 after DELAY_MXBSC;
        when '1' =>
             muxc <= '0'  after DELAY_MXBSC;
        when others =>
             null;
    end case;
  end process  prcs_muxc;

--####################################################################
--#####                       Asynchronous set flops             #####
--####################################################################
  prcs_qr1:process(R, CLKDIV)
  begin
-- FP TMP -- should CLKDIV and R have to be rising_edge
     case AttrSRtype is
        when 0 => 
         --------------- // async SET/RESET
             if(R = '1') then
                qr1        <= '1' after DELAY_FFBSC;
             elsif(rising_edge(CLKDIV)) then
                qr1        <= '0' after DELAY_FFBSC;
             end if;

        when 1 => 
         --------------- // sync SET/RESET
             if(rising_edge(CLKDIV)) then
                if(R = '1') then
                   qr1        <= '1' after DELAY_FFBSC;
                else
                   qr1        <= '0' after DELAY_FFBSC;
                end if;
             end if;

        when others => 
             null;
     end case;
  end process  prcs_qr1;
----------------------------------------------------------------------
  prcs_qr2:process(R, CLK)
  begin
-- FP TMP -- should CLK and R have to be rising_edge
     case AttrSRtype is
        when 0 => 
         --------------- // async SET/RESET
             if(R = '1') then
                qr2        <= '1' after DELAY_FFBSC;
             elsif(rising_edge(CLK)) then
                qr2        <= qr1 after DELAY_FFBSC;
             end if;

        when 1 => 
         --------------- // sync SET/RESET
             if(rising_edge(CLK)) then
                if(R = '1') then
                   qr2        <= '1' after DELAY_FFBSC;
                else
                   qr2        <= qr1 after DELAY_FFBSC;
                end if;
             end if;

        when others => 
             null;
     end case;
  end process  prcs_qr2;
--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(clkdiv_zd)
  begin
      CLKDIV_INT <= clkdiv_zd;
  end process prcs_output;
--####################################################################
end bscntrl_nodelay_V;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;


library unisim;
use unisim.vpkg.all;
use unisim.vcomponents.all;

--//////////////////////////////////////////////////////////// 
--///////////////// ICE_MODULE_NODELAY ///////////////////////
--//////////////////////////////////////////////////////////// 

entity ice_module_nodelay is
  generic(
      SRTYPE  : string;
      INIT_CE : bit_vector(1 downto 0)
      );
  port(
      ICE		: out std_ulogic;

      CE1		: in std_ulogic;
      CE2		: in std_ulogic;
      GSR		: in std_ulogic;
      NUM_CE		: in std_ulogic;
      CLKDIV		: in std_ulogic;
      R			: in std_ulogic
      );
end ice_module_nodelay;

architecture ice_module_nodelay_V of ice_module_nodelay is
--  constant DELAY_FFICE		: time := 300 ns;
--  constant DELAY_MXICE		: time := 60 ns;
  constant DELAY_FFICE			: time := 300 ps;
  constant DELAY_MXICE			: time := 60 ps;

  signal AttrSRtype		: integer := 0;

  signal ce1r			: std_ulogic := 'X';
  signal ce2r			: std_ulogic := 'X';
  signal cesel			: std_logic_vector(1 downto 0) := (others => 'X');

  signal ice_zd			: std_ulogic := 'X';

begin

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process
  begin

     if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
        AttrSrtype <= 0;
     elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
        AttrSrtype <= 1;
     end if;

     wait;
  end process prcs_init;

--###################################################################
--#####                      update cesel                       #####
--###################################################################

  cesel  <= NUM_CE & CLKDIV; 

--####################################################################
--#####                         registers                        #####
--####################################################################
  prcs_reg:process(CLKDIV, GSR)
  variable ce1r_var		:  std_ulogic := TO_X01(INIT_CE(1));
  variable ce2r_var		:  std_ulogic := TO_X01(INIT_CE(0));
  begin
     if(GSR = '1') then
         ce1r_var		:= TO_X01(INIT_CE(1));
         ce2r_var		:= TO_X01(INIT_CE(0));
     elsif(GSR = '0') then
        case AttrSRtype is
           when 0 => 
            --------------- // async SET/RESET
                if(R = '1') then
                   ce1r_var := '0';
                   ce2r_var := '0';
                elsif(rising_edge(CLKDIV)) then
                   ce1r_var := ce1;
                   ce2r_var := ce2;
                end if;

           when 1 => 
            --------------- // sync SET/RESET
                if(rising_edge(CLKDIV)) then
                   if(R = '1') then
                      ce1r_var := '0';
                      ce2r_var := '0';
                   else
                      ce1r_var := ce1;
                      ce2r_var := ce2;
                   end if;
                end if;

           when others => 
                null;

        end case;
    end if;

   ce1r <= ce1r_var after DELAY_FFICE;
   ce2r <= ce2r_var after DELAY_FFICE;

  end process prcs_reg;
--####################################################################
--#####                        Output mux                        #####
--####################################################################
  prcs_mux:process(cesel, ce1, ce1r, ce2r)
  begin
    case cesel is
        when "00" =>
             ice_zd  <= ce1;
        when "01" =>
             ice_zd  <= ce1;
-- 426606
        when "10" =>
             ice_zd  <= ce2r;
        when "11" =>
             ice_zd  <= ce1r;
        when others =>
             null;
    end case;
  end process  prcs_mux;

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(ice_zd)
  begin
      ICE <= ice_zd;
  end process prcs_output;
end ice_module_nodelay_V;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;

library STD;
use STD.TEXTIO.all;


library unisim;
use unisim.vpkg.all;
use unisim.vcomponents.all;
use unisim.vcomponents.all;

----- CELL ISERDES_NODELAY -----
--//////////////////////////////////////////////////////////// 
--////////////////////////// ISERDES_NODELAY /////////////////////////
--//////////////////////////////////////////////////////////// 

entity ISERDES_NODELAY is

  generic(


      BITSLIP_ENABLE	: boolean	:= false;
      DATA_RATE		: string	:= "DDR";
      DATA_WIDTH	: integer	:= 4;
      INIT_Q1		: bit		:= '0';
      INIT_Q2		: bit		:= '0';
      INIT_Q3		: bit		:= '0';
      INIT_Q4		: bit		:= '0';
      INTERFACE_TYPE	: string	:= "MEMORY";
      NUM_CE		: integer	:= 2;
      SERDES_MODE	: string	:= "MASTER"
      );

  port(
      Q1		: out std_ulogic;
      Q2		: out std_ulogic;
      Q3		: out std_ulogic;
      Q4		: out std_ulogic;
      Q5		: out std_ulogic;
      Q6		: out std_ulogic;
      SHIFTOUT1		: out std_ulogic;
      SHIFTOUT2		: out std_ulogic;

      BITSLIP		: in std_ulogic;
      CE1		: in std_ulogic;
      CE2		: in std_ulogic;
      CLK		: in std_ulogic;
      CLKB		: in std_ulogic;
      CLKDIV		: in std_ulogic;
      D			: in std_ulogic;
      OCLK		: in std_ulogic;
      RST		: in std_ulogic;
      SHIFTIN1		: in std_ulogic;
      SHIFTIN2		: in std_ulogic
    );

end ISERDES_NODELAY;

architecture ISERDES_NODELAY_V OF ISERDES_NODELAY is

component bscntrl_nodelay
  generic (
      SRTYPE            : string;
      INIT_BITSLIPCNT	: bit_vector(3 downto 0)
    );
  port(
      CLKDIV_INT        : out std_ulogic;
      MUXC              : out std_ulogic;

      BITSLIP           : in std_ulogic;
      C23               : in std_ulogic;
      C45               : in std_ulogic;
      C67               : in std_ulogic;
      CLK               : in std_ulogic;
      CLKDIV            : in std_ulogic;
      DATA_RATE         : in std_ulogic;
      GSR               : in std_ulogic;
      R                 : in std_ulogic;
      SEL               : in std_logic_vector (1 downto 0)
      );
end component;

component ice_module_nodelay
  generic(
      SRTYPE            : string;
      INIT_CE		: bit_vector(1 downto 0)
      );
  port(
      ICE		: out std_ulogic;

      CE1		: in std_ulogic;
      CE2		: in std_ulogic;
      GSR		: in std_ulogic;
      NUM_CE		: in std_ulogic;
      CLKDIV		: in std_ulogic;
      R			: in std_ulogic
      );
end component;


  constant SRVAL_Q1		: bit := '0';
  constant SRVAL_Q2		: bit := '0';
  constant SRVAL_Q3		: bit := '0';
  constant SRVAL_Q4		: bit := '0';

  constant DDR_CLK_EDGE		: string	:= "SAME_EDGE_PIPELINED";
  constant INIT_BITSLIPCNT	: bit_vector(3 downto 0) := "0000";
  constant INIT_CE		: bit_vector(1 downto 0) := "00";
  constant INIT_RANK1_PARTIAL	: bit_vector(4 downto 0) := "00000";
  constant INIT_RANK2		: bit_vector(5 downto 0) := "000000";
  constant INIT_RANK3		: bit_vector(5 downto 0) := "000000";
  constant SERDES		: boolean	:= TRUE;
  constant SRTYPE		: string	:= "ASYNC";

--  constant DELAY_FFINP          : time       := 300 ns; 
--  constant DELAY_MXINP1         : time       := 60  ns;
--  constant DELAY_MXINP2         : time       := 120 ns;
--  constant DELAY_OCLKDLY        : time       := 750 ns;

  constant SYNC_PATH_DELAY      : time       := 100 ps; 

  constant DELAY_FFINP          : time       := 300 ps; 
  constant DELAY_MXINP1         : time       := 60  ps;
  constant DELAY_MXINP2         : time       := 120 ps;
  constant DELAY_OCLKDLY        : time       := 750 ps;

  constant MAX_DATAWIDTH	: integer    := 4;

  signal BITSLIP_ipd	        : std_ulogic := 'X';
  signal CE1_ipd	        : std_ulogic := 'X';
  signal CE2_ipd	        : std_ulogic := 'X';
  signal CLK_ipd	        : std_ulogic := 'X';
  signal CLKB_ipd	        : std_ulogic := 'X';
  signal CLKDIV_ipd		: std_ulogic := 'X';
  signal D_ipd			: std_ulogic := 'X';
  signal GSR			: std_ulogic := '0';
  signal GSR_ipd		: std_ulogic := 'X';
  signal OCLK_ipd		: std_ulogic := 'X';
  signal RST_ipd		: std_ulogic := 'X';
  signal SHIFTIN1_ipd		: std_ulogic := 'X';
  signal SHIFTIN2_ipd		: std_ulogic := 'X';

  signal BITSLIP_dly	        : std_ulogic := 'X';
  signal CE1_dly	        : std_ulogic := 'X';
  signal CE2_dly	        : std_ulogic := 'X';
  signal CLK_dly	        : std_ulogic := 'X';
  signal CLKB_dly	        : std_ulogic := 'X';
  signal CLKDIV_dly		: std_ulogic := 'X';
  signal D_dly			: std_ulogic := 'X';
  signal GSR_dly		: std_ulogic := 'X';
  signal OCLK_dly		: std_ulogic := 'X';
  signal RST_dly		: std_ulogic := 'X';
  signal SHIFTIN1_dly		: std_ulogic := 'X';
  signal SHIFTIN2_dly		: std_ulogic := 'X';

  signal REV_dly		: std_ulogic := '0';
  signal SR_dly			: std_ulogic := '0';

  signal Q1_zd			: std_ulogic := 'X';
  signal Q2_zd			: std_ulogic := 'X';
  signal Q3_zd			: std_ulogic := 'X';
  signal Q4_zd			: std_ulogic := 'X';
  signal Q5_zd			: std_ulogic := 'X';
  signal Q6_zd			: std_ulogic := 'X';
  signal SHIFTOUT1_zd		: std_ulogic := 'X';
  signal SHIFTOUT2_zd		: std_ulogic := 'X';

  signal Q1_viol		: std_ulogic := 'X';
  signal Q2_viol		: std_ulogic := 'X';
  signal Q3_viol		: std_ulogic := 'X';
  signal Q4_viol		: std_ulogic := 'X';
  signal Q5_viol		: std_ulogic := 'X';
  signal Q6_viol		: std_ulogic := 'X';
  signal SHIFTOUT1_viol		: std_ulogic := 'X';
  signal SHIFTOUT2_viol		: std_ulogic := 'X';

  signal AttrSerdes		: std_ulogic := 'X';
  signal AttrMode		: std_ulogic := 'X';
  signal AttrDataRate		: std_ulogic := 'X';
  signal AttrDataWidth		: std_logic_vector(3 downto 0) := (others => 'X');
  signal AttrInterfaceType	: std_ulogic := 'X';
  signal AttrBitslipEnable	: std_ulogic := 'X';
  signal AttrNumCe		: std_ulogic := 'X';
  signal AttrDdrClkEdge		: std_logic_vector(1 downto 0) := (others => 'X');
  signal AttrSRtype		: integer := 0;
  signal AttrIobDelay		: integer := 0;

  signal sel1			: std_logic_vector(1 downto 0) := (others => 'X');
  signal selrnk3		: std_logic_vector(3 downto 0) := (others => 'X');
  signal bsmux			: std_logic_vector(2 downto 0) := (others => 'X');
  signal cntr			: std_logic_vector(4 downto 0) := (others => 'X');
  
  signal q1rnk1			: std_ulogic := 'X';
  signal q2nrnk1		: std_ulogic := 'X';
  signal q5rnk1			: std_ulogic := 'X';
  signal q6rnk1			: std_ulogic := 'X';
  signal q6prnk1		: std_ulogic := 'X';

  signal q1prnk1		: std_ulogic := 'X';
  signal q2prnk1		: std_ulogic := 'X';
  signal q3rnk1			: std_ulogic := 'X';
  signal q4rnk1			: std_ulogic := 'X';

  signal dataq5rnk1		: std_ulogic := 'X';
  signal dataq6rnk1		: std_ulogic := 'X';

  signal dataq3rnk1		: std_ulogic := 'X';
  signal dataq4rnk1		: std_ulogic := 'X';

  signal oclkmux		: std_ulogic := '0';
  signal memmux			: std_ulogic := '0';
  signal q2pmux			: std_ulogic := '0';

  signal clkdiv_int		: std_ulogic := '0';
  signal clkdivmux		: std_ulogic := '0';

  signal q1rnk2			: std_ulogic := 'X';
  signal q2rnk2			: std_ulogic := 'X';
  signal q3rnk2			: std_ulogic := 'X';
  signal q4rnk2			: std_ulogic := 'X';
  signal q5rnk2			: std_ulogic := 'X';
  signal q6rnk2			: std_ulogic := 'X';
  signal dataq1rnk2		: std_ulogic := 'X';
  signal dataq2rnk2		: std_ulogic := 'X';
  signal dataq3rnk2		: std_ulogic := 'X';
  signal dataq4rnk2		: std_ulogic := 'X';
  signal dataq5rnk2		: std_ulogic := 'X';
  signal dataq6rnk2		: std_ulogic := 'X';

  signal muxc			: std_ulogic := 'X';

  signal q1rnk3			: std_ulogic := 'X';
  signal q2rnk3			: std_ulogic := 'X';
  signal q3rnk3			: std_ulogic := 'X';
  signal q4rnk3			: std_ulogic := 'X';
  signal q5rnk3			: std_ulogic := 'X';
  signal q6rnk3			: std_ulogic := 'X';

  signal c23			: std_ulogic := 'X';
  signal c45			: std_ulogic := 'X';
  signal c67			: std_ulogic := 'X';
  signal sel			: std_logic_vector(1 downto 0) := (others => 'X');

  signal ice			: std_ulogic := 'X';
  signal datain			: std_ulogic := 'X';
  signal idelay_out		: std_ulogic := 'X';

  signal CLKN_dly		: std_ulogic := '0';

  procedure CR454107_msg(INTERFACE_TYPE : IN string;
                         DATA_RATE  : IN string;
                         DATA_WIDTH : IN integer) is

  variable Message : line;
  begin
        Write (Message, string'("DRC  Warning : The combination of INTERFACE_TYPE, DATA_RATE and DATA_WIDTH values on X_ISERDES_NODELAY component is not recommended."));
        Write (Message, LF);
        Write (Message, string'("The current settings are: INTERFACE_TYPE = "));
        Write (Message, INTERFACE_TYPE);
        Write (Message, string'(", DATA_RATE = "));
        Write (Message, DATA_RATE );
        Write (Message, string'(" and DATA_WIDTH = "));
        Write (Message, DATA_WIDTH );
        Write (Message, LF);
        Write (Message, string'("The recommended combinations of values are :"));
        Write (Message, LF);
        Write (Message, string'("NETWORKING SDR 2, 3, 4, 5, 6, 7, 8")); 
        Write (Message, LF);
        Write (Message, string'("NETWORKING DDR 4, 6, 8, 10")); 
        Write (Message, LF);
        Write (Message, string'("MEMORY SDR None")); 
        Write (Message, LF);
        Write (Message, string'("MEMORY DDR 4")); 
        assert false report Message.all severity Warning;
        DEALLOCATE (Message);
   end CR454107_msg;
begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  BITSLIP_dly    	 <= BITSLIP        	after 0 ps;
  CE1_dly        	 <= CE1            	after 0 ps;
  CE2_dly        	 <= CE2            	after 0 ps;
  CLK_dly        	 <= CLK            	after 0 ps;
  CLKB_dly        	 <= CLKB            	after 0 ps;
  CLKDIV_dly     	 <= CLKDIV         	after 0 ps;
  D_dly          	 <= D              	after 0 ps;
  GSR_dly        	 <= GSR            	after 0 ps;
  OCLK_dly       	 <= OCLK           	after 0 ps;
  RST_dly        	 <= RST            	after 0 ps;
  SHIFTIN1_dly   	 <= SHIFTIN1       	after 0 ps;
  SHIFTIN2_dly   	 <= SHIFTIN2       	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

  SR_dly <= RST_dly;

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process
  variable AttrSerdes_var		: std_ulogic := 'X';
  variable AttrMode_var			: std_ulogic := 'X';
  variable AttrDataRate_var		: std_ulogic := 'X';
  variable AttrDataWidth_var		: std_logic_vector(3 downto 0) := (others => 'X');
  variable AttrInterfaceType_var	: std_ulogic := 'X';
  variable AttrBitslipEnable_var	: std_ulogic := 'X';
  variable AttrDdrClkEdge_var		: std_logic_vector(1 downto 0) := (others => 'X');
  variable AttrIobDelay_var		: integer := 0;

  begin
      --------CR 454107  DRC Warning -- INTERFACE_TYPE / DATA_RATE /  DATA_WIDTH combinations  ------------------
      if (INTERFACE_TYPE = "NETWORKING") then
         if(DATA_RATE = "SDR")then 
            case (DATA_WIDTH) is
                when 2|3|4|5|6|7|8  => null;
                when others       => CR454107_msg(INTERFACE_TYPE, DATA_RATE, DATA_WIDTH);
            end case;
         elsif(DATA_RATE = "DDR")then 
            case (DATA_WIDTH) is
                when 4|6|8|10 => null;
                when others       => CR454107_msg(INTERFACE_TYPE, DATA_RATE, DATA_WIDTH);
            end case;
         end if;
      elsif (INTERFACE_TYPE = "MEMORY") then
         if(DATA_RATE = "DDR")then 
            case (DATA_WIDTH) is
                when 4  => null;
                when others       => CR454107_msg(INTERFACE_TYPE, DATA_RATE, DATA_WIDTH);
            end case;
         elsif(DATA_RATE = "SDR")then 
                CR454107_msg(INTERFACE_TYPE, DATA_RATE, DATA_WIDTH);
         end if;
      end if;

      --------CR 447760  DRC -- BITSLIP - INTERFACE_TYPE combination  ------------------

      if((INTERFACE_TYPE = "MEMORY") and (BITSLIP_ENABLE = TRUE)) then
        assert false
        report "Attribute Syntax Error: BITSLIP_ENABLE is currently set to TRUE when INTERFACE_TYPE is set to MEMORY. This is an invalid configuration."
        severity Failure;
     elsif((INTERFACE_TYPE = "NETWORKING") and (BITSLIP_ENABLE = FALSE)) then
        assert false
        report "Attribute Syntax Error: BITSLIP_ENABLE is currently set to FALSE when INTERFACE_TYPE is set to NETWORKING. If BITSLIP is not intended to be used, please set BITSLIP_ENABLE to TRUE and tie the BITSLIP port to ground."
        severity Failure;
     end if;

      -------------------- SERDES validity check --------------------
      if(SERDES = true) then
        AttrSerdes_var := '1';
      else
        AttrSerdes_var := '0';
      end if;

      ------------- SERDES_MODE validity check --------------------
      if((SERDES_MODE = "MASTER") or (SERDES_MODE = "master")) then
         AttrMode_var := '0';
      elsif((SERDES_MODE = "SLAVE") or (SERDES_MODE = "slave")) then
         AttrMode_var := '1';
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => "SERDES_MODE ",
             EntityName => "/ISERDES_NODELAY",
             GenericValue => SERDES_MODE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " MASTER or SLAVE.",
             TailMsg => "",
             MsgSeverity => FAILURE 
         );
      end if;

      ------------------ DATA_RATE validity check ------------------
      if((DATA_RATE = "DDR") or (DATA_RATE = "ddr")) then
         AttrDataRate_var := '0';
      elsif((DATA_RATE = "SDR") or (DATA_RATE = "sdr")) then
         AttrDataRate_var := '1';
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " DATA_RATE ",
             EntityName => "/ISERDES_NODELAY",
             GenericValue => DATA_RATE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " DDR or SDR. ",
             TailMsg => "",
             MsgSeverity => Failure
         );
      end if;

      ------------------ DATA_WIDTH validity check ------------------
      if((DATA_WIDTH = 2) or (DATA_WIDTH = 3) or  (DATA_WIDTH = 4) or
         (DATA_WIDTH = 5) or (DATA_WIDTH = 6) or  (DATA_WIDTH = 7) or
         (DATA_WIDTH = 8) or (DATA_WIDTH = 10)) then
         AttrDataWidth_var := CONV_STD_LOGIC_VECTOR(DATA_WIDTH, MAX_DATAWIDTH); 
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " DATA_WIDTH ",
             EntityName => "/ISERDES_NODELAY",
             GenericValue => DATA_WIDTH,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " 2, 3, 4, 5, 6, 7, 8, or 10 ",
             TailMsg => "",
             MsgSeverity => Failure
         );
      end if;
      ------------ DATA_WIDTH /DATA_RATE combination check ------------
      if((DATA_RATE = "DDR") or (DATA_RATE = "ddr")) then
         case (DATA_WIDTH) is
             when 4|6|8|10  => null;
             when others       =>
                GenericValueCheckMessage
                (  HeaderMsg  => " Attribute Syntax Warning ",
                   GenericName => " DATA_WIDTH ",
                   EntityName => "/ISERDES_NODELAY",
                   GenericValue => DATA_WIDTH,
                   Unit => "",
                   ExpectedValueMsg => " The Legal values for DDR mode are ",
                   ExpectedGenericValue => " 4, 6, 8, or 10 ",
                   TailMsg => "",
                   MsgSeverity => Failure
                );
          end case;
      end if;

      if((DATA_RATE = "SDR") or (DATA_RATE = "sdr")) then
         case (DATA_WIDTH) is
             when 2|3|4|5|6|7|8  => null;
             when others       =>
                GenericValueCheckMessage
                (  HeaderMsg  => " Attribute Syntax Warning ",
                   GenericName => " DATA_WIDTH ",
                   EntityName => "/ISERDES_NODELAY",
                   GenericValue => DATA_WIDTH,
                   Unit => "",
                   ExpectedValueMsg => " The Legal values for SDR mode are ",
                   ExpectedGenericValue => " 2, 3, 4, 5, 6, 7 or 8",
                   TailMsg => "",
                   MsgSeverity => Failure
                );
          end case;
      end if;
      ---------------- INTERFACE_TYPE validity check ---------------
      if((INTERFACE_TYPE = "MEMORY") or (INTERFACE_TYPE = "memory")) then
         AttrInterfaceType_var := '0';
      elsif((INTERFACE_TYPE = "NETWORKING") or (INTERFACE_TYPE = "networking")) then
         AttrInterfaceType_var := '1';
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => "INTERFACE_TYPE ",
             EntityName => "/ISERDES_NODELAY",
             GenericValue => INTERFACE_TYPE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " MEMORY or NETWORKING.",
             TailMsg => "",
             MsgSeverity => FAILURE 
         );
      end if;

      ---------------- BITSLIP_ENABLE validity check -------------------
      if(BITSLIP_ENABLE = false) then
         AttrBitslipEnable_var := '0';
      elsif(BITSLIP_ENABLE = true) then
         AttrBitslipEnable_var := '1';
      else
        GenericValueCheckMessage
          (  HeaderMsg  => " Attribute Syntax Warning ",
             GenericName => " BITSLIP_ENABLE ",
             EntityName => "/ISERDES_NODELAY",
             GenericValue => BITSLIP_ENABLE,
             Unit => "",
             ExpectedValueMsg => " The Legal values for this attribute are ",
             ExpectedGenericValue => " TRUE or FALSE ",
             TailMsg => "",
             MsgSeverity => Failure
         );
      end if;

      ----------------     NUM_CE validity check    -------------------
      case NUM_CE is
         when 1 =>
                AttrNumCe <= '0';
         when 2 =>
                AttrNumCe <= '1';
         when others =>
                GenericValueCheckMessage
                  (  HeaderMsg  => " Attribute Syntax Warning ",
                     GenericName => " NUM_CE ",
                     EntityName => "/ISERDES_NODELAY",
                     GenericValue => NUM_CE,
                     Unit => "",
                     ExpectedValueMsg => " The Legal values for this attribute are ",
                     ExpectedGenericValue => " 1 or 2 ",
                     TailMsg => "",
                     MsgSeverity => Failure
                  );
      end case;
--
--
--
      ------------------ DDR_CLK_EDGE validity check ------------------
         AttrDdrClkEdge_var := "00";

--      if((DDR_CLK_EDGE = "SAME_EDGE_PIPELINED") or (DDR_CLK_EDGE = "same_edge_pipelined")) then
--         AttrDdrClkEdge_var := "00";
--      elsif((DDR_CLK_EDGE = "SAME_EDGE") or (DDR_CLK_EDGE = "same_edge")) then
--         AttrDdrClkEdge_var := "01";
--      elsif((DDR_CLK_EDGE = "OPPOSITE_EDGE") or (DDR_CLK_EDGE = "opposite_edge")) then
--         AttrDdrClkEdge_var := "10";
--      else
--        GenericValueCheckMessage
--          (  HeaderMsg  => " Attribute Syntax Warning ",
--             GenericName => " DDR_CLK_EDGE ",
--             EntityName => "/ISERDES_NODELAY",
--             GenericValue => DDR_CLK_EDGE,
--             Unit => "",
--             ExpectedValueMsg => " The Legal values for this attribute are ",
--             ExpectedGenericValue => " SAME_EDGE_PIPELINED or SAME_EDGE or OPPOSITE_EDGE ",
--             TailMsg => "",
--             MsgSeverity => Failure
--         );
--      end if;
      ------------------ DATA_RATE validity check ------------------
         AttrSrtype <= 0;

--      if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then
--         AttrSrtype <= 0;
--      elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then
--         AttrSrtype <= 1;
--      else
--        GenericValueCheckMessage
--          (  HeaderMsg  => " Attribute Syntax Warning ",
--             GenericName => " SRTYPE ",
--             EntityName => "/ISERDES_NODELAY",
--             GenericValue => SRTYPE,
--             Unit => "",
--             ExpectedValueMsg => " The Legal values for this attribute are ",
--             ExpectedGenericValue => " ASYNC or SYNC. ",
--             TailMsg => "",
--             MsgSeverity => ERROR
--         );
--      end if;
---------------------------------------------------------------------

     AttrSerdes		<= AttrSerdes_var;
     AttrMode		<= AttrMode_var;
     AttrDataRate	<= AttrDataRate_var;
     AttrDataWidth	<= AttrDataWidth_var;
     AttrInterfaceType	<= AttrInterfaceType_var;
     AttrBitslipEnable	<= AttrBitslipEnable_var;
     AttrDdrClkEdge	<= AttrDdrClkEdge_var;
     AttrIobDelay	<= AttrIobDelay_var;

     sel1     <= AttrMode_var & AttrDataRate_var; 
     selrnk3  <= AttrSerdes_var & AttrBitslipEnable_var & AttrDdrClkEdge_var; 
     cntr     <= AttrDataRate_var & AttrDataWidth_var;

     wait;
  end process prcs_init;

--###################################################################
--#####               SHIFTOUT1 and SHIFTOUT2                   #####
--###################################################################

  SHIFTOUT2_zd <= q5rnk1;
  SHIFTOUT1_zd <= q6rnk1;

--###################################################################
--#####               SHIFTOUT1 and SHIFTOUT2                   #####
--###################################################################

  datain <= D_dly;

--###################################################################
--#####                     q1rnk1 reg                          #####
--###################################################################
  prcs_Q1_rnk1:process(CLK_dly, GSR_dly, REV_dly, SR_dly)
  variable q1rnk1_var         : std_ulogic := TO_X01(INIT_Q1);
  begin
     if(GSR_dly = '1') then
         q1rnk1_var  :=  TO_X01(INIT_Q1);
     elsif(GSR_dly = '0') then
        case AttrSRtype is
           when 0 => 
           --------------- // async SET/RESET
                   if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q1) = '1')))) then
                      q1rnk1_var := TO_X01(SRVAL_Q1);
                   elsif(REV_dly = '1') then
                      q1rnk1_var := not TO_X01(SRVAL_Q1);
                   elsif((SR_dly = '0') and (REV_dly = '0')) then
                      if(ice = '1') then
                         if(rising_edge(CLK_dly)) then
                            q1rnk1_var := datain;
                         end if;
                      end if;
                   end if;

           when 1 => 
           --------------- // sync SET/RESET
                   if(rising_edge(CLK_dly)) then
                      if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q1) = '1')))) then
                         q1rnk1_var := TO_X01(SRVAL_Q1);
                      Elsif(REV_dly = '1') then
                         q1rnk1_var := not TO_X01(SRVAL_Q1);
                      elsif((SR_dly = '0') and (REV_dly = '0')) then
                         if(ice = '1') then
                            q1rnk1_var := datain;
                         end if;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     q1rnk1  <= q1rnk1_var  after DELAY_FFINP;

  end process prcs_Q1_rnk1;
--###################################################################
--#####              q5rnk1, q6rnk1 and q6prnk1 reg             #####
--###################################################################
  prcs_Q5Q6Q6p_rnk1:process(CLK_dly, GSR_dly, SR_dly)
  variable q5rnk1_var         : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(2));
  variable q6rnk1_var         : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(1));
  variable q6prnk1_var        : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(0));
  begin
     if(GSR_dly = '1') then
         q5rnk1_var  := TO_X01(INIT_RANK1_PARTIAL(2));
         q6rnk1_var  := TO_X01(INIT_RANK1_PARTIAL(1));
         q6prnk1_var := TO_X01(INIT_RANK1_PARTIAL(0));
     elsif(GSR_dly = '0') then
        case AttrSRtype is
           when 0 => 
           --------- // async SET/RESET  -- Not full featured FFs
                   if(SR_dly = '1') then
                      q5rnk1_var  := '0';
                      q6rnk1_var  := '0';
                      q6prnk1_var := '0';
                   elsif(SR_dly = '0') then
                      if(rising_edge(CLK_dly)) then
                         q5rnk1_var  := dataq5rnk1;
                         q6rnk1_var  := dataq6rnk1;
                         q6prnk1_var := q6rnk1;
                      end if;
                   end if;

           when 1 => 
           --------- // sync SET/RESET  -- Not full featured FFs
                   if(rising_edge(CLK_dly)) then
                      if(SR_dly = '1') then
                         q5rnk1_var  := '0';
                         q6rnk1_var  := '0';
                         q6prnk1_var := '0';
                      elsif(SR_dly = '0') then
                         q5rnk1_var  := dataq5rnk1;
                         q6rnk1_var  := dataq6rnk1;
                         q6prnk1_var := q6rnk1;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     q5rnk1  <= q5rnk1_var  after DELAY_FFINP;
     q6rnk1  <= q6rnk1_var  after DELAY_FFINP;
     q6prnk1 <= q6prnk1_var after DELAY_FFINP;

  end process prcs_Q5Q6Q6p_rnk1;
--###################################################################
--#####                     q2nrnk1 reg                          #####
--###################################################################
  prcs_Q2_rnk1:process(CLKB_dly, GSR_dly, SR_dly, REV_dly)
  variable q2nrnk1_var         : std_ulogic := TO_X01(INIT_Q2);
  begin
     if(GSR_dly = '1') then
         q2nrnk1_var  := TO_X01(INIT_Q2);
     elsif(GSR_dly = '0') then
        case AttrSRtype is
           when 0 => 
           --------------- // async SET/RESET
                   if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q2) = '1')))) then
                      q2nrnk1_var  := TO_X01(SRVAL_Q2);
                   elsif(REV_dly = '1') then
                      q2nrnk1_var  := not TO_X01(SRVAL_Q2);
                   elsif((SR_dly = '0') and (REV_dly = '0')) then
                      if(ice = '1') then
                         if(rising_edge(CLKB_dly)) then
                            q2nrnk1_var     := datain;
                         end if;
                      end if;
                   end if;

           when 1 => 
           --------------- // sync SET/RESET
                   if(rising_edge(CLKB_dly)) then
                      if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q2) = '1')))) then
                         q2nrnk1_var  := TO_X01(SRVAL_Q2);
                      elsif(REV_dly = '1') then
                         q2nrnk1_var  := not TO_X01(SRVAL_Q2);
                      elsif((SR_dly = '0') and (REV_dly = '0')) then
                         if(ice = '1') then
                            q2nrnk1_var := datain;
                         end if;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     q2nrnk1  <= q2nrnk1_var after DELAY_FFINP;

  end process prcs_Q2_rnk1;
--###################################################################
--#####                       q2prnk1 reg                       #####
--###################################################################
  prcs_Q2p_rnk1:process(q2pmux, GSR_dly, REV_dly, SR_dly)
  variable q2prnk1_var        : std_ulogic := TO_X01(INIT_Q4);
  begin
     if(GSR_dly = '1') then
         q2prnk1_var := TO_X01(INIT_Q4);
     elsif(GSR_dly = '0') then
        case AttrSRtype is
           when 0 => 
           --------------- // async SET/RESET
                   if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q4) = '1')))) then
                      q2prnk1_var := TO_X01(SRVAL_Q4);
                   elsif(REV_dly = '1') then
                      q2prnk1_var := not TO_X01(SRVAL_Q4);
                   elsif((SR_dly = '0') and (REV_dly = '0')) then
                      if(ice = '1') then
                         if(rising_edge(q2pmux)) then
                            q2prnk1_var := q2nrnk1;
                         end if;
                      end if;
                   end if;

           when 1 => 
           --------------- // sync SET/RESET
                   if(rising_edge(q2pmux)) then
                      if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q4) = '1')))) then
                         q2prnk1_var := TO_X01(SRVAL_Q4);
                      elsif(REV_dly = '1') then
                         q2prnk1_var := not TO_X01(SRVAL_Q4);
                      elsif((SR_dly = '0') and (REV_dly = '0')) then
                         if(ice = '1') then
                              q2prnk1_var := q2nrnk1;
                         end if;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     q2prnk1  <= q2prnk1_var after DELAY_FFINP;

  end process prcs_Q2p_rnk1;
--###################################################################
--#####                      q1prnk1  reg                       #####
--###################################################################
  prcs_Q1p_rnk1:process(memmux, GSR_dly, REV_dly, SR_dly)
  variable q1prnk1_var        : std_ulogic := TO_X01(INIT_Q3);
  begin
     if(GSR_dly = '1') then
         q1prnk1_var := TO_X01(INIT_Q3);
     elsif(GSR_dly = '0') then
        case AttrSRtype is
           when 0 => 
           --------------- // async SET/RESET
                   if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q3) = '1')))) then
                      q1prnk1_var := TO_X01(SRVAL_Q3);
                   elsif(REV_dly = '1') then
                      q1prnk1_var := not TO_X01(SRVAL_Q3);
                   elsif((SR_dly = '0') and (REV_dly = '0')) then
                      if(ice = '1') then
                         if(rising_edge(memmux)) then
                            q1prnk1_var := q1rnk1;
                         end if;
                      end if;
                   end if;


           when 1 => 
           --------------- // sync SET/RESET
                   if(rising_edge(memmux)) then
                      if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q3) = '1')))) then
                         q1prnk1_var := TO_X01(SRVAL_Q3);
                      elsif(REV_dly = '1') then
                         q1prnk1_var := not TO_X01(SRVAL_Q3);
                      elsif((SR_dly = '0') and (REV_dly = '0')) then
                         if(ice = '1') then
                            q1prnk1_var := q1rnk1;
                         end if;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     q1prnk1  <= q1prnk1_var after DELAY_FFINP;

  end process prcs_Q1p_rnk1;
--###################################################################
--#####                  q3rnk1 and q4rnk1 reg                  #####
--###################################################################
  prcs_Q3Q4_rnk1:process(memmux, GSR_dly, SR_dly)
  variable q3rnk1_var         : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(4));
  variable q4rnk1_var         : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(3));
  begin
     if(GSR_dly = '1') then
         q3rnk1_var  := TO_X01(INIT_RANK1_PARTIAL(4));
         q4rnk1_var  := TO_X01(INIT_RANK1_PARTIAL(3));
     elsif(GSR_dly = '0') then
        case AttrSRtype is
           when 0 => 
           -------- // async SET/RESET  -- not fully featured FFs
                   if(SR_dly = '1') then
                      q3rnk1_var  := '0';
                      q4rnk1_var  := '0';
                   elsif(SR_dly = '0') then
                      if(rising_edge(memmux)) then
                         q3rnk1_var  := dataq3rnk1;
                         q4rnk1_var  := dataq4rnk1;
                      end if;
                   end if;

           when 1 => 
           -------- // sync SET/RESET -- not fully featured FFs
                   if(rising_edge(memmux)) then
                      if(SR_dly = '1') then
                         q3rnk1_var  := '0';
                         q4rnk1_var  := '0';
                      elsif(SR_dly = '0') then
                         q3rnk1_var  := dataq3rnk1;
                         q4rnk1_var  := dataq4rnk1;
                      end if;
                   end if;

           when others =>
                   null;
                        
        end case;
     end if;

     q3rnk1   <= q3rnk1_var after DELAY_FFINP;
     q4rnk1   <= q4rnk1_var after DELAY_FFINP;

  end process prcs_Q3Q4_rnk1;
--###################################################################
--#####        clock mux --  oclkmux with delay element         #####
--###################################################################
--  prcs_oclkmux:process(OCLK_dly)
--  begin
--     case AttrOclkDelay is
--           when '0' => 
--                    oclkmux <= OCLK_dly after DELAY_MXINP1;
--           when '1' => 
--                    oclkmux <= OCLK_dly after DELAY_OCLKDLY;
--           when others =>
--                    oclkmux <= OCLK_dly after DELAY_MXINP1;
--     end case;
--  end process prcs_oclkmux;
--
--
--
--///////////////////////////////////////////////////////////////////
--// Mux elements for the 1st Rank
--///////////////////////////////////////////////////////////////////
--###################################################################
--#####              memmux -- 4 clock muxes in first rank      #####
--###################################################################
  prcs_memmux:process(CLK_dly, OCLK_dly)
  begin
     case AttrInterfaceType is
           when '0' => 
                    memmux <= OCLK_dly after DELAY_MXINP1;
           when '1' => 
                    memmux <= CLK_dly after DELAY_MXINP1;
           when others =>
                    memmux <= OCLK_dly after DELAY_MXINP1;
     end case;
  end process prcs_memmux;

--###################################################################
--#####      q2pmux -- Optional inverter for q2p (4th flop in rank1)
--###################################################################
  prcs_q2pmux:process(memmux)
  begin
     case AttrInterfaceType is
           when '0' => 
                    q2pmux <= not memmux after DELAY_MXINP1;
           when '1' => 
                    q2pmux <= memmux after DELAY_MXINP1;
           when others =>
                    q2pmux <= memmux after DELAY_MXINP1;
     end case;
  end process prcs_q2pmux;
--###################################################################
--#####                data input muxes for q3q4  and q5q6      #####
--###################################################################
  prcs_Q3Q4_mux:process(q1prnk1, q2prnk1, q3rnk1, SHIFTIN1_dly, SHIFTIN2_dly)
  begin
     case sel1 is
           when "00" =>
                    dataq3rnk1 <= q1prnk1 after DELAY_MXINP1;
                    dataq4rnk1 <= q2prnk1 after DELAY_MXINP1;
           when "01" =>
                    dataq3rnk1 <= q1prnk1 after DELAY_MXINP1;
                    dataq4rnk1 <= q3rnk1  after DELAY_MXINP1;
           when "10" =>
                    dataq3rnk1 <= SHIFTIN2_dly after DELAY_MXINP1;
                    dataq4rnk1 <= SHIFTIN1_dly after DELAY_MXINP1;
           when "11" =>
                    dataq3rnk1 <= SHIFTIN1_dly after DELAY_MXINP1;
                    dataq4rnk1 <= q3rnk1   after DELAY_MXINP1;
           when others =>
                    dataq3rnk1 <= q1prnk1 after DELAY_MXINP1;
                    dataq4rnk1 <= q2prnk1 after DELAY_MXINP1;
     end case;

  end process prcs_Q3Q4_mux;
----------------------------------------------------------------------
  prcs_Q5Q6_mux:process(q3rnk1, q4rnk1, q5rnk1)
  begin
     case AttrDataRate is 
           when '0' =>
                    dataq5rnk1 <= q3rnk1 after DELAY_MXINP1;
                    dataq6rnk1 <= q4rnk1 after DELAY_MXINP1;
           when '1' =>
                    dataq5rnk1 <= q4rnk1 after DELAY_MXINP1;
                    dataq6rnk1 <= q5rnk1 after DELAY_MXINP1;
           when others =>
                    dataq5rnk1 <= q4rnk1 after DELAY_MXINP1;
                    dataq6rnk1 <= q5rnk1 after DELAY_MXINP1;
     end case;
  end process prcs_Q5Q6_mux;



---////////////////////////////////////////////////////////////////////
---                       2nd rank of registors
---////////////////////////////////////////////////////////////////////

--###################################################################
--#####    clkdivmux to choose between clkdiv_int or CLKDIV     #####
--###################################################################
  prcs_clkdivmux:process(clkdiv_int, CLKDIV_dly)
  begin
     case AttrBitslipEnable is
           when '0' =>
                    clkdivmux <= CLKDIV_dly after DELAY_MXINP1;
           when '1' =>
                    clkdivmux <= clkdiv_int after DELAY_MXINP1;
           when others =>
                    clkdivmux <= CLKDIV_dly after DELAY_MXINP1;
     end case;
  end process prcs_clkdivmux;

--###################################################################
--#####  q1rnk2, q2rnk2, q3rnk2,q4rnk2 ,q5rnk2 and q6rnk2 reg   #####
--###################################################################
  prcs_Q1Q2Q3Q4Q5Q6_rnk2:process(clkdivmux, GSR_dly, SR_dly)
  variable q1rnk2_var         : std_ulogic := TO_X01(INIT_RANK2(0));
  variable q2rnk2_var         : std_ulogic := TO_X01(INIT_RANK2(1));
  variable q3rnk2_var         : std_ulogic := TO_X01(INIT_RANK2(2));
  variable q4rnk2_var         : std_ulogic := TO_X01(INIT_RANK2(3));
  variable q5rnk2_var         : std_ulogic := TO_X01(INIT_RANK2(4));
  variable q6rnk2_var         : std_ulogic := TO_X01(INIT_RANK2(5));
  begin
     if(GSR_dly = '1') then
         q1rnk2_var := TO_X01(INIT_RANK2(0));
         q2rnk2_var := TO_X01(INIT_RANK2(1));
         q3rnk2_var := TO_X01(INIT_RANK2(2));
         q4rnk2_var := TO_X01(INIT_RANK2(3));
         q5rnk2_var := TO_X01(INIT_RANK2(4));
         q6rnk2_var := TO_X01(INIT_RANK2(5));
     elsif(GSR_dly = '0') then
        case AttrSRtype is
           when 0 => 
           --------------- // async SET/RESET
                   if(SR_dly = '1') then
                      q1rnk2_var := '0';
                      q2rnk2_var := '0';
                      q3rnk2_var := '0';
                      q4rnk2_var := '0';
                      q5rnk2_var := '0';
                      q6rnk2_var := '0';
                   elsif(SR_dly = '0') then
                       if(rising_edge(clkdivmux)) then
                           q1rnk2_var := dataq1rnk2;
                           q2rnk2_var := dataq2rnk2;
                           q3rnk2_var := dataq3rnk2;
                           q4rnk2_var := dataq4rnk2;
                           q5rnk2_var := dataq5rnk2;
                           q6rnk2_var := dataq6rnk2;
                       end if;
                   end if;

           when 1 => 
           --------------- // sync SET/RESET
                   if(rising_edge(clkdivmux)) then
                      if(SR_dly = '1') then
                         q1rnk2_var := '0';
                         q2rnk2_var := '0';
                         q3rnk2_var := '0';
                         q4rnk2_var := '0';
                         q5rnk2_var := '0';
                         q6rnk2_var := '0';
                      elsif(SR_dly = '0') then
                         q1rnk2_var := dataq1rnk2;
                         q2rnk2_var := dataq2rnk2;
                         q3rnk2_var := dataq3rnk2;
                         q4rnk2_var := dataq4rnk2;
                         q5rnk2_var := dataq5rnk2;
                         q6rnk2_var := dataq6rnk2;
                      end if;
                   end if;
           when others =>
                   null;
        end case;
     end if;

     q1rnk2  <= q1rnk2_var after DELAY_FFINP;
     q2rnk2  <= q2rnk2_var after DELAY_FFINP;
     q3rnk2  <= q3rnk2_var after DELAY_FFINP;
     q4rnk2  <= q4rnk2_var after DELAY_FFINP;
     q5rnk2  <= q5rnk2_var after DELAY_FFINP;
     q6rnk2  <= q6rnk2_var after DELAY_FFINP;

  end process prcs_Q1Q2Q3Q4Q5Q6_rnk2;

--###################################################################
--#####                    update bitslip mux                   #####
--###################################################################

  bsmux  <= AttrBitslipEnable & AttrDataRate & muxc; 

--###################################################################
--#####    Data mux for 2nd rank of registers                  ######
--###################################################################
  prcs_Q1Q2Q3Q4Q5Q6_rnk2_mux:process(bsmux, q1rnk1, q1prnk1, q2prnk1, 
                           q3rnk1, q4rnk1, q5rnk1, q6rnk1, q6prnk1)
  begin
     case bsmux is
        when "000" | "001" =>
                 dataq1rnk2 <= q2prnk1 after DELAY_MXINP2;
                 dataq2rnk2 <= q1prnk1 after DELAY_MXINP2;
                 dataq3rnk2 <= q4rnk1  after DELAY_MXINP2;
                 dataq4rnk2 <= q3rnk1  after DELAY_MXINP2;
                 dataq5rnk2 <= q6rnk1  after DELAY_MXINP2;
                 dataq6rnk2 <= q5rnk1  after DELAY_MXINP2;
        when "100"  =>
                 dataq1rnk2 <= q2prnk1 after DELAY_MXINP2;
                 dataq2rnk2 <= q1prnk1 after DELAY_MXINP2;
                 dataq3rnk2 <= q4rnk1  after DELAY_MXINP2;
                 dataq4rnk2 <= q3rnk1  after DELAY_MXINP2;
                 dataq5rnk2 <= q6rnk1  after DELAY_MXINP2;
                 dataq6rnk2 <= q5rnk1  after DELAY_MXINP2;
        when "101"  =>
                 dataq1rnk2 <= q1prnk1 after DELAY_MXINP2;
                 dataq2rnk2 <= q4rnk1  after DELAY_MXINP2;
                 dataq3rnk2 <= q3rnk1  after DELAY_MXINP2;
                 dataq4rnk2 <= q6rnk1  after DELAY_MXINP2;
                 dataq5rnk2 <= q5rnk1  after DELAY_MXINP2;
                 dataq6rnk2 <= q6prnk1 after DELAY_MXINP2;
        when "010" | "011" | "110" | "111" =>
                 dataq1rnk2 <= q1rnk1  after DELAY_MXINP2;
                 dataq2rnk2 <= q1prnk1 after DELAY_MXINP2;
                 dataq3rnk2 <= q3rnk1  after DELAY_MXINP2;
                 dataq4rnk2 <= q4rnk1  after DELAY_MXINP2;
                 dataq5rnk2 <= q5rnk1  after DELAY_MXINP2;
                 dataq6rnk2 <= q6rnk1  after DELAY_MXINP2;
        when others =>
                 dataq1rnk2 <= q2prnk1 after DELAY_MXINP2;
                 dataq2rnk2 <= q1prnk1 after DELAY_MXINP2;
                 dataq3rnk2 <= q4rnk1  after DELAY_MXINP2;
                 dataq4rnk2 <= q3rnk1  after DELAY_MXINP2;
                 dataq5rnk2 <= q6rnk1  after DELAY_MXINP2;
                 dataq6rnk2 <= q5rnk1  after DELAY_MXINP2;
     end case;
  end process prcs_Q1Q2Q3Q4Q5Q6_rnk2_mux;

---////////////////////////////////////////////////////////////////////
---                       3rd rank of registors
---////////////////////////////////////////////////////////////////////

--###################################################################
--#####  q1rnk3, q2rnk3, q3rnk3, q4rnk3, q5rnk3 and q6rnk3 reg   #####
--###################################################################
  prcs_Q1Q2Q3Q4Q5Q6_rnk3:process(CLKDIV_dly, GSR_dly, SR_dly)
  variable q1rnk3_var         : std_ulogic := TO_X01(INIT_RANK3(0));
  variable q2rnk3_var         : std_ulogic := TO_X01(INIT_RANK3(1));
  variable q3rnk3_var         : std_ulogic := TO_X01(INIT_RANK3(2));
  variable q4rnk3_var         : std_ulogic := TO_X01(INIT_RANK3(3));
  variable q5rnk3_var         : std_ulogic := TO_X01(INIT_RANK3(4));
  variable q6rnk3_var         : std_ulogic := TO_X01(INIT_RANK3(5));
  begin
     if(GSR_dly = '1') then
         q1rnk3_var := TO_X01(INIT_RANK3(0));
         q2rnk3_var := TO_X01(INIT_RANK3(1));
         q3rnk3_var := TO_X01(INIT_RANK3(2));
         q4rnk3_var := TO_X01(INIT_RANK3(3));
         q5rnk3_var := TO_X01(INIT_RANK3(4));
         q6rnk3_var := TO_X01(INIT_RANK3(5));
     elsif(GSR_dly = '0') then
        case AttrSRtype is
           when 0 => 
           --------------- // async SET/RESET
                   if(SR_dly = '1') then
                      q1rnk3_var := '0';
                      q2rnk3_var := '0';
                      q3rnk3_var := '0';
                      q4rnk3_var := '0';
                      q5rnk3_var := '0';
                      q6rnk3_var := '0';
                   elsif(SR_dly = '0') then
                       if(rising_edge(CLKDIV_dly)) then
                           q1rnk3_var := q1rnk2;
                           q2rnk3_var := q2rnk2;
                           q3rnk3_var := q3rnk2;
                           q4rnk3_var := q4rnk2;
                           q5rnk3_var := q5rnk2;
                           q6rnk3_var := q6rnk2;
                        end if;
                   end if;

           when 1 => 
           --------------- // sync SET/RESET
                   if(rising_edge(CLKDIV_dly)) then
                      if(SR_dly = '1') then
                         q1rnk3_var := '0';
                         q2rnk3_var := '0';
                         q3rnk3_var := '0';
                         q4rnk3_var := '0';
                         q5rnk3_var := '0';
                         q6rnk3_var := '0';
                      elsif(SR_dly = '0') then
                         q1rnk3_var := q1rnk2;
                         q2rnk3_var := q2rnk2;
                         q3rnk3_var := q3rnk2;
                         q4rnk3_var := q4rnk2;
                         q5rnk3_var := q5rnk2;
                         q6rnk3_var := q6rnk2;
                      end if;
                   end if;
           when others =>
                   null;
        end case;
     end if;

     q1rnk3  <= q1rnk3_var after DELAY_FFINP;
     q2rnk3  <= q2rnk3_var after DELAY_FFINP;
     q3rnk3  <= q3rnk3_var after DELAY_FFINP;
     q4rnk3  <= q4rnk3_var after DELAY_FFINP;
     q5rnk3  <= q5rnk3_var after DELAY_FFINP;
     q6rnk3  <= q6rnk3_var after DELAY_FFINP;

  end process prcs_Q1Q2Q3Q4Q5Q6_rnk3;

---////////////////////////////////////////////////////////////////////
---                       Outputs
---////////////////////////////////////////////////////////////////////
  prcs_Q1Q2_rnk3_mux:process(q1rnk1, q1prnk1, q1rnk2, q1rnk3,  
                           q2nrnk1, q2prnk1, q2rnk2, q2rnk3)
  begin
     case selrnk3 is
        when "0000" | "0100" | "0X00" =>
                 Q1_zd <= q1prnk1 after DELAY_MXINP1;
                 Q2_zd <= q2prnk1 after DELAY_MXINP1;
        when "0001" | "0101" | "0X01" =>
                 Q1_zd <= q1rnk1  after DELAY_MXINP1;
                 Q2_zd <= q2prnk1 after DELAY_MXINP1;
        when "0010" | "0110" | "0X10" =>
                 Q1_zd <= q1rnk1  after DELAY_MXINP1;
                 Q2_zd <= q2nrnk1 after DELAY_MXINP1;
        when "1000" | "1001" | "1010" | "1011" | "10X0" | "10X1" |
             "100X" | "101X" | "10XX" =>
                 Q1_zd <= q1rnk2 after DELAY_MXINP1;
                 Q2_zd <= q2rnk2 after DELAY_MXINP1;
        when "1100" | "1101" | "1110" | "1111" | "11X0" | "11X1" |
             "110X" | "111X" | "11XX" =>
                 Q1_zd <= q1rnk3 after DELAY_MXINP1;
                 Q2_zd <= q2rnk3 after DELAY_MXINP1;
        when others =>
                 Q1_zd <= q1rnk2 after DELAY_MXINP1;
                 Q2_zd <= q2rnk2 after DELAY_MXINP1;
     end case;
  end process prcs_Q1Q2_rnk3_mux;
--------------------------------------------------------------------
  prcs_Q3Q4Q5Q6_rnk3_mux:process(q3rnk2, q3rnk3, q4rnk2, q4rnk3,  
                                 q5rnk2, q5rnk3, q6rnk2, q6rnk3)
  begin
     case AttrBitslipEnable is
        when '0'  =>
                 Q3_zd <= q3rnk2 after DELAY_MXINP1;
                 Q4_zd <= q4rnk2 after DELAY_MXINP1;
                 Q5_zd <= q5rnk2 after DELAY_MXINP1;
                 Q6_zd <= q6rnk2 after DELAY_MXINP1;
        when '1'  =>
                 Q3_zd <= q3rnk3 after DELAY_MXINP1;
                 Q4_zd <= q4rnk3 after DELAY_MXINP1;
                 Q5_zd <= q5rnk3 after DELAY_MXINP1;
                 Q6_zd <= q6rnk3 after DELAY_MXINP1;
        when others =>
                 Q3_zd <= q3rnk2 after DELAY_MXINP1;
                 Q4_zd <= q4rnk2 after DELAY_MXINP1;
                 Q5_zd <= q5rnk2 after DELAY_MXINP1;
                 Q6_zd <= q6rnk2 after DELAY_MXINP1;
     end case;
  end process prcs_Q3Q4Q5Q6_rnk3_mux;
----------------------------------------------------------------------
-----------    Inverted CLK  -----------------------------------------
----------------------------------------------------------------------

  CLKN_dly <= not CLK_dly;

----------------------------------------------------------------------
-----------    Instant BSCNTRL_NODELAY  ------------------------------
----------------------------------------------------------------------
  INST_BSCNTRL_NODELAY : BSCNTRL_NODELAY
  generic map (
      SRTYPE => SRTYPE,
      INIT_BITSLIPCNT => INIT_BITSLIPCNT
     )
  port map (
      CLKDIV_INT => clkdiv_int,
      MUXC       => muxc,

      BITSLIP    => BITSLIP_dly,
      C23        => c23,
      C45        => c45,
      C67        => c67,
      CLK        => CLKN_dly,
      CLKDIV     => CLKDIV_dly,
      DATA_RATE  => AttrDataRate,
      GSR        => GSR_dly,
      R          => SR_dly,
      SEL        => sel
      );

--###################################################################
--#####     Set value of the counter in BSCNTRL_NODELAY         ##### 
--###################################################################
  prcs_bscntrl_nodelay_cntr:process
  begin
     wait for 10 ps;
     case cntr is
        when "00100" =>
                 c23<='0'; c45<='0'; c67<='0'; sel<="00";
        when "00110" =>
                 c23<='1'; c45<='0'; c67<='0'; sel<="00";
        when "01000" =>
                 c23<='0'; c45<='0'; c67<='0'; sel<="01";
        when "01010" =>
                 c23<='0'; c45<='1'; c67<='0'; sel<="01";
        when "10010" =>
                 c23<='0'; c45<='0'; c67<='0'; sel<="00";
        when "10011" =>
                 c23<='1'; c45<='0'; c67<='0'; sel<="00";
        when "10100" =>
                 c23<='0'; c45<='0'; c67<='0'; sel<="01";
        when "10101" =>
                 c23<='0'; c45<='1'; c67<='0'; sel<="01";
        when "10110" =>
                 c23<='0'; c45<='0'; c67<='0'; sel<="10";
        when "10111" =>
                 c23<='0'; c45<='0'; c67<='1'; sel<="10";
        when "11000" =>
                 c23<='0'; c45<='0'; c67<='0'; sel<="11";
        when others =>
                assert FALSE 
                report "Error : DATA_WIDTH or DATA_RATE has illegal values."
                severity failure;
     end case;
     wait on cntr, c23, c45, c67, sel;

  end process prcs_bscntrl_nodelay_cntr;
         
----------------------------------------------------------------------
-----------    Instant Clock Enable Circuit  ------------------------- 
----------------------------------------------------------------------
  INST_ICE : ICE_MODULE_NODELAY 
  generic map (
      SRTYPE => SRTYPE,
      INIT_CE => INIT_CE
     )
  port map (
      ICE	=> ice,

      CE1	=> CE1_dly,
      CE2	=> CE2_dly,
      GSR	=> GSR_dly,
      NUM_CE	=> AttrNumCe,
      CLKDIV	=> CLKDIV_dly,
      R		=> SR_dly 
      );
----------------------------------------------------------------------
-----------    Instant IDELAY  --------------------------------------- 
----------------------------------------------------------------------
--  INST_IDELAY : IDELAY 
--  generic map (
--      IOBDELAY_VALUE => IOBDELAY_VALUE,
--      IOBDELAY_TYPE  => IOBDELAY_TYPE
--     )
--  port map (
--      O		=> idelay_out,
--
--      C		=> CLKDIV_dly,
--      CE	=> DLYCE_dly,
--      
--      I		=> D_dly,
--      INC	=> DLYINC_dly,
--      RST	=> DLYRST_dly
--      );
--
--###################################################################
--#####           IOBDELAY -- Delay input Data                  ##### 
--###################################################################
--  prcs_d_delay:process(D_dly, idelay_out)
--  begin
--     case AttrIobDelay is
--        when 0 =>
--               O_zd   <= D_dly;
--               datain <= D_dly;
--        when 1 =>
--               O_zd   <= idelay_out; 
--               datain <= D_dly;
--        when 2 =>
--               O_zd   <= D_dly; 
--               datain <= idelay_out;
--        when 3 =>
--               O_zd   <= idelay_out; 
--               datain <= idelay_out;
--        when others =>
--               null;
--     end case;
--  end process prcs_d_delay;

--####################################################################

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(Q1_zd, Q2_zd, Q3_zd, Q4_zd, Q5_zd, Q6_zd, 
                      SHIFTOUT1_zd, SHIFTOUT2_zd)
  begin
      Q1 <= Q1_zd after SYNC_PATH_DELAY;
      Q2 <= Q2_zd after SYNC_PATH_DELAY;
      Q3 <= Q3_zd after SYNC_PATH_DELAY;
      Q4 <= Q4_zd after SYNC_PATH_DELAY;
      Q5 <= Q5_zd after SYNC_PATH_DELAY;
      Q6 <= Q6_zd after SYNC_PATH_DELAY;
      SHIFTOUT1 <= SHIFTOUT1_zd after SYNC_PATH_DELAY;
      SHIFTOUT2 <= SHIFTOUT2_zd after SYNC_PATH_DELAY;
  end process prcs_output;
--####################################################################


end ISERDES_NODELAY_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2005 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Jtag TAP contorller 
--  /   /         
-- /___/   /\     Filename : JTAG_SIM_VIRTEX5.vhd
-- \   \  /  \    Timestamp : Thu Nov 10 17:26:14 PST 2005
--  \___\/\___\
--
-- Revision:
--    11/10/05 - Initial version.
-- End Revision

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Primitives.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.vpkg.all;
use unisim.Vcomponents.all;



entity JTAG_SIM_VIRTEX5_SUBMOD is

  generic(
      PART_NAME : string;
      IRLength  : integer
      );

  port(
      TDO	: out std_ulogic;

      TCK	: in  std_ulogic;
      TDI	: in  std_ulogic;
      TMS	: in  std_ulogic
    );

end JTAG_SIM_VIRTEX5_SUBMOD;

architecture JTAG_SIM_VIRTEX5_SUBMOD_V OF JTAG_SIM_VIRTEX5_SUBMOD is


  TYPE JtagTapState is (TestLogicReset, RunTestIdle,SelectDRScan, CaptureDR,
                        ShiftDR, Exit1DR, PauseDR, Exit2DR, UPdateDR,
                        SelectIRScan, CaptureIR, ShiftIR, Exit1IR, PauseIR,
                        Exit2IR, UPdateIR);


-------------------------------------------------------------------------------
-----------------  Virtex4 Specific Constants ---------------------------------
-------------------------------------------------------------------------------

  TYPE JtagInstructionType is (UNKNOWN, IR_CAPTURE, BYPASS, IDCODE, USER1, USER2, USER3, USER4);                  

  TYPE PartType            is (LX30, LX50, LX85, LX110, LX220, LX330,
                               LX30T, LX50T, LX85T, LX110T, LX220T, LX330T); 

  constant IRLengthMax          : integer := 14;
  constant IDLength             : integer := 32;
  constant RevBitsLength        : integer := 4;

  constant IR_CAPTURE_VAL	: std_logic_vector ((IRLengthMax -1) downto 0) := "11111111010001";
  constant BYPASS_INSTR         : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111111111";
  constant IDCODE_INSTR         : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111001001";
  constant USER1_INSTR          : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111000010";
  constant USER2_INSTR          : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111000011";
  constant USER3_INSTR          : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111100010";
  constant USER4_INSTR          : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111100011";



--------------------------------------------------------

  constant DELAY_SIG     : time := 1 ps;

  constant Xon : boolean := true;
  constant MsgOn : boolean := true;

  signal ticd_TCK     : VitalDelayType := 0.0 ns;

  signal tisd_TDI_TCK : VitalDelayType := 0.0 ns;
  signal tisd_TMS_TCK : VitalDelayType := 0.0 ns;

  signal tsetup_TMS_TCK_posedge_posedge : VitalDelayType := 1.0 ns;
  signal tsetup_TMS_TCK_negedge_posedge : VitalDelayType := 1.0 ns;

  signal tsetup_TDI_TCK_posedge_posedge : VitalDelayType := 1.0 ns;
  signal tsetup_TDI_TCK_negedge_posedge : VitalDelayType := 1.0 ns;

  signal thold_TMS_TCK_posedge_posedge : VitalDelayType := 2.0 ns;
  signal thold_TMS_TCK_negedge_posedge : VitalDelayType := 2.0 ns;

  signal thold_TDI_TCK_posedge_posedge : VitalDelayType := 2.0 ns;
  signal thold_TDI_TCK_negedge_posedge : VitalDelayType := 2.0 ns;

  signal tpd_TCK_TDO : VitalDelayType01 := (6.0 ns, 6.0 ns);

  signal CurrentState    : JtagTapState := TestLogicReset;
  signal JtagInstruction : JtagInstructionType := IDCODE;

  signal jtag_state_name	: JtagTapState		:= TestLogicReset;
  signal jtag_instruction_name	: JtagInstructionType	:= IDCODE;

  signal TCK_ipd		: std_ulogic := 'X';
  signal TDI_ipd		: std_ulogic := 'X';
  signal TMS_ipd		: std_ulogic := 'X';
  signal TRST_ipd		: std_ulogic := 'X';


  signal TCK_dly		: std_ulogic := 'X';
  signal TDI_dly		: std_ulogic := 'X';
  signal TMS_dly		: std_ulogic := 'X';
  signal TRST_dly		: std_ulogic := '0';

  signal TDO_zd			: std_ulogic := 'X';
  signal TDO_viol		: std_ulogic := 'X';

-----------     signal declaration    -------------------

  signal CaptureDR_sig          : std_ulogic := '0';
  signal RESET_sig              : std_ulogic := '0';
  signal ShiftDR_sig            : std_ulogic := '0';
  signal UpdateDR_sig           : std_ulogic := '0';

  signal ClkIR_active           : std_ulogic := '0';

  signal ClkIR_sig		: std_ulogic := '0';
  signal ClkID_sig		: std_ulogic := '0';
  signal ShiftIR_sig		: std_ulogic := 'X';
  signal UpdateIR_sig		: std_ulogic := 'X';
  signal ClkUpdateIR_sig	: std_ulogic := '0';
  signal IRcontent_sig		: std_logic_vector ((IRLength -1) downto 0) := (others => 'X');
  signal IDCODEval_sig		: std_logic_vector ((IDLength -1) downto 0) := (others => 'X');

  signal BypassReg		: std_ulogic := '0';
  signal BYPASS_sig		: std_ulogic := '0';
  signal IDCODE_sig		: std_ulogic := '0';
  signal USER1_sig		: std_ulogic := '0';
  signal USER2_sig		: std_ulogic := '0';
  signal USER3_sig		: std_ulogic := '0';
  signal USER4_sig		: std_ulogic := '0';

  signal TDO_latch              : std_ulogic := 'Z';

  signal Tlrst_sig              : std_ulogic := '1';
  signal TlrstN_sig             : std_ulogic := '1';

  signal IRegLastBit_sig        : std_ulogic := '0';
  signal IDregLastBit_sig       : std_ulogic := '0';

begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  TCK_dly        	 <= TCK            	after 0 ps;
  TDI_dly        	 <= TDI            	after 0 ps;
  TMS_dly        	 <= TMS            	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process
  variable PartName_var        : PartType;
  variable IDCODE_str          : std_ulogic_vector ((IDLength -1) downto 0) := (others => 'X');
  begin
	if((PART_NAME   = "LX30") or (PART_NAME = "lx30")) then
	      PartName_var := LX30;
	      IDCODE_str   := X"0286E093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "LX50") or (PART_NAME = "lx50")) then
	      PartName_var := LX50;
	      IDCODE_str   := X"02896093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "LX85") or (PART_NAME = "lx85")) then
	      PartName_var := LX85;
	      IDCODE_str   := X"028AE093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "LX110") or (PART_NAME = "lx110")) then
	      PartName_var := LX110;
	      IDCODE_str   := X"028D6093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "LX220") or (PART_NAME = "lx220")) then
	      PartName_var := LX220;
	      IDCODE_str   := X"0290C093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "LX330") or (PART_NAME = "lx330")) then
	      PartName_var := LX330;
	      IDCODE_str   := X"0295C093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "LX30T") or (PART_NAME = "lx30t")) then
	      PartName_var := LX30T;
	      IDCODE_str   := X"02A6E093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "LX50T") or (PART_NAME = "lx50t")) then
	      PartName_var := LX50T;
	      IDCODE_str   := X"02A96093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "LX85T") or (PART_NAME = "lx85t")) then
	      PartName_var := LX85T;
	      IDCODE_str   := X"02AAE093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "LX110T") or (PART_NAME = "lx110t")) then
	      PartName_var := LX110T;
	      IDCODE_str   := X"02AD6093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "LX220T") or (PART_NAME = "lx220t")) then
	      PartName_var := LX220T;
	      IDCODE_str   := X"02B0C093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
	elsif((PART_NAME   = "LX330T") or (PART_NAME = "lx330t")) then
	      PartName_var := LX330T;
	      IDCODE_str   := X"02B5C093";
	      IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
        else
           assert false
           report "Attribute Syntax Error: The allowed values for PART_NAME are LX30, LX50, LX85, LX110, LX220, LX330, LX30T, LX50T, LX85T, LX110T, LX220T or LX330T"
           severity Failure;
        end if;

        wait;

  end process prcs_init;
--####################################################################
--#####                     JtagTapSM                            #####
--####################################################################
  prcs_JtagTapSM:process(TCK_dly, TRST_dly)
  begin

     if(TRST_dly = '1') then
         CurrentState <= TestLogicReset; 
     elsif(TRST_dly = '0') then
        if(rising_edge(TCK_dly)) then
           case CurrentState is
              -------------------------------
              ----  Reset path ---------------
              -------------------------------
              when TestLogicReset =>
                 if(TMS_dly = '0') then 
                    CurrentState <= RunTestIdle;
                 end if;
              when RunTestIdle => 
                 if(TMS_dly = '1') then 
                    CurrentState <= SelectDRScan;
                 end if;
              -------------------------------
              ------  DR path ---------------
              -------------------------------
              when SelectDRScan => 
                 if(TMS_dly = '0') then 
                    CurrentState <= CaptureDR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= SelectIRScan;
                 end if;
              when CaptureDR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= ShiftDR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= Exit1DR;
                 end if;
              when ShiftDR => 
                 if(TMS_dly = '1') then 
                    CurrentState <= Exit1DR;
                 end if;
              
                 if(IRcontent_sig = BYPASS_INSTR((IRLength -1) downto 0)) then
                    BypassReg <= TDI_dly;
                 end if;

              when Exit1DR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= PauseDR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= UpdateDR;
                 end if;
              when PauseDR => 
                 if(TMS_dly = '1') then 
                    CurrentState <= Exit2DR;
                 end if;
              when Exit2DR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= ShiftDR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= UpdateDR;
                 end if;
              when UpdateDR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= RunTestIdle;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= SelectDRScan;
                 end if;
              -------------------------------
              ------  IR path ---------------
              -------------------------------
              when SelectIRScan => 
                 if(TMS_dly = '0') then 
                    CurrentState <= CaptureIR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= TestLogicReset;
                 end if;
              when CaptureIR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= ShiftIR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= Exit1IR;
                 end if;
              when ShiftIR => 
                 if(TMS_dly = '1') then 
                    CurrentState <= Exit1IR;
                 end if;
              when Exit1IR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= PauseIR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= UpdateIR;
                 end if;
              when PauseIR => 
                 if(TMS_dly = '1') then 
                    CurrentState <= Exit2IR;
                 end if;
              when Exit2IR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= ShiftIR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= UpdateIR;
                 end if;
              when UpdateIR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= RunTestIdle;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= SelectDRScan;
                 end if;
           end case;
        end if;
     end if;
  end process  prcs_JtagTapSM;

--####################################################################
--#####                     CurrentState                         #####
--####################################################################

  prcs_CurrentState:process(TCK_dly, CurrentState, TRST_dly)
  begin

     ClkIR_sig <= '1';

     if(TRST_dly = '1') then
         CaptureDR_sig <= '0';
         ShiftDR_sig   <= '0';
         UpdateDR_sig  <= '0';
         ShiftIR_sig   <= '0';
         UpdateIR_sig  <= '0';
     elsif(TRST_dly = '0') then

         case CurrentState is

            when TestLogicReset =>
                          Tlrst_sig     <= '1' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;

            when CaptureDR =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '1' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;

            when ShiftDR  =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '1' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;
 
            when UpdateDR =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '1' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;

            when CaptureIR  =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;
                          ClkIR_sig     <= TCK_dly;

 
            when ShiftIR  =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '1' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;
                          ClkIR_sig     <= TCK_dly;

            when UpdateIR =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '1' after DELAY_SIG;

            when others   =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;
         end case;
     end if;
 
  end process  prcs_CurrentState;

------------- ?? TCK  NEGATIVE EDGE activities ----------

  prcs_ClkIR:process(TCK_dly)
  begin
--     ClkIR_sig <= ShiftIR_sig and TCK_dly;
     CLkUpdateIR_sig <= UpdateIR_sig and not TCK_dly;
  end process  prcs_ClkIR;

  prcs_ClkID:process(TCK_dly)
  begin
     ClkID_sig <= IDCODE_sig and TCK_dly;
  end process  prcs_ClkID;

  prcs_glblsigs:process(TCK_dly, UpdateDR_sig)
  begin
    if(falling_edge(TCK_dly)) then
       JTAG_CAPTURE_GLBL <= CaptureDR_sig;
       -- CR 211337 Reset should go high as soon as it gets to State Trlst
       --  JTAG_RESET_GLBL   <= Tlrst_sig;
       JTAG_SHIFT_GLBL   <= ShiftDR_sig;
       JTAG_UPDATE_GLBL  <= UpdateDR_sig;
       TlrstN_sig        <= Tlrst_sig;
    end if;
  
    if(falling_edge(UpdateDR_sig))then
      JTAG_UPDATE_GLBL  <= UpdateDR_sig;
    end if; 

  end process  prcs_glblsigs;

-- CR 211337
  prcs_reset:process(Tlrst_sig)
  begin
      JTAG_RESET_GLBL   <= Tlrst_sig;
  end process  prcs_reset;
--####################################################################
--#####                       JtagIR                             #####
--####################################################################
  prcs_JtagIR:process(ClkIR_sig, ClkUpdateIR_sig, ShiftIR_sig,  TlrstN_sig, TRST_dly)
  variable NextIRreg : std_logic_vector ((IRLength -1) downto 0) := IR_CAPTURE_VAL((IRLength -1) downto 0);
  variable ir_int    : std_logic_vector ((IRLength -1) downto 0) := IR_CAPTURE_VAL((IRLength -1) downto 0);
  begin
     NextIRreg((IRLength -1) downto 0) := (TDI_dly & ir_int((IRLength -1) downto 1)); 

     if((TRST_dly = '1') or (TlrstN_sig = '1'))then
        IRcontent_sig((IRLength -1) downto 0) <= IDCODE_INSTR((IRLength -1) downto 0);  -- IDCODE instruction is loaded into IR reg.
        IRegLastBit_sig <= ir_int(0);
     elsif((TRST_dly = '0') and (TlrstN_sig = '0')) then
        if(rising_edge(ClkIR_sig)) then
           if(ShiftIR_sig = '1') then
              ir_int((IRLength -1) downto 0) := NextIRreg((IRLength -1) downto 0);
              IRegLastBit_sig <= ir_int(0);
           else
               ir_int := IR_CAPTURE_VAL((IRLength -1) downto 0);
               IRegLastBit_sig <= ir_int(0);
           end if;
        end if;
        if(rising_edge(ClkUpdateIR_sig)) then
           if(UpdateIR_sig = '1') then
              IRcontent_sig <= ir_int;
           end if;
        end if;
     end if;
  end process  prcs_JtagIR;
--####################################################################
--#####                       JtagDecodeIR                       #####
--####################################################################
  prcs_JtagDecodeIR:process(IRcontent_sig)
  begin
     if(IRcontent_sig((IRLength -1) downto 0) = IR_CAPTURE_VAL((IRLength-1) downto 0)) then
        JTagInstruction <= IR_CAPTURE;

     elsif(IRcontent_sig((IRLength -1) downto 0) = BYPASS_INSTR((IRLength-1) downto 0)) then
        JTagInstruction <= BYPASS;
        BYPASS_sig <= '1';
        IDCODE_sig <= '0';
        USER1_sig  <= '0';
        USER2_sig  <= '0';
        USER3_sig  <= '0';
        USER4_sig  <= '0';

     elsif(IRcontent_sig((IRLength -1) downto 0) = IDCODE_INSTR((IRLength-1) downto 0)) then
        JTagInstruction <= IDCODE;
        BYPASS_sig <= '0';
        IDCODE_sig <= '1';
        USER1_sig  <= '0';
        USER2_sig  <= '0';
        USER3_sig  <= '0';
        USER4_sig  <= '0';

     elsif(IRcontent_sig((IRLength -1) downto 0) = USER1_INSTR((IRLength-1) downto 0)) then
        JTagInstruction <= USER1;
        BYPASS_sig <= '0';
        IDCODE_sig <= '0';
        USER1_sig  <= '1';
        USER2_sig  <= '0';
        USER3_sig  <= '0';
        USER4_sig  <= '0';

     elsif(IRcontent_sig((IRLength -1) downto 0) = USER2_INSTR((IRLength-1) downto 0)) then
        JTagInstruction <= USER2;
        BYPASS_sig <= '0';
        IDCODE_sig <= '0';
        USER1_sig  <= '0';
        USER2_sig  <= '1';
        USER3_sig  <= '0';
        USER4_sig  <= '0';

     elsif(IRcontent_sig((IRLength -1) downto 0) = USER3_INSTR((IRLength-1) downto 0)) then
        JTagInstruction <= USER3;
        BYPASS_sig <= '0';
        IDCODE_sig <= '0';
        USER1_sig  <= '0';
        USER2_sig  <= '0';
        USER3_sig  <= '1';
        USER4_sig  <= '0';

     elsif(IRcontent_sig((IRLength -1) downto 0) = USER4_INSTR((IRLength-1) downto 0)) then
        JTagInstruction <= USER4;
        BYPASS_sig <= '0';
        IDCODE_sig <= '0';
        USER1_sig  <= '0';
        USER2_sig  <= '0';
        USER3_sig  <= '0';
        USER4_sig  <= '1';

    else
        JTagInstruction <= UNKNOWN;
        NULL; 
     end if;
  end process prcs_JtagDecodeIR;
--####################################################################
--#####                       JtagIDCODE                         #####
--####################################################################
  prcs_JtagIDCODE:process(ClkID_sig)
  variable IDreg : bit_vector ((IDLength -1) downto 0);
  begin
     if(rising_edge(ClkID_sig)) then
        if(ShiftDR_sig = '1') then
          IDreg := IDreg sra 1;
          IDreg(IDLength -1) := TO_BIT(TDI_dly);
        else
          IDreg := TO_BITVECTOR(IDCODEval_sig);
        end if;
     end if;

     IDregLastBit_sig <= TO_STDULOGIC(IDreg(0));

  end process  prcs_JtagIDCODE;
--####################################################################
--####################################################################
--#####                    JtagSetGlobalSignals                  #####
--####################################################################
  prcs_JtagSetGlobalSignals:process(ClkUpdateIR_sig, Tlrst_sig, USER1_sig, USER2_sig, USER3_sig, USER4_sig)
  begin
     if(rising_edge(USER1_sig)) then
         JTAG_SEL1_GLBL     <= '1';
         JTAG_SEL2_GLBL     <= '0';
         JTAG_SEL3_GLBL     <= '0';
         JTAG_SEL4_GLBL     <= '0';
     elsif(rising_edge(USER2_sig)) then
         JTAG_SEL1_GLBL     <= '0';
         JTAG_SEL2_GLBL     <= '1';
         JTAG_SEL3_GLBL     <= '0';
         JTAG_SEL4_GLBL     <= '0';
     elsif(rising_edge(USER3_sig)) then
         JTAG_SEL1_GLBL     <= '0';
         JTAG_SEL2_GLBL     <= '0';
         JTAG_SEL3_GLBL     <= '1';
         JTAG_SEL4_GLBL     <= '0';
     elsif(rising_edge(USER4_sig)) then
         JTAG_SEL1_GLBL     <= '0';
         JTAG_SEL2_GLBL     <= '0';
         JTAG_SEL3_GLBL     <= '0';
         JTAG_SEL4_GLBL     <= '1';
     elsif(rising_edge(ClkUpdateIR_sig)) then
         JTAG_SEL1_GLBL     <= '0';
         JTAG_SEL2_GLBL     <= '0';
         JTAG_SEL3_GLBL     <= '0';
         JTAG_SEL4_GLBL     <= '0';
     elsif(rising_edge(Tlrst_sig)) then
         JTAG_SEL1_GLBL     <= '0';
         JTAG_SEL2_GLBL     <= '0';
         JTAG_SEL3_GLBL     <= '0';
         JTAG_SEL4_GLBL     <= '0';
     end if;

  end process prcs_JtagSetGlobalSignals;
      
--####################################################################

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################

  jtag_state_name       <= CurrentState;
  jtag_instruction_name <= JtagInstruction;

  JTAG_TCK_GLBL  <= TCK_dly;
  JTAG_TDI_GLBL  <= TDI_dly;
  JTAG_TMS_GLBL  <= TMS_dly;
  JTAG_TRST_GLBL <= TRST_dly;

  TDO_latch <= BypassReg
         when ((CurrentState = ShiftDR) and (IRcontent_sig=BYPASS_INSTR((IRLength -1) downto 0)))
       else IRegLastBit_sig
         when (CurrentState = ShiftIR)
       else IDregLastBit_sig
         when ((CurrentState = ShiftDR) and (IRcontent_sig=IDCODE_INSTR((IRLength -1) downto 0)))
       else JTAG_USER_TDO1_GLBL
         when ((CurrentState = ShiftDR) and (IRcontent_sig=USER1_INSTR((IRLength -1) downto 0)))
       else JTAG_USER_TDO2_GLBL
         when ((CurrentState = ShiftDR) and (IRcontent_sig=USER2_INSTR((IRLength -1) downto 0)))
       else JTAG_USER_TDO3_GLBL
         when ((CurrentState = ShiftDR) and (IRcontent_sig=USER3_INSTR((IRLength -1) downto 0)))
       else JTAG_USER_TDO4_GLBL
         when ((CurrentState = ShiftDR) and (IRcontent_sig=USER4_INSTR((IRLength -1) downto 0)))
       else 'Z';
 
-- CR 212040 -- added timing        
--  prcs_TDO:process(TCK_dly)
--  begin
--    if(falling_edge(TCK_dly)) then
--       TDO <= TDO_latch;
--    end if;
--  end process  prcs_TDO;

--####################################################################
--#####                         Timing                           #####
--####################################################################
  VITALBehavior                    : process (TCK_dly, TDI_dly, TMS_dly)

    variable PInfo_TCK           : VitalPeriodDataType := VitalPeriodDataInit;
    variable Pviol_TCK           : std_ulogic          := '0';

    variable Tmkr_TDI_TCK_posedge  : VitalTimingDataType := VitalTimingDataInit;   
    variable Tviol_TDI_TCK_posedge : std_ulogic          := '0';

    variable Tmkr_TMS_TCK_posedge  : VitalTimingDataType := VitalTimingDataInit;   
    variable Tviol_TMS_TCK_posedge : std_ulogic          := '0';

    variable Violation : std_ulogic := '0';

    variable TDO_GlitchData : VitalGlitchDataType;


  begin
      VitalSetupHoldCheck (
        Violation            => Tviol_TDI_TCK_posedge,
        TimingData           => Tmkr_TDI_TCK_posedge,
        TestSignal           => TDI_dly,
        TestSignalName       => "TDI",
        TestDelay            => tisd_TDI_TCK,
        RefSignal            => TCK_dly,
        RefSignalName        => "TCK",
        RefDelay             => ticd_TCK,
        SetupHigh            => tsetup_TDI_TCK_posedge_posedge,
        SetupLow             => tsetup_TDI_TCK_negedge_posedge,
        HoldLow              => thold_TDI_TCK_posedge_posedge,
        HoldHigh             => thold_TDI_TCK_negedge_posedge,
        CheckEnabled         => TO_X01(TRST_dly) = '0',
        RefTransition        => 'R',
        HeaderMsg            => "/X_JTAG_SIM_VIRTEX5",
        Xon                  => Xon,
        MsgOn                => MsgOn,
        MsgSeverity          => warning);

      VitalSetupHoldCheck (
        Violation            => Tviol_TMS_TCK_posedge,
        TimingData           => Tmkr_TMS_TCK_posedge,
        TestSignal           => TMS_dly,
        TestSignalName       => "TMS",
        TestDelay            => tisd_TMS_TCK,
        RefSignal            => TCK_dly,
        RefSignalName        => "TCK",
        RefDelay             => ticd_TCK,
        SetupHigh            => tsetup_TMS_TCK_posedge_posedge,
        SetupLow             => tsetup_TMS_TCK_negedge_posedge,
        HoldLow              => thold_TMS_TCK_posedge_posedge,
        HoldHigh             => thold_TMS_TCK_negedge_posedge,
        CheckEnabled         => TO_X01(TRST_dly) = '0',
        RefTransition        => 'R',
        HeaderMsg            => "/X_JTAG_SIM_VIRTEX5",
        Xon                  => Xon,
        MsgOn                => MsgOn,
        MsgSeverity          => warning);

    VitalPathDelay01 (
      OutSignal              => TDO,
      GlitchData             => TDO_GlitchData,
      OutSignalName          => "TDO",
      OutTemp                => TDO_latch,
      Paths                  => (0 => (TCK_dly'last_event, tpd_TCK_TDO, TRST_dly = '0')),
      Mode                   => VitalTransport,
      Xon                    => Xon,
      MsgOn                  => MsgOn,
      MsgSeverity            => warning);
  end process;



--####################################################################
--####################################################################


end JTAG_SIM_VIRTEX5_SUBMOD_V;


----- CELL JTAG_SIM_VIRTEX5  -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.vpkg.all;
use unisim.Vcomponents.all;

entity JTAG_SIM_VIRTEX5 is

  generic(
      PART_NAME : string := "LX50"
      );

  port(
      TDO	: out std_ulogic;

      TCK	: in  std_ulogic;
      TDI	: in  std_ulogic;
      TMS	: in  std_ulogic
    );

end JTAG_SIM_VIRTEX5;

architecture JTAG_SIM_VIRTEX5_V OF JTAG_SIM_VIRTEX5 is

  component JTAG_SIM_VIRTEX5_SUBMOD
     generic(
         PART_NAME : string;
         IRLength  : integer
         );

     port(
         TDO       : out std_ulogic;

         TCK       : in  std_ulogic;
         TDI       : in  std_ulogic;
         TMS       : in  std_ulogic
       );
  end component;

  signal TCK_ipd		: std_ulogic := 'X';
  signal TDI_ipd		: std_ulogic := 'X';
  signal TMS_ipd		: std_ulogic := 'X';
  signal TRST_ipd		: std_ulogic := 'X';


  signal TCK_dly		: std_ulogic := 'X';
  signal TDI_dly		: std_ulogic := 'X';
  signal TMS_dly		: std_ulogic := 'X';
  signal TRST_dly		: std_ulogic := '0';

  signal TDO_zd			: std_ulogic := 'X';
  signal TDO_viol		: std_ulogic := 'X';

  signal TDO1_zd                : std_ulogic := 'X';
  signal TDO2_zd                : std_ulogic := 'X';

  signal IRLen10, IRLen14       : boolean := false;




begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  TCK_dly        	 <= TCK            	after 0 ps;
  TDI_dly        	 <= TDI            	after 0 ps;
  TMS_dly        	 <= TMS            	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------


--####################################################################
--#####                   Initialization                         #####
--####################################################################
  prcs_init:process
  begin
      if((PART_NAME   = "LX30") or (PART_NAME = "lx30") or
         (PART_NAME   = "LX50") or (PART_NAME = "lx50") or
         (PART_NAME   = "LX85") or (PART_NAME = "lx85") or
         (PART_NAME   = "LX110") or (PART_NAME = "lx110") or
         (PART_NAME   = "LX220") or (PART_NAME = "lx220") or
         (PART_NAME   = "LX330") or (PART_NAME = "lx330") or
         (PART_NAME   = "LX30T") or (PART_NAME = "lx30t") or
         (PART_NAME   = "LX50T") or (PART_NAME = "lx50t") or
         (PART_NAME   = "LX85T") or (PART_NAME = "lx85t") or
         (PART_NAME   = "LX110T") or (PART_NAME = "lx110t") or
         (PART_NAME   = "LX220T") or (PART_NAME = "lx220t") or
         (PART_NAME   = "LX330T") or (PART_NAME = "lx330t")) then
          IRLen10 <= true;
      elsif((PART_NAME   = "FX40") or (PART_NAME = "fx40") or
         (PART_NAME   = "FX60") or (PART_NAME = "fx60") or
         (PART_NAME   = "FX100") or (PART_NAME = "fx100") or
         (PART_NAME   = "FX140") or (PART_NAME = "fx140") or
         (PART_NAME   = "FX200") or (PART_NAME = "fx200")) then
          IRLen14 <= true;
      end if;

      wait;

  end process prcs_init;

--####################################################################
--#####                       Generate                           #####
--####################################################################
  G1: if((PART_NAME   = "LX30") or (PART_NAME = "lx30") or
         (PART_NAME   = "LX50") or (PART_NAME = "lx50") or
         (PART_NAME   = "LX85") or (PART_NAME = "lx85") or
         (PART_NAME   = "LX110") or (PART_NAME = "lx110") or
         (PART_NAME   = "LX220") or (PART_NAME = "lx220") or
         (PART_NAME   = "LX330") or (PART_NAME = "lx330") or
         (PART_NAME   = "LX30T") or (PART_NAME = "lx30t") or
         (PART_NAME   = "LX50T") or (PART_NAME = "lx50t") or
         (PART_NAME   = "LX85T") or (PART_NAME = "lx85t") or
         (PART_NAME   = "LX110T") or (PART_NAME = "lx110t") or
         (PART_NAME   = "LX220T") or (PART_NAME = "lx220t") or
         (PART_NAME   = "LX330T") or (PART_NAME = "lx330t")) generate
          
        JTAG_INST : JTAG_SIM_VIRTEX5_SUBMOD
          generic map (
            PART_NAME => PART_NAME,
            IRLength  => 10
          )
          port map (
            TDO => TDO1_zd,
            TCK => TCK_dly,
            TDI => TDI_dly,
            TMS => TMS_dly
          );

  end generate;   

  G2: if((PART_NAME   = "FX40") or (PART_NAME = "fx40") or
         (PART_NAME   = "FX60") or (PART_NAME = "fx60") or
         (PART_NAME   = "FX100") or (PART_NAME = "fx100") or
         (PART_NAME   = "FX140") or (PART_NAME = "fx140") or
         (PART_NAME   = "FX200") or (PART_NAME = "fx200")) generate

        JTAG_INST : JTAG_SIM_VIRTEX5_SUBMOD
          generic map (
            PART_NAME => PART_NAME,
            IRLength  => 14
          )
          port map (
            TDO => TDO2_zd,
            TCK => TCK_dly,
            TDI => TDI_dly,
            TMS => TMS_dly
          );

  end generate;   


         
--####################################################################

  TDO <= TDO1_zd when IRLen10 else
         TDO2_zd when IRLen14;


end JTAG_SIM_VIRTEX5_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  
-- /___/   /\     Filename : KEY_CLEAR.vhd
-- \   \  /  \    Timestamp : Wed Aug 17 17:14:41 PDT 2005
--  \___\/\___\
--
-- Revision:
--    08/17/05 - Initial version.
-- End Revision:

----- CELL KEY_CLEAR -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity KEY_CLEAR is
  port(
      KEYCLEARB            : in std_ulogic
    );

end KEY_CLEAR;

architecture KEY_CLEAR_V of KEY_CLEAR is

begin
end KEY_CLEAR_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/lut5_d.vhd,v 1.2 2006/03/11 00:55:40 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input Look-Up-Table with Dual Output
-- /___/   /\     Filename : lut5_d.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:02 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    03/15/05 - Modified to handle the address unknown case.
--    03/10/06 - Change d to df in function lut4_mux4f and replace TO_INTEGER to
--               SLV_TO_INT. (CR 226842)
-- End Revision

----- CELL LUT5_D -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity LUT5_D is
  generic(
    INIT : bit_vector := X"00000000"
    );

  port(
    LO : out std_ulogic;
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end LUT5_D;

architecture LUT5_D_V of LUT5_D is

function lut6_mux8 (d :  std_logic_vector(7 downto 0); s : std_logic_vector(2 downto 0)) 
                    return std_logic is

       variable lut6_mux8_o : std_logic;
       function lut4_mux4f (df :  std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) )
                    return std_logic is

            variable lut4_mux4_f : std_logic;
       begin

            if (((sf(1) xor sf(0)) = '1')  or  ((sf(1) xor sf(0)) = '0')) then
                lut4_mux4_f := df(SLV_TO_INT(sf));
            elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0'
                    and (df(0) xor df(2)) = '0') then
                lut4_mux4_f := df(0);
            elsif ((sf(1) = '0') and (df(0) = df(1))) then
                lut4_mux4_f := df(0);
            elsif ((sf(1) = '1') and (df(2) = df(3))) then
                lut4_mux4_f := df(2);
            elsif ((sf(0) = '0') and (df(0) = df(2))) then
                lut4_mux4_f := df(0);
            elsif ((sf(0) = '1') and (df(1) = df(3))) then
                lut4_mux4_f := df(1);
            else
                lut4_mux4_f := 'X';
           end if;

           return (lut4_mux4_f);
    
       end function lut4_mux4f;
  begin
       
    if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then
       lut6_mux8_o := d(SLV_TO_INT(s));
    else
       lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) &
            lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2)));
    end if;

      return (lut6_mux8_o);
     
  end function lut6_mux8;

function lut4_mux4 (d :  std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) )
                    return std_logic is

       variable lut4_mux4_o : std_logic;
  begin
       
       if (((s(1) xor s(0)) = '1')  or  ((s(1) xor s(0)) = '0')) then
           lut4_mux4_o := d(SLV_TO_INT(s));
       elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0'
                    and (d(0) xor d(2)) = '0') then
           lut4_mux4_o := d(0);
       elsif ((s(1) = '0') and (d(0) = d(1))) then
           lut4_mux4_o := d(0);
       elsif ((s(1) = '1') and (d(2) = d(3))) then
           lut4_mux4_o := d(2);
       elsif ((s(0) = '0') and (d(0) = d(2))) then
           lut4_mux4_o := d(0);
       elsif ((s(0) = '1') and (d(1) = d(3))) then
           lut4_mux4_o := d(1);
       else
           lut4_mux4_o := 'X';
      end if;

      return (lut4_mux4_o);
     
  end function lut4_mux4;

 constant INIT_reg : std_logic_vector(31 downto 0) := To_StdLogicVector(INIT);    

begin
    

  lut_p   : process (I0, I1, I2, I3, I4)
    variable I_reg : std_logic_vector(4 downto 0);
   variable O_out : std_ulogic;
  begin

    I_reg := TO_STDLOGICVECTOR(I4 & I3 &  I2 & I1 & I0);

    if ((I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I4 xor I3 xor I2 xor I1 xor I0) = '0') then
       O_out := INIT_reg(SLV_TO_INT(I_reg));
    else 

       O_out :=  lut4_mux4 ( 
           (lut6_mux8 ( INIT_reg(31 downto 24), I_reg(2 downto 0)) &
            lut6_mux8 ( INIT_reg(23 downto 16), I_reg(2 downto 0)) &
            lut6_mux8 ( INIT_reg(15 downto 8), I_reg(2 downto 0)) &
            lut6_mux8 ( INIT_reg(7 downto 0), I_reg(2 downto 0))),
                        I_reg(4 downto 3));
 
    end if;
    LO <= O_out;
    O <= O_out;
  end process;
end LUT5_D_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/lut5_l.vhd,v 1.2 2006/03/11 00:55:40 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input Look-Up-Table with General Output
-- /___/   /\     Filename : lut5_l.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:02 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    03/15/05 - Modified to handle the address unknown case.
--    03/10/06 - Change d to df in function lut4_mux4f and replace TO_INTEGER to
--               SLV_TO_INT. (CR 226842)
-- End Revision

----- CELL LUT5_L -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity LUT5_L is
  generic(
    INIT : bit_vector := X"00000000"
    );

  port(
    LO : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end LUT5_L;

architecture LUT5_L_V of LUT5_L is

function lut6_mux8 (d :  std_logic_vector(7 downto 0); s : std_logic_vector(2 downto 0)) 
                    return std_logic is

       variable lut6_mux8_o : std_logic;
       function lut4_mux4f (df :  std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) )
                    return std_logic is

            variable lut4_mux4_f : std_logic;
       begin

            if (((sf(1) xor sf(0)) = '1')  or  ((sf(1) xor sf(0)) = '0')) then
                lut4_mux4_f := df(SLV_TO_INT(sf));          
            elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0'
                    and (df(0) xor df(2)) = '0') then
                lut4_mux4_f := df(0);
            elsif ((sf(1) = '0') and (df(0) = df(1))) then
                lut4_mux4_f := df(0);
            elsif ((sf(1) = '1') and (df(2) = df(3))) then
                lut4_mux4_f := df(2);
            elsif ((sf(0) = '0') and (df(0) = df(2))) then
                lut4_mux4_f := df(0);
            elsif ((sf(0) = '1') and (df(1) = df(3))) then
                lut4_mux4_f := df(1);
            else
                lut4_mux4_f := 'X';
           end if;

           return (lut4_mux4_f);
    
       end function lut4_mux4f;
  begin
       
    if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then
       lut6_mux8_o := d(SLV_TO_INT(s));
    else
       lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) &
            lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2)));
    end if;

      return (lut6_mux8_o);
     
  end function lut6_mux8;

function lut4_mux4 (d :  std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) )
                    return std_logic is

       variable lut4_mux4_o : std_logic;
  begin
       
       if (((s(1) xor s(0)) = '1')  or  ((s(1) xor s(0)) = '0')) then
           lut4_mux4_o := d(SLV_TO_INT(s));
       elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0'
                    and (d(0) xor d(2)) = '0') then
           lut4_mux4_o := d(0);
       elsif ((s(1) = '0') and (d(0) = d(1))) then
           lut4_mux4_o := d(0);
       elsif ((s(1) = '1') and (d(2) = d(3))) then
           lut4_mux4_o := d(2);
       elsif ((s(0) = '0') and (d(0) = d(2))) then
           lut4_mux4_o := d(0);
       elsif ((s(0) = '1') and (d(1) = d(3))) then
           lut4_mux4_o := d(1);
       else
           lut4_mux4_o := 'X';
      end if;

      return (lut4_mux4_o);
     
  end function lut4_mux4;

    constant INIT_reg : std_logic_vector(31 downto 0) := To_StdLogicVector(INIT);    
begin

  lut_p   : process (I0, I1, I2, I3, I4)
    variable INIT_reg : std_logic_vector(31 downto 0) := To_StdLogicVector(INIT);    
    variable I_reg : std_logic_vector(4 downto 0);
  begin

    I_reg := TO_STDLOGICVECTOR(I4 & I3 &  I2 & I1 & I0);

    if ((I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I4 xor I3 xor I2 xor I1 xor I0) = '0') then
       LO <= INIT_reg(SLV_TO_INT(I_reg));
    else 

       LO <=  lut4_mux4 ( 
           (lut6_mux8 ( INIT_reg(31 downto 24), I_reg(2 downto 0)) &
            lut6_mux8 ( INIT_reg(23 downto 16), I_reg(2 downto 0)) &
            lut6_mux8 ( INIT_reg(15 downto 8), I_reg(2 downto 0)) &
            lut6_mux8 ( INIT_reg(7 downto 0), I_reg(2 downto 0))),
                        I_reg(4 downto 3));
 
    end if;
  end process;
end LUT5_L_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/lut5.vhd,v 1.3 2006/03/11 00:55:40 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  5-input Look-Up-Table with General Output
-- /___/   /\     Filename : LUT5.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:02 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    03/15/05 - Modified to handle the address unknown case.
--    03/10/06 - Change d to df in function lut4_mux4f and replace TO_INTEGER to
--               SLV_TO_INT. (CR 226842)
-- End Revision

----- CELL LUT5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity LUT5 is
  generic(
    INIT : bit_vector := X"00000000"
    );

  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic
    );
end LUT5;

architecture LUT5_V of LUT5 is

function lut6_mux8 (d :  std_logic_vector(7 downto 0); s : std_logic_vector(2 downto 0)) 
                    return std_logic is

       variable lut6_mux8_o : std_logic;
       function lut4_mux4f (df :  std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) )
                    return std_logic is

            variable lut4_mux4_f : std_logic;
       begin

            if (((sf(1) xor sf(0)) = '1')  or  ((sf(1) xor sf(0)) = '0')) then
                lut4_mux4_f := df(SLV_TO_INT(sf));
            elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0'
                    and (df(0) xor df(2)) = '0') then
                lut4_mux4_f := df(0);
            elsif ((sf(1) = '0') and (df(0) = df(1))) then
                lut4_mux4_f := df(0);
            elsif ((sf(1) = '1') and (df(2) = df(3))) then
                lut4_mux4_f := df(2);
            elsif ((sf(0) = '0') and (df(0) = df(2))) then
                lut4_mux4_f := df(0);
            elsif ((sf(0) = '1') and (df(1) = df(3))) then
                lut4_mux4_f := df(1);
            else
                lut4_mux4_f := 'X';
           end if;

           return (lut4_mux4_f);
    
       end function lut4_mux4f;
  begin
       
    if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then
       lut6_mux8_o := d(SLV_TO_INT(s));
    else
       lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) &
            lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2)));
    end if;

      return (lut6_mux8_o);
     
  end function lut6_mux8;

function lut4_mux4 (d :  std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) )
                    return std_logic is

       variable lut4_mux4_o : std_logic;
  begin
       
       if (((s(1) xor s(0)) = '1')  or  ((s(1) xor s(0)) = '0')) then
           lut4_mux4_o := d(SLV_TO_INT(s));
       elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0'
                    and (d(0) xor d(2)) = '0') then
           lut4_mux4_o := d(0);
       elsif ((s(1) = '0') and (d(0) = d(1))) then
           lut4_mux4_o := d(0);
       elsif ((s(1) = '1') and (d(2) = d(3))) then
           lut4_mux4_o := d(2);
       elsif ((s(0) = '0') and (d(0) = d(2))) then
           lut4_mux4_o := d(0);
       elsif ((s(0) = '1') and (d(1) = d(3))) then
           lut4_mux4_o := d(1);
       else
           lut4_mux4_o := 'X';
      end if;

      return (lut4_mux4_o);
     
  end function lut4_mux4;

    constant INIT_reg : std_logic_vector(31 downto 0) := To_StdLogicVector(INIT);    
begin

  lut_p   : process (I0, I1, I2, I3, I4)
    variable I_reg : std_logic_vector(4 downto 0);
  begin

    I_reg := TO_STDLOGICVECTOR(I4 & I3 &  I2 & I1 & I0);

    if ((I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I4 xor I3 xor I2 xor I1 xor I0) = '0') then
       O <= INIT_reg(SLV_TO_INT(I_reg));
    else 

       O <=  lut4_mux4 ( 
           (lut6_mux8 ( INIT_reg(31 downto 24), I_reg(2 downto 0)) &
            lut6_mux8 ( INIT_reg(23 downto 16), I_reg(2 downto 0)) &
            lut6_mux8 ( INIT_reg(15 downto 8), I_reg(2 downto 0)) &
            lut6_mux8 ( INIT_reg(7 downto 0), I_reg(2 downto 0))),
                        I_reg(4 downto 3));
 
    end if;
  end process;
end LUT5_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/lut6_2.vhd,v 1.1 2006/08/24 00:12:26 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  6-input Look-Up-Table with Two General Outputs
-- /___/   /\     Filename : LUT6_2.vhd
-- \   \  /  \    Timestamp : 
--  \___\/\___\
--
-- Revision:
--    08/09/06 - Initial version.
-- End Revision

----- CELL LUT6_2 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity LUT6_2 is
  generic(
    INIT : bit_vector := X"0000000000000000"
    );

  port(
    O5 : out std_ulogic;
    O6 : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic;
    I5 : in std_ulogic
    );
end LUT6_2;

architecture LUT6_2_V of LUT6_2 is

function lut6_mux8 (d :  std_logic_vector(7 downto 0); s : std_logic_vector(2 downto 0)) 
                    return std_logic is

       variable lut6_mux8_o : std_logic;
       function lut4_mux4f (df :  std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) )
                    return std_logic is

            variable lut4_mux4_f : std_logic;
       begin

            if (((sf(1) xor sf(0)) = '1')  or  ((sf(1) xor sf(0)) = '0')) then
                lut4_mux4_f := df(SLV_TO_INT(sf));
            elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0'
                    and (df(0) xor df(2)) = '0') then
                lut4_mux4_f := df(0);
            elsif ((sf(1) = '0') and (df(0) = df(1))) then
                lut4_mux4_f := df(0);
            elsif ((sf(1) = '1') and (df(2) = df(3))) then
                lut4_mux4_f := df(2);
            elsif ((sf(0) = '0') and (df(0) = df(2))) then
                lut4_mux4_f := df(0);
            elsif ((sf(0) = '1') and (df(1) = df(3))) then
                lut4_mux4_f := df(1);
            else
                lut4_mux4_f := 'X';
           end if;

           return (lut4_mux4_f);
    
       end function lut4_mux4f;
  begin
       
    if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then
       lut6_mux8_o := d(SLV_TO_INT(s));
    else
       lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) &
            lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2)));
    end if;

      return (lut6_mux8_o);
     
  end function lut6_mux8;

function lut4_mux4 (d :  std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) )
                    return std_logic is

       variable lut4_mux4_o : std_logic;
  begin
       
       if (((s(1) xor s(0)) = '1')  or  ((s(1) xor s(0)) = '0')) then
           lut4_mux4_o := d(SLV_TO_INT(s));
       elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0'
                    and (d(0) xor d(2)) = '0') then
           lut4_mux4_o := d(0);
       elsif ((s(1) = '0') and (d(0) = d(1))) then
           lut4_mux4_o := d(0);
       elsif ((s(1) = '1') and (d(2) = d(3))) then
           lut4_mux4_o := d(2);
       elsif ((s(0) = '0') and (d(0) = d(2))) then
           lut4_mux4_o := d(0);
       elsif ((s(0) = '1') and (d(1) = d(3))) then
           lut4_mux4_o := d(1);
       else
           lut4_mux4_o := 'X';
      end if;

      return (lut4_mux4_o);
     
  end function lut4_mux4;

    constant INIT_reg : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT);    
    constant init_l : std_logic_vector(31 downto 0) := INIT_reg(31 downto 0);    
    constant init_h : std_logic_vector(31 downto 0) := INIT_reg(63 downto 32);    
begin

  lut_p   : process (I0, I1, I2, I3, I4, I5)
    variable I_reg : std_logic_vector(4 downto 0);
    variable o_l : std_ulogic;
    variable o_h : std_ulogic;
  begin

    I_reg := TO_STDLOGICVECTOR(I4 & I3 &  I2 & I1 & I0);

    if ((I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I4 xor I3 xor I2 xor I1 xor I0) = '0') then
       o_l := init_l(SLV_TO_INT(I_reg));
       o_h := init_h(SLV_TO_INT(I_reg));
    else 
       o_l :=  lut4_mux4 ( 
           (lut6_mux8 ( init_l(31 downto 24), I_reg(2 downto 0)) &
            lut6_mux8 ( init_l(23 downto 16), I_reg(2 downto 0)) &
            lut6_mux8 ( init_l(15 downto 8), I_reg(2 downto 0)) &
            lut6_mux8 ( init_l(7 downto 0), I_reg(2 downto 0))),
                        I_reg(4 downto 3));

       o_h :=  lut4_mux4 (
           (lut6_mux8 ( init_h(31 downto 24), I_reg(2 downto 0)) &
            lut6_mux8 ( init_h(23 downto 16), I_reg(2 downto 0)) &
            lut6_mux8 ( init_h(15 downto 8), I_reg(2 downto 0)) &
            lut6_mux8 ( init_h(7 downto 0), I_reg(2 downto 0))),
                        I_reg(4 downto 3));
 
    end if;

    O5 <= o_l;
    if (I5 = '1') then
      O6 <= o_h;
    elsif (I5 = '0') then
      O6 <= o_l;
    else 
      if (o_h = '0' and  o_l = '0') then
         O6 <= '0';
      elsif (o_h = '1' and o_l = '1') then
         O6 <= '1';
      else
         O6 <= 'X';
      end if;
   end if;

  end process;
end LUT6_2_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/lut6_d.vhd,v 1.5 2006/03/23 18:56:36 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  6-input Look-Up-Table with Dural Output
-- /___/   /\     Filename : lut6_d.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:02 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    03/15/05 - Modified to handle the address unknown case.
--    03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842)
-- End Revision

----- CELL LUT6_D -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity LUT6_D is
  generic(
     INIT : bit_vector := X"0000000000000000"
     );

  port(
    LO : out std_ulogic;
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic;
    I5 : in std_ulogic
    );
end LUT6_D;

architecture LUT6_D_V of LUT6_D is

function lut6_mux8 (d :  std_logic_vector(7 downto 0); s : std_logic_vector(2  downto 0) )
                    return std_logic is
       variable lut6_mux8_o : std_logic;
       function lut4_mux4f (df :  std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) )
                    return std_logic is

            variable lut4_mux4_f : std_logic;
       begin

            if (((sf(1) xor sf(0)) = '1')  or  ((sf(1) xor sf(0)) = '0')) then
                lut4_mux4_f := df(SLV_TO_INT(sf));
            elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0'
                    and (df(0) xor df(2)) = '0') then
                lut4_mux4_f := df(0);
            elsif ((sf(1) = '0') and (df(0) = df(1))) then
                lut4_mux4_f := df(0);
            elsif ((sf(1) = '1') and (df(2) = df(3))) then
                lut4_mux4_f := df(2);
            elsif ((sf(0) = '0') and (df(0) = df(2))) then
                lut4_mux4_f := df(0);
            elsif ((sf(0) = '1') and (df(1) = df(3))) then
                lut4_mux4_f := df(1);
            else
                lut4_mux4_f := 'X';
           end if;

           return (lut4_mux4_f);
    
       end function lut4_mux4f;
  begin

   if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then
       lut6_mux8_o := d(SLV_TO_INT(s));
    else
       lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) &
            lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2)));
    end if;

      return (lut6_mux8_o);
     
  end function lut6_mux8;

    constant INIT_reg : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT);    
begin

  lut_p   : process (I0, I1, I2, I3, I4, I5)
    variable I_reg : std_logic_vector(5 downto 0);
    variable O_out : std_ulogic;
  begin
    
    I_reg := TO_STDLOGICVECTOR(I5 & I4 & I3 &  I2 & I1 & I0);

    if ((I5 xor I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I5 xor I4 xor I3 xor I2 xor I1 xor I0) = '0') then
       O_out := INIT_reg(SLV_TO_INT(I_reg));
    else 

       O_out :=  lut6_mux8 ( 
               (lut6_mux8 ( INIT_reg(63 downto 56), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(55 downto 48), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(47 downto 40), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(39 downto 32), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(31 downto 24), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(23 downto 16), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(15 downto 8), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(7 downto 0), I_reg(2 downto 0))),
                        I_reg(5 downto 3));
 
    end if;
    O <= O_out;
    LO <= O_out;
  end process;
end LUT6_D_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/lut6_l.vhd,v 1.5 2006/03/23 18:56:36 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  6-input Look-Up-Table with Local Output
-- /___/   /\     Filename : lut6_l.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:02 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    03/15/05 - Modified to handle the address unknown case.
--    03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842)
-- End Revision

----- CELL LUT6_L -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity LUT6_L is
  generic(
      INIT : bit_vector := X"0000000000000000"
     );

  port(
    LO : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic;
    I5 : in std_ulogic
    );
end LUT6_L;

architecture LUT6_L_V of LUT6_L is

function lut6_mux8 (d :  std_logic_vector(7 downto 0); s : std_logic_vector(2  downto 0) )
                    return std_logic is
       variable lut6_mux8_o : std_logic;
       function lut4_mux4f (df :  std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) )
                    return std_logic is

            variable lut4_mux4_f : std_logic;
       begin

            if (((sf(1) xor sf(0)) = '1')  or  ((sf(1) xor sf(0)) = '0')) then
                lut4_mux4_f := df(SLV_TO_INT(sf));
            elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0'
                    and (df(0) xor df(2)) = '0') then
                lut4_mux4_f := df(0);
            elsif ((sf(1) = '0') and (df(0) = df(1))) then
                lut4_mux4_f := df(0);
            elsif ((sf(1) = '1') and (df(2) = df(3))) then
                lut4_mux4_f := df(2);
            elsif ((sf(0) = '0') and (df(0) = df(2))) then
                lut4_mux4_f := df(0);
            elsif ((sf(0) = '1') and (df(1) = df(3))) then
                lut4_mux4_f := df(1);
            else
                lut4_mux4_f := 'X';
           end if;

           return (lut4_mux4_f);
    
       end function lut4_mux4f;

  begin

   if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then
       lut6_mux8_o := d(SLV_TO_INT(s));
    else
       lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) &
            lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2)));
    end if;

      return (lut6_mux8_o);
     
  end function lut6_mux8;

    constant INIT_reg : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT);    
begin

  lut_p   : process (I0, I1, I2, I3, I4, I5)
    variable I_reg : std_logic_vector(5 downto 0);
  begin
    
    I_reg := TO_STDLOGICVECTOR(I5 & I4 & I3 &  I2 & I1 & I0);

    if ((I5 xor I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I5 xor I4 xor I3 xor I2 xor I1 xor I0) = '0') then
       LO <= INIT_reg(SLV_TO_INT(I_reg));
    else 

       LO <=  lut6_mux8 ( 
               (lut6_mux8 ( INIT_reg(63 downto 56), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(55 downto 48), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(47 downto 40), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(39 downto 32), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(31 downto 24), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(23 downto 16), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(15 downto 8), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(7 downto 0), I_reg(2 downto 0))),
                        I_reg(5 downto 3));
 
    end if;
  end process;
end LUT6_L_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/lut6.vhd,v 1.6 2006/03/23 18:56:36 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  6-input Look-Up-Table with General Output
-- /___/   /\     Filename : LUT6.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:02 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.
--    03/15/05 - Modified to handle the address unknown case.
--    03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842)
-- End Revision

----- CELL LUT6 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity LUT6 is
  generic(
     INIT : bit_vector := X"0000000000000000"
    );

  port(
    O : out std_ulogic;

    I0 : in std_ulogic;
    I1 : in std_ulogic;
    I2 : in std_ulogic;
    I3 : in std_ulogic;
    I4 : in std_ulogic;
    I5 : in std_ulogic
    );
end LUT6;

architecture LUT6_V of LUT6 is

function lut6_mux8 (d :  std_logic_vector(7 downto 0); s : std_logic_vector(2  downto 0) )
                    return std_logic is
       variable lut6_mux8_o : std_logic;
       function lut4_mux4f (df :  std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) )
                    return std_logic is

            variable lut4_mux4_f : std_logic;
       begin

            if (((sf(1) xor sf(0)) = '1')  or  ((sf(1) xor sf(0)) = '0')) then
                lut4_mux4_f := df(SLV_TO_INT(sf));
            elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0'
                    and (df(0) xor df(2)) = '0') then
                lut4_mux4_f := df(0);
            elsif ((sf(1) = '0') and (df(0) = df(1))) then
                lut4_mux4_f := df(0);
            elsif ((sf(1) = '1') and (df(2) = df(3))) then
                lut4_mux4_f := df(2);
            elsif ((sf(0) = '0') and (df(0) = df(2))) then
                lut4_mux4_f := df(0);
            elsif ((sf(0) = '1') and (df(1) = df(3))) then
                lut4_mux4_f := df(1);
            else
                lut4_mux4_f := 'X';
           end if;

           return (lut4_mux4_f);
    
       end function lut4_mux4f;
  begin

   if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then
       lut6_mux8_o := d(SLV_TO_INT(s));
    else
       lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) &
            lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2)));
    end if;

      return (lut6_mux8_o);
     
  end function lut6_mux8;

    constant INIT_reg : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT);    
begin

  lut_p   : process (I0, I1, I2, I3, I4, I5)
    variable I_reg : std_logic_vector(5 downto 0);
  begin
    
    I_reg := TO_STDLOGICVECTOR(I5 & I4 & I3 &  I2 & I1 & I0);

    if ((I5 xor I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I5 xor I4 xor I3 xor I2 xor I1 xor I0) = '0') then
       O <= INIT_reg(SLV_TO_INT(I_reg));
    else 

       O <=  lut6_mux8 ( 
               (lut6_mux8 ( INIT_reg(63 downto 56), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(55 downto 48), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(47 downto 40), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(39 downto 32), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(31 downto 24), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(23 downto 16), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(15 downto 8), I_reg(2 downto 0)) &
                lut6_mux8 ( INIT_reg(7 downto 0), I_reg(2 downto 0))),
                        I_reg(5 downto 3));
 
    end if;
  end process;
end LUT6_V;


-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                 Phase Lock Loop Clock 
-- /___/   /\     Filename : PLL_ADV.vhd
-- \   \  /  \    Timestamp : Fri Mar 26 08:18:19 PST 2004
--  \___\/\___\
-- Revision:
--    07/11/05 - Initial version.
--    10/14/05 - Add REL pin.
--    11/16/05 - Add PMCD related generics.
--    12/02/05 - Change parameter default values.
--    01/03/06 - Change RST_DEASSER_CLK value to CLKIN1 and CLKFB (BT#735).
--    01/13/06 - Add DRP and PMCD logic. (CR 222944)
--    02/17/06 - Add support for -360.0 to +360.0 phase shift. (CR225765)
--    03/17/96 - Reduce lock time by MD (CR 224502).
--    07/19/06 - Remove first 4 clkvco_lk cycle generation (CR234931).
--    08/08/06 - Fix real2int when less than 1 (CR 236219).
--    08/23/06 - Use clkout_en_tmp to generate clkout_en0. (CR422250)
--    09/19/06 - Fix real2int with time method  and md_product update (CR 424286).
--    09/27/06 - Add error check for RESET_ON_LOSS_OF_LOCK (CR 425255)
--             - Check rst when generating clkfb_tst (CR 425185).
--    11/10/06 - Keep 3 digits for real in duty cycle check function. (CR 428703).
--    01/12/07 - Add CLKOUT_DESKEW_ADJUST parameters (CR 432189).
--    04/09/07 - Enhance error message for RESET_ON_LOSS_OF_LOCK (CR 437405).
--    05/22/07 - Add setup check for REL (438781).
--    06/8/07  - Generate clkfb_tst when GSR=0; Add clkx_edgei after DRP write(CR441293).
--             - Chang VCOCLK_FREQ_MAX and VCOCLK_FREQ_MIN to generic for unisim (BT1485).
--    06/20/07 - Add CLKFBIN pulse width check (BT1476).
--    06/28/07 - Initial DRP memory (CR 434042), Error message improve (CR 438250).
--    08/02/07 - Remove numbers from CLKOUT DESKEW_ADJUST check for unisim (CR443161).
--    08/21/07 - Not check CLKIN period when PMCD mode set (445101).
--               Fix DUTY_CYCLE_MAX formula in case of divider larger than O_MAX_HT_LT (CR445945).
--               Add warning if phase shift over pll ability (63 vco) (CR446037).
--    09/20/07 - Seperate fb_delay and delay_edge to handle 0 fb_delay (CR448938)
--    10/23/07 - Add warnings to initial phase shift calculation (CR448965)
--    11/01/07 - Remove zero check for CLKOUTx dly register bit15-8 (CR434042)
--    01/18/08 - Generate vco clk with period_vco/2 as high time and period_vco - high time as 
--               low time (CR458475).
--    03/06/08 - Change max vco freq from 1100Mhz to 1440 Mhz (CR469212).
--    03/11/08 - Not check clkinsel_in change with RST=0 if clkinsel_in change from X  to
--               handle the time 0 X value caused by sdf delay. (CR469589).
--    03/27/08 - Add period_vco_cmp_cnt and period_vco_md_rm to spread acuminated rounded error
--               of period_vco/2 during M*D CLKIN cycles instead of last cycle. (CR470494).
--    06/06/08 - Change default values of CLKIN_FREQ_MAX, CLKIN_FREQ_MIN,
--               CLKPFD_FREQ_MIN and REF_CLK_JITTER_MAX (CR469212).
--    06/23/08 - Assign clkind_ht with clkind_hti when DRP write. 
--               Same for clkind_lt. (CR475182)
--    07/10/08 - Calculate clklt first instead of clkht in clkout_hl_para_drp (CR476560).
-- End Revision

----- CELL PLL_ADV -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library STD;
use STD.TEXTIO.all;


library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity PLL_ADV is
generic (

                BANDWIDTH : string := "OPTIMIZED";
                CLKFBOUT_DESKEW_ADJUST : string := "NONE";
                CLKFBOUT_MULT : integer := 1;
                CLKFBOUT_PHASE : real := 0.0;
                CLKIN1_PERIOD : real := 0.000;
                CLKIN2_PERIOD : real := 0.000;
                CLKOUT0_DESKEW_ADJUST : string := "NONE";
                CLKOUT0_DIVIDE : integer := 1;
                CLKOUT0_DUTY_CYCLE : real := 0.5;
                CLKOUT0_PHASE : real := 0.0;
                CLKOUT1_DESKEW_ADJUST : string := "NONE";
                CLKOUT1_DIVIDE : integer := 1;
                CLKOUT1_DUTY_CYCLE : real := 0.5;
                CLKOUT1_PHASE : real := 0.0;
                CLKOUT2_DESKEW_ADJUST : string := "NONE";
                CLKOUT2_DIVIDE : integer := 1;
                CLKOUT2_DUTY_CYCLE : real := 0.5;
                CLKOUT2_PHASE : real := 0.0;
                CLKOUT3_DESKEW_ADJUST : string := "NONE";
                CLKOUT3_DIVIDE : integer := 1;
                CLKOUT3_DUTY_CYCLE : real := 0.5;
                CLKOUT3_PHASE : real := 0.0;
                CLKOUT4_DESKEW_ADJUST : string := "NONE";
                CLKOUT4_DIVIDE : integer := 1;
                CLKOUT4_DUTY_CYCLE : real := 0.5;
                CLKOUT4_PHASE : real := 0.0;
                CLKOUT5_DESKEW_ADJUST : string := "NONE";
                CLKOUT5_DIVIDE : integer := 1;
                CLKOUT5_DUTY_CYCLE : real := 0.5;
                CLKOUT5_PHASE : real := 0.0;
                COMPENSATION : string := "SYSTEM_SYNCHRONOUS";
                DIVCLK_DIVIDE : integer := 1;
                EN_REL : boolean := FALSE;
                PLL_PMCD_MODE : boolean := FALSE;
                REF_JITTER : real := 0.100;
                RESET_ON_LOSS_OF_LOCK : boolean := FALSE;
                RST_DEASSERT_CLK : string := "CLKIN1"

  );
port (
                CLKFBDCM : out std_ulogic := '0';
                CLKFBOUT : out std_ulogic := '0';
                CLKOUT0 : out std_ulogic := '0';
                CLKOUT1 : out std_ulogic := '0';
                CLKOUT2 : out std_ulogic := '0';
                CLKOUT3 : out std_ulogic := '0';
                CLKOUT4 : out std_ulogic := '0';
                CLKOUT5 : out std_ulogic := '0';
                CLKOUTDCM0 : out std_ulogic := '0';
                CLKOUTDCM1 : out std_ulogic := '0';
                CLKOUTDCM2 : out std_ulogic := '0';
                CLKOUTDCM3 : out std_ulogic := '0';
                CLKOUTDCM4 : out std_ulogic := '0';
                CLKOUTDCM5 : out std_ulogic := '0';
                DO : out std_logic_vector(15 downto 0);
                DRDY : out std_ulogic := '0';
                LOCKED : out std_ulogic := '0';
                CLKFBIN : in std_ulogic;
                CLKIN1 : in std_ulogic;
                CLKIN2 : in std_ulogic;
                CLKINSEL : in std_ulogic;
                DADDR : in std_logic_vector(4 downto 0);
                DCLK : in std_ulogic;
                DEN : in std_ulogic;
                DI : in std_logic_vector(15 downto 0);
                DWE : in std_ulogic;
                REL : in std_ulogic;
                RST : in std_ulogic
     );
end PLL_ADV;


-- Architecture body --

architecture PLL_ADV_V of PLL_ADV is

  ---------------------------------------------------------------------------
  -- Function SLV_TO_INT converts a std_logic_vector TO INTEGER
  ---------------------------------------------------------------------------
  function SLV_TO_INT(SLV: in std_logic_vector
                      ) return integer is

    variable int : integer;
  begin
    int := 0;
    for i in SLV'high downto SLV'low loop
      int := int * 2;
      if SLV(i) = '1' then
        int := int + 1;
      end if;
    end loop;
    return int;
  end;

  ---------------------------------------------------------------------------
  -- Function ADDR_IS_VALID checks for the validity of the argument. A FALSE
  -- is returned if any argument bit is other than a '0' or '1'.
  ---------------------------------------------------------------------------
  function ADDR_IS_VALID (
    SLV : in std_logic_vector
    ) return boolean is

    variable IS_VALID : boolean := TRUE;

  begin
    for I in SLV'high downto SLV'low loop
      if (SLV(I) /= '0' AND SLV(I) /= '1') then
        IS_VALID := FALSE;
      end if;
    end loop;
    return IS_VALID;
  end ADDR_IS_VALID;

  function int2real( int_in : in integer) return real is
    variable conline1 : line;
    variable rl_value : real;
    variable tmpv1 : real;
    variable tmpv2 : real := 1.0;
    variable tmpi : integer;
  begin
    tmpi := int_in;
    write (conline1, tmpi);
    write (conline1, string'(".0 "));
    write (conline1, tmpv2);
    read (conline1, tmpv1);
    rl_value := tmpv1;
    return rl_value;
    DEALLOCATE(conline1);
  end int2real;

  function real2int( real_in : in real) return integer is
    variable int_value : integer;
    variable int_value1 : integer;
    variable tmps : time := 1 ps;
    variable tmps1 : real;
    
  begin
    if (real_in < 1.00000 and real_in > -1.00000) then
        int_value1 := 0;
    else
      tmps := real_in * 1 ns;
      int_value := tmps / 1 ns;
      tmps1 := int2real (int_value);
      if ( tmps1 > real_in) then
        int_value1 := int_value - 1 ;
      else
        int_value1 := int_value;
      end if;
    end if;
    return int_value1;
  end real2int;

  
  procedure clkout_dly_cal (clkout_dly : out std_logic_vector(5 downto 0);
                          clkpm_sel : out std_logic_vector(2 downto 0);
                          clkdiv : in integer;
                          clk_ps : in real;
                          clk_ps_name : in string )
  is
    variable clk_dly_rl : real;
    variable clk_dly_rem : real;
    variable clk_dly_int : integer;
    variable clk_dly_int_rl : real;
    variable clkdiv_real : real;
    variable clkpm_sel_rl : real;
    variable clk_ps_rl : real;
    variable  Message : line;
  begin

     clkdiv_real := int2real(clkdiv);
     if (clk_ps < 0.0) then
        clk_dly_rl := (360.0 + clk_ps) * clkdiv_real / 360.0;
     else
        clk_dly_rl := clk_ps * clkdiv_real / 360.0;
     end if;
     clk_dly_int := real2int (clk_dly_rl);

     if (clk_dly_int > 63) then
        Write ( Message, string'(" Warning : Attribute "));
        Write ( Message, clk_ps_name );
        Write ( Message, string'(" of PLL_ADV is set to "));
        Write ( Message, clk_ps);
        Write ( Message, string'(". Required phase shifting can not be reached since it is over the maximum phase shifting ability of PLL_ADV"));
        Write ( Message, '.' & LF );
        assert false report Message.all severity error;
        DEALLOCATE (Message);
        clkout_dly := "111111";
     else
       clkout_dly := STD_LOGIC_VECTOR(TO_UNSIGNED(clk_dly_int, 6));
     end if;

     clk_dly_int_rl := int2real (clk_dly_int);
     clk_dly_rem := clk_dly_rl - clk_dly_int_rl;

    if (clk_dly_rem < 0.125) then
        clkpm_sel :=  "000";
        clkpm_sel_rl := 0.0;
    elsif (clk_dly_rem >=  0.125 and  clk_dly_rem < 0.25) then
        clkpm_sel(2 downto 0) :=  "001";
        clkpm_sel_rl := 1.0;
    elsif (clk_dly_rem >=  0.25 and clk_dly_rem < 0.375) then
        clkpm_sel :=  "010";
        clkpm_sel_rl := 2.0;
    elsif (clk_dly_rem >=  0.375 and clk_dly_rem < 0.5) then
        clkpm_sel :=  "011";
        clkpm_sel_rl := 3.0;
    elsif (clk_dly_rem >=  0.5 and clk_dly_rem < 0.625) then
        clkpm_sel :=  "100";
        clkpm_sel_rl := 4.0;
    elsif (clk_dly_rem >=  0.625 and clk_dly_rem < 0.75) then
        clkpm_sel :=  "101";
        clkpm_sel_rl := 5.0;
    elsif (clk_dly_rem >=  0.75 and clk_dly_rem < 0.875) then
        clkpm_sel :=  "110";
        clkpm_sel_rl := 6.0;
    elsif (clk_dly_rem >=  0.875 ) then
        clkpm_sel :=  "111";
        clkpm_sel_rl := 7.0;
    end if;

    if (clk_ps < 0.0) then
       clk_ps_rl := (clk_dly_int_rl + 0.125 * clkpm_sel_rl) * 360.0 / clkdiv_real - 360.0;
    else
       clk_ps_rl := (clk_dly_int_rl + 0.125 * clkpm_sel_rl) * 360.0 / clkdiv_real;
    end if;

    if (((clk_ps_rl- clk_ps) > 0.001) or ((clk_ps_rl- clk_ps) < -0.001)) then
        Write ( Message, string'(" Warning : Attribute "));
        Write ( Message, clk_ps_name );
        Write ( Message, string'(" of PLL_ADV is set to "));
        Write ( Message, clk_ps);
        Write ( Message, string'(". Real phase shifting is "));
        Write ( Message, clk_ps_rl);
        Write ( Message, string'(". Required phase shifting can not be reached"));
        Write ( Message, '.' & LF );
        assert false report Message.all severity error;
        DEALLOCATE (Message);
    end if;
  end procedure clkout_dly_cal;

procedure clk_out_para_cal (clk_ht : out std_logic_vector(6 downto 0);
                            clk_lt : out std_logic_vector(6 downto 0);
                            clk_nocnt : out std_ulogic;
                            clk_edge : out std_ulogic;
                            CLKOUT_DIVIDE : in  integer;
                            CLKOUT_DUTY_CYCLE : in  real )
  is 
     variable tmp_value : real;
     variable tmp_value0 : real;
     variable tmp_value_l: real;
     variable tmp_value2 : real;
     variable tmp_value1 : integer;
     variable clk_lt_tmp : real;
     variable clk_ht_i : integer;
     variable clk_lt_i : integer;
     variable CLKOUT_DIVIDE_real : real;
     constant O_MAX_HT_LT_real : real := 64.0;
  begin
     CLKOUT_DIVIDE_real := int2real(CLKOUT_DIVIDE);
     tmp_value := CLKOUT_DIVIDE_real * CLKOUT_DUTY_CYCLE;
     tmp_value0 := tmp_value * 2.0;
     tmp_value1 := real2int(tmp_value0) mod 2;
     tmp_value2 := CLKOUT_DIVIDE_real - tmp_value;

     if ((tmp_value) >= O_MAX_HT_LT_real) then
       clk_lt_tmp := 64.0;
       clk_lt := "1000000";
     else
       if (tmp_value < 1.0) then
           clk_lt := "0000001";
           clk_lt_tmp := 1.0;
       else
           if (tmp_value1 /= 0) then
             clk_lt_i := real2int(tmp_value) + 1;
           else
             clk_lt_i := real2int(tmp_value);
           end if;
           clk_lt := STD_LOGIC_VECTOR(TO_UNSIGNED(clk_lt_i, 7));
           clk_lt_tmp := int2real(clk_lt_i);
       end if;
     end if;

   tmp_value_l := CLKOUT_DIVIDE_real -  clk_lt_tmp;

   if ( tmp_value_l >= O_MAX_HT_LT_real) then
       clk_ht := "1000000";
   else
      clk_ht_i := real2int(tmp_value_l);
      clk_ht :=  STD_LOGIC_VECTOR(TO_UNSIGNED(clk_ht_i, 7));
   end if;

   if (CLKOUT_DIVIDE = 1) then
      clk_nocnt := '1';
   else
      clk_nocnt := '0';
   end if;

   if (tmp_value < 1.0) then
      clk_edge := '1';
   elsif (tmp_value1 /= 0) then
      clk_edge := '1';
   else
      clk_edge := '0';
   end if;

  end procedure clk_out_para_cal;

 procedure clkout_pm_cal ( clk_ht1 : out integer ;
                           clk_div : out integer;
                           clk_div1 : out integer;
                           clk_ht : in std_logic_vector(6 downto 0);
                           clk_lt : in std_logic_vector(6 downto 0);
                           clk_nocnt : in std_ulogic;
                           clk_edge : in std_ulogic )
  is 
     variable clk_div_tmp : integer;
  begin
    if (clk_nocnt = '1') then
        clk_div := 1;
        clk_div1 := 1;
        clk_ht1 := 1;
    else 
      if (clk_edge = '1') then
           clk_ht1 := 2 * SLV_TO_INT(clk_ht) + 1;
      else
           clk_ht1 :=  2 * SLV_TO_INT(clk_ht);
      end if;
       clk_div_tmp := SLV_TO_INT(clk_ht) + SLV_TO_INT(clk_lt);
       clk_div := clk_div_tmp;
       clk_div1 :=  2 * clk_div_tmp - 1;
    end if;

  end procedure clkout_pm_cal;

 procedure clkout_delay_para_drp ( clkout_dly : out std_logic_vector(5 downto 0);
                           clk_nocnt : out std_ulogic;
                           clk_edge : out std_ulogic;
                           di_in : in std_logic_vector(15 downto 0);
                           daddr_in : in std_logic_vector(4 downto 0);
                           di_str : string ( 1 to 16);
                           daddr_str : string ( 1 to 5))
  is
     variable  Message : line;
  begin
     clkout_dly := di_in(5 downto 0);
     clk_nocnt := di_in(6);
     clk_edge := di_in(7);
 end procedure clkout_delay_para_drp;
                           
procedure clkout_hl_para_drp ( clk_lt : out std_logic_vector(6 downto 0) ;
                               clk_ht : out std_logic_vector(6 downto 0) ;
                               clkpm_sel : out std_logic_vector(2 downto 0) ;
                           di_in : in std_logic_vector(15 downto 0);
                           daddr_in : in std_logic_vector(4 downto 0);
                           di_str : string ( 1 to 16);
                           daddr_str : string ( 1 to 5))
  is
     variable  Message : line;
  begin
     if (di_in(12) /= '1')  then
      Write ( Message, string'(" Error : PLL_ADV input DI(15 downto 0) is set to"));
      Write ( Message, di_str);
      Write ( Message, string'(" at address DADDR = "));
      Write ( Message, daddr_str );
      Write ( Message, string'(". The bit 12 need to be set to 1."));
      Write ( Message, '.' & LF );
      assert false report Message.all severity error;
      DEALLOCATE (Message);
     end if;
  
    if ( di_in(5 downto 0) = "000000") then
       clk_lt := "1000000";
    else
       clk_lt := ( '0' & di_in(5 downto 0));
    end if;
    if (  di_in(11 downto 6) = "000000") then
      clk_ht := "1000000";
    else
      clk_ht := ( '0' & di_in(11 downto 6));
    end if;
    clkpm_sel := di_in(15 downto 13);
end procedure clkout_hl_para_drp;

  function clkout_duty_chk (CLKOUT_DIVIDE : in integer;
                            CLKOUT_DUTY_CYCLE : in real;
                            CLKOUT_DUTY_CYCLE_N : in string)
                          return std_ulogic is
   constant O_MAX_HT_LT_real : real := 64.0;
   variable CLKOUT_DIVIDE_real : real;
   variable CLK_DUTY_CYCLE_MIN : real;
   variable CLK_DUTY_CYCLE_MIN_rnd : real;
   variable CLK_DUTY_CYCLE_MAX : real;
   variable CLK_DUTY_CYCLE_STEP : real;
   variable clk_duty_tmp_int : integer;
   variable  duty_cycle_valid : std_ulogic;
   variable tmp_duty_value : real;
   variable  tmp_j : real; 
   variable Message : line;
   variable step_round_tmp : integer;
   variable step_round_tmp1 : real;

  begin
   CLKOUT_DIVIDE_real := int2real(CLKOUT_DIVIDE);
   step_round_tmp := 1000 /CLKOUT_DIVIDE;
   step_round_tmp1 := int2real(step_round_tmp);
   if (CLKOUT_DIVIDE_real > O_MAX_HT_LT_real) then 
      CLK_DUTY_CYCLE_MIN := (CLKOUT_DIVIDE_real - O_MAX_HT_LT_real)/CLKOUT_DIVIDE_real;
      CLK_DUTY_CYCLE_MAX := (O_MAX_HT_LT_real + 0.5)/CLKOUT_DIVIDE_real;
      CLK_DUTY_CYCLE_MIN_rnd := CLK_DUTY_CYCLE_MIN;
   else  
      if (CLKOUT_DIVIDE = 1) then
          CLK_DUTY_CYCLE_MIN_rnd := 0.0;
          CLK_DUTY_CYCLE_MIN := 0.0;
      else
          CLK_DUTY_CYCLE_MIN_rnd := step_round_tmp1 / 1000.00;
          CLK_DUTY_CYCLE_MIN := 1.0 / CLKOUT_DIVIDE_real;
      end if;
      CLK_DUTY_CYCLE_MAX := 1.0;
   end if;

   if ((CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_MAX) or (CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd)) then 
     Write ( Message, string'(" Attribute Syntax Warning : "));
     Write ( Message, CLKOUT_DUTY_CYCLE_N);
     Write ( Message, string'(" is set to "));
     Write ( Message, CLKOUT_DUTY_CYCLE);
     Write ( Message, string'(" and is not in the allowed range "));
     Write ( Message, CLK_DUTY_CYCLE_MIN);
     Write ( Message, string'("  to "));
     Write ( Message, CLK_DUTY_CYCLE_MAX);
     Write ( Message, '.' & LF );
      assert false report Message.all severity warning;
      DEALLOCATE (Message);
     end if;

    CLK_DUTY_CYCLE_STEP := 0.5 / CLKOUT_DIVIDE_real;
    tmp_j := 0.0;
    duty_cycle_valid := '0';
    clk_duty_tmp_int := 0;
    for j in 0 to  (2 * CLKOUT_DIVIDE ) loop
      tmp_duty_value := CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * tmp_j;
      if (abs(tmp_duty_value - CLKOUT_DUTY_CYCLE) < 0.001 and (tmp_duty_value <= CLK_DUTY_CYCLE_MAX)) then
          duty_cycle_valid := '1';
      end if;
      tmp_j := tmp_j + 1.0;
    end loop;

   if (duty_cycle_valid /= '1') then
    Write ( Message, string'(" Attribute Syntax Warning : "));
    Write ( Message, CLKOUT_DUTY_CYCLE_N);
    Write ( Message, string'(" =  "));
    Write ( Message, CLKOUT_DUTY_CYCLE);
    Write ( Message, string'(" which is  not an allowed value. Allowed value s are: "));
    Write ( Message,  LF );
    tmp_j := 0.0;
    for j in 0 to  (2 * CLKOUT_DIVIDE ) loop
      tmp_duty_value := CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * tmp_j;
      if ( (tmp_duty_value <= CLK_DUTY_CYCLE_MAX) and (tmp_duty_value < 1.0)) then
       Write ( Message,  tmp_duty_value);
       Write ( Message,  LF );
      end if;
      tmp_j := tmp_j + 1.0;
    end loop;
      assert false report Message.all severity warning;
      DEALLOCATE (Message);
  end if;
    return duty_cycle_valid;
  end function clkout_duty_chk;

-- Input/Output Pin signals

        constant VCOCLK_FREQ_MAX : real := 1440.0;
        constant VCOCLK_FREQ_MIN : real := 400.0;
        constant VCOCLK_FREQ_TARGET : real := 800.0;
        constant CLKIN_FREQ_MAX : real := 710.0;
        constant CLKIN_FREQ_MIN : real := 19.0;
        constant CLKPFD_FREQ_MAX : real := 550.0;
        constant CLKPFD_FREQ_MIN : real := 19.0;
        constant O_MAX_HT_LT : integer := 64;
        constant REF_CLK_JITTER_MAX : time := 1000 ps;
        constant REF_CLK_JITTER_SCALE : real := 0.1;
        constant MAX_FEEDBACK_DELAY : time := 10 ns;
        constant MAX_FEEDBACK_DELAY_SCALE : real := 1.0;

        constant  PLL_LOCK_TIME : integer := 7;

        signal   CLKIN1_ipd  :  std_ulogic;
        signal   CLKIN2_ipd  :  std_ulogic;
        signal   CLKFBIN_ipd  :  std_ulogic;
        signal   RST_ipd  :  std_ulogic;
        signal   REL_ipd  :  std_ulogic;
        signal   CLKINSEL_ipd  :  std_ulogic;
        signal   DADDR_ipd  :  std_logic_vector(4 downto 0);
        signal   DI_ipd  :  std_logic_vector(15 downto 0);
        signal   DWE_ipd  :  std_ulogic;
        signal   DEN_ipd  :  std_ulogic;
        signal   DCLK_ipd  :  std_ulogic;
        signal   GSR          : std_ulogic := '0';
        signal   CLKOUT0_out  :  std_ulogic := '0';
        signal   CLKOUT1_out  :  std_ulogic := '0';
        signal   CLKOUT2_out  :  std_ulogic := '0';
        signal   CLKOUT3_out  :  std_ulogic := '0';
        signal   CLKOUT4_out  :  std_ulogic := '0';
        signal   CLKOUT5_out  :  std_ulogic := '0';
        signal   CLKFBOUT_out  :  std_ulogic := '0';
        signal   LOCKED_out  :  std_ulogic := '0';
        signal   do_out  :  std_logic_vector(15 downto 0);
        signal   DRDY_out  :  std_ulogic := '0';
        signal   CLKIN1_dly  :  std_ulogic;
        signal   CLKIN2_dly  :  std_ulogic;
        signal   CLKFBIN_dly  :  std_ulogic;
        signal   RST_dly  :  std_ulogic;
        signal   REL_dly  :  std_ulogic;
        signal   CLKINSEL_dly  :  std_ulogic;
        signal   DADDR_dly  :  std_logic_vector(4 downto 0);
        signal   DI_dly  :  std_logic_vector(15 downto 0);
        signal   DWE_dly  :  std_ulogic;
        signal   DEN_dly  :  std_ulogic;
        signal   DCLK_dly  :  std_ulogic;

        signal di_in : std_logic_vector (15 downto 0);
        signal dwe_in : std_ulogic := '0';
        signal den_in : std_ulogic := '0';
        signal dclk_in : std_ulogic := '0';
        signal rst_in : std_ulogic := '0';
        signal rst_input : std_ulogic := '0';
        signal rel_in : std_ulogic := '0';
        signal clkfb_in : std_ulogic := '0';
        signal clkin1_in : std_ulogic := '0';
        signal clkin1_in_dly : std_ulogic := '0';
        signal clkin2_in : std_ulogic := '0';
        signal clkinsel_in : std_ulogic := '0';
        signal clkinsel_tmp : std_ulogic := '0';
        signal daddr_in :  std_logic_vector(4 downto 0);
        signal daddr_in_lat :  integer := 0;
        signal drp_lock :  std_ulogic := '0';
        signal drp_lock1  :  std_ulogic := '0';
        type   drp_array is array (31 downto 0) of std_logic_vector(15 downto 0);
        signal dr_sram : drp_array;
        
        signal clk0in :  std_ulogic := '0';
        signal clk1in :  std_ulogic := '0';
        signal clk2in :  std_ulogic := '0';
        signal clk3in :  std_ulogic := '0';
        signal clk4in :  std_ulogic := '0';
        signal clk5in :  std_ulogic := '0';
        signal clkfbm1in :  std_ulogic := '0';
        signal clk0_out :  std_ulogic := '0';
        signal clk1_out :  std_ulogic := '0';
        signal clk2_out :  std_ulogic := '0';
        signal clk3_out :  std_ulogic := '0';
        signal clk4_out :  std_ulogic := '0';
        signal clk5_out :  std_ulogic := '0';
        signal clkfb_out :  std_ulogic := '0';
        signal clkfbm1_out :  std_ulogic := '0';
        signal clkout_en :  std_ulogic := '0';
        signal clkout_en1 :  std_ulogic := '0';
        signal clkout_en0 :  std_ulogic := '0';
        signal clkout_en0_tmp :  std_ulogic := '0';
        signal clkout_cnt : integer := 0;
        signal clkin_cnt : integer := 0;
        signal clkin_lock_cnt : integer := 0;
        signal clkout_en_time : integer := PLL_LOCK_TIME + 2;
        signal locked_en_time : integer := 0;
        signal lock_cnt_max : integer := 0;
        signal clkvco_lk :  std_ulogic := '0';
        signal clkvco_lk_rst :  std_ulogic := '0';
        signal clkvco_free :  std_ulogic := '0';
        signal clkvco :  std_ulogic := '0';
        signal fbclk_tmp :  std_ulogic := '0';

        signal rst_in1 :  std_ulogic := '0';
        signal rst_unlock :  std_ulogic := '0';
        signal rst_on_loss :  std_ulogic := '0';
        signal rst_edge : time := 0 ps;
        signal rst_ht : time := 0 ps;
        signal fb_delay_found :  std_ulogic := '0';
        signal fb_delay_found_tmp :  std_ulogic := '0';
        signal clkfb_tst :  std_ulogic := '0';
        constant fb_delay_max : time := MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE;
        signal fb_delay : time := 0 ps;
        signal clkvco_delay : time := 0 ps;
        signal val_tmp : time := 0 ps;
        signal clkin_edge : time := 0 ps;
        signal delay_edge : time := 0 ps;

        type   real_array_usr is array (4 downto 0) of time;
        signal clkin_period : real_array_usr := (others => 2.0 ns);
        signal period_vco : time := 0.000 ns;
        signal period_vco_rm : integer := 0;
        signal period_vco_cmp_cnt : integer := 0;
        signal clkvco_tm_cnt : integer := 0;
        signal period_vco_cmp_flag : integer := 0;
        signal period_vco1 : time := 0.000 ns;
        signal period_vco2 : time := 0.000 ns;
        signal period_vco3 : time := 0.000 ns;
        signal period_vco4 : time := 0.000 ns;
        signal period_vco5 : time := 0.000 ns;
        signal period_vco6 : time := 0.000 ns;
        signal period_vco7 : time := 0.000 ns;
        signal period_vco_half : time := 0.000 ns;
        signal period_vco_half1 : time := 0.000 ns;
        signal period_vco_half_rm : time := 0.000 ns;
        constant period_vco_max : time := 1 ns * 1000 / VCOCLK_FREQ_MIN;
        constant period_vco_min : time := 1 ns * 1000 / VCOCLK_FREQ_MAX;
        constant period_vco_target : time := 1 ns * 1000 / VCOCLK_FREQ_TARGET;
        constant period_vco_target_half : time := 1 ns * 500 / VCOCLK_FREQ_TARGET;
        signal period_fb : time := 0.000 ns;
        signal period_avg : time := 0.000 ns;

        signal clkvco_freq_init_chk : real := 0.0;
        signal clkfb_stop_max : integer := 3;
        signal clkin_stop_max : integer := DIVCLK_DIVIDE + 1;
        signal md_product : integer := CLKFBOUT_MULT * DIVCLK_DIVIDE;
        signal m_product : integer := CLKFBOUT_MULT;
        signal m_product2 : integer := CLKFBOUT_MULT / 2;

        signal pll_locked_delay : time := 0 ps;
        signal clkin_dly_t : time := 0 ps;
        signal clkfb_dly_t : time := 0 ps;
        signal clkpll : std_ulogic := '0';
        signal clkpll_dly : std_ulogic := '0';
        signal clkfb_in_dly : std_ulogic := '0';
        signal pll_unlock : std_ulogic := '0';
        signal pll_locked_tm : std_ulogic := '0';
        signal pll_locked_tmp1 : std_ulogic := '0';
        signal pll_locked_tmp2 : std_ulogic := '0';
        signal lock_period : std_ulogic := '0';
        signal pll_lock_tm: std_ulogic := '0';
        signal unlock_recover : std_ulogic := '0';
        signal clkin_stopped : std_ulogic := '0';
        signal clkin_stopped_p : std_ulogic := '0';
        signal clkin_stopped_n : std_ulogic := '0';
        signal  clkstop_cnt_p : integer := 0;
        signal  clkstop_cnt_n : integer := 0;
        signal  clkfbstop_cnt_p : integer := 0;
        signal  clkfbstop_cnt_n : integer := 0;
        signal clkfb_stopped : std_ulogic := '0';
        signal clkfb_stopped_p : std_ulogic := '0';
        signal clkfb_stopped_n : std_ulogic := '0';
        signal clkpll_jitter_unlock : std_ulogic := '0';
        signal clkin_jit : time := 0 ps;
        constant ref_jitter_max_tmp : time := REF_CLK_JITTER_MAX;
        
        signal clka1_out : std_ulogic := '0';
        signal clkb1_out : std_ulogic := '0';
        signal clka1d2_out : std_ulogic := '0';
        signal clka1d4_out : std_ulogic := '0';
        signal clka1d8_out : std_ulogic := '0';
        signal clkdiv_rel_rst : std_ulogic := '0';
        signal qrel_o_reg1 : std_ulogic := '0';
        signal qrel_o_reg2 : std_ulogic := '0';
        signal qrel_o_reg3 : std_ulogic := '0';
        signal rel_o_mux_sel : std_ulogic := '0';
        signal pmcd_mode : std_ulogic := '0';
        signal rel_rst_o : std_ulogic := '0';
        signal rel_o_mux_clk : std_ulogic := '0';
        signal rel_o_mux_clk_tmp : std_ulogic := '0';
        signal clka1_in : std_ulogic := '0';
        signal clkb1_in : std_ulogic := '0';
        signal clkout0_out_out : std_ulogic := '0';
        signal clkout1_out_out : std_ulogic := '0';
        signal clkout2_out_out : std_ulogic := '0';
        signal clkout3_out_out : std_ulogic := '0';
        signal clkout4_out_out : std_ulogic := '0';
        signal clkout5_out_out : std_ulogic := '0';
        signal clkfbout_out_out : std_ulogic := '0';
        signal clk0ps_en : std_ulogic := '0';
        signal clk1ps_en : std_ulogic := '0';
        signal clk2ps_en : std_ulogic := '0';
        signal clk3ps_en : std_ulogic := '0';
        signal clk4ps_en : std_ulogic := '0';
        signal clk5ps_en : std_ulogic := '0';
        signal clkfbm1ps_en : std_ulogic := '0';
        signal clkout_mux : std_logic_vector (7 downto 0) := X"00";
        signal clk0pm_sel : integer := 0;
        signal clk1pm_sel : integer := 0;
        signal clk2pm_sel : integer := 0;
        signal clk3pm_sel : integer := 0; 
        signal clk4pm_sel : integer := 0;
        signal clk5pm_sel : integer := 0;
        signal clkfbm1pm_sel : integer := 0;
        signal clkfbm1pm_rl : real := 0.0;
        signal clk0_edge  : std_ulogic := '0';
        signal clk1_edge  : std_ulogic := '0';
        signal clk2_edge  : std_ulogic := '0';
        signal clk3_edge  : std_ulogic := '0';
        signal clk4_edge  : std_ulogic := '0';
        signal clk5_edge  : std_ulogic := '0';
        signal clkfbm1_edge  : std_ulogic := '0';
        signal clkind_edge  : std_ulogic := '0';
        signal clk0_nocnt  : std_ulogic := '0';
        signal clk1_nocnt  : std_ulogic := '0';
        signal clk2_nocnt  : std_ulogic := '0';
        signal clk3_nocnt  : std_ulogic := '0';
        signal clk4_nocnt  : std_ulogic := '0';
        signal clk5_nocnt  : std_ulogic := '0';
        signal clkfbm1_nocnt  : std_ulogic := '0';
        signal clkind_nocnt  : std_ulogic := '0';
        signal clk0_dly_cnt : integer := 0;
        signal clk1_dly_cnt : integer := 0;
        signal clk2_dly_cnt : integer := 0;
        signal clk3_dly_cnt : integer := 0;
        signal clk4_dly_cnt : integer := 0;
        signal clk5_dly_cnt : integer := 0;
        signal clkfbm1_dly_cnt : integer := 0;
        signal clk0_ht : std_logic_vector (6 downto 0) := "0000000";
        signal clk1_ht : std_logic_vector (6 downto 0) := "0000000";
        signal clk2_ht : std_logic_vector (6 downto 0) := "0000000";
        signal clk3_ht : std_logic_vector (6 downto 0) := "0000000";
        signal clk4_ht : std_logic_vector (6 downto 0) := "0000000";
        signal clk5_ht : std_logic_vector (6 downto 0) := "0000000";
        signal clkfbm1_ht : std_logic_vector (6 downto 0) := "0000000";
        signal clk0_lt : std_logic_vector (6 downto 0) := "0000000";
        signal clk1_lt : std_logic_vector (6 downto 0) := "0000000";
        signal clk2_lt : std_logic_vector (6 downto 0) := "0000000";
        signal clk3_lt : std_logic_vector (6 downto 0) := "0000000";
        signal clk4_lt : std_logic_vector (6 downto 0) := "0000000";
        signal clk5_lt : std_logic_vector (6 downto 0) := "0000000";
        signal clkfbm1_lt : std_logic_vector (6 downto 0) := "0000000";
        signal clkout0_dly : integer := 0;
        signal clkout1_dly : integer := 0;
        signal clkout2_dly : integer := 0;
        signal clkout3_dly : integer := 0;
        signal clkout4_dly : integer := 0;
        signal clkout5_dly : integer := 0;
        signal clkfbm1_dly : integer := 0;
        signal clkind_ht : std_logic_vector (6 downto 0) := "0000000";
        signal clkind_lt : std_logic_vector (6 downto 0) := "0000000";
        signal clk0_ht1 : integer := 0;
        signal clk1_ht1 : integer := 0;
        signal clk2_ht1 : integer := 0;
        signal clk3_ht1 : integer := 0;
        signal clk4_ht1 : integer := 0;
        signal clk5_ht1 : integer := 0;
        signal clkfbm1_ht1 : integer := 0;
        signal clk0_cnt : integer := 0;
        signal clk1_cnt : integer := 0;
        signal clk2_cnt : integer := 0;
        signal clk3_cnt : integer := 0;
        signal clk4_cnt : integer := 0;
        signal clk5_cnt : integer := 0;
        signal clkfbm1_cnt : integer := 0;
        signal clk0_div : integer := 0;
        signal clk1_div : integer := 0;
        signal clk2_div : integer := 0;
        signal clk3_div : integer := 0;
        signal clk4_div : integer := 0;
        signal clk5_div : integer := 0;
        signal clkfbm1_div : integer := 1;
        signal clk0_div1 : integer := 0;
        signal clk1_div1 : integer := 0;
        signal clk2_div1 : integer := 0;
        signal clk3_div1 : integer := 0;
        signal clk4_div1 : integer := 0;
        signal clk5_div1 : integer := 0;
        signal clkfbm1_div1 : integer := 0;
        signal clkind_div : integer := 0;

begin

        CLKOUT0 <=  clkout0_out_out;
        CLKOUT1 <=  clkout1_out_out;
        CLKOUT2 <=  clkout2_out_out;
        CLKOUT3 <=   clkout3_out_out;
        CLKOUT4 <=   clkout4_out_out;
        CLKOUT5 <=   clkout5_out_out;
        CLKFBOUT <=   clkfbout_out_out;
        CLKOUTDCM0 <=  clkout0_out_out;
        CLKOUTDCM1 <=  clkout1_out_out;
        CLKOUTDCM2 <=  clkout2_out_out;
        CLKOUTDCM3 <=  clkout3_out_out;
        CLKOUTDCM4 <=  clkout4_out_out;
        CLKOUTDCM5 <=  clkout5_out_out;
        CLKFBDCM <=   clkfbout_out_out;

        DO <=   do_out(15 downto 0);
        DRDY <=   DRDY_out;
        LOCKED <= locked_out;

        clkin1_in <= CLKIN1;
        clkin2_in <= CLKIN2;
        clkinsel_in <= CLKINSEL;
        clkfb_in <= CLKFBIN;
        rst_input <= RST;
        rel_in <= REL;
        clkin1_in_dly <= CLKIN1;
        daddr_in(4 downto 0) <= DADDR(4 downto 0);
        di_in(15 downto 0) <= DI(15 downto 0);
        dwe_in <= DWE;
        den_in <= DEN;
        dclk_in <= DCLK;

        INIPROC : process
            variable Message : line;
            variable con_line : line;
            variable tmpvalue : real;
            variable chk_ok : std_ulogic;
            variable tmp_string : string(1 to 18);
            variable skipspace : character;
            variable CLK_DUTY_CYCLE_MIN : real;
            variable CLK_DUTY_CYCLE_MAX : real;
            variable  CLK_DUTY_CYCLE_STEP : real;
            variable O_MAX_HT_LT_real : real;
            variable duty_cycle_valid : std_ulogic;
            variable CLKOUT0_DIVIDE_real : real;
            variable CLKOUT1_DIVIDE_real : real;
            variable CLKOUT2_DIVIDE_real : real;
            variable CLKOUT3_DIVIDE_real : real;
            variable CLKOUT4_DIVIDE_real : real;
            variable CLKOUT5_DIVIDE_real : real;
            variable tmp_j : real;
            variable tmp_duty_value : real;
            variable clk_ht_i : std_logic_vector(5 downto 0);
            variable clk_lt_i : std_logic_vector(5 downto 0);
            variable clk_nocnt_i : std_ulogic;
            variable clk_edge_i : std_ulogic;
        begin
           if((COMPENSATION /= "INTERNAL") and (COMPENSATION /= "internal") and
                 (COMPENSATION /= "EXTERNAL") and (COMPENSATION /= "external") and
                 (COMPENSATION /= "SYSTEM_SYNCHRONOUS") and (COMPENSATION /= "system_synchronous") and
                 (COMPENSATION /= "SOURCE_SYNCHRONOUS") and (COMPENSATION /= "source_synchronous") and
                 (COMPENSATION /= "DCM2PLL") and (COMPENSATION /= "dcm2pll") and
                 (COMPENSATION /= "PLL2DCM") and (COMPENSATION /= "pll2dcm")) then 
             assert FALSE report "Attribute Syntax Error : COMPENSATION  is not INTERNAL, EXTERNAL, SYSTEM_SYNCHRONOUS, SOURCE_SYNCHRONOUS , DCM2PLL, PLL2DCM." severity error;
            end if;

           if((BANDWIDTH /= "HIGH") and (BANDWIDTH /= "high") and
                 (BANDWIDTH /= "LOW") and (BANDWIDTH /= "low") and
                 (BANDWIDTH /= "OPTIMIZED") and (BANDWIDTH /= "optimized")) then
             assert FALSE report "Attribute Syntax Error : BANDWIDTH  is not HIGH, LOW, OPTIMIZED." severity error;
            end if;

       if ((CLKOUT0_DESKEW_ADJUST /= "NONE") and (CLKOUT0_DESKEW_ADJUST /= "none")
            and (CLKOUT0_DESKEW_ADJUST /= "PPC") and (CLKOUT0_DESKEW_ADJUST /= "ppc")
            ) then 
          assert FALSE report "Error : CLKOUT0_DESKEW_ADJUST is not NONE or PPC." severity error;
       end if;  

       if ((CLKOUT1_DESKEW_ADJUST /= "NONE") and (CLKOUT1_DESKEW_ADJUST /= "none")
            and (CLKOUT1_DESKEW_ADJUST /= "PPC") and (CLKOUT1_DESKEW_ADJUST /= "ppc")
            ) then
          assert FALSE report "Error : CLKOUT1_DESKEW_ADJUST is not NONE or PPC." severity error;
       end if;  

       if ((CLKOUT2_DESKEW_ADJUST /= "NONE") and (CLKOUT2_DESKEW_ADJUST /= "none")
            and (CLKOUT2_DESKEW_ADJUST /= "PPC") and (CLKOUT2_DESKEW_ADJUST /= "ppc")
            ) then
          assert FALSE report "Error : CLKOUT2_DESKEW_ADJUST is not NONE or PPC." severity error;
       end if;  

       if ((CLKOUT3_DESKEW_ADJUST /= "NONE") and (CLKOUT3_DESKEW_ADJUST /= "none")
            and (CLKOUT3_DESKEW_ADJUST /= "PPC") and (CLKOUT3_DESKEW_ADJUST /= "ppc")
            ) then
          assert FALSE report "Error : CLKOUT3_DESKEW_ADJUST is not NONE or PPC." severity error;
       end if;  

       if ((CLKOUT4_DESKEW_ADJUST /= "NONE") and (CLKOUT4_DESKEW_ADJUST /= "none")
            and (CLKOUT4_DESKEW_ADJUST /= "PPC") and (CLKOUT4_DESKEW_ADJUST /= "ppc")
            ) then
          assert FALSE report "Error : CLKOUT4_DESKEW_ADJUST is not NONE or PPC." severity error;
       end if;  

       if ((CLKOUT5_DESKEW_ADJUST /= "NONE") and (CLKOUT5_DESKEW_ADJUST /= "none")
            and (CLKOUT5_DESKEW_ADJUST /= "PPC") and (CLKOUT5_DESKEW_ADJUST /= "ppc")
            ) then
          assert FALSE report "Error : CLKOUT5_DESKEW_ADJUST is not NONE or PPC." severity error;
       end if;  

       if ((CLKFBOUT_DESKEW_ADJUST /= "NONE") and (CLKFBOUT_DESKEW_ADJUST /= "none")
            and (CLKFBOUT_DESKEW_ADJUST /= "PPC") and (CLKFBOUT_DESKEW_ADJUST /= "ppc")
            ) then
          assert FALSE report "Error : CLKFBOUT_DESKEW_ADJUST is not NONE or PPC." severity error;
       end if;  

       case PLL_PMCD_MODE is
          when TRUE => pmcd_mode <= '1';
          when FALSE => pmcd_mode <= '0';
           when others  =>  assert FALSE report "Attribute Syntax Error : PLL_PMCD_MODE is not TRUE or FALSE." severity error;
       end case;

       case CLKOUT0_DIVIDE is
           when   1 to 128 => NULL ;
           when others  =>  assert FALSE report "Attribute Syntax Error : CLKOUT0_DIVIDE is not in range 1...128." severity error;
       end case;

        if ((CLKOUT0_PHASE < -360.0) or (CLKOUT0_PHASE > 360.0)) then
            assert FALSE report "Attribute Syntax Error : CLKOUT0_PHASE is not in range -360.0 to 360.0" severity error;
        elsif (pmcd_mode = '1' and CLKOUT0_PHASE /= 0.0) then
           assert FALSE report "Attribute Syntax Error : CLKOUT0_PHASE need set to 0.0 when attribute PLL_PMCD_MODE is set to TRUE." severity error; 
        end if;

        if ((CLKOUT0_DUTY_CYCLE < 0.0) or (CLKOUT0_DUTY_CYCLE > 1.0)) then
             assert FALSE report "Attribute Syntax Error : CLKOUT0_DUTY_CYCLE is not real in range 0.0 to 1.0 pecentage."severity error;
        elsif (pmcd_mode = '1' and CLKOUT0_DUTY_CYCLE /= 0.5) then
             assert FALSE report "Attribute Syntax Error : CLKOUT0_DUTY_CYCLE need set to 0.5 when attribute PLL_PMCD_MODE is set to TRUE." severity error;
        end if;

       case CLKOUT1_DIVIDE is
           when   1 to 128 => NULL ;
           when others  =>  assert FALSE report "Attribute Syntax Error : CLKOUT1_DIVIDE is not in range 1...128." severity error;
       end case;

        if ((CLKOUT1_PHASE < -360.0) or (CLKOUT1_PHASE > 360.0)) then
            assert FALSE report "Attribute Syntax Error : CLKOUT1_PHASE is not in range -360.0 to 360.0" severity error;
        elsif (pmcd_mode = '1' and CLKOUT1_PHASE /= 0.0) then
           assert FALSE report "Attribute Syntax Error : CLKOUT1_PHASE need set to 0.0 when attribute PLL_PMCD_MODE is set to TRUE." severity error; 
        end if;

        if ((CLKOUT1_DUTY_CYCLE < 0.0) or (CLKOUT1_DUTY_CYCLE > 1.0)) then
             assert FALSE report "Attribute Syntax Error : CLKOUT1_DUTY_CYCLE is not real in range 0.0 to 1.0 pecentage."severity error;
        elsif (pmcd_mode = '1' and CLKOUT1_DUTY_CYCLE /= 0.5) then
             assert FALSE report "Attribute Syntax Error : CLKOUT1_DUTY_CYCLE need set to 0.5 when attribute PLL_PMCD_MODE is set to TRUE." severity error;
        end if;

       case CLKOUT2_DIVIDE is
           when   1 to 128 => NULL ;
           when others  =>  assert FALSE report "Attribute Syntax Error : CLKOUT2_DIVIDE is not in range 1...128." severity error;
       end case;

        if ((CLKOUT2_PHASE < -360.0) or (CLKOUT2_PHASE > 360.0)) then
            assert FALSE report "Attribute Syntax Error : CLKOUT2_PHASE is not in range -360.0 to 360.0" severity error;
        elsif (pmcd_mode = '1' and CLKOUT2_PHASE /= 0.0) then
           assert FALSE report "Attribute Syntax Error : CLKOUT2_PHASE need set to 0.0 when attribute PLL_PMCD_MODE is set to TRUE." severity error; 
        end if;

        if ((CLKOUT2_DUTY_CYCLE < 0.0) or (CLKOUT2_DUTY_CYCLE > 1.0)) then
             assert FALSE report "Attribute Syntax Error : CLKOUT2_DUTY_CYCLE is not real in range 0.0 to 1.0 pecentage."severity error;
        elsif (pmcd_mode = '1' and CLKOUT2_DUTY_CYCLE /= 0.5) then
             assert FALSE report "Attribute Syntax Error : CLKOUT2_DUTY_CYCLE need set to 0.5 when attribute PLL_PMCD_MODE is set to TRUE." severity error;
        end if;


       case CLKOUT3_DIVIDE is
           when   1 to 128 => NULL ;
           when others  =>  assert FALSE report "Attribute Syntax Error : CLKOUT3_DIVIDE is not in range 1...128." severity error;
       end case;

        if ((CLKOUT3_PHASE < -360.0) or (CLKOUT3_PHASE > 360.0)) then
            assert FALSE report "Attribute Syntax Error : CLKOUT3_PHASE is not in range -360.0 to 360.0" severity error;
        elsif (pmcd_mode = '1' and CLKOUT3_PHASE /= 0.0) then
           assert FALSE report "Attribute Syntax Error : CLKOUT3_PHASE need set to 0.0 when attribute PLL_PMCD_MODE is set to TRUE." severity error; 
        end if;

        if ((CLKOUT3_DUTY_CYCLE < 0.0) or (CLKOUT3_DUTY_CYCLE > 1.0)) then
             assert FALSE report "Attribute Syntax Error : CLKOUT3_DUTY_CYCLE is not real in range 0.0 to 1.0 pecentage."severity error;
        elsif (pmcd_mode = '1' and CLKOUT3_DUTY_CYCLE /= 0.5) then
             assert FALSE report "Attribute Syntax Error : CLKOUT3_DUTY_CYCLE need set to 0.5 when attribute PLL_PMCD_MODE is set to TRUE." severity error;
        end if;


       case CLKOUT4_DIVIDE is
           when   1 to 128 => NULL ;
           when others  =>  assert FALSE report "Attribute Syntax Error : CLKOUT4_DIVIDE is not in range 1...128." severity error;
       end case;

        if ((CLKOUT4_PHASE < -360.0) or (CLKOUT4_PHASE > 360.0)) then
            assert FALSE report "Attribute Syntax Error : CLKOUT4_PHASE is not in range -360.0 to 360.0" severity error;
        end if;

        if ((CLKOUT4_DUTY_CYCLE < 0.0) or (CLKOUT4_DUTY_CYCLE > 1.0)) then
             assert FALSE report "Attribute Syntax Error : CLKOUT4_DUTY_CYCLE is not real in range 0.0 to 1.0 pecentage."severity error;
        end if;

       case CLKOUT5_DIVIDE is
           when   1 to 128 => NULL ;
           when others  =>  assert FALSE report "Attribute Syntax Error : CLKOUT5_DIVIDE is not in range 1...128." severity error;
       end case;

        if ((CLKOUT5_PHASE < -360.0) or (CLKOUT5_PHASE > 360.0)) then
            assert FALSE report "Attribute Syntax Error : CLKOUT5_PHASE is not in range 360.0 to 360.0" severity error;
        end if;

        if ((CLKOUT5_DUTY_CYCLE < 0.0) or (CLKOUT5_DUTY_CYCLE > 1.0)) then
             assert FALSE report "Attribute Syntax Error : CLKOUT5_DUTY_CYCLE is not real in range 0.0 to 1.0 pecentage."severity error;
        end if;


       case CLKFBOUT_MULT is
           when   1 to 74 =>  NULL;
           when others  =>  assert FALSE report "Attribute Syntax Error : CLKFBOUT_MULT is not in range 1...74." severity error;
       end case;

       if ( CLKFBOUT_PHASE < -360.0 or CLKFBOUT_PHASE > 360.0 ) then
             assert FALSE report "Attribute Syntax Error : CLKFBOUT_PHASE is not in range -360.0 to 360.0" severity error;
        elsif (pmcd_mode = '1' and CLKFBOUT_PHASE /= 0.0) then
           assert FALSE report "Attribute Syntax Error : CLKFBOUT_PHASE need set to 0.0 when attribute PLL_PMCD_MODE is set to TRUE." severity error; 
       end if;

       case DIVCLK_DIVIDE is
       when    1  to 52 => NULL;

           when others  =>  assert FALSE report "Attribute Syntax Error : DIVCLK_DIVIDE is not in range 1...52." severity error;
       end case;

           if ((REF_JITTER < 0.0) or (REF_JITTER > 0.999)) then
             assert FALSE report "Attribute Syntax Error : REF_JITTER is not in range 0.0 ... 1.0." severity error;
           end if;

          if (((CLKIN1_PERIOD < 1.0) or (CLKIN1_PERIOD > 52.630)) and (pmcd_mode = '0') and (CLKINSEL = '1')) then
            assert FALSE report "Attribute Syntax Error : CLKIN1_PERIOD is not in range 1.0 ... 52.630" severity error;
          end if;

          if (((CLKIN2_PERIOD < 1.0) or (CLKIN2_PERIOD > 52.630)) and (pmcd_mode = '0') and (CLKINSEL = '0')) then
            assert FALSE report "Attribute Syntax Error : CLKIN2_PERIOD is not in range 1.0 ...  52.630" severity error;
          end if;

       case RESET_ON_LOSS_OF_LOCK is
           when FALSE   =>  rst_on_loss <= '0';
--           when TRUE    =>  rst_on_loss <= '1';
           when others  =>  assert FALSE report " Attribute Syntax Error : generic RESET_ON_LOSS_OF_LOCK must be set to FALSE for PLL_ADV to function correctly. Please correct the setting for the attribute and re-run the simulation." severity error;
       end case;

   write (con_line, O_MAX_HT_LT);
   write (con_line, string'(".0 "));
   write (con_line, CLKOUT0_DIVIDE);
   write (con_line, string'(".0 "));
   write (con_line, CLKOUT1_DIVIDE);
   write (con_line, string'(".0 "));
   write (con_line, CLKOUT2_DIVIDE);
   write (con_line, string'(".0 "));
   write (con_line, CLKOUT3_DIVIDE);
   write (con_line, string'(".0 "));
   write (con_line, CLKOUT4_DIVIDE);
   write (con_line, string'(".0 "));
   write (con_line, CLKOUT5_DIVIDE);
   write (con_line, string'(".0 "));
   read (con_line, tmpvalue);
   O_MAX_HT_LT_real := tmpvalue;
   read (con_line, skipspace);
   read (con_line, tmpvalue);
   CLKOUT0_DIVIDE_real := tmpvalue;
   read (con_line, skipspace);
   read (con_line, tmpvalue);
   CLKOUT1_DIVIDE_real := tmpvalue;
   read (con_line, skipspace);
   read (con_line, tmpvalue);
   CLKOUT2_DIVIDE_real := tmpvalue;
   read (con_line, skipspace);
   read (con_line, tmpvalue);
   CLKOUT3_DIVIDE_real := tmpvalue;
   read (con_line, skipspace);
   read (con_line, tmpvalue);
   CLKOUT4_DIVIDE_real := tmpvalue;
   read (con_line, skipspace);
   read (con_line, tmpvalue);
   CLKOUT5_DIVIDE_real := tmpvalue;
   DEALLOCATE (con_line);

    chk_ok := clkout_duty_chk (CLKOUT0_DIVIDE, CLKOUT0_DUTY_CYCLE, "CLKOUT0_DUTY_CYCLE");
    chk_ok := clkout_duty_chk (CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE, "CLKOUT1_DUTY_CYCLE");
    chk_ok := clkout_duty_chk (CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE, "CLKOUT2_DUTY_CYCLE");
    chk_ok := clkout_duty_chk (CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE, "CLKOUT3_DUTY_CYCLE");
    chk_ok := clkout_duty_chk (CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE, "CLKOUT4_DUTY_CYCLE");
    chk_ok := clkout_duty_chk (CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE, "CLKOUT5_DUTY_CYCLE");

   locked_en_time <= md_product +  clkout_en_time + 2;
   lock_cnt_max <= md_product +  clkout_en_time + 6 + 2;

--------PMCD --------------

    if (RST_DEASSERT_CLK = "CLKIN1") then
         rel_o_mux_sel <= '1';
    elsif (RST_DEASSERT_CLK = "CLKFBIN") then
         rel_o_mux_sel <= '0';
    else
     assert false report "Attribute Syntax Error : The attribute RST_DEASSERT_CLK on PLL_ADV should be CLKIN1 or CLKFBIN." severity error;
     end if;

        case EN_REL is
          when FALSE => clkdiv_rel_rst <= '0';
          when TRUE => clkdiv_rel_rst <= '1';
          when others   => assert false report "Attribute Syntax Error : The attribute EN_REL on PLL_ADV should be TRUE or FALSE." severity error;
        end case;

     wait;
  end process INIPROC;


--
-- PMCD function
--

-- *** Clocks MUX
--   rel_o_mux_clk_tmp <= clkin1_in when rel_o_mux_sel = '1' else clkfb_in;
   rel_o_mux_clk_tmp <= clkin1_in_dly when rel_o_mux_sel = '1' else clkfb_in;
   rel_o_mux_clk <= rel_o_mux_clk_tmp when (pmcd_mode = '1') else '0';
   clka1_in <= clkin1_in when (pmcd_mode = '1') else '0';
   clkb1_in <= clkfb_in when (pmcd_mode = '1')  else '0';

--*** Rel and Rst
    rel_rst_P : process(rel_o_mux_clk, rst_input)
    begin
      if (rst_input = '1') then
         qrel_o_reg1 <= '1';
         qrel_o_reg2 <= '1';
      else
         if (rising_edge(rel_o_mux_clk)) then
            qrel_o_reg1 <= '0';
         end if;

         if (falling_edge(rel_o_mux_clk)) then
            qrel_o_reg2 <= qrel_o_reg1;
          end if;
      end if;
   end process;

    qrel_o_reg3_P : process ( rel_in, rst_input)
    begin
      if (rst_input = '1') then
          qrel_o_reg3 <= '1';
      elsif (rising_edge(rel_in)) then
            qrel_o_reg3 <= '0';
      end if;
    end process;

    rel_rst_o <= (qrel_o_reg3 or qrel_o_reg1) when clkdiv_rel_rst = '1' else qrel_o_reg1;

--*** CLKA
    clka1_out_P : process (clka1_in, qrel_o_reg2)
    begin
        if (qrel_o_reg2 = '1') then
            clka1_out <= '0';
        elsif (qrel_o_reg2 = '0') then
            clka1_out <= clka1_in;
        end if;
    end process;

---** CLKB
    clkb1_out_P : process (clkb1_in, qrel_o_reg2)
    begin
        if (qrel_o_reg2 = '1') then
            clkb1_out <= '0';
        elsif (qrel_o_reg2 = '0') then
            clkb1_out <= clkb1_in;
        end if;
    end process;

--*** Clock divider
    clka1d2_out_P : process(clka1_in, rel_rst_o) 
    begin
        if (rel_rst_o = '1') then
            clka1d2_out <= '0';
        elsif (rising_edge(clka1_in)) then
            clka1d2_out <= not clka1d2_out;
       end if;
    end process;

    clka1d4_out_P : process (clka1d2_out, rel_rst_o) 
    begin
        if (rel_rst_o = '1') then
            clka1d4_out <= '0';
        elsif (rising_edge(clka1d2_out)) then
            clka1d4_out <= not clka1d4_out;
       end if;
    end process;

    clka1d8_out_P : process (clka1d4_out, rel_rst_o)
     begin
        if (rel_rst_o = '1') then
            clka1d8_out <= '0';
        elsif (rising_edge(clka1d4_out)) then
            clka1d8_out <= not clka1d8_out;
        end if;
    end process;

          clkout5_out_out <=  '0' when (pmcd_mode = '1') else clkout5_out;
          clkout4_out_out <= '0' when (pmcd_mode = '1') else clkout4_out;
          clkout3_out_out <= clka1_out  when (pmcd_mode = '1') else clkout3_out;
          clkout2_out_out <= clka1d2_out when (pmcd_mode = '1') else clkout2_out;
          clkout1_out_out <=  clka1d4_out when (pmcd_mode = '1') else  clkout1_out;
          clkout0_out_out <= clka1d8_out when (pmcd_mode = '1') else clkout0_out;
          clkfbout_out_out <=  clkb1_out when (pmcd_mode = '1') else clkfb_out;

--
-- PLL  function start
--  

    clkinsel_tmp <= clkinsel_in after 1 ps;

    clkinsel_p : process 
          variable period_clkin : real;
          variable clkvco_freq_init_chk : real;
          variable Message : line;
          variable tmpreal1 : real;
          variable tmpreal2 : real;
    begin
      if (NOW > 1 ps  and  rst_in = '0' and (clkinsel_tmp = '0' or clkinsel_tmp = '1')) then
          assert false report
            "Input Error : PLL input clock can only be switched when RST=1.  CLKINSEL is changed when RST low, should be changed at RST high." 
          severity error;
      end if;

      if (NOW = 0 ps) then
         wait for 1 ps;
      end if;

      if ( clkinsel_in='1') then
         period_clkin :=  CLKIN1_PERIOD;
      else
         period_clkin := CLKIN2_PERIOD;
      end if;
      
      tmpreal1 := int2real(CLKFBOUT_MULT);
      tmpreal2 := int2real(DIVCLK_DIVIDE);
      clkvco_freq_init_chk :=  (tmpreal1 / ( period_clkin * tmpreal2)) * 1000.0;
      
      if ((clkvco_freq_init_chk > VCOCLK_FREQ_MAX) or (clkvco_freq_init_chk < VCOCLK_FREQ_MIN)) then
         Write ( Message, string'(" Attribute Syntax Error : The calculation of VCO frequency="));
         Write ( Message, clkvco_freq_init_chk);
         Write ( Message, string'(" Mhz. This exceeds the permitted VCO frequency range of "));
         Write ( Message, VCOCLK_FREQ_MIN);
          Write ( Message, string'(" MHz to "));
          Write ( Message, VCOCLK_FREQ_MAX);
          Write ( Message, string'(" MHz. The VCO frequency is calculated with formula: VCO frequency =  CLKFBOUT_MULT / (DIVCLK_DIVIDE * CLKIN_PERIOD)."));
         Write ( Message, string'(" Please adjust the attributes to the permitted VCO frequency range."));
          assert false report Message.all severity error;
              DEALLOCATE (Message);
      end if;   

     wait on clkinsel_in;
     end process;

   clkpll <= clkin1_in when clkinsel_in = '1' else clkin2_in;
   
   RST_SYNC_P : process (clkpll, rst_input)
   begin
     if (rst_input = '1') then
        rst_in1 <= '1';
     elsif (rising_edge (clkpll)) then
        rst_in1 <= rst_input;
     end if;
   end process;

   rst_in <= rst_in1 or rst_unlock;

   RST_ON_LOSS_P : process (pll_unlock)
   begin
     if (rising_edge(pll_unlock)) then
      if (rst_on_loss = '1' and locked_out = '1') then
          rst_unlock <= '1', '0' after 10 ns;
      end if;
     end if;
   end process;

   RST_PW_P : process (rst_input)
      variable rst_edge : time := 0 ps;
      variable rst_ht : time := 0 ps;
   begin
      if (rising_edge(rst_input)) then
         rst_edge := NOW;
      elsif (falling_edge(rst_input)) then
         rst_ht := NOW - rst_edge;
         if (rst_ht < 10 ns and rst_ht > 0 ps) then
            assert false report
               "Input Error : RST must be asserted at least for 10 ns."
            severity error;
         end if;
      end if;
   end process;
     
---- 
----  DRP port read and write
----

   do_out <= dr_sram(daddr_in_lat);

  DRP_PROC : process
    variable address : integer;
    variable valid_daddr : boolean := false;
    variable Message : line;
    variable di_str : string (1 to 16);
    variable daddr_str : string ( 1 to 5);
    variable first_time : boolean := true;
    variable clk_ht : std_logic_vector (6 downto 0);
    variable tmp_ht : std_logic_vector (6 downto 0);
    variable clk_lt : std_logic_vector (6 downto 0);
    variable tmp_lt : std_logic_vector (6 downto 0);
    variable clk_nocnt : std_ulogic;
    variable clk_edge : std_ulogic;
    variable clkout_dly : std_logic_vector (5 downto 0);
    variable clkpm_sel : std_logic_vector (2 downto 0);
    variable tmpx : std_logic_vector (7 downto 0);
    variable clk0_hti : std_logic_vector (6 downto 0);
    variable clk1_hti : std_logic_vector (6 downto 0);
    variable clk2_hti : std_logic_vector (6 downto 0);
    variable clk3_hti : std_logic_vector (6 downto 0);
    variable clk4_hti : std_logic_vector (6 downto 0);
    variable clk5_hti : std_logic_vector (6 downto 0);
    variable clkfbm1_hti : std_logic_vector (6 downto 0);
    variable clk0_lti : std_logic_vector (6 downto 0);
    variable clk1_lti : std_logic_vector (6 downto 0);
    variable clk2_lti : std_logic_vector (6 downto 0);
    variable clk3_lti : std_logic_vector (6 downto 0);
    variable clk4_lti : std_logic_vector (6 downto 0);
    variable clk5_lti : std_logic_vector (6 downto 0);
    variable clkfbm1_lti : std_logic_vector (6 downto 0);
    variable clk0_nocnti : std_ulogic;
    variable clk1_nocnti : std_ulogic;
    variable clk2_nocnti : std_ulogic;
    variable clk3_nocnti : std_ulogic;
    variable clk4_nocnti : std_ulogic;
    variable clk5_nocnti : std_ulogic;
    variable clkfbm1_nocnti : std_ulogic;
    variable clk0_edgei  : std_ulogic;
    variable clk1_edgei  : std_ulogic;
    variable clk2_edgei  : std_ulogic;
    variable clk3_edgei  : std_ulogic;
    variable clk4_edgei  : std_ulogic;
    variable clk5_edgei  : std_ulogic;
    variable clkfbm1_edgei  : std_ulogic;
    variable clkout0_dlyi : std_logic_vector (5 downto 0);
    variable clkout1_dlyi : std_logic_vector (5 downto 0);
    variable clkout2_dlyi : std_logic_vector (5 downto 0);
    variable clkout3_dlyi : std_logic_vector (5 downto 0);
    variable clkout4_dlyi : std_logic_vector (5 downto 0);
    variable clkout5_dlyi : std_logic_vector (5 downto 0);
    variable clkfbm1_dlyi : std_logic_vector (5 downto 0);
    variable clk0pm_seli : std_logic_vector (2 downto 0);
    variable clk1pm_seli : std_logic_vector (2 downto 0);
    variable clk2pm_seli : std_logic_vector (2 downto 0);
    variable clk3pm_seli : std_logic_vector (2 downto 0);
    variable clk4pm_seli : std_logic_vector (2 downto 0);
    variable clk5pm_seli : std_logic_vector (2 downto 0);
    variable clkfbm1pm_seli : std_logic_vector (2 downto 0);
    variable clk_ht1 : integer;
    variable clk_div : integer;
    variable  clk_div1 : integer;
    variable clkind_hti : std_logic_vector (6 downto 0);
    variable clkind_lti : std_logic_vector (6 downto 0);
    variable clkind_nocnti : std_ulogic;
    variable clkind_edgei : std_ulogic;
    variable pll_cp : std_logic_vector (3 downto 0);
    variable pll_res : std_logic_vector (3 downto 0);
    variable pll_lfhf : std_logic_vector (1 downto 0);
    variable pll_cpres : std_logic_vector (1 downto 0) := "01";
    variable tmpadd : std_logic_vector (4 downto 0);
  begin

   if (first_time = true) then
   clk_out_para_cal (clk_ht, clk_lt, clk_nocnt, clk_edge, CLKOUT0_DIVIDE, CLKOUT0_DUTY_CYCLE);
   clk0_hti := clk_ht;
   clk0_lti := clk_lt;
   clk0_nocnti := clk_nocnt;
   clk0_edgei := clk_edge;
   clk0_ht <= clk0_hti;
   clk0_lt <= clk0_lti;
   clk0_nocnt <= clk0_nocnti;
   clk0_edge <= clk0_edgei;

   clk_out_para_cal (clk_ht, clk_lt, clk_nocnt, clk_edge, CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE);
   clk1_hti := clk_ht;
   clk1_lti := clk_lt;
   clk1_nocnti := clk_nocnt;
   clk1_edgei := clk_edge;
   clk1_ht <= clk1_hti;
   clk1_lt <= clk1_lti;
   clk1_nocnt <= clk1_nocnti;
   clk1_edge <= clk1_edgei;

   clk_out_para_cal (clk_ht, clk_lt, clk_nocnt, clk_edge, CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE);
   clk2_hti := clk_ht;
   clk2_lti := clk_lt;
   clk2_nocnti := clk_nocnt;
   clk2_edgei := clk_edge;
   clk2_ht <= clk2_hti;
   clk2_lt <= clk2_lti;
   clk2_nocnt <= clk2_nocnti;
   clk2_edge <= clk2_edgei;

   clk_out_para_cal (clk_ht, clk_lt, clk_nocnt, clk_edge, CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE);
   clk3_hti := clk_ht;
   clk3_lti := clk_lt;
   clk3_nocnti := clk_nocnt;
   clk3_edgei := clk_edge;
   clk3_ht <= clk3_hti;
   clk3_lt <= clk3_lti;
   clk3_nocnt <= clk3_nocnti;
   clk3_edge <= clk3_edgei;

   clk_out_para_cal (clk_ht, clk_lt, clk_nocnt, clk_edge, CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE);
   clk4_hti := clk_ht;
   clk4_lti := clk_lt;
   clk4_nocnti := clk_nocnt;
   clk4_edgei := clk_edge;
   clk4_ht <= clk4_hti;
   clk4_lt <= clk4_lti;
   clk4_nocnt <= clk4_nocnti;
   clk4_edge <= clk4_edgei;

   clk_out_para_cal (clk_ht, clk_lt, clk_nocnt, clk_edge, CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE);
   clk5_hti := clk_ht;
   clk5_lti := clk_lt;
   clk5_nocnti := clk_nocnt;
   clk5_edgei := clk_edge;
   clk5_ht <= clk5_hti;
   clk5_lt <= clk5_lti;
   clk5_nocnt <= clk5_nocnti;
   clk5_edge <= clk5_edgei;

   clk_out_para_cal (clk_ht, clk_lt, clk_nocnt, clk_edge, CLKFBOUT_MULT, 0.50);
   clkfbm1_hti := clk_ht;
   clkfbm1_lti := clk_lt;
   clkfbm1_nocnti := clk_nocnt;
   clkfbm1_edgei := clk_edge;
   clkfbm1_ht <= clkfbm1_hti;
   clkfbm1_lt <= clkfbm1_lti;
   clkfbm1_nocnt <= clkfbm1_nocnti;
   clkfbm1_edge <= clkfbm1_edgei;

   clk_out_para_cal (clk_ht, clk_lt, clk_nocnt, clk_edge, DIVCLK_DIVIDE, 0.50);
   clkind_hti := clk_ht;
   clkind_lti := clk_lt;
   clkind_nocnti := clk_nocnt;
   clkind_edgei := clk_edge;
   clkind_ht <= clkind_hti;
   clkind_lt <= clkind_lti;

   clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk0_hti, clk0_lti, clk0_nocnti, clk0_edgei);
   clk0_ht1 <= clk_ht1;
   clk0_div <= clk_div;
   clk0_div1 <= clk_div1;
   clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk1_hti, clk1_lti, clk1_nocnti, clk1_edgei);
   clk1_ht1 <= clk_ht1;
   clk1_div <= clk_div;
   clk1_div1 <= clk_div1;
   clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk2_hti, clk2_lti, clk2_nocnti, clk2_edgei);
   clk2_ht1 <= clk_ht1;
   clk2_div <= clk_div;
   clk2_div1 <= clk_div1;
   clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk3_hti, clk3_lti, clk3_nocnti, clk3_edgei);
   clk3_ht1 <= clk_ht1;
   clk3_div <= clk_div;
   clk3_div1 <= clk_div1;
   clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk4_hti, clk4_lti, clk4_nocnti, clk4_edgei);
   clk4_ht1 <= clk_ht1;
   clk4_div <= clk_div;
   clk4_div1 <= clk_div1;
   clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk5_hti, clk5_lti, clk5_nocnti, clk5_edgei);
   clk5_ht1 <= clk_ht1;
   clk5_div <= clk_div;
   clk5_div1 <= clk_div1;
   clkout_pm_cal(clk_ht1, clk_div, clk_div1, clkfbm1_hti, clkfbm1_lti, clkfbm1_nocnti, clkfbm1_edgei);
   clkfbm1_ht1 <= clk_ht1;
   clkfbm1_div <= clk_div;
   clkfbm1_div1 <= clk_div1;
   clkout_pm_cal(clk_ht1, clk_div, clk_div1, clkind_hti, clkind_lti, clkind_nocnti, '0');
   clkind_div <= clk_div;

   clkout_dly_cal (clkout_dly, clkpm_sel, CLKOUT0_DIVIDE, CLKOUT0_PHASE, "CLKOUT0_PHASE");
   clkout0_dly <= SLV_TO_INT(clkout_dly);
   clk0pm_sel <= SLV_TO_INT(clkpm_sel);
   clkout0_dlyi := clkout_dly;
   clk0pm_seli := clkpm_sel;
   
   clkout_dly_cal (clkout_dly, clkpm_sel, CLKOUT1_DIVIDE, CLKOUT1_PHASE, "CLKOUT1_PHASE");
   clkout1_dly <= SLV_TO_INT(clkout_dly);
   clk1pm_sel <= SLV_TO_INT(clkpm_sel);
   clkout1_dlyi := clkout_dly;
   clk1pm_seli := clkpm_sel;

   clkout_dly_cal (clkout_dly, clkpm_sel, CLKOUT2_DIVIDE, CLKOUT2_PHASE, "CLKOUT2_PHASE");
   clkout2_dly <= SLV_TO_INT(clkout_dly);
   clk2pm_sel <= SLV_TO_INT(clkpm_sel);
   clkout2_dlyi := clkout_dly;
   clk2pm_seli := clkpm_sel;
   clkout_dly_cal (clkout_dly, clkpm_sel, CLKOUT3_DIVIDE, CLKOUT3_PHASE, "CLKOUT3_PHASE");
   clkout3_dly <= SLV_TO_INT(clkout_dly);
   clk3pm_sel <= SLV_TO_INT(clkpm_sel);
   clkout3_dlyi := clkout_dly;
   clk3pm_seli := clkpm_sel;
   clkout_dly_cal (clkout_dly, clkpm_sel, CLKOUT4_DIVIDE, CLKOUT4_PHASE, "CLKOUT4_PHASE");
   clkout4_dly <= SLV_TO_INT(clkout_dly);
   clk4pm_sel <= SLV_TO_INT(clkpm_sel);
   clkout4_dlyi := clkout_dly;
   clk4pm_seli := clkpm_sel;
   clkout_dly_cal (clkout_dly, clkpm_sel, CLKOUT5_DIVIDE, CLKOUT5_PHASE, "CLKOUT5_PHASE");
   clkout5_dly <= SLV_TO_INT(clkout_dly);
   clk5pm_sel <= SLV_TO_INT(clkpm_sel);
   clkout5_dlyi := clkout_dly;
   clk5pm_seli := clkpm_sel;
   clkout_dly_cal (clkout_dly, clkpm_sel, CLKFBOUT_MULT, CLKFBOUT_PHASE, "CLKFBOUT_PHASE");
   clkfbm1_dly <= SLV_TO_INT(clkout_dly);
   clkfbm1pm_sel <= SLV_TO_INT(clkpm_sel);
   clkfbm1_dlyi := clkout_dly;
   clkfbm1pm_seli := clkpm_sel;
   
   case CLKFBOUT_MULT is
when  1   =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1101"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0101"; pll_res := "1111"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0101"; pll_res := "1111"; pll_lfhf := "11"; end if;
when  2   =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1110"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "1111"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1110"; pll_res := "1111"; pll_lfhf := "11"; end if;
when  3   =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0110"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "0111"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0110"; pll_res := "0101"; pll_lfhf := "11"; end if;
when  4   =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1010"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1101"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0111"; pll_res := "1001"; pll_lfhf := "11"; end if;
when  5   =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "0101"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1101"; pll_res := "1001"; pll_lfhf := "11"; end if;
when  6   =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "0101"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0111"; pll_res := "0001"; pll_lfhf := "11"; end if;
when  7   =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1001"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1100"; pll_res := "0001"; pll_lfhf := "11"; end if;
when  8   =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0010"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1110"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1111"; pll_res := "1110"; pll_lfhf := "11"; end if;
when  9   =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0010"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1110"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1110"; pll_res := "0001"; pll_lfhf := "11"; end if;
when  10  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "0001"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1111"; pll_res := "0001"; pll_lfhf := "11"; end if;
when  11  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "0001"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1101"; pll_res := "0110"; pll_lfhf := "11"; end if;
when  12  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "0110"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1110"; pll_res := "0110"; pll_lfhf := "11"; end if;
when  13  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "0110"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1110"; pll_res := "0110"; pll_lfhf := "11"; end if;
when  14  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "0110"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1111"; pll_res := "0110"; pll_lfhf := "11"; end if;
when  15  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "1010"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1110"; pll_res := "1010"; pll_lfhf := "11"; end if;
when  16  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "1010"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1110"; pll_res := "1010"; pll_lfhf := "11"; end if;
when  17  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1010"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1111"; pll_res := "1010"; pll_lfhf := "11"; end if;
when  18  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1010"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1111"; pll_res := "1010"; pll_lfhf := "11"; end if;
when  19  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1010"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1111"; pll_res := "1010"; pll_lfhf := "11"; end if;when  20  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1010"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1100"; pll_res := "1100"; pll_lfhf := "11"; end if;
when  21  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1010"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1100"; pll_res := "1100"; pll_lfhf := "11"; end if;
when  22  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1101"; pll_res := "1100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1101"; pll_res := "1100"; pll_lfhf := "11"; end if;
when  23  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1101"; pll_res := "1100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1101"; pll_res := "1100"; pll_lfhf := "11"; end if;
when  24  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1101"; pll_res := "1100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0111"; pll_res := "0010"; pll_lfhf := "11"; end if;
when  25  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "1100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1110"; pll_res := "1100"; pll_lfhf := "11"; end if;
when  26  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "1100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1110"; pll_res := "1100"; pll_lfhf := "11"; end if;
when  27  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1111"; pll_res := "1100"; pll_lfhf := "11"; end if;
when  28  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "1100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1100"; pll_res := "0010"; pll_lfhf := "11"; end if;
when  29  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "1100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1100"; pll_res := "0010"; pll_lfhf := "11"; end if;
when  30  =>    if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "1100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1100"; pll_res := "0010"; pll_lfhf := "11"; end if;
when  31  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1100"; pll_res := "0010"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1100"; pll_res := "0010"; pll_lfhf := "11"; end if;
when  32  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1100"; pll_res := "0010"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1100"; pll_res := "0010"; pll_lfhf := "11"; end if;
when  33  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1010"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11"; end if;
when  34  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0111"; pll_res := "0010"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11"; end if;
when  35  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0111"; pll_res := "0010"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11"; end if;
when  36  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0111"; pll_res := "0010"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11"; end if;
when  37  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0110"; pll_res := "0010"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11"; end if;
when  38  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0110"; pll_res := "0010"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11"; end if;when  39  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11"; end if;
when  40  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0011"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  41  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0011"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  42  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0011"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  43  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0011"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  44  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0011"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  45  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0011"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0011"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  46  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0011"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0011"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  47  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0101"; pll_res := "0010"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  48  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0101"; pll_res := "0010"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  49  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0011"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  50  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0011"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  51  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0011"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  52  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0011"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  53  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0011"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  54  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0011"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  55  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0011"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0011"; pll_res := "0100"; pll_lfhf := "11"; end if;
when  56  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0011"; pll_res := "0100"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0011"; pll_res := "0100"; pll_lfhf := "11"; end if;
when  57  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if;when  58  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  59  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  60  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  61  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  62  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  63  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if;
when  64  =>    if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "HIGH") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11";
 elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if;
when others => NULL;
  end case;

   tmpx := ('X' & 'X' & 'X' & 'X' & 'X' & 'X' & 'X' & 'X' );
   tmpadd := "11100";
   address := slv_to_int(tmpadd);
   dr_sram(address) <= (tmpx(7 downto 0) & clk0_edgei & clk0_nocnti & clkout0_dlyi(5 downto 0));
   tmpadd := "11011";
   address := slv_to_int(tmpadd);
   dr_sram(address) <= (clk0pm_seli(2 downto 0) & '1' & clk0_hti(5 downto 0) & clk0_lti(5 downto 0));
   tmpadd := "11010";
   address := slv_to_int(tmpadd);
   dr_sram(address) <= (tmpx(7 downto 0) & clk1_edgei & clk1_nocnti & clkout1_dlyi(5 downto 0));
   tmpadd := "11001";
   address := slv_to_int(tmpadd);
   dr_sram(address) <= (clk1pm_seli(2 downto 0) & '1' & clk1_hti(5 downto 0) & clk1_lti(5 downto 0));
   tmpadd := "10111";
   address := slv_to_int(tmpadd);
   dr_sram(address) <= (tmpx(7 downto 0) & clk2_edgei & clk2_nocnti & clkout2_dlyi(5 downto 0));
   tmpadd := "10110";
   address := slv_to_int(tmpadd);
   dr_sram(address) <= (clk2pm_seli(2 downto 0) & '1' & clk2_hti(5 downto 0) & clk2_lti(5 downto 0));
   tmpadd := "10101";
   address := slv_to_int(tmpadd);
   dr_sram(address) <= (tmpx(7 downto 0) & clk3_edgei & clk3_nocnti & clkout3_dlyi(5 downto 0));
   tmpadd := "10100";
   address := slv_to_int(tmpadd);
   dr_sram(address) <= (clk3pm_seli(2 downto 0) & '1' & clk3_hti(5 downto 0) & clk3_lti(5 downto 0));
   tmpadd := "10011";
   address := slv_to_int(tmpadd);
   dr_sram(address) <= (tmpx(7 downto 0) & clk4_edgei & clk4_nocnti & clkout4_dlyi(5 downto 0));
   tmpadd := "10010";
   address := slv_to_int(tmpadd);
   dr_sram(address) <= (clk4pm_seli(2 downto 0) & '1' & clk4_hti(5 downto 0) & clk4_lti(5 downto 0));
   tmpadd := "01111";
   address := slv_to_int(tmpadd);
   dr_sram(address) <= (tmpx(7 downto 0) & clk5_edgei & clk5_nocnti & clkout5_dlyi(5 downto 0));
   tmpadd := "01110";
   address := slv_to_int(tmpadd);
   dr_sram(address) <= (clk5pm_seli(2 downto 0) & '1' & clk5_hti(5 downto 0) & clk5_lti(5 downto 0));
   tmpadd := "01101";
   address := slv_to_int(tmpadd);
   dr_sram(address) <= (tmpx(7 downto 0) & clkfbm1_edgei & clkfbm1_nocnti & clkfbm1_dlyi(5 downto 0));
   tmpadd := "01100";
   address := slv_to_int(tmpadd);
   dr_sram(address) <= (clkfbm1pm_seli(2 downto 0) & '1' & clkfbm1_hti(5 downto 0) & clkfbm1_lti(5 downto 0));
   tmpadd := "00110";
   address := slv_to_int(tmpadd);
   dr_sram(address) <= (tmpx(1 downto 0) & clkind_edgei & clkind_nocnti & clkind_hti(5 downto 0) & clkind_lti(5 downto 0));
   tmpadd := "00001";
   address := slv_to_int(tmpadd);
   dr_sram(address) <= (tmpx(7 downto 0) & pll_lfhf & pll_cpres & pll_cp);
   tmpadd := "00000";
   address := slv_to_int(tmpadd);
   dr_sram(address) <= (tmpx(5 downto 0) & pll_res & tmpx(5 downto 0));

   first_time := false;

   end if;


    if (GSR = '1') then
       drp_lock <= '0';
    elsif (rising_edge(dclk_in)) then 
    if (den_in = '1') then
       valid_daddr := addr_is_valid(daddr_in);
       if (valid_daddr) then
         address := slv_to_int(daddr_in);
         daddr_in_lat <= address;
       end if;

        if (drp_lock = '1') then
          assert false report " Warning : DEN is high at PLL_ADV before DRDY high . Need wait for DRDY signal before next read/write operation through DRP. " severity  warning;
        else 
          drp_lock <= '1';
        end if;

        if (valid_daddr and ( address = 6  or address = 0 or address = 1 or ((address >= 12 and 
                                  address <= 28) and address /= 16 and address /= 17 and
                                  address /= 24))) then
              else 
      Write ( Message, string'(" Warning :  Address DADDR="));
      Write ( Message,  address);
      Write ( Message, string'(" on the PLL_ADV instance is unsupported") );
      Write ( Message, '.' & LF );
      assert false report Message.all severity warning;
      DEALLOCATE (Message);
             end if;

        if (dwe_in = '1')  then
          if (rst_input = '1') then
             if (valid_daddr and ( address = 6  or address = 0 or address = 1 or ((address >= 12 and 
                                  address <= 28) and address /= 16 and address /= 17 and
                                  address /= 24))) then
                  dr_sram(address) <= di_in;
                  di_str := SLV_TO_STR(di_in);
             end if;

             if (daddr_in = "11100") then
                 daddr_str := "11100";
                 clkout_delay_para_drp (clkout_dly, clk_nocnt, clk_edge, di_in, daddr_in, di_str, daddr_str);
                 clkout0_dly <= SLV_TO_INT(clkout_dly);
                 clk0_nocnt <= clk_nocnt;
                 clk0_nocnti := clk_nocnt;
                 clk0_edgei := clk_edge;
                 clk0_edge <= clk_edge;
             end if;

             if (daddr_in = "11011") then
                daddr_str := "11011";
                 clkout_hl_para_drp (clk_lt, clk_ht, clkpm_sel, di_in, daddr_in, di_str, daddr_str);
                 clk0_lt <= clk_lt;
                 clk0_ht <= clk_ht;
                 clk0_lti := clk_lt;
                 clk0_hti := clk_ht;
                 clk0pm_sel <=  SLV_TO_INT(clkpm_sel);
             end if;

             if (daddr_in = "11010") then
                 daddr_str := "11010";
                 clkout_delay_para_drp (clkout_dly, clk_nocnt, clk_edge, di_in, daddr_in, di_str, daddr_str);
                 clkout1_dly <= SLV_TO_INT(clkout_dly);
                 clk1_nocnt <= clk_nocnt;
                 clk1_nocnti := clk_nocnt;
                 clk1_edgei := clk_edge;
                 clk1_edge <= clk_edge;
             end if;


             if (daddr_in = "11001") then
                 daddr_str := "11001";
                 clkout_hl_para_drp (clk_lt, clk_ht, clkpm_sel, di_in, daddr_in, di_str, daddr_str);
                 clk1_lt <= clk_lt;
                 clk1_ht <= clk_ht;
                 clk1_lti := clk_lt;
                 clk1_hti := clk_ht;
                 clk1pm_sel <=  SLV_TO_INT(clkpm_sel);
             end if;

             if (daddr_in = "10111") then
                 daddr_str := "10111";
                 clkout_delay_para_drp (clkout_dly, clk_nocnt, clk_edge, di_in, daddr_in, di_str, daddr_str);
                 clkout2_dly <= SLV_TO_INT(clkout_dly);
                 clk2_nocnt <= clk_nocnt;
                 clk2_nocnti := clk_nocnt;
                 clk2_edgei := clk_edge;
                 clk2_edge <= clk_edge;
             end if;

             if (daddr_in = "10110") then
                 daddr_str := "10110";
                 clkout_hl_para_drp (clk_lt, clk_ht, clkpm_sel, di_in, daddr_in, di_str, daddr_str);
                 clk2_lt <= clk_lt;
                 clk2_ht <= clk_ht;
                 clk2_lti := clk_lt;
                 clk2_hti := clk_ht;
                 clk2pm_sel <=  SLV_TO_INT(clkpm_sel);
             end if;

             if (daddr_in = "10101") then
                 daddr_str := "10101";
                 clkout_delay_para_drp (clkout_dly, clk_nocnt, clk_edge, di_in, daddr_in, di_str, daddr_str);
                 clkout3_dly <= SLV_TO_INT(clkout_dly);
                 clk3_nocnt <= clk_nocnt;
                 clk3_nocnti := clk_nocnt;
                 clk3_edgei := clk_edge;
                 clk3_edge <= clk_edge;
             end if;

             if (daddr_in = "10100") then
                 daddr_str := "10100";
                 clkout_hl_para_drp (clk_lt, clk_ht, clkpm_sel, di_in, daddr_in, di_str, daddr_str);
                 clk3_lt <= clk_lt;
                 clk3_ht <= clk_ht;
                 clk3_lti := clk_lt;
                 clk3_hti := clk_ht;
                 clk3pm_sel <=  SLV_TO_INT(clkpm_sel);
             end if;

             if (daddr_in = "10011") then
                 daddr_str := "10011";
                 clkout_delay_para_drp (clkout_dly, clk_nocnt, clk_edge, di_in, daddr_in, di_str, daddr_str);
                 clkout4_dly <= SLV_TO_INT(clkout_dly);
                 clk4_nocnt <= clk_nocnt;
                 clk4_nocnti := clk_nocnt;
                 clk4_edgei := clk_edge;
                 clk4_edge <= clk_edge;
             end if;

             if (daddr_in = "10010") then
                 daddr_str := "10010";
                 clkout_hl_para_drp (clk_lt, clk_ht, clkpm_sel, di_in, daddr_in, di_str, daddr_str);
                 clk4_lt <= clk_lt;
                 clk4_ht <= clk_ht;
                 clk4_lti := clk_lt;
                 clk4_hti := clk_ht;
                 clk4pm_sel <=  SLV_TO_INT(clkpm_sel);
             end if;

             if (daddr_in = "01111") then
                 daddr_str := "01111";
                 clkout_delay_para_drp (clkout_dly, clk_nocnt, clk_edge, di_in, daddr_in, di_str, daddr_str);
                 clkout5_dly <= SLV_TO_INT(clkout_dly);
                 clk5_nocnt <= clk_nocnt;
                 clk5_nocnti := clk_nocnt;
                 clk5_edgei := clk_edge;
                 clk5_edge <= clk_edge;
             end if;

             if (daddr_in = "01110") then
                 daddr_str := "01110";
                 clkout_hl_para_drp (clk_lt, clk_ht, clkpm_sel, di_in, daddr_in, di_str, daddr_str);
                 clk5_lt <= clk_lt;
                 clk5_lti := clk_lt;
                 clk5_ht <= clk_ht;
                 clk5_hti := clk_ht;
                 clk5pm_sel <=  SLV_TO_INT(clkpm_sel);
             end if;

             if (daddr_in = "01101") then
                 daddr_str := "01101";
                 clkout_delay_para_drp (clkout_dly, clk_nocnt, clk_edge, di_in, daddr_in, di_str, daddr_str);
                 clkfbm1_dly <= SLV_TO_INT(clkout_dly);
                 clkfbm1_nocnt <= clk_nocnt;
                 clkfbm1_nocnti := clk_nocnt;
                 clkfbm1_edge <= clk_edge;
                 clkfbm1_edgei := clk_edge;
             end if;

             if (daddr_in = "01100") then
                 daddr_str := "01100";
                 clkout_hl_para_drp (clk_lt, clk_ht, clkpm_sel, di_in, daddr_in, di_str, daddr_str);
                 clkfbm1_lt <= clk_lt;
                 clkfbm1_lti := clk_lt;
                 clkfbm1_ht <= clk_ht;
                 clkfbm1_hti := clk_ht;
                 clkfbm1pm_sel <=  SLV_TO_INT(clkpm_sel);
             end if;

             if (daddr_in = "00110") then
                 clkind_lti := ('0' & di_in(11 downto 6));
                 clkind_hti := ('0' & di_in(5 downto 0));
                 clkind_lt <= clkind_lti;
                 clkind_ht <= clkind_hti;
                 clkind_nocnti := di_in(12);
                 clkind_edgei := di_in(13);
              end if;

   clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk0_hti, clk0_lti, clk0_nocnti, clk0_edgei);
   clk0_ht1 <= clk_ht1;
   clk0_div <= clk_div;
   clk0_div1 <= clk_div1;
   clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk1_hti, clk1_lti, clk1_nocnti, clk1_edgei);
   clk1_ht1 <= clk_ht1;
   clk1_div <= clk_div;
   clk1_div1 <= clk_div1;
   clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk2_hti, clk2_lti, clk2_nocnti, clk2_edgei);
   clk2_ht1 <= clk_ht1;
   clk2_div <= clk_div;
   clk2_div1 <= clk_div1;
   clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk3_hti, clk3_lti, clk3_nocnti, clk3_edgei);
   clk3_ht1 <= clk_ht1;
   clk3_div <= clk_div;
   clk3_div1 <= clk_div1;
   clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk4_hti, clk4_lti, clk4_nocnti, clk4_edgei);
   clk4_ht1 <= clk_ht1;
   clk4_div <= clk_div;
   clk4_div1 <= clk_div1;
   clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk5_hti, clk5_lti, clk5_nocnti, clk5_edgei);
   clk5_ht1 <= clk_ht1;
   clk5_div <= clk_div;
   clk5_div1 <= clk_div1;
   clkout_pm_cal(clk_ht1, clk_div, clk_div1, clkfbm1_hti, clkfbm1_lti, clkfbm1_nocnti, clkfbm1_edgei);
   clkfbm1_ht1 <= clk_ht1;
   clkfbm1_div <= clk_div;
   clkfbm1_div1 <= clk_div1;
   clkout_pm_cal(clk_ht1, clk_div, clk_div1, clkind_hti, clkind_lti, clkind_nocnti, '0');
   clkind_div <= clk_div;
   if (clk_div > 52 or (clk_div < 1 and clkind_nocnti = '0')) then
     assert false report " Input Error : The sum of DI[11:6] and DI[5:0] Address DADDR=00110 is input clock divider of PLL_ADV and over the 1 to 52 range." severity error;
   end if;

          else 
                 assert false report " Error : RST is low at PLL_ADV. RST need to be high when change X_PLL_ADV paramters through DRP. " severity error;
          end if; -- end rst

        end if; --DWE
    end if;  --DEN

    if ( drp_lock = '1') then
          drp_lock <= '0';
          drp_lock1 <= '1';
    end if;
    if (drp_lock1 = '1') then
         drp_lock1 <= '0';
         drdy_out <= '1';
    end if;
    if (drdy_out = '1') then
        drdy_out <= '0';
    end if;
 end if; -- end GSR

  wait on dclk_in, GSR;

end process;


   CLOCK_PERIOD_P : process (clkpll, rst_in)
      variable  clkin_edge_previous : time := 0 ps;
      variable  clkin_edge_current : time := 0 ps;
   begin
     if (rst_in = '1') then
        clkin_period(0) <= period_vco_target;
        clkin_period(1) <= period_vco_target;
        clkin_period(2) <= period_vco_target;
        clkin_period(3) <= period_vco_target;
        clkin_period(4) <= period_vco_target;
        clkin_jit <= 0 ps;
        clkin_lock_cnt <= 0;
        pll_locked_tm <= '0';
        pll_locked_tmp1 <= '0';
        lock_period <= '0';
        clkout_en0_tmp <= '0';
        unlock_recover <= '0';
        clkin_edge_previous := 0 ps;
     elsif (rising_edge(clkpll)) then
       clkin_edge_current := NOW;
       clkin_period(4) <= clkin_period(3);
       clkin_period(3) <= clkin_period(2);
       clkin_period(2) <= clkin_period(1);
       clkin_period(1) <= clkin_period(0);
       if (clkin_edge_previous /= 0 ps and  clkin_stopped_p = '0' and clkin_stopped_n = '0') then
          clkin_period(0) <= clkin_edge_current - clkin_edge_previous;
       end if;

       if (pll_unlock = '0') then
          clkin_jit <=  clkin_edge_current - clkin_edge_previous - clkin_period(0);
       else
          clkin_jit <= 0 ps;
       end if;

          clkin_edge_previous := clkin_edge_current;

      if ( pll_unlock = '0' and  (clkin_lock_cnt < lock_cnt_max) and fb_delay_found = '1' ) then
            clkin_lock_cnt <= clkin_lock_cnt + 1;
      elsif (pll_unlock = '1' and rst_on_loss = '0' and pll_locked_tmp1 = '1' ) then
            clkin_lock_cnt <= locked_en_time;
            unlock_recover <= '1';
      end if;

      if ( clkin_lock_cnt >= PLL_LOCK_TIME and pll_unlock = '0') then
        pll_locked_tm <= '1';
      end if;

      if ( clkin_lock_cnt = 6 ) then
        lock_period <= '1';
      end if;

      if (clkin_lock_cnt >= clkout_en_time) then
          clkout_en0_tmp <= '1';
      end if;
 
      if (clkin_lock_cnt >= locked_en_time) then
          pll_locked_tmp1 <= '1';
      end if;

      if (unlock_recover = '1' and clkin_lock_cnt  >= lock_cnt_max) then
          unlock_recover <= '0';
      end if;

    end if;
   end process;

   CLKOUT_EN_P : process 
   begin
      if (clkout_en0_tmp = '0') then
         clkout_en0 <= '0';
      else
        wait until (falling_edge(clkpll));
         clkout_en0 <= clkout_en0_tmp after (clkin_period(0)/2.0);
      end if;
     wait on clkout_en0_tmp;
   end process;

   PLL_LOCK_P1 : process (pll_locked_tmp1, rst_in)
   begin
     if (rst_in = '1') then
         pll_locked_tmp2 <= '0';
     elsif (pll_locked_tmp1 = '0') then
         pll_locked_tmp2 <=  pll_locked_tmp1;
     else 
--          wait until (rising_edge(clkvco));
          pll_locked_tmp2 <= pll_locked_tmp1 after pll_locked_delay;
     end if;
   end process;

   locked_out <= '1' when pll_locked_tm = '1' and pll_locked_tmp2 ='1' and pll_unlock = '0'
                         and unlock_recover = '0' else '0';

   CLOCK_PERIOD_AVG_P : process (clkin_period(0), clkin_period(1), clkin_period(2),
                                 clkin_period(3), clkin_period(4), period_avg)
      variable period_avg_tmp : time := 0.000 ps;
      variable clkin_period_tmp0 : time := 0.000 ps;
   begin
      clkin_period_tmp0 := clkin_period(0);
     if (clkin_period_tmp0 /= period_avg) then
         period_avg_tmp := (clkin_period(0) + clkin_period(1) + clkin_period(2)
                       + clkin_period(3) + clkin_period(4))/5.0;
         period_avg <= period_avg_tmp;
     end if;
   end process;

   CLOCK_PERIOD_UPDATE_P : process (period_avg, clkind_div, clkfbm1_div)
      variable period_fb_tmp : time;
      variable period_vco_tmp : time;
      variable tmpreal : real;
      variable tmpreal1: real;
      variable period_vco_rm_tmp : integer;
      variable period_vco_rm_tmp1 : integer;
   begin
       md_product <= clkfbm1_div * clkind_div;
       m_product <= clkfbm1_div;
       m_product2 <= clkfbm1_div / 2;
       period_fb_tmp :=  clkind_div * period_avg;
       period_vco_tmp := period_fb_tmp / clkfbm1_div;
       period_vco_rm_tmp1 := period_fb_tmp / 1 ps;
       period_vco_rm_tmp := period_vco_rm_tmp1 mod clkfbm1_div;
       period_vco_rm <= period_vco_rm_tmp;
   if (period_vco_rm > 1) then
      if (period_vco_rm > m_product2)  then
          period_vco_cmp_cnt <= (m_product / (m_product - period_vco_rm)) - 1;
          period_vco_cmp_flag <= 2;
      else 
         period_vco_cmp_cnt <= (m_product / period_vco_rm) - 1;
         period_vco_cmp_flag <= 1;
      end if;
   else 
      period_vco_cmp_cnt <= 0;
      period_vco_cmp_flag <= 0;
   end if;

       period_vco_half <= period_vco_tmp /2;
       period_vco_half1 <= ((period_vco_tmp /2) / 1 ps + 1) * 1 ps;
       period_vco_half_rm <= period_vco_tmp - (period_vco_tmp /2);
       pll_locked_delay <= period_fb_tmp * clkfbm1_div;
       clkin_dly_t <=  period_avg * clkind_div + period_avg * 1.25;
       clkfb_dly_t <= period_fb_tmp * 2.25; 
       period_fb <= period_fb_tmp;
       period_vco <= period_vco_tmp;
       period_vco1 <= period_vco_tmp / 8.0;
       period_vco2 <= period_vco_tmp / 4.0;
       period_vco3 <= period_vco_tmp * 3.0 / 8.0;
       period_vco4 <= period_vco_tmp / 2.0;
       period_vco5 <= period_vco_tmp * 5.0 / 8.0;
       period_vco6 <= period_vco_tmp * 3.0 / 4.0;
       period_vco7 <= period_vco_tmp * 7.0 / 8.0;
   end process;

   clkvco_lk_rst <=  '1' when ( rst_in = '1' or  pll_unlock = '1' or  pll_locked_tm = '0') else '0';

   CLKVCO_LK_P : process
       variable clkvco_rm_cnt : integer;
   begin
   if ( clkvco_lk_rst = '1') then
        clkvco_lk <= '0';
   else
     if (rising_edge(clkpll)) then
       if (pll_locked_tm = '1') then
          clkvco_lk <= '1';
          clkvco_rm_cnt := 0;
       if ( period_vco_cmp_flag = 1) then
          for I in 2 to m_product loop
               wait for (period_vco_half);
               clkvco_lk <=  '0';  
               if ( clkvco_rm_cnt = 1) then
                   wait for (period_vco_half1);
                   clkvco_lk <=  '1';  
               else
                   wait for (period_vco_half_rm);
                   clkvco_lk <=  '1';  
               end if;

               if ( clkvco_rm_cnt = period_vco_cmp_cnt) then
                  clkvco_rm_cnt := 0;
               else
                   clkvco_rm_cnt := clkvco_rm_cnt + 1;
               end if;
          end loop;
       elsif ( period_vco_cmp_flag = 2) then
          for I in 2 to m_product loop
               wait for (period_vco_half);
               clkvco_lk <=  '0';
               if ( clkvco_rm_cnt = 1) then
                   wait for (period_vco_half_rm);
                   clkvco_lk <=  '1';
               else
                   wait for (period_vco_half1);
                   clkvco_lk <=  '1';
               end if;

               if ( clkvco_rm_cnt = period_vco_cmp_cnt) then
                  clkvco_rm_cnt := 0;
               else
                   clkvco_rm_cnt := clkvco_rm_cnt + 1;
               end if;
          end loop;
       else
          for I in 2 to md_product loop
           wait for (period_vco_half);
           clkvco_lk <=  '0';

           wait for (period_vco_half_rm);
           clkvco_lk <=  '1';
          end loop;
       end if;
       wait for (period_vco_half);
       clkvco_lk <= '0';
      end if;
     end if;
   end if;
   wait on clkpll, rst_in ,  pll_unlock;
  end process;

  CLKVCO_DLY_CAL_P : process ( period_vco, fb_delay, clkfbm1_dly, clkfbm1pm_rl)
    variable val_tmp : integer;
    variable val_tmp2 : integer;
    variable val_tmp3 : integer;
    variable fbm1_comp_delay : integer;
    variable fbm1_comp_delay_rl : real;
    variable period_vco_i : integer;
    variable period_vco_rl : real;
    variable dly_tmp : integer;
    variable tmp_rl : real;
  begin
   if (fb_delay /= 0 ps and period_vco /= 0 ps) then
    period_vco_i := period_vco * 1 / 1 ps;
    period_vco_rl := int2real(period_vco_i);
    tmp_rl := int2real(clkfbm1_dly);
    val_tmp := period_vco_i * md_product;
    fbm1_comp_delay_rl := period_vco_rl *(tmp_rl  + clkfbm1pm_rl );
    fbm1_comp_delay := real2int(fbm1_comp_delay_rl);
    val_tmp2 := fb_delay * 1 / 1 ps;
    dly_tmp := val_tmp2 + fbm1_comp_delay;
    if ( dly_tmp < val_tmp) then
       clkvco_delay <= (val_tmp - dly_tmp) * 1 ps;
    else
       clkvco_delay <=  (val_tmp - dly_tmp mod val_tmp) * 1 ps;
    end if;
   end if;
  end process;

  CLKFB_PS_P : process (clkfbm1pm_sel)
  begin
    case (clkfbm1pm_sel) is
       when 0 => clkfbm1pm_rl <= 0.0;
       when 1 => clkfbm1pm_rl <= 0.125;
       when 2 => clkfbm1pm_rl <= 0.25;
       when 3 => clkfbm1pm_rl <= 0.375;
       when 4 => clkfbm1pm_rl <= 0.50;
       when 5 => clkfbm1pm_rl <= 0.625;
       when 6 => clkfbm1pm_rl <= 0.75;
       when 7 => clkfbm1pm_rl <= 0.875;
       when others => clkfbm1pm_rl <= 0.0;
    end case;
   end process;

   CLKVCO_FREE_P : process 
   begin
      if (pmcd_mode /= '1' and pll_locked_tm = '0') then
          wait for period_vco_target_half;
          clkvco_free <= not clkvco_free;
      end if;
      wait on clkvco_free;
   end process;
  
   CLKVCO_GEN_P : process ( pll_locked_tm, clkvco_lk, clkvco_free)
   begin
     if (pll_locked_tm = '1') then
          clkvco <= transport clkvco_lk after clkvco_delay;
     else
          clkvco <= transport clkvco_free after clkvco_delay;
     end if;
   end process;

   clkout_en <=  clkout_en0 after clkvco_delay;


  CLKOUT_MUX_P : process (clkvco, clkout_en, rst_in) 
  begin
   if (rst_in = '1') then
       clkout_mux <= "00000000";
   elsif (clkout_en = '1') then
       clkout_mux(0) <= clkvco;
       clkout_mux(1) <= transport clkvco after (period_vco1);
       clkout_mux(2) <= transport clkvco after (period_vco2);
       clkout_mux(3) <= transport clkvco after (period_vco3);
       clkout_mux(4) <= transport clkvco after (period_vco4);
       clkout_mux(5) <= transport clkvco after (period_vco5);
       clkout_mux(6) <= transport clkvco after (period_vco6);
       clkout_mux(7) <= transport clkvco after (period_vco7);
  end if;
  end process;

   clk0in <= clkout_mux(clk0pm_sel);
   clk1in <= clkout_mux(clk1pm_sel);
   clk2in <= clkout_mux(clk2pm_sel);
   clk3in <= clkout_mux(clk3pm_sel);
   clk4in <= clkout_mux(clk4pm_sel);
   clk5in <= clkout_mux(clk5pm_sel);
   clkfbm1in <= clkout_mux(clkfbm1pm_sel);

   clk0ps_en <= clkout_en when clk0_dly_cnt = clkout0_dly else '0';
   clk1ps_en <= clkout_en when clk1_dly_cnt = clkout1_dly else '0';
   clk2ps_en <= clkout_en when clk2_dly_cnt = clkout2_dly else '0';
   clk3ps_en <= clkout_en when clk3_dly_cnt = clkout3_dly else '0';
   clk4ps_en <= clkout_en when clk4_dly_cnt = clkout4_dly else '0';
   clk5ps_en <= clkout_en when clk5_dly_cnt = clkout5_dly else '0';
   clkfbm1ps_en <= clkout_en when clkfbm1_dly_cnt = clkfbm1_dly else '0';

   CLK_DLY_CNT_P : process(clk0in, clk1in, clk2in, clk3in, clk4in, clk5in, clkfbm1in,
                    rst_in)
   begin
     if (rst_in = '1') then
         clk0_dly_cnt <= 0;
         clk1_dly_cnt <= 0;
         clk2_dly_cnt <= 0;
         clk3_dly_cnt <= 0;
         clk4_dly_cnt <= 0;
         clk5_dly_cnt <= 0;
         clkfbm1_dly_cnt <= 0;
     else
       if (falling_edge(clk0in)) then
          if ((clk0_dly_cnt < clkout0_dly) and clkout_en = '1') then
            clk0_dly_cnt <= clk0_dly_cnt + 1;
          end if;
        end if;

       if (falling_edge(clk1in)) then
          if ((clk1_dly_cnt < clkout1_dly) and clkout_en = '1') then
            clk1_dly_cnt <= clk1_dly_cnt + 1;
          end if;
        end if;

       if (falling_edge(clk2in)) then
          if ((clk2_dly_cnt < clkout2_dly) and clkout_en = '1') then
            clk2_dly_cnt <= clk2_dly_cnt + 1;
          end if;
        end if;

       if (falling_edge(clk3in)) then
          if ((clk3_dly_cnt < clkout3_dly) and clkout_en = '1') then
            clk3_dly_cnt <= clk3_dly_cnt + 1;
          end if;
        end if;

       if (falling_edge(clk4in)) then
         if ((clk4_dly_cnt < clkout4_dly) and clkout_en = '1') then
            clk4_dly_cnt <= clk4_dly_cnt + 1;
         end if;
        end if;

       if (falling_edge(clk5in)) then
          if ((clk5_dly_cnt < clkout5_dly) and clkout_en = '1') then
            clk5_dly_cnt <= clk5_dly_cnt + 1;
          end if;
        end if;

       if (falling_edge(clkfbm1in)) then
          if ((clkfbm1_dly_cnt < clkfbm1_dly) and clkout_en = '1') then
            clkfbm1_dly_cnt <= clkfbm1_dly_cnt + 1;
          end if;
        end if;

    end if;
   end process;


   CLK0_GEN_P : process (clk0in, rst_in)
   begin
     if (rst_in = '1') then
         clk0_cnt <= 0;
         clk0_out <= '0';
     else
        if (rising_edge(clk0in) or falling_edge(clk0in)) then
            if (clk0ps_en = '1') then

              if (clk0_cnt < clk0_div1) then
                      clk0_cnt <= clk0_cnt + 1;
               else
                      clk0_cnt <= 0;
               end if;

               if  (clk0_cnt < clk0_ht1) then
                     clk0_out <= '1';
               else
                     clk0_out <= '0';
               end if;
          else
             clk0_out <= '0';
             clk0_cnt <= 0;
          end if;
        end if;
    end if;
   end process;
              
   CLK1_GEN_P : process (clk1in, rst_in)
   begin
     if (rst_in = '1') then
         clk1_cnt <= 0;
         clk1_out <= '0';
     else
        if (rising_edge(clk1in)  or falling_edge(clk1in)) then
            if (clk1ps_en = '1') then
              if (clk1_cnt < clk1_div1) then
                      clk1_cnt <= clk1_cnt + 1;
               else
                      clk1_cnt <= 0;
               end if;

               if  (clk1_cnt < clk1_ht1) then
                     clk1_out <= '1';
               else
                     clk1_out <= '0';
               end if;
          else
             clk1_out <= '0';
             clk1_cnt <= 0;
          end if;
        end if;
    end if;
   end process;


   CLK2_GEN_P : process (clk2in, rst_in)
   begin
     if (rst_in = '1') then
         clk2_cnt <= 0;
         clk2_out <= '0';
     else
        if (rising_edge(clk2in)  or falling_edge(clk2in)) then
            if (clk2ps_en = '1') then
              if (clk2_cnt < clk2_div1) then
                      clk2_cnt <= clk2_cnt + 1;
               else
                      clk2_cnt <= 0;
               end if;

               if  (clk2_cnt < clk2_ht1) then
                     clk2_out <= '1';
               else
                     clk2_out <= '0';
               end if;
          else
             clk2_out <= '0';
             clk2_cnt <= 0;
          end if;
        end if;
    end if;
   end process;


   CLK3_GEN_P : process (clk3in, rst_in)
   begin
     if (rst_in = '1') then
         clk3_cnt <= 0;
         clk3_out <= '0';
     else
        if (rising_edge(clk3in)  or falling_edge(clk3in)) then
            if (clk3ps_en = '1') then
               if  (clk3_cnt < clk3_ht1) then
                     clk3_out <= '1';
               else
                     clk3_out <= '0';
               end if;

              if (clk3_cnt < clk3_div1) then
                      clk3_cnt <= clk3_cnt + 1;
               else
                      clk3_cnt <= 0;
               end if;
          else
             clk3_out <= '0';
             clk3_cnt <= 0;
          end if;
        end if;
    end if;
   end process;


   CLK4_GEN_P : process (clk4in, rst_in)
   begin
     if (rst_in = '1') then
         clk4_cnt <= 0;
         clk4_out <= '0';
     else
        if (rising_edge(clk4in)  or falling_edge(clk4in)) then
            if (clk4ps_en = '1') then
              if (clk4_cnt < clk4_div1) then
                      clk4_cnt <= clk4_cnt + 1;
               else
                      clk4_cnt <= 0;
               end if;

               if  (clk4_cnt < clk4_ht1) then
                     clk4_out <= '1';
               else
                     clk4_out <= '0';
               end if;
          else
             clk4_out <= '0';
             clk4_cnt <= 0;
          end if;
        end if;
    end if;
   end process;


   CLK5_GEN_P : process (clk5in, rst_in)
   begin
     if (rst_in = '1') then
         clk5_cnt <= 0;
         clk5_out <= '0';
     else
        if (rising_edge(clk5in)  or falling_edge(clk5in)) then
            if (clk5ps_en = '1') then
              if (clk5_cnt < clk5_div1) then
                      clk5_cnt <= clk5_cnt + 1;
               else
                      clk5_cnt <= 0;
               end if;

               if  (clk5_cnt < clk5_ht1) then
                     clk5_out <= '1';
               else
                     clk5_out <= '0';
               end if;
          else
             clk5_out <= '0';
             clk5_cnt <= 0;
          end if;
        end if;
    end if;
   end process;


   CLKFB_GEN_P : process (clkfbm1in, rst_in)
   begin
     if (rst_in = '1') then
         clkfbm1_cnt <= 0;
         clkfbm1_out <= '0';
     else
        if (rising_edge(clkfbm1in)  or falling_edge(clkfbm1in)) then
            if (clkfbm1ps_en = '1') then
              if (clkfbm1_cnt < clkfbm1_div1) then
                      clkfbm1_cnt <= clkfbm1_cnt + 1;
               else
                      clkfbm1_cnt <= 0;
               end if;

               if  (clkfbm1_cnt < clkfbm1_ht1) then
                     clkfbm1_out <= '1';
               else
                     clkfbm1_out <= '0';
               end if;
          else
             clkfbm1_out <= '0';
             clkfbm1_cnt <= 0;
          end if;
        end if;
    end if;
   end process;

              
    clkout0_out <= transport clk0_out  when fb_delay_found = '1' else clkfb_tst;
    clkout1_out <= transport clk1_out  when fb_delay_found = '1' else clkfb_tst;
    clkout2_out <= transport clk2_out  when fb_delay_found = '1' else clkfb_tst;
    clkout3_out <= transport clk3_out  when fb_delay_found = '1' else clkfb_tst;
    clkout4_out <= transport clk4_out  when fb_delay_found = '1' else clkfb_tst;
    clkout5_out <= transport clk5_out  when fb_delay_found = '1' else clkfb_tst;
    clkfb_out <= transport clkfbm1_out  when fb_delay_found = '1' else clkfb_tst;

--
-- determine feedback delay
--

  CLKFB_TST_P : process (clkpll, rst_in1)
  begin
  if (rst_in1 = '1') then
       clkfb_tst <= '0';
  elsif (rising_edge(clkpll)) then
    if (fb_delay_found_tmp = '0' and GSR = '0') then
       clkfb_tst <=   '1';
     else
       clkfb_tst <=   '0';
    end if;
  end if;
  end process;

  FB_DELAY_CAL_P0 : process (clkfb_tst, rst_in1)
  begin
     if (rst_in1 = '1')  then
         delay_edge <= 0 ps;
     elsif (rising_edge(clkfb_tst)) then
        delay_edge <= NOW;
     end if;
  end process;

  FB_DELAY_CAL_P : process (clkfb_in, rst_in1)
      variable delay_edge1 : time := 0 ps;
      variable fb_delay_tmp : time := 0 ps;
      variable Message : line;
  begin
  if (rst_in1 = '1')  then
    fb_delay  <= 0 ps;
    fb_delay_found_tmp <= '0';
    delay_edge1 := 0 ps;
    fb_delay_tmp := 0 ps;
  elsif (clkfb_in'event and clkfb_in = '1') then
     if (fb_delay_found_tmp = '0') then
         if (delay_edge /= 0 ps) then
           delay_edge1 := NOW;
           fb_delay_tmp := delay_edge1 - delay_edge;
         else
           fb_delay_tmp := 0 ps;
        end if;
        fb_delay <= fb_delay_tmp;
        fb_delay_found_tmp <= '1';
        if (rst_in1 = '0' and fb_delay_tmp > fb_delay_max) then
            Write ( Message, string'(" Warning : The feedback delay is "));
            Write ( Message, fb_delay_tmp);
            Write ( Message, string'(". It is over the maximun value "));
            Write ( Message, fb_delay_max);
            Write ( Message, '.' & LF );
            assert false report Message.all severity warning;
            DEALLOCATE (Message);
         end if;
    end if;
  end if;
  end process;

   fb_delay_found <= fb_delay_found_tmp after clkvco_delay when rst_in1 = '0' else '0';

--
-- generate unlock signal
--

  clkpll_dly <= transport clkpll after clkin_dly_t;
  clkfb_in_dly <= transport clkfb_in after clkfb_dly_t when (pmcd_mode /= '1') else '0';

  CLKINSTOP_CNT_P : process (clkpll_dly,  clkpll, rst_in)
  begin

  if (rst_in = '1' or clkpll = '0') then
      clkstop_cnt_p <= 0;
      clkin_stopped_p <= '0';
  elsif ( rising_edge (clkpll_dly) ) then
   if (fb_delay_found = '1' and pll_locked_tmp2 = '1') then
      if (clkpll_jitter_unlock = '0' and clkpll = '1') then
         clkstop_cnt_p <=  clkstop_cnt_p + 1;
      else
         clkstop_cnt_p <= 0;
      end if;
      
      if (clkstop_cnt_p > clkin_stop_max) then
         clkin_stopped_p <= '1';
      else
         clkin_stopped_p <= '0';
      end if;
   else    
      clkstop_cnt_p <= 0;
      clkin_stopped_p <= '0';
   end if;
  end if;
  end process;

  CLKINSTOP_CNT_N : process (clkpll_dly,  clkpll, rst_in)
  begin

  if (rst_in = '1' or clkpll = '1') then
      clkstop_cnt_n <= 0;
      clkin_stopped_n <= '0';
  elsif ( rising_edge (clkpll_dly) ) then
   if (fb_delay_found = '1' and pll_locked_tmp2 = '1') then
      if (clkpll_jitter_unlock = '0' and clkpll = '0') then
         clkstop_cnt_n <=  clkstop_cnt_n + 1;
      else
         clkstop_cnt_n <= 0;
      end if;
      
      if (clkstop_cnt_n > clkin_stop_max) then
         clkin_stopped_n <= '1';
      else
         clkin_stopped_n <= '0';
      end if;
   else
      clkstop_cnt_n <= 0;
      clkin_stopped_n <= '0';
   end if;
  end if;
  end process;    

  CLKFBSTOP_CNT_PROC : process (clkfb_in_dly,  clkfb_in, rst_in)
  begin
  if (rst_in = '1' or clkfb_in = '0') then
      clkfbstop_cnt_p <= 0;
      clkfb_stopped_p <= '0';
  elsif ( rising_edge (clkfb_in_dly) ) then
   if (fb_delay_found = '1' and pll_locked_tmp2 = '1') then
      if (clkpll_jitter_unlock = '0' and clkfb_in = '1') then
         clkfbstop_cnt_p <=  clkfbstop_cnt_p + 1;
      else
         clkfbstop_cnt_p <= 0;
      end if;

      if (clkfbstop_cnt_p > clkfb_stop_max) then
         clkfb_stopped_p <= '1';
      else
         clkfb_stopped_p <= '0';
      end if;
   else
      clkfbstop_cnt_p <= 0;
      clkfb_stopped_p <= '0';
   end if;
  end if;
  end process;

  CLKFBSTOP_CNT_N_PROC : process (clkfb_in_dly,  clkfb_in, rst_in)
  begin

  if (rst_in = '1' or clkfb_in = '1') then
      clkfbstop_cnt_n <= 0;
      clkfb_stopped_n <= '0';
  elsif ( rising_edge (clkfb_in_dly) ) then
   if (fb_delay_found = '1' and pll_locked_tmp2 = '1') then
      if (clkpll_jitter_unlock = '0' and clkfb_in = '0') then
         clkfbstop_cnt_n <=  clkfbstop_cnt_n + 1;
      else
         clkfbstop_cnt_n <= 0;
      end if;

      if (clkfbstop_cnt_n > clkfb_stop_max) then
         clkfb_stopped_n <= '1';
      else
         clkfb_stopped_n <= '0';
      end if;
   else
      clkfbstop_cnt_n <= 0;
      clkfb_stopped_n <= '0';
   end if;
  end if;
  end process;

  CLK_JITTER_P : process (clkin_jit, rst_in)
  begin
  if (rst_in = '1') then
      clkpll_jitter_unlock <= '0';
  else
   if ( locked_out = '1' and clkfb_stopped = '0' and clkin_stopped = '0') then
      if  (ABS(clkin_jit) > ref_jitter_max_tmp) then
        clkpll_jitter_unlock <= '1';
      else
         clkpll_jitter_unlock <= '0';
      end if;
   else
         clkpll_jitter_unlock <= '0';
   end if;
  end if;
  end process;
     
   clkin_stopped <= '1' when (clkin_stopped_p = '1' or clkin_stopped_n = '1') else '0';
   clkfb_stopped <= '1' when (clkfb_stopped_p = '1' or clkfb_stopped_n = '1') else '0';

   pll_unlock <= clkin_stopped or clkfb_stopped or clkpll_jitter_unlock;

  

end PLL_ADV_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/pll_base.vhd,v 1.3 2006/01/07 00:13:03 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                 Phase Lock Loop Clock 
-- /___/   /\     Filename : PLL_BASE.vhd
-- \   \  /  \    Timestamp : 
--  \___\/\___\
-- Revision:
--    12/02/05 - Initial version.
-- End Revision


----- CELL PLL_BASE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_SIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;

library unisim;
use unisim.vpkg.all;
use unisim.VCOMPONENTS.all;

entity PLL_BASE is
generic (
		BANDWIDTH : string := "OPTIMIZED";
		CLKFBOUT_MULT : integer := 1;
		CLKFBOUT_PHASE : real := 0.0;
		CLKIN_PERIOD : real := 0.000;
		CLKOUT0_DIVIDE : integer := 1;
		CLKOUT0_DUTY_CYCLE : real := 0.5;
		CLKOUT0_PHASE : real := 0.0;
		CLKOUT1_DIVIDE : integer := 1;
		CLKOUT1_DUTY_CYCLE : real := 0.5;
		CLKOUT1_PHASE : real := 0.0;
		CLKOUT2_DIVIDE : integer := 1;
		CLKOUT2_DUTY_CYCLE : real := 0.5;
		CLKOUT2_PHASE : real := 0.0;
		CLKOUT3_DIVIDE : integer := 1;
		CLKOUT3_DUTY_CYCLE : real := 0.5;
		CLKOUT3_PHASE : real := 0.0;
		CLKOUT4_DIVIDE : integer := 1;
		CLKOUT4_DUTY_CYCLE : real := 0.5;
		CLKOUT4_PHASE : real := 0.0;
		CLKOUT5_DIVIDE : integer := 1;
		CLKOUT5_DUTY_CYCLE : real := 0.5;
		CLKOUT5_PHASE : real := 0.0;
		COMPENSATION : string := "SYSTEM_SYNCHRONOUS";
                DIVCLK_DIVIDE : integer := 1;
		REF_JITTER : real := 0.100;
		RESET_ON_LOSS_OF_LOCK : boolean := FALSE


  );

port (
		CLKFBOUT : out std_ulogic;
		CLKOUT0 : out std_ulogic;
		CLKOUT1 : out std_ulogic;
		CLKOUT2 : out std_ulogic;
		CLKOUT3 : out std_ulogic;
		CLKOUT4 : out std_ulogic;
		CLKOUT5 : out std_ulogic;
		LOCKED : out std_ulogic;

		CLKFBIN : in std_ulogic;
		CLKIN : in std_ulogic;
		RST : in std_ulogic
     );
end PLL_BASE;

-- Architecture body --

architecture PLL_BASE_V of PLL_BASE is

signal  h1 : std_ulogic := '1';
signal  z1 : std_ulogic := '0';
signal  z5 : std_logic_vector(4 downto 0) := "00000";
signal  z16 : std_logic_vector(15 downto 0) := "0000000000000000";
signal  OPEN0 : std_ulogic;
signal  OPEN1 : std_ulogic;
signal  OPEN2 : std_ulogic;
signal  OPEN3 : std_ulogic;
signal  OPEN4 : std_ulogic;
signal  OPEN5 : std_ulogic;
signal  OPEN6 : std_ulogic;
signal  OPEN7 : std_ulogic;
signal  OPEN16 : std_logic_vector(15 downto 0);

begin
-- PLL_ADV Instantiation (port map, generic map)

PLL_ADV_inst : PLL_ADV
	generic map (
		BANDWIDTH => BANDWIDTH,
		CLKFBOUT_MULT => CLKFBOUT_MULT,
		CLKFBOUT_PHASE => CLKFBOUT_PHASE,
		CLKIN1_PERIOD => CLKIN_PERIOD,
		CLKIN2_PERIOD => 10.0,
		CLKOUT0_DIVIDE => CLKOUT0_DIVIDE,
		CLKOUT0_DUTY_CYCLE => CLKOUT0_DUTY_CYCLE,
		CLKOUT0_PHASE => CLKOUT0_PHASE,
		CLKOUT1_DIVIDE => CLKOUT1_DIVIDE,
		CLKOUT1_DUTY_CYCLE => CLKOUT1_DUTY_CYCLE,
		CLKOUT1_PHASE => CLKOUT1_PHASE,
		CLKOUT2_DIVIDE => CLKOUT2_DIVIDE,
		CLKOUT2_DUTY_CYCLE => CLKOUT2_DUTY_CYCLE,
		CLKOUT2_PHASE => CLKOUT2_PHASE,
		CLKOUT3_DIVIDE => CLKOUT3_DIVIDE,
		CLKOUT3_DUTY_CYCLE => CLKOUT3_DUTY_CYCLE,
		CLKOUT3_PHASE => CLKOUT3_PHASE,
		CLKOUT4_DIVIDE => CLKOUT4_DIVIDE,
		CLKOUT4_DUTY_CYCLE => CLKOUT4_DUTY_CYCLE,
		CLKOUT4_PHASE => CLKOUT4_PHASE,
		CLKOUT5_DIVIDE => CLKOUT5_DIVIDE,
		CLKOUT5_DUTY_CYCLE => CLKOUT5_DUTY_CYCLE,
		CLKOUT5_PHASE => CLKOUT5_PHASE,
		COMPENSATION => COMPENSATION,
                DIVCLK_DIVIDE => DIVCLK_DIVIDE,
                EN_REL => FALSE,
                PLL_PMCD_MODE => FALSE,
		REF_JITTER => REF_JITTER,
		RESET_ON_LOSS_OF_LOCK => RESET_ON_LOSS_OF_LOCK, 
                RST_DEASSERT_CLK => "CLKIN1"
)
port map (
		CLKFBDCM => OPEN6,
		CLKFBOUT => CLKFBOUT,
		CLKOUT0 => CLKOUT0,
		CLKOUT1 => CLKOUT1,
		CLKOUT2 => CLKOUT2,
		CLKOUT3 => CLKOUT3,
		CLKOUT4 => CLKOUT4,
		CLKOUT5 => CLKOUT5,
		CLKOUTDCM0 => OPEN0,
		CLKOUTDCM1 => OPEN1,
		CLKOUTDCM2 => OPEN2,
		CLKOUTDCM3 => OPEN3,
		CLKOUTDCM4 => OPEN4,
		CLKOUTDCM5 => OPEN5,
		DO => OPEN16,
		DRDY => OPEN7,
		LOCKED => LOCKED,
		CLKFBIN => CLKFBIN,
		CLKIN1 => CLKIN,
		CLKIN2 => z1,
                CLKINSEL => h1,
                DADDR => z5,
                DCLK => z1,
                DEN => z1,
                DI => z16,
                DWE => z1,
                REL => z1,
		RST => RST
);

end PLL_BASE_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/ram128x1d.vhd,v 1.3 2005/10/07 18:35:24 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Dual Port Synchronous RAM 128-Deep by 1-Wide
-- /___/   /\     Filename : RAM128X1D.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:49 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/15/05 - Initial version.
--    09/21/05 - Use SLV_TO_INT to decode the address. (CR 217651)
-- End Revision

----- CELL RAM128X1D -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM128X1D is
  generic (
    INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000"
    );

  port (
    DPO : out std_ulogic;
    SPO : out std_ulogic;

    A     : in std_logic_vector(6 downto 0);
    D     : in std_ulogic;
    DPRA  : in std_logic_vector(6 downto 0);
    WCLK  : in std_ulogic;
    WE    : in std_ulogic
    );
end RAM128X1D;

architecture RAM128X1D_V of RAM128X1D is
  signal MEM : std_ulogic_vector( 128 downto 0 ) :=  ('X' & TO_STDULOGICVECTOR(INIT));

begin

  ReadBehavior   : process(A, DPRA, MEM)
    variable Index_SP : integer := 128;
    variable Index_DP : integer := 128;
  begin
    Index_SP := SLV_TO_INT(SLV => A);
    Index_DP := SLV_TO_INT(SLV => DPRA);
    SPO <= MEM(Index_SP);
    DPO <= MEM(Index_DP);      
  end process ReadBehavior;

 WriteBehavior  : process(WCLK)
    variable Index_SP : integer := 128;
  begin
    Index_SP := SLV_TO_INT(SLV => A );
    if ((WE = '1') and (wclk'event) and (wclk'last_value = '0') and (wclk = '1')) then
      MEM(Index_SP) <= D after 100 ps;      
    end if;
  end process WriteBehavior;

end RAM128X1D_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/ram256x1s.vhd,v 1.3 2005/10/07 18:35:24 sranade Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Static Synchronous RAM 256-Deep by 1-Wide
-- /___/   /\     Filename : RAM256X1S.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:49 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/15/05 - Initial version.
--    09/21/05 - Use SLV_TO_INT to decode the address. (CR 217651)
-- End Revision

----- CELL RAM256X1S -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VPKG.all;

entity RAM256X1S is
  generic (
    INIT : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"
    );

  port (
    O : out std_ulogic;

    A     : in std_logic_vector(7 downto 0);
    D     : in std_ulogic;
    WCLK  : in std_ulogic;
    WE    : in std_ulogic
    );
end RAM256X1S;

architecture RAM256X1S_V of RAM256X1S is
  signal MEM : std_ulogic_vector( 256 downto 0 ) :=  ('X' & TO_STDULOGICVECTOR(INIT));

begin

  ReadBehavior  : process(A, MEM)
    variable Index   : integer := 256;

  begin
    Index   := SLV_TO_INT(SLV => A);
    O <= MEM(Index);      
  end process ReadBehavior;

  WriteBehavior : process(WCLK)
    variable Index   : integer := 256;
  begin
    Index                  := SLV_TO_INT(SLV => A);
    if ((WE = '1') and (wclk'event) and (wclk'last_value = '0') and (wclk = '1')) then
        MEM(Index) <= D after 100 ps;
    end if;
  end process WriteBehavior;

end RAM256X1S_V;


-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/ram32m.vhd,v 1.2 2007/02/12 23:25:30 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Function Simulation Library Component
--  /   /                  Static Synchronous RAM 32-Deep by 8-Wide
-- /___/   /\     Filename : RAM32M.vhd
-- \   \  /  \    Timestamp : 
--  \___\/\___\
--
-- Revision:
--    03/23/06 - Initial version.
--    02/12/07 - Change MEM_a in QB_P process to MEM_b (CR 434008)
-- End Revision

----- CELL RAM32M -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity RAM32M is
  generic (
      INIT_A : bit_vector(63 downto 0) := X"0000000000000000";
      INIT_B : bit_vector(63 downto 0) := X"0000000000000000";
      INIT_C : bit_vector(63 downto 0) := X"0000000000000000";
      INIT_D : bit_vector(63 downto 0) := X"0000000000000000"
    );

  port (
    DOA    : out std_logic_vector (1 downto 0);
    DOB    : out std_logic_vector (1 downto 0);
    DOC    : out std_logic_vector (1 downto 0);
    DOD    : out std_logic_vector (1 downto 0);

    ADDRA : in  std_logic_vector(4 downto 0);
    ADDRB : in  std_logic_vector(4 downto 0);
    ADDRC : in  std_logic_vector(4 downto 0);
    ADDRD : in  std_logic_vector(4 downto 0);
    DIA   : in  std_logic_vector (1 downto 0);
    DIB   : in  std_logic_vector (1 downto 0);
    DIC   : in  std_logic_vector (1 downto 0);
    DID   : in  std_logic_vector (1 downto 0);
    WCLK  : in  std_ulogic;
    WE   : in  std_ulogic
    );
end RAM32M;

architecture RAM32M_V of RAM32M is

  signal MEM_a : std_logic_vector( 65 downto 0 ) := ("XX" & To_StdLogicVector(INIT_A) );
  signal MEM_b : std_logic_vector( 65 downto 0 ) := ("XX" & To_StdLogicVector(INIT_B) );
  signal MEM_c : std_logic_vector( 65 downto 0 ) := ("XX" & To_StdLogicVector(INIT_C) );
  signal MEM_d : std_logic_vector( 65 downto 0 ) := ("XX" & To_StdLogicVector(INIT_D) );
begin

  QA_P : process ( ADDRA, MEM_a) 
    variable Index_a : integer := 32;
  begin
    Index_a := 2 * SLV_TO_INT(SLV => ADDRA);
    DOA(0) <= MEM_a(Index_a);
    DOA(1) <= MEM_a(Index_a + 1);
  end process QA_P;

  QB_P : process ( ADDRB, MEM_b) 
    variable Index_b : integer := 32;
  begin
    Index_b := 2 * SLV_TO_INT(SLV => ADDRB);
    DOB(0) <= MEM_b(Index_b);
    DOB(1) <= MEM_b(Index_b + 1);
  end process QB_P;

  QC_P : process ( ADDRC, MEM_c) 
    variable Index_c : integer := 32;
  begin
    Index_c := 2 * SLV_TO_INT(SLV => ADDRC);
    DOC(0) <= MEM_c(Index_c);
    DOC(1) <= MEM_c(Index_c + 1);
  end process QC_P;

  QD_P : process ( ADDRD, MEM_d) 
    variable Index_d : integer := 32;
  begin
    Index_d := 2 * SLV_TO_INT(SLV => ADDRD);
    DOD(0) <= MEM_d(Index_d);
    DOD(1) <= MEM_d(Index_d + 1);
  end process QD_P;

  VITALWriteBehavior : process(WCLK)
    variable Index   : integer := 32 ;
  begin
    if (rising_edge(WCLK)) then
      if (WE = '1') then
        Index                  := 2 * SLV_TO_INT(SLV => ADDRD);
        MEM_a(Index) <= DIA(0)  after 100 ps;
        MEM_a(Index+1) <= DIA(1) after 100 ps;
        MEM_b(Index) <= DIB(0)  after 100 ps;
        MEM_b(Index+1) <= DIB(1) after 100 ps;
        MEM_c(Index) <= DIC(0)  after 100 ps;
        MEM_c(Index+1) <= DIC(1) after 100 ps;
        MEM_d(Index) <= DID(0)  after 100 ps;
        MEM_d(Index+1) <= DID(1)  after 100 ps;
      end if;
    end if;
  end process VITALWriteBehavior;

end RAM32M_V;

-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/ram64m.vhd,v 1.1 2006/03/28 22:24:21 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Function Simulation Library Component
--  /   /                  Static Synchronous RAM 64-Deep by 4-Wide
-- /___/   /\     Filename : RAM64M.vhd
-- \   \  /  \    Timestamp : 
--  \___\/\___\
--
-- Revision:
--    03/23/06 - Initial version.
-- End Revision

----- CELL RAM64M -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity RAM64M is
  generic (
      INIT_A : bit_vector(63 downto 0) := X"0000000000000000";
      INIT_B : bit_vector(63 downto 0) := X"0000000000000000";
      INIT_C : bit_vector(63 downto 0) := X"0000000000000000";
      INIT_D : bit_vector(63 downto 0) := X"0000000000000000"
    );

  port (
    DOA    : out std_ulogic;
    DOB    : out std_ulogic;
    DOC    : out std_ulogic;
    DOD    : out std_ulogic;

    ADDRA : in  std_logic_vector(5 downto 0);
    ADDRB : in  std_logic_vector(5 downto 0);
    ADDRC : in  std_logic_vector(5 downto 0);
    ADDRD : in  std_logic_vector(5 downto 0);
    DIA   : in  std_ulogic;
    DIB   : in  std_ulogic;
    DIC   : in  std_ulogic;
    DID   : in  std_ulogic;
    WCLK  : in  std_ulogic;
    WE   : in  std_ulogic
    );
end RAM64M;

architecture RAM64M_V of RAM64M is

  signal MEM_a : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT_A) );
  signal MEM_b : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT_B) );
  signal MEM_c : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT_C) );
  signal MEM_d : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT_D) );
begin

   DOA   <= MEM_a(SLV_TO_INT(SLV => ADDRA));
   DOB   <= MEM_b(SLV_TO_INT(SLV => ADDRB));
   DOC   <= MEM_c(SLV_TO_INT(SLV => ADDRC));
   DOD   <= MEM_d(SLV_TO_INT(SLV => ADDRD));

  VITALWriteBehavior : process(WCLK)
    variable Index   : integer := 64 ;
  begin
    if (rising_edge(WCLK)) then
      if (WE = '1') then
        Index                  := SLV_TO_INT(SLV => ADDRD);
        MEM_a(Index) <= DIA  after 100 ps;
        MEM_b(Index) <= DIB  after 100 ps;
        MEM_c(Index) <= DIC  after 100 ps;
        MEM_d(Index) <= DID  after 100 ps;
      end if;
    end if;
  end process VITALWriteBehavior;

end RAM64M_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/ramb18sdp.vhd,v 1.12 2007/06/15 21:01:09 wloo Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2005 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB18SDP.vhd
-- \   \  /  \    Timestamp : Tues October 18 16:43:59 PST 2005
--  \___\/\___\
--
-- Revision:
--    10/18/05 - Initial version.
--    01/04/07 - Added support of memory file to initialize memory and parity (CR 431584).
--    03/14/07 - Removed attribute INITP_FILE (CR 436003).
--    04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812).
--    06/14/07 - Implemented high performace version of the model.
-- End Revision

----- CELL RAMB18SDP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity RAMB18SDP is
generic (
  
    DO_REG : integer := 0;
    INIT : bit_vector := X"000000000";
    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_FILE : string := "NONE";
    SIM_COLLISION_CHECK : string := "ALL";
    SIM_MODE : string := "SAFE";
    SRVAL : bit_vector := X"000000000"
    
  );

port (

    DO : out std_logic_vector(31 downto 0);
    DOP : out std_logic_vector(3 downto 0);
    
    DI : in std_logic_vector(31 downto 0);
    DIP : in std_logic_vector(3 downto 0);
    RDADDR : in std_logic_vector(8 downto 0);
    RDCLK : in std_ulogic;
    RDEN : in std_ulogic;
    REGCE : in std_ulogic;
    SSR : in std_ulogic;
    WE : in std_logic_vector(3 downto 0);
    WRADDR : in std_logic_vector(8 downto 0);
    WRCLK : in std_ulogic;
    WREN : in std_ulogic

  );
end RAMB18SDP;
                                                                        
architecture RAMB18SDP_V of RAMB18SDP is

  component ARAMB36_INTERNAL
	generic
	(
          BRAM_MODE : string := "TRUE_DUAL_PORT";
          BRAM_SIZE : integer := 36;
          DOA_REG : integer := 0;
          DOB_REG : integer := 0;
          INIT_A : bit_vector := X"000000000000000000";
          INIT_B : bit_vector := X"000000000000000000";
          RAM_EXTENSION_A : string := "NONE";
          RAM_EXTENSION_B : string := "NONE";
          READ_WIDTH_A : integer := 0;
          READ_WIDTH_B : integer := 0;
          SIM_COLLISION_CHECK : string := "ALL";
          SIM_MODE : string := "SAFE";
          SRVAL_A : bit_vector := X"000000000000000000";
          SRVAL_B : bit_vector := X"000000000000000000";
          WRITE_MODE_A : string := "WRITE_FIRST";
          WRITE_MODE_B : string := "WRITE_FIRST";
          WRITE_WIDTH_A : integer := 0;
          WRITE_WIDTH_B : integer := 0;
          INIT_FILE : string := "NONE";
          INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
           );
	port
	(
          CASCADEOUTLATA : out std_ulogic;
          CASCADEOUTLATB : out std_ulogic;
          CASCADEOUTREGA : out std_ulogic;
          CASCADEOUTREGB : out std_ulogic;
          DBITERR : out std_ulogic;
          DOA : out std_logic_vector(63 downto 0);
          DOB : out std_logic_vector(63 downto 0);
          DOPA : out std_logic_vector(7 downto 0);
          DOPB : out std_logic_vector(7 downto 0);
          ECCPARITY : out std_logic_vector(7 downto 0);
          SBITERR : out std_ulogic;
    
          ADDRA : in std_logic_vector(15 downto 0);
          ADDRB : in std_logic_vector(15 downto 0);
          CASCADEINLATA : in std_ulogic;
          CASCADEINLATB : in std_ulogic;
          CASCADEINREGA : in std_ulogic;
          CASCADEINREGB : in std_ulogic;
          CLKA : in std_ulogic;
          CLKB : in std_ulogic;
          DIA : in std_logic_vector(63 downto 0);
          DIB : in std_logic_vector(63 downto 0);
          DIPA : in std_logic_vector(7 downto 0);
          DIPB : in std_logic_vector(7 downto 0);
          ENA : in std_ulogic;
          ENB : in std_ulogic;
          REGCEA : in std_ulogic;
          REGCEB : in std_ulogic;
          REGCLKA : in std_ulogic;
          REGCLKB : in std_ulogic;
          SSRA : in std_ulogic;
          SSRB : in std_ulogic;
          WEA : in std_logic_vector(7 downto 0);
          WEB : in std_logic_vector(7 downto 0)
 	);
  end component;

  
  constant SYNC_PATH_DELAY : time := 100 ps;
  signal we_int : std_logic_vector(7 downto 0) := (others => '0');
  signal addra_int : std_logic_vector(15 downto 0) := (others => '0');
  signal addrb_int : std_logic_vector(15 downto 0) := (others => '0');
  signal GND : std_ulogic := '0';
  signal GND_4 : std_logic_vector(3 downto 0) := (others => '0');
  signal GND_8 : std_logic_vector(7 downto 0) := (others => '0');
  signal GND_32 : std_logic_vector(31 downto 0) := (others => '0');
  signal GND_64 : std_logic_vector(63 downto 0) := (others => '0');
  signal OPEN_4 : std_logic_vector(3 downto 0);
  signal OPEN_8 : std_logic_vector(7 downto 0);
  signal OPEN_32 : std_logic_vector(31 downto 0);
  signal OPEN_64 : std_logic_vector(63 downto 0);
  signal do_dly : std_logic_vector(31 downto 0) :=  (others => '0');
  signal dop_dly : std_logic_vector(3 downto 0) :=  (others => '0');
  signal eccparity_dly : std_logic_vector(7 downto 0) :=  (others => '0');
  signal dbiterr_dly : std_ulogic := '0';
  signal sbiterr_dly : std_ulogic := '0';
  
begin
  
   addra_int <= "00" & RDADDR & "00000";
   addrb_int <= "00" & WRADDR & "00000";
   we_int <= WE & WE;
   
-- RAMB18SDP_INTERNAL Instantiation

RAMB18SDP_inst : ARAMB36_INTERNAL
	generic map (

                INIT_00 => INIT_00,
		INIT_01 => INIT_01,
		INIT_02 => INIT_02,
		INIT_03 => INIT_03,
		INIT_04 => INIT_04,
		INIT_05 => INIT_05,
		INIT_06 => INIT_06,
		INIT_07 => INIT_07,
		INIT_08 => INIT_08,
		INIT_09 => INIT_09,
		INIT_0A => INIT_0A,
		INIT_0B => INIT_0B,
		INIT_0C => INIT_0C,
		INIT_0D => INIT_0D,
		INIT_0E => INIT_0E,
		INIT_0F => INIT_0F,
		INIT_10 => INIT_10,
		INIT_11 => INIT_11,
		INIT_12 => INIT_12,
		INIT_13 => INIT_13,
		INIT_14 => INIT_14,
		INIT_15 => INIT_15,
		INIT_16 => INIT_16,
		INIT_17 => INIT_17,
		INIT_18 => INIT_18,
		INIT_19 => INIT_19,
		INIT_1A => INIT_1A,
		INIT_1B => INIT_1B,
		INIT_1C => INIT_1C,
		INIT_1D => INIT_1D,
		INIT_1E => INIT_1E,
		INIT_1F => INIT_1F,
		INIT_20 => INIT_20,
		INIT_21 => INIT_21,
		INIT_22 => INIT_22,
		INIT_23 => INIT_23,
		INIT_24 => INIT_24,
		INIT_25 => INIT_25,
		INIT_26 => INIT_26,
		INIT_27 => INIT_27,
		INIT_28 => INIT_28,
		INIT_29 => INIT_29,
		INIT_2A => INIT_2A,
		INIT_2B => INIT_2B,
		INIT_2C => INIT_2C,
		INIT_2D => INIT_2D,
		INIT_2E => INIT_2E,
		INIT_2F => INIT_2F,
		INIT_30 => INIT_30,
		INIT_31 => INIT_31,
		INIT_32 => INIT_32,
		INIT_33 => INIT_33,
		INIT_34 => INIT_34,
		INIT_35 => INIT_35,
		INIT_36 => INIT_36,
		INIT_37 => INIT_37,
		INIT_38 => INIT_38,
		INIT_39 => INIT_39,
		INIT_3A => INIT_3A,
		INIT_3B => INIT_3B,
		INIT_3C => INIT_3C,
		INIT_3D => INIT_3D,
		INIT_3E => INIT_3E,
		INIT_3F => INIT_3F,
                
		INITP_00 => INITP_00,
		INITP_01 => INITP_01,
		INITP_02 => INITP_02,
		INITP_03 => INITP_03,
		INITP_04 => INITP_04,
		INITP_05 => INITP_05,
		INITP_06 => INITP_06,
		INITP_07 => INITP_07,

		INIT_A  => INIT,
		INIT_B  => INIT,
                INIT_FILE => INIT_FILE,
		SIM_COLLISION_CHECK => SIM_COLLISION_CHECK,
                SIM_MODE => SIM_MODE,
		SRVAL_A => SRVAL,
		SRVAL_B => SRVAL,
		WRITE_MODE_A => "READ_FIRST",
		WRITE_MODE_B => "READ_FIRST",                
                BRAM_MODE => "SIMPLE_DUAL_PORT",
                BRAM_SIZE => 18,
                DOA_REG => DO_REG,
                DOB_REG => DO_REG,
                READ_WIDTH_A => 36,
                READ_WIDTH_B => 36,                
                WRITE_WIDTH_A => 36,
                WRITE_WIDTH_B => 36          
                )
  
        port map (
                ADDRA => addra_int,
                ADDRB => addrb_int,
                CLKA => RDCLK,
                CLKB => WRCLK,
                DIA => GND_64,
                DIB(63 downto 32) => GND_32,
                DIB(31 downto 0) => DI,
                DIPA => GND_8,
                DIPB(7 downto 4) => GND_4,
                DIPB(3 downto 0) => DIP,
                
                ENA => RDEN,
                ENB => WREN,
                SSRA => SSR,
                SSRB => GND,
                WEA => GND_8,
                WEB => we_int,
                DOA(31  downto 0) => do_dly,
                DOA(63 downto 32) => OPEN_32,
                DOB => OPEN_64,
                DOPA(3 downto 0) => dop_dly,
                DOPA(7 downto 4) => OPEN_4,
                DOPB => OPEN_8,
                CASCADEOUTLATA => OPEN,
                CASCADEOUTLATB => OPEN,
                CASCADEOUTREGA => OPEN,
                CASCADEOUTREGB => OPEN,
                CASCADEINLATA => GND,
                CASCADEINLATB => GND,
                CASCADEINREGA => GND,
                CASCADEINREGB => GND,
                REGCLKA => RDCLK,
                REGCLKB => GND,
                REGCEA => REGCE,
                REGCEB => GND,
                DBITERR => OPEN,
                SBITERR => OPEN,
                ECCPARITY => OPEN
        );

   prcs_output_wtiming: process (do_dly, dop_dly)
   begin  -- process prcs_output_wtiming

     DO <= do_dly after SYNC_PATH_DELAY;
     DOP <= dop_dly after SYNC_PATH_DELAY;

   end process prcs_output_wtiming;
     
   
end RAMB18SDP_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/ramb18.vhd,v 1.13 2007/06/15 21:01:09 wloo Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2005 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB18.vhd
-- \   \  /  \    Timestamp : Tues October 18 16:43:59 PST 2005
--  \___\/\___\
--
-- Revision:
--    10/18/05 - Initial version.
--    01/04/07 - Added support of memory file to initialize memory and parity (CR 431584).
--    03/14/07 - Removed attribute INITP_FILE (CR 436003).
--    04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812).
--    06/14/07 - Implemented high performace version of the model.
-- End Revision

----- CELL RAMB18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity RAMB18 is
generic (
  
    DOA_REG : integer := 0;
    DOB_REG : integer := 0;
    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_A : bit_vector := X"00000";
    INIT_B : bit_vector := X"00000";
    INIT_FILE : string := "NONE";
    READ_WIDTH_A : integer := 0;
    READ_WIDTH_B : integer := 0;
    SIM_COLLISION_CHECK : string := "ALL";
    SIM_MODE : string := "SAFE";
    SRVAL_A : bit_vector := X"00000";
    SRVAL_B : bit_vector := X"00000";
    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST";
    WRITE_WIDTH_A : integer := 0;
    WRITE_WIDTH_B : integer := 0
    
  );

port (
  
    DOA : out std_logic_vector(15 downto 0);
    DOB : out std_logic_vector(15 downto 0);
    DOPA : out std_logic_vector(1 downto 0);
    DOPB : out std_logic_vector(1 downto 0);
    
    ADDRA : in std_logic_vector(13 downto 0);
    ADDRB : in std_logic_vector(13 downto 0);
    CLKA : in std_ulogic;
    CLKB : in std_ulogic;
    DIA : in std_logic_vector(15 downto 0);
    DIB : in std_logic_vector(15 downto 0);
    DIPA : in std_logic_vector(1 downto 0);
    DIPB : in std_logic_vector(1 downto 0);
    ENA : in std_ulogic;
    ENB : in std_ulogic;
    REGCEA : in std_ulogic;
    REGCEB : in std_ulogic;
    SSRA : in std_ulogic;
    SSRB : in std_ulogic;
    WEA : in std_logic_vector(1 downto 0);
    WEB : in std_logic_vector(1 downto 0)

  );
end RAMB18;
                                                                        
architecture RAMB18_V of RAMB18 is

  component ARAMB36_INTERNAL
	generic
	(
          BRAM_MODE : string := "TRUE_DUAL_PORT";
          BRAM_SIZE : integer := 36;
          DOA_REG : integer := 0;
          DOB_REG : integer := 0;
          INIT_A : bit_vector := X"000000000000000000";
          INIT_B : bit_vector := X"000000000000000000";
          RAM_EXTENSION_A : string := "NONE";
          RAM_EXTENSION_B : string := "NONE";
          READ_WIDTH_A : integer := 0;
          READ_WIDTH_B : integer := 0;
          SIM_COLLISION_CHECK : string := "ALL";
          SIM_MODE : string := "SAFE";
          SRVAL_A : bit_vector := X"000000000000000000";
          SRVAL_B : bit_vector := X"000000000000000000";
          WRITE_MODE_A : string := "WRITE_FIRST";
          WRITE_MODE_B : string := "WRITE_FIRST";
          WRITE_WIDTH_A : integer := 0;
          WRITE_WIDTH_B : integer := 0;
          INIT_FILE : string := "NONE";
          INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
           );
	port
	(
          CASCADEOUTLATA : out std_ulogic;
          CASCADEOUTLATB : out std_ulogic;
          CASCADEOUTREGA : out std_ulogic;
          CASCADEOUTREGB : out std_ulogic;
          DBITERR : out std_ulogic;
          DOA : out std_logic_vector(63 downto 0);
          DOB : out std_logic_vector(63 downto 0);
          DOPA : out std_logic_vector(7 downto 0);
          DOPB : out std_logic_vector(7 downto 0);
          ECCPARITY : out std_logic_vector(7 downto 0);
          SBITERR : out std_ulogic;
    
          ADDRA : in std_logic_vector(15 downto 0);
          ADDRB : in std_logic_vector(15 downto 0);
          CASCADEINLATA : in std_ulogic;
          CASCADEINLATB : in std_ulogic;
          CASCADEINREGA : in std_ulogic;
          CASCADEINREGB : in std_ulogic;
          CLKA : in std_ulogic;
          CLKB : in std_ulogic;
          DIA : in std_logic_vector(63 downto 0);
          DIB : in std_logic_vector(63 downto 0);
          DIPA : in std_logic_vector(7 downto 0);
          DIPB : in std_logic_vector(7 downto 0);
          ENA : in std_ulogic;
          ENB : in std_ulogic;
          REGCEA : in std_ulogic;
          REGCEB : in std_ulogic;
          REGCLKA : in std_ulogic;
          REGCLKB : in std_ulogic;
          SSRA : in std_ulogic;
          SSRB : in std_ulogic;
          WEA : in std_logic_vector(7 downto 0);
          WEB : in std_logic_vector(7 downto 0)
 	);
  end component;

  constant SYNC_PATH_DELAY : time := 100 ps;    
  signal wea_int : std_logic_vector(7 downto 0) := (others => '0');
  signal web_int : std_logic_vector(7 downto 0) := (others => '0');
  signal addra_int : std_logic_vector(15 downto 0) := (others => '0');
  signal addrb_int : std_logic_vector(15 downto 0) := (others => '0');
  signal GND : std_ulogic := '0';
  signal GND_6 : std_logic_vector(5 downto 0) := (others => '0');
  signal GND_48 : std_logic_vector(47 downto 0) := (others => '0');
  signal OPEN_6 : std_logic_vector(5 downto 0);
  signal OPEN_48 : std_logic_vector(47 downto 0);
  signal doa_dly : std_logic_vector(15 downto 0) :=  (others => '0');
  signal dob_dly : std_logic_vector(15 downto 0) :=  (others => '0');
  signal dopa_dly : std_logic_vector(1 downto 0) :=  (others => '0');
  signal dopb_dly : std_logic_vector(1 downto 0) :=  (others => '0');
  
begin

  addra_int <= "00" & ADDRA;
  addrb_int <= "00" & ADDRB;
  wea_int <= WEA & WEA & WEA & WEA;
  web_int <= WEB & WEB & WEB & WEB;
                     
-- RAMB18_INTERNAL Instantiation

RAMB18_inst : ARAMB36_INTERNAL
	generic map (

                DOA_REG => DOA_REG,
                DOB_REG => DOB_REG,
		INIT_A  => INIT_A,
		INIT_B  => INIT_B,
                INIT_FILE => INIT_FILE,
                
		INIT_00 => INIT_00,
		INIT_01 => INIT_01,
		INIT_02 => INIT_02,
		INIT_03 => INIT_03,
		INIT_04 => INIT_04,
		INIT_05 => INIT_05,
		INIT_06 => INIT_06,
		INIT_07 => INIT_07,
		INIT_08 => INIT_08,
		INIT_09 => INIT_09,
		INIT_0A => INIT_0A,
		INIT_0B => INIT_0B,
		INIT_0C => INIT_0C,
		INIT_0D => INIT_0D,
		INIT_0E => INIT_0E,
		INIT_0F => INIT_0F,
		INIT_10 => INIT_10,
		INIT_11 => INIT_11,
		INIT_12 => INIT_12,
		INIT_13 => INIT_13,
		INIT_14 => INIT_14,
		INIT_15 => INIT_15,
		INIT_16 => INIT_16,
		INIT_17 => INIT_17,
		INIT_18 => INIT_18,
		INIT_19 => INIT_19,
		INIT_1A => INIT_1A,
		INIT_1B => INIT_1B,
		INIT_1C => INIT_1C,
		INIT_1D => INIT_1D,
		INIT_1E => INIT_1E,
		INIT_1F => INIT_1F,
		INIT_20 => INIT_20,
		INIT_21 => INIT_21,
		INIT_22 => INIT_22,
		INIT_23 => INIT_23,
		INIT_24 => INIT_24,
		INIT_25 => INIT_25,
		INIT_26 => INIT_26,
		INIT_27 => INIT_27,
		INIT_28 => INIT_28,
		INIT_29 => INIT_29,
		INIT_2A => INIT_2A,
		INIT_2B => INIT_2B,
		INIT_2C => INIT_2C,
		INIT_2D => INIT_2D,
		INIT_2E => INIT_2E,
		INIT_2F => INIT_2F,
		INIT_30 => INIT_30,
		INIT_31 => INIT_31,
		INIT_32 => INIT_32,
		INIT_33 => INIT_33,
		INIT_34 => INIT_34,
		INIT_35 => INIT_35,
		INIT_36 => INIT_36,
		INIT_37 => INIT_37,
		INIT_38 => INIT_38,
		INIT_39 => INIT_39,
		INIT_3A => INIT_3A,
		INIT_3B => INIT_3B,
		INIT_3C => INIT_3C,
		INIT_3D => INIT_3D,
		INIT_3E => INIT_3E,
		INIT_3F => INIT_3F,
                
		INITP_00 => INITP_00,
		INITP_01 => INITP_01,
		INITP_02 => INITP_02,
		INITP_03 => INITP_03,
		INITP_04 => INITP_04,
		INITP_05 => INITP_05,
		INITP_06 => INITP_06,
		INITP_07 => INITP_07,

		SIM_COLLISION_CHECK => SIM_COLLISION_CHECK,
                SIM_MODE => SIM_MODE,
		SRVAL_A => SRVAL_A,
		SRVAL_B => SRVAL_B,
		WRITE_MODE_A => WRITE_MODE_A,
		WRITE_MODE_B => WRITE_MODE_B,                
                BRAM_MODE => "TRUE_DUAL_PORT",
                BRAM_SIZE => 18,
                READ_WIDTH_A => READ_WIDTH_A,
                READ_WIDTH_B => READ_WIDTH_B,                
                WRITE_WIDTH_A => WRITE_WIDTH_A,
                WRITE_WIDTH_B => WRITE_WIDTH_B          
                )

  port map (
                ADDRA => addra_int,
                ADDRB => addrb_int,
                CLKA => CLKA,
                CLKB => CLKB,
                DIA(15 downto 0)  => DIA,
                DIA(63 downto 16) => GND_48,
                DIB(15 downto 0) => DIB,
                DIB(63 downto 16) => GND_48,
                DIPA(1 downto 0) => DIPA,
                DIPA(7 downto 2) => GND_6,
                DIPB(1 downto 0) => DIPB,
                DIPB(7 downto 2) => GND_6,
                ENA => ENA,
                ENB => ENB,
                SSRA => SSRA,
                SSRB => SSRB,
                WEA => wea_int,
                web => web_int,
                DOA(15  downto 0) => DOA_dly,
                DOA(63 downto 16) => OPEN_48,
                DOB(15 downto 0) => DOB_dly,
                DOB(63 downto 16) => OPEN_48,
                DOPA(1 downto 0) => DOPA_dly,
                DOPA(7 downto 2) => OPEN_6,
                DOPB(1 downto 0) => DOPB_dly,
                DOPB(7 downto 2) => OPEN_6,
                REGCLKA => CLKA,
                REGCLKB => CLKB,
                REGCEA => REGCEA,
                REGCEB => REGCEB,
                CASCADEOUTLATA => OPEN,
                CASCADEOUTLATB => OPEN,
                CASCADEOUTREGA => OPEN,
                CASCADEOUTREGB => OPEN,
                CASCADEINLATA => GND,
                CASCADEINLATB => GND,
                CASCADEINREGA => GND,
                CASCADEINREGB => GND
        );

  prcs_output_wtiming: process (doa_dly, dob_dly, dopa_dly, dopb_dly)
   begin  -- process prcs_output_wtiming

     DOA <= doa_dly after SYNC_PATH_DELAY;
     DOPA <= dopa_dly after SYNC_PATH_DELAY;
     DOB <= dob_dly after SYNC_PATH_DELAY;
     DOPB <= dopb_dly after SYNC_PATH_DELAY;

   end process prcs_output_wtiming;
  
end RAMB18_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/ramb36_exp.vhd,v 1.11 2007/06/15 21:01:09 wloo Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2005 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  32K-Bit Data and 4K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB36_EXP.vhd
-- \   \  /  \    Timestamp : Tues October 18 16:43:59 PST 2005
--  \___\/\___\
--
-- Revision:
--    10/18/05 - Initial version.
--    01/04/07 - Added support of memory file to initialize memory and parity (CR 431584).
--    03/14/07 - Removed attribute INITP_FILE (CR 436003).
--    04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812).
--    06/14/07 - Implemented high performace version of the model.
-- End Revision

----- CELL RAMB36_EXP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity RAMB36_EXP is
generic (
  
    DOA_REG : integer := 0;
    DOB_REG : integer := 0;
    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_A : bit_vector := X"000000000";
    INIT_B : bit_vector := X"000000000";
    INIT_FILE : string := "NONE";
    RAM_EXTENSION_A : string := "NONE";
    RAM_EXTENSION_B : string := "NONE";
    READ_WIDTH_A : integer := 0;
    READ_WIDTH_B : integer := 0;
    SIM_COLLISION_CHECK : string := "ALL";
    SIM_MODE : string := "SAFE";
    SRVAL_A : bit_vector := X"000000000";
    SRVAL_B : bit_vector := X"000000000";
    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST";
    WRITE_WIDTH_A : integer := 0;
    WRITE_WIDTH_B : integer := 0
    
  );

port (
  
    CASCADEOUTLATA : out std_ulogic;
    CASCADEOUTLATB : out std_ulogic;
    CASCADEOUTREGA : out std_ulogic;
    CASCADEOUTREGB : out std_ulogic;
    DOA : out std_logic_vector(31 downto 0);
    DOB : out std_logic_vector(31 downto 0);
    DOPA : out std_logic_vector(3 downto 0);
    DOPB : out std_logic_vector(3 downto 0);
    
    ADDRAL : in std_logic_vector(15 downto 0);
    ADDRAU : in std_logic_vector(14 downto 0);
    ADDRBL : in std_logic_vector(15 downto 0);
    ADDRBU : in std_logic_vector(14 downto 0);
    CASCADEINLATA : in std_ulogic;
    CASCADEINLATB : in std_ulogic;
    CASCADEINREGA : in std_ulogic;
    CASCADEINREGB : in std_ulogic;
    CLKAL : in std_ulogic;
    CLKAU : in std_ulogic;
    CLKBL : in std_ulogic;
    CLKBU : in std_ulogic;
    DIA : in std_logic_vector(31 downto 0);
    DIB : in std_logic_vector(31 downto 0);
    DIPA : in std_logic_vector(3 downto 0);
    DIPB : in std_logic_vector(3 downto 0);
    ENAL : in std_ulogic;
    ENAU : in std_ulogic;
    ENBL : in std_ulogic;
    ENBU : in std_ulogic;
    REGCEAL : in std_ulogic;
    REGCEAU : in std_ulogic;
    REGCEBL : in std_ulogic;
    REGCEBU : in std_ulogic;
    REGCLKAL : in std_ulogic;
    REGCLKAU : in std_ulogic;
    REGCLKBL : in std_ulogic;
    REGCLKBU : in std_ulogic;
    SSRAL : in std_ulogic;
    SSRAU : in std_ulogic;
    SSRBL : in std_ulogic;
    SSRBU : in std_ulogic;
    WEAL : in std_logic_vector(3 downto 0);
    WEAU : in std_logic_vector(3 downto 0);
    WEBL : in std_logic_vector(7 downto 0);
    WEBU : in std_logic_vector(7 downto 0)

  );
end RAMB36_EXP;
                                                                        
architecture RAMB36_EXP_V of RAMB36_EXP is

    component ARAMB36_INTERNAL
	generic
	(
          BRAM_MODE : string := "TRUE_DUAL_PORT";
          BRAM_SIZE : integer := 36;
          DOA_REG : integer := 0;
          DOB_REG : integer := 0;
          INIT_A : bit_vector := X"000000000000000000";
          INIT_B : bit_vector := X"000000000000000000";
          RAM_EXTENSION_A : string := "NONE";
          RAM_EXTENSION_B : string := "NONE";
          READ_WIDTH_A : integer := 0;
          READ_WIDTH_B : integer := 0;
          SIM_COLLISION_CHECK : string := "ALL";
          SIM_MODE : string := "SAFE";
          SRVAL_A : bit_vector := X"000000000000000000";
          SRVAL_B : bit_vector := X"000000000000000000";
          WRITE_MODE_A : string := "WRITE_FIRST";
          WRITE_MODE_B : string := "WRITE_FIRST";
          WRITE_WIDTH_A : integer := 0;
          WRITE_WIDTH_B : integer := 0;
          INIT_FILE : string := "NONE";
          INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
           );
	port
	(
          CASCADEOUTLATA : out std_ulogic;
          CASCADEOUTLATB : out std_ulogic;
          CASCADEOUTREGA : out std_ulogic;
          CASCADEOUTREGB : out std_ulogic;
          DBITERR : out std_ulogic;
          DOA : out std_logic_vector(63 downto 0);
          DOB : out std_logic_vector(63 downto 0);
          DOPA : out std_logic_vector(7 downto 0);
          DOPB : out std_logic_vector(7 downto 0);
          ECCPARITY : out std_logic_vector(7 downto 0);
          SBITERR : out std_ulogic;
    
          ADDRA : in std_logic_vector(15 downto 0);
          ADDRB : in std_logic_vector(15 downto 0);
          CASCADEINLATA : in std_ulogic;
          CASCADEINLATB : in std_ulogic;
          CASCADEINREGA : in std_ulogic;
          CASCADEINREGB : in std_ulogic;
          CLKA : in std_ulogic;
          CLKB : in std_ulogic;
          DIA : in std_logic_vector(63 downto 0);
          DIB : in std_logic_vector(63 downto 0);
          DIPA : in std_logic_vector(7 downto 0);
          DIPB : in std_logic_vector(7 downto 0);
          ENA : in std_ulogic;
          ENB : in std_ulogic;
          REGCEA : in std_ulogic;
          REGCEB : in std_ulogic;
          REGCLKA : in std_ulogic;
          REGCLKB : in std_ulogic;
          SSRA : in std_ulogic;
          SSRB : in std_ulogic;
          WEA : in std_logic_vector(7 downto 0);
          WEB : in std_logic_vector(7 downto 0)
 	);
  end component;

    
  constant SYNC_PATH_DELAY : time := 100 ps;
  signal GND_4 : std_logic_vector(3 downto 0) := (others => '0');
  signal GND_32 : std_logic_vector(31 downto 0) := (others => '0');
  signal OPEN_4 : std_logic_vector(3 downto 0);
  signal OPEN_32 : std_logic_vector(31 downto 0);
  signal doa_dly : std_logic_vector(31 downto 0) :=  (others => '0');
  signal dob_dly : std_logic_vector(31 downto 0) :=  (others => '0');
  signal dopa_dly : std_logic_vector(3 downto 0) :=  (others => '0');
  signal dopb_dly : std_logic_vector(3 downto 0) :=  (others => '0');
  signal cascadeoutlata_dly : std_ulogic := '0';
  signal cascadeoutlatb_dly : std_ulogic := '0';
  signal cascadeoutrega_dly : std_ulogic := '0';
  signal cascadeoutregb_dly : std_ulogic := '0';
    
begin


RAMB36_EXP_inst : ARAMB36_INTERNAL
	generic map (

                DOA_REG => DOA_REG,
                DOB_REG => DOB_REG,
		INIT_A  => INIT_A,
		INIT_B  => INIT_B,
                INIT_FILE => INIT_FILE,
                
		INIT_00 => INIT_00,
		INIT_01 => INIT_01,
		INIT_02 => INIT_02,
		INIT_03 => INIT_03,
		INIT_04 => INIT_04,
		INIT_05 => INIT_05,
		INIT_06 => INIT_06,
		INIT_07 => INIT_07,
		INIT_08 => INIT_08,
		INIT_09 => INIT_09,
		INIT_0A => INIT_0A,
		INIT_0B => INIT_0B,
		INIT_0C => INIT_0C,
		INIT_0D => INIT_0D,
		INIT_0E => INIT_0E,
		INIT_0F => INIT_0F,
		INIT_10 => INIT_10,
		INIT_11 => INIT_11,
		INIT_12 => INIT_12,
		INIT_13 => INIT_13,
		INIT_14 => INIT_14,
		INIT_15 => INIT_15,
		INIT_16 => INIT_16,
		INIT_17 => INIT_17,
		INIT_18 => INIT_18,
		INIT_19 => INIT_19,
		INIT_1A => INIT_1A,
		INIT_1B => INIT_1B,
		INIT_1C => INIT_1C,
		INIT_1D => INIT_1D,
		INIT_1E => INIT_1E,
		INIT_1F => INIT_1F,
		INIT_20 => INIT_20,
		INIT_21 => INIT_21,
		INIT_22 => INIT_22,
		INIT_23 => INIT_23,
		INIT_24 => INIT_24,
		INIT_25 => INIT_25,
		INIT_26 => INIT_26,
		INIT_27 => INIT_27,
		INIT_28 => INIT_28,
		INIT_29 => INIT_29,
		INIT_2A => INIT_2A,
		INIT_2B => INIT_2B,
		INIT_2C => INIT_2C,
		INIT_2D => INIT_2D,
		INIT_2E => INIT_2E,
		INIT_2F => INIT_2F,
		INIT_30 => INIT_30,
		INIT_31 => INIT_31,
		INIT_32 => INIT_32,
		INIT_33 => INIT_33,
		INIT_34 => INIT_34,
		INIT_35 => INIT_35,
		INIT_36 => INIT_36,
		INIT_37 => INIT_37,
		INIT_38 => INIT_38,
		INIT_39 => INIT_39,
		INIT_3A => INIT_3A,
		INIT_3B => INIT_3B,
		INIT_3C => INIT_3C,
		INIT_3D => INIT_3D,
		INIT_3E => INIT_3E,
		INIT_3F => INIT_3F,
		INIT_40 => INIT_40,
		INIT_41 => INIT_41,
		INIT_42 => INIT_42,
		INIT_43 => INIT_43,
		INIT_44 => INIT_44,
		INIT_45 => INIT_45,
		INIT_46 => INIT_46,
		INIT_47 => INIT_47,
		INIT_48 => INIT_48,
		INIT_49 => INIT_49,
		INIT_4A => INIT_4A,
		INIT_4B => INIT_4B,
		INIT_4C => INIT_4C,
		INIT_4D => INIT_4D,
		INIT_4E => INIT_4E,
		INIT_4F => INIT_4F,
		INIT_50 => INIT_50,
		INIT_51 => INIT_51,
		INIT_52 => INIT_52,
		INIT_53 => INIT_53,
		INIT_54 => INIT_54,
		INIT_55 => INIT_55,
		INIT_56 => INIT_56,
		INIT_57 => INIT_57,
		INIT_58 => INIT_58,
		INIT_59 => INIT_59,
		INIT_5A => INIT_5A,
		INIT_5B => INIT_5B,
		INIT_5C => INIT_5C,
		INIT_5D => INIT_5D,
		INIT_5E => INIT_5E,
		INIT_5F => INIT_5F,
		INIT_60 => INIT_60,
		INIT_61 => INIT_61,
		INIT_62 => INIT_62,
		INIT_63 => INIT_63,
		INIT_64 => INIT_64,
		INIT_65 => INIT_65,
		INIT_66 => INIT_66,
		INIT_67 => INIT_67,
		INIT_68 => INIT_68,
		INIT_69 => INIT_69,
		INIT_6A => INIT_6A,
		INIT_6B => INIT_6B,
		INIT_6C => INIT_6C,
		INIT_6D => INIT_6D,
		INIT_6E => INIT_6E,
		INIT_6F => INIT_6F,
		INIT_70 => INIT_70,
		INIT_71 => INIT_71,
		INIT_72 => INIT_72,
		INIT_73 => INIT_73,
		INIT_74 => INIT_74,
		INIT_75 => INIT_75,
		INIT_76 => INIT_76,
		INIT_77 => INIT_77,
		INIT_78 => INIT_78,
		INIT_79 => INIT_79,
		INIT_7A => INIT_7A,
		INIT_7B => INIT_7B,
		INIT_7C => INIT_7C,
		INIT_7D => INIT_7D,
		INIT_7E => INIT_7E,
		INIT_7F => INIT_7F,
                
		INITP_00 => INITP_00,
		INITP_01 => INITP_01,
		INITP_02 => INITP_02,
		INITP_03 => INITP_03,
		INITP_04 => INITP_04,
		INITP_05 => INITP_05,
		INITP_06 => INITP_06,
		INITP_07 => INITP_07,
		INITP_08 => INITP_08,
		INITP_09 => INITP_09,
		INITP_0A => INITP_0A,
		INITP_0B => INITP_0B,
		INITP_0C => INITP_0C,
		INITP_0D => INITP_0D,
		INITP_0E => INITP_0E,
		INITP_0F => INITP_0F,
                
		SIM_COLLISION_CHECK => SIM_COLLISION_CHECK,
                SIM_MODE => SIM_MODE,
		SRVAL_A => SRVAL_A,
		SRVAL_B => SRVAL_B,
		WRITE_MODE_A => WRITE_MODE_A,
		WRITE_MODE_B => WRITE_MODE_B,                
                BRAM_MODE => "TRUE_DUAL_PORT",
                BRAM_SIZE => 36,
                RAM_EXTENSION_A => RAM_EXTENSION_A,
                RAM_EXTENSION_B => RAM_EXTENSION_B,                
                READ_WIDTH_A => READ_WIDTH_A,
                READ_WIDTH_B => READ_WIDTH_B,                
                WRITE_WIDTH_A => WRITE_WIDTH_A,
                WRITE_WIDTH_B => WRITE_WIDTH_B          
                )
  
        port map (
                ADDRA => ADDRAL,
                ADDRB => ADDRBL,
                CLKA => CLKAL,
                CLKB => CLKBL,
                DIA(31 downto 0)  => DIA,
                DIA(63 downto 32) => GND_32,
                DIB(31 downto 0) => DIB,
                DIB(63 downto 32) => GND_32,
                DIPA(3 downto 0) => DIPA,
                DIPA(7 downto 4) => GND_4,
                DIPB(3 downto 0) => DIPB,
                DIPB(7 downto 4) => GND_4,
                ENA => ENAL,
                ENB => ENBL,
                SSRA => SSRAL,
                SSRB => SSRBL,
                WEA(3 downto 0) => WEAL,
                WEA(7 downto 4) => GND_4,
                WEB => WEBL,
                DOA(31  downto 0) => doa_dly,
                DOA(63 downto 32) => OPEN_32,
                DOB(31 downto 0) => dob_dly,
                DOB(63 downto 32) => OPEN_32,
                DOPA(3 downto 0) => dopa_dly,
                DOPA(7 downto 4) => OPEN_4,
                DOPB(3 downto 0) => dopb_dly,
                DOPB(7 downto 4) => OPEN_4,
                CASCADEOUTLATA => cascadeoutlata_dly,
                CASCADEOUTLATB => cascadeoutlatb_dly,
                CASCADEOUTREGA => cascadeoutrega_dly,
                CASCADEOUTREGB => cascadeoutregb_dly,
                CASCADEINLATA => CASCADEINLATA,
                CASCADEINLATB => CASCADEINLATB,
                CASCADEINREGA => CASCADEINREGA,
                CASCADEINREGB => CASCADEINREGB,
                REGCLKA => REGCLKAL,
                REGCLKB => REGCLKBL,
                REGCEA => REGCEAL,
                REGCEB => REGCEBL
        );

   prcs_output_wtiming: process (doa_dly, dob_dly, dopa_dly, dopb_dly, cascadeoutlata_dly, cascadeoutlatb_dly, cascadeoutrega_dly, cascadeoutregb_dly )
   begin  -- process prcs_output_wtiming

     CASCADEOUTREGA <= cascadeoutrega_dly after SYNC_PATH_DELAY;
     CASCADEOUTREGB <= cascadeoutregb_dly after SYNC_PATH_DELAY;
     CASCADEOUTLATA <= cascadeoutlata_dly after SYNC_PATH_DELAY;
     CASCADEOUTLATB <= cascadeoutlatb_dly after SYNC_PATH_DELAY;
     DOA <= doa_dly after SYNC_PATH_DELAY;
     DOPA <= dopa_dly after SYNC_PATH_DELAY;
     DOB <= dob_dly after SYNC_PATH_DELAY;
     DOPB <= dopb_dly after SYNC_PATH_DELAY;

   end process prcs_output_wtiming;

end RAMB36_EXP_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/ramb36sdp_exp.vhd,v 1.12 2007/06/15 21:01:09 wloo Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2005 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  32K-Bit Data and 4K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB36SDP_EXP.vhd
-- \   \  /  \    Timestamp : Tues October 18 16:43:59 PST 2005
--  \___\/\___\
--
-- Revision:
--    10/18/05 - Initial version.
--    01/04/07 - Added support of memory file to initialize memory and parity (CR 431584).
--    03/14/07 - Removed attribute INITP_FILE (CR 436003).
--    04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812).
--    06/14/07 - Implemented high performace version of the model.
-- End Revision

----- CELL RAMB36SDP_EXP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity RAMB36SDP_EXP is
generic (
  
    DO_REG : integer := 0;
    EN_ECC_READ : boolean := FALSE;
    EN_ECC_SCRUB : boolean := FALSE;
    EN_ECC_WRITE : boolean := FALSE; 
    INIT : bit_vector := X"000000000000000000";
    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_FILE : string := "NONE";
    SIM_COLLISION_CHECK : string := "ALL";
    SIM_MODE : string := "SAFE";
    SRVAL : bit_vector := X"000000000000000000"
    
  );

port (

    DBITERR : out std_ulogic;
    DO : out std_logic_vector(63 downto 0);
    DOP : out std_logic_vector(7 downto 0);
    ECCPARITY : out std_logic_vector(7 downto 0);
    SBITERR : out std_ulogic;
    
    DI : in std_logic_vector(63 downto 0);
    DIP : in std_logic_vector(7 downto 0);
    RDADDRL : in std_logic_vector(15 downto 0);
    RDADDRU : in std_logic_vector(14 downto 0);    
    RDCLKL : in std_ulogic;
    RDCLKU : in std_ulogic;    
    RDENU : in std_ulogic;
    RDENL : in std_ulogic;    
    RDRCLKL : in std_ulogic;
    RDRCLKU : in std_ulogic;    
    REGCEL : in std_ulogic;
    REGCEU : in std_ulogic;    
    SSRL : in std_ulogic;
    SSRU : in std_ulogic;    
    WEL : in std_logic_vector(7 downto 0);
    WEU : in std_logic_vector(7 downto 0);    
    WRADDRL : in std_logic_vector(15 downto 0);
    WRADDRU : in std_logic_vector(14 downto 0);    
    WRCLKL : in std_ulogic;
    WRCLKU : in std_ulogic;    
    WRENL : in std_ulogic;
    WRENU : in std_ulogic    

  );
end RAMB36SDP_EXP;
                                                                        
architecture RAMB36SDP_EXP_V of RAMB36SDP_EXP is

  component ARAMB36_INTERNAL
	generic
	(
          BRAM_MODE : string := "TRUE_DUAL_PORT";
          BRAM_SIZE : integer := 36;
          DOA_REG : integer := 0;
          DOB_REG : integer := 0;
          INIT_A : bit_vector := X"000000000000000000";
          INIT_B : bit_vector := X"000000000000000000";
          RAM_EXTENSION_A : string := "NONE";
          RAM_EXTENSION_B : string := "NONE";
          READ_WIDTH_A : integer := 0;
          READ_WIDTH_B : integer := 0;
          SIM_COLLISION_CHECK : string := "ALL";
          SIM_MODE : string := "SAFE";
          SRVAL_A : bit_vector := X"000000000000000000";
          SRVAL_B : bit_vector := X"000000000000000000";
          WRITE_MODE_A : string := "WRITE_FIRST";
          WRITE_MODE_B : string := "WRITE_FIRST";
          WRITE_WIDTH_A : integer := 0;
          WRITE_WIDTH_B : integer := 0;
          EN_ECC_READ : boolean := FALSE;
          EN_ECC_SCRUB : boolean := FALSE;
          EN_ECC_WRITE : boolean := FALSE;
          INIT_FILE : string := "NONE";
          INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
           );
	port
	(
          CASCADEOUTLATA : out std_ulogic;
          CASCADEOUTLATB : out std_ulogic;
          CASCADEOUTREGA : out std_ulogic;
          CASCADEOUTREGB : out std_ulogic;
          DBITERR : out std_ulogic;
          DOA : out std_logic_vector(63 downto 0);
          DOB : out std_logic_vector(63 downto 0);
          DOPA : out std_logic_vector(7 downto 0);
          DOPB : out std_logic_vector(7 downto 0);
          ECCPARITY : out std_logic_vector(7 downto 0);
          SBITERR : out std_ulogic;
    
          ADDRA : in std_logic_vector(15 downto 0);
          ADDRB : in std_logic_vector(15 downto 0);
          CASCADEINLATA : in std_ulogic;
          CASCADEINLATB : in std_ulogic;
          CASCADEINREGA : in std_ulogic;
          CASCADEINREGB : in std_ulogic;
          CLKA : in std_ulogic;
          CLKB : in std_ulogic;
          DIA : in std_logic_vector(63 downto 0);
          DIB : in std_logic_vector(63 downto 0);
          DIPA : in std_logic_vector(7 downto 0);
          DIPB : in std_logic_vector(7 downto 0);
          ENA : in std_ulogic;
          ENB : in std_ulogic;
          REGCEA : in std_ulogic;
          REGCEB : in std_ulogic;
          REGCLKA : in std_ulogic;
          REGCLKB : in std_ulogic;
          SSRA : in std_ulogic;
          SSRB : in std_ulogic;
          WEA : in std_logic_vector(7 downto 0);
          WEB : in std_logic_vector(7 downto 0)
 	);
  end component;

  
  function GENERICS_STR_BRAM_MODE (
    IN_STR1 : in boolean;
    IN_STR2 : in boolean
    ) return string is
  begin
    if (IN_STR1 = TRUE or IN_STR2 = TRUE) then
      return "ECC";
    else
      return "SIMPLE_DUAL_PORT";
    end if;
  end GENERICS_STR_BRAM_MODE;

  
  constant SYNC_PATH_DELAY : time := 100 ps;
  signal GND : std_ulogic := '0';
  signal GND_8 : std_logic_vector(7 downto 0) := (others => '0');
  signal GND_64 : std_logic_vector(63 downto 0) := (others => '0');
  signal OPEN_8 : std_logic_vector(7 downto 0);
  signal OPEN_64 : std_logic_vector(63 downto 0);
  signal do_dly : std_logic_vector(63 downto 0) :=  (others => '0');
  signal dop_dly : std_logic_vector(7 downto 0) :=  (others => '0');
  signal eccparity_dly : std_logic_vector(7 downto 0) :=  (others => '0');
  signal dbiterr_dly : std_ulogic := '0';
  signal sbiterr_dly : std_ulogic := '0';
  
begin
  
RAMB36SDP_EXP_inst : ARAMB36_INTERNAL
	generic map (

                INIT_00 => INIT_00,
		INIT_01 => INIT_01,
		INIT_02 => INIT_02,
		INIT_03 => INIT_03,
		INIT_04 => INIT_04,
		INIT_05 => INIT_05,
		INIT_06 => INIT_06,
		INIT_07 => INIT_07,
		INIT_08 => INIT_08,
		INIT_09 => INIT_09,
		INIT_0A => INIT_0A,
		INIT_0B => INIT_0B,
		INIT_0C => INIT_0C,
		INIT_0D => INIT_0D,
		INIT_0E => INIT_0E,
		INIT_0F => INIT_0F,
		INIT_10 => INIT_10,
		INIT_11 => INIT_11,
		INIT_12 => INIT_12,
		INIT_13 => INIT_13,
		INIT_14 => INIT_14,
		INIT_15 => INIT_15,
		INIT_16 => INIT_16,
		INIT_17 => INIT_17,
		INIT_18 => INIT_18,
		INIT_19 => INIT_19,
		INIT_1A => INIT_1A,
		INIT_1B => INIT_1B,
		INIT_1C => INIT_1C,
		INIT_1D => INIT_1D,
		INIT_1E => INIT_1E,
		INIT_1F => INIT_1F,
		INIT_20 => INIT_20,
		INIT_21 => INIT_21,
		INIT_22 => INIT_22,
		INIT_23 => INIT_23,
		INIT_24 => INIT_24,
		INIT_25 => INIT_25,
		INIT_26 => INIT_26,
		INIT_27 => INIT_27,
		INIT_28 => INIT_28,
		INIT_29 => INIT_29,
		INIT_2A => INIT_2A,
		INIT_2B => INIT_2B,
		INIT_2C => INIT_2C,
		INIT_2D => INIT_2D,
		INIT_2E => INIT_2E,
		INIT_2F => INIT_2F,
		INIT_30 => INIT_30,
		INIT_31 => INIT_31,
		INIT_32 => INIT_32,
		INIT_33 => INIT_33,
		INIT_34 => INIT_34,
		INIT_35 => INIT_35,
		INIT_36 => INIT_36,
		INIT_37 => INIT_37,
		INIT_38 => INIT_38,
		INIT_39 => INIT_39,
		INIT_3A => INIT_3A,
		INIT_3B => INIT_3B,
		INIT_3C => INIT_3C,
		INIT_3D => INIT_3D,
		INIT_3E => INIT_3E,
		INIT_3F => INIT_3F,
		INIT_40 => INIT_40,
		INIT_41 => INIT_41,
		INIT_42 => INIT_42,
		INIT_43 => INIT_43,
		INIT_44 => INIT_44,
		INIT_45 => INIT_45,
		INIT_46 => INIT_46,
		INIT_47 => INIT_47,
		INIT_48 => INIT_48,
		INIT_49 => INIT_49,
		INIT_4A => INIT_4A,
		INIT_4B => INIT_4B,
		INIT_4C => INIT_4C,
		INIT_4D => INIT_4D,
		INIT_4E => INIT_4E,
		INIT_4F => INIT_4F,
		INIT_50 => INIT_50,
		INIT_51 => INIT_51,
		INIT_52 => INIT_52,
		INIT_53 => INIT_53,
		INIT_54 => INIT_54,
		INIT_55 => INIT_55,
		INIT_56 => INIT_56,
		INIT_57 => INIT_57,
		INIT_58 => INIT_58,
		INIT_59 => INIT_59,
		INIT_5A => INIT_5A,
		INIT_5B => INIT_5B,
		INIT_5C => INIT_5C,
		INIT_5D => INIT_5D,
		INIT_5E => INIT_5E,
		INIT_5F => INIT_5F,
		INIT_60 => INIT_60,
		INIT_61 => INIT_61,
		INIT_62 => INIT_62,
		INIT_63 => INIT_63,
		INIT_64 => INIT_64,
		INIT_65 => INIT_65,
		INIT_66 => INIT_66,
		INIT_67 => INIT_67,
		INIT_68 => INIT_68,
		INIT_69 => INIT_69,
		INIT_6A => INIT_6A,
		INIT_6B => INIT_6B,
		INIT_6C => INIT_6C,
		INIT_6D => INIT_6D,
		INIT_6E => INIT_6E,
		INIT_6F => INIT_6F,
		INIT_70 => INIT_70,
		INIT_71 => INIT_71,
		INIT_72 => INIT_72,
		INIT_73 => INIT_73,
		INIT_74 => INIT_74,
		INIT_75 => INIT_75,
		INIT_76 => INIT_76,
		INIT_77 => INIT_77,
		INIT_78 => INIT_78,
		INIT_79 => INIT_79,
		INIT_7A => INIT_7A,
		INIT_7B => INIT_7B,
		INIT_7C => INIT_7C,
		INIT_7D => INIT_7D,
		INIT_7E => INIT_7E,
		INIT_7F => INIT_7F,
                
		INITP_00 => INITP_00,
		INITP_01 => INITP_01,
		INITP_02 => INITP_02,
		INITP_03 => INITP_03,
		INITP_04 => INITP_04,
		INITP_05 => INITP_05,
		INITP_06 => INITP_06,
		INITP_07 => INITP_07,
		INITP_08 => INITP_08,
		INITP_09 => INITP_09,
		INITP_0A => INITP_0A,
		INITP_0B => INITP_0B,
		INITP_0C => INITP_0C,
		INITP_0D => INITP_0D,
		INITP_0E => INITP_0E,
		INITP_0F => INITP_0F,

		INIT_A  => INIT,
		INIT_B  => INIT,
                INIT_FILE => INIT_FILE,
		SIM_COLLISION_CHECK => SIM_COLLISION_CHECK,
                SIM_MODE => SIM_MODE,
		SRVAL_A => SRVAL,
		SRVAL_B => SRVAL,
		WRITE_MODE_A => "READ_FIRST",
		WRITE_MODE_B => "READ_FIRST",                
                BRAM_MODE => GENERICS_STR_BRAM_MODE(EN_ECC_WRITE, EN_ECC_READ),
                EN_ECC_READ => EN_ECC_READ,
                EN_ECC_WRITE => EN_ECC_WRITE,
                EN_ECC_SCRUB => EN_ECC_SCRUB,
                DOA_REG => DO_REG,
                DOB_REG => DO_REG,
                READ_WIDTH_A => 72,
                READ_WIDTH_B => 72,                
                WRITE_WIDTH_A => 72,
                WRITE_WIDTH_B => 72          
                )
  
        port map (
                ADDRA => RDADDRL,
                ADDRB => WRADDRL,
                CLKA => RDCLKL,
                CLKB => WRCLKL,
                DIA => GND_64,
                DIB => DI,
                DIPA => GND_8,
                DIPB => DIP,
                ENA => RDENL,
                ENB => WRENL,
                SSRA => SSRL,
                SSRB => GND,
                WEA => GND_8,
                WEB => WEL,
                DOA => do_dly,
                DOB => OPEN_64,
                DOPA => dop_dly,
                DOPB => OPEN_8,
                CASCADEOUTLATA => OPEN,
                CASCADEOUTLATB => OPEN,
                CASCADEOUTREGA => OPEN,
                CASCADEOUTREGB => OPEN,
                CASCADEINLATA => GND,
                CASCADEINLATB => GND,
                CASCADEINREGA => GND,
                CASCADEINREGB => GND,
                REGCLKA => RDRCLKL,
                REGCLKB => GND,
                REGCEA => REGCEL,
                REGCEB => GND,
                DBITERR => dbiterr_dly,
                SBITERR => sbiterr_dly,
                ECCPARITY => eccparity_dly
        );

   prcs_output_wtiming: process (do_dly, dop_dly, eccparity_dly, dbiterr_dly, sbiterr_dly)
   begin  -- process prcs_output_wtiming

     DBITERR <= dbiterr_dly after SYNC_PATH_DELAY;
     SBITERR <= sbiterr_dly after SYNC_PATH_DELAY;
     ECCPARITY <= eccparity_dly after SYNC_PATH_DELAY;
     DO <= do_dly after SYNC_PATH_DELAY;
     DOP <= dop_dly after SYNC_PATH_DELAY;

   end process prcs_output_wtiming;

end RAMB36SDP_EXP_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/ramb36sdp.vhd,v 1.13 2007/06/15 21:01:09 wloo Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2005 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  32K-Bit Data and 4K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB36SDP.vhd
-- \   \  /  \    Timestamp : Tues October 18 16:43:59 PST 2005
--  \___\/\___\
--
-- Revision:
--    10/18/05 - Initial version.
--    01/04/07 - Added support of memory file to initialize memory and parity (CR 431584).
--    03/14/07 - Removed attribute INITP_FILE (CR 436003).
--    04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812).
--    06/14/07 - Implemented high performace version of the model.
-- End Revision

----- CELL RAMB36SDP -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity RAMB36SDP is
generic (

    DO_REG : integer := 0;
    EN_ECC_READ : boolean := FALSE;
    EN_ECC_SCRUB : boolean := FALSE;
    EN_ECC_WRITE : boolean := FALSE; 
    INIT : bit_vector := X"000000000000000000";
    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_FILE : string := "NONE";
    SIM_COLLISION_CHECK : string := "ALL";
    SIM_MODE : string := "SAFE";
    SRVAL : bit_vector := X"000000000000000000"
    
  );

port (

    DBITERR : out std_ulogic;
    DO : out std_logic_vector(63 downto 0);
    DOP : out std_logic_vector(7 downto 0);
    ECCPARITY : out std_logic_vector(7 downto 0);
    SBITERR : out std_ulogic;
    
    DI : in std_logic_vector(63 downto 0);
    DIP : in std_logic_vector(7 downto 0);
    RDADDR : in std_logic_vector(8 downto 0);
    RDCLK : in std_ulogic;
    RDEN : in std_ulogic;
    REGCE : in std_ulogic;
    SSR : in std_ulogic;
    WE : in std_logic_vector(7 downto 0);
    WRADDR : in std_logic_vector(8 downto 0);
    WRCLK : in std_ulogic;
    WREN : in std_ulogic

  );
end RAMB36SDP;
                                                                        
architecture RAMB36SDP_V of RAMB36SDP is

  component ARAMB36_INTERNAL
	generic
	(
          BRAM_MODE : string := "TRUE_DUAL_PORT";
          BRAM_SIZE : integer := 36;
          DOA_REG : integer := 0;
          DOB_REG : integer := 0;
          INIT_A : bit_vector := X"000000000000000000";
          INIT_B : bit_vector := X"000000000000000000";
          RAM_EXTENSION_A : string := "NONE";
          RAM_EXTENSION_B : string := "NONE";
          READ_WIDTH_A : integer := 0;
          READ_WIDTH_B : integer := 0;
          SIM_COLLISION_CHECK : string := "ALL";
          SIM_MODE : string := "SAFE";
          SRVAL_A : bit_vector := X"000000000000000000";
          SRVAL_B : bit_vector := X"000000000000000000";
          WRITE_MODE_A : string := "WRITE_FIRST";
          WRITE_MODE_B : string := "WRITE_FIRST";
          WRITE_WIDTH_A : integer := 0;
          WRITE_WIDTH_B : integer := 0;
          EN_ECC_READ : boolean := FALSE;
          EN_ECC_SCRUB : boolean := FALSE;
          EN_ECC_WRITE : boolean := FALSE;
          INIT_FILE : string := "NONE";
          INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
           );
	port
	(
          CASCADEOUTLATA : out std_ulogic;
          CASCADEOUTLATB : out std_ulogic;
          CASCADEOUTREGA : out std_ulogic;
          CASCADEOUTREGB : out std_ulogic;
          DBITERR : out std_ulogic;
          DOA : out std_logic_vector(63 downto 0);
          DOB : out std_logic_vector(63 downto 0);
          DOPA : out std_logic_vector(7 downto 0);
          DOPB : out std_logic_vector(7 downto 0);
          ECCPARITY : out std_logic_vector(7 downto 0);
          SBITERR : out std_ulogic;
    
          ADDRA : in std_logic_vector(15 downto 0);
          ADDRB : in std_logic_vector(15 downto 0);
          CASCADEINLATA : in std_ulogic;
          CASCADEINLATB : in std_ulogic;
          CASCADEINREGA : in std_ulogic;
          CASCADEINREGB : in std_ulogic;
          CLKA : in std_ulogic;
          CLKB : in std_ulogic;
          DIA : in std_logic_vector(63 downto 0);
          DIB : in std_logic_vector(63 downto 0);
          DIPA : in std_logic_vector(7 downto 0);
          DIPB : in std_logic_vector(7 downto 0);
          ENA : in std_ulogic;
          ENB : in std_ulogic;
          REGCEA : in std_ulogic;
          REGCEB : in std_ulogic;
          REGCLKA : in std_ulogic;
          REGCLKB : in std_ulogic;
          SSRA : in std_ulogic;
          SSRB : in std_ulogic;
          WEA : in std_logic_vector(7 downto 0);
          WEB : in std_logic_vector(7 downto 0)
 	);
  end component;

  
  function GENERICS_STR_BRAM_MODE (
    IN_STR1 : in boolean;
    IN_STR2 : in boolean
    ) return string is
  begin
    if (IN_STR1 = TRUE or IN_STR2 = TRUE) then
      return "ECC";
    else
      return "SIMPLE_DUAL_PORT";
    end if;
  end GENERICS_STR_BRAM_MODE;

  
  constant SYNC_PATH_DELAY : time := 100 ps;
  signal addra_int : std_logic_vector(15 downto 0) := (others => '0');
  signal addrb_int : std_logic_vector(15 downto 0) := (others => '0');
  signal GND : std_ulogic := '0';
  signal GND_8 : std_logic_vector(7 downto 0) := (others => '0');
  signal GND_64 : std_logic_vector(63 downto 0) := (others => '0');
  signal OPEN_8 : std_logic_vector(7 downto 0);
  signal OPEN_64 : std_logic_vector(63 downto 0);
  signal do_dly : std_logic_vector(63 downto 0) :=  (others => '0');
  signal dop_dly : std_logic_vector(7 downto 0) :=  (others => '0');
  signal eccparity_dly : std_logic_vector(7 downto 0) :=  (others => '0');
  signal dbiterr_dly : std_ulogic := '0';
  signal sbiterr_dly : std_ulogic := '0';
  
begin
  
   addra_int <= '0' & RDADDR & "000000";
   addrb_int <= '0' & WRADDR & "000000";
  
RAMB36SDP_inst : ARAMB36_INTERNAL
	generic map (

                INIT_00 => INIT_00,
		INIT_01 => INIT_01,
		INIT_02 => INIT_02,
		INIT_03 => INIT_03,
		INIT_04 => INIT_04,
		INIT_05 => INIT_05,
		INIT_06 => INIT_06,
		INIT_07 => INIT_07,
		INIT_08 => INIT_08,
		INIT_09 => INIT_09,
		INIT_0A => INIT_0A,
		INIT_0B => INIT_0B,
		INIT_0C => INIT_0C,
		INIT_0D => INIT_0D,
		INIT_0E => INIT_0E,
		INIT_0F => INIT_0F,
		INIT_10 => INIT_10,
		INIT_11 => INIT_11,
		INIT_12 => INIT_12,
		INIT_13 => INIT_13,
		INIT_14 => INIT_14,
		INIT_15 => INIT_15,
		INIT_16 => INIT_16,
		INIT_17 => INIT_17,
		INIT_18 => INIT_18,
		INIT_19 => INIT_19,
		INIT_1A => INIT_1A,
		INIT_1B => INIT_1B,
		INIT_1C => INIT_1C,
		INIT_1D => INIT_1D,
		INIT_1E => INIT_1E,
		INIT_1F => INIT_1F,
		INIT_20 => INIT_20,
		INIT_21 => INIT_21,
		INIT_22 => INIT_22,
		INIT_23 => INIT_23,
		INIT_24 => INIT_24,
		INIT_25 => INIT_25,
		INIT_26 => INIT_26,
		INIT_27 => INIT_27,
		INIT_28 => INIT_28,
		INIT_29 => INIT_29,
		INIT_2A => INIT_2A,
		INIT_2B => INIT_2B,
		INIT_2C => INIT_2C,
		INIT_2D => INIT_2D,
		INIT_2E => INIT_2E,
		INIT_2F => INIT_2F,
		INIT_30 => INIT_30,
		INIT_31 => INIT_31,
		INIT_32 => INIT_32,
		INIT_33 => INIT_33,
		INIT_34 => INIT_34,
		INIT_35 => INIT_35,
		INIT_36 => INIT_36,
		INIT_37 => INIT_37,
		INIT_38 => INIT_38,
		INIT_39 => INIT_39,
		INIT_3A => INIT_3A,
		INIT_3B => INIT_3B,
		INIT_3C => INIT_3C,
		INIT_3D => INIT_3D,
		INIT_3E => INIT_3E,
		INIT_3F => INIT_3F,
		INIT_40 => INIT_40,
		INIT_41 => INIT_41,
		INIT_42 => INIT_42,
		INIT_43 => INIT_43,
		INIT_44 => INIT_44,
		INIT_45 => INIT_45,
		INIT_46 => INIT_46,
		INIT_47 => INIT_47,
		INIT_48 => INIT_48,
		INIT_49 => INIT_49,
		INIT_4A => INIT_4A,
		INIT_4B => INIT_4B,
		INIT_4C => INIT_4C,
		INIT_4D => INIT_4D,
		INIT_4E => INIT_4E,
		INIT_4F => INIT_4F,
		INIT_50 => INIT_50,
		INIT_51 => INIT_51,
		INIT_52 => INIT_52,
		INIT_53 => INIT_53,
		INIT_54 => INIT_54,
		INIT_55 => INIT_55,
		INIT_56 => INIT_56,
		INIT_57 => INIT_57,
		INIT_58 => INIT_58,
		INIT_59 => INIT_59,
		INIT_5A => INIT_5A,
		INIT_5B => INIT_5B,
		INIT_5C => INIT_5C,
		INIT_5D => INIT_5D,
		INIT_5E => INIT_5E,
		INIT_5F => INIT_5F,
		INIT_60 => INIT_60,
		INIT_61 => INIT_61,
		INIT_62 => INIT_62,
		INIT_63 => INIT_63,
		INIT_64 => INIT_64,
		INIT_65 => INIT_65,
		INIT_66 => INIT_66,
		INIT_67 => INIT_67,
		INIT_68 => INIT_68,
		INIT_69 => INIT_69,
		INIT_6A => INIT_6A,
		INIT_6B => INIT_6B,
		INIT_6C => INIT_6C,
		INIT_6D => INIT_6D,
		INIT_6E => INIT_6E,
		INIT_6F => INIT_6F,
		INIT_70 => INIT_70,
		INIT_71 => INIT_71,
		INIT_72 => INIT_72,
		INIT_73 => INIT_73,
		INIT_74 => INIT_74,
		INIT_75 => INIT_75,
		INIT_76 => INIT_76,
		INIT_77 => INIT_77,
		INIT_78 => INIT_78,
		INIT_79 => INIT_79,
		INIT_7A => INIT_7A,
		INIT_7B => INIT_7B,
		INIT_7C => INIT_7C,
		INIT_7D => INIT_7D,
		INIT_7E => INIT_7E,
		INIT_7F => INIT_7F,
                
		INITP_00 => INITP_00,
		INITP_01 => INITP_01,
		INITP_02 => INITP_02,
		INITP_03 => INITP_03,
		INITP_04 => INITP_04,
		INITP_05 => INITP_05,
		INITP_06 => INITP_06,
		INITP_07 => INITP_07,
		INITP_08 => INITP_08,
		INITP_09 => INITP_09,
		INITP_0A => INITP_0A,
		INITP_0B => INITP_0B,
		INITP_0C => INITP_0C,
		INITP_0D => INITP_0D,
		INITP_0E => INITP_0E,
		INITP_0F => INITP_0F,

		INIT_A  => INIT,
		INIT_B  => INIT,
                INIT_FILE => INIT_FILE,
		SIM_COLLISION_CHECK => SIM_COLLISION_CHECK,
                SIM_MODE => SIM_MODE,
		SRVAL_A => SRVAL,
		SRVAL_B => SRVAL,
		WRITE_MODE_A => "READ_FIRST",
		WRITE_MODE_B => "READ_FIRST",                
                BRAM_MODE => GENERICS_STR_BRAM_MODE(EN_ECC_WRITE, EN_ECC_READ),
                EN_ECC_READ => EN_ECC_READ,
                EN_ECC_WRITE => EN_ECC_WRITE,
                EN_ECC_SCRUB => EN_ECC_SCRUB,
                DOA_REG => DO_REG,
                DOB_REG => DO_REG,
                READ_WIDTH_A => 72,
                READ_WIDTH_B => 72,                
                WRITE_WIDTH_A => 72,
                WRITE_WIDTH_B => 72          
                )
  
        port map (
                ADDRA => addra_int,
                ADDRB => addrb_int,
                CLKA => RDCLK,
                CLKB => WRCLK,
                DIA => GND_64,
                DIB => DI,
                DIPA => GND_8,
                DIPB => DIP,
                ENA => RDEN,
                ENB => WREN,
                SSRA => SSR,
                SSRB => GND,
                WEA => GND_8,
                WEB => WE,
                DOA => do_dly,
                DOB => OPEN_64,
                DOPA => dop_dly,
                DOPB => OPEN_8,
                CASCADEOUTLATA => OPEN,
                CASCADEOUTLATB => OPEN,
                CASCADEOUTREGA => OPEN,
                CASCADEOUTREGB => OPEN,
                CASCADEINLATA => GND,
                CASCADEINLATB => GND,
                CASCADEINREGA => GND,
                CASCADEINREGB => GND,
                REGCLKA => RDCLK,
                REGCLKB => GND,
                REGCEA => REGCE,
                REGCEB => GND,
                DBITERR => dbiterr_dly,
                SBITERR => sbiterr_dly,
                ECCPARITY => eccparity_dly
        );

   prcs_output_wtiming: process (do_dly, dop_dly, eccparity_dly, dbiterr_dly, sbiterr_dly)
   begin  -- process prcs_output_wtiming

     DBITERR <= dbiterr_dly after SYNC_PATH_DELAY;
     SBITERR <= sbiterr_dly after SYNC_PATH_DELAY;
     ECCPARITY <= eccparity_dly after SYNC_PATH_DELAY;
     DO <= do_dly after SYNC_PATH_DELAY;
     DOP <= dop_dly after SYNC_PATH_DELAY;

   end process prcs_output_wtiming;
   
end RAMB36SDP_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/ramb36.vhd,v 1.12 2007/06/15 21:01:09 wloo Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2005 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  32K-Bit Data and 4K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB36.vhd
-- \   \  /  \    Timestamp : Tues October 18 16:43:59 PST 2005
--  \___\/\___\
--
-- Revision:
--    10/18/05 - Initial version.
--    01/04/07 - Added support of memory file to initialize memory and parity (CR 431584).
--    03/14/07 - Removed attribute INITP_FILE (CR 436003).
--    04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812).
--    06/14/07 - Implemented high performace version of the model.
-- End Revision

----- CELL RAMB36 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity RAMB36 is
generic (

    DOA_REG : integer := 0;
    DOB_REG : integer := 0;
    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_A : bit_vector := X"000000000";
    INIT_B : bit_vector := X"000000000";
    INIT_FILE : string := "NONE";
    RAM_EXTENSION_A : string := "NONE";
    RAM_EXTENSION_B : string := "NONE";
    READ_WIDTH_A : integer := 0;
    READ_WIDTH_B : integer := 0;
    SIM_COLLISION_CHECK : string := "ALL";
    SIM_MODE : string := "SAFE";
    SRVAL_A : bit_vector := X"000000000";
    SRVAL_B : bit_vector := X"000000000";
    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST";
    WRITE_WIDTH_A : integer := 0;
    WRITE_WIDTH_B : integer := 0
    
  );

port (
  
    CASCADEOUTLATA : out std_ulogic;
    CASCADEOUTLATB : out std_ulogic;
    CASCADEOUTREGA : out std_ulogic;
    CASCADEOUTREGB : out std_ulogic;
    DOA : out std_logic_vector(31 downto 0);
    DOB : out std_logic_vector(31 downto 0);
    DOPA : out std_logic_vector(3 downto 0);
    DOPB : out std_logic_vector(3 downto 0);
    
    ADDRA : in std_logic_vector(15 downto 0);
    ADDRB : in std_logic_vector(15 downto 0);
    CASCADEINLATA : in std_ulogic;
    CASCADEINLATB : in std_ulogic;
    CASCADEINREGA : in std_ulogic;
    CASCADEINREGB : in std_ulogic;
    CLKA : in std_ulogic;
    CLKB : in std_ulogic;
    DIA : in std_logic_vector(31 downto 0);
    DIB : in std_logic_vector(31 downto 0);
    DIPA : in std_logic_vector(3 downto 0);
    DIPB : in std_logic_vector(3 downto 0);
    ENA : in std_ulogic;
    ENB : in std_ulogic;
    REGCEA : in std_ulogic;
    REGCEB : in std_ulogic;
    SSRA : in std_ulogic;
    SSRB : in std_ulogic;
    WEA : in std_logic_vector(3 downto 0);
    WEB : in std_logic_vector(3 downto 0)

  );
end RAMB36;
                                                                        
architecture RAMB36_V of RAMB36 is

  component ARAMB36_INTERNAL
	generic
	(
          BRAM_MODE : string := "TRUE_DUAL_PORT";
          BRAM_SIZE : integer := 36;
          DOA_REG : integer := 0;
          DOB_REG : integer := 0;
          INIT_A : bit_vector := X"000000000000000000";
          INIT_B : bit_vector := X"000000000000000000";
          RAM_EXTENSION_A : string := "NONE";
          RAM_EXTENSION_B : string := "NONE";
          READ_WIDTH_A : integer := 0;
          READ_WIDTH_B : integer := 0;
          SIM_COLLISION_CHECK : string := "ALL";
          SIM_MODE : string := "SAFE";
          SRVAL_A : bit_vector := X"000000000000000000";
          SRVAL_B : bit_vector := X"000000000000000000";
          WRITE_MODE_A : string := "WRITE_FIRST";
          WRITE_MODE_B : string := "WRITE_FIRST";
          WRITE_WIDTH_A : integer := 0;
          WRITE_WIDTH_B : integer := 0;
          INIT_FILE : string := "NONE";
          INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
          INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
           );
	port
	(
          CASCADEOUTLATA : out std_ulogic;
          CASCADEOUTLATB : out std_ulogic;
          CASCADEOUTREGA : out std_ulogic;
          CASCADEOUTREGB : out std_ulogic;
          DBITERR : out std_ulogic;
          DOA : out std_logic_vector(63 downto 0);
          DOB : out std_logic_vector(63 downto 0);
          DOPA : out std_logic_vector(7 downto 0);
          DOPB : out std_logic_vector(7 downto 0);
          ECCPARITY : out std_logic_vector(7 downto 0);
          SBITERR : out std_ulogic;
    
          ADDRA : in std_logic_vector(15 downto 0);
          ADDRB : in std_logic_vector(15 downto 0);
          CASCADEINLATA : in std_ulogic;
          CASCADEINLATB : in std_ulogic;
          CASCADEINREGA : in std_ulogic;
          CASCADEINREGB : in std_ulogic;
          CLKA : in std_ulogic;
          CLKB : in std_ulogic;
          DIA : in std_logic_vector(63 downto 0);
          DIB : in std_logic_vector(63 downto 0);
          DIPA : in std_logic_vector(7 downto 0);
          DIPB : in std_logic_vector(7 downto 0);
          ENA : in std_ulogic;
          ENB : in std_ulogic;
          REGCEA : in std_ulogic;
          REGCEB : in std_ulogic;
          REGCLKA : in std_ulogic;
          REGCLKB : in std_ulogic;
          SSRA : in std_ulogic;
          SSRB : in std_ulogic;
          WEA : in std_logic_vector(7 downto 0);
          WEB : in std_logic_vector(7 downto 0)
 	);
  end component;

    
  constant SYNC_PATH_DELAY : time := 100 ps;
  signal GND_4 : std_logic_vector(3 downto 0) := (others => '0');
  signal GND_32 : std_logic_vector(31 downto 0) := (others => '0');
  signal OPEN_4 : std_logic_vector(3 downto 0);
  signal OPEN_32 : std_logic_vector(31 downto 0);
  signal doa_dly : std_logic_vector(31 downto 0) :=  (others => '0');
  signal dob_dly : std_logic_vector(31 downto 0) :=  (others => '0');
  signal dopa_dly : std_logic_vector(3 downto 0) :=  (others => '0');
  signal dopb_dly : std_logic_vector(3 downto 0) :=  (others => '0');
  signal cascadeoutlata_dly : std_ulogic := '0';
  signal cascadeoutlatb_dly : std_ulogic := '0';
  signal cascadeoutrega_dly : std_ulogic := '0';
  signal cascadeoutregb_dly : std_ulogic := '0';
  
begin

RAMB36_inst : ARAMB36_INTERNAL
	generic map (

                DOA_REG => DOA_REG,
                DOB_REG => DOB_REG,
		INIT_A  => INIT_A,
		INIT_B  => INIT_B,
                INIT_FILE => INIT_FILE,
                
		INIT_00 => INIT_00,
		INIT_01 => INIT_01,
		INIT_02 => INIT_02,
		INIT_03 => INIT_03,
		INIT_04 => INIT_04,
		INIT_05 => INIT_05,
		INIT_06 => INIT_06,
		INIT_07 => INIT_07,
		INIT_08 => INIT_08,
		INIT_09 => INIT_09,
		INIT_0A => INIT_0A,
		INIT_0B => INIT_0B,
		INIT_0C => INIT_0C,
		INIT_0D => INIT_0D,
		INIT_0E => INIT_0E,
		INIT_0F => INIT_0F,
		INIT_10 => INIT_10,
		INIT_11 => INIT_11,
		INIT_12 => INIT_12,
		INIT_13 => INIT_13,
		INIT_14 => INIT_14,
		INIT_15 => INIT_15,
		INIT_16 => INIT_16,
		INIT_17 => INIT_17,
		INIT_18 => INIT_18,
		INIT_19 => INIT_19,
		INIT_1A => INIT_1A,
		INIT_1B => INIT_1B,
		INIT_1C => INIT_1C,
		INIT_1D => INIT_1D,
		INIT_1E => INIT_1E,
		INIT_1F => INIT_1F,
		INIT_20 => INIT_20,
		INIT_21 => INIT_21,
		INIT_22 => INIT_22,
		INIT_23 => INIT_23,
		INIT_24 => INIT_24,
		INIT_25 => INIT_25,
		INIT_26 => INIT_26,
		INIT_27 => INIT_27,
		INIT_28 => INIT_28,
		INIT_29 => INIT_29,
		INIT_2A => INIT_2A,
		INIT_2B => INIT_2B,
		INIT_2C => INIT_2C,
		INIT_2D => INIT_2D,
		INIT_2E => INIT_2E,
		INIT_2F => INIT_2F,
		INIT_30 => INIT_30,
		INIT_31 => INIT_31,
		INIT_32 => INIT_32,
		INIT_33 => INIT_33,
		INIT_34 => INIT_34,
		INIT_35 => INIT_35,
		INIT_36 => INIT_36,
		INIT_37 => INIT_37,
		INIT_38 => INIT_38,
		INIT_39 => INIT_39,
		INIT_3A => INIT_3A,
		INIT_3B => INIT_3B,
		INIT_3C => INIT_3C,
		INIT_3D => INIT_3D,
		INIT_3E => INIT_3E,
		INIT_3F => INIT_3F,
		INIT_40 => INIT_40,
		INIT_41 => INIT_41,
		INIT_42 => INIT_42,
		INIT_43 => INIT_43,
		INIT_44 => INIT_44,
		INIT_45 => INIT_45,
		INIT_46 => INIT_46,
		INIT_47 => INIT_47,
		INIT_48 => INIT_48,
		INIT_49 => INIT_49,
		INIT_4A => INIT_4A,
		INIT_4B => INIT_4B,
		INIT_4C => INIT_4C,
		INIT_4D => INIT_4D,
		INIT_4E => INIT_4E,
		INIT_4F => INIT_4F,
		INIT_50 => INIT_50,
		INIT_51 => INIT_51,
		INIT_52 => INIT_52,
		INIT_53 => INIT_53,
		INIT_54 => INIT_54,
		INIT_55 => INIT_55,
		INIT_56 => INIT_56,
		INIT_57 => INIT_57,
		INIT_58 => INIT_58,
		INIT_59 => INIT_59,
		INIT_5A => INIT_5A,
		INIT_5B => INIT_5B,
		INIT_5C => INIT_5C,
		INIT_5D => INIT_5D,
		INIT_5E => INIT_5E,
		INIT_5F => INIT_5F,
		INIT_60 => INIT_60,
		INIT_61 => INIT_61,
		INIT_62 => INIT_62,
		INIT_63 => INIT_63,
		INIT_64 => INIT_64,
		INIT_65 => INIT_65,
		INIT_66 => INIT_66,
		INIT_67 => INIT_67,
		INIT_68 => INIT_68,
		INIT_69 => INIT_69,
		INIT_6A => INIT_6A,
		INIT_6B => INIT_6B,
		INIT_6C => INIT_6C,
		INIT_6D => INIT_6D,
		INIT_6E => INIT_6E,
		INIT_6F => INIT_6F,
		INIT_70 => INIT_70,
		INIT_71 => INIT_71,
		INIT_72 => INIT_72,
		INIT_73 => INIT_73,
		INIT_74 => INIT_74,
		INIT_75 => INIT_75,
		INIT_76 => INIT_76,
		INIT_77 => INIT_77,
		INIT_78 => INIT_78,
		INIT_79 => INIT_79,
		INIT_7A => INIT_7A,
		INIT_7B => INIT_7B,
		INIT_7C => INIT_7C,
		INIT_7D => INIT_7D,
		INIT_7E => INIT_7E,
		INIT_7F => INIT_7F,
                
		INITP_00 => INITP_00,
		INITP_01 => INITP_01,
		INITP_02 => INITP_02,
		INITP_03 => INITP_03,
		INITP_04 => INITP_04,
		INITP_05 => INITP_05,
		INITP_06 => INITP_06,
		INITP_07 => INITP_07,
		INITP_08 => INITP_08,
		INITP_09 => INITP_09,
		INITP_0A => INITP_0A,
		INITP_0B => INITP_0B,
		INITP_0C => INITP_0C,
		INITP_0D => INITP_0D,
		INITP_0E => INITP_0E,
		INITP_0F => INITP_0F,
                
		SIM_COLLISION_CHECK => SIM_COLLISION_CHECK,
                SIM_MODE => SIM_MODE,
		SRVAL_A => SRVAL_A,
		SRVAL_B => SRVAL_B,
		WRITE_MODE_A => WRITE_MODE_A,
		WRITE_MODE_B => WRITE_MODE_B,                
                BRAM_MODE => "TRUE_DUAL_PORT",
                BRAM_SIZE => 36,
                RAM_EXTENSION_A => RAM_EXTENSION_A,
                RAM_EXTENSION_B => RAM_EXTENSION_B,                
                READ_WIDTH_A => READ_WIDTH_A,
                READ_WIDTH_B => READ_WIDTH_B,                
                WRITE_WIDTH_A => WRITE_WIDTH_A,
                WRITE_WIDTH_B => WRITE_WIDTH_B          

                )
        port map (
                ADDRA => ADDRA,
                ADDRB => ADDRB,
                CLKA => CLKA,
                CLKB => CLKB,
                DIA(31 downto 0)  => DIA,
                DIA(63 downto 32) => GND_32,
                DIB(31 downto 0) => DIB,
                DIB(63 downto 32) => GND_32,
                DIPA(3 downto 0) => DIPA,
                DIPA(7 downto 4) => GND_4,
                DIPB(3 downto 0) => DIPB,
                DIPB(7 downto 4) => GND_4,
                ENA => ENA,
                ENB => ENB,
                SSRA => SSRA,
                SSRB => SSRB,
                WEA(3 downto 0) => WEA,
                WEA(7 downto 4) => GND_4,
                WEB(3 downto 0) => WEB,
                WEB(7 downto 4) => GND_4,
                DOA(31  downto 0) => doa_dly,
                DOA(63 downto 32) => OPEN_32,
                DOB(31 downto 0) => dob_dly,
                DOB(63 downto 32) => OPEN_32,
                DOPA(3 downto 0) => dopa_dly,
                DOPA(7 downto 4) => OPEN_4,
                DOPB(3 downto 0) => dopb_dly,
                DOPB(7 downto 4) => OPEN_4,
                CASCADEOUTLATA => cascadeoutlata_dly,
                CASCADEOUTLATB => cascadeoutlatb_dly,
                CASCADEOUTREGA => cascadeoutrega_dly,
                CASCADEOUTREGB => cascadeoutregb_dly,
                CASCADEINLATA => CASCADEINLATA,
                CASCADEINLATB => CASCADEINLATB,
                CASCADEINREGA => CASCADEINREGA,
                CASCADEINREGB => CASCADEINREGB,
                REGCLKA => CLKA,
                REGCLKB => CLKB,
                REGCEA => REGCEA,
                REGCEB => REGCEB
        );

   prcs_output_wtiming: process (doa_dly, dob_dly, dopa_dly, dopb_dly, cascadeoutlata_dly, cascadeoutlatb_dly, cascadeoutrega_dly, cascadeoutregb_dly )
   begin  -- process prcs_output_wtiming

     CASCADEOUTREGA <= cascadeoutrega_dly after SYNC_PATH_DELAY;
     CASCADEOUTREGB <= cascadeoutregb_dly after SYNC_PATH_DELAY;
     CASCADEOUTLATA <= cascadeoutlata_dly after SYNC_PATH_DELAY;
     CASCADEOUTLATB <= cascadeoutlatb_dly after SYNC_PATH_DELAY;
     DOA <= doa_dly after SYNC_PATH_DELAY;
     DOPA <= dopa_dly after SYNC_PATH_DELAY;
     DOB <= dob_dly after SYNC_PATH_DELAY;
     DOPB <= dopb_dly after SYNC_PATH_DELAY;

   end process prcs_output_wtiming;

end RAMB36_V;
------------------------------------------------------------------------------/
-- Copyright (c) 1995/2005 Xilinx, Inc.
-- All Right Reserved.
------------------------------------------------------------------------------/
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Function Simulation Library Component
--  /   /                  Configuration Simulation Model
-- /___/   /\     Filename : sim_config_v5.vhd
-- \   \  /  \    Timestamp : 
--  \___\/\___\
--
-- Revision:
--    07/23/07 - Initial version.
-- End Revision


----- CELL SIM_CONFIG_V5  -----
library IEEE;
use IEEE.std_logic_1164.all;




library STD;
use STD.TEXTIO.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity SIM_CONFIG_V5 is
  generic (

    DEVICE_ID : bit_vector := X"00000000"

    );

  port (
                   BUSY : out std_ulogic := '0';
                   CSOB : out std_ulogic := '1';
                   DONE : inout std_ulogic := '0';
                   CCLK : in  std_ulogic := '0';
                   CSB : in  std_ulogic := '0';
                   D : inout std_logic_vector(31 downto 0);
                   DCMLOCK : in  std_ulogic := '0';
                   INITB : inout std_ulogic := 'H';
                   M : in  std_logic_vector(2 downto 0) := "000";
                   PROGB : in  std_ulogic := '0';
                   RDWRB : in  std_ulogic := '0'
                   );



end SIM_CONFIG_V5;


architecture SIM_CONFIG_V5_V of SIM_CONFIG_V5 is

function  crc_next (
   crc_currf : in std_logic_vector(31 downto 0);
   crc_inputf : in std_logic_vector(36 downto 0)
 ) return  std_logic_vector
   is
      variable x : std_logic_vector(31 downto 0);
      variable m : std_logic_vector(36 downto 0);
      variable bcc_next : std_logic_vector(31 downto 0);
  begin
 m := crc_inputf;
 x := crc_inputf(31 downto 0)  xor  crc_currf(31 downto 0);

 bcc_next(31) := m(32) xor m(36) xor x(31) xor x(30) xor x(29) xor x(28) xor x(27) xor x(24) xor x(20) xor x(19) xor x(18) xor x(15) xor x(13) xor x(11) xor x(10) xor x(9) xor x(8) xor x(6) xor x(5) xor x(1) xor x(0);

 bcc_next(30) := m(35) xor x(31) xor x(30) xor x(29) xor x(28) xor x(27) xor x(26) xor x(23) xor x(19) xor x(18) xor x(17) xor x(14) xor x(12) xor x(10) xor x(9) xor x(8) xor x(7) xor x(5) xor x(4) xor x(0);

 bcc_next(29) := m(34) xor x(30) xor x(29) xor x(28) xor x(27) xor x(26) xor x(25) xor x(22) xor x(18) xor x(17) xor x(16) xor x(13) xor x(11) xor x(9) xor x(8) xor x(7) xor x(6) xor x(4) xor x(3);

 bcc_next(28) := m(33) xor x(29) xor x(28) xor x(27) xor x(26) xor x(25) xor x(24) xor x(21) xor x(17) xor x(16) xor x(15) xor x(12) xor x(10) xor x(8) xor x(7) xor x(6) xor x(5) xor x(3) xor x(2);

 bcc_next(27) := m(32) xor x(28) xor x(27) xor x(26) xor x(25) xor x(24) xor x(23) xor x(20) xor x(16) xor x(15) xor x(14) xor x(11) xor x(9) xor x(7) xor x(6) xor x(5) xor x(4) xor x(2) xor x(1);

 bcc_next(26) := x(31) xor x(27) xor x(26) xor x(25) xor x(24) xor x(23) xor x(22) xor x(19) xor x(15) xor x(14) xor x(13) xor x(10) xor x(8) xor x(6) xor x(5) xor x(4) xor x(3) xor x(1) xor x(0);

 bcc_next(25) := m(32) xor m(36) xor x(31) xor x(29) xor x(28) xor x(27) xor x(26) xor x(25) xor x(23) xor x(22) xor x(21) xor x(20) xor x(19) xor x(15) xor x(14) xor x(12) xor x(11) xor x(10) xor x(8) xor x(7) xor x(6) xor x(4) xor x(3) xor x(2) xor x(1);

 bcc_next(24) := m(35) xor x(31) xor x(30) xor x(28) xor x(27) xor x(26) xor x(25) xor x(24) xor x(22) xor x(21) xor x(20) xor x(19) xor x(18) xor x(14) xor x(13) xor x(11) xor x(10) xor x(9) xor x(7) xor x(6) xor x(5) xor x(3) xor x(2) xor x(1) xor x(0);

 bcc_next(23) := m(32) xor m(34) xor m(36) xor x(31) xor x(28) xor x(26) xor x(25) xor x(23) xor x(21) xor x(17) xor x(15) xor x(12) xor x(11) xor x(4) xor x(2);

 bcc_next(22) := m(32) xor m(33) xor m(35) xor m(36) xor x(29) xor x(28) xor x(25) xor x(22) xor x(19) xor x(18) xor x(16) xor x(15) xor x(14) xor x(13) xor x(9) xor x(8) xor x(6) xor x(5) xor x(3) xor x(0);

 bcc_next(21) := m(34) xor m(35) xor m(36) xor x(30) xor x(29) xor x(21) xor x(20) xor x(19) xor x(17) xor x(14) xor x(12) xor x(11) xor x(10) xor x(9) xor x(7) xor x(6) xor x(4) xor x(2) xor x(1) xor x(0);

 bcc_next(20) := m(32) xor m(33) xor m(34) xor m(35) xor m(36) xor x(31) xor x(30) xor x(27) xor x(24) xor x(16) xor x(15) xor x(3);

 bcc_next(19) := m(32) xor m(33) xor m(34) xor m(35) xor x(31) xor x(30) xor x(29) xor x(26) xor x(23) xor x(15) xor x(14) xor x(2);

 bcc_next(18) := m(33) xor m(34) xor m(36) xor x(27) xor x(25) xor x(24) xor x(22) xor x(20) xor x(19) xor x(18) xor x(15) xor x(14) xor x(11) xor x(10) xor x(9) xor x(8) xor x(6) xor x(5) xor x(0);

 bcc_next(17) := m(33) xor m(35) xor m(36) xor x(31) xor x(30) xor x(29) xor x(28) xor x(27) xor x(26) xor x(23) xor x(21) xor x(20) xor x(17) xor x(15) xor x(14) xor x(11) xor x(7) xor x(6) xor x(4) xor x(1) xor x(0);

 bcc_next(16) := m(32) xor m(34) xor m(35) xor x(30) xor x(29) xor x(28) xor x(27) xor x(26) xor x(25) xor x(22) xor x(20) xor x(19) xor x(16) xor x(14) xor x(13) xor x(10) xor x(6) xor x(5) xor x(3) xor x(0);

 bcc_next(15) := m(33) xor m(34) xor x(31) xor x(29) xor x(28) xor x(27) xor x(26) xor x(25) xor x(24) xor x(21) xor x(19) xor x(18) xor x(15) xor x(13) xor x(12) xor x(9) xor x(5) xor x(4) xor x(2);

 bcc_next(14) := m(32) xor m(33) xor x(30) xor x(28) xor x(27) xor x(26) xor x(25) xor x(24) xor x(23) xor x(20) xor x(18) xor x(17) xor x(14) xor x(12) xor x(11) xor x(8) xor x(4) xor x(3) xor x(1);

 bcc_next(13) := m(36) xor x(30) xor x(28) xor x(26) xor x(25) xor x(23) xor x(22) xor x(20) xor x(18) xor x(17) xor x(16) xor x(15) xor x(9) xor x(8) xor x(7) xor x(6) xor x(5) xor x(3) xor x(2) xor x(1);

 bcc_next(12) := m(32) xor m(35) xor m(36) xor x(31) xor x(30) xor x(28) xor x(25) xor x(22) xor x(21) xor x(20) xor x(18) xor x(17) xor x(16) xor x(14) xor x(13) xor x(11) xor x(10) xor x(9) xor x(7) xor x(4) xor x(2);

 bcc_next(11) := m(32) xor m(34) xor m(35) xor m(36) xor x(28) xor x(21) xor x(18) xor x(17) xor x(16) xor x(12) xor x(11) xor x(5) xor x(3) xor x(0);

 bcc_next(10) := m(33) xor m(34) xor m(35) xor x(31) xor x(27) xor x(20) xor x(17) xor x(16) xor x(15) xor x(11) xor x(10) xor x(4) xor x(2);

 bcc_next(9) := m(33) xor m(34) xor m(36) xor x(31) xor x(29) xor x(28) xor x(27) xor x(26) xor x(24) xor x(20) xor x(18) xor x(16) xor x(14) xor x(13) xor x(11) xor x(8) xor x(6) xor x(5) xor x(3) xor x(0);

 bcc_next(8) := m(33) xor m(35) xor m(36) xor x(31) xor x(29) xor x(26) xor x(25) xor x(24) xor x(23) xor x(20) xor x(18) xor x(17) xor x(12) xor x(11) xor x(9) xor x(8) xor x(7) xor x(6) xor x(4) xor x(2) xor x(1) xor x(0);

 bcc_next(7) := m(32) xor m(34) xor m(35) xor x(30) xor x(28) xor x(25) xor x(24) xor x(23) xor x(22) xor x(19) xor x(17) xor x(16) xor x(11) xor x(10) xor x(8) xor x(7) xor x(6) xor x(5) xor x(3) xor x(1) xor x(0);

 bcc_next(6) := m(32) xor m(33) xor m(34) xor m(36) xor x(30) xor x(28) xor x(23) xor x(22) xor x(21) xor x(20) xor x(19) xor x(16) xor x(13) xor x(11) xor x(8) xor x(7) xor x(4) xor x(2) xor x(1);

 bcc_next(5) := m(33) xor m(35) xor m(36) xor x(30) xor x(28) xor x(24) xor x(22) xor x(21) xor x(13) xor x(12) xor x(11) xor x(9) xor x(8) xor x(7) xor x(5) xor x(3);

 bcc_next(4) := m(34) xor m(35) xor m(36) xor x(31) xor x(30) xor x(28) xor x(24) xor x(23) xor x(21) xor x(19) xor x(18) xor x(15) xor x(13) xor x(12) xor x(9) xor x(7) xor x(5) xor x(4) xor x(2) xor x(1) xor x(0);

 bcc_next(3) := m(32) xor m(33) xor m(34) xor m(35) xor m(36) xor x(31) xor x(28) xor x(24) xor x(23) xor x(22) xor x(19) xor x(17) xor x(15) xor x(14) xor x(13) xor x(12) xor x(10) xor x(9) xor x(5) xor x(4) xor x(3);

 bcc_next(2) := m(32) xor m(33) xor m(34) xor m(35) xor x(31) xor x(30) xor x(27) xor x(23) xor x(22) xor x(21) xor x(18) xor x(16) xor x(14) xor x(13) xor x(12) xor x(11) xor x(9) xor x(8) xor x(4) xor x(3) xor x(2);

 bcc_next(1) := m(32) xor m(33) xor m(34) xor x(31) xor x(30) xor x(29) xor x(26) xor x(22) xor x(21) xor x(20) xor x(17) xor x(15) xor x(13) xor x(12) xor x(11) xor x(10) xor x(8) xor x(7) xor x(3) xor x(2) xor x(1);

 bcc_next(0) := m(32) xor m(33) xor x(31) xor x(30) xor x(29) xor x(28) xor x(25) xor x(21) xor x(20) xor x(19) xor x(16) xor x(14) xor x(12) xor x(11) xor x(10) xor x(9) xor x(7) xor x(6) xor x(2) xor x(1) xor x(0);

 return bcc_next;

end crc_next;

function bit_revers8 ( din8 : in std_logic_vector(7 downto 0))
                   return  std_logic_vector is
  variable bit_rev8 : std_logic_vector(7 downto 0);
  begin
      bit_rev8(0) := din8(7);
      bit_rev8(1) := din8(6);
      bit_rev8(2) := din8(5);
      bit_rev8(3) := din8(4);
      bit_rev8(4) := din8(3);
      bit_rev8(5) := din8(2);
      bit_rev8(6) := din8(1);
      bit_rev8(7) := din8(0);

     return bit_rev8;
  end bit_revers8;

  constant cfg_Tprog : time := 300000 ps;   -- min PROG must be low, 300 ns
  constant cfg_Tpl : time :=   100000 ps;  -- max program latency us.
  constant STARTUP_PH0 : std_logic_vector(2 downto 0) := "000";
  constant STARTUP_PH1 : std_logic_vector(2 downto 0) := "001";
  constant STARTUP_PH2 : std_logic_vector(2 downto 0) := "010";
  constant STARTUP_PH3 : std_logic_vector(2 downto 0) := "011";
  constant STARTUP_PH4 : std_logic_vector(2 downto 0) := "100";
  constant STARTUP_PH5 : std_logic_vector(2 downto 0) := "101";
  constant STARTUP_PH6 : std_logic_vector(2 downto 0) := "110";
  constant STARTUP_PH7 : std_logic_vector(2 downto 0) := "111";
  signal GSR : std_ulogic := '1';
  signal GTS : std_ulogic := '1';
  signal GWE : std_ulogic := '0';
  signal cclk_in : std_ulogic;
  signal init_b_in : std_ulogic;
  signal prog_b_in : std_ulogic;
  signal rdwr_b_in : std_ulogic;
  signal init_b_out  : std_ulogic :=  '1';
  signal done_o  : std_ulogic :=  '0';
  signal por_b : std_ulogic := '0';
  signal m_in  : std_logic_vector (2 downto 0) ; 
  signal d_in  : std_logic_vector (31 downto 0) ; 
  signal d_out  : std_logic_vector (31 downto 0) ; 
  signal busy_out : std_ulogic;
  signal cso_b_out : std_ulogic;
  signal csi_b_in : std_ulogic;
  signal d_out_en : std_ulogic;
  signal dcm_locked : std_ulogic;
  signal init_b_t : std_ulogic;
  signal prog_b_t : std_ulogic;
  signal bus_en : std_ulogic;
  signal desync_flag : std_ulogic;
  signal crc_rst : std_ulogic;

  signal  prog_pulse_low_edge  : time :=  0 ps;
  signal  prog_pulse_low  : time :=  0 ps;
  signal  mode_sample_flag  : std_ulogic :=  '0';
  signal  buswid_flag_init  : std_ulogic :=  '0';
  signal  buswid_flag  : std_ulogic :=  '0';
  signal buswidth : std_logic_vector (1 downto 0) :=  "00"; 
  signal pack_in_reg : std_logic_vector (31 downto 0) :=  X"00000000";
  signal reg_addr  : std_logic_vector (4 downto 0) ; 
  signal  new_data_in_flag   : std_ulogic :=  '0';
  signal  wr_flag   : std_ulogic :=  '0';
  signal  rd_flag   : std_ulogic :=  '0';
  signal  cmd_wr_flag   : std_ulogic :=  '0';
  signal  cmd_reg_new_flag  : std_ulogic :=  '0';
  signal  cmd_rd_flag   : std_ulogic :=  '0';
  signal  bus_sync_flag  : std_ulogic :=  '0';
  signal  conti_data_flag  : std_ulogic :=  '0';
  signal  wr_cnt   : integer :=  0;
  signal  conti_data_cnt  : integer :=  0;
  signal  rd_data_cnt  : integer :=  0;
  signal  abort_cnt  : integer :=  0;
  signal st_state : std_logic_vector (2 downto 0) :=  STARTUP_PH0; 
  signal  startup_begin_flag  : std_ulogic :=  '0';
  signal  startup_end_flag  : std_ulogic :=  '0';
  signal  crc_ck  : std_ulogic :=  '0';
  signal crc_err_flag  : std_ulogic :=  '0';
  signal crc_err_flag_tot : std_ulogic;
  signal crc_err_flag_reg  : std_ulogic :=  '0';
  signal  crc_en : std_ulogic;
  signal crc_curr : std_logic_vector (31 downto 0) :=  X"00000000";
  signal  gwe_out  : std_ulogic :=  '0';
  signal  gts_out  : std_ulogic :=  '1';
  signal outbus : std_logic_vector (7 downto 0) :=  "00000000";
  signal  busy_o  : std_ulogic :=  '0';
  signal tmp_val1  : std_logic_vector (31 downto 0) ; 
  signal ctl0_reg : std_logic_vector (31 downto 0) :=  "X0XXXXXXXXXXXXXXXXXXX001X0000XX1"; 
  signal cor0_reg : std_logic_vector (31 downto 0) :=  "00000X0000000000X011111111101100"; 
  signal cor1_reg : std_logic_vector (31 downto 0) :=  X"00000000";
  signal wbstar_reg : std_logic_vector (31 downto 0) :=  X"00000000";
  signal timer_reg : std_logic_vector (31 downto 0) :=  X"00000000";
  signal bootsts_reg : std_logic_vector (31 downto 0) :=  X"00000000";
  signal crc_reg  : std_logic_vector (31 downto 0) ; 
  signal far_reg  : std_logic_vector (31 downto 0) ; 
  signal fdri_reg  : std_logic_vector (31 downto 0) ; 
  signal mask_reg  : std_logic_vector (31 downto 0) ; 
  signal lout_reg  : std_logic_vector (31 downto 0) ; 
  signal mfwr_reg  : std_logic_vector (31 downto 0) ; 
  signal cbc_reg  : std_logic_vector (31 downto 0) ; 
  signal idcode_reg  : std_logic_vector (31 downto 0) ; 
  signal csob_reg  : std_logic_vector (31 downto 0) ; 
  signal ctl1_reg  : std_logic_vector (31 downto 0) ; 
  signal axss_reg  : std_logic_vector (31 downto 0) ; 
  signal cmd_reg  : std_logic_vector (4 downto 0) ; 
  signal mode_pin_in : std_logic_vector (2 downto 0) :=  "000"; 
  signal mode_reg  : std_logic_vector (2 downto 0) ; 
  signal  crc_reset  : std_ulogic :=  '0';
  signal  gsr_set  : std_ulogic :=  '0';
  signal  gts_usr_b  : std_ulogic :=  '1';
  signal  done_pin_drv  : std_ulogic :=  '0';
  
  signal  shutdown_set  : std_ulogic :=  '0';
  signal  desynch_set  : std_ulogic :=  '0';
  signal done_cycle_reg  : std_logic_vector (2 downto 0) ; 
  signal gts_cycle_reg  : std_logic_vector (2 downto 0) ; 
  signal gwe_cycle_reg  : std_logic_vector (2 downto 0) ; 
  signal  init_pin : std_ulogic;
  signal  init_rst  : std_ulogic :=  '0';
  signal  init_complete : std_ulogic; 
  signal nx_st_state : std_logic_vector (2 downto 0) :=  "000"; 
  signal  ghigh_b  : std_ulogic :=  '0';
  signal  gts_cfg_b  : std_ulogic :=  '0';
  signal  eos_startup  : std_ulogic :=  '0';
  signal startup_set  : std_ulogic :=  '0';
  signal startup_set_pulse : std_logic_vector (1 downto 0) :=  "00"; 
  signal abort_out_en  : std_ulogic :=  '0';
  signal tmp_dword  : std_logic_vector (31 downto 0) ; 
  signal id_error_flag  : std_ulogic :=  '0';
  signal iprog_b  : std_ulogic :=  '1';
  signal i_init_b_cmd  : std_ulogic :=  '1';
  signal i_init_b  : std_ulogic :=  '0';
  signal abort_flag_wr  : std_ulogic :=  '0';
  signal abort_flag_rd  : std_ulogic :=  '0';
  signal abort_status : std_logic_vector (7 downto 0) :=  "00000000"; 
  signal persist_en  : std_ulogic :=  '0';
  signal rst_sync  : std_ulogic :=  '0';
  signal abort_dis  : std_ulogic :=  '0';
  signal lock_cycle_reg : std_logic_vector (2 downto 0) :=  "000"; 
  signal rbcrc_no_pin  : std_ulogic :=  '0';
  signal abort_flag_rst  : std_ulogic :=  '0';
  signal gsr_st_out  : std_ulogic :=  '1'; 
  signal gsr_cmd_out  : std_ulogic :=  '0';
  signal gsr_cmd_out_pulse  : std_ulogic :=  '0';
  signal d_o_en  : std_ulogic :=  '0';
  signal stat_reg  : std_logic_vector (31 downto 0) ; 
  signal rst_intl : std_ulogic;
  signal rw_en : std_ulogic;
  signal gsr_out : std_ulogic;
  signal cfgerr_b_flag : std_ulogic;
  signal abort_flag : std_ulogic;
  signal downcont_cnt  : integer :=  0;
--  signal rst_en  : std_ulogic :=  '1';
  signal rst_en  : std_ulogic :=  '0';
  signal prog_b_a  : std_ulogic :=  '1';
  signal csbo_flag  : std_ulogic :=  '0';
  signal crc_bypass  : std_ulogic :=  '0';
  signal csi_sync  : std_ulogic :=  '0';
  signal rd_sw_en  : std_ulogic :=  '0';
  signal csbo_cnt  : integer :=  0;
  signal rd_reg_addr : std_logic_vector (4 downto 0) :=  "00000"; 
  signal init_b_p : std_ulogic :=  '0';
  signal done_in : std_ulogic :=  '0';
  
begin
   INITB <=  (not crc_err_flag_tot) when mode_sample_flag = '1' else init_b_out when init_b_out ='0' else 'H';

    DONE <= done_o;
    done_in <= DONE;

   BUSY <= busy_out;
   CSOB <= cso_b_out;
   cclk_in <= CCLK;
   csi_b_in <= CSB;

   d_in <= D;
   D <=  d_out when d_out_en = '1' else "HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH";
   dcm_locked <= DCMLOCK;

   init_b_in <= INITB;
   m_in <= M;
   prog_b_in <= PROGB;
   rdwr_b_in <= RDWRB;

        INIPROC : process
        begin
          if (DEVICE_ID = X"00000000") then
             assert FALSE report "Attribute Syntax Error : The attribute DEVICE_ID on  SIM_CONFIG_V5 is not set." severity error;
          end if;
          wait;
        end process;

    GSR <= gsr_out;
    GTS <= gts_out;
    GWE <= gwe_out;
    busy_out <= busy_o;
    cfgerr_b_flag <= rw_en  and   not crc_err_flag_tot;
    crc_err_flag_tot <= id_error_flag  or  crc_err_flag_reg;
    d_out(7 downto 0) <=  abort_status when (abort_out_en = '1') else outbus;
    d_out_en <= d_o_en;
    cso_b_out <= '0' when (csbo_flag= '1') else '1';
    crc_en <=  '1';

   process (csi_b_in, abort_flag) begin
        if (csi_b_in = '1')  then
           busy_o <= '1';
        else
          if (abort_flag = '1') then
            busy_o <= '1';
          else
            busy_o <= '0';
          end if;
        end if;
   end process;

   process (abort_out_en, csi_b_in, rdwr_b_in, rd_flag ) begin
    if (abort_out_en = '1') then
       d_o_en <= '1';
    else
       d_o_en <= rdwr_b_in  and  (not csi_b_in)  and  rd_flag;
    end if;
    end process;


   init_b_t <= init_b_in  and  i_init_b_cmd;

  process (rst_en, init_rst, prog_b_in, iprog_b)
  begin
   if (init_rst = '1') then
       init_b_out <= '0';
   else
     if ((rst_en = '1' and prog_b_in  =  '0') or iprog_b = '0' ) then
         init_b_out <= '0';
     elsif ((rst_en = '1' and prog_b_in  =  '1') or iprog_b = '1') then
         init_b_out <= '1' after cfg_Tpl;
     end if;
   end if;
--   wait on rst_en, init_rst, prog_b_in, iprog_b;
   end process;

  process  begin
     if  (rising_edge(id_error_flag)) then
      init_rst <= '1';
      init_rst <= '0' after cfg_Tprog;
     end if;
   wait on id_error_flag;
  end process;
  
    process  
    variable rst_en_v : std_ulogic;
    begin
      if (prog_b_in'event and prog_b_in = '0') then
         rst_en_v := '0';
         rst_en <= '0';
         wait for cfg_Tprog;
         wait for 1 ps;
         rst_en_v := '1';
         rst_en <= '1';
      end if;
    if (rst_en_v = '1') then
       if (prog_pulse_low  =  cfg_Tprog) then
           prog_b_a <= '0';
           prog_b_a <= '1' after 500 ps;
       else
          prog_b_a <= prog_b_in;
       end if;
    else 
          prog_b_a <= '1';
    end if;
     wait on prog_b_in, prog_pulse_low;
  end process;

   process begin
    por_b <= '0';
    por_b <= '1' after 400 ns;
    wait;
  end process; 

   prog_b_t <= prog_b_a   and  iprog_b  and  por_b;

   rst_intl <= '0' when (prog_b_t  =  '0' ) else '1';

  process (init_b_t, prog_b_t)
    variable Message : line;
  begin
   if (falling_edge (prog_b_t)) then
      mode_sample_flag <= '0';
   elsif (init_b_t'event and init_b_t = '1') then
      if (mode_sample_flag = '0') then
        if(prog_b_t = '1') then
           mode_pin_in <= m_in;
           mode_sample_flag <= '1' after 1 ps;
           if (m_in /= "110") then
              Write ( Message, string'(" Error: input M is "));
              Write ( Message, string'(SLV_TO_STR(m_in)));
              Write ( Message, string'(" . Only Slave SelectMAP mode M=110 supported on SIM_CONFIG_V5."));
              assert false report Message.all severity error;
              DEALLOCATE (Message);
           end if;
        elsif (NOW > 0 ps) then
            assert false report "Error: PROGB is not high when INITB goes high on SIM_CONFIG_V5." severity error;
       end if;
    end if;
   end if;
  end process;

  process (m_in) begin
    if (mode_sample_flag = '1' and persist_en = '1') then
       assert false report "Error : Mode pine M[2:0] changed after rising edge of INITB on SIM_CONFIG_V5." severity error;
    end if;
  end process;

  prog_pulse_P : process (prog_b_in)
     variable prog_pulse_low_v : time;
--     variable prog_pulse_low : time;
     variable Message : line;
  begin
    if (falling_edge (prog_b_in)) then
       prog_pulse_low_edge <= NOW;
    else
      if (NOW > 0 ps ) then
         prog_pulse_low_v := NOW - prog_pulse_low_edge;
         prog_pulse_low <= NOW - prog_pulse_low_edge;
         if (prog_pulse_low_v < cfg_Tprog ) then
             Write ( Message, string'(" Error: Low time of PROGB is less than required minimum Tprogram time "));
             Write ( Message, prog_pulse_low_v);
             Write ( Message, string'(" ."));
             assert false report Message.all severity error;
             DEALLOCATE(Message);
         end if;
      end if;
    end if;
  end process;

     bus_en <= '1' when (mode_sample_flag  =  '1'  and   csi_b_in  = '0') else '0';

    process (cclk_in,  rst_intl)
       variable tmp_byte : std_logic_vector (7 downto 0);
    begin
      if (rst_intl  = '0') then
         buswid_flag_init <= '0';
         buswid_flag <= '0';
         buswidth <= "00";
      elsif (rising_edge(cclk_in)) then
        if (buswid_flag  =  '0') then
           if (bus_en = '1'  and  rdwr_b_in  =  '0')  then
                 tmp_byte := bit_revers8(d_in(7 downto 0));
                 if (buswid_flag_init  =  '0') then
                     if (tmp_byte  =  X"BB") then
                         buswid_flag_init <= '1';
                     end if;
                  else 
                     if (tmp_byte  =  X"11") then
                         buswid_flag <= '1'; 
                         buswidth <= "01";
                     elsif (tmp_byte  =  X"22") then
                         buswid_flag <= '1'; 
                         buswidth <= "10";
                     elsif (tmp_byte  =  X"44") then
                         buswid_flag <= '1'; 
                         buswidth <= "11";
                     else 
                         buswid_flag <= '0'; 
                         buswidth <= "00";
                         buswid_flag_init <= '0';
             assert false report 
                         "Error : BUS Width Auto Dection did not find 0x11 or 0x22 or 0x44 on D(7:0) followed 0xBB on SIM_CONFIG_V5."
              severity error;
                     end if;
                 end if;
            end if;
         end if;
     end if;
     end process;
 
     rw_en <=  '1' when (bus_en  =  '1'  and  buswid_flag  =  '1') else '0';
     desync_flag <=  (not rst_intl)  or  desynch_set  or  crc_err_flag  or  id_error_flag;

   process (cclk_in) begin
   if (rising_edge(cclk_in)) then
       csi_sync <= csi_b_in;
     end if;
   end process;

   process (cclk_in, rdwr_b_in) begin
      if (rdwr_b_in = '0') then
           rd_sw_en <= '0';
      elsif (rising_edge(cclk_in)) then
           if (csi_sync = '1' and rdwr_b_in = '1') then
              rd_sw_en <= '1';
           end if;
      end if;
   end process;


    bus_sync_p : process (cclk_in, desync_flag)
      variable tmp_byte  : std_logic_vector (7 downto 0);
      variable tmp_word  : std_logic_vector (15 downto 0);
      variable tmp_dword  : std_logic_vector (31 downto 0);
    begin
      if (desync_flag = '1') then
          pack_in_reg <= X"00000000";
          new_data_in_flag <= '0';
          bus_sync_flag <= '0';
          wr_cnt <= 0;
          wr_flag <= '0';
          rd_flag <= '0';
      elsif (rising_edge(cclk_in)) then
       if (rw_en  =  '1' ) then
         if (rdwr_b_in  =  '0') then
           wr_flag <= '1';
           rd_flag <= '0';
           if (buswidth  =  "01") then
               tmp_byte := bit_revers8(d_in(7 downto 0));
               if (bus_sync_flag  =  '0') then
                  if (pack_in_reg(23 downto 16) = X"AA" and pack_in_reg(15 downto 8) = X"99"
                       and  pack_in_reg(7 downto 0)  =  X"55"  and  tmp_byte = X"66") then
                          bus_sync_flag <= '1';
                          new_data_in_flag <= '0';
                          wr_cnt <= 0;
                   else 
                      pack_in_reg(31 downto 24) <= pack_in_reg(23 downto 16);
                      pack_in_reg(23 downto 16) <= pack_in_reg(15 downto 8);
                      pack_in_reg(15 downto 8) <= pack_in_reg(7 downto 0);
                      pack_in_reg(7 downto 0) <= tmp_byte;
                   end if;
               else 
                 if (wr_cnt  =  0) then
                    pack_in_reg(31 downto 24) <= tmp_byte;
                     new_data_in_flag <= '0';
                     wr_cnt <=  1;
                 elsif (wr_cnt  =  1) then
                     pack_in_reg(23 downto 16) <= tmp_byte;
                     new_data_in_flag <= '0';
                     wr_cnt <= 2;
                 elsif (wr_cnt  =  2) then
                     pack_in_reg(15 downto 8) <= tmp_byte;
                     new_data_in_flag <= '0';
                     wr_cnt <= 3;
                 elsif (wr_cnt  =  3) then
                     pack_in_reg(7 downto 0) <= tmp_byte;
                     new_data_in_flag <= '1';
                     wr_cnt <= 0;
                 end if;
             end if;
           elsif (buswidth  =  "10") then
             tmp_word := bit_revers8(d_in(15 downto 8)) & bit_revers8(d_in(7 downto 0));
             if (bus_sync_flag  =  '0') then
                if (pack_in_reg(15 downto 0)  =  X"AA99"  and  tmp_word  = X"5566") then
                     wr_cnt <= 0;
                     bus_sync_flag <= '1';
                     new_data_in_flag <= '0';
                else 
                   pack_in_reg(31 downto 16) <= pack_in_reg(15 downto 0);
                   pack_in_reg(15 downto 0) <= tmp_word;
                   new_data_in_flag <= '0';
                   wr_cnt <= 0;
                end if;
             else 
               if (wr_cnt  =  0) then
                   pack_in_reg(31 downto 16) <= tmp_word;
                   new_data_in_flag <= '0';
                   wr_cnt <= 1;
               elsif (wr_cnt  =  1) then
                   pack_in_reg(15 downto 0) <= tmp_word;
                   new_data_in_flag <= '1';
                   wr_cnt <= 0;
               end if;
             end if;
           elsif (buswidth  =  "11" ) then
             tmp_dword := bit_revers8(d_in(31 downto 24)) & bit_revers8(d_in(23 downto 16)) &
                          bit_revers8(d_in(15 downto 8)) &  bit_revers8(d_in(7 downto 0));
             pack_in_reg(31 downto 0) <= tmp_dword;
             if (bus_sync_flag  =  '0') then
                if (tmp_dword  =  X"AA995566") then
                     bus_sync_flag <= '1';
                     new_data_in_flag <= '0';
                end if;
             else
                pack_in_reg(31 downto 0) <= tmp_dword;
                new_data_in_flag <= '1';
             end if;
           end if;  -- end buswidth check
       else 
            wr_flag <= '0';
            new_data_in_flag <= '0';
            if (rd_sw_en  = '1') then
               rd_flag <= '1';
            end if;
       end if; -- end rdwr check
     else 
            wr_flag <= '0';
            rd_flag <= '0';
            new_data_in_flag <= '0';
     end if;
   end if;
   end process;
           
   pack_decode_p :  process (cclk_in, rst_intl)
      variable tmp_v : std_logic_vector(5 downto 0);
      variable tmp_v27 : std_logic_vector(26 downto 0);
      variable tmp_v11 : std_logic_vector(10 downto 0);
      variable tmp_v1 : std_logic_vector(27 downto 0);
      variable tmp_v2 : std_logic_vector(31 downto 0);
      variable tmp_v3 : std_logic_vector(27 downto 0);
      variable message_line : line;
--      variable csbo_cnt : integer := 0;
      variable crc_new : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
      variable crc_input : std_logic_vector(36 downto 0) := "0000000000000000000000000000000000000";
   begin
      if (rst_intl  = '0') then
         conti_data_flag <= '0';
         conti_data_cnt <= 0;
         cmd_wr_flag <= '0';
         cmd_rd_flag <= '0';
         id_error_flag <= '0';
         crc_curr <= X"00000000";
         crc_ck <= '0';
         csbo_cnt <= 0;
         csbo_flag <= '0';
         downcont_cnt <= 0;
         rd_data_cnt <= 0;
      elsif (falling_edge(cclk_in)) then
        if (crc_reset  =  '1' ) then
            crc_reg <= X"00000000";
            crc_ck <= '0';
            crc_curr <= X"00000000";
        end if;
        if (crc_ck  =  '1') then
             crc_curr <= X"00000000";
        end if;
        if (desynch_set = '1'  or  crc_err_flag = '1') then
           conti_data_flag <= '0';
           conti_data_cnt <= 0;
           cmd_wr_flag <= '0';
           cmd_rd_flag <= '0';
           cmd_reg_new_flag <= '0';
           crc_ck <= '0';
           csbo_cnt <= 0;
           csbo_flag <= '0';
           downcont_cnt <= 0;
           rd_data_cnt <= 0;
        end if;

        if (new_data_in_flag = '1'  and  wr_flag = '1') then
           if (conti_data_flag  =  '1' ) then
               case (reg_addr) is
               when "00000" =>  crc_reg <= pack_in_reg;
                                crc_ck <= '1';
               when "00001" => far_reg <= pack_in_reg;
               when "00010" => fdri_reg <= pack_in_reg;
               when "00100" => cmd_reg <= pack_in_reg(4 downto 0);
               when "00101" => ctl0_reg <= (pack_in_reg and mask_reg) or (ctl0_reg and not mask_reg);
               when "00110" => mask_reg <= pack_in_reg;
               when "01000" => lout_reg <= pack_in_reg;
               when "01001" => cor0_reg <= pack_in_reg;
               when "01010" => mfwr_reg <= pack_in_reg;
--               when "01101" => cbc_reg <= pack_in_reg;
               when "01100" => idcode_reg <= pack_in_reg;
                          tmp_v1 := pack_in_reg(27 downto 0);
                          tmp_v2 := TO_STDLOGICVECTOR(DEVICE_ID);
                          tmp_v3 := tmp_v2(27 downto 0);
--                          if (pack_in_reg(27 downto 0)  /=  DEVICE_ID(27 downto 0)) then
                          if (tmp_v1  /=  tmp_v3) then
                             id_error_flag <= '1';
                                write(message_line, string'("Error : written value to IDCODE register is "));
                                write(message_line, string'(SLV_TO_STR(tmp_v1)));
                                write(message_line, string'(" which does not match DEVICE ID "));
                                write(message_line, string'(SLV_TO_STR(tmp_v2)));
                                write(message_line, string'("."));
                                assert false report message_line.all  severity error;
                                DEALLOCATE(message_line);
                          else
                             id_error_flag <= '0';
                          end if;
               when "01101" => axss_reg <= pack_in_reg;
               when "01110" => cor1_reg <= pack_in_reg;
               when "01111" => csob_reg <= pack_in_reg;
               when "10000" => wbstar_reg <= pack_in_reg;
               when "10001" => timer_reg <= pack_in_reg;
               when "11000" => ctl1_reg <= (pack_in_reg and mask_reg) or (ctl1_reg and not mask_reg);
               when others => NULL;
               end case;
   
             if (reg_addr  /=  "00000") then
                crc_ck <= '0';
             end if;

             if (reg_addr  =  "00100") then
                  cmd_reg_new_flag <= '1';
             else
                 cmd_reg_new_flag <= '0';
             end if;

             if (crc_en  =  '1')  then
               if (reg_addr  = "00100"  and  pack_in_reg(4 downto 0)  =  "00111") then
                   crc_curr(31 downto 0) <= X"00000000";
               else 
                  if ( reg_addr /= "00011" and reg_addr /= "00111" and reg_addr /= "10110" and 
                    reg_addr /= "01000" and reg_addr /= "00000") then
                     crc_input(36 downto 0) := reg_addr(4 downto 0) & pack_in_reg(31 downto 0); 
                     crc_new(31 downto 0) := crc_next(crc_curr, crc_input);
                     crc_curr(31 downto 0) <= crc_new;
                   end if;
               end if;
             end if;

             if (conti_data_cnt = 1) then
                  conti_data_cnt <= 0;
             else 
                conti_data_cnt <= conti_data_cnt - 1;
             end if;
        elsif (conti_data_flag  =  '0' ) then
            if ( downcont_cnt >= 1) then
                   if (crc_en  =  '1') then
                     crc_input(36 downto 0) :=  "00010" & pack_in_reg; 
                     crc_new(31 downto 0) := crc_next(crc_curr, crc_input);
                     crc_curr(31 downto 0) <= crc_new;
                   end if;
             end if;
       
             if (pack_in_reg(31 downto 29)  =  "010"  and  downcont_cnt  =  0  ) then
                cmd_rd_flag <= '0';
                cmd_wr_flag <= '0';
                conti_data_flag <= '0';
                conti_data_cnt <= 0;
                tmp_v27 := pack_in_reg(26 downto 0);
                downcont_cnt <= SLV_TO_INT(SLV=>tmp_v27);
             elsif (pack_in_reg(31 downto 29)  =  "001") then
                if (pack_in_reg(28 downto 27)  =  "01"  and  downcont_cnt  =  0) then
                    if (pack_in_reg(10 downto 0)  /=  "00000000000") then
                       cmd_rd_flag <= '1';
                       cmd_wr_flag <= '0';
                       rd_data_cnt <= 4;
                       conti_data_cnt <= 0;
                       conti_data_flag <= '0';
                       rd_reg_addr <= pack_in_reg(17 downto 13);
                    end if;
                elsif (pack_in_reg(28 downto 27)  =  "10"  and  downcont_cnt  =  0) then
                   if (pack_in_reg(17 downto 13)  =  "01111")   then
                           csob_reg <= pack_in_reg;
                           csbo_cnt <= SLV_TO_INT(SLV=>pack_in_reg(10 downto 0));
                           csbo_flag <= '1';
                           conti_data_flag <= '0';
                           reg_addr <= pack_in_reg(17 downto 13);
                           cmd_wr_flag <= '1';
                           conti_data_cnt <= 0;
                    elsif (pack_in_reg(10 downto 0)  /=  "00000000000") then
                       cmd_rd_flag <= '0';
                       cmd_wr_flag <= '1';
                       conti_data_flag <= '1';
                       tmp_v11 := pack_in_reg(10 downto 0);
                       conti_data_cnt <= SLV_TO_INT(SLV=>tmp_v11);
                       reg_addr <= pack_in_reg(17 downto 13);
                    end if;
                else 
                    cmd_wr_flag <= '0';
                    conti_data_flag <= '0';
                    conti_data_cnt <= 0;
                end if;
             end if;
             cmd_reg_new_flag <= '0';
             crc_ck <= '0';
          end  if;  -- if (conti_data_flag  =  '0' ) 
          if (csbo_cnt  /=  0 ) then
             if (csbo_flag  =  '1') then
              csbo_cnt <= csbo_cnt - 1;
             end if;
          else
              csbo_flag <= '0';
          end if;

          if (conti_data_cnt  =  1 )  then
                conti_data_flag <= '0';
          end if;

      end if;

      if (rw_en  = '1') then
         if (rd_data_cnt  =  1)  then
            rd_data_cnt <= 0;
         elsif (rd_data_cnt  =  0  and  rd_flag  =  '1') then
               cmd_rd_flag <= '0';
         elsif (cmd_rd_flag  = '1'   and  rd_flag  =  '1') then
             rd_data_cnt <= rd_data_cnt - 1;
         end if;

          if (downcont_cnt >= 1 and conti_data_flag = '0' and new_data_in_flag = '1' and wr_flag = '1') then
              downcont_cnt <= downcont_cnt - 1;
          end if;
      end if;

     if (crc_ck = '1') then
         crc_ck <= '0';
     end if;
    end if;
    end  process;

   rd_back_p : process ( cclk_in, rst_intl) begin
    if (rst_intl  = '0') then
         outbus <= "00000000";
    elsif (rising_edge(cclk_in)) then
        if (cmd_rd_flag  =  '1'  and  rdwr_b_in  =  '1'  and  csi_b_in  =  '0') then
               case (rd_reg_addr) is
               when "00000" => if (rd_data_cnt = 1)  then
                             outbus <= crc_reg(7 downto 0);
                          elsif (rd_data_cnt = 2)  then
                             outbus <= crc_reg(15 downto 8);
                          elsif (rd_data_cnt = 3)  then
                             outbus <= crc_reg(23 downto 16);
                          elsif (rd_data_cnt = 4)  then
                             outbus <= crc_reg(31 downto 24);
                          end if;
               when "00111" => if (rd_data_cnt = 1)  then
                             outbus <= stat_reg(7 downto 0);
                          elsif (rd_data_cnt = 2) then
                             outbus <= stat_reg(15 downto 8);
                          elsif (rd_data_cnt = 3) then
                             outbus <= stat_reg(23 downto 16);
                          elsif (rd_data_cnt = 4) then
                             outbus <= stat_reg(31 downto 24);
                          end if;
               when "01100" => if (rd_data_cnt = 1) then
                             outbus <= idcode_reg(7 downto 0);
                          elsif (rd_data_cnt = 2) then
                             outbus <= idcode_reg(15 downto 8);
                          elsif (rd_data_cnt = 3) then
                             outbus <= idcode_reg(23 downto 16);
                          elsif (rd_data_cnt = 4) then
                             outbus <= idcode_reg(31 downto 24);
                          end if;
               when others => NULL;
               end case;
       else
             outbus <= "00000000";
       end if;
    end if;
   end process;

     crc_rst <= crc_reset  or   not rst_intl;

    process ( cclk_in,  crc_rst ) begin
     if (crc_rst = '1') then
         crc_err_flag <= '0';
     elsif (rising_edge(cclk_in)) then
        if (crc_ck = '1') then
          if (crc_bypass = '1') then
             if (crc_reg(15 downto 0)  /=  X"DEFC")  then
                 crc_err_flag <= '1';
             else
                 crc_err_flag <= '0';
             end if;
          else 
            if (crc_curr(31 downto 0)  /=  crc_reg(31 downto 0))  then
                crc_err_flag <= '1';
            else
                 crc_err_flag <= '0';
            end if;
          end if;
       else
           crc_err_flag <= '0';
       end if;
    end if;
    end process;

    process ( crc_err_flag,  rst_intl,  bus_sync_flag) begin
     if (rst_intl  =  '0') then
         crc_err_flag_reg <= '0';
     elsif (rising_edge(crc_err_flag)) then
         crc_err_flag_reg <= '1';
     elsif (rising_edge(bus_sync_flag)) then
         crc_err_flag_reg <= '0';
     end if;
    end process;


    process (cclk_in, rst_intl) begin
    if (rst_intl  = '0') then
         startup_set <= '0';
         crc_reset  <= '0';
         gsr_cmd_out <= '0';
         shutdown_set <= '0';
         desynch_set <= '0';
         ghigh_b <= '0';
    elsif (rising_edge(cclk_in)) then
    if (cmd_reg_new_flag  = '1') then
      if (cmd_reg  =  "00011")  then
          ghigh_b <= '1';
      elsif (cmd_reg  =  "01000") then
           ghigh_b <= '0';
      end if;

      if (cmd_reg  =  "00101") then
           startup_set <= '1';
      end if;

      if (cmd_reg  =  "00111")  then
           crc_reset <= '1';
      end if;

      if (cmd_reg  =  "01010")  then
           gsr_cmd_out <= '1';
      end if;

      if (cmd_reg  =  "01011") then
           shutdown_set <= '1';
      end if;

      if (cmd_reg  =  "01101")  then
           desynch_set <= '1';
      end if;

      if (cmd_reg  =  "01111") then
          iprog_b <= '0';
          i_init_b_cmd <= '0';
          iprog_b <= '1' after cfg_Tprog;
          i_init_b_cmd <= '1' after (cfg_Tprog + cfg_Tpl);
      end if;
    else 
             startup_set <= '0';
              crc_reset <= '0';
              gsr_cmd_out <= '0';
              shutdown_set <= '0';
              desynch_set <= '0';
    end if;
    end if;
   end process;

   startup_set_pulse_p : process  begin
    if (rw_en  =  '0') then
       startup_set_pulse <= "00";
    elsif (rising_edge(startup_set)) then
      if (startup_set_pulse  =  "00") then
         startup_set_pulse <= "01";
      end if;
    elsif (rising_edge(desynch_set)) then
      if (startup_set_pulse  =  "01") then
          startup_set_pulse <= "11";
          wait until (rising_edge(cclk_in ));
          startup_set_pulse <= "00";
      end if;
    end if;
      wait on startup_set, desynch_set, rw_en;
    end process;


   gsr_cmd_out_pulse_p :  process  begin
    if (rw_en  =  '0') then
       gsr_cmd_out_pulse <= '0';
    elsif (rising_edge(gsr_cmd_out)) then
       gsr_cmd_out_pulse <= '1';
       wait until (rising_edge(cclk_in ));
       wait until (rising_edge(cclk_in ));
       gsr_cmd_out_pulse <=  '0';
    end if;
      wait on gsr_cmd_out, rw_en;
   end process;


    process (ctl0_reg) begin
      if (ctl0_reg(9)  =  '1') then
         abort_dis <= '1';
      else
         abort_dis <= '0';
      end if;
      if (ctl0_reg(3)  =  '1') then
         persist_en <= '1';
      else
         persist_en <= '0';
      end if;
      if (ctl0_reg(0)  =  '1') then
         gts_usr_b <= '1';
      else
         gts_usr_b <= '0';
      end if;
    end process;

    process (cor0_reg) 
    begin
      done_cycle_reg <= cor0_reg(14 downto 12);
      lock_cycle_reg <= cor0_reg(8 downto 6);
      gts_cycle_reg <= cor0_reg(5 downto 3);
      gwe_cycle_reg <= cor0_reg(2 downto 0);

     if (cor0_reg(24)  =  '1') then
         done_pin_drv <= '1';
      else
         done_pin_drv <= '0';
      end if;
      if (cor0_reg(28)  =  '1') then
         crc_bypass <= '1';
      else
         crc_bypass <= '0';
      end if;
    end process;

    process (cor1_reg) begin
       rbcrc_no_pin <= cor1_reg(8);
    end process;

     stat_reg(26 downto 25) <= buswidth;
     stat_reg(20 downto 18) <= st_state;
     stat_reg(16) <= '0';
     stat_reg(15) <= id_error_flag;
     stat_reg(14) <= DONE;
     stat_reg(13) <= '1' when (done_o /=  '0') else '0';
     stat_reg(12) <= INITB;
     stat_reg(11) <= mode_sample_flag;
     stat_reg(10 downto 8) <= mode_pin_in;
     stat_reg(7) <= ghigh_b;
     stat_reg(6) <= gwe_out;
     stat_reg(5) <= gts_cfg_b;
     stat_reg(4) <= eos_startup;
     stat_reg(3) <= 'X';
     stat_reg(2) <= dcm_locked;
     stat_reg(1) <= 'X';
     stat_reg(0) <= crc_err_flag_reg; 


    st_state_p : process ( cclk_in, rst_intl) begin
      if (rst_intl  =  '0') then
        st_state <= STARTUP_PH0;
        startup_begin_flag <= '0';
        startup_end_flag <= '0';
      elsif (rising_edge(cclk_in)) then
           if (nx_st_state  =  STARTUP_PH1) then
              startup_begin_flag <= '1';
              startup_end_flag <= '0';
           elsif (st_state  =  STARTUP_PH7) then
              startup_end_flag <= '1';
              startup_begin_flag <= '0';
           end if;
           if  ((lock_cycle_reg = "111") or (dcm_locked  =  '1') or (st_state /= lock_cycle_reg)) then
                st_state <= nx_st_state;
           else
              st_state <= st_state;
           end if;
      end if;
     end process;

    nx_st_state_p : process (st_state, startup_set_pulse, done_in ) begin
    if ((( st_state  =  done_cycle_reg) and (done_in /= '0')) or ( st_state /= done_cycle_reg)) then
      case (st_state) is
      when STARTUP_PH0  =>      if (startup_set_pulse  =  "11" ) then
                                     nx_st_state <= STARTUP_PH1;
                                else
                                     nx_st_state <= STARTUP_PH0;
                                end if;
      when STARTUP_PH1  =>      nx_st_state <= STARTUP_PH2;

      when STARTUP_PH2  =>      nx_st_state <= STARTUP_PH3;

      when STARTUP_PH3  =>      nx_st_state <= STARTUP_PH4;

      when STARTUP_PH4  =>      nx_st_state <= STARTUP_PH5;

      when STARTUP_PH5  =>      nx_st_state <= STARTUP_PH6;

      when STARTUP_PH6  =>      nx_st_state <= STARTUP_PH7;

      when STARTUP_PH7  =>      nx_st_state <= STARTUP_PH0;
      when others => NULL;
      end case;
   end if;
   end process;

    start_out_p : process ( cclk_in, rst_intl ) begin
      if (rst_intl  =  '0') then
          gwe_out <= '0';
          gts_out <= '1';
          eos_startup <= '0';
          gsr_st_out <= '1';
          done_o <= '0';
      elsif (rising_edge(cclk_in)) then

         if (nx_st_state  =  done_cycle_reg) then
            if (done_in  /=  '0' or done_pin_drv = '1') then
               done_o <= '1';
            else
               done_o <= 'H';
            end if;
         else
             if (done_in  /=  '0') then
                     done_o <= '1';
             end if;
         end if;
         
         if (st_state  =  gwe_cycle_reg  and  DONE  /=  '0')   then
             gwe_out <= '1';
         end if;   
         if (st_state  =  gts_cycle_reg  and  DONE  /=  '0')   then
             gts_out <= '0';
         end if;   
         if (st_state  =  STARTUP_PH6  and  DONE  /=  '0') then
             gsr_st_out <= '0';
         end if;
         if (st_state  =  STARTUP_PH7  and  DONE  /=  '0')  then
            eos_startup <= '1';
         end if; 
      end if;
    end process;
      
      gsr_out <= gsr_st_out  or  gsr_cmd_out;

    process (rdwr_b_in ,  rst_intl, abort_flag_rst , csi_b_in)
    begin
      if (rst_intl = '0'  or  abort_flag_rst = '1'  or  csi_b_in  =  '1') then
          abort_flag_wr <= '0';
      elsif (rising_edge(rdwr_b_in)) then
        if (abort_dis  =  '0'  and  csi_b_in  =  '0') then
             if (NOW  /=  0 ps) then
               abort_flag_wr <= '1';
               assert false report " Warning : RDWRB changes when CS_B low, which causes Configuration abort on SIM_CONFIG_V5."
               severity warning;
             end if;
        else
           abort_flag_wr <= '0';
        end if;
     end if;
    end process;
     

    process ( rdwr_b_in,  rst_intl,  abort_flag_rst,  csi_b_in) begin
      if (rst_intl = '0'  or   csi_b_in  =  '1'  or  abort_flag_rst = '1') then
          abort_flag_rd <= '0';
      elsif (falling_edge(rdwr_b_in)) then
       if (abort_dis  =  '0'  and  csi_b_in  =  '0') then
         if (NOW  /=  0 ps) then
          abort_flag_rd <= '1';
          assert false report " Warning :  RDWRB changes when CS_B low, which causes Configuration abort on SIM_CONFIG_V5."
          severity warning;
         end if;
       else
         abort_flag_rd <= '0';
       end if;
     end if;
    end process;

     abort_flag <= abort_flag_wr  or  abort_flag_rd;

    process ( cclk_in,  rst_intl) begin
      if (rst_intl  =  '0') then
         abort_cnt <= 0;
         abort_out_en <= '0';
      elsif (rising_edge(cclk_in)) then
         if ( abort_flag  = '1' ) then
             if (abort_cnt < 4) then
                 abort_cnt <= abort_cnt + 1;
                 abort_out_en <= '1';
             else
                abort_flag_rst <= '1';
             end if;
         else
                abort_cnt <=  0;
                abort_out_en <= '0';
                abort_flag_rst <= '0';
         end if;

         if (abort_cnt =  0) then
            abort_status <= (cfgerr_b_flag & bus_sync_flag &  "011111");
            abort_status <= (cfgerr_b_flag & bus_sync_flag &  "011111");
         elsif (abort_cnt =  1) then
            abort_status <= (cfgerr_b_flag & "1001111");
         elsif (abort_cnt =  2) then
            abort_status <= (cfgerr_b_flag & "0001111");
         elsif (abort_cnt =  3) then
            abort_status <= (cfgerr_b_flag & "0011111");
         end if;
      end if;
    end process;
         
end SIM_CONFIG_V5_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/srlc32e.vhd,v 1.3 2005/04/22 20:21:58 yanx Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  32-Bit Shift Register Look-Up-Table with Carry and Clock Enable
-- /___/   /\     Filename : SRLC32E.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:56:58 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/15/04 - Initial version.
--    04/22/05 - Change input A type from ulogic vector to logic vector.
-- End Revision

----- CELL SRLC32E -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity SRLC32E is

  generic (
       INIT : bit_vector := X"00000000"
  );

  port (
        Q   : out STD_ULOGIC;
        Q31 : out STD_ULOGIC;

        A   : in STD_LOGIC_VECTOR (4 downto 0);
        CE  : in STD_ULOGIC;
        CLK : in STD_ULOGIC;        
        D   : in STD_ULOGIC
       ); 
end SRLC32E;

architecture SRLC32E_V of SRLC32E is
  signal SHIFT_REG : std_logic_vector (31 downto 0) :=  To_StdLogicVector(INIT);
begin

    Q <= SHIFT_REG(TO_INTEGER(UNSIGNED(A)));
    Q31 <= SHIFT_REG(31);


   WriteBehavior : process

    variable FIRST_TIME : boolean := TRUE;

  begin

    if (FIRST_TIME) then
        wait until ((CE = '1' or CE = '0') and
                   (CLK'last_value = '0' or CLK'last_value = '1') and
                   (CLK = '0' or CLK = '1'));
        FIRST_TIME := FALSE;
    end if;

    if (CLK'event AND CLK = '1') then
        if (CE = '1') then
           SHIFT_REG(31 downto 0) <= (SHIFT_REG(30 downto 0) & D) after 100 ps;
        end if ;
    end if;

    wait on CLK;

  end process WriteBehavior;
end SRLC32E_V;


-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  User Interface to Global Clock, Reset and 3-State Controls for VIRTEX5
-- /___/   /\     Filename : STARTUP_VIRTEX5.vhd
-- \   \  /  \    Timestamp : Thu Jun  2 10:57:05 PDT 2005
--  \___\/\___\
--
-- Revision:
--    06/02/05 - Initial version.

----- CELL STARTUP_VIRTEX5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity STARTUP_VIRTEX5 is
  port(
    CFGCLK	: out std_ulogic;
    CFGMCLK	: out std_ulogic;
    DINSPI	: out std_ulogic;
    EOS		: out std_ulogic;
    TCKSPI	: out std_ulogic;

    CLK		: in std_ulogic := 'X';
    GSR		: in std_ulogic := 'X';
    GTS		: in std_ulogic := 'X';
    USRCCLKO	: in std_ulogic := 'X';
    USRCCLKTS	: in std_ulogic := 'X';
    USRDONEO	: in std_ulogic := 'X';
    USRDONETS	: in std_ulogic := 'X'
    );

end STARTUP_VIRTEX5;

architecture STARTUP_VIRTEX5_V of STARTUP_VIRTEX5 is

begin
end STARTUP_VIRTEX5_V;
------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  
-- /___/   /\     Filename : SYSMON.vhd
-- \   \  /  \    Timestamp : 
--  \___\/\___\
-- Revision:
--    03/24/06 - Initial version.
--    06/26/06 - remove SIM_MONITOR_FILE from file definition (CR 234006).
--    08/04/06 - Change tmp_dr_ram_out out range from 83 to 87 (CR235676).
--               Add 100 ps delay to output (CR235566).
--    08/30/06 - GSR only reset DRP port (CR 422678).
--    09/06/06 - Add internal 1 ns reset at time 0 (422678).
--    09/07/06 - Match verilog model: alarm_update pulse etc. (CR 424061).
--    09/26/06 - Update error messages; Make unipolar same as bipolar for external channels;
--             - etc. (CR426629).
--    10/26/06 - Add tipd for analog channel although not used (CR423564).
--    10/30/06 - Match HW timing (CR 428185)
--    12/13/06 - Reset eoc_out_temp1 when calibration channel (CR430923)
--               Change INIT_42 to 0800 (CR 429642).
-- End Revision

----- CELL SYSMON -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_SIGNED.all;
use IEEE.NUMERIC_STD.all;

library STD;
use STD.TEXTIO.all;




library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity SYSMON is

generic (


                INIT_40 : bit_vector := X"0000";
                INIT_41 : bit_vector := X"0000";
                INIT_42 : bit_vector := X"0800";
                INIT_43 : bit_vector := X"0000";
                INIT_44 : bit_vector := X"0000";
                INIT_45 : bit_vector := X"0000";
                INIT_46 : bit_vector := X"0000";
                INIT_47 : bit_vector := X"0000";
                INIT_48 : bit_vector := X"0000";
                INIT_49 : bit_vector := X"0000";
                INIT_4A : bit_vector := X"0000";
                INIT_4B : bit_vector := X"0000";
                INIT_4C : bit_vector := X"0000";
                INIT_4D : bit_vector := X"0000";
                INIT_4E : bit_vector := X"0000";
                INIT_4F : bit_vector := X"0000";
                INIT_50 : bit_vector := X"0000";
                INIT_51 : bit_vector := X"0000";
                INIT_52 : bit_vector := X"0000";
                INIT_53 : bit_vector := X"0000";
                INIT_54 : bit_vector := X"0000";
                INIT_55 : bit_vector := X"0000";
                INIT_56 : bit_vector := X"0000";
                INIT_57 : bit_vector := X"0000";
                SIM_MONITOR_FILE : string := "design.txt"
  );

port (
                ALM : out std_logic_vector(2 downto 0);
                BUSY : out std_ulogic;
                CHANNEL : out std_logic_vector(4 downto 0);
                DO : out std_logic_vector(15 downto 0);
                DRDY : out std_ulogic;
                EOC : out std_ulogic;
                EOS : out std_ulogic;
                JTAGBUSY : out std_ulogic;
                JTAGLOCKED : out std_ulogic;
                JTAGMODIFIED : out std_ulogic;
                OT : out std_ulogic;

                CONVST : in std_ulogic;
                CONVSTCLK : in std_ulogic;
                DADDR : in std_logic_vector(6 downto 0);
                DCLK : in std_ulogic;
                DEN : in std_ulogic;
                DI : in std_logic_vector(15 downto 0);
                DWE : in std_ulogic;
                RESET : in std_ulogic;
                VAUXN : in std_logic_vector(15 downto 0);
                VAUXP : in std_logic_vector(15 downto 0);
                VN : in std_ulogic;
                VP : in std_ulogic
     );



end SYSMON;


architecture SYSMON_V of SYSMON is
 
  ---------------------------------------------------------------------------
  -- Function SLV_TO_INT converts a std_logic_vector TO INTEGER
  ---------------------------------------------------------------------------
  function SLV_TO_INT(SLV: in std_logic_vector
                      ) return integer is

    variable int : integer;
  begin
    int := 0;
    for i in SLV'high downto SLV'low loop
      int := int * 2;
      if SLV(i) = '1' then
        int := int + 1;
      end if;
    end loop;
    return int;
  end;


  ---------------------------------------------------------------------------
  -- Function ADDR_IS_VALID checks for the validity of the argument. A FALSE
  -- is returned if any argument bit is other than a '0' or '1'.
  ---------------------------------------------------------------------------
  function ADDR_IS_VALID (
    SLV : in std_logic_vector
    ) return boolean is

    variable IS_VALID : boolean := TRUE;

  begin
    for I in SLV'high downto SLV'low loop
      if (SLV(I) /= '0' AND SLV(I) /= '1') then
        IS_VALID := FALSE;
      end if;
    end loop;
    return IS_VALID;
  end ADDR_IS_VALID;

  ---------------------------------------------------------------------------
  -- Function SLV_TO_STR returns a string version of the std_logic_vector
  -- argument.
  ---------------------------------------------------------------------------
  function SLV_TO_STR (
    SLV : in std_logic_vector
    ) return string is

    variable j : integer := SLV'length;
    variable STR : string (SLV'length downto 1);
  begin
    for I in SLV'high downto SLV'low loop
      case SLV(I) is
        when '0' => STR(J) := '0';
        when '1' => STR(J) := '1';
        when 'X' => STR(J) := 'X';
        when 'U' => STR(J) := 'U';
        when others => STR(J) := 'X';
      end case;
      J := J - 1;
    end loop;
    return STR;
  end SLV_TO_STR;

  function int2real( int_in : in integer) return real is
    variable conline1 : line;
    variable rl_value : real;
    variable tmpv1 : real;
    variable tmpv2 : real := 1.0;
    variable tmpi : integer;
  begin
    tmpi := int_in;
    write (conline1, tmpi);
    write (conline1, string'(".0 "));
    write (conline1, tmpv2);
    read (conline1, tmpv1);
    rl_value := tmpv1;
    return rl_value;
    DEALLOCATE(conline1);
  end int2real;


  function real2int( real_in : in real) return integer is
    variable int_value : integer;
    variable tmpt : time;
    variable tmpt1 : time;
    variable tmpa : real;
    variable tmpr : real;
    variable int_out : integer;
  begin
    tmpa := abs(real_in);
    tmpt := tmpa * 1 ps;
    int_value := (tmpt / 1 ps ) * 1;
    tmpt1 := int_value * 1 ps;
      tmpr := int2real(int_value);  

    if ( real_in < 0.0000) then
       if (tmpr > tmpa) then
           int_out := 1 - int_value;
       else
           int_out := -int_value;
       end if;
    else
      if (tmpr > tmpa) then 
           int_out := int_value - 1;
      else
           int_out := int_value;
      end if;
    end if;
    return int_out;
  end real2int;


    FUNCTION  To_Upper  ( CONSTANT  val    : IN String
                         ) RETURN STRING IS
        VARIABLE result   : string (1 TO val'LENGTH) := val;
        VARIABLE ch       : character;
    BEGIN
        FOR i IN 1 TO val'LENGTH LOOP
            ch := result(i);
            EXIT WHEN ((ch = NUL) OR (ch = nul));
            IF ( ch >= 'a' and ch <= 'z') THEN
                  result(i) := CHARACTER'VAL( CHARACTER'POS(ch)
                                       - CHARACTER'POS('a')
                                       + CHARACTER'POS('A') );
            END IF;
        END LOOP;
        RETURN result;
    END To_Upper;

    procedure get_token(buf : inout LINE; token : out string;
                            token_len : out integer) 
    is
       variable index : integer := buf'low;
       variable tk_index : integer := 0;
       variable old_buf : LINE := buf; 
    BEGIN
         while ((index <= buf' high) and ((buf(index) = ' ') or
                                         (buf(index) = HT))) loop
              index := index + 1; 
         end loop;
        
         while((index <= buf'high) and ((buf(index) /= ' ') and 
                                    (buf(index) /= HT))) loop 
              tk_index := tk_index + 1;
              token(tk_index) := buf(index);
              index := index + 1; 
         end loop;
   
         token_len := tk_index;
        
         buf := new string'(old_buf(index to old_buf'high));
           old_buf := NULL;
    END;

    procedure skip_blanks(buf : inout LINE) 
    is
         variable index : integer := buf'low;
         variable old_buf : LINE := buf; 
    BEGIN
         while ((index <= buf' high) and ((buf(index) = ' ') or 
                                       (buf(index) = HT))) loop
              index := index + 1; 
         end loop;
         buf := new string'(old_buf(index to old_buf'high));
           old_buf := NULL;
    END;

    procedure infile_format
    is
         variable message_line : line;
    begin

    write(message_line, string'("***** SYSMON Simulation Analog Data File Format ******"));
    writeline(output, message_line);
    write(message_line, string'("NAME: design.txt or user file name passed with generic sim_monitor_file"));
    writeline(output, message_line);
    write(message_line, string'("FORMAT: First line is header line. Valid column name are: TIME TEMP VCCINT VCCAUX VP VN VAUXP[0] VAUXN[0] ...."));
    writeline(output, message_line);
    write(message_line, string'("TIME must be in first column."));
    writeline(output, message_line);
    write(message_line, string'("Time value need to be integer in ns scale"));
    writeline(output, message_line);
    write(message_line, string'("Analog  value need to be real and contain a decimal  point '.', zero should be 0.0, 3 should be 3.0"));
    writeline(output, message_line);
    write(message_line, string'("Each line including header line can not have extra space after the last character/digit."));
    writeline(output, message_line);
    write(message_line, string'("Each data line must have same number of columns as the header line."));
    writeline(output, message_line);
    write(message_line, string'("Comment line start with -- or //"));
    writeline(output, message_line);
    write(message_line, string'("Example:"));
    writeline(output, message_line);
    write(message_line, string'("TIME TEMP VCCINT  VP VN VAUXP[0] VAUXN[0]"));
    writeline(output, message_line);
    write(message_line, string'("000  125.6  1.0  0.7  0.4  0.3  0.6"));
    writeline(output, message_line);
    write(message_line, string'("200  25.6   0.8  0.5  0.3  0.8  0.2"));
    writeline(output, message_line);

    end infile_format;

    type     REG_FILE   is  array (integer range <>) of 
                            std_logic_vector(15 downto 0);
    signal   dr_sram     :  REG_FILE(16#40# to 16#57#) := 
               ( 
                  16#40# => TO_STDLOGICVECTOR(INIT_40),
                  16#41# => TO_STDLOGICVECTOR(INIT_41),
                  16#42# => TO_STDLOGICVECTOR(INIT_42),
                  16#43# => TO_STDLOGICVECTOR(INIT_43),
                  16#44# => TO_STDLOGICVECTOR(INIT_44),
                  16#45# => TO_STDLOGICVECTOR(INIT_45),
                  16#46# => TO_STDLOGICVECTOR(INIT_46),
                  16#47# => TO_STDLOGICVECTOR(INIT_47),
                  16#48# => TO_STDLOGICVECTOR(INIT_48),
                  16#49# => TO_STDLOGICVECTOR(INIT_49),
                  16#4A# => TO_STDLOGICVECTOR(INIT_4A),
                  16#4B# => TO_STDLOGICVECTOR(INIT_4B),
                  16#4C# => TO_STDLOGICVECTOR(INIT_4C),
                  16#4D# => TO_STDLOGICVECTOR(INIT_4D),
                  16#4E# => TO_STDLOGICVECTOR(INIT_4E),
                  16#4F# => TO_STDLOGICVECTOR(INIT_4F),
                  16#50# => TO_STDLOGICVECTOR(INIT_50),
                  16#51# => TO_STDLOGICVECTOR(INIT_51),
                  16#52# => TO_STDLOGICVECTOR(INIT_52),
                  16#53# => TO_STDLOGICVECTOR(INIT_53),
                  16#54# => TO_STDLOGICVECTOR(INIT_54),
                  16#55# => TO_STDLOGICVECTOR(INIT_55),
                  16#56# => TO_STDLOGICVECTOR(INIT_56),
                  16#57# => TO_STDLOGICVECTOR(INIT_57)
               );

       signal ot_sf_limit_low_reg : unsigned(15 downto 0) := "1010111001000000";  --X"AE40";
       type     adc_statetype    is (INIT_STATE, ACQ_STATE, CONV_STATE, 
                                   ADC_PRE_END, END_STATE, SINGLE_SEQ_STATE);
       type     ANALOG_DATA    is array (0 to 31) of real;
       type     DR_data_reg    is array (0 to 63) of 
                                  std_logic_vector(15 downto 0);
       type     ACC_ARRAY      is array (0 to 31) of integer;
       type     int_array      is array(0 to 31) of integer;
       type     seq_array      is array(32 downto 0 ) of integer;

       signal   ot_limit_reg     : UNSIGNED(15 downto 0) := "1100011110000000";
       signal   adc_state         : adc_statetype := CONV_STATE;
       signal   next_state        : adc_statetype;
       signal   cfg_reg0         : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   cfg_reg0_adc     : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   cfg_reg0_seq     : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   cfg_reg1         : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   cfg_reg1_init    : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   cfg_reg2         : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   seq1_0           : std_logic_vector(1 downto 0) := "00";
       signal   curr_seq1_0      : std_logic_vector(1 downto 0) := "00";
       signal   curr_seq1_0_lat  : std_logic_vector(1 downto 0) := "00";
       signal   busy_r           : std_ulogic := '0';
       signal   busy_r_rst       : std_ulogic := '0';
       signal   busy_rst         : std_ulogic := '0';
       signal   busy_conv        : std_ulogic := '0';
       signal   busy_out_tmp     : std_ulogic := '0';
       signal   busy_out_dly     : std_ulogic := '0';
       signal   busy_out_sync    : std_ulogic := '0';
       signal   busy_out_low_edge : std_ulogic := '0';
       signal   shorten_acq      : integer := 1;
       signal   busy_seq_rst     : std_ulogic := '0';
       signal   busy_sync1       : std_ulogic := '0';
       signal   busy_sync2       : std_ulogic := '0';
       signal   busy_sync_fall   : std_ulogic := '0';
       signal   busy_sync_rise   : std_ulogic := '0';
       signal   cal_chan_update  : std_ulogic := '0';
       signal   first_cal_chan   : std_ulogic := '0';
       signal   seq_reset_flag   : std_ulogic := '0';
       signal   seq_reset_flag_dly   : std_ulogic := '0';
       signal   seq_reset_dly   : std_ulogic := '0';
       signal   seq_reset_busy_out  : std_ulogic := '0';
       signal   rst_in_not_seq   : std_ulogic := '0';
       signal   rst_in_out       : std_ulogic := '0';
       signal   rst_lock_early   : std_ulogic := '0';
       signal   conv_count       : integer := 0;
       signal   acq_count       : integer := 1;
       signal   do_out_rdtmp     : std_logic_vector(15 downto 0);
       signal   rst_in1          : std_ulogic := '0';
       signal   rst_in2          : std_ulogic := '0';
       signal   int_rst          : std_ulogic := '1';
       signal   rst_input_t      : std_ulogic := '0';
       signal   rst_in           : std_ulogic := '0';
       signal   ot_en            : std_logic := '1';
       signal   curr_clkdiv_sel  : std_logic_vector(7 downto 0) 
                                                  := "00000000";
       signal   curr_clkdiv_sel_int : integer := 0;
       signal   adcclk           : std_ulogic := '0';
       signal   adcclk_div1      : std_ulogic := '0';
       signal   sysclk           : std_ulogic := '0';
       signal   curr_adc_resl    : std_logic_vector(2 downto 0) := "010";
       signal   nx_seq           : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   curr_seq         : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   acq_cnt          : integer := 0;
       signal   acq_chan         : std_logic_vector(4 downto 0) := "00000";
       signal   acq_chan_index   : integer := 0;
       signal   acq_chan_lat     : std_logic_vector(4 downto 0) := "00000";
       signal   curr_chan        : std_logic_vector(4 downto 0) := "00000";
       signal   curr_chan_dly    : std_logic_vector(4 downto 0) := "00000";
       signal   curr_chan_lat    : std_logic_vector(4 downto 0) := "00000";
       signal   curr_avg_set     : std_logic_vector(1 downto 0) := "00";
       signal   acq_avg          : std_logic_vector(1 downto 0) := "00";
       signal   curr_e_c         : std_logic:= '0';
       signal   acq_e_c          : std_logic:= '0';
       signal   acq_b_u          : std_logic:= '0';
       signal   curr_b_u         : std_logic:= '0';
       signal   acq_acqsel       : std_logic:= '0';
       signal   curr_acq         : std_logic:= '0';
       signal   seq_cnt          : integer := 0;
       signal   busy_rst_cnt     : integer := 0;
       signal   adc_s1_flag      : std_ulogic := '0';
       signal   adc_convst       : std_ulogic := '0';
       signal   conv_start       : std_ulogic := '0';
       signal   conv_end         : std_ulogic := '0'; 
       signal   eos_en           : std_ulogic := '0';
       signal   eos_tmp_en       : std_ulogic := '0';
       signal   seq_cnt_en       : std_ulogic := '0'; 
       signal   eoc_en           : std_ulogic := '0';
       signal   eoc_en_delay       : std_ulogic := '0';
       signal   eoc_out_tmp     : std_ulogic := '0';
       signal   eos_out_tmp     : std_ulogic := '0';
       signal   eoc_out_tmp1     : std_ulogic := '0';
       signal   eos_out_tmp1     : std_ulogic := '0';
       signal   eoc_up_data      : std_ulogic := '0';
       signal   eoc_up_alarm    : std_ulogic := '0';
       signal   conv_time        : integer := 17;
       signal   conv_time_cal_1  : integer := 69;
       signal   conv_time_cal    : integer := 69;
       signal   conv_result      : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   conv_result_reg  : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   data_written     : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   conv_result_int  : integer := 0;
       signal   conv_result_int_resl  : integer := 0;
       signal   analog_in_uni    : ANALOG_DATA :=(others=>0.0); 
       signal   analog_in_diff   : ANALOG_DATA :=(others=>0.0); 
       signal   analog_in        : ANALOG_DATA :=(others=>0.0); 
       signal   analog_in_comm   : ANALOG_DATA :=(others=>0.0); 
       signal   chan_val_tmp   : ANALOG_DATA :=(others=>0.0); 
       signal   chan_valn_tmp   : ANALOG_DATA :=(others=>0.0); 
       signal   data_reg         : DR_data_reg
                                  :=( 36 to 39 => "1111111111111111",
                                     others=>"0000000000000000");
       signal   tmp_data_reg_out : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   tmp_dr_sram_out  : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   seq_chan_reg1    : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   seq_chan_reg2    : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   seq_acq_reg1     : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   seq_acq_reg2     : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   seq_avg_reg1     : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   seq_avg_reg2     : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   seq_du_reg1      : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   seq_du_reg2      : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   seq_count        : integer := 1;
       signal   seq_count_en     : std_ulogic := '0';
       signal   conv_acc         : ACC_ARRAY :=(others=>0);
       signal   conv_avg_count   : ACC_ARRAY :=(others=>0);
       signal   conv_acc_vec     : std_logic_vector (20 downto 1);
       signal   conv_acc_result  : std_logic_vector(15 downto 0);
       signal   seq_status_avg   : integer := 0;
       signal   curr_chan_index       : integer := 0;
       signal   curr_chan_index_lat   : integer := 0;
       signal   conv_avg_cnt     : int_array :=(others=>0);
       signal   analog_mux_in    : real := 0.0;
       signal   adc_temp_result  : real := 0.0;
       signal   adc_intpwr_result : real := 0.0;
       signal   adc_ext_result    : real := 0.0;
       signal   seq_reset        : std_ulogic := '0';
       signal   seq_en           : std_ulogic := '0';
       signal   seq_en_drp       : std_ulogic := '0';
       signal   seq_en_init      : std_ulogic := '0';
       signal   seq_en_dly       : std_ulogic := '0';
       signal   seq_num          : integer := 0;
       signal   seq_mem          : seq_array :=(others=>0);
       signal   adc_seq_reset       : std_ulogic := '0';
       signal   adc_seq_en          : std_ulogic := '0';
       signal   adc_seq_reset_dly   : std_ulogic := '0';
       signal   adc_seq_en_dly      : std_ulogic := '0';
       signal   adc_seq_reset_hold  : std_ulogic := '0';
       signal   adc_seq_en_hold     : std_ulogic := '0';
       signal   rst_lock            : std_ulogic := '1';
       signal   sim_file_flag       : std_ulogic := '0';
       signal   gsr_in              : std_ulogic := '0';
       signal   convstclk_in       : std_ulogic := '0';
       signal   convst_raw_in      : std_ulogic := '0';
       signal   convst_in          : std_ulogic := '0';
       signal   dclk_in            : std_ulogic := '0';
       signal   den_in             : std_ulogic := '0';
       signal   rst_input          : std_ulogic := '0';
       signal   dwe_in             : std_ulogic := '0';
       signal   di_in              : std_logic_vector(15 downto 0) := "0000000000000000";
       signal   daddr_in           : std_logic_vector(6 downto 0) := "0000000";
       signal   daddr_in_lat       : std_logic_vector(6 downto 0) := "0000000";
       signal   daddr_in_lat_int   : integer := 0;
       signal   drdy_out_tmp1      : std_ulogic := '0';
       signal   drdy_out_tmp2      : std_ulogic := '0';
       signal   drdy_out_tmp3      : std_ulogic := '0';
       signal   drp_update         : std_ulogic := '0';
       signal   alarm_en           : std_logic_vector(2 downto 0) := "111";
       signal   alarm_update       : std_ulogic := '0';
       signal   adcclk_tmp         : std_ulogic := '0';
       signal   ot_out_reg         : std_ulogic := '0';
       signal   alarm_out_reg      : std_logic_vector(2 downto 0) := "000";
       signal   conv_end_reg_read  :  std_logic_vector(3 downto 0) := "0000";
       signal   busy_reg_read      : std_ulogic := '0';
       signal   single_chan_conv_end : std_ulogic := '0';
       signal   first_acq          : std_ulogic := '1';
       signal   conv_start_cont    : std_ulogic := '0';
       signal   conv_start_sel     : std_ulogic := '0';
       signal   reset_conv_start   : std_ulogic := '0';
       signal   reset_conv_start_tmp   : std_ulogic := '0';
       signal   busy_r_rst_done    : std_ulogic := '0';
       signal   op_count           : integer := 15;
      

-- Input/Output Pin signals

        signal   DI_ipd  :  std_logic_vector(15 downto 0);
        signal   DADDR_ipd  :  std_logic_vector(6 downto 0);
        signal   DEN_ipd  :  std_ulogic;
        signal   DWE_ipd  :  std_ulogic;
        signal   DCLK_ipd  :  std_ulogic;
        signal   CONVSTCLK_ipd  :  std_ulogic;
        signal   RESET_ipd  :  std_ulogic;
        signal   CONVST_ipd  :  std_ulogic;

        signal   do_out  :  std_logic_vector(15 downto 0) := "0000000000000000";
        signal   drdy_out  :  std_ulogic := '0';
        signal   ot_out  :  std_ulogic := '0';
        signal   alarm_out  :  std_logic_vector(2 downto 0) := "000";
        signal   channel_out  :  std_logic_vector(4 downto 0) := "00000";
        signal   eoc_out  :  std_ulogic := '0';
        signal   eos_out  :  std_ulogic := '0';
        signal   busy_out  :  std_ulogic := '0';

        signal   DI_dly  :  std_logic_vector(15 downto 0);
        signal   DADDR_dly  :  std_logic_vector(6 downto 0);
        signal   DEN_dly  :  std_ulogic;
        signal   DWE_dly  :  std_ulogic;
        signal   DCLK_dly  :  std_ulogic;
        signal   CONVSTCLK_dly  :  std_ulogic;
        signal   RESET_dly  :  std_ulogic;
        signal   CONVST_dly  :  std_ulogic;

begin 

   BUSY <= busy_out after 100 ps;
   DRDY <= drdy_out after 100 ps;
   EOC <= eoc_out after 100 ps;
   EOS <= eos_out after 100 ps;
   OT <= ot_out after 100 ps;
   DO <= do_out after 100 ps;
   CHANNEL <= channel_out after 100 ps;
   ALM <= alarm_out after 100 ps;

   convst_raw_in <= CONVST;
   convstclk_in <= CONVSTCLK;
   dclk_in <= DCLK;
   den_in <= DEN;
   rst_input <= RESET;
   dwe_in <= DWE;
   di_in <= Di;
   daddr_in <= DADDR;

   gsr_in <= GSR;
   convst_in <= '1' when (convst_raw_in = '1' or convstclk_in = '1') else  '0';
   JTAGLOCKED <= '0';
   JTAGMODIFIED <= '0';
   JTAGBUSY <= '0';

   DEFAULT_CHECK : process
       variable init40h_tmp : std_logic_vector(15 downto 0);
       variable init41h_tmp : std_logic_vector(15 downto 0);
       variable init42h_tmp : std_logic_vector(15 downto 0);
       variable init4eh_tmp : std_logic_vector(15 downto 0);
       variable init40h_tmp_chan : integer;
       variable init42h_tmp_clk : integer;
       variable tmp_value : std_logic_vector(7 downto 0);
   begin
        init40h_tmp := TO_STDLOGICVECTOR(INIT_40);
        init40h_tmp_chan := SLV_TO_INT(SLV=>init40h_tmp(4 downto 0));
        init41h_tmp := TO_STDLOGICVECTOR(INIT_41);
        init42h_tmp := TO_STDLOGICVECTOR(INIT_42);
        tmp_value :=  init42h_tmp(15 downto 8);
        init42h_tmp_clk := SLV_TO_INT(SLV=>tmp_value);
        init4eh_tmp := TO_STDLOGICVECTOR(INIT_4E);
 
        if ((init41h_tmp(13 downto 12)="11") and (init40h_tmp(8)='1') and (init40h_tmp_chan /= 3 ) and (init40h_tmp_chan < 16)) then
          assert false report " Attribute Syntax warning : The attribute INIT_40 bit[8] must be set to 0 on SYSMON. Long acquistion mode is only allowed for external channels."
          severity warning;
        end if;

        if ((init41h_tmp(13 downto 12) /="11") and (init4eh_tmp(10 downto 0) /= "00000000000") and (init4eh_tmp(15 downto 12) /= "0000")) then
           assert false report " Attribute Syntax warning : The attribute INIT_4E Bit[15:12] and bit[10:0] must be set to 0. Long acquistion mode is only allowed for external channels."
          severity warning;
        end if;

        if ((init41h_tmp(13 downto 12)="11") and (init40h_tmp(9) = '1') and (init40h_tmp(4 downto 0) /= "00011") and (init40h_tmp_chan < 16)) then 
          assert false report " Attribute Syntax warning : The attribute INIT_40 bit[9] must be set to 0 on SYSMON. Event mode timing can only be used with external channels, and only in single channel mode."
          severity warning;
        end if;

        if ((init41h_tmp(13 downto 12)="11") and (init40h_tmp(13 downto 12) /= "00") and (INIT_48 /=X"0000") and (INIT_49 /= X"0000")) then
           assert false report " Attribute Syntax warning : The attribute INIT_48 and INIT_49 must be set to 0000h in single channel mode and averaging enabled."
          severity warning;
        end if;

        if (init42h_tmp(1 downto 0) /= "00") then
             assert false report
             " Attribute Syntax Error : The attribute INIT_42 Bit[1:0] must be set to 00."
              severity Error;
        end if;

        if (init42h_tmp_clk < 8) then
             assert false report
             " Attribute Syntax Error : The attribute INIT_42 Bit[15:8] is the ADC Clock divider and must be equal or greater than 8."
              severity failure;
        end if;

        if (INIT_43 /= "0000000000000000") then
             assert false report
             " Warning : The attribute INIT_43 must   be set to 0000."
             severity warning;
        end if;

        if (INIT_44 /= "0000000000000000") then
             assert false report
             " Warning : The attribute INIT_44 must   be set to 0000."
             severity warning;
        end if;

        if (INIT_45 /= "0000000000000000") then
             assert false report
             " Warning : The attribute INIT_45 must   be set to 0000."
             severity warning;
        end if;

        if (INIT_46 /= "0000000000000000") then
             assert false report
             " Warning : The attribute INIT_46 must   be set to 0000."
             severity warning;
        end if;

        if (INIT_47 /= "0000000000000000") then
             assert false report
             " Warning : The attribute INIT_47 must   be set to 0000."
             severity warning;
        end if;

         wait;
   end process;


   curr_chan_index <= SLV_TO_INT(curr_chan);
   curr_chan_index_lat <= SLV_TO_INT(curr_chan_lat);

  CHEK_COMM_P : process( busy_r )
       variable Message : line;
  begin 
  if (busy_r'event and busy_r = '1' ) then
   if (rst_in = '0' and acq_b_u = '0' and ((acq_chan_index = 3) or (acq_chan_index >= 16 and acq_chan_index <= 31))) then
      if ( chan_valn_tmp(acq_chan_index) > chan_val_tmp(acq_chan_index)) then
       Write ( Message, string'("Input File Warning: The N input for external channel "));
       Write ( Message, acq_chan_index);
       Write ( Message, string'(" must be smaller than P input when in unipolar mode (P="));
       Write ( Message, chan_val_tmp(acq_chan_index));
       Write ( Message, string'(" N="));
       Write ( Message, chan_valn_tmp(acq_chan_index));
       Write ( Message, string'(") for SYSMON."));
      assert false report Message.all severity warning;
      DEALLOCATE (Message);
    end if;

     if (( chan_valn_tmp(acq_chan_index) > 0.5) or  (chan_valn_tmp(acq_chan_index) < 0.0)) then
       Write ( Message, string'("Input File Warning: The N input for external channel "));
       Write ( Message, acq_chan_index);
       Write ( Message, string'(" should be between 0V to 0.5V when in unipolar mode (N="));
       Write ( Message, chan_valn_tmp(acq_chan_index));
      Write ( Message, string'(") for SYSMON."));
      assert false report Message.all severity warning;
      DEALLOCATE (Message);
    end if;

   end if;
  end if;
  end process;

  busy_mkup_p : process( dclk_in, rst_in_out)
  begin
    if (rst_in_out = '1') then
       busy_rst <= '1';
       rst_lock <= '1';
       rst_lock_early <= '1';
       busy_rst_cnt <= 0;
    elsif (rising_edge(dclk_in)) then
       if (rst_lock = '1') then
          if (busy_rst_cnt < 29) then
               busy_rst_cnt <= busy_rst_cnt + 1;
               if ( busy_rst_cnt = 26) then
                    rst_lock_early <= '0';
               end if;
          else
               busy_rst <= '0';
               rst_lock <= '0';
          end if;
       end if;
    end if;
  end process;

  busy_out_p : process (busy_rst, busy_conv, rst_lock)
  begin
     if (rst_lock = '1') then
         busy_out <= busy_rst;
     else
         busy_out <= busy_conv;
     end if;
  end process;      

  busy_conv_p : process (dclk_in, rst_in)
  begin
    if (rst_in = '1') then
       busy_conv <= '0';
       cal_chan_update <= '0';
    elsif (rising_edge(dclk_in)) then
        if (seq_reset_flag = '1'  and curr_clkdiv_sel_int <= 3)  then
             busy_conv <= busy_seq_rst;
        elsif (busy_sync_fall = '1') then
            busy_conv <= '0';
        elsif (busy_sync_rise = '1') then
            busy_conv <= '1';
        end if;

        if (conv_count = 21 and curr_chan = "01000" ) then
              cal_chan_update  <= '1';
         else
              cal_chan_update  <= '0';
         end if;
    end if;
  end process;

  busy_sync_p : process (dclk_in, rst_lock)
  begin
     if (rst_lock = '1') then 
        busy_sync1 <= '0';
        busy_sync2 <= '0';
     elsif (rising_edge (dclk_in)) then 
         busy_sync1 <= busy_r;
         busy_sync2 <= busy_sync1;
     end if;
  end process;

  busy_sync_fall <= '1' when (busy_r = '0' and busy_sync1 = '1') else '0';
  busy_sync_rise <= '1' when (busy_sync1 = '1' and busy_sync2 = '0') else '0';

  busy_seq_rst_p : process
    variable tmp_uns_div : unsigned(7 downto 0);
  begin
     if (falling_edge(busy_out) or rising_edge(busy_r)) then
        if (seq_reset_flag = '1' and seq1_0 = "00" and curr_clkdiv_sel_int <= 3) then
           wait until (rising_edge(dclk_in));
           wait  until (rising_edge(dclk_in));
           wait  until (rising_edge(dclk_in));
           wait  until (rising_edge(dclk_in));
           wait  until (rising_edge(dclk_in));
           busy_seq_rst <= '1';
        elsif (seq_reset_flag = '1' and seq1_0 /= "00" and curr_clkdiv_sel_int <= 3) then
            wait  until (rising_edge(dclk_in));
            wait  until (rising_edge(dclk_in));
            wait  until (rising_edge(dclk_in));
            wait  until (rising_edge(dclk_in));
            wait  until (rising_edge(dclk_in));
            wait  until (rising_edge(dclk_in));
            wait  until (rising_edge(dclk_in));
           busy_seq_rst <= '1';
        else
           busy_seq_rst <= '0';
        end if;
     end if;
    wait on busy_out, busy_r;
   end process;

  chan_out_p : process(busy_out, rst_in_out, cal_chan_update)
  begin
   if (rst_in_out = '1') then
         channel_out <= "00000";
   elsif (rising_edge(busy_out) or rising_edge(cal_chan_update)) then
           if ( busy_out = '1' and cal_chan_update = '1') then
                channel_out <= "01000";
           end if;
   elsif (falling_edge(busy_out)) then
                channel_out <= curr_chan;
                curr_chan_lat <= curr_chan;
   end if;
  end process;

  INT_RST_GEN_P : process
  begin
    int_rst <= '1';
    wait until (rising_edge(dclk_in));
    wait until (rising_edge(dclk_in));
    int_rst <= '0';
    wait;
  end process;

  rst_input_t <= rst_input or int_rst;

  RST_DE_SYNC_P: process(dclk_in, rst_input_t)
  begin
      if (rst_input_t = '1') then
              rst_in2 <= '1';
              rst_in1 <= '1';
      elsif (dclk_in'event and dclk_in='1') then
              rst_in2 <= rst_in1;
              rst_in1 <= rst_input_t;
     end if;
  end process;

    rst_in_not_seq <= rst_in2;
    rst_in <= rst_in2 or seq_reset_dly;
    rst_in_out <= rst_in2 or seq_reset_busy_out;

  seq_reset_dly_p : process
  begin
   if (rising_edge(seq_reset)) then
    wait until rising_edge(dclk_in);
    wait until rising_edge(dclk_in);
       seq_reset_dly <= '1';
    wait until rising_edge(dclk_in);
    wait until falling_edge(dclk_in);
       seq_reset_busy_out <= '1';
    wait until rising_edge(dclk_in);
    wait until rising_edge(dclk_in);
    wait until rising_edge(dclk_in);
       seq_reset_dly <= '0';
       seq_reset_busy_out <= '0';
   end if;
    wait on seq_reset, dclk_in;
  end process;


  seq_reset_flag_p : process (seq_reset_dly, busy_r)
    begin
       if (rising_edge(seq_reset_dly)) then
          seq_reset_flag <= '1';
       elsif (rising_edge(busy_r)) then
          seq_reset_flag <= '0';
       end if;
    end process;

  seq_reset_flag_dly_p : process (seq_reset_flag, busy_out)
    begin
       if (rising_edge(seq_reset_flag)) then
          seq_reset_flag_dly <= '1';
       elsif (rising_edge(busy_out)) then
           seq_reset_flag_dly <= '0';
       end if;
    end process;

  first_cal_chan_p : process ( busy_out)
    begin
      if (rising_edge(busy_out )) then
          if (seq_reset_flag_dly = '1' and  acq_chan = "01000" and seq1_0 = "00") then
                  first_cal_chan <= '1';
          else 
                  first_cal_chan <= '0';
          end if;
      end if;
    end process;


  ADC_SM: process (adcclk, rst_in, sim_file_flag)
  begin
     if (sim_file_flag = '1') then
        adc_state <= INIT_STATE;
     elsif (rst_in = '1' or rst_lock_early = '1') then
        adc_state <= INIT_STATE;
     elsif (adcclk'event and adcclk = '1') then
         adc_state <= next_state;
     end if;
  end process;

  next_state_p : process (adc_state, eos_en, conv_start , conv_end, curr_seq1_0_lat)
  begin
      case (adc_state) is
      when INIT_STATE => next_state <= ACQ_STATE;

      when  ACQ_STATE => if (conv_start = '1') then
                                  next_state <= CONV_STATE;
                              else
                                  next_state <= ACQ_STATE;
                              end if;

      when  CONV_STATE => if (conv_end = '1') then
                                   next_state <= END_STATE;
                               else
                                   next_state <= CONV_STATE;
                                end if;

      when  END_STATE => if (curr_seq1_0_lat = "01")  then
                                if (eos_en = '1') then
                                    next_state <= SINGLE_SEQ_STATE;
                                else
                                    next_state <= ACQ_STATE;
                                end if;
                            else
                                next_state <= ACQ_STATE;
                            end if;

      when  SINGLE_SEQ_STATE => next_state <= INIT_STATE;

      when  others => next_state <= INIT_STATE;
    end case;
  end process;

  seq_en_init_p : process
  begin
      seq_en_init <= '0';
      if (cfg_reg1_init(13 downto 12) /= "11" ) then
          wait for 20 ps;
          seq_en_init <= '1';
          wait for 150 ps;
          seq_en_init <= '0';
      end if;
      wait;
  end process;

  
      seq_en <= seq_en_init or  seq_en_drp;

  DRPORT_DO_OUT_P : process(dclk_in, gsr_in)
       variable message : line;
       variable di_str : string (16 downto 1);
       variable daddr_str : string (7 downto  1);
       variable di_40 : std_logic_vector(4 downto 0);
       variable valid_daddr : boolean := false;
       variable address : integer;
       variable tmp_value : integer := 0;
       variable tmp_value1 : std_logic_vector (7 downto 0);
  begin
       
     if (gsr_in = '1') then 
         drdy_out <= '0';
         daddr_in_lat  <= "0000000";
         do_out <= "0000000000000000";
     elsif (rising_edge(dclk_in)) then
        if (den_in = '1') then
           valid_daddr := addr_is_valid(daddr_in);
           if (valid_daddr) then
               address := slv_to_int(daddr_in);
               if (  (address > 88 or
                   (address >= 13 and address <= 15)
                    or (address >= 39 and address <= 63))) then
                 Write ( Message, string'(" Invalid Input Warning : The DADDR "));
                 Write ( Message, string'(SLV_TO_STR(daddr_in)));
                 Write ( Message, string'("  is not defined. The data in this location is invalid."));
                 assert false report Message.all  severity warning;
                 DEALLOCATE(Message);
               end if;
            end if;

            if (drdy_out_tmp1 = '1' or drdy_out_tmp2 = '1' or drdy_out_tmp3 = '1') then
                drdy_out_tmp1 <= '0';
            else
                drdy_out_tmp1 <= '1';
            end if;
            daddr_in_lat  <= daddr_in;
        else
           drdy_out_tmp1 <= '0';
        end if;

        drdy_out_tmp2 <= drdy_out_tmp1;
        drdy_out_tmp3 <= drdy_out_tmp2;
        drdy_out <= drdy_out_tmp3;

        if (drdy_out_tmp3 = '1') then
            do_out <= do_out_rdtmp;
        end if;

-- write  all available daddr addresses

        if (dwe_in = '1' and den_in = '1') then  
           if (valid_daddr) then
               dr_sram(address) <= di_in;
           end if;
          
           if ( address = 42 and  di_in( 1 downto 0) /= "00") then
             Write ( Message, string'(" Invalid Input Error : The DI bit[1:0] "));
             Write ( Message, bit_vector'(TO_BITVECTOR(di_in(1 downto 0))));
             Write ( Message, string'("  at DADDR "));
             Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in)));
             Write ( Message, string'(" of SYSMON is invalid. These must be set to 00."));
             assert false report Message.all  severity error;
           end if;

           tmp_value1 := di_in(15 downto 8) ; 
           tmp_value := SLV_TO_INT(SLV=>tmp_value1);

           if ( address = 42 and  tmp_value < 8) then
             Write ( Message, string'(" Invalid Input Error : The DI bit[15:8] "));
             Write ( Message, bit_vector'(TO_BITVECTOR(di_in(15 downto 8))));
             Write ( Message, string'("  at DADDR "));
             Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in)));
             Write ( Message, string'(" of SYSMON is invalid. Bit[15:8] of Control Register 42h is the ADC Clock divider and must be equal or greater than 8."));
             assert false report Message.all  severity failure;
           end if;

           if ( (address >= 43 and  address <= 47) and di_in(15 downto 0) /= "0000000000000000") then
             Write ( Message, string'(" Invalid Input Error : The DI value "));
             Write ( Message, bit_vector'(TO_BITVECTOR(di_in)));
             Write ( Message, string'("  at DADDR "));
             Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in)));
             Write ( Message, string'(" of SYSMON is invalid. These must be set to 0000."));
             assert false report Message.all  severity error;
             DEALLOCATE(Message);
           end if;

          tmp_value := SLV_TO_INT(SLV=>di_in(4 downto 0));
      
          if (address = 40) then

           if (((tmp_value = 6) or ( tmp_value = 7) or ((tmp_value >= 10) and (tmp_value <= 15)))) then
             Write ( Message, string'(" Invalid Input Warning : The DI bit[4:0] at DADDR "));
             Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in)));
             Write ( Message, string'(" is  "));
            Write ( Message, bit_vector'(TO_BITVECTOR(di_in(4 downto 0))));
             Write ( Message, string'(", which is invalid analog channel."));
             assert false report Message.all  severity warning;
             DEALLOCATE(Message);
           end if;

           if ((cfg_reg1(13 downto 12)="11") and (di_in(8)='1') and (tmp_value /= 3) and (tmp_value < 16)) then
             Write ( Message, string'(" Invalid Input Warning : The DI value is "));
             Write ( Message, bit_vector'(TO_BITVECTOR(di_in)));
             Write ( Message, string'(" at DADDR "));
             Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in)));
             Write ( Message, string'(". Bit[8] of DI must be set to 0. Long acquistion mode is only allowed for external channels."));
             assert false report Message.all  severity warning;
             DEALLOCATE(Message);
           end if;

           if ((cfg_reg1(13 downto 12)="11") and (di_in(9)='1') and (tmp_value /= 3) and (tmp_value < 16)) then
             Write ( Message, string'(" Invalid Input Warning : The DI value is "));
             Write ( Message, bit_vector'(TO_BITVECTOR(di_in)));
             Write ( Message, string'(" at DADDR "));
             Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in)));
             Write ( Message, string'(". Bit[9] of DI must be set to 0. Event mode timing can only be used with external channels."));
             assert false report Message.all  severity warning;
             DEALLOCATE(Message);
           end if;

           if ((cfg_reg1(13 downto 12)="11") and (di_in(13 downto 12)/="00") and (seq_chan_reg1 /= X"0000") and (seq_chan_reg2 /= X"0000")) then
             Write ( Message, string'(" Invalid Input Warning : The Control Regiter 48h and 49h are "));
             Write ( Message, bit_vector'(TO_BITVECTOR(seq_chan_reg1)));
             Write ( Message, string'(" and  "));
             Write ( Message, bit_vector'(TO_BITVECTOR(seq_chan_reg2)));
             Write ( Message, string'(". Those registers should be set to 0000h in single channel mode and averaging enabled."));
             assert false report Message.all  severity warning;
             DEALLOCATE(Message);
           end if;
        end if;

          tmp_value := SLV_TO_INT(SLV=>cfg_reg0(4 downto 0));

          if (address = 41) then

           if ((di_in(13 downto 12)="11") and (cfg_reg0(8)='1') and (tmp_value /= 3) and (tmp_value < 16)) then
             Write ( Message, string'(" Invalid Input Warning : The Control Regiter 40h value is "));
             Write ( Message, bit_vector'(TO_BITVECTOR(cfg_reg0)));
             Write ( Message, string'(". Bit[8] of Control Regiter 40h must be set to 0. Long acquistion mode is only allowed for external channels."));
             assert false report Message.all  severity warning;
             DEALLOCATE(Message);
           end if;

           if ((di_in(13 downto 12)="11") and (cfg_reg0(9)='1') and (tmp_value /= 3) and (tmp_value < 16)) then
             Write ( Message, string'(" Invalid Input Warning : The Control Regiter 40h value is "));
             Write ( Message, bit_vector'(TO_BITVECTOR(cfg_reg0)));
             Write ( Message, string'(". Bit[9] of Control Regiter 40h must be set to 0. Event mode timing can only be used with external channels."));
             assert false report Message.all  severity warning;
             DEALLOCATE(Message);
           end if;

           if ((di_in(13 downto 12) /= "11") and (seq_acq_reg1(10 downto 0) /= "00000000000") and (seq_acq_reg1(15 downto 12) /= "0000")) then
             Write ( Message, string'(" Invalid Input Warning : The Control Regiter 4Eh is "));
             Write ( Message, bit_vector'(TO_BITVECTOR(seq_acq_reg1)));
             Write ( Message, string'(". Bit[15:12] and bit[10:0] of this register must be set to 0. Long acquistion mode is only allowed for external channels."));
             assert false report Message.all  severity warning;
             DEALLOCATE(Message);
           end if;

           if ((di_in(13 downto 12) = "11") and (cfg_reg0(13 downto 12) /= "00") and (seq_chan_reg1 /= X"0000") and (seq_chan_reg2 /= X"0000")) then
             Write ( Message, string'(" Invalid Input Warning : The Control Regiter 48h and 49h are "));
             Write ( Message, bit_vector'(TO_BITVECTOR(seq_chan_reg1)));
             Write ( Message, string'(" and  "));
             Write ( Message, bit_vector'(TO_BITVECTOR(seq_chan_reg2)));
             Write ( Message, string'(". Those registers should be set to 0000h in single channel mode and averaging enabled."));
             assert false report Message.all  severity warning;
             DEALLOCATE(Message);
           end if;
        end if;
       end if;



        if (daddr_in = "1000001" ) then
           if (dwe_in = '1' and den_in = '1') then

                if (di_in(13 downto 12) /= cfg_reg1(13 downto 12)) then
                            seq_reset <= '1';
                else
                            seq_reset <= '0';
                end if;

                if (di_in(13 downto 12) /= "11" ) then
                            seq_en_drp <= '1';
                else
                            seq_en_drp <= '0';
                end if;
             else  
                        seq_reset <= '0';
                        seq_en_drp <= '0';
             end if;
        else 
            seq_reset <= '0';
            seq_en_drp <= '0';
        end if;
     end if;
  end process;

  tmp_dr_sram_out <= dr_sram(daddr_in_lat_int) when (daddr_in_lat_int >= 64 and
                daddr_in_lat_int <= 87) else "0000000000000000";

  tmp_data_reg_out <= data_reg(daddr_in_lat_int) when (daddr_in_lat_int >= 0 and
                daddr_in_lat_int <= 38) else "0000000000000000";

  do_out_rdtmp_p : process( daddr_in_lat, tmp_data_reg_out, tmp_dr_sram_out ) 
      variable Message : line;
      variable valid_daddr : boolean := false;
  begin
           valid_daddr := addr_is_valid(daddr_in_lat);
           daddr_in_lat_int <= slv_to_int(daddr_in_lat);
           if (valid_daddr) then
              if ((daddr_in_lat_int > 88) or 
                               (daddr_in_lat_int >= 13 and daddr_in_lat_int <= 15)
                or (daddr_in_lat_int >= 39 and daddr_in_lat_int <= 63)) then 
                    do_out_rdtmp <= "XXXXXXXXXXXXXXXX";
              end if;
        
              if ((daddr_in_lat_int >= 0 and  daddr_in_lat_int <= 12) or 
              (daddr_in_lat_int >= 16 and daddr_in_lat_int <= 38)) then

                   do_out_rdtmp <= tmp_data_reg_out;

               elsif (daddr_in_lat_int >= 64 and daddr_in_lat_int <= 87) then
 
                    do_out_rdtmp <= tmp_dr_sram_out;
             end if;
          end if;
   end process;

-- end DRP RAM


  cfg_reg0 <= dr_sram(16#40#);
  cfg_reg1 <= dr_sram(16#41#);
  cfg_reg2 <= dr_sram(16#42#);
  seq_chan_reg1 <= dr_sram(16#48#);
  seq_chan_reg2 <= dr_sram(16#49#);
  seq_avg_reg1 <= dr_sram(16#4A#);
  seq_avg_reg2 <= dr_sram(16#4B#);
  seq_du_reg1 <= dr_sram(16#4C#);
  seq_du_reg2 <= dr_sram(16#4D#);
  seq_acq_reg1 <= dr_sram(16#4E#);
  seq_acq_reg2 <= dr_sram(16#4F#);

  seq1_0 <= cfg_reg1(13 downto 12);

  drp_update_p : process 
    variable seq_bits : std_logic_vector( 1 downto 0);
   begin
    if (rst_in = '1') then
       wait until (rising_edge(dclk_in));
       wait until (rising_edge(dclk_in));
           seq_bits := seq1_0;
    elsif (rising_edge(drp_update)) then
       seq_bits := curr_seq1_0;
    end if;

    if (rising_edge(drp_update) or (rst_in = '1')) then
       if (seq_bits = "00") then 
         alarm_en <= "000";
         ot_en <= '1';
       else 
         ot_en  <= not cfg_reg1(0);
         alarm_en <= not cfg_reg1(3 downto 1);
       end if;
    end if;
      wait on drp_update, rst_in;
   end process;


-- Clock divider, generate  and adcclk

    sysclk_p : process(dclk_in)
    begin
      if (rising_edge(dclk_in)) then
          sysclk <= not sysclk;
      end if;
    end process;


    curr_clkdiv_sel_int_p : process (curr_clkdiv_sel)
    begin
        curr_clkdiv_sel_int <= SLV_TO_INT(curr_clkdiv_sel);
    end process;

    clk_count_p : process(dclk_in)
       variable clk_count : integer := -1;
    begin
     
       if (rising_edge(dclk_in)) then
        if (curr_clkdiv_sel_int > 2 ) then 
            if (clk_count >= curr_clkdiv_sel_int - 1) then
                clk_count := 0;
            else
                clk_count := clk_count + 1;
            end if;

            if (clk_count > (curr_clkdiv_sel_int/2) - 1) then
               adcclk_tmp <= '1';
            else
               adcclk_tmp <= '0';
            end if;
        else
             adcclk_tmp <= not adcclk_tmp;
         end if;
      end if;
   end process;

        curr_clkdiv_sel <= cfg_reg2(15 downto 8);
        adcclk_div1 <= '0' when (curr_clkdiv_sel_int > 1) else '1';
        adcclk <=  not sysclk when adcclk_div1 = '1' else adcclk_tmp;

-- end clock divider

-- latch configuration registers
    acq_latch_p : process ( seq1_0, adc_s1_flag, curr_seq, cfg_reg0_adc, rst_in)
    begin
        if ((seq1_0 = "01" and adc_s1_flag = '0') or seq1_0 = "10") then
            acq_acqsel <= curr_seq(8);
        elsif (seq1_0 = "11") then
            acq_acqsel <= cfg_reg0_adc(8);
        else
            acq_acqsel <= '0';
        end if;

        if (rst_in = '0') then
          if (seq1_0 /= "11" and  adc_s1_flag = '0') then
            acq_avg <= curr_seq(13 downto 12);
            acq_chan <= curr_seq(4 downto 0);
            acq_b_u <= curr_seq(10);
          else 
            acq_avg <= cfg_reg0_adc(13 downto 12);
            acq_chan <= cfg_reg0_adc(4 downto 0);
            acq_b_u <= cfg_reg0_adc(10);
          end if;
        end if;
    end process;

    acq_chan_index <= SLV_TO_INT(acq_chan);

    conv_end_reg_read_P : process ( adcclk, rst_in)
    begin
       if (rst_in = '1') then
           conv_end_reg_read <= "0000";
       elsif (rising_edge(adcclk)) then
           conv_end_reg_read(3 downto 1) <= conv_end_reg_read(2 downto 0);  
           conv_end_reg_read(0) <= single_chan_conv_end or conv_end;
       end if;
   end process;

-- synch to DCLK
       busy_reg_read_P : process ( dclk_in, rst_in)
    begin
       if (rst_in = '1') then
           busy_reg_read <= '1';
       elsif (rising_edge(dclk_in)) then
           busy_reg_read <= not conv_end_reg_read(2);
       end if;
   end process;

   cfg_reg0_adc_P : process
      variable  first_after_reset : std_ulogic := '1';
   begin
       if (rst_in='1') then
          cfg_reg0_seq <= X"0000";
          cfg_reg0_adc  <= X"0000";
          acq_e_c <= '0';
          first_after_reset := '1';
       elsif (falling_edge(busy_reg_read) or falling_edge(rst_in)) then
          wait until (rising_edge(dclk_in));
          wait until (rising_edge(dclk_in));
          wait until (rising_edge(dclk_in));
          if (first_after_reset = '1') then
             first_after_reset := '0';
             cfg_reg0_adc <= cfg_reg0;
             cfg_reg0_seq <= cfg_reg0;
          else
             cfg_reg0_adc <= cfg_reg0_seq;
             cfg_reg0_seq <= cfg_reg0;
          end if;
          acq_e_c <= cfg_reg0(9);
       end if;
       wait on busy_reg_read, rst_in;
   end process;

   busy_r_p : process(conv_start, busy_r_rst, rst_in)
   begin
      if (rst_in = '1') then
         busy_r <= '0';
      elsif (rising_edge(conv_start) and rst_lock = '0') then
          busy_r <= '1';
      elsif (rising_edge(busy_r_rst)) then
          busy_r <= '0';
      end if;
   end process;

   curr_seq1_0_p : process( busy_out)
   begin
     if (falling_edge( busy_out)) then
        if (adc_s1_flag = '1') then
            curr_seq1_0 <= "00";
        else
            curr_seq1_0 <= seq1_0;
        end if;
     end if;
   end process;

   start_conv_p : process ( conv_start, rst_in)
      variable       Message : line;
   begin
     if (rst_in = '1') then
        analog_mux_in <= 0.0;
        curr_chan <= "00000";
     elsif (rising_edge(conv_start)) then
        if ( ((acq_chan_index = 3) or (acq_chan_index >= 16 and acq_chan_index <= 31))) then
            analog_mux_in <= analog_in_diff(acq_chan_index);
        else
             analog_mux_in <= analog_in_uni(acq_chan_index);
        end if;
        curr_chan <= acq_chan;
        curr_seq1_0_lat <= curr_seq1_0;
          
        if (acq_chan_index = 6 or acq_chan_index = 7 or (acq_chan_index >= 10 and acq_chan_index <= 15)) then
            Write ( Message, string'(" Invalid Input Warning : The analog channel  "));
            Write ( Message, acq_chan_index);
            Write ( Message, string'(" to SYSMON is invalid."));
            assert false report Message.all severity warning;
        end if;
           
        if ((seq1_0 = "01" and adc_s1_flag = '0') or seq1_0 = "10" or seq1_0 = "00") then
                curr_avg_set <= curr_seq(13 downto 12);
                curr_b_u <= curr_seq(10);
                curr_e_c <= '0';
                curr_acq <= curr_seq(8);
            else 
                curr_avg_set <= acq_avg;
                curr_b_u <= acq_b_u;
                curr_e_c <= cfg_reg0(9);
                curr_acq <= cfg_reg0(8);
        end if;
      end if; 

    end  process;

-- end latch configuration registers

-- sequence control

     seq_en_dly <= seq_en after 1 ps;

    seq_num_p : process(seq_en_dly)
       variable seq_num_tmp : integer := 0;
       variable si_tmp : integer := 0;
       variable si : integer := 0;
    begin
     if (rising_edge(seq_en_dly)) then
       if (seq1_0  = "01" or seq1_0 = "10") then
          seq_num_tmp := 0;
          for I in 0 to 15 loop
              si := I;
              if (seq_chan_reg1(si) = '1') then
                 seq_num_tmp := seq_num_tmp + 1;
                 seq_mem(seq_num_tmp) <= si;
              end if;
          end loop;
          for I in 16 to 31 loop
              si := I;
              si_tmp := si-16;
              if (seq_chan_reg2(si_tmp) = '1') then
                   seq_num_tmp := seq_num_tmp + 1;
                   seq_mem(seq_num_tmp) <= si;
              end if;
          end loop;
          seq_num <= seq_num_tmp;
        elsif (seq1_0  = "00") then
           seq_num <= 4;
           seq_mem(1) <= 0;
           seq_mem(2) <= 8;
           seq_mem(3) <= 9;
           seq_mem(4) <= 10;
         end if;
     end if;
   end process;


   curr_seq_p : process(seq_count, seq_en_dly)
      variable seq_curr_i : std_logic_vector(4 downto 0);
      variable seq_curr_index : integer;
      variable tmp_value : integer;
      variable curr_seq_tmp : std_logic_vector(15  downto 0);
    begin
    if (seq_count'event or falling_edge(seq_en_dly)) then
      seq_curr_index := seq_mem(seq_count);
      seq_curr_i := STD_LOGIC_VECTOR(TO_UNSIGNED(seq_curr_index, 5));
      curr_seq_tmp := "0000000000000000";
      if (seq_curr_index >= 0 and seq_curr_index <= 15) then
          curr_seq_tmp(2 downto 0) := seq_curr_i(2 downto 0);
          curr_seq_tmp(4 downto 3) := "01";
          curr_seq_tmp(8) := seq_acq_reg1(seq_curr_index);
          curr_seq_tmp(10) := seq_du_reg1(seq_curr_index);
          if (seq1_0 = "00") then
             curr_seq_tmp(13 downto 12) := "01";
          elsif (seq_avg_reg1(seq_curr_index) = '1') then
             curr_seq_tmp(13 downto 12) := cfg_reg0(13 downto 12);
          else
             curr_seq_tmp(13 downto 12) := "00";
          end if;
          if (seq_curr_index >= 0 and seq_curr_index <= 7) then
             curr_seq_tmp(4 downto 3) := "01";
          else
             curr_seq_tmp(4 downto 3) := "00";
          end if;
      elsif (seq_curr_index >= 16 and seq_curr_index <= 31) then
          tmp_value := seq_curr_index -16;
          curr_seq_tmp(4 downto 0) := seq_curr_i;
          curr_seq_tmp(8) := seq_acq_reg2(tmp_value);
          curr_seq_tmp(10) := seq_du_reg2(tmp_value);
          if (seq_avg_reg2(tmp_value) = '1') then
             curr_seq_tmp(13 downto 12) := cfg_reg0(13 downto 12);
          else
             curr_seq_tmp(13 downto 12) := "00";
          end if;
      end if;
      curr_seq <= curr_seq_tmp;
   end if;
   end process;

   eos_en_p : process (adcclk, rst_in)
   begin
        if (rst_in = '1') then 
            seq_count <= 1;
            eos_en <= '0';
        elsif (rising_edge(adcclk)) then
            if ((seq_count = seq_num  ) and (adc_state = CONV_STATE and next_state = END_STATE)
                 and  (curr_seq1_0_lat /= "11") and rst_lock = '0') then
                eos_tmp_en <= '1';
            else
                eos_tmp_en <= '0';
            end if;

            if ((eos_tmp_en = '1') and (seq_status_avg = 0))  then
                eos_en <= '1';
            else
                eos_en <= '0';
            end if;

            if (eos_tmp_en = '1' or curr_seq1_0_lat = "11") then
                seq_count <= 1;
            elsif (seq_count_en = '1' ) then
               if (seq_count >= 32) then
                  seq_count <= 1;
               else
                seq_count <= seq_count +1;
               end if;
            end if;
        end if; 
   end process;

-- end sequence control

-- Acquisition

   busy_out_dly <= busy_out after 10 ps;

   short_acq_p : process(adc_state, rst_in, first_acq)
   begin
       if (rst_in = '1') then
           shorten_acq <= 0;
       elsif (adc_state'event or first_acq'event) then
         if  ((busy_out_dly = '0') and (adc_state=ACQ_STATE) and (first_acq='1')) then
           shorten_acq <= 1;
         else
           shorten_acq <= 0;
         end if;
       end if;
   end process;

   acq_count_p : process (adcclk, rst_in)
   begin
        if (rst_in = '1') then
            acq_count <= 1;
            first_acq <= '1';
        elsif (rising_edge(adcclk)) then
            if (adc_state = ACQ_STATE and rst_lock = '0' and acq_e_c = '0') then 
                first_acq <= '0';

                if (acq_acqsel = '1') then
                    if (acq_count <= 11) then
                        acq_count <= acq_count + 1 + shorten_acq;
                    end if;
                else 
                    if (acq_count <= 4) then
                        acq_count <= acq_count + 1 + shorten_acq;
                    end if;
                end if;

                if (next_state = CONV_STATE) then
                    if ((acq_acqsel = '1' and acq_count < 10) or (acq_acqsel = '0' and acq_count < 4)) then
                    assert false report "Warning: Acquisition time not enough for SYSMON."
                    severity warning;
                    end if;
                end if;
            else
                if (first_acq = '1') then
                    acq_count <= 1;
                else
                    acq_count <= 0;
                end if;
            end if;
        end if; 
    end process;

    conv_start_con_p: process(adc_state, acq_acqsel, acq_count)
    begin
      if (adc_state = ACQ_STATE) then
        if (rst_lock = '0') then
         if ((seq_reset_flag = '0' or (seq_reset_flag = '1' and curr_clkdiv_sel_int > 3))
           and ((acq_acqsel = '1' and acq_count > 10) or (acq_acqsel = '0' and acq_count > 4))) then
                 conv_start_cont <= '1';
         else
                 conv_start_cont <= '0';
         end if;
       end if;
     else
         conv_start_cont <= '0';
     end if;
   end process;
 
   conv_start_sel <= convst_in when (acq_e_c = '1') else conv_start_cont;
   reset_conv_start_tmp <= '1' when (conv_count=2) else '0';
   reset_conv_start <= rst_in or reset_conv_start_tmp;
  
   conv_start_p : process(conv_start_sel, reset_conv_start)
   begin
      if (reset_conv_start ='1') then
          conv_start <= '0';
      elsif (rising_edge(conv_start_sel)) then
          conv_start <= '1';
      end if;
   end process;

-- end acquisition


-- Conversion
    conv_result_p : process (adc_state, next_state, curr_chan, curr_chan_index, analog_mux_in, curr_b_u)
       variable conv_result_int_i : integer := 0;
       variable conv_result_int_tmp : integer := 0;
       variable conv_result_int_tmp_rl : real := 0.0;
       variable adc_analog_tmp : real := 0.0;
    begin
        if ((adc_state = CONV_STATE and next_state = END_STATE) or adc_state = END_STATE) then
            if (curr_chan = "00000") then    -- temperature conversion
                    adc_analog_tmp := (analog_mux_in + 273.0) * 130.0382;
                    adc_temp_result <= adc_analog_tmp;
                    if (adc_analog_tmp >= 65535.0) then
                        conv_result_int_i := 65535;
                    elsif (adc_analog_tmp < 0.0) then
                        conv_result_int_i := 0;
                    else 
                        conv_result_int_tmp := real2int(adc_analog_tmp);
                        conv_result_int_tmp_rl := int2real(conv_result_int_tmp);
                        if (adc_analog_tmp - conv_result_int_tmp_rl > 0.9999) then
                            conv_result_int_i := conv_result_int_tmp + 1;
                        else
                            conv_result_int_i := conv_result_int_tmp;
                        end if;
                    end if;
                    conv_result_int <= conv_result_int_i;
                    conv_result <= STD_LOGIC_VECTOR(TO_UNSIGNED(conv_result_int_i, 16));
            elsif (curr_chan = "00001" or curr_chan = "00010") then     -- internal power conversion
                    adc_analog_tmp := analog_mux_in * 65536.0 / 3.0;
                    adc_intpwr_result <= adc_analog_tmp;
                    if (adc_analog_tmp >= 65535.0) then
                        conv_result_int_i := 65535;
                    elsif (adc_analog_tmp < 0.0) then
                        conv_result_int_i := 0;
                    else 
                       conv_result_int_tmp := real2int(adc_analog_tmp);
                        conv_result_int_tmp_rl := int2real(conv_result_int_tmp);
                        if (adc_analog_tmp - conv_result_int_tmp_rl > 0.9999) then
                            conv_result_int_i := conv_result_int_tmp + 1;
                        else
                            conv_result_int_i := conv_result_int_tmp;
                        end if;
                    end if;
                    conv_result_int <= conv_result_int_i;
                    conv_result <= STD_LOGIC_VECTOR(TO_UNSIGNED(conv_result_int_i, 16));
            elsif ((curr_chan = "00011") or ((curr_chan_index >= 16) and  (curr_chan_index <= 31))) then
                    adc_analog_tmp :=  (analog_mux_in) * 65536.0;
                    adc_ext_result <= adc_analog_tmp;
                    if (curr_b_u = '1')  then
                        if (adc_analog_tmp > 32767.0) then
                             conv_result_int_i := 32767;
                        elsif (adc_analog_tmp < -32768.0) then
                             conv_result_int_i := -32768;
                        else 
                            conv_result_int_tmp := real2int(adc_analog_tmp);
                            conv_result_int_tmp_rl := int2real(conv_result_int_tmp);
                            if (adc_analog_tmp - conv_result_int_tmp_rl > 0.9999) then
                                conv_result_int_i := conv_result_int_tmp + 1;
                            else
                                conv_result_int_i := conv_result_int_tmp;
                            end if;
                        end if;
                    conv_result_int <= conv_result_int_i;
                    conv_result <= STD_LOGIC_VECTOR(TO_SIGNED(conv_result_int_i, 16));
                    else
                       if (adc_analog_tmp  > 65535.0) then
                             conv_result_int_i := 65535;
                        elsif (adc_analog_tmp  < 0.0) then
                             conv_result_int_i := 0;
                        else
                            conv_result_int_tmp := real2int(adc_analog_tmp);
                            conv_result_int_tmp_rl := int2real(conv_result_int_tmp);
                            if (adc_analog_tmp - conv_result_int_tmp_rl > 0.9999) then
                                conv_result_int_i := conv_result_int_tmp + 1;
                            else
                                conv_result_int_i := conv_result_int_tmp;
                            end if;
                        end if;
                    conv_result_int <= conv_result_int_i;
                    conv_result <= STD_LOGIC_VECTOR(TO_UNSIGNED(conv_result_int_i, 16));
                    end if;
            else 
                conv_result_int <= 0;
                conv_result <= "0000000000000000";
            end if;
         end if;

    end process;


    conv_count_p : process (adcclk, rst_in)
    begin
        if (rst_in = '1') then
            conv_count <= 6;
            conv_end <= '0';
            seq_status_avg <= 0;
            busy_r_rst <= '0';
            busy_r_rst_done <= '0';
            for i in 0 to 31 loop
                conv_avg_count(i) <= 0;     -- array of integer
            end loop;
            single_chan_conv_end <= '0';
        elsif (rising_edge(adcclk)) then
            if (adc_state = ACQ_STATE) then
               if (busy_r_rst_done = '0') then
                    busy_r_rst <= '1';
               else
                    busy_r_rst <= '0';
               end if;
               busy_r_rst_done <= '1';
            end if;

            if (adc_state = ACQ_STATE and conv_start = '1') then
                conv_count <= 0;
                conv_end <= '0';
            elsif (adc_state = CONV_STATE ) then
                busy_r_rst_done <= '0';
                conv_count <= conv_count + 1;

                if (((curr_chan /= "01000" ) and (conv_count = conv_time )) or 
              ((curr_chan = "01000") and (conv_count = conv_time_cal_1) and (first_cal_chan = '1'))
              or ((curr_chan = "01000") and (conv_count = conv_time_cal) and (first_cal_chan = '0'))) then
                    conv_end <= '1';
                else
                    conv_end <= '0';
                end if;
            else  
                conv_end <= '0';
                conv_count <= 0;
            end if;

           single_chan_conv_end <= '0';
           if ( (conv_count = conv_time) or (conv_count = 44)) then
                   single_chan_conv_end <= '1';
           end if;

            if (adc_state = CONV_STATE and next_state = END_STATE and rst_lock = '0') then
                case curr_avg_set is
                    when "00" => eoc_en <= '1';
                                conv_avg_count(curr_chan_index) <= 0;
                    when "01" =>
                                if (conv_avg_count(curr_chan_index) = 15) then
                                  eoc_en <= '1';
                                  conv_avg_count(curr_chan_index) <= 0;
                                  seq_status_avg <= seq_status_avg - 1;
                                else 
                                  eoc_en <= '0';
                                  if (conv_avg_count(curr_chan_index) = 0) then
                                      seq_status_avg <= seq_status_avg + 1;
                                  end if;
                                  conv_avg_count(curr_chan_index) <= conv_avg_count(curr_chan_index) + 1;
                                end if;
                   when "10" =>
                                if (conv_avg_count(curr_chan_index) = 63) then
                                    eoc_en <= '1';
                                    conv_avg_count(curr_chan_index) <= 0;
                                    seq_status_avg <= seq_status_avg - 1;
                                else 
                                    eoc_en <= '0';
                                    if (conv_avg_count(curr_chan_index) = 0) then
                                        seq_status_avg <= seq_status_avg + 1;
                                    end if;
                                    conv_avg_count(curr_chan_index) <= conv_avg_count(curr_chan_index) + 1;
                                end if;
                    when "11" => 
                                if (conv_avg_count(curr_chan_index) = 255) then
                                    eoc_en <= '1';
                                    conv_avg_count(curr_chan_index) <= 0;
                                    seq_status_avg <= seq_status_avg - 1;
                                else 
                                    eoc_en <= '0';
                                    if (conv_avg_count(curr_chan_index) = 0) then
                                        seq_status_avg <= seq_status_avg + 1;
                                    end if;
                                    conv_avg_count(curr_chan_index) <= conv_avg_count(curr_chan_index) + 1;
                                end if;
                   when  others => eoc_en <= '0';
                end case;
            else
                eoc_en <= '0';
            end if;

            if (adc_state = END_STATE) then
                   conv_result_reg <= conv_result;
            end if;
        end if;
   end process;

-- end conversion

   
-- average
    
    conv_acc_result_p : process(adcclk, rst_in)
       variable conv_acc_vec : std_logic_vector(23 downto 0);
       variable conv_acc_vec_int  : integer;
    begin
        if (rst_in = '1') then 
            for j in 0 to 31 loop
                conv_acc(j) <= 0;
            end loop;
            conv_acc_result <= "0000000000000000";
        elsif (rising_edge(adcclk)) then
            if (adc_state = CONV_STATE and  next_state = END_STATE) then
                if (curr_avg_set /= "00" and rst_lock /= '1') then
                    conv_acc(curr_chan_index) <= conv_acc(curr_chan_index) + conv_result_int;
                else
                    conv_acc(curr_chan_index) <= 0;
                end if;
            elsif (eoc_en = '1') then
                conv_acc_vec_int := conv_acc(curr_chan_index);
                if ((curr_b_u = '1') and (((curr_chan_index >= 16) and (curr_chan_index <= 31))
                   or (curr_chan_index = 3))) then
                    conv_acc_vec := STD_LOGIC_VECTOR(TO_SIGNED(conv_acc_vec_int, 24));
                else
                    conv_acc_vec := STD_LOGIC_VECTOR(TO_UNSIGNED(conv_acc_vec_int, 24));
                end if;
                case curr_avg_set(1 downto 0) is
                  when "00" => conv_acc_result <= "0000000000000000";
                  when "01" => conv_acc_result <= conv_acc_vec(19 downto 4);
                  when "10" => conv_acc_result <= conv_acc_vec(21 downto 6);
                  when "11" => conv_acc_result <= conv_acc_vec(23 downto 8);
                  when others => conv_acc_result <= "0000000000000000";
                end case;
                conv_acc(curr_chan_index) <= 0;
            end if;
        end if;
    end process;

-- end average   

-- single sequence
    adc_s1_flag_p : process(adcclk, rst_in)
    begin
        if (rst_in = '1') then
            adc_s1_flag <= '0';
        elsif (rising_edge(adcclk)) then 
            if (adc_state = SINGLE_SEQ_STATE) then
                adc_s1_flag <= '1';
            end if;
        end if;
    end process;


--  end state
    eos_eoc_p: process(adcclk, rst_in)
    begin
        if (rst_in = '1') then
            seq_count_en <= '0';
            eos_out_tmp <= '0';
            eoc_out_tmp <= '0';
        elsif (rising_edge(adcclk)) then
            if ((adc_state = CONV_STATE and next_state = END_STATE) and (curr_seq1_0_lat /= "11")
                  and (rst_lock = '0')) then
                seq_count_en <= '1';
            else
                seq_count_en <= '0';
            end if;

            if (rst_lock = '0') then
                 eos_out_tmp <= eos_en;
                 eoc_en_delay <= eoc_en;
                 eoc_out_tmp <= eoc_en_delay;
            else 
                 eos_out_tmp <= '0';
                 eoc_en_delay <= '0';
                 eoc_out_tmp <= '0';
            end if;
        end if;
   end process;

    data_reg_p : process(eoc_out, rst_in_not_seq)
       variable tmp_uns1 : unsigned(15 downto 0);
       variable tmp_uns2 : unsigned(15 downto 0);
       variable tmp_uns3 : unsigned(15 downto 0);
    begin
        if (rst_in_not_seq = '1') then
            for k in  32 to  39 loop
                if (k >= 36) then
                    data_reg(k) <= "1111111111111111";
                else
                    data_reg(k) <= "0000000000000000";
                end if;
            end loop;
        elsif (rising_edge(eoc_out)) then
            if ( rst_lock = '0') then
                if ((curr_chan_index >= 0 and curr_chan_index <= 3) or 
                          (curr_chan_index >= 16 and curr_chan_index <= 31)) then
                    if (curr_avg_set = "00") then
                        data_reg(curr_chan_index) <= conv_result_reg;
                    else
                        data_reg(curr_chan_index) <= conv_acc_result;
                    end if;
                end if;
                if (curr_chan_index = 4) then
                    data_reg(curr_chan_index) <= X"D555";
                end if;
                if (curr_chan_index = 5) then
                    data_reg(curr_chan_index) <= X"0000";
                end if;
                if (curr_chan_index = 0 or curr_chan_index = 1 or curr_chan_index = 2) then
                    tmp_uns2 := UNSIGNED(data_reg(32 + curr_chan_index));
                    tmp_uns3 := UNSIGNED(data_reg(36 + curr_chan_index));
                    if (curr_avg_set = "00") then
                        tmp_uns1 := UNSIGNED(conv_result_reg);
                        if (tmp_uns1 > tmp_uns2) then
                            data_reg(32 + curr_chan_index) <= conv_result_reg;
                         end if;
                        if (tmp_uns1 < tmp_uns3) then
                            data_reg(36 + curr_chan_index) <= conv_result_reg;
                        end if;
                    else 
                        tmp_uns1 := UNSIGNED(conv_acc_result);
                        if (tmp_uns1 > tmp_uns2) then
                            data_reg(32 + curr_chan_index) <= conv_acc_result;
                        end if;
                        if (tmp_uns1 < tmp_uns3) then
                            data_reg(36 + curr_chan_index) <= conv_acc_result;
                        end if;
                    end if;
                end if;
           end if;
       end if;
     end process;

    data_written_p : process(busy_r, rst_in_not_seq)
    begin
       if (rst_in_not_seq = '1') then
            data_written <= X"0000";
       elsif (falling_edge(busy_r)) then
          if (curr_avg_set = "00") then
               data_written <= conv_result_reg;
           else
              data_written <= conv_acc_result;
           end if;
       end if;
    end process;

-- eos and eoc

    eoc_out_tmp1_p : process (eoc_out_tmp, eoc_out, rst_in)
    begin
           if (rst_in = '1') then
              eoc_out_tmp1 <= '0';
           elsif (rising_edge(eoc_out)) then
               eoc_out_tmp1 <= '0';
           elsif (rising_edge(eoc_out_tmp)) then
               if (curr_chan /= "01000") then
                  eoc_out_tmp1 <= '1';
               else
                  eoc_out_tmp1 <= '0';
               end if;
           end if;
    end process;

    eos_out_tmp1_p : process (eos_out_tmp, eos_out, rst_in)
    begin
           if (rst_in = '1') then
              eos_out_tmp1 <= '0';
           elsif (rising_edge(eos_out)) then
               eos_out_tmp1 <= '0';
           elsif (rising_edge(eos_out_tmp)) then
               eos_out_tmp1 <= '1';
           end if;
    end process;

    busy_out_low_edge <= '1' when (busy_out='0' and busy_out_sync='1') else '0';

    eoc_eos_out_p : process (dclk_in, rst_in)
    begin
      if (rst_in = '1') then
          op_count <= 15;
          busy_out_sync <= '0';
          drp_update <= '0';
          alarm_update <= '0';
          eoc_out <= '0';
          eos_out <= '0';
      elsif ( rising_edge(dclk_in)) then
         busy_out_sync <= busy_out;   
         if (op_count = 3) then
            drp_update <= '1';
          else 
            drp_update <= '0';
          end if;
          if (op_count = 5 and eoc_out_tmp1 = '1') then
             alarm_update <= '1';
          else
             alarm_update <= '0';
          end if;
          if (op_count = 9 ) then
             eoc_out <= eoc_out_tmp1;
          else
             eoc_out <= '0';
          end if;
          if (op_count = 9) then
             eos_out <= eos_out_tmp1;
          else
             eos_out <= '0';
          end if;
          if (busy_out_low_edge = '1') then
              op_count <= 0;
          elsif (op_count < 15) then
              op_count <= op_count +1;
          end if;
      end if;
   end process;

-- end eos and eoc


-- alarm

    alm_reg_p : process(alarm_update, rst_in_not_seq )
       variable  tmp_unsig1 : unsigned(15 downto 0);
       variable  tmp_unsig2 : unsigned(15 downto 0);
       variable  tmp_unsig3 : unsigned(15 downto 0);
    begin
     if (rst_in_not_seq = '1') then
        ot_out_reg <= '0';
        alarm_out_reg <= "000";
     elsif (rising_edge(alarm_update)) then
       if (rst_lock = '0') then
          if (curr_chan_lat = "00000") then
            tmp_unsig1 := UNSIGNED(data_written);
            tmp_unsig2 := UNSIGNED(dr_sram(16#57#));
            if (tmp_unsig1 >= ot_limit_reg) then
                ot_out_reg <= '1';
            elsif (((tmp_unsig1 < tmp_unsig2) and (curr_seq1_0_lat /= "00")) or
                           ((curr_seq1_0_lat = "00") and (tmp_unsig1 < ot_sf_limit_low_reg))) then
                ot_out_reg <= '0';
            end if;
            tmp_unsig2 := UNSIGNED(dr_sram(16#50#));
            tmp_unsig3 := UNSIGNED(dr_sram(16#54#));
            if ( tmp_unsig1 > tmp_unsig2) then
                     alarm_out_reg(0) <= '1';
            elsif (tmp_unsig1 <= tmp_unsig3) then
                     alarm_out_reg(0) <= '0';
            end if;
          end if;
          tmp_unsig1 := UNSIGNED(data_written);
          tmp_unsig2 := UNSIGNED(dr_sram(16#51#));
          tmp_unsig3 := UNSIGNED(dr_sram(16#55#));
          if (curr_chan_lat = "00001") then
             if ((tmp_unsig1 > tmp_unsig2) or (tmp_unsig1 < tmp_unsig3)) then
                      alarm_out_reg(1) <= '1';
             else
                      alarm_out_reg(1) <= '0';
             end if;
          end if;
          tmp_unsig1 := UNSIGNED(data_written);
          tmp_unsig2 := UNSIGNED(dr_sram(16#52#));
          tmp_unsig3 := UNSIGNED(dr_sram(16#56#));
          if (curr_chan_lat = "00010") then
              if ((tmp_unsig1 > tmp_unsig2) or (tmp_unsig1 < tmp_unsig3)) then
                      alarm_out_reg(2) <= '1';
                 else
                      alarm_out_reg(2) <= '0';
              end if;
          end if;
     end if;
    end if;
   end process;


    alm_p : process(ot_out_reg, ot_en, alarm_out_reg, alarm_en)
    begin
             ot_out <= ot_out_reg and ot_en;
             alarm_out(0) <= alarm_out_reg(0) and alarm_en(0);
             alarm_out(1) <= alarm_out_reg(1) and alarm_en(1);
             alarm_out(2) <= alarm_out_reg(2) and alarm_en(2);
      end process;

-- end alarm


  READFILE_P : process
      file in_file : text;
      variable open_status : file_open_status;
      variable in_buf    : line;
      variable str_token : string(1 to 12);
      variable str_token_in : string(1 to 12);
      variable str_token_tmp : string(1 to 12);
      variable next_time     : time := 0 ps; 
      variable pre_time : time := 0 ps; 
      variable time_val : integer := 0;
      variable a1   : real;

      variable commentline : boolean := false;
      variable HeaderFound : boolean := false;
      variable read_ok : boolean := false;
      variable token_len : integer;
      variable HeaderCount : integer := 0;

      variable vals : ANALOG_DATA := (others => 0.0);
      variable valsn : ANALOG_DATA := (others => 0.0);
      variable inchannel : integer := 0 ;
      type int_a is array (0 to 41) of integer;
      variable index_to_channel : int_a := (others => -1);
      variable low : integer := -1;
      variable low2 : integer := -1;
      variable sim_file_flag1 : std_ulogic := '0';
      variable file_line : integer := 0;

      type channm_array is array (0 to 31 ) of string(1 to  12);
      constant chanlist_p : channm_array := (
       0 => "TEMP" & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL,
       1 => "VCCINT" & NUL & NUL & NUL & NUL & NUL & NUL,
       2 => "VCCAUX" & NUL & NUL & NUL & NUL & NUL & NUL,	
       3 => "VP" & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL,
       4 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL &
             NUL & NUL,
       5 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL &
             NUL & NUL,
       6 => "xxxxxxxxxxxx",
       7 => "xxxxxxxxxxxx",
       8 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL &
             NUL & NUL,
       9 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL &
             NUL & NUL,
       10 => "xxxxxxxxxxxx",
       11 => "xxxxxxxxxxxx",
       12 => "xxxxxxxxxxxx",
       13 => "xxxxxxxxxxxx",
       14 => "xxxxxxxxxxxx",
       15 => "xxxxxxxxxxxx",
       16 => "VAUXP[0]" & NUL & NUL & NUL & NUL,
       17 => "VAUXP[1]" & NUL & NUL & NUL & NUL,
       18 => "VAUXP[2]" & NUL & NUL & NUL & NUL,
       19 => "VAUXP[3]" & NUL & NUL & NUL & NUL,
       20 => "VAUXP[4]" & NUL & NUL & NUL & NUL,
       21 => "VAUXP[5]" & NUL & NUL & NUL & NUL,
       22 => "VAUXP[6]" & NUL & NUL & NUL & NUL,
       23 => "VAUXP[7]" & NUL & NUL & NUL & NUL,
       24 => "VAUXP[8]" & NUL & NUL & NUL & NUL,
       25 => "VAUXP[9]" & NUL & NUL & NUL & NUL,
       26 => "VAUXP[10]" & NUL & NUL & NUL,
       27 => "VAUXP[11]" & NUL & NUL & NUL,
       28 => "VAUXP[12]" & NUL & NUL & NUL,
       29 => "VAUXP[13]" & NUL & NUL & NUL,
       30 => "VAUXP[14]" & NUL & NUL & NUL,
       31 => "VAUXP[15]" & NUL & NUL & NUL
      );
       
      constant chanlist_n : channm_array := (
       0 => "xxxxxxxxxxxx",
       1 => "xxxxxxxxxxxx",
       2 => "xxxxxxxxxxxx",
       3 => "VN" & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL,
       4 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL &
             NUL & NUL,
       5 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL &
             NUL & NUL,
       6 => "xxxxxxxxxxxx",
       7 => "xxxxxxxxxxxx",
       8 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL &
             NUL & NUL,
       9 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL &
             NUL & NUL,
       10 => "xxxxxxxxxxxx",
       11 => "xxxxxxxxxxxx",
       12 => "xxxxxxxxxxxx",
       13 => "xxxxxxxxxxxx",
       14 => "xxxxxxxxxxxx",
       15 => "xxxxxxxxxxxx",
       16 => "VAUXN[0]" & NUL & NUL & NUL & NUL,
       17 => "VAUXN[1]" & NUL & NUL & NUL & NUL,
       18 => "VAUXN[2]" & NUL & NUL & NUL & NUL,
       19 => "VAUXN[3]" & NUL & NUL & NUL & NUL,
       20 => "VAUXN[4]" & NUL & NUL & NUL & NUL,
       21 => "VAUXN[5]" & NUL & NUL & NUL & NUL,
       22 => "VAUXN[6]" & NUL & NUL & NUL & NUL,
       23 => "VAUXN[7]" & NUL & NUL & NUL & NUL,
       24 => "VAUXN[8]" & NUL & NUL & NUL & NUL,
       25 => "VAUXN[9]" & NUL & NUL & NUL & NUL,
       26 => "VAUXN[10]" & NUL & NUL & NUL,
       27 => "VAUXN[11]" & NUL & NUL & NUL,
       28 => "VAUXN[12]" & NUL & NUL & NUL,
       29 => "VAUXN[13]" & NUL & NUL & NUL,
       30 => "VAUXN[14]" & NUL & NUL & NUL,
       31 => "VAUXN[15]" & NUL & NUL & NUL
           );

  begin
 
    file_open(open_status, in_file, SIM_MONITOR_FILE, read_mode);
    if (open_status /= open_ok) then
         assert false report
         "*** Warning: The analog data file for SYSMON was not found. Use the SIM_MONITOR_FILE generic to specify the input analog data file name or use default name: design.txt. "
         severity warning; 
         sim_file_flag1 := '1';
         sim_file_flag <= '1';
    end if;

   if ( sim_file_flag1 = '0') then
      while (not endfile(in_file) and (not HeaderFound)) loop
        commentline := false;
        readline(in_file, in_buf);
        file_line := file_line + 1;
        if (in_buf'LENGTH > 0 ) then
          skip_blanks(in_buf);
        
          low := in_buf'low;
          low2 := in_buf'low+2;
           if ( low2 <= in_buf'high) then
              if ((in_buf(in_buf'low to in_buf'low+1) = "//" ) or 
                  (in_buf(in_buf'low to in_buf'low+1) = "--" )) then
                 commentline := true;
               end if;

               while((in_buf'LENGTH > 0 ) and (not commentline)) loop
                   HeaderFound := true;
                   get_token(in_buf, str_token_in, token_len);
                   str_token_tmp := To_Upper(str_token_in);
                   if (str_token_tmp(1 to 4) = "TEMP") then
                      str_token := "TEMP" & NUL & NUL & NUL & NUL & NUL 
                                                  & NUL & NUL & NUL;
                   else
                      str_token := str_token_tmp;
                   end if;

                   if(token_len > 0) then
                    HeaderCount := HeaderCount + 1;
                   end if;
       
                   if (HeaderCount=1) then
                      if (str_token(1 to token_len) /= "TIME") then
                         infile_format;
                         assert false report
                  " Analog Data File Error : No TIME label is found in the input file for SYSMON."
                         severity failure;
                      end if;
                   elsif (HeaderCount > 1) then
                      inchannel := -1;
                      for i in 0 to 31 loop
                          if (chanlist_p(i) = str_token) then
                             inchannel := i;
                             index_to_channel(headercount) := i;
                           end if;
                       end loop;
                       if (inchannel = -1) then
                         for i in 0 to 31 loop
                           if ( chanlist_n(i) = str_token) then
                             inchannel := i;
                             index_to_channel(headercount) := i+32;
                           end if;
                         end loop;
                       end if;
                       if (inchannel = -1 and token_len >0) then
                           infile_format;
                           assert false report
                    "Analog Data File Error : No valid channel name in the input file for SYSMON. Valid names: TEMP VCCINT VCCAUX VP VN VAUXP[1] VAUXN[1] ....."
                           severity failure;
                       end if;
                  else
                       infile_format;
                       assert false report
                    "Analog Data File Error : NOT found header in the input file for SYSMON. The header is: TIME TEMP VCCINT VCCAUX VP VN VAUXP[1] VAUXN[1] ..."
                           severity failure;
                  end if;

           str_token_in := NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL &
                           NUL & NUL & NUL & NUL;
        end loop;
        end if;
       end if;
      end loop;

-----  Read Values
      while (not endfile(in_file)) loop
        commentline := false;
        readline(in_file, in_buf);
        file_line := file_line + 1;
        if (in_buf'length > 0) then
           skip_blanks(in_buf);
        
           if (in_buf'low < in_buf'high) then
             if((in_buf(in_buf'low to in_buf'low+1) = "//" ) or 
                    (in_buf(in_buf'low to in_buf'low+1) = "--" )) then
              commentline := true;
             end if;
 
          if(not commentline and in_buf'length > 0) then
            for i IN 1 to HeaderCount Loop
              if ( i=1) then
                 read(in_buf, time_val, read_ok);
                if (not read_ok) then
                  infile_format;
                  assert false report
                   " Analog Data File Error : The time value should be integer in ns scale and the last time value needs bigger than simulation time."
                  severity failure;
                 end if;
                 next_time := time_val * 1 ns; 
              else
               read(in_buf, a1, read_ok);
               if (not read_ok) then
                  assert false report
                    "*** Analog Data File Error: The data type should be REAL, e.g. 3.0  0.0  -0.5 "
                  severity failure;
               end if;
               inchannel:= index_to_channel(i);
              if (inchannel >= 32) then
                valsn(inchannel-32):=a1;
              else
                vals(inchannel):=a1;
              end if;
            end if;
           end loop;  -- i loop

           if ( now < next_time) then
               wait for ( next_time - now ); 
           end if;
           for i in 0 to 31 loop
                 chan_val_tmp(i) <= vals(i);
                 chan_valn_tmp(i) <= valsn(i);
                 analog_in_diff(i) <= vals(i)-valsn(i);
                 analog_in_uni(i) <= vals(i);
           end loop;
        end if;
        end if;
       end if;
      end loop;  -- while loop
      file_close(in_file);
    end if;
    wait;
  end process READFILE_P;



end SYSMON_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  
-- /___/   /\     Filename : USR_ACCESS_VIRTEX5.vhd
-- \   \  /  \    Timestamp : Thu Apr  8 10:57:05 PDT 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL USR_ACCESS_VIRTEX5 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity USR_ACCESS_VIRTEX5 is
  port(
    CFGCLK      : out std_ulogic;
    DATA	: out std_logic_vector(31 downto 0);
    DATAVALID	: out std_ulogic
    );

end USR_ACCESS_VIRTEX5;

architecture USR_ACCESS_VIRTEX5_V of USR_ACCESS_VIRTEX5 is

begin
end USR_ACCESS_VIRTEX5_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Boundary Scan Logic Control Circuit for SPARTAN3A
-- /___/   /\     Filename : BSCAN_SPARTAN3A.vhd
-- \   \  /  \    Timestamp : Tue Jul  5 16:58:04 PDT 2005
--  \___\/\___\
--
-- Revision:
--    07/05/05 - Initial version.
--    01/24/06 - CR 224623, added TCK and TMS ports
-- End Revision

----- CELL BSCAN_SPARTAN3A -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.vcomponents.all;

entity BSCAN_SPARTAN3A is

  port(
      CAPTURE : out std_ulogic := 'H';
      DRCK1   : out std_ulogic := 'L';
      DRCK2   : out std_ulogic := 'L';
      RESET   : out std_ulogic := 'L';
      SEL1    : out std_ulogic := 'L';
      SEL2    : out std_ulogic := 'L';
      SHIFT   : out std_ulogic := 'L';
      TCK     : out std_ulogic := 'L';
      TDI     : out std_ulogic := 'L';
      TMS     : out std_ulogic := 'L';
      UPDATE  : out std_ulogic := 'L';

      TDO1 : in std_ulogic := 'X';
      TDO2 : in std_ulogic := 'X'
      );
end BSCAN_SPARTAN3A;


-- architecture body  

architecture BSCAN_SPARTAN3A_V of BSCAN_SPARTAN3A is



  signal        TDO1_dly         : std_ulogic := '0';
  signal        TDO2_dly         : std_ulogic := '0';

begin

  TDO1_dly       	 <= TDO1           	after 0 ps;
  TDO2_dly       	 <= TDO2           	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------


-- synopsys translate_off

      CAPTURE <= JTAG_CAPTURE_GLBL ;

--####################################################################
--#####                        jtag_select                         ###
--####################################################################
      DRCK1  <= ((JTAG_SEL1_GLBL and not JTAG_SHIFT_GLBL and not JTAG_CAPTURE_GLBL)
                                     or
                 (JTAG_SEL1_GLBL and JTAG_SHIFT_GLBL and JTAG_TCK_GLBL)
                                     or
                 (JTAG_SEL1_GLBL and JTAG_CAPTURE_GLBL and JTAG_TCK_GLBL));
      DRCK2  <= ((JTAG_SEL2_GLBL and not JTAG_SHIFT_GLBL and not JTAG_CAPTURE_GLBL)
                                     or
                 (JTAG_SEL2_GLBL and JTAG_SHIFT_GLBL and JTAG_TCK_GLBL)
                                     or
                 (JTAG_SEL2_GLBL and JTAG_CAPTURE_GLBL and JTAG_TCK_GLBL));
      RESET  <= JTAG_RESET_GLBL ;
      SEL1   <= JTAG_SEL1_GLBL;
      SEL2   <= JTAG_SEL2_GLBL;
      SHIFT  <= JTAG_SHIFT_GLBL;
      TCK    <= JTAG_TCK_GLBL;
      TDI    <= JTAG_TDI_GLBL;
      TMS    <= JTAG_TMS_GLBL;
      UPDATE <= JTAG_UPDATE_GLBL;

      JTAG_USER_TDO1_GLBL <=  TDO1;
      JTAG_USER_TDO2_GLBL <=  TDO2;

-- synopsys translate_on


end BSCAN_SPARTAN3A_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Register State Capture for Bitstream Readback for SPARTAN3
-- /___/   /\     Filename : CAPTURE_SPARTAN3A.vhd
-- \   \  /  \    Timestamp : Tue Jul  5 15:01:35 PDT 2005
--  \___\/\___\
--
-- Revision:
--    07/05/05 - Initial version.

----- CELL CAPTURE_SPARTAN3A -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CAPTURE_SPARTAN3A is
  generic(
    ONESHOT : boolean := true
    );  
  port(
    CAP : in std_ulogic;
    CLK : in std_ulogic
    );
end CAPTURE_SPARTAN3A;

architecture CAPTURE_SPARTAN3A_V of CAPTURE_SPARTAN3A is
begin
end CAPTURE_SPARTAN3A_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                       Device DNA Data Access Port
-- /___/   /\     Filename : DNA_PORT.vhd
-- \   \  /  \    Timestamp : Mon Oct 10 15:21:52 PDT 2005
--  \___\/\___\
--
-- Revision:
--    10/10/05 - Initial version
--    06/04/08 - CR 472697 -- added check for SIM_DNA_VALUE
-- End Revision

----- CELL DNA_PORT -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library unisim;
use unisim.vpkg.all;

entity DNA_PORT is
  generic(

      SIM_DNA_VALUE : bit_vector := X"000000000000000"
      );

  port(
    DOUT  : out std_ulogic;

    CLK   : in std_ulogic;
    DIN   : in std_ulogic;
    READ  : in std_ulogic;
    SHIFT : in std_ulogic
    );

end DNA_PORT;

architecture DNA_PORT_V of DNA_PORT is


-----------------------------------------------------------
-----------------------------------------------------------
  function eval_init (
                         sim_dna_val : in  bit_vector;
                         msb         : in integer
              ) return std_logic_vector is
  variable ret_sim_dna_val : std_logic_vector (msb downto 0);
  variable tmp_sim_dna_val : std_logic_vector ((sim_dna_val'length-1) downto 0);
  begin
    if (sim_dna_val'length >= msb ) then
--        ret_sim_dna_val(msb downto 0)  := To_stdLogicVector(sim_dna_val((sim_dna_val'length-msb-1) to (sim_dna_val'length-1)));
        tmp_sim_dna_val((sim_dna_val'length-1) downto 0) := To_stdLogicVector(sim_dna_val);
        ret_sim_dna_val(msb downto 0) := tmp_sim_dna_val(msb downto 0);

    else
        ret_sim_dna_val := (others => '0');
        ret_sim_dna_val((sim_dna_val'length-1) downto 0) := To_stdLogicVector(sim_dna_val);
    end if;

    return ret_sim_dna_val(msb downto 0);
  end;
-----------------------------------------------------------
-----------------------------------------------------------

  constant MAX_DNA_BITS     : integer := 57;
  constant MSB_DNA_BITS     : integer := (MAX_DNA_BITS - 1);

  constant SYNC_PATH_DELAY      : time := 100 ps;

  signal        CLK_ipd          : std_ulogic := 'X';
  signal        DIN_ipd          : std_ulogic := 'X';
  signal        GSR              : std_ulogic := '0';
  signal        GSR_ipd          : std_ulogic := '0';
  signal        READ_ipd         : std_ulogic := 'X';
  signal        SHIFT_ipd        : std_ulogic := 'X';

  signal        CLK_dly          : std_ulogic := 'X';
  signal        DIN_dly          : std_ulogic := 'X';
  signal        GSR_dly          : std_ulogic := '0';
  signal        READ_dly         : std_ulogic := 'X';
  signal        SHIFT_dly        : std_ulogic := 'X';

  signal        DOUT_zd          : std_ulogic := 'X';

  signal        dna_val          : std_logic_vector(MSB_DNA_BITS downto 0) := eval_init(SIM_DNA_VALUE, MSB_DNA_BITS);

  signal	Violation        : std_ulogic := '0';

begin
  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  CLK_dly        	 <= CLK            	after 0 ps;
  DIN_dly        	 <= DIN            	after 0 ps;
  READ_dly       	 <= READ           	after 0 ps;
  SHIFT_dly      	 <= SHIFT          	after 0 ps;
  GSR_dly        	 <= GSR            	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                        Initialization                      ###
--####################################################################
  prcs_init:process
  begin
    if(dna_val(MSB_DNA_BITS downto (MSB_DNA_BITS -1)) /= "10") then
       assert false
       report "Attribute Syntax Warning: SIM_DNA_VALUE bits [56:55] on component DNA_PORT do not match the expected value ""10"". The simulation will not exactly model the hardware behavior, as detailed in the Spartan-3 Generation FPGA User Guide." 
       severity warning;
    end if;
    wait;
  end process prcs_init;

--####################################################################
--#####                            READ                            ###
--####################################################################
  prcs_read:process(CLK_dly, GSR_dly, READ_dly, SHIFT_dly)
  begin
     if(GSR_dly = '1') then
        dna_val(0) <= '0';
     elsif(GSR_dly = '0') then
        if(rising_edge(CLK_dly)) then
           if(READ_dly = '1') then
              dna_val(MSB_DNA_BITS downto 0) <= eval_init(SIM_DNA_VALUE, MSB_DNA_BITS);
              dna_val(0) <= '1';
           elsif(READ_dly = '0') then
               if(SHIFT_dly = '1') then
                  dna_val <= DIN_dly & dna_val(MSB_DNA_BITS downto 1);
               end if; -- SHIFT_dly = '1'   
           end if;  -- READ_dly = '1'  
        end if; -- rising_edge(CLK_dly)   
     end if; -- GSR_dly = '1'   
  end process prcs_read;

--####################################################################
--#####             Update Zero Delay Output                     #####
--####################################################################

DOUT_zd <= dna_val(0);



--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(DOUT_zd)
  begin
      DOUT <= DOUT_zd after SYNC_PATH_DELAY;
  end process prcs_output;

end DNA_PORT_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                       Dynamically Adjustable Input Delay Buffer
-- /___/   /\     Filename : IBUF_DLY_ADJ.vhd
-- \   \  /  \    Timestamp : Tue Apr 19 08:18:20 PST 2005
--  \___\/\___\
--
-- Revision:
--    04/19/05 - Initial version.
--    06/30/06 - CR 233887 -- Corrected generic ordering
--    08/08/07 - CR 439320 -- Simprim fix -- Added attributes SIM_DELAY0, ... SIM_DELAY16 to fix timing issues
--    09/11/07 - CR 447604 -- When S[2:0]=0, it should correlate to 1 tap
-- End Revision


----- CELL IBUF_DLY_ADJ -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;


library unisim;
use unisim.vpkg.all;

entity IBUF_DLY_ADJ is

  generic(

      DELAY_OFFSET : string := "OFF";
      IOSTANDARD : string := "DEFAULT"
      );

  port(
      O      : out std_ulogic;

      I      : in  std_ulogic;
      S      : in  std_logic_vector (2 downto 0)
      );

end IBUF_DLY_ADJ;

architecture IBUF_DLY_ADJ_V OF IBUF_DLY_ADJ is

  constant SIM_TAPDELAY_VALUE : integer := 200;
  constant SPECTRUM_OFFSET_DELAY : time := 1600 ps;

  ---------------------------------------------------------
  -- Function  str_2_int converts string to integer
  ---------------------------------------------------------
  function str_2_int(str: in string ) return integer is
  variable int : integer;
  variable val : integer := 0;
  variable neg_flg   : boolean := false;
  variable is_it_int : boolean := true;
  begin
    int := 0;
    val := 0;
    is_it_int := true;
    neg_flg   := false;

    for i in  1 to str'length loop
      case str(i) is
         when  '-'
           =>
             if(i = 1) then
                neg_flg := true;
                val := -1;
             end if;
         when  '1'
           =>  val := 1;
         when  '2'
           =>   val := 2;
         when  '3'
           =>   val := 3;
         when  '4'
           =>   val := 4;
         when  '5'
           =>   val := 5;
         when  '6'
           =>   val := 6;
         when  '7'
           =>   val := 7;
         when  '8'
           =>   val := 8;
         when  '9'
           =>   val := 9;
         when  '0'
           =>   val := 0;
         when others
           => is_it_int := false;
        end case;
        if(val /= -1) then
          int := int *10  + val;
        end if;
        val := 0;
    end loop;
    if(neg_flg) then
      int := int * (-1);
    end if;

    if(NOT is_it_int) then
      int := -9999;
    end if;
    return int;
  end;
-----------------------------------------------------------

  constant      MAX_S		: integer := 3;
  constant      MAX_TAP		: integer := 7;
  constant      MIN_TAP		: integer := 0;

  constant      MSB_S		: integer := MAX_S -1;
  constant      LSB_S		: integer := 0;

  constant	SYNC_PATH_DELAY	: time := 0 ps;


  signal	O_zd		: std_ulogic := 'X';
  signal	O_viol		: std_ulogic := 'X';

  signal	I_ipd		: std_ulogic := 'X';
  signal        S_ipd           : std_logic_vector(MSB_S downto LSB_S);

  signal	INITIAL_DELAY	: time  := 0 ps;
  signal	DELAY   	: time  := 0 ps;

begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  I_ipd          	 <= I              	after 0 ps;
  S_ipd          	 <= S              	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process
  variable TapCount_var   : integer := 0;
  variable IsTapDelay_var : boolean := true; 
  variable IsTapFixed_var : boolean := false; 
  variable IsTapDefault_var : boolean := false; 
  begin
     if((DELAY_OFFSET /= "ON") and (DELAY_OFFSET /= "on") and 
        (DELAY_OFFSET /= "OFF") and (DELAY_OFFSET /= "off")) then
           GenericValueCheckMessage
           (  HeaderMsg  => " Attribute Syntax Warning ",
              GenericName => " DELAY_OFFSET ",
              EntityName => "/IBUF_DLY_ADJ",
              GenericValue => DELAY_OFFSET,
              Unit => "",
              ExpectedValueMsg => " The Legal values for this attribute are ",
              ExpectedGenericValue => " ON or  OFF ",
              TailMsg => "",
              MsgSeverity => failure 
           );
     end if; 

     if((DELAY_OFFSET = "ON") or (DELAY_OFFSET = "on")) then  
-- CR 447604
--        INITIAL_DELAY <= SPECTRUM_OFFSET_DELAY;
        INITIAL_DELAY <= SPECTRUM_OFFSET_DELAY + (SIM_TAPDELAY_VALUE * 1 ps);
     else
--        INITIAL_DELAY <=  0 ps;
        INITIAL_DELAY <=  SIM_TAPDELAY_VALUE * 1 ps;
     end if;
     wait;
  end process prcs_init;
--####################################################################
--#####                  CALCULATE DELAY                         #####
--####################################################################
  prcs_s:process(S_ipd)
  variable TapCount_var : integer := 0;
  variable FIRST_TIME   : boolean :=true;
  variable BaseTime_var : time    := 1 ps ;
  variable delay_var    : time    := 0 ps ;
  variable S_int_var    : integer := 0;
  begin
     S_int_var := SLV_TO_INT(S_ipd);

     if((S_int_var >= MIN_TAP) and (S_int_var <= MAX_TAP)) then
         Delay        <= S_int_var * SIM_TAPDELAY_VALUE * BaseTime_var + INITIAL_DELAY;
     end if;
  end process prcs_s;

--####################################################################
--#####                      DELAY INPUT                         #####
--####################################################################
  prcs_i:process(I_ipd)
  begin
      O_zd <= transport I_ipd after delay; 
  end process prcs_i;


--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(O_zd)
  begin
      O <= O_zd after SYNC_PATH_DELAY;
  end process prcs_output;
--####################################################################


end IBUF_DLY_ADJ_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                       Dynamically Adjustable Differential Input Delay Buffer
-- /___/   /\     Filename :    IBUFDS_DLY_ADJ.vhd
-- \   \  /  \    Timestamp :   Tue Apr 19 08:18:20 PST 2005
--  \___\/\___\
--
-- Revision:
--    04/19/05 - Initial version.
--    06/30/06 - CR 233887 -- Corrected generic ordering
--    08/08/07 - CR 439320 -- Simprim fix -- Added attributes SIM_DELAY0, ... SIM_DELAY16 to fix timing issues
--    09/11/07 - CR 447604 -- When S[2:0]=0, it should correlate to 1 tap
-- End Revision
----- CELL IBUFDS_DLY_ADJ -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;


library unisim;
use unisim.vpkg.all;

entity IBUFDS_DLY_ADJ is

  generic(

      DELAY_OFFSET : string := "OFF";
      DIFF_TERM   : boolean :=  FALSE;
      IOSTANDARD : string := "DEFAULT"
      );

  port(
      O      : out std_ulogic;

      I      : in  std_ulogic;
      IB     : in  std_ulogic;
      S      : in  std_logic_vector (2 downto 0)
      );

end IBUFDS_DLY_ADJ;

architecture IBUFDS_DLY_ADJ_V OF IBUFDS_DLY_ADJ is

  constant SIM_TAPDELAY_VALUE : integer := 200;
  constant SPECTRUM_OFFSET_DELAY : time := 1600 ps;

  ---------------------------------------------------------
  -- Function  str_2_int converts string to integer
  ---------------------------------------------------------
  function str_2_int(str: in string ) return integer is
  variable int : integer;
  variable val : integer := 0;
  variable neg_flg   : boolean := false;
  variable is_it_int : boolean := true;
  begin
    int := 0;
    val := 0;
    is_it_int := true;
    neg_flg   := false;

    for i in  1 to str'length loop
      case str(i) is
         when  '-'
           =>
             if(i = 1) then
                neg_flg := true;
                val := -1;
             end if;
         when  '1'
           =>  val := 1;
         when  '2'
           =>   val := 2;
         when  '3'
           =>   val := 3;
         when  '4'
           =>   val := 4;
         when  '5'
           =>   val := 5;
         when  '6'
           =>   val := 6;
         when  '7'
           =>   val := 7;
         when  '8'
           =>   val := 8;
         when  '9'
           =>   val := 9;
         when  '0'
           =>   val := 0;
         when others
           => is_it_int := false;
        end case;
        if(val /= -1) then
          int := int *10  + val;
        end if;
        val := 0;
    end loop;
    if(neg_flg) then
      int := int * (-1);
    end if;

    if(NOT is_it_int) then
      int := -9999;
    end if;
    return int;
  end;
-----------------------------------------------------------

  
  constant      MAX_S		: integer := 3;
  constant      MAX_TAP		: integer := 7;
  constant      MIN_TAP		: integer := 0;

  constant      MSB_S		: integer := MAX_S -1;
  constant      LSB_S		: integer := 0;

  constant	SYNC_PATH_DELAY	: time := 0 ps;


  signal	O_zd		: std_ulogic := 'X';
  signal	O_viol		: std_ulogic := 'X';

  signal	I_int		: std_ulogic := 'X';

  signal	I_ipd		: std_ulogic := 'X';
  signal	IB_ipd		: std_ulogic := 'X';
  signal        S_ipd           : std_logic_vector(MSB_S downto LSB_S);

  signal	INITIAL_DELAY	: time  := 0 ps;
  signal	DELAY   	: time  := 0 ps;

begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  I_ipd          	 <= I              	after 0 ps;
  IB_ipd         	 <= IB             	after 0 ps;
  S_ipd          	 <= S              	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process
  variable TapCount_var   : integer := 0;
  variable IsTapDelay_var : boolean := true; 
  variable IsTapFixed_var : boolean := false; 
  variable IsTapDefault_var : boolean := false; 
  begin
     if((DELAY_OFFSET /= "ON") and (DELAY_OFFSET /= "on") and 
        (DELAY_OFFSET /= "OFF") and (DELAY_OFFSET /= "off")) then
           GenericValueCheckMessage
           (  HeaderMsg  => " Attribute Syntax Warning ",
              GenericName => " DELAY_OFFSET ",
              EntityName => "/IBUFDS_DLY_ADJ",
              GenericValue => DELAY_OFFSET,
              Unit => "",
              ExpectedValueMsg => " The Legal values for this attribute are ",
              ExpectedGenericValue => " ON or  OFF ",
              TailMsg => "",
              MsgSeverity => failure 
           );
     end if; 

     if((DELAY_OFFSET = "ON") or (DELAY_OFFSET = "on")) then  
-- CR 447604
--        INITIAL_DELAY <= SPECTRUM_OFFSET_DELAY;
        INITIAL_DELAY <= SPECTRUM_OFFSET_DELAY + (SIM_TAPDELAY_VALUE * 1 ps);
     else
--        INITIAL_DELAY <= 0 ps;
        INITIAL_DELAY <=  SIM_TAPDELAY_VALUE * 1 ps;
     end if;
     wait;
  end process prcs_init;
--####################################################################
--#####                  CALCULATE DELAY                         #####
--####################################################################
  prcs_s:process(S_ipd)
  variable TapCount_var : integer := 0;
  variable FIRST_TIME   : boolean :=true;
  variable BaseTime_var : time    := 1 ps ;
  variable delay_var    : time    := 0 ps ;
  variable S_int_var    : integer := 0;
  begin
     S_int_var := SLV_TO_INT(S_ipd);

     if((S_int_var >= MIN_TAP) and (S_int_var <= MAX_TAP)) then
         Delay        <= S_int_var * SIM_TAPDELAY_VALUE * BaseTime_var + INITIAL_DELAY;
     end if;
  end process prcs_s;

  VitalBehavior : process (I_ipd, IB_ipd)
  begin
    if ((I_ipd = '1') and (IB_ipd = '0')) then
      I_int <= TO_X01(I_ipd);
    elsif ((I_ipd = '0') and (IB_ipd = '1')) then
      I_int <= TO_X01(I_ipd);
    end if;
  end process;

--####################################################################
--#####                      DELAY INPUT                         #####
--####################################################################
  prcs_i:process(I_int)
  begin
      O_zd <= transport I_int after delay; 
  end process prcs_i;


--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(O_zd)
  begin
      O <= O_zd after SYNC_PATH_DELAY;
  end process prcs_output;
--####################################################################


end IBUFDS_DLY_ADJ_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Internal Configuration Access Port for Spartan3A
-- /___/   /\     Filename : ICAP_SPARTAN3A.vhd
-- \   \  /  \    Timestamp : Wed Jul  6 18:07:07 PDT 2005
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL ICAP_SPARTAN3A -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

entity ICAP_SPARTAN3A is

  port(
    BUSY : out std_ulogic;
    O    : out std_logic_vector(7 downto 0);

    CE    : in std_ulogic;
    CLK   : in std_ulogic;
    I     : in std_logic_vector(7 downto 0);
    WRITE : in std_ulogic
    );

end ICAP_SPARTAN3A;

architecture ICAP_SPARTAN3A_V of ICAP_SPARTAN3A is

begin
end ICAP_SPARTAN3A_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Jtag TAP contorller for SPARTAN3A 
--  /   /         
-- /___/   /\     Filename : JTAG_SIM_SPARTAN3A.vhd
-- \   \  /  \    Timestamp : Mon Aug  8 18:09:16 PDT 2005
--  \___\/\___\
--
-- Revision:
--    08/08/05 - Initial version.
-- End Revision

----- CELL JTAG_SIM_SPARTAN3A  -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;

library unisim;
use unisim.vpkg.all;
use unisim.Vcomponents.all;



entity JTAG_SIM_SPARTAN3A is

  generic(
      PART_NAME : string := "3S200A"
      );

  port(
      TDO	: out std_ulogic;

      TCK	: in  std_ulogic;
      TDI	: in  std_ulogic;
      TMS	: in  std_ulogic
    );

end JTAG_SIM_SPARTAN3A;

architecture JTAG_SIM_SPARTAN3A_V OF JTAG_SIM_SPARTAN3A is


  TYPE JtagTapState is (TestLogicReset, RunTestIdle,SelectDRScan, CaptureDR,
                        ShiftDR, Exit1DR, PauseDR, Exit2DR, UPdateDR,
                        SelectIRScan, CaptureIR, ShiftIR, Exit1IR, PauseIR,
                        Exit2IR, UPdateIR);


-------------------------------------------------------------------------------
-----------------  Virtex4 Specific Constants ---------------------------------
-------------------------------------------------------------------------------

  TYPE JtagInstructionType is (UNKNOWN, IR_CAPTURE, BYPASS, IDCODE, USER1, USER2, USER3, USER4);                  

  TYPE PartType            is (XC3S200A, XC3S400A, XC3S700A, XC3S1400A, XC3S1800A);                  

  constant IRLength             : integer := 6;
  constant IDLength             : integer := 32;

  constant IR_CAPTURE_VAL	: std_logic_vector ((IRLength -1) downto 0) := "010001";

  constant BYPASS_INSTR		: std_logic_vector ((IRLength -1) downto 0) := "111111";
  constant IDCODE_INSTR		: std_logic_vector ((IRLength -1) downto 0) := "001001";
  constant USER1_INSTR		: std_logic_vector ((IRLength -1) downto 0) := "000010";
  constant USER2_INSTR		: std_logic_vector ((IRLength -1) downto 0) := "000011";
  constant USER3_INSTR		: std_logic_vector ((IRLength -1) downto 0) := "XXXXXX";
  constant USER4_INSTR		: std_logic_vector ((IRLength -1) downto 0) := "ZXXXXX";

--------------------------------------------------------

  constant DELAY_SIG     : time := 1 ps;

  constant Xon : boolean := true;
  constant MsgOn : boolean := true;

  signal ticd_TCK     : VitalDelayType := 0.0 ns;

  signal tisd_TDI_TCK : VitalDelayType := 0.0 ns;
  signal tisd_TMS_TCK : VitalDelayType := 0.0 ns;

  signal tsetup_TMS_TCK_posedge_posedge : VitalDelayType := 1.0 ns;
  signal tsetup_TMS_TCK_negedge_posedge : VitalDelayType := 1.0 ns;

  signal tsetup_TDI_TCK_posedge_posedge : VitalDelayType := 1.0 ns;
  signal tsetup_TDI_TCK_negedge_posedge : VitalDelayType := 1.0 ns;

  signal thold_TMS_TCK_posedge_posedge : VitalDelayType := 2.0 ns;
  signal thold_TMS_TCK_negedge_posedge : VitalDelayType := 2.0 ns;

  signal thold_TDI_TCK_posedge_posedge : VitalDelayType := 2.0 ns;
  signal thold_TDI_TCK_negedge_posedge : VitalDelayType := 2.0 ns;

  signal tpd_TCK_TDO : VitalDelayType01 := (6.0 ns, 6.0 ns);

  signal CurrentState    : JtagTapState := TestLogicReset;
  signal JtagInstruction : JtagInstructionType := IDCODE;

  signal TCK_ipd		: std_ulogic := 'X';
  signal TDI_ipd		: std_ulogic := 'X';
  signal TMS_ipd		: std_ulogic := 'X';
  signal TRST_ipd		: std_ulogic := '0';


  signal TCK_dly		: std_ulogic := 'X';
  signal TDI_dly		: std_ulogic := 'X';
  signal TMS_dly		: std_ulogic := 'X';
  signal TRST_dly		: std_ulogic := '0';

  signal TDO_zd			: std_ulogic := 'X';
  signal TDO_viol		: std_ulogic := 'X';

-----------     signal declaration    -------------------

  signal CaptureDR_sig          : std_ulogic := '0';
  signal RESET_sig              : std_ulogic := '0';
  signal ShiftDR_sig            : std_ulogic := '0';
  signal UpdateDR_sig           : std_ulogic := '0';

  signal ClkIR_active           : std_ulogic := '0';

  signal ClkIR_sig		: std_ulogic := '0';
  signal ClkID_sig		: std_ulogic := '0';
  signal ShiftIR_sig		: std_ulogic := 'X';
  signal UpdateIR_sig		: std_ulogic := 'X';
  signal ClkUpdateIR_sig	: std_ulogic := '0';
  signal IRcontent_sig		: std_logic_vector ((IRLength -1) downto 0) := (others => 'X');
  signal IDCODEval_sig		: std_logic_vector ((IDLength -1) downto 0) := (others => 'X');

  signal BypassReg		: std_ulogic := '0';
  signal BYPASS_sig		: std_ulogic := '0';
  signal IDCODE_sig		: std_ulogic := '0';
  signal USER1_sig		: std_ulogic := '0';
  signal USER2_sig		: std_ulogic := '0';
  signal USER3_sig		: std_ulogic := '0';
  signal USER4_sig		: std_ulogic := '0';

  signal TDO_latch              : std_ulogic := 'Z';

  signal Tlrst_sig              : std_ulogic := '1';
  signal TlrstN_sig              : std_ulogic := '1';

  signal IRegLastBit_sig        : std_ulogic := '0';
  signal IDregLastBit_sig       : std_ulogic := '0';

begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  TCK_dly        	 <= TCK            	after 0 ps;
  TDI_dly        	 <= TDI            	after 0 ps;
  TMS_dly        	 <= TMS            	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                     Initialize                           #####
--####################################################################
  prcs_init:process
  variable PartName_var        : PartType;
  variable IDCODE_str          : bit_vector ((IDLength -1) downto 0) ;
  begin
     if((PART_NAME   = "3S200A") or (PART_NAME = "3s200a")) then
        PartName_var := XC3S200A;
        IDCODE_str   := X"02218093";
        IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
     elsif((PART_NAME   = "3S400A") or (PART_NAME = "3s400a")) then
        PartName_var := XC3S400A;
        IDCODE_str   := X"02220093";
        IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
     elsif((PART_NAME   = "3S700A") or (PART_NAME = "3s700a")) then
        PartName_var := XC3S700A;
        IDCODE_str   := X"02228093";
        IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
     elsif((PART_NAME   = "3S1400A") or (PART_NAME = "3s1400a")) then
        PartName_var := XC3S1400A;
        IDCODE_str   := X"02230093";
        IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
     elsif((PART_NAME   = "3S1800A") or (PART_NAME = "3s1800a")) then
        PartName_var := XC3S1800A;
        IDCODE_str   := X"0224c093";
        IDCODEval_sig <= To_StdLogicVector(IDCODE_str);
     else
        assert false
        report "Attribute Syntax Error: The allowed values for PART_NAME are 3S200A, 3S400A, 3S700A, 3S1400A or 3S1800A"
        severity Failure;
     end if;

     wait;

  end process prcs_init;
--####################################################################
--#####                     JtagTapSM                            #####
--####################################################################
  prcs_JtagTapSM:process(TCK_dly, TRST_dly)
  begin

     if(TRST_dly = '1') then
         CurrentState <= TestLogicReset; 
     elsif(TRST_dly = '0') then
        if(rising_edge(TCK_dly)) then
           case CurrentState is
              -------------------------------
              ----  Reset path ---------------
              -------------------------------
              when TestLogicReset =>
                 if(TMS_dly = '0') then 
                    CurrentState <= RunTestIdle;
                 end if;
              when RunTestIdle => 
                 if(TMS_dly = '1') then 
                    CurrentState <= SelectDRScan;
                 end if;
              -------------------------------
              ------  DR path ---------------
              -------------------------------
              when SelectDRScan => 
                 if(TMS_dly = '0') then 
                    CurrentState <= CaptureDR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= SelectIRScan;
                 end if;
              when CaptureDR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= ShiftDR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= Exit1DR;
                 end if;
              when ShiftDR => 
                 if(TMS_dly = '1') then 
                    CurrentState <= Exit1DR;
                 end if;
              
                 if(IRcontent_sig = BYPASS_INSTR) then
                    BypassReg <= TDI_dly;
                 end if;

              when Exit1DR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= PauseDR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= UpdateDR;
                 end if;
              when PauseDR => 
                 if(TMS_dly = '1') then 
                    CurrentState <= Exit2DR;
                 end if;
              when Exit2DR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= ShiftDR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= UpdateDR;
                 end if;
              when UpdateDR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= RunTestIdle;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= SelectDRScan;
                 end if;
              -------------------------------
              ------  IR path ---------------
              -------------------------------
              when SelectIRScan => 
                 if(TMS_dly = '0') then 
                    CurrentState <= CaptureIR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= TestLogicReset;
                 end if;
              when CaptureIR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= ShiftIR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= Exit1IR;
                 end if;
              when ShiftIR => 
                 if(TMS_dly = '1') then 
                    CurrentState <= Exit1IR;
                 end if;
              when Exit1IR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= PauseIR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= UpdateIR;
                 end if;
              when PauseIR => 
                 if(TMS_dly = '1') then 
                    CurrentState <= Exit2IR;
                 end if;
              when Exit2IR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= ShiftIR;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= UpdateIR;
                 end if;
              when UpdateIR => 
                 if(TMS_dly = '0') then 
                    CurrentState <= RunTestIdle;
                 elsif(TMS_dly = '1') then 
                    CurrentState <= SelectDRScan;
                 end if;
           end case;
        end if;
     end if;
  end process  prcs_JtagTapSM;

--####################################################################
--#####                     CurrentState                         #####
--####################################################################

  prcs_CurrentState:process(TCK_dly, CurrentState, TRST_dly)
  begin

     ClkIR_sig <= '1';

     if(TRST_dly = '1') then
         CaptureDR_sig <= '0';
         ShiftDR_sig   <= '0';
         UpdateDR_sig  <= '0';
         ShiftIR_sig   <= '0';
         UpdateIR_sig  <= '0';
     elsif(TRST_dly = '0') then

         case CurrentState is

            when TestLogicReset =>
                          Tlrst_sig     <= '1' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;

            when CaptureDR =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '1' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;

            when ShiftDR  =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '1' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;
 
            when UpdateDR =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '1' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;

            when CaptureIR  =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;
                          ClkIR_sig     <= TCK_dly;

 
            when ShiftIR  =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '1' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;
                          ClkIR_sig     <= TCK_dly;

            when UpdateIR =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '1' after DELAY_SIG;

            when others   =>
                          Tlrst_sig     <= '0' after DELAY_SIG;
                          CaptureDR_sig <= '0' after DELAY_SIG;
                          ShiftDR_sig   <= '0' after DELAY_SIG;
                          UpdateDR_sig  <= '0' after DELAY_SIG;
                          ShiftIR_sig   <= '0' after DELAY_SIG;
                          UpdateIR_sig  <= '0' after DELAY_SIG;
         end case;
     end if;
 
  end process  prcs_CurrentState;

------------- ?? TCK  NEGATIVE EDGE activities ----------

  prcs_ClkIR:process(TCK_dly)
  begin
--     ClkIR_sig <= ShiftIR_sig and TCK_dly;
     CLkUpdateIR_sig <= UpdateIR_sig and not TCK_dly;
  end process  prcs_ClkIR;

  prcs_ClkID:process(TCK_dly)
  begin
     ClkID_sig <= IDCODE_sig and TCK_dly;
  end process  prcs_ClkID;

  prcs_glblsigs:process(TCK_dly, UpdateDR_sig)
  begin
    if(falling_edge(TCK_dly)) then
       JTAG_CAPTURE_GLBL <= CaptureDR_sig;
       -- CR 211337 Reset should go high as soon as it gets to State Trlst
       --  JTAG_RESET_GLBL   <= Tlrst_sig;
       JTAG_SHIFT_GLBL   <= ShiftDR_sig;
       JTAG_UPDATE_GLBL  <= UpdateDR_sig;
       TlrstN_sig        <= Tlrst_sig;
    end if;
  
    if(falling_edge(UpdateDR_sig))then
      JTAG_UPDATE_GLBL  <= UpdateDR_sig;
    end if; 

  end process  prcs_glblsigs;

-- CR 211337
  prcs_reset:process(Tlrst_sig)
  begin
      JTAG_RESET_GLBL   <= Tlrst_sig;
  end process  prcs_reset;

--####################################################################
--#####                       JtagIR                             #####
--####################################################################
  prcs_JtagIR:process(ClkIR_sig, ClkUpdateIR_sig, ShiftIR_sig,  TlrstN_sig, TRST_dly)
  variable NextIRreg : std_logic_vector ((IRLength -1) downto 0) := IR_CAPTURE_VAL;
  variable ir_int    : std_logic_vector ((IRLength -1) downto 0) := IR_CAPTURE_VAL;
  begin
     NextIRreg((IRLength -1) downto 0) := (TDI_dly & ir_int((IRLength -1) downto 1)); 

     if((TRST_dly = '1') or (TlrstN_sig = '1'))then
        IRcontent_sig((IRLength -1) downto 0) <= IDCODE_INSTR;  -- IDCODE instruction is loaded into IR reg.
        IRegLastBit_sig <= ir_int(0);
     elsif((TRST_dly = '0') and (TlrstN_sig = '0')) then
        if(rising_edge(ClkIR_sig)) then
           if(ShiftIR_sig = '1') then
              ir_int((IRLength -1) downto 0) := NextIRreg((IRLength -1) downto 0);
              IRegLastBit_sig <= ir_int(0);
           else
               ir_int := IR_CAPTURE_VAL ;
               IRegLastBit_sig <= ir_int(0);
           end if;
        end if;
        if(rising_edge(ClkUpdateIR_sig)) then
           if(UpdateIR_sig = '1') then
              IRcontent_sig <= ir_int;
           end if;
        end if;
     end if;
  end process  prcs_JtagIR;
--####################################################################
--#####                       JtagDecodeIR                       #####
--####################################################################
  prcs_JtagDecodeIR:process(IRcontent_sig)
  begin
     case IRcontent_sig is

        when IR_CAPTURE_VAL =>
           JTagInstruction <= IR_CAPTURE;

        when BYPASS_INSTR =>
           JTagInstruction <= BYPASS;
           BYPASS_sig <= '1';
           IDCODE_sig <= '0';
           USER1_sig  <= '0';
           USER2_sig  <= '0';
           USER3_sig  <= '0';
           USER4_sig  <= '0';

        when IDCODE_INSTR =>
           JTagInstruction <= IDCODE;
           BYPASS_sig <= '0';
           IDCODE_sig <= '1';
           USER1_sig  <= '0';
           USER2_sig  <= '0';
           USER3_sig  <= '0';
           USER4_sig  <= '0';

        when USER1_INSTR =>
           JTagInstruction <= USER1;
           BYPASS_sig <= '0';
           IDCODE_sig <= '0';
           USER1_sig  <= '1';
           USER2_sig  <= '0';
           USER3_sig  <= '0';
           USER4_sig  <= '0';

        when USER2_INSTR => 
           JTagInstruction <= USER2;
           BYPASS_sig <= '0';
           IDCODE_sig <= '0';
           USER1_sig  <= '0';
           USER2_sig  <= '1';
           USER3_sig  <= '0';
           USER4_sig  <= '0';

        when USER3_INSTR => 
           JTagInstruction <= USER3;
           BYPASS_sig <= '0';
           IDCODE_sig <= '0';
           USER1_sig  <= '0';
           USER2_sig  <= '0';
           USER3_sig  <= '1';
           USER4_sig  <= '0';

        when USER4_INSTR => 
           JTagInstruction <= USER4;
           BYPASS_sig <= '0';
           IDCODE_sig <= '0';
           USER1_sig  <= '0';
           USER2_sig  <= '0';
           USER3_sig  <= '0';
           USER4_sig  <= '1';
        when others =>
           JTagInstruction <= UNKNOWN;
           NULL; 
     end case;
  end process prcs_JtagDecodeIR;
--####################################################################
--#####                       JtagIDCODE                         #####
--####################################################################
  prcs_JtagIDCODE:process(ClkID_sig)
  variable IDreg : bit_vector ((IDLength -1) downto 0);
  begin
     if(rising_edge(ClkID_sig)) then
        if(ShiftDR_sig = '1') then
          IDreg := IDreg sra 1;
          IDreg(IDLength -1) := TO_BIT(TDI_dly);
        else
          IDreg := TO_BITVECTOR(IDCODEval_sig);
        end if;
     end if;

     IDregLastBit_sig <= TO_STDULOGIC(IDreg(0));

  end process  prcs_JtagIDCODE;
--####################################################################
--####################################################################
--#####                    JtagSetGlobalSignals                  #####
--####################################################################
  prcs_JtagSetGlobalSignals:process(ClkUpdateIR_sig, Tlrst_sig, USER1_sig, USER2_sig, USER3_sig, USER4_sig)
  begin
     if(rising_edge(USER1_sig)) then
         JTAG_SEL1_GLBL     <= '1';
         JTAG_SEL2_GLBL     <= '0';
         JTAG_SEL3_GLBL     <= '0';
         JTAG_SEL4_GLBL     <= '0';
     elsif(rising_edge(USER2_sig)) then
         JTAG_SEL1_GLBL     <= '0';
         JTAG_SEL2_GLBL     <= '1';
         JTAG_SEL3_GLBL     <= '0';
         JTAG_SEL4_GLBL     <= '0';
     elsif(rising_edge(USER3_sig)) then
         JTAG_SEL1_GLBL     <= '0';
         JTAG_SEL2_GLBL     <= '0';
         JTAG_SEL3_GLBL     <= '1';
         JTAG_SEL4_GLBL     <= '0';
     elsif(rising_edge(USER4_sig)) then
         JTAG_SEL1_GLBL     <= '0';
         JTAG_SEL2_GLBL     <= '0';
         JTAG_SEL3_GLBL     <= '0';
         JTAG_SEL4_GLBL     <= '1';
     elsif(rising_edge(ClkUpdateIR_sig)) then
         JTAG_SEL1_GLBL     <= '0';
         JTAG_SEL2_GLBL     <= '0';
         JTAG_SEL3_GLBL     <= '0';
         JTAG_SEL4_GLBL     <= '0';
     elsif(rising_edge(Tlrst_sig)) then
         JTAG_SEL1_GLBL     <= '0';
         JTAG_SEL2_GLBL     <= '0';
         JTAG_SEL3_GLBL     <= '0';
         JTAG_SEL4_GLBL     <= '0';
     end if;

  end process prcs_JtagSetGlobalSignals;
      
--####################################################################

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################

  JTAG_TCK_GLBL  <= TCK_dly;
  JTAG_TDI_GLBL  <= TDI_dly;
  JTAG_TMS_GLBL  <= TMS_dly;
  JTAG_TRST_GLBL <= TRST_dly;

  TDO_latch <= BypassReg
         when ((CurrentState = ShiftDR) and (IRcontent_sig=BYPASS_INSTR))
       else IRegLastBit_sig
         when (CurrentState = ShiftIR)
       else IDregLastBit_sig
         when ((CurrentState = ShiftDR) and (IRcontent_sig=IDCODE_INSTR))
       else JTAG_USER_TDO1_GLBL
         when ((CurrentState = ShiftDR) and (IRcontent_sig=USER1_INSTR))
       else JTAG_USER_TDO2_GLBL
         when ((CurrentState = ShiftDR) and (IRcontent_sig=USER2_INSTR))
       else JTAG_USER_TDO3_GLBL
         when ((CurrentState = ShiftDR) and (IRcontent_sig=USER3_INSTR))
       else JTAG_USER_TDO4_GLBL
         when ((CurrentState = ShiftDR) and (IRcontent_sig=USER4_INSTR))
       else 'Z';

--  prcs_TDO:process(TCK_dly)
--  begin
--    if(falling_edge(TCK_dly)) then
--       TDO <= TDO_latch;
--    end if;
--  end process  prcs_TDO;

--####################################################################
--#####                         Timing                           #####
--####################################################################
  VITALBehavior                    : process (TCK_dly, TDI_dly, TMS_dly)

    variable PInfo_TCK           : VitalPeriodDataType := VitalPeriodDataInit;
    variable Pviol_TCK           : std_ulogic          := '0';

    variable Tmkr_TDI_TCK_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tviol_TDI_TCK_posedge : std_ulogic          := '0';

    variable Tmkr_TMS_TCK_posedge  : VitalTimingDataType := VitalTimingDataInit;
    variable Tviol_TMS_TCK_posedge : std_ulogic          := '0';

    variable Violation : std_ulogic := '0';

    variable TDO_GlitchData : VitalGlitchDataType;


  begin
      VitalSetupHoldCheck (
        Violation            => Tviol_TDI_TCK_posedge,
        TimingData           => Tmkr_TDI_TCK_posedge,
        TestSignal           => TDI_dly,
        TestSignalName       => "TDI",
        TestDelay            => tisd_TDI_TCK,
        RefSignal            => TCK_dly,
        RefSignalName        => "TCK",
        RefDelay             => ticd_TCK,
        SetupHigh            => tsetup_TDI_TCK_posedge_posedge,
        SetupLow             => tsetup_TDI_TCK_negedge_posedge,
        HoldLow              => thold_TDI_TCK_posedge_posedge,
        HoldHigh             => thold_TDI_TCK_negedge_posedge,
        CheckEnabled         => TO_X01(TRST_dly) = '0',
        RefTransition        => 'R',
        HeaderMsg            => "/X_JTAG_SIM_VIRTEX4",
        Xon                  => Xon,
        MsgOn                => MsgOn,
        MsgSeverity          => warning);

      VitalSetupHoldCheck (
        Violation            => Tviol_TMS_TCK_posedge,
        TimingData           => Tmkr_TMS_TCK_posedge,
        TestSignal           => TMS_dly,
        TestSignalName       => "TMS",
        TestDelay            => tisd_TMS_TCK,
        RefSignal            => TCK_dly,
        RefSignalName        => "TCK",
        RefDelay             => ticd_TCK,
        SetupHigh            => tsetup_TMS_TCK_posedge_posedge,
        SetupLow             => tsetup_TMS_TCK_negedge_posedge,
        HoldLow              => thold_TMS_TCK_posedge_posedge,
        HoldHigh             => thold_TMS_TCK_negedge_posedge,
        CheckEnabled         => TO_X01(TRST_dly) = '0',
        RefTransition        => 'R',
        HeaderMsg            => "/X_JTAG_SIM_VIRTEX4",
        Xon                  => Xon,
        MsgOn                => MsgOn,
        MsgSeverity          => warning);

      if(falling_edge(TCK_dly)) then
         VitalPathDelay01 (
           OutSignal              => TDO,
           GlitchData             => TDO_GlitchData,
           OutSignalName          => "TDO",
           OutTemp                => TDO_latch,
           Paths                  => (0 => (TCK_dly'last_event, tpd_TCK_TDO, TRST_dly = '0')),
           Mode                   => VitalTransport,
           Xon                    => Xon,
           MsgOn                  => MsgOn,
           MsgSeverity            => warning);
      end if;
  end process;

--####################################################################
--####################################################################


end JTAG_SIM_SPARTAN3A_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                     16K-Bit Data and 2K-Bit Parity Single Port Block RAM
-- /___/   /\     Filename : RAMB16BWE_S18_S18.vhd
-- \   \  /  \    Timestamp : Wed Jun 8 16:43:35 PST 2005
--  \___\/\___\
--
-- Generated by : write_vhdl
--
-- Revision:
--    06/08/05 - Initial version.
-- End Revision

----- CELL RAMB16BWE_S18_S18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity RAMB16BWE_S18_S18 is
generic (

	INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

	INIT_A : bit_vector := X"00000";
	INIT_B : bit_vector := X"00000";

	INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

	SIM_COLLISION_CHECK : string := "ALL";

	SRVAL_A  : bit_vector := X"00000";
	SRVAL_B  : bit_vector := X"00000";

	WRITE_MODE_A : string := "WRITE_FIRST";
	WRITE_MODE_B : string := "WRITE_FIRST"
	);

port (
	DOA : out std_logic_vector(15 downto 0);
	DOB : out std_logic_vector(15 downto 0);
	DOPA : out std_logic_vector(1 downto 0);
	DOPB : out std_logic_vector(1 downto 0);

	ADDRA : in std_logic_vector(9 downto 0);
	ADDRB : in std_logic_vector(9 downto 0);
	CLKA : in std_ulogic;
	CLKB : in std_ulogic;
	DIA : in std_logic_vector(15 downto 0);
	DIB : in std_logic_vector(15 downto 0);
	DIPA : in std_logic_vector(1 downto 0);
	DIPB : in std_logic_vector(1 downto 0);
	ENA : in std_ulogic;
	ENB : in std_ulogic;
	SSRA : in std_ulogic;
	SSRB : in std_ulogic;
	WEA :  in std_logic_vector(1 downto 0);
	WEB :  in std_logic_vector(1 downto 0)
     );
end RAMB16BWE_S18_S18;

-- Architecture body --

architecture RAMB16BWE_S18_S18_V of RAMB16BWE_S18_S18 is

 signal DOA_open  : std_logic_vector(15 downto 0);
 signal DOB_open  : std_logic_vector(15 downto 0);
 signal DOPA_open : std_logic_vector(1 downto 0);
 signal DOPB_open : std_logic_vector(1 downto 0);

 signal ADDRA_GND : std_logic_vector(3 downto 0) := (others => '0');
 signal ADDRB_GND : std_logic_vector(3 downto 0) := (others => '0');

 signal DIA_GND : std_logic_vector(15 downto 0) := (others => '0');
 signal DIB_GND : std_logic_vector(15 downto 0) := (others => '0');

 signal DIPA_GND : std_logic_vector(1 downto 0) := (others => '0');
 signal DIPB_GND : std_logic_vector(1 downto 0) := (others => '0');

begin
-- RAMB16BWE Instantiation (port map, generic map)
RAMB16BWE_inst : RAMB16BWE
	generic map (
	DATA_WIDTH_A => 18,
	DATA_WIDTH_B => 18,

	INIT_00 => INIT_00,
	INIT_01 => INIT_01,
	INIT_02 => INIT_02,
	INIT_03 => INIT_03,
	INIT_04 => INIT_04,
	INIT_05 => INIT_05,
	INIT_06 => INIT_06,
	INIT_07 => INIT_07,
	INIT_08 => INIT_08,
	INIT_09 => INIT_09,
	INIT_0A => INIT_0A,
	INIT_0B => INIT_0B,
	INIT_0C => INIT_0C,
	INIT_0D => INIT_0D,
	INIT_0E => INIT_0E,
	INIT_0F => INIT_0F,
	INIT_10 => INIT_10,
	INIT_11 => INIT_11,
	INIT_12 => INIT_12,
	INIT_13 => INIT_13,
	INIT_14 => INIT_14,
	INIT_15 => INIT_15,
	INIT_16 => INIT_16,
	INIT_17 => INIT_17,
	INIT_18 => INIT_18,
	INIT_19 => INIT_19,
	INIT_1A => INIT_1A,
	INIT_1B => INIT_1B,
	INIT_1C => INIT_1C,
	INIT_1D => INIT_1D,
	INIT_1E => INIT_1E,
	INIT_1F => INIT_1F,
	INIT_20 => INIT_20,
	INIT_21 => INIT_21,
	INIT_22 => INIT_22,
	INIT_23 => INIT_23,
	INIT_24 => INIT_24,
	INIT_25 => INIT_25,
	INIT_26 => INIT_26,
	INIT_27 => INIT_27,
	INIT_28 => INIT_28,
	INIT_29 => INIT_29,
	INIT_2A => INIT_2A,
	INIT_2B => INIT_2B,
	INIT_2C => INIT_2C,
	INIT_2D => INIT_2D,
	INIT_2E => INIT_2E,
	INIT_2F => INIT_2F,
	INIT_30 => INIT_30,
	INIT_31 => INIT_31,
	INIT_32 => INIT_32,
	INIT_33 => INIT_33,
	INIT_34 => INIT_34,
	INIT_35 => INIT_35,
	INIT_36 => INIT_36,
	INIT_37 => INIT_37,
	INIT_38 => INIT_38,
	INIT_39 => INIT_39,
	INIT_3A => INIT_3A,
	INIT_3B => INIT_3B,
	INIT_3C => INIT_3C,
	INIT_3D => INIT_3D,
	INIT_3E => INIT_3E,
	INIT_3F => INIT_3F,

	INIT_A  => INIT_A,
	INIT_B  => INIT_B,

	INITP_00 => INITP_00,
	INITP_01 => INITP_01,
	INITP_02 => INITP_02,
	INITP_03 => INITP_03,
	INITP_04 => INITP_04,
	INITP_05 => INITP_05,
	INITP_06 => INITP_06,
	INITP_07 => INITP_07,

	SIM_COLLISION_CHECK => SIM_COLLISION_CHECK,

	SRVAL_A => SRVAL_A,
	SRVAL_B => SRVAL_B,

	WRITE_MODE_A => WRITE_MODE_A,
	WRITE_MODE_B => WRITE_MODE_B
	)
port map (
	ADDRA(13 downto 4)   => ADDRA,
        ADDRA(3 downto 0) => ADDRA_GND(3 downto 0),
	ADDRB(13 downto 4)   => ADDRB,
        ADDRB(3 downto 0) => ADDRB_GND(3 downto 0),
	CLKA => CLKA,
	CLKB => CLKB,
	DIA(15 downto 0)  => DIA,
	DIA(31 downto 16) => DIA_GND,
	DIB(15 downto 0)  => DIB,
	DIB(31 downto 16) => DIB_GND,
	DIPA(1 downto 0)  => DIPA,
	DIPA(3 downto 2)  => DIPA_GND,
	DIPB(1 downto 0)  => DIPB,
	DIPB(3 downto 2)  => DIPB_GND,
	ENA => ENA,
	ENB => ENB,
	SSRA => SSRA,
	SSRB => SSRB,
	WEA(0) => WEA(0),
	WEA(1) => WEA(1),
	WEA(2) => WEA(0),
	WEA(3) => WEA(1),
	WEB(0) => WEB(0),
	WEB(1) => WEB(1),
	WEB(2) => WEB(0),
	WEB(3) => WEB(1),
	DOA(15 downto 0)  => DOA,
	DOA(31 downto 16) => DOA_open,
	DOB(15 downto 0)  => DOB,
	DOB(31 downto 16) => DOB_open,
	DOPA(1 downto 0)  => DOPA,
	DOPA(3 downto 2)  => DOPA_open,
	DOPB(1 downto 0)  => DOPB,
	DOPB(3 downto 2)  => DOPB_open
	);

end RAMB16BWE_S18_S18_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                     16K-Bit Data and 2K-Bit Parity Single Port Block RAM
-- /___/   /\     Filename : RAMB16BWE_S18_S9.vhd
-- \   \  /  \    Timestamp : Wed Jun 8 16:43:35 PST 2005
--  \___\/\___\
--
-- Generated by : write_vhdl
--
-- Revision:
--    06/08/05 - Initial version.
-- End Revision

----- CELL RAMB16BWE_S18_S9 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity RAMB16BWE_S18_S9 is
generic (

	INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

	INIT_A : bit_vector := X"00000";
	INIT_B : bit_vector := X"000";

	INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

	SIM_COLLISION_CHECK : string := "ALL";

	SRVAL_A  : bit_vector := X"00000";
	SRVAL_B  : bit_vector := X"000";

	WRITE_MODE_A : string := "WRITE_FIRST";
	WRITE_MODE_B : string := "WRITE_FIRST"
	);

port (
	DOA : out std_logic_vector(15 downto 0);
	DOB : out std_logic_vector(7 downto 0);
	DOPA : out std_logic_vector(1 downto 0);
	DOPB : out std_logic_vector(0 downto 0);

	ADDRA : in std_logic_vector(9 downto 0);
	ADDRB : in std_logic_vector(10 downto 0);
	CLKA : in std_ulogic;
	CLKB : in std_ulogic;
	DIA : in std_logic_vector(15 downto 0);
	DIB : in std_logic_vector(7 downto 0);
	DIPA : in std_logic_vector(1 downto 0);
	DIPB : in std_logic_vector(0 downto 0);
	ENA : in std_ulogic;
	ENB : in std_ulogic;
	SSRA : in std_ulogic;
	SSRB : in std_ulogic;
	WEA :  in std_logic_vector(1 downto 0);
	WEB :  in std_ulogic
     );
end RAMB16BWE_S18_S9;

-- Architecture body --

architecture RAMB16BWE_S18_S9_V of RAMB16BWE_S18_S9 is

 signal DOA_open  : std_logic_vector(15 downto 0);
 signal DOB_open  : std_logic_vector(23 downto 0);
 signal DOPA_open : std_logic_vector(1 downto 0);
 signal DOPB_open : std_logic_vector(2 downto 0);

 signal ADDRA_GND : std_logic_vector(3 downto 0) := (others => '0');
 signal ADDRB_GND : std_logic_vector(2 downto 0) := (others => '0');

 signal DIA_GND : std_logic_vector(15 downto 0) := (others => '0');
 signal DIB_GND : std_logic_vector(23 downto 0) := (others => '0');

 signal DIPA_GND : std_logic_vector(1 downto 0) := (others => '0');
 signal DIPB_GND : std_logic_vector(2 downto 0) := (others => '0');

begin
-- RAMB16BWE Instantiation (port map, generic map)
RAMB16BWE_inst : RAMB16BWE
	generic map (
	DATA_WIDTH_A => 18,
	DATA_WIDTH_B => 9,

	INIT_00 => INIT_00,
	INIT_01 => INIT_01,
	INIT_02 => INIT_02,
	INIT_03 => INIT_03,
	INIT_04 => INIT_04,
	INIT_05 => INIT_05,
	INIT_06 => INIT_06,
	INIT_07 => INIT_07,
	INIT_08 => INIT_08,
	INIT_09 => INIT_09,
	INIT_0A => INIT_0A,
	INIT_0B => INIT_0B,
	INIT_0C => INIT_0C,
	INIT_0D => INIT_0D,
	INIT_0E => INIT_0E,
	INIT_0F => INIT_0F,
	INIT_10 => INIT_10,
	INIT_11 => INIT_11,
	INIT_12 => INIT_12,
	INIT_13 => INIT_13,
	INIT_14 => INIT_14,
	INIT_15 => INIT_15,
	INIT_16 => INIT_16,
	INIT_17 => INIT_17,
	INIT_18 => INIT_18,
	INIT_19 => INIT_19,
	INIT_1A => INIT_1A,
	INIT_1B => INIT_1B,
	INIT_1C => INIT_1C,
	INIT_1D => INIT_1D,
	INIT_1E => INIT_1E,
	INIT_1F => INIT_1F,
	INIT_20 => INIT_20,
	INIT_21 => INIT_21,
	INIT_22 => INIT_22,
	INIT_23 => INIT_23,
	INIT_24 => INIT_24,
	INIT_25 => INIT_25,
	INIT_26 => INIT_26,
	INIT_27 => INIT_27,
	INIT_28 => INIT_28,
	INIT_29 => INIT_29,
	INIT_2A => INIT_2A,
	INIT_2B => INIT_2B,
	INIT_2C => INIT_2C,
	INIT_2D => INIT_2D,
	INIT_2E => INIT_2E,
	INIT_2F => INIT_2F,
	INIT_30 => INIT_30,
	INIT_31 => INIT_31,
	INIT_32 => INIT_32,
	INIT_33 => INIT_33,
	INIT_34 => INIT_34,
	INIT_35 => INIT_35,
	INIT_36 => INIT_36,
	INIT_37 => INIT_37,
	INIT_38 => INIT_38,
	INIT_39 => INIT_39,
	INIT_3A => INIT_3A,
	INIT_3B => INIT_3B,
	INIT_3C => INIT_3C,
	INIT_3D => INIT_3D,
	INIT_3E => INIT_3E,
	INIT_3F => INIT_3F,

	INIT_A  => INIT_A,
	INIT_B  => INIT_B,

	INITP_00 => INITP_00,
	INITP_01 => INITP_01,
	INITP_02 => INITP_02,
	INITP_03 => INITP_03,
	INITP_04 => INITP_04,
	INITP_05 => INITP_05,
	INITP_06 => INITP_06,
	INITP_07 => INITP_07,

	SIM_COLLISION_CHECK => SIM_COLLISION_CHECK,

	SRVAL_A => SRVAL_A,
	SRVAL_B => SRVAL_B,

	WRITE_MODE_A => WRITE_MODE_A,
	WRITE_MODE_B => WRITE_MODE_B
	)
port map (
	ADDRA(13 downto 4)   => ADDRA,
        ADDRA(3 downto 0) => ADDRA_GND(3 downto 0),
	ADDRB(13 downto 3)   => ADDRB,
        ADDRB(2 downto 0) => ADDRB_GND(2 downto 0),
	CLKA => CLKA,
	CLKB => CLKB,
	DIA(15 downto 0)  => DIA,
	DIA(31 downto 16) => DIA_GND,
	DIB(7 downto 0)  => DIB,
	DIB(31 downto 8) => DIB_GND,
	DIPA(1 downto 0)  => DIPA,
	DIPA(3 downto 2)  => DIPA_GND,
	DIPB(0 downto 0)  => DIPB,
	DIPB(3 downto 1)  => DIPB_GND,
	ENA => ENA,
	ENB => ENB,
	SSRA => SSRA,
	SSRB => SSRB,
	WEA(0) => WEA(0),
	WEA(1) => WEA(1),
	WEA(2) => WEA(0),
	WEA(3) => WEA(1),
	WEB(0) => WEB,
	WEB(1) => WEB,
	WEB(2) => WEB,
	WEB(3) => WEB,
	DOA(15 downto 0)  => DOA,
	DOA(31 downto 16) => DOA_open,
	DOB(7 downto 0)  => DOB,
	DOB(31 downto 8) => DOB_open,
	DOPA(1 downto 0)  => DOPA,
	DOPA(3 downto 2)  => DOPA_open,
	DOPB(0 downto 0)  => DOPB,
	DOPB(3 downto 1)  => DOPB_open
	);

end RAMB16BWE_S18_S9_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                       16K-Bit Data and 2K-Bit Parity Single Port Block RAM
-- /___/   /\     Filename : RAMB16BWE_S18.vhd
-- \   \  /  \    Timestamp : Wed Jun 8 16:43:35 PST 2005
--  \___\/\___\
--
-- Generated by : write_vhdl
--
-- Revision:
--    06/08/05 - Initial version.
-- End Revision

----- CELL RAMB16BWE_S18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity RAMB16BWE_S18 is
generic (

	INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

	INIT : bit_vector := X"00000";

	INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
	INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

	SRVAL  : bit_vector := X"00000";

	WRITE_MODE : string := "WRITE_FIRST"
	);

port (
	DO : out std_logic_vector(15 downto 0);
	DOP : out std_logic_vector(1 downto 0);

	ADDR : in std_logic_vector(9 downto 0);
	CLK : in std_ulogic;
	DI : in std_logic_vector(15 downto 0);
	DIP : in std_logic_vector(1 downto 0);
	EN : in std_ulogic;
	SSR : in std_ulogic;
	WE :  in std_logic_vector(1 downto 0)
     );
end RAMB16BWE_S18;

-- Architecture body --

architecture RAMB16BWE_S18_V of RAMB16BWE_S18 is

 signal DOA_open  : std_logic_vector(15 downto 0);
 signal DOB_open  : std_logic_vector(31 downto 0);
 signal DOPA_open : std_logic_vector(1 downto 0);
 signal DOPB_open : std_logic_vector(3 downto 0);

 signal ADDRA_GND : std_logic_vector(3 downto 0) := (others => '0');
 signal ADDRB_GND : std_logic_vector(13 downto 0) := (others => '0');

 signal DIA_GND : std_logic_vector(15 downto 0) := (others => '0');
 signal DIB_GND : std_logic_vector(31 downto 0) := (others => '0');

 signal DIPA_GND : std_logic_vector(1 downto 0) := (others => '0');
 signal DIPB_GND : std_logic_vector(3 downto 0) := (others => '0');

 signal CLKB_GND, ENB_GND, SSRB_GND : std_ulogic := '0';
 signal WEB_GND : std_logic_vector(3 downto 0) := (others => '0');

begin
-- RAMB16BWE Instantiation (port map, generic map)
RAMB16BWE_inst : RAMB16BWE
	generic map (
	DATA_WIDTH_A => 18,

	INIT_00 => INIT_00,
	INIT_01 => INIT_01,
	INIT_02 => INIT_02,
	INIT_03 => INIT_03,
	INIT_04 => INIT_04,
	INIT_05 => INIT_05,
	INIT_06 => INIT_06,
	INIT_07 => INIT_07,
	INIT_08 => INIT_08,
	INIT_09 => INIT_09,
	INIT_0A => INIT_0A,
	INIT_0B => INIT_0B,
	INIT_0C => INIT_0C,
	INIT_0D => INIT_0D,
	INIT_0E => INIT_0E,
	INIT_0F => INIT_0F,
	INIT_10 => INIT_10,
	INIT_11 => INIT_11,
	INIT_12 => INIT_12,
	INIT_13 => INIT_13,
	INIT_14 => INIT_14,
	INIT_15 => INIT_15,
	INIT_16 => INIT_16,
	INIT_17 => INIT_17,
	INIT_18 => INIT_18,
	INIT_19 => INIT_19,
	INIT_1A => INIT_1A,
	INIT_1B => INIT_1B,
	INIT_1C => INIT_1C,
	INIT_1D => INIT_1D,
	INIT_1E => INIT_1E,
	INIT_1F => INIT_1F,
	INIT_20 => INIT_20,
	INIT_21 => INIT_21,
	INIT_22 => INIT_22,
	INIT_23 => INIT_23,
	INIT_24 => INIT_24,
	INIT_25 => INIT_25,
	INIT_26 => INIT_26,
	INIT_27 => INIT_27,
	INIT_28 => INIT_28,
	INIT_29 => INIT_29,
	INIT_2A => INIT_2A,
	INIT_2B => INIT_2B,
	INIT_2C => INIT_2C,
	INIT_2D => INIT_2D,
	INIT_2E => INIT_2E,
	INIT_2F => INIT_2F,
	INIT_30 => INIT_30,
	INIT_31 => INIT_31,
	INIT_32 => INIT_32,
	INIT_33 => INIT_33,
	INIT_34 => INIT_34,
	INIT_35 => INIT_35,
	INIT_36 => INIT_36,
	INIT_37 => INIT_37,
	INIT_38 => INIT_38,
	INIT_39 => INIT_39,
	INIT_3A => INIT_3A,
	INIT_3B => INIT_3B,
	INIT_3C => INIT_3C,
	INIT_3D => INIT_3D,
	INIT_3E => INIT_3E,
	INIT_3F => INIT_3F,

	INIT_A  => INIT,

	INITP_00 => INITP_00,
	INITP_01 => INITP_01,
	INITP_02 => INITP_02,
	INITP_03 => INITP_03,
	INITP_04 => INITP_04,
	INITP_05 => INITP_05,
	INITP_06 => INITP_06,
	INITP_07 => INITP_07,

	SIM_COLLISION_CHECK => "NONE",

	SRVAL_A => SRVAL,

	WRITE_MODE_A => WRITE_MODE
	)
port map (
	ADDRA(13 downto 4)   => ADDR,
        ADDRA(3 downto 0) => ADDRA_GND(3 downto 0),
        ADDRB(13 downto 0) => ADDRB_GND(13 downto 0),
	CLKA => CLK,
	CLKB => CLKB_GND,
	DIA(15 downto 0)  => DI,
	DIA(31 downto 16) => DIA_GND,
	DIB(31 downto 0) => DIB_GND,
	DIPA(1 downto 0)  => DIP,
	DIPA(3 downto 2)  => DIPA_GND,
	DIPB(3 downto 0)  => DIPB_GND,
	ENA => EN,
	ENB => ENB_GND,
	SSRA => SSR,
	SSRB => SSRB_GND,
	WEA(0) => WE(0),
	WEA(1) => WE(1),
	WEA(2) => WE(0),
	WEA(3) => WE(1),
	WEB    => WEB_GND,
	DOA(15 downto 0)  => DO,
	DOA(31 downto 16) => DOA_open,
	DOB(31 downto 0)  => DOB_open,
	DOPA(1 downto 0)  => DOP,
	DOPA(3 downto 2)  => DOPA_open,
	DOPB(3 downto 0)  => DOPB_open
	);

end RAMB16BWE_S18_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Single Port Block RAM
-- /___/   /\     Filename : RAMB16BWE_S36_S18.vhd
-- \   \  /  \    Timestamp : Wed Jun 8 16:43:35 PST 2005
--  \___\/\___\
--
-- Generated by : write_vhdl
--
-- Revision:
--    06/08/05 - Initial version.
-- End Revision

----- CELL RAMB16BWE_S36_S18 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity RAMB16BWE_S36_S18 is
generic (

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"000000000";
    INIT_B : bit_vector := X"00000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A  : bit_vector := X"000000000";
    SRVAL_B  : bit_vector := X"00000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
  );

port (
		DOA : out std_logic_vector(31 downto 0);
		DOB : out std_logic_vector(15 downto 0);
		DOPA : out std_logic_vector(3 downto 0);
		DOPB : out std_logic_vector(1 downto 0);

		ADDRA : in std_logic_vector(8 downto 0);
		ADDRB : in std_logic_vector(9 downto 0);
		CLKA : in std_ulogic;
		CLKB : in std_ulogic;
		DIA : in std_logic_vector(31 downto 0);
		DIB : in std_logic_vector(15 downto 0);
		DIPA : in std_logic_vector(3 downto 0);
		DIPB : in std_logic_vector(1 downto 0);
		ENA : in std_ulogic;
		ENB : in std_ulogic;
		SSRA : in std_ulogic;
		SSRB : in std_ulogic;
		WEA : in std_logic_vector(3 downto 0);
		WEB : in std_logic_vector(1 downto 0)
     );
end RAMB16BWE_S36_S18;

-- Architecture body --

architecture RAMB16BWE_S36_S18_V of RAMB16BWE_S36_S18 is

 signal DOB_open  : std_logic_vector(15 downto 0);
 signal DOPB_open : std_logic_vector(1 downto 0);

 signal ADDRA_GND : std_logic_vector(4 downto 0) := (others => '0');
 signal ADDRB_GND : std_logic_vector(3 downto 0) := (others => '0');

 signal DIB_GND : std_logic_vector(15 downto 0) := (others => '0');

 signal DIPB_GND : std_logic_vector(1 downto 0) := (others => '0');


begin

-- RAMB16BWE Instantiation

RAMB16BWE_inst : RAMB16BWE
	generic map (
		DATA_WIDTH_A => 36,
		DATA_WIDTH_B => 18,

		INIT_00 => INIT_00,
		INIT_01 => INIT_01,
		INIT_02 => INIT_02,
		INIT_03 => INIT_03,
		INIT_04 => INIT_04,
		INIT_05 => INIT_05,
		INIT_06 => INIT_06,
		INIT_07 => INIT_07,
		INIT_08 => INIT_08,
		INIT_09 => INIT_09,
		INIT_0A => INIT_0A,
		INIT_0B => INIT_0B,
		INIT_0C => INIT_0C,
		INIT_0D => INIT_0D,
		INIT_0E => INIT_0E,
		INIT_0F => INIT_0F,
		INIT_10 => INIT_10,
		INIT_11 => INIT_11,
		INIT_12 => INIT_12,
		INIT_13 => INIT_13,
		INIT_14 => INIT_14,
		INIT_15 => INIT_15,
		INIT_16 => INIT_16,
		INIT_17 => INIT_17,
		INIT_18 => INIT_18,
		INIT_19 => INIT_19,
		INIT_1A => INIT_1A,
		INIT_1B => INIT_1B,
		INIT_1C => INIT_1C,
		INIT_1D => INIT_1D,
		INIT_1E => INIT_1E,
		INIT_1F => INIT_1F,
		INIT_20 => INIT_20,
		INIT_21 => INIT_21,
		INIT_22 => INIT_22,
		INIT_23 => INIT_23,
		INIT_24 => INIT_24,
		INIT_25 => INIT_25,
		INIT_26 => INIT_26,
		INIT_27 => INIT_27,
		INIT_28 => INIT_28,
		INIT_29 => INIT_29,
		INIT_2A => INIT_2A,
		INIT_2B => INIT_2B,
		INIT_2C => INIT_2C,
		INIT_2D => INIT_2D,
		INIT_2E => INIT_2E,
		INIT_2F => INIT_2F,
		INIT_30 => INIT_30,
		INIT_31 => INIT_31,
		INIT_32 => INIT_32,
		INIT_33 => INIT_33,
		INIT_34 => INIT_34,
		INIT_35 => INIT_35,
		INIT_36 => INIT_36,
		INIT_37 => INIT_37,
		INIT_38 => INIT_38,
		INIT_39 => INIT_39,
		INIT_3A => INIT_3A,
		INIT_3B => INIT_3B,
		INIT_3C => INIT_3C,
		INIT_3D => INIT_3D,
		INIT_3E => INIT_3E,
		INIT_3F => INIT_3F,

		INIT_A  => INIT_A,
		INIT_B  => INIT_B,

		INITP_00 => INITP_00,
		INITP_01 => INITP_01,
		INITP_02 => INITP_02,
		INITP_03 => INITP_03,
		INITP_04 => INITP_04,
		INITP_05 => INITP_05,
		INITP_06 => INITP_06,
		INITP_07 => INITP_07,

		SIM_COLLISION_CHECK => SIM_COLLISION_CHECK,

		SRVAL_A => SRVAL_A,
		SRVAL_B => SRVAL_B,

		WRITE_MODE_A => WRITE_MODE_A,
		WRITE_MODE_B => WRITE_MODE_B
	)
        port map (
                ADDRA(13 downto 5)   => ADDRA,
                ADDRA(4 downto 0)  => ADDRA_GND(4 downto 0),
                ADDRB(13 downto 4)  => ADDRB,
                ADDRB(3 downto 0) => ADDRB_GND(3 downto 0),
                CLKA => CLKA,
                CLKB => CLKB,
                DIA(31 downto 0) => DIA,
                DIB(15 downto 0)  => DIB,
                DIB(31 downto 16) => DIB_GND,
                DIPA(3 downto 0) => DIPA,
                DIPB(1 downto 0) => DIPB,
                DIPB(3 downto 2) => DIPB_GND,
                ENA => ENA,
                ENB => ENB,
                SSRA => SSRA,
                SSRB => SSRB,
                WEA(0) => WEA(0),
                WEA(1) => WEA(1),
                WEA(2) => WEA(2),
                WEA(3) => WEA(3),
                WEB(0) => WEB(0),
                WEB(1) => WEB(1),
                WEB(2) => WEB(0),
                WEB(3) => WEB(1),
                DOA(31 downto 0) => DOA,
                DOB(15  downto 0) => DOB,
                DOB(31 downto 16) => DOB_open,
                DOPA(3 downto 0) => DOPA,
                DOPB(1 downto 0) => DOPB,
                DOPB(3 downto 2) => DOPB_open

        );
end RAMB16BWE_S36_S18_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Single Port Block RAM
-- /___/   /\     Filename : RAMB16BWE_S36_S36.vhd
-- \   \  /  \    Timestamp : Wed Jun 8 16:43:35 PST 2005
--  \___\/\___\
--
-- Generated by : write_vhdl
--
-- Revision:
--    06/08/05 - Initial version.
-- End Revision

----- CELL RAMB16BWE_S36_S36 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity RAMB16BWE_S36_S36 is
generic (

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"000000000";
    INIT_B : bit_vector := X"000000000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A  : bit_vector := X"000000000";
    SRVAL_B  : bit_vector := X"000000000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
  );

port (
		DOA : out std_logic_vector(31 downto 0);
		DOB : out std_logic_vector(31 downto 0);
		DOPA : out std_logic_vector(3 downto 0);
		DOPB : out std_logic_vector(3 downto 0);

		ADDRA : in std_logic_vector(8 downto 0);
		ADDRB : in std_logic_vector(8 downto 0);
		CLKA : in std_ulogic;
		CLKB : in std_ulogic;
		DIA : in std_logic_vector(31 downto 0);
		DIB : in std_logic_vector(31 downto 0);
		DIPA : in std_logic_vector(3 downto 0);
		DIPB : in std_logic_vector(3 downto 0);
		ENA : in std_ulogic;
		ENB : in std_ulogic;
		SSRA : in std_ulogic;
		SSRB : in std_ulogic;
		WEA : in std_logic_vector(3 downto 0);
		WEB : in std_logic_vector(3 downto 0)
     );
end RAMB16BWE_S36_S36;

-- Architecture body --

architecture RAMB16BWE_S36_S36_V of RAMB16BWE_S36_S36 is

 signal ADDRA_GND : std_logic_vector(4 downto 0) := (others => '0');
 signal ADDRB_GND : std_logic_vector(4 downto 0) := (others => '0');



begin

-- RAMB16BWE Instantiation

RAMB16BWE_inst : RAMB16BWE
	generic map (
		DATA_WIDTH_A => 36,
		DATA_WIDTH_B => 36,

		INIT_00 => INIT_00,
		INIT_01 => INIT_01,
		INIT_02 => INIT_02,
		INIT_03 => INIT_03,
		INIT_04 => INIT_04,
		INIT_05 => INIT_05,
		INIT_06 => INIT_06,
		INIT_07 => INIT_07,
		INIT_08 => INIT_08,
		INIT_09 => INIT_09,
		INIT_0A => INIT_0A,
		INIT_0B => INIT_0B,
		INIT_0C => INIT_0C,
		INIT_0D => INIT_0D,
		INIT_0E => INIT_0E,
		INIT_0F => INIT_0F,
		INIT_10 => INIT_10,
		INIT_11 => INIT_11,
		INIT_12 => INIT_12,
		INIT_13 => INIT_13,
		INIT_14 => INIT_14,
		INIT_15 => INIT_15,
		INIT_16 => INIT_16,
		INIT_17 => INIT_17,
		INIT_18 => INIT_18,
		INIT_19 => INIT_19,
		INIT_1A => INIT_1A,
		INIT_1B => INIT_1B,
		INIT_1C => INIT_1C,
		INIT_1D => INIT_1D,
		INIT_1E => INIT_1E,
		INIT_1F => INIT_1F,
		INIT_20 => INIT_20,
		INIT_21 => INIT_21,
		INIT_22 => INIT_22,
		INIT_23 => INIT_23,
		INIT_24 => INIT_24,
		INIT_25 => INIT_25,
		INIT_26 => INIT_26,
		INIT_27 => INIT_27,
		INIT_28 => INIT_28,
		INIT_29 => INIT_29,
		INIT_2A => INIT_2A,
		INIT_2B => INIT_2B,
		INIT_2C => INIT_2C,
		INIT_2D => INIT_2D,
		INIT_2E => INIT_2E,
		INIT_2F => INIT_2F,
		INIT_30 => INIT_30,
		INIT_31 => INIT_31,
		INIT_32 => INIT_32,
		INIT_33 => INIT_33,
		INIT_34 => INIT_34,
		INIT_35 => INIT_35,
		INIT_36 => INIT_36,
		INIT_37 => INIT_37,
		INIT_38 => INIT_38,
		INIT_39 => INIT_39,
		INIT_3A => INIT_3A,
		INIT_3B => INIT_3B,
		INIT_3C => INIT_3C,
		INIT_3D => INIT_3D,
		INIT_3E => INIT_3E,
		INIT_3F => INIT_3F,
		INIT_A  => INIT_A,
		INIT_B  => INIT_B,

		INITP_00 => INITP_00,
		INITP_01 => INITP_01,
		INITP_02 => INITP_02,
		INITP_03 => INITP_03,
		INITP_04 => INITP_04,
		INITP_05 => INITP_05,
		INITP_06 => INITP_06,
		INITP_07 => INITP_07,

		SIM_COLLISION_CHECK => SIM_COLLISION_CHECK,

		SRVAL_A => SRVAL_A,
		SRVAL_B => SRVAL_B,

		WRITE_MODE_A => WRITE_MODE_A,
		WRITE_MODE_B => WRITE_MODE_B
	)
        port map (
                ADDRA(13 downto 5)   => ADDRA,
                ADDRA(4 downto 0)  => ADDRA_GND(4 downto 0),
                ADDRB(13 downto 5)   => ADDRB,
                ADDRB(4 downto 0)  => ADDRB_GND(4 downto 0),
                CLKA => CLKA,
                CLKB => CLKB,
                DIA(31 downto 0) => DIA,
                DIB(31 downto 0) => DIB,
                DIPA(3 downto 0) => DIPA,
                DIPB(3 downto 0) => DIPB,
                ENA => ENA,
                ENB => ENB,
                SSRA => SSRA,
                SSRB => SSRB,
                WEA => WEA,
                WEB => WEB,
                DOA(31 downto 0) => DOA,
                DOB(31 downto 0) => DOB,
                DOPA(3 downto 0) => DOPA,
                DOPB(3 downto 0) => DOPB

        );
end RAMB16BWE_S36_S36_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Single Port Block RAM
-- /___/   /\     Filename : RAMB16BWE_S36_S9.vhd
-- \   \  /  \    Timestamp : Wed Jun 8 16:43:35 PST 2005
--  \___\/\___\
--
-- Generated by : write_vhdl
--
-- Revision:
--    06/08/05 - Initial version.
-- End Revision


----- CELL RAMB16BWE_S36_S9 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity RAMB16BWE_S36_S9 is
generic (

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"000000000";
    INIT_B : bit_vector := X"000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A  : bit_vector := X"000000000";
    SRVAL_B  : bit_vector := X"000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
  );

port (
		DOA : out std_logic_vector(31 downto 0);
		DOB : out std_logic_vector(7 downto 0);
		DOPA : out std_logic_vector(3 downto 0);
		DOPB : out std_logic_vector(0 downto 0);

		ADDRA : in std_logic_vector(8 downto 0);
		ADDRB : in std_logic_vector(10 downto 0);
		CLKA : in std_ulogic;
		CLKB : in std_ulogic;
		DIA : in std_logic_vector(31 downto 0);
		DIB : in std_logic_vector(7 downto 0);
		DIPA : in std_logic_vector(3 downto 0);
		DIPB : in std_logic_vector(0 downto 0);
		ENA : in std_ulogic;
		ENB : in std_ulogic;
		SSRA : in std_ulogic;
		SSRB : in std_ulogic;
		WEA : in std_logic_vector(3 downto 0);
		WEB : in std_ulogic
     );
end RAMB16BWE_S36_S9;

-- Architecture body --

architecture RAMB16BWE_S36_S9_V of RAMB16BWE_S36_S9 is

 signal DOB_open  : std_logic_vector(23 downto 0);
 signal DOPB_open : std_logic_vector(2 downto 0);

 signal ADDRA_GND : std_logic_vector(4 downto 0) := (others => '0');
 signal ADDRB_GND : std_logic_vector(2 downto 0) := (others => '0');

 signal DIB_GND : std_logic_vector(23 downto 0) := (others => '0');
 signal DIPB_GND : std_logic_vector(2 downto 0) := (others => '0');


begin

-- RAMB16BWE Instantiation

RAMB16BWE_inst : RAMB16BWE
	generic map (
		DATA_WIDTH_A => 36,
		DATA_WIDTH_B => 9,

		INIT_00 => INIT_00,
		INIT_01 => INIT_01,
		INIT_02 => INIT_02,
		INIT_03 => INIT_03,
		INIT_04 => INIT_04,
		INIT_05 => INIT_05,
		INIT_06 => INIT_06,
		INIT_07 => INIT_07,
		INIT_08 => INIT_08,
		INIT_09 => INIT_09,
		INIT_0A => INIT_0A,
		INIT_0B => INIT_0B,
		INIT_0C => INIT_0C,
		INIT_0D => INIT_0D,
		INIT_0E => INIT_0E,
		INIT_0F => INIT_0F,
		INIT_10 => INIT_10,
		INIT_11 => INIT_11,
		INIT_12 => INIT_12,
		INIT_13 => INIT_13,
		INIT_14 => INIT_14,
		INIT_15 => INIT_15,
		INIT_16 => INIT_16,
		INIT_17 => INIT_17,
		INIT_18 => INIT_18,
		INIT_19 => INIT_19,
		INIT_1A => INIT_1A,
		INIT_1B => INIT_1B,
		INIT_1C => INIT_1C,
		INIT_1D => INIT_1D,
		INIT_1E => INIT_1E,
		INIT_1F => INIT_1F,
		INIT_20 => INIT_20,
		INIT_21 => INIT_21,
		INIT_22 => INIT_22,
		INIT_23 => INIT_23,
		INIT_24 => INIT_24,
		INIT_25 => INIT_25,
		INIT_26 => INIT_26,
		INIT_27 => INIT_27,
		INIT_28 => INIT_28,
		INIT_29 => INIT_29,
		INIT_2A => INIT_2A,
		INIT_2B => INIT_2B,
		INIT_2C => INIT_2C,
		INIT_2D => INIT_2D,
		INIT_2E => INIT_2E,
		INIT_2F => INIT_2F,
		INIT_30 => INIT_30,
		INIT_31 => INIT_31,
		INIT_32 => INIT_32,
		INIT_33 => INIT_33,
		INIT_34 => INIT_34,
		INIT_35 => INIT_35,
		INIT_36 => INIT_36,
		INIT_37 => INIT_37,
		INIT_38 => INIT_38,
		INIT_39 => INIT_39,
		INIT_3A => INIT_3A,
		INIT_3B => INIT_3B,
		INIT_3C => INIT_3C,
		INIT_3D => INIT_3D,
		INIT_3E => INIT_3E,
		INIT_3F => INIT_3F,
		INIT_A  => INIT_A,
		INIT_B  => INIT_B,

		INITP_00 => INITP_00,
		INITP_01 => INITP_01,
		INITP_02 => INITP_02,
		INITP_03 => INITP_03,
		INITP_04 => INITP_04,
		INITP_05 => INITP_05,
		INITP_06 => INITP_06,
		INITP_07 => INITP_07,

		SIM_COLLISION_CHECK => SIM_COLLISION_CHECK,

		SRVAL_A => SRVAL_A,
		SRVAL_B => SRVAL_B,

		WRITE_MODE_A => WRITE_MODE_A,
		WRITE_MODE_B => WRITE_MODE_B
	)
        port map (
                ADDRA(13 downto 5)  => ADDRA,
                ADDRA(4 downto 0)   => ADDRA_GND(4 downto 0),
                ADDRB(13 downto 3)  => ADDRB,
                ADDRB(2 downto 0)   => ADDRB_GND(2 downto 0),
                CLKA => CLKA,
                CLKB => CLKB,
                DIA(31 downto 0) => DIA,
                DIB(7 downto 0)  => DIB,
                DIB(31 downto 8) => DIB_GND,
                DIPA(3 downto 0) => DIPA,
                DIPB(0 downto 0) => DIPB,
                DIPB(3 downto 1) => DIPB_GND,
                ENA => ENA,
                ENB => ENB,
                SSRA => SSRA,
                SSRB => SSRB,
                WEA(0) => WEA(0),
                WEA(1) => WEA(1),
                WEA(2) => WEA(2),
                WEA(3) => WEA(3),
                WEB(0) => WEB,
                WEB(1) => WEB,
                WEB(2) => WEB,
                WEB(3) => WEB,
                DOA(31 downto 0) => DOA,
                DOB(7  downto 0) => DOB,
                DOB(31 downto 8) => DOB_open,
                DOPA(3 downto 0) => DOPA,
                DOPB(0 downto 0) => DOPB,
                DOPB(3 downto 1) => DOPB_open
        );
end RAMB16BWE_S36_S9_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Single Port Block RAM
-- /___/   /\     Filename : RAMB16BWE_S36.vhd
-- \   \  /  \    Timestamp : Wed Jun 8 16:43:35 PST 2005
--  \___\/\___\
--
-- Generated by : write_vhdl
--
-- Revision:
--    06/08/05 - Initial version.
-- End Revision

----- CELL RAMB16BWE_S36 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

library unisim;
use unisim.VCOMPONENTS.all;

entity RAMB16BWE_S36 is
generic (

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT : bit_vector := X"000000000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    SRVAL  : bit_vector := X"000000000";

    WRITE_MODE : string := "WRITE_FIRST"
  );

port (
		DO : out std_logic_vector(31 downto 0);
		DOP : out std_logic_vector(3 downto 0);

		ADDR : in std_logic_vector(8 downto 0);
		CLK : in std_ulogic;
		DI : in std_logic_vector(31 downto 0);
		DIP : in std_logic_vector(3 downto 0);
		EN : in std_ulogic;
		SSR : in std_ulogic;
		WE : in std_logic_vector(3 downto 0)
     );
end RAMB16BWE_S36;

-- Architecture body --

architecture RAMB16BWE_S36_V of RAMB16BWE_S36 is

 signal ADDRA_GND : std_logic_vector(4 downto 0) := (others => '0');
 signal ADDRB_GND : std_logic_vector(13 downto 0) := (others => '0');

 signal DOB_open  : std_logic_vector(31 downto 0);
 signal DOPB_open : std_logic_vector(3 downto 0);


 signal DIB_GND : std_logic_vector(31 downto 0) := (others => '0');
 signal DIPB_GND : std_logic_vector(3 downto 0) := (others => '0');

 signal CLKB_GND, ENB_GND, SSRB_GND : std_ulogic := '0';
 signal WEB_GND : std_logic_vector(3 downto 0) := (others => '0');


begin

-- RAMB16BWE Instantiation

RAMB16BWE_inst : RAMB16BWE
	generic map (
		DATA_WIDTH_A => 36,
		DATA_WIDTH_B => 36,

		INIT_00 => INIT_00,
		INIT_01 => INIT_01,
		INIT_02 => INIT_02,
		INIT_03 => INIT_03,
		INIT_04 => INIT_04,
		INIT_05 => INIT_05,
		INIT_06 => INIT_06,
		INIT_07 => INIT_07,
		INIT_08 => INIT_08,
		INIT_09 => INIT_09,
		INIT_0A => INIT_0A,
		INIT_0B => INIT_0B,
		INIT_0C => INIT_0C,
		INIT_0D => INIT_0D,
		INIT_0E => INIT_0E,
		INIT_0F => INIT_0F,
		INIT_10 => INIT_10,
		INIT_11 => INIT_11,
		INIT_12 => INIT_12,
		INIT_13 => INIT_13,
		INIT_14 => INIT_14,
		INIT_15 => INIT_15,
		INIT_16 => INIT_16,
		INIT_17 => INIT_17,
		INIT_18 => INIT_18,
		INIT_19 => INIT_19,
		INIT_1A => INIT_1A,
		INIT_1B => INIT_1B,
		INIT_1C => INIT_1C,
		INIT_1D => INIT_1D,
		INIT_1E => INIT_1E,
		INIT_1F => INIT_1F,
		INIT_20 => INIT_20,
		INIT_21 => INIT_21,
		INIT_22 => INIT_22,
		INIT_23 => INIT_23,
		INIT_24 => INIT_24,
		INIT_25 => INIT_25,
		INIT_26 => INIT_26,
		INIT_27 => INIT_27,
		INIT_28 => INIT_28,
		INIT_29 => INIT_29,
		INIT_2A => INIT_2A,
		INIT_2B => INIT_2B,
		INIT_2C => INIT_2C,
		INIT_2D => INIT_2D,
		INIT_2E => INIT_2E,
		INIT_2F => INIT_2F,
		INIT_30 => INIT_30,
		INIT_31 => INIT_31,
		INIT_32 => INIT_32,
		INIT_33 => INIT_33,
		INIT_34 => INIT_34,
		INIT_35 => INIT_35,
		INIT_36 => INIT_36,
		INIT_37 => INIT_37,
		INIT_38 => INIT_38,
		INIT_39 => INIT_39,
		INIT_3A => INIT_3A,
		INIT_3B => INIT_3B,
		INIT_3C => INIT_3C,
		INIT_3D => INIT_3D,
		INIT_3E => INIT_3E,
		INIT_3F => INIT_3F,
		INIT_A  => INIT,

		INITP_00 => INITP_00,
		INITP_01 => INITP_01,
		INITP_02 => INITP_02,
		INITP_03 => INITP_03,
		INITP_04 => INITP_04,
		INITP_05 => INITP_05,
		INITP_06 => INITP_06,
		INITP_07 => INITP_07,

		SIM_COLLISION_CHECK => "NONE",

		SRVAL_A => SRVAL,

		WRITE_MODE_A => WRITE_MODE
	)
        port map (
                ADDRA(13 downto 5)   => ADDR,
                ADDRA(4 downto 0)  => ADDRA_GND(4 downto 0),
                ADDRB(13 downto 0)  => ADDRB_GND(13 downto 0),
                CLKA => CLK,
                CLKB => CLKB_GND,
                DIA  => DI,
                DIB  => DIB_GND,
                DIPA => DIP,
                DIPB => DIPB_GND,
                ENA => EN,
                ENB => ENB_GND,
                SSRA => SSR,
                SSRB => SSRB_GND,
                WEA => WE,
                WEB => WEB_GND,
                DOA(31 downto 0) => DO,
                DOB(31 downto 0) => DOB_OPEN,
                DOPA => DOP,
                DOPB => DOPB_OPEN

        );
end RAMB16BWE_S36_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Timing Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Single Port Block RAM
-- /___/   /\     Filename : RAMB16BWE.vhd
-- \   \  /  \    Timestamp : Fri Mar 26 08:18:21 PST 2004
--  \___\/\___\
--
-- Revision:
--    03/23/04 - Initial version.

----- CELL RAMB16BWE -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library STD;
use STD.TEXTIO.all;



library unisim;
use unisim.vpkg.all;

entity RAMB16BWE is

  generic (

    DATA_WIDTH_A : integer := 0;
    DATA_WIDTH_B : integer := 0;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"000000000";
    INIT_B : bit_vector := X"000000000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";


    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A  : bit_vector := X"000000000";
    SRVAL_B  : bit_vector := X"000000000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA          : out std_logic_vector (31 downto 0);
    DOB          : out std_logic_vector (31 downto 0);
    DOPA         : out std_logic_vector (3 downto 0);
    DOPB         : out std_logic_vector (3 downto 0);

    ADDRA        : in  std_logic_vector (13 downto 0);
    ADDRB        : in  std_logic_vector (13 downto 0);
    CLKA         : in  std_ulogic;
    CLKB         : in  std_ulogic;
    DIA          : in  std_logic_vector (31 downto 0);
    DIB          : in  std_logic_vector (31 downto 0);
    DIPA         : in  std_logic_vector (3 downto 0);
    DIPB         : in  std_logic_vector (3 downto 0);
    ENA          : in  std_ulogic;
    ENB          : in  std_ulogic;
    SSRA         : in  std_ulogic;
    SSRB         : in  std_ulogic;
    WEA          : in  std_logic_vector (3 downto 0);
    WEB          : in  std_logic_vector (3 downto 0)
    );

end RAMB16BWE;

architecture RAMB16BWE_V of RAMB16BWE is


-- Constants

  constant MAX_ADDR: integer := 13;

  constant MAX_DI:   integer := 31;
  constant MAX_DIP:  integer := 3;
  constant MAX_WE:   integer := 3;

  constant SYNC_PATH_DELAY : time  := 100 ps;

  TYPE CollisionFlagType IS RECORD
     active_port : integer; 
     read_write  : boolean; 
     write_read  : boolean; 
     write_write : boolean; 
     we          : std_logic_vector(MAX_WE downto 0);
  END RECORD;

  TYPE DataWidthType IS RECORD
     diaw  : integer; 
     dipaw : integer; 
     doaw  : integer; 
     dopaw : integer; 
     dibw  : integer; 
     dipbw : integer; 
     dobw  : integer; 
     dopbw : integer; 
  END RECORD;

  TYPE ClsnXbufType IS RECORD
     DO1_clsn   : std_logic_vector(31 downto 0);
     DOP1_clsn  : std_logic_vector(3 downto 0);
     MEM1_clsn  : std_logic_vector(31 downto 0);
     MEMP1_clsn : std_logic_vector(3 downto 0);

     DO2_clsn   : std_logic_vector(31 downto 0);
     DOP2_clsn  : std_logic_vector(3 downto 0);
     MEM2_clsn  : std_logic_vector(31 downto 0);
     MEMP2_clsn : std_logic_vector(3 downto 0);
  END RECORD;

  TYPE memory_collision_type is (Read_A_Write_B,
                                 Write_A_Read_B,
                                 Write_A_Write_B,
                                 Read_B_Write_A,
                                 Write_B_Read_A,
                                 Write_B_Write_A);

  constant SETUP_ALL       : time  := 1000 ps;
  constant SETUP_READ_FIRST : time := 3000 ps;

-- Procedures and Functions

------------------------------------------------
-- procedure ClkCollisionCheck
------------------------------------------------
--
--  Checks whether the time duration of rising
--  clka and clkb violates required setup time
--  between these clocks.
--
   procedure ClkCollisionCheck(
             variable violation        : out integer;
             constant CheckEnabled     : in boolean := false;
             variable CLK1_time        : in time := 0 ns;
             variable CLK2_time        : in time := 0 ns;
             constant SETUP_ALL        : in time := 0 ns;
             constant SETUP_READ_FIRST : in time := 0 ns
   ) is

   begin

     violation := 0;
     if(CheckEnabled) then
        if((CLK1_time > 0 ns ) and (CLK2_time > 0 ns )) then
           if((CLK1_time - CLK2_time) = 0 ns ) then
              violation := 3;
           elsif ((CLK1_time - CLK2_time) < SETUP_ALL) then
              violation := 11;
           elsif ((CLK1_time - CLK2_time) < SETUP_READ_FIRST) then
              violation := 12;
           end if;
        end if;
     end if;
   end ClkCollisionCheck;

------------------------------------------------
-- function AddrOverlapCheck
------------------------------------------------
--

   function AddrOverlapCheck(
                   d1w         : in integer := 0;
                   d2w         : in integer := 0;
                   addr1       : in  std_logic_vector(MAX_ADDR downto 0)   := (others => 'X');
                   addr2       : in  std_logic_vector(MAX_ADDR downto 0)   := (others => 'X');
                   zero_addr1  : in  std_logic_vector(MAX_ADDR downto 0)   := (others => 'X');
                   zero_addr2  : in  std_logic_vector(MAX_ADDR downto 0)   := (others => 'X');
                   we_segment  : in integer := 0
   ) return boolean is 
   variable collision, port1_overlap, port2_overlap : boolean := false;
   variable addr1_zero_int, addr2_zero_int, wea_index, INDEX1, INDEX2 : integer := -1;
   variable tmp_addr1_zero, tmp_addr2_zero : std_logic_vector(MAX_ADDR downto 0) := (others => 'X');
   variable zero_out                       : std_logic_vector(MAX_ADDR downto 0)   := (others => 'X');
   variable tmp_we                         : std_logic_vector(1 downto 0)          := (others => '0');


   
   
   begin
     INDEX1 := SLV_TO_INT(addr1(4 downto 0));
     INDEX2 := SLV_TO_INT(addr2(4 downto 0));

     if(D1W >= D2W) then  
        zero_out := zero_addr1;
     elsif(D1W < D2W) then
        zero_out := zero_addr2;
     end if;

     tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_out);
     tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_out);

     addr1_zero_int := SLV_TO_INT(tmp_addr1_zero); 
     addr2_zero_int := SLV_TO_INT(tmp_addr2_zero); 
   
--     if((addr1_zero_int = addr2_zero_int) and ((INDEX1 + D1W) > we_segment * 8 ) and ((INDEX2 + D2W) > we_segment * 8 )) then
     if(addr1_zero_int = addr2_zero_int) then

        case D1W is
           ---------
           when 1|2|4|8 =>
           ---------
              tmp_we(1 downto 0) := addr1( 4 downto 3);
              wea_index := SLV_TO_INT(tmp_we);
              if(wea_index = we_segment) then
                port1_overlap := true;
              end if;

           ---------
           when 16 =>
           ---------

              tmp_we(1) := addr1(4);
              tmp_we(0) := '0';
              wea_index := SLV_TO_INT(tmp_we);
              if(wea_index = we_segment) then
                port1_overlap := true;
              end if;
   
              tmp_we(1) := addr1(4);
              tmp_we(0) := '1';
              wea_index := SLV_TO_INT(tmp_we);
              if(wea_index = we_segment) then
                port1_overlap := true;
              end if;
            
           ---------
           when 32 =>
           ---------

                port1_overlap := true;

           ---------
           when others => null;
           ---------
        end case;



        case D2W is
           ---------
           when 1|2|4|8 =>
           ---------
              tmp_we(1 downto 0) := addr2( 4 downto 3);
              wea_index := SLV_TO_INT(tmp_we);
              if(wea_index = we_segment) then
                port2_overlap := true;
              end if;

           ---------
           when 16 =>
           ---------

              tmp_we(1) := addr2(4);
              tmp_we(0) := '0';
              wea_index := SLV_TO_INT(tmp_we);
              if(wea_index = we_segment) then
                port2_overlap := true;
              end if;
   
              tmp_we(1) := addr2(4);
              tmp_we(0) := '1';
              wea_index := SLV_TO_INT(tmp_we);
              if(wea_index = we_segment) then
                port2_overlap := true;
              end if;
            
           ---------
           when 32 =>
           ---------

                port2_overlap := true;

           ---------
           when others => null;
           ---------
        end case;

     end if;

     collision :=  (port1_overlap and port2_overlap);
     return collision;
   end;
------------------------------------------------
-- procedure QkAddrOverlapChk
------------------------------------------------
--

   procedure QkAddrOverlapChk(
                   variable addr_overlap : out boolean;
                   variable data_widths  : in DataWidthType;
                   variable addra        : in  std_logic_vector(MAX_ADDR downto 0) := (others => 'X');
                   variable addrb        : in  std_logic_vector(MAX_ADDR downto 0) := (others => 'X')
   ) is
   variable addra_int, addrb_int, max_width : integer := -1;
   variable tmp_addra_zero, tmp_addrb_zero  : std_logic_vector(MAX_ADDR downto 0) := (others => 'X');
   variable zero_data_out                   : std_logic_vector(MAX_ADDR downto 0) := (others => 'X');
   variable zero_parity_out                 : std_logic_vector((MAX_ADDR-3) downto 0) := (others => 'X');
 
   begin
     addr_overlap := false;
     zero_data_out   := (others => '1');
     zero_parity_out := (others => '1');

     max_width := data_widths.diaw;

     if(data_widths.doaw > max_width) then
        max_width := data_widths.doaw;
     end if;
   
     if(data_widths.dibw > max_width) then
        max_width := data_widths.dibw;
     end if;

     if(data_widths.dobw > max_width) then
        max_width := data_widths.dobw;
     end if;

    
     case max_width is

        -------
        when 32 =>
        -------
            zero_data_out(4 downto 0) := (others => '0'); 
            zero_parity_out(1 downto 0) := (others => '0'); 

        -------
        when 16 =>
        -------
            zero_data_out(3 downto 0) := (others => '0'); 
            zero_parity_out(0 downto 0) := (others => '0'); 

        -------
        when 8 =>
        -------
            zero_data_out(2 downto 0) := (others => '0'); 

        -------
        when 4 =>
        -------
            zero_data_out(1 downto 0) := (others => '0'); 

        -------
        when 2 =>
        -------
            zero_data_out(0 downto 0) := (others => '0'); 

        -------
        when others =>
        -------
           null;


     end case;

     tmp_addra_zero := (addra(MAX_ADDR downto 0) and zero_data_out);
     tmp_addrb_zero := (addrb(MAX_ADDR downto 0) and zero_data_out);

     addra_int := SLV_TO_INT(tmp_addra_zero); 
     addrb_int := SLV_TO_INT(tmp_addrb_zero); 
   
     if(addra_int = addrb_int) then
          addr_overlap := true;
     end if;

   end QkAddrOverlapChk;

------------------------------------------------
-- procedure SameDataChk 
------------------------------------------------
--
--  Checks whether the data written is the same
--  as in the memory, or in the case of both ports
--  writing whether the inputs are the same.
--  If true, then there is no collision
--
   procedure SameDataChk(
             variable same_data  : out boolean;
             variable same_datap : out boolean;
             constant MEM        : in std_logic_vector(18431 downto 0); 
             constant di1        : in std_logic_vector(31 downto 0);
             constant di2        : in std_logic_vector(31 downto 0);
             constant dip1       : in std_logic_vector(3 downto 0);
             constant dip2       : in std_logic_vector(3 downto 0);
             variable addr1      : in std_logic_vector(13 downto 0) := (others => 'X');
             variable addr2      : in std_logic_vector(13 downto 0) := (others => 'X');
             variable addrp1     : in std_logic_vector(10 downto 0) := (others => 'X');
             variable addrp2     : in std_logic_vector(10 downto 0) := (others => 'X');
             variable wr_mode_1  : in std_logic_vector(1 downto 0) := "00";
             variable wr_mode_2  : in std_logic_vector(1 downto 0) := "00";
             constant we_segment : in integer := -1;
             variable we1        : in std_ulogic := 'X';
             variable we2        : in std_ulogic := 'X';
             variable D1W       : in integer := -1;
             variable D1PW      : in integer := -1;
             variable D2W       : in integer := -1;
             variable D2PW      : in integer := -1
   ) is
   variable REM1 : integer := -1;
   variable REM2 : integer := -1;
   variable XOUT_BITS : integer := -1;
   variable XOUT_BITS_1 : integer := -1;
   variable XOUT_PBITS_1 : integer := 0;
   variable INDEX, INDEXP, DATA_INDEX : integer := -1;
   variable ADDRESS, ADDRESS_P, ADDRESS32_1, ADDRESS32P_1, ADDRESS32_2, ADDRESS32P_2 : integer := -1;
   variable SMALL_ADDRESS32, SMALL_ADDRESS32P : integer := -1;
   variable SMALL_DW : integer := -1;

  
   variable TableRow : std_logic_vector(1 downto 0) := (others => '0');

   variable cmp_d1_buf   : std_logic_vector(7 downto 0) := (others => '0');
   variable cmp_d1p_buf  : std_logic_vector(0 downto 0) := (others => '0');
   variable cmp_d2_buf   : std_logic_vector(7 downto 0) := (others => '0');
   variable cmp_d2p_buf  : std_logic_vector(0 downto 0) := (others => '0');
   variable cmp_mem_buf  : std_logic_vector(7 downto 0) := (others => '0');
   variable cmp_memp_buf : std_logic_vector(0 downto 0) := (others => '0');

   variable cmp_d1_buf32 : std_logic_vector(31 downto 0) := (others => '0');
   variable cmp_d1p_buf4 : std_logic_vector(3 downto 0)  := (others => '0');
   variable cmp_d2_buf32 : std_logic_vector(31 downto 0) := (others => '0');
   variable cmp_d2p_buf4 : std_logic_vector(3 downto 0)  := (others => '0');

   variable tmp_cmp_d1_buf  : std_logic_vector(7 downto 0) := (others => '0');
   variable tmp_cmp_d1p_buf : std_logic_vector(0 downto 0) := (others => '0');
   variable tmp_cmp_d2_buf  : std_logic_vector(7 downto 0) := (others => '0');
   variable tmp_cmp_d2p_buf : std_logic_vector(0 downto 0) := (others => '0');

   variable memp_fp      :  std_logic_vector(3 downto 0)  := (others => '0');

   begin

-- ##################################################################
-----------------------------------------------------------------------
------------ Port 1  Active Clock -------------------------------------
-----------------------------------------------------------------------

      same_data  := false;
      same_datap := false;

      if((D1W >= D2W) and (D2W < 8)) then
         INDEX := SLV_TO_INT(addr2(4 downto 0));
      elsif((D2W >= D1W) and (D1W < 8)) then
         INDEX := SLV_TO_INT(addr1(4 downto 0));
      else
         INDEX := we_segment * 8;
      end if;


      ---  Data Bits ---

      REM1 := D1W REM 8;
      REM2 := D2W REM 8;

      -- find the minimum data bits to overlap
      if((REM1 = 0) and (REM2 = 0)) then
          XOUT_BITS := 8 ;
      elsif(REM1 = 0) then
          XOUT_BITS := REM2;
      elsif(REM2 = 0) then
          XOUT_BITS := REM1;
      elsif(REM1 > REM2) then
          XOUT_BITS := REM2 ;
      elsif (REM1 <= REM2) then
          XOUT_BITS := REM1 ;
      end if;

      XOUT_BITS_1 := XOUT_BITS - 1 ;


      if(D1W <= D2W) then
         SMALL_DW := D1W;
         ADDRESS  := SLV_TO_INT(addr1);
         SMALL_ADDRESS32:= SLV_TO_INT(addr1(4 downto 0));
      elsif(D1W > D2W) then
         SMALL_DW := D2W;
         ADDRESS  := SLV_TO_INT(addr2);
         SMALL_ADDRESS32:= SLV_TO_INT(addr2(4 downto 0));
      end if;

      if(D1PW <= D2PW) then
         ADDRESS_P := SLV_TO_INT(addrp1);
         SMALL_ADDRESS32P:= SLV_TO_INT(addrp1(1 downto 0));
      elsif(D1PW > D2PW) then
         ADDRESS_P := SLV_TO_INT(addrp2);
         SMALL_ADDRESS32P:= SLV_TO_INT(addrp2(1 downto 0));
      end if;
  
      INDEXP  := we_segment;
 
      TableRow := (we1 & we2);

      cmp_d1_buf   := (others => '0'); 
      cmp_d1p_buf  := (others => '0'); 
      cmp_d2_buf   := (others => '0'); 
      cmp_d2p_buf  := (others => '0'); 
      cmp_mem_buf  := (others => '0'); 
      cmp_memp_buf := (others => '0'); 

--==================================================================================================
      ADDRESS32_1  := SLV_TO_INT(addr1(4 downto 0));
      ADDRESS32P_1 := SLV_TO_INT(addrp1(1 downto 0));
      cmp_d1_buf32(((D1W - 1) + ADDRESS32_1) downto ADDRESS32_1)   :=  di1((D1W - 1) downto 0);
      cmp_d1p_buf4(((D1PW - 1) + ADDRESS32P_1) downto ADDRESS32P_1) :=  dip1((D1PW - 1) downto 0);

      ADDRESS32_2  := SLV_TO_INT(addr2(4 downto 0));
      ADDRESS32P_2 := SLV_TO_INT(addrp2(1 downto 0));
      cmp_d2_buf32(((D2W - 1) + ADDRESS32_2) downto ADDRESS32_2)    :=  di2((D2W - 1) downto 0);
      cmp_d2p_buf4(((D2PW - 1) + ADDRESS32P_2) downto ADDRESS32P_2) :=  dip2((D2PW - 1 ) downto 0);

      case SMALL_DW is
         when 1|2|4 =>
            cmp_mem_buf(XOUT_BITS_1 downto 0)      := MEM((XOUT_BITS_1 + ADDRESS ) downto (ADDRESS)); 
               
            tmp_cmp_d1_buf(XOUT_BITS_1 downto 0)   :=  cmp_d1_buf32((XOUT_BITS_1 + SMALL_ADDRESS32 ) downto SMALL_ADDRESS32);
            tmp_cmp_d2_buf(XOUT_BITS_1 downto 0)   :=  cmp_d2_buf32((XOUT_BITS_1 + SMALL_ADDRESS32 ) downto SMALL_ADDRESS32);

         when 8 =>
            cmp_mem_buf(XOUT_BITS_1 downto 0)      := MEM((XOUT_BITS_1 + ADDRESS ) downto (ADDRESS)); 
            cmp_memp_buf(XOUT_PBITS_1 downto 0)    := MEM((XOUT_PBITS_1 + 16384 + ADDRESS_P) downto (ADDRESS_P + 16384)); 

            tmp_cmp_d1_buf(XOUT_BITS_1 downto 0)   := cmp_d1_buf32((XOUT_BITS_1 + SMALL_ADDRESS32 ) downto SMALL_ADDRESS32);
            tmp_cmp_d1p_buf(XOUT_PBITS_1 downto 0) := cmp_d1p_buf4((XOUT_PBITS_1 + SMALL_ADDRESS32P) downto SMALL_ADDRESS32P);  

            tmp_cmp_d2_buf(XOUT_BITS_1 downto 0)   := cmp_d2_buf32((XOUT_BITS_1 + SMALL_ADDRESS32 ) downto SMALL_ADDRESS32);
            tmp_cmp_d2p_buf(XOUT_PBITS_1 downto 0) := cmp_d2p_buf4((XOUT_PBITS_1 + SMALL_ADDRESS32P) downto SMALL_ADDRESS32P);  

         when 16 =>
            if((we_segment = 0) or (we_segment = 2)) then
                DATA_INDEX := 0;
            elsif((we_segment = 1) or (we_segment = 3))then
                DATA_INDEX := 1;
            end if;

            cmp_mem_buf(XOUT_BITS_1 downto 0)   := MEM((XOUT_BITS_1 + ADDRESS + DATA_INDEX*8 ) downto (DATA_INDEX*8 + ADDRESS)); 
            cmp_memp_buf(XOUT_PBITS_1 downto 0) := MEM((XOUT_PBITS_1 + 16384 + DATA_INDEX + ADDRESS_P) downto (DATA_INDEX + ADDRESS_P + 16384)); 
            tmp_cmp_d1_buf(XOUT_BITS_1 downto 0)   := cmp_d1_buf32((XOUT_BITS_1 + we_segment*8 ) downto we_segment*8);
            tmp_cmp_d1p_buf(XOUT_PBITS_1 downto 0) := cmp_d1p_buf4((XOUT_PBITS_1 + we_segment*1) downto we_segment*1);  

            tmp_cmp_d2_buf(XOUT_BITS_1 downto 0)   := cmp_d2_buf32((XOUT_BITS_1 + we_segment*8 ) downto we_segment*8);
            tmp_cmp_d2p_buf(XOUT_PBITS_1 downto 0) := cmp_d2p_buf4((XOUT_PBITS_1 + we_segment*1) downto we_segment*1);  

         when 32 =>
            cmp_mem_buf(XOUT_BITS_1 downto 0)   := MEM((XOUT_BITS_1 + INDEX + ADDRESS ) downto (INDEX + ADDRESS)); 
            cmp_memp_buf(XOUT_PBITS_1 downto 0) := MEM((XOUT_PBITS_1 + 16384 + INDEXP + ADDRESS_P) downto (INDEXP + ADDRESS_P + 16384)); 

            tmp_cmp_d1_buf(XOUT_BITS_1 downto 0)   := cmp_d1_buf32((XOUT_BITS_1 + we_segment*8 ) downto we_segment*8);
            tmp_cmp_d1p_buf(XOUT_PBITS_1 downto 0) := cmp_d1p_buf4((XOUT_PBITS_1 + we_segment*1) downto we_segment*1);  

            tmp_cmp_d2_buf(XOUT_BITS_1 downto 0)   := cmp_d2_buf32((XOUT_BITS_1 + we_segment*8 ) downto we_segment*8);
            tmp_cmp_d2p_buf(XOUT_PBITS_1 downto 0) := cmp_d2p_buf4((XOUT_PBITS_1 + we_segment*1) downto we_segment*1);  

         when  others => null; 

      end case;

      case TableRow is
---===============================================================================
---                           wea&web = 11
---===============================================================================
          ----
          when "11" =>
          ----
              
               memp_fp := MEM(( 3 + 16384 + ADDRESS_P) downto (16384 + ADDRESS_P)); 


               if((tmp_cmp_d1_buf = tmp_cmp_d2_buf) and (tmp_cmp_d2_buf = cmp_mem_buf)) then
                   same_data := true;
               end if;

           -- Parity
               if((D1PW /= 0) and (D2PW /= 0)) then
                  if((tmp_cmp_d1p_buf = tmp_cmp_d2p_buf) and (tmp_cmp_d2p_buf = cmp_memp_buf)) then
                      same_datap := true;
                  end if;
               end if;
---===============================================================================
---                           wea&web = 01
---===============================================================================
          ----
          when "01" =>
          ----

               if(tmp_cmp_d2_buf = cmp_mem_buf) then
                   same_data := true;
               end if;

               -- Parity
               if((D1PW /= 0) and (D2PW /= 0)) then
                  if(tmp_cmp_d2p_buf = cmp_memp_buf) then
                      same_datap := true;
                  end if;
               end if;
---===============================================================================
---                           wea&web = 10
---===============================================================================
          ----
          when "10" =>
          ----
               if(tmp_cmp_d1_buf = cmp_mem_buf) then
                   same_data := true;
               end if;

               -- Parity
               if((D1PW /= 0) and (D2PW /= 0)) then
                  if(tmp_cmp_d1p_buf = cmp_memp_buf) then
                      same_datap := true;
                  end if;
               end if;
---===============================================================================
---                           others 
---===============================================================================

          ---------
          when others =>
          ---------
                null;
      end case;

   end SameDataChk;

------------------------------------------------
-- procedure CollisionTableRest
------------------------------------------------
--
--  Checks whether the time duration of rising
--  clka and clkb violates required setup time
--  between these clocks.
--
   procedure CollisionTableRest(
             variable clsn_bufs      : out ClsnXbufType;
             variable same_data_flg  : out boolean;
             variable same_datap_flg : out boolean;
             constant MEM            : in std_logic_vector(18431 downto 0);
             constant di1            : in std_logic_vector(31 downto 0);
             constant di2            : in std_logic_vector(31 downto 0);
             constant dip1           : in std_logic_vector(3 downto 0);
             constant dip2           : in std_logic_vector(3 downto 0);
             variable addr1          : in std_logic_vector(13 downto 0) := (others => 'X');
             variable addr2          : in std_logic_vector(13 downto 0) := (others => 'X');
             variable addrp1         : in std_logic_vector(10 downto 0) := (others => 'X');
             variable addrp2         : in std_logic_vector(10 downto 0) := (others => 'X');
             variable wr_mode_1      : in std_logic_vector(1 downto 0) := "00";
             variable wr_mode_2      : in std_logic_vector(1 downto 0) := "00";
             constant we_segment     : in integer := -1;
             constant violation      : in integer := -1;
             variable we1            : in std_ulogic := 'X';
             variable we2            : in std_ulogic := 'X';
             variable D1W            : in integer := -1;
             variable D1PW           : in integer := -1;
             variable D2W            : in integer := -1;
             variable D2PW           : in integer := -1
   ) is
   variable REM1 : integer := -1;
   variable REM2 : integer := -1;
   variable XOUT_BITS : integer := -1;
   variable XOUT_BITS_1 : integer := -1;
   variable INDEX, INDEX_P : integer := -1;
  
   variable TableRow :  std_logic_vector(5 downto 0) := (others => '0');
   variable we1we2   :  std_logic_vector(1 downto 0) := (others => '0');

   variable same_data                : boolean    := false;
   variable same_datap               : boolean    := false;
   variable SAME_DATA_CHECK_DISABLED : boolean    := true;

   begin

-- ##################################################################
-----------------------------------------------------------------------
------------ Port 1  Active Clock -------------------------------------
-----------------------------------------------------------------------


   if((D1W >= D2W) and (D2W < 8)) then
      INDEX := SLV_TO_INT(addr2(4 downto 0));
   elsif((D2W >= D1W) and (D1W < 8)) then
      INDEX := SLV_TO_INT(addr1(4 downto 0));
   else
      INDEX := we_segment * 8;
   end if;


   ---  Data Bits ---

   REM1 := D1W REM 8;
   REM2 := D2W REM 8;

   -- find the minimum data bits to overlap
   if((REM1 = 0) and (REM2 = 0)) then
       XOUT_BITS := 8 ;
   elsif(REM1 = 0) then
       XOUT_BITS := REM2;
   elsif(REM2 = 0) then
       XOUT_BITS := REM1;
   elsif(REM1 > REM2) then
       XOUT_BITS := REM2 ;
   elsif (REM1 <= REM2) then
       XOUT_BITS := REM1 ;
   end if;

   XOUT_BITS_1 := XOUT_BITS - 1 ;



   ---  Parity Bits ---

   -- find the minimum parity bits to overlap

   if(D1PW >= D2PW) then
      INDEX_P := SLV_TO_INT(addrp2(1 downto 0));
   else
      INDEX_P := SLV_TO_INT(addrp1(1 downto 0));
   end if;
--===============================================================================
--   Same Data Check for both Data and Parity 
--   If Data/Parity_Data are the same in Ports A and B, and the contents of the 
--   Memory/Parity_memory are the same as the Data, then here is no collision
--===============================================================================


   SameDataChk(
      same_data  => same_data,
      same_datap => same_datap,
      mem        => mem,
      di1        => di1,
      di2        => di2,
      dip1       => dip1,
      dip2       => dip2,
      addr1      => addr1,
      addr2      => addr2,
      addrp1     => addrp1,
      addrp2     => addrp2,
      wr_mode_1  => wr_mode_1,
      wr_mode_2  => wr_mode_2,
      we_segment => we_segment,
      we1        => we1,
      we2        => we2,
      D1W        => D1W,
      D1PW       => D1PW,
      D2W        => D2W,
      D2PW       => D2PW
    );

---===============================================================================
---===============================================================================
-- DEBUG                    
if(SAME_DATA_CHECK_DISABLED) then
  same_data  := false;
  same_datap := false;
end if;

  same_data_flg  := same_data;
  same_datap_flg := same_datap;
 
   TableRow := (wr_mode_1 & wr_mode_2 & we1 & we2);
   case TableRow is
---===============================================================================
---                           wea&web = 11
---===============================================================================
          ----
          when "000011" | "010011"  =>
          ----
            if((violation = 3) or (violation = 11)) then
                if(not same_data) then
                   -- port 1
                   clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                   clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                   -- port 2
                   clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                   clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                end if;
                if(not same_datap) then
                   -- parity port 1
                   if((D1PW /= 0) and (D2PW /= 0)) then
--                       clsn_bufs.DOP1_clsn((INDEX_P + (we_segment * 1))  downto (INDEX_P + (we_segment * 1))) := (others => 'X');
                       clsn_bufs.DOP1_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                       clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;
                   -- parity port 2
                   if((D1PW /= 0) and (D2PW /= 0)) then
--                       clsn_bufs.DOP2_clsn((INDEX_P + (we_segment * 1))  downto (INDEX_P + (we_segment * 1))) := (others => 'X');
                       clsn_bufs.DOP2_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                       clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;

            end if;

          ----
          when "001011" | "011011" =>
          ----
            if((violation = 3) or (violation = 11)) then
                if(not same_data) then
                   -- port 1
                   clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                   clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                   -- port 2
                   clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                end if;
                if(not same_datap) then
                   -- parity port 1
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.DOP1_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                       clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;

                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;
            end if;
          ----
          when "000111" | "010111"  =>
          ----
            if((violation = 3) or (violation = 11) or (violation = 12)) then
                if(not same_data) then
                   -- port 1
                   clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                   clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                   -- port 2
                   clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                   clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                end if;
                if(not same_datap) then
                   -- parity port 1
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.DOP1_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                       clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;
                   -- parity port 2
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.DOP2_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                       clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;
            end if;

          ----
          when "100011" =>
          ----
             if((violation = 3) or (violation = 11)) then
                if(not same_data) then
                   -- port 1
                   clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                   -- port 2
                   clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                   clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                end if;

                if(not same_datap) then
                   -- parity port 1
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;
                   -- parity port 2
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.DOP2_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                       clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;

             end if;

          ----
          when "100111" =>
          ----
             if((violation = 3) or (violation = 11) or (violation = 12) ) then
                if(not same_data) then
                   -- port 1
                   clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                   -- port 2
                   clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                   clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                end if;

                if(not same_datap) then
                   -- parity port 1
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;
                   -- parity port 2
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.DOP2_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                       clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;

             end if;
          ----
          when "101011" =>
          ----
             if((violation = 3) or (violation = 11)) then
                if(not same_data) then
                   -- port 1
                   clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                   -- port 2
                   clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                end if;
                if(not same_datap) then
                   if((D1PW /= 0) and (D2PW /= 0)) then
                        -- parity port 1
                       clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                        -- parity port 2
                       clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;
             end if;

---===============================================================================
---                           wea&web = 01
---===============================================================================
          ----
          when "000001" | "010001" | "100001"  =>
          ----
             if((violation = 3) or (violation = 11)) then
                if(not same_data) then
                   -- port 1
                   clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                end if;
                if(not same_datap) then
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.DOP1_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;
             end if;
          ----
          when "000101" | "010101" | "100101"  =>
          ----
             if((violation = 11)  or (violation = 12)) then
                if(not same_data) then
                   -- port 1
                   clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                end if;
                if(not same_datap) then
                   -- parity port 1
                   if((D1PW /= 0) and (D2PW /= 0)) then
                      clsn_bufs.DOP1_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;

             end if;
          ----
          when "001001" | "011001" | "101001"  =>
          ----
             if((violation = 3) or (violation = 11)) then
                if(not same_data) then
                   -- port 1
                   clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                end if;
                if(not same_datap) then
                   -- parity port 1
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.DOP1_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;
             end if;

---===============================================================================
---                           wea&web = 10
---===============================================================================

          ----
          when "000010" | "000110" | "001010"  =>
          ----
             if((violation = 3) or (violation = 11)) then
                if(not same_data) then
                   --  port 1
                   clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                end if;
                if(not same_datap) then
                   -- parity port 1
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.DOP2_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;
             end if;
          ----
          when "100010" | "100110" | "101010"  =>
          ----
             if((violation = 3) or (violation = 11)) then
                if(not same_data) then
                   --  port 1
                   clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                end if;
                if(not same_datap) then
                   -- parity port 1
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.DOP2_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;

             end if;

---===============================================================================
---                           others 
---===============================================================================

          ---------
          when others =>
          ---------
                null;
   end case;

   end CollisionTableRest;

------------------------------------------------
-- procedure PreProcessWe1We2
------------------------------------------------
--
--  Checks whether the time duration of rising
--  clka and clkb violates required setup time
--  between these clocks.
--
   procedure PreProcessWe1We2(
             variable clsn_bufs     : out ClsnXbufType;
             variable clsn_Type     : out CollisionFlagType;
             constant memory        : in std_logic_vector(18431 downto 0);
             constant di1           : in std_logic_vector(31 downto 0)   := (others => 'X');
             constant di2           : in std_logic_vector(31 downto 0)   := (others => 'X');
             constant dip1          : in std_logic_vector(3 downto 0)    := (others => 'X');
             constant dip2          : in std_logic_vector(3 downto 0)    := (others => 'X');
             variable addr1         : in std_logic_vector(13 downto 0)   := (others => 'X');
             variable addr2         : in std_logic_vector(13 downto 0)   := (others => 'X');
             variable we1           : in std_logic_vector(3 downto 0)    := (others => 'X');
             variable we2           : in std_logic_vector(3 downto 0)    := (others => 'X');
             variable zero_read_1   : in std_logic_vector(13 downto 0)   := (others => 'X');
             variable zero_readp_1  : in std_logic_vector(10 downto 0)   := (others => 'X');
             variable zero_write_1  : in std_logic_vector(13 downto 0)   := (others => 'X');
             variable zero_writep_1 : in std_logic_vector(10 downto 0)   := (others => 'X');
             variable zero_read_2   : in std_logic_vector(13 downto 0)   := (others => 'X');
             variable zero_readp_2  : in std_logic_vector(10 downto 0)   := (others => 'X');
             variable zero_write_2  : in std_logic_vector(13 downto 0)   := (others => 'X');
             variable zero_writep_2 : in std_logic_vector(10 downto 0)   := (others => 'X');
             variable wr_mode_1     : in std_logic_vector(1 downto 0)    := "00";
             variable wr_mode_2     : in std_logic_vector(1 downto 0)    := "00";
             constant violation     : in integer := -1;
             variable DI1W          : in integer := -1;
             variable DIP1W         : in integer := -1;
             variable DI2W          : in integer := -1;
             variable DIP2W         : in integer := -1;
             variable DO1W          : in integer := -1;
             variable DOP1W         : in integer := -1;
             variable DO2W          : in integer := -1;
             variable DOP2W         : in integer := -1
   ) is

   variable we1we2 : std_logic_vector(1 downto 0) := "XX";
   variable zero_addr1        : std_logic_vector(13 downto 0) := (others => 'X');
   variable zero_addr2        : std_logic_vector(13 downto 0) := (others => 'X');
   variable zero_parity_addr1 : std_logic_vector(10 downto 0) := (others => 'X');
   variable zero_parity_addr2 : std_logic_vector(10 downto 0) := (others => 'X');
   variable tmp_addr1_zero    : std_logic_vector(13 downto 0) := (others => 'X');
   variable tmp_addr2_zero    : std_logic_vector(13 downto 0) := (others => 'X');
   variable tmp_parity_addr1_zero    : std_logic_vector(10 downto 0) := (others => 'X');
   variable tmp_parity_addr2_zero    : std_logic_vector(10 downto 0) := (others => 'X');


   variable tmp_we1                  : std_ulogic := 'X';
   variable tmp_we2                  : std_ulogic := 'X';
   variable j                        : integer    := 0;

   variable same_data_flg            : boolean    := false;
   variable same_datap_flg           : boolean    := false;

   begin
      
      clsn_type.read_write  := false;
      clsn_type.write_read  := false;
      clsn_type.write_write := false;

      for i in  0 to 3 loop
         we1we2 := we1(i)&we2(i);
         clsn_type.we(i)  := '0';
         case we1we2 is
             ---------
             when "00" =>
             ---------
                null;
   
             ---------
             when "01" =>
             ---------
                same_data_flg  := false;
                same_datap_flg := false;

                zero_addr1 := zero_read_1;
                zero_addr2 := zero_write_2;
             
                zero_parity_addr1 := zero_readp_1;
                zero_parity_addr2 := zero_writep_2;

                tmp_we1 := '0';
                tmp_we2 := '1';

                if(AddrOverlapCheck(DO1W, DI2W, addr1, addr2, zero_addr1, zero_addr2,i)) then

                   tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_addr1);
                   tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_addr2);

                   tmp_parity_addr1_zero := addr1(13 downto 3) and zero_parity_addr1;
                   tmp_parity_addr2_zero := addr2(13 downto 3) and zero_parity_addr2;

-- FP fixed false message for DSP group 12/06/04

                      clsn_type.read_write := true;
                      clsn_type.we(i)  := '1';

                      if((wr_mode_2 = "01")) then
                        clsn_type.read_write := false;
                        clsn_type.we(i)  := '0';
                      end if;

	
                      CollisionTableRest(
                        same_data_flg  => same_data_flg,
                        same_datap_flg => same_datap_flg,
                        clsn_bufs      => clsn_bufs,
                        mem            => memory,
                        di1            => di1,
                        di2            => di2,
                        dip1           => dip1,
                        dip2           => dip2,
                        addr1          => tmp_addr1_zero,
                        addr2          => tmp_addr2_zero,
                        addrp1         => tmp_parity_addr1_zero,
                        addrp2         => tmp_parity_addr2_zero,
                        wr_mode_1      => wr_mode_1,
                        wr_mode_2      => wr_mode_2,
                        violation      => violation,
                        we_segment     => i,
                        we1            => tmp_we1,
                        we2            => tmp_we2,
                        D1W            => DO1W,
                        D1PW           => DOP1W,
                        D2W            => DI2W,
                        D2PW           => DIP2W
                      );
                end if;
             ---------
             when "10" =>
             ---------
                same_data_flg  := false;
                same_datap_flg := false;

                zero_addr1 := zero_write_1;
                zero_addr2 := zero_read_2;

                zero_parity_addr1 := zero_writep_1;
                zero_parity_addr2 := zero_readp_2;

                tmp_we1 := '1';
                tmp_we2 := '0';


                if(AddrOverlapCheck(DI1W, DO2W, addr1, addr2, zero_addr1, zero_addr2,i)) then

                   tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_addr1);
                   tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_addr2);

                   tmp_parity_addr1_zero := addr1(13 downto 3) and zero_parity_addr1;
                   tmp_parity_addr2_zero := addr2(13 downto 3) and zero_parity_addr2;

                      clsn_type.write_read := true;
                      clsn_type.we(i)  := '1';

-- FP fixed false message for DSP group 12/06/04
--                      if((violation = 12) or (wr_mode_1 = "01")) then
                      if((wr_mode_1 = "01")) then
                        clsn_type.write_read := false;
                        clsn_type.we(i)  := '0';
                      end if; 

                      CollisionTableRest(
                        same_data_flg  => same_data_flg,
                        same_datap_flg => same_datap_flg,
                        clsn_bufs      => clsn_bufs,
                        mem            => memory,
                        di1            => di1,
                        di2            => di2,
                        dip1           => dip1,
                        dip2           => dip2,
                        addr1          => tmp_addr1_zero,
                        addr2          => tmp_addr2_zero,
                        addrp1         => tmp_parity_addr1_zero,
                        addrp2         => tmp_parity_addr2_zero,
                        wr_mode_1      => wr_mode_1,
                        wr_mode_2      => wr_mode_2,
                        violation      => violation,
                        we_segment     => i,
                        we1            => tmp_we1,
                        we2            => tmp_we2,
                        D1W            => DI1W,
                        D1PW           => DIP1W,
                        D2W            => DO2W,
                        D2PW           => DOP2W
                      );
                end if;
             ---------
             when "11" =>
             ---------
                same_data_flg  := false;
                same_datap_flg := false;

                zero_addr1 := zero_write_1;
                zero_addr2 := zero_write_2;

                zero_parity_addr1 := zero_writep_1;
                zero_parity_addr2 := zero_writep_2;

                tmp_we1 := '1';
                tmp_we2 := '1';

                if(AddrOverlapCheck(DI1W, DI2W, addr1, addr2, zero_addr1, zero_addr2,i)) then

                   tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_addr1);
                   tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_addr2);

                   tmp_parity_addr1_zero := addr1(13 downto 3) and zero_parity_addr1;
                   tmp_parity_addr2_zero := addr2(13 downto 3) and zero_parity_addr2;

                      if(violation = 12) then
                         if(wr_mode_2 = "01") then
                            clsn_type.write_write := true;
                            clsn_type.we(i)  := '1';
                         end if; 
                      else 
                         clsn_type.write_write := true;
                         clsn_type.we(i)  := '1';
                      end if;

                      CollisionTableRest(
                        same_data_flg  => same_data_flg,
                        same_datap_flg => same_datap_flg,
                        clsn_bufs      => clsn_bufs,
                        mem            => memory,
                        di1            => di1,
                        di2            => di2,
                        dip1           => dip1,
                        dip2           => dip2,
                        addr1          => tmp_addr1_zero,
                        addr2          => tmp_addr2_zero,
                        addrp1         => tmp_parity_addr1_zero,
                        addrp2         => tmp_parity_addr2_zero,
                        wr_mode_1      => wr_mode_1,
                        wr_mode_2      => wr_mode_2,
                        violation      => violation,
                        we_segment     => i,
                        we1            => tmp_we1,
                        we2            => tmp_we2,
                        D1W            => DI1W,
                        D1PW           => DIP1W,
                        D2W            => DI2W,
                        D2PW           => DIP2W
                      );
                end if;

                if((DI1W /= DO1W) or (DI2W /= DO2W)) then
--FP disabled the cross check call
--                   tmp_we1 := '1';
--                   tmp_we2 := '0';
                   tmp_we1 := '0';
                   tmp_we2 := '0';

                   zero_addr1 := zero_write_1;
                   zero_addr2 := zero_read_2;

                   zero_parity_addr1 := zero_writep_1;
                   zero_parity_addr2 := zero_readp_2;

                   if(AddrOverlapCheck(DI1W, DO2W, addr1, addr2, zero_addr1, zero_addr2,i)) then

                      tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_addr1);
                      tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_addr2);

                      tmp_parity_addr1_zero := addr1(13 downto 3) and zero_parity_addr1;
                      tmp_parity_addr2_zero := addr2(13 downto 3) and zero_parity_addr2;

                      CollisionTableRest(
                        same_data_flg  => same_data_flg,
                        same_datap_flg => same_datap_flg,
                        clsn_bufs      => clsn_bufs,
                        mem            => memory,
                        di1            => di1,
                        di2            => di2,
                        dip1           => dip1,
                        dip2           => dip2,
                        addr1          => tmp_addr1_zero,
                        addr2          => tmp_addr2_zero,
                        addrp1         => tmp_parity_addr1_zero,
                        addrp2         => tmp_parity_addr2_zero,
                        wr_mode_1      => wr_mode_1,
                        wr_mode_2      => wr_mode_2,
                        violation      => violation,
                        we_segment     => i,
                        we1            => tmp_we1,
                        we2            => tmp_we2,
                        D1W            => DI1W,
                        D1PW           => DIP1W,
                        D2W            => DO2W,
                        D2PW           => DOP2W
                      );
                   end if;

--FP disabled the cross check call
--                   tmp_we1 := '0';
--                   tmp_we2 := '1';
                   tmp_we1 := '0';
                   tmp_we2 := '0';

                   zero_addr1 := zero_read_1;
                   zero_addr2 := zero_write_2;

                   zero_parity_addr1 := zero_readp_1;
                   zero_parity_addr2 := zero_writep_2;

                   if(AddrOverlapCheck(DO1W, DI2W, addr1, addr2, zero_addr1, zero_addr2,i)) then

                      tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_addr1);
                      tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_addr2);

                      tmp_parity_addr1_zero := addr1(13 downto 3) and zero_parity_addr1;
                      tmp_parity_addr2_zero := addr2(13 downto 3) and zero_parity_addr2;

                      CollisionTableRest(
                        same_data_flg  => same_data_flg,
                        same_datap_flg => same_datap_flg,
                        clsn_bufs      => clsn_bufs,
                        mem            => memory,
                        di1            => di1,
                        di2            => di2,
                        dip1           => dip1,
                        dip2           => dip2,
                        addr1          => tmp_addr1_zero,
                        addr2          => tmp_addr2_zero,
                        addrp1         => tmp_parity_addr1_zero,
                        addrp2         => tmp_parity_addr2_zero,
                        wr_mode_1      => wr_mode_1,
                        wr_mode_2      => wr_mode_2,
                        violation      => violation,
                        we_segment     => i,
                        we1            => tmp_we1,
                        we2            => tmp_we2,
                        D1W            => DO1W,
                        D1PW           => DOP1W,
                        D2W            => DI2W,
                        D2PW           => DIP2W
                      );

                   end if;
                end if;
  
             when others =>
                null;

         end case;

      end loop;

   end PreProcessWe1We2;
------------------------------------------------
-- procedure Memory_Collision_Msg_ramb16
------------------------------------------------
-- This is almost the same procedure as the procedure for V2 ram collision 
-- except that is is local to the model (since this is the only one that 
-- calls this procedure
  Procedure Memory_Collision_Msg_ramb16 (
    CONSTANT HeaderMsg      : IN STRING := " Memory Collision Error on ";        
    CONSTANT EntityName : IN STRING := "";
    CONSTANT InstanceName : IN STRING := "";
    constant collision_type : in memory_collision_type;
    constant address_1 : in std_logic_vector; 
    constant address_2 : in std_logic_vector; 
    CONSTANT MsgSeverity    : IN SEVERITY_LEVEL := Error
    
    
    ) IS
    variable current_time : time := NOW;
    variable string_length_1 : integer;
    variable string_length_2 : integer;    

    VARIABLE Message : LINE;
  BEGIN
    if ((address_1'length mod 4) = 0) then
      string_length_1 := address_1'length/4;
    elsif ((address_1'length mod 4) > 0) then
      string_length_1 := address_1'length/4 + 1;      
    end if;
    if ((address_2'length mod 4) = 0) then
      string_length_2 := address_2'length/4;
    elsif ((address_2'length mod 4) > 0) then
      string_length_2 := address_2'length/4 + 1;      
    end if;    
--    if ((collision_type = Read_A_Write_B) or (collision_type = Read_B_Write_A)) then
    if ((collision_type = Read_A_Write_B) or (collision_type = Write_A_Read_B) or
        (collision_type = Read_B_Write_A) or (collision_type = Write_B_Read_A)) then
      Write ( Message, HeaderMsg);
      Write ( Message, EntityName);    
      Write ( Message, STRING'(": "));
      Write ( Message, InstanceName);
      Write ( Message, STRING'(" at simulation time "));
      Write ( Message, current_time);
      Write ( Message, STRING'("."));
      Write ( Message, LF );            
      Write ( Message, STRING'(" A read was performed on address "));
      Write ( Message, SLV_TO_HEX(address_1, string_length_1));
      Write ( Message, STRING'(" (hex) "));            
--      if (collision_type = Read_A_Write_B) then
      if ((collision_type = Read_A_Write_B) or (collision_type = Write_B_Read_A))then
         Write ( Message, STRING'("of port A while a write was requested to the same address on Port B "));
         Write ( Message, STRING'(" The write will be successful however the read value is unknown until the next CLKA cycle  "));
--      elsif(collision_type = Read_B_Write_A) then
      elsif((collision_type = Read_B_Write_A) or (collision_type = Write_A_Read_B)) then
         Write ( Message, STRING'("of port B while a write was requested to the same address on Port A "));
         Write ( Message, STRING'(" The write will be successful however the read value is unknown until the next CLKB cycle  "));
      end if;
    elsif ((collision_type = Write_A_Write_B) or (collision_type = Write_B_Write_A)) then
      Write ( Message, HeaderMsg);
      Write ( Message, EntityName);    
      Write ( Message, STRING'(": "));
      Write ( Message, InstanceName);
      Write ( Message, STRING'(" at simulation time "));
      Write ( Message, current_time);
      Write ( Message, STRING'("."));
      Write ( Message, LF );            
      Write ( Message, STRING'(" A write was requested to the same address simultaneously at both Port A and Port B of the RAM."));
      Write ( Message, STRING'(" The contents written to the RAM at address location "));      
      Write ( Message, SLV_TO_HEX(address_1, string_length_1));
      Write ( Message, STRING'(" (hex) "));            
      Write ( Message, STRING'("of Port A and address location "));
      Write ( Message, SLV_TO_HEX(address_2, string_length_2));
      Write ( Message, STRING'(" (hex) "));            
      Write ( Message, STRING'("of Port B are unknown. "));
    end if;      
    ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;

    DEALLOCATE (Message);
  END Memory_Collision_Msg_ramb16;      

------------------ END Procedures/Functions ------------------------------

  signal ADDRA_ipd    : std_logic_vector(MAX_ADDR downto 0) := (others => 'X');
  signal CLKA_ipd     : std_ulogic                          := 'X';
  signal DIA_ipd      : std_logic_vector(MAX_DI  downto 0)  := (others => 'X');
  signal DIPA_ipd     : std_logic_vector(MAX_DIP downto 0)  := (others => 'X');
  signal ENA_ipd      : std_ulogic                          := 'X';
  signal SSRA_ipd     : std_ulogic                          := 'X';
  signal WEA_ipd      : std_logic_vector(MAX_WE downto 0)   := (others => 'X');

  signal ADDRB_ipd    : std_logic_vector(MAX_ADDR downto 0) := (others => 'X');
  signal CLKB_ipd     : std_ulogic                          := 'X';
  signal DIB_ipd      : std_logic_vector(MAX_DI  downto 0)  := (others => 'X');
  signal DIPB_ipd     : std_logic_vector(MAX_DIP downto 0)  := (others => 'X');
  signal ENB_ipd      : std_ulogic                          := 'X';
  signal SSRB_ipd     : std_ulogic                          := 'X';
  signal WEB_ipd      : std_logic_vector(MAX_WE downto 0)   := (others => 'X');

  signal GSR          : std_ulogic := '0';
  signal GSR_ipd      : std_ulogic                          := 'X';

  signal GSR_dly      : std_ulogic                          := 'X';

  signal ADDRA_dly    : std_logic_vector(MAX_ADDR downto 0) := (others => 'X');
  signal CLKA_dly     : std_ulogic                          := 'X';
  signal DIA_dly      : std_logic_vector(MAX_DI downto 0) := (others => 'X');
  signal DIPA_dly     : std_logic_vector(MAX_DIP downto 0)  := (others => 'X');
  signal ENA_dly      : std_ulogic                          := 'X';
  signal GSR_CLKA_dly : std_ulogic                          := 'X';
  signal SSRA_dly     : std_ulogic                          := 'X';
  signal WEA_dly      : std_logic_vector(MAX_WE downto 0)   := (others => 'X');

  signal ADDRB_dly    : std_logic_vector(MAX_ADDR downto 0) := (others => 'X');
  signal CLKB_dly     : std_ulogic                          := 'X';
  signal DIB_dly      : std_logic_vector(MAX_DI downto 0) := (others => 'X');
  signal DIPB_dly     : std_logic_vector(MAX_DIP downto 0)  := (others => 'X');
  signal ENB_dly      : std_ulogic                          := 'X';
  signal GSR_CLKB_dly : std_ulogic                          := 'X';
  signal SSRB_dly     : std_ulogic                          := 'X';
  signal WEB_dly      : std_logic_vector(MAX_WE downto 0)   := (others => 'X');

  signal DOA_viol     : std_logic_vector(MAX_DI downto 0);
  signal DOPA_viol    : std_logic_vector(3 downto 0);
  signal DOB_viol     : std_logic_vector(MAX_DI downto 0);
  signal DOPB_viol    : std_logic_vector(3 downto 0);

  signal DIAW              : integer;
  signal DIAW_1            : integer;
  signal DIBW              : integer;
  signal DIBW_1            : integer;
  signal DIPAW             : integer;
  signal DIPAW_1           : integer;
  signal DIPBW             : integer;
  signal DIPBW_1           : integer;

  signal DOAW              : integer;
  signal DOAW_1            : integer;
  signal DOBW              : integer;
  signal DOBW_1            : integer;
  signal DOPAW             : integer;
  signal DOPAW_1           : integer;
  signal DOPBW             : integer;
  signal DOPBW_1           : integer;

  signal INI_A_sig         : std_logic_vector (35 downto 0) :=  (others => 'X');
  signal INI_B_sig         : std_logic_vector (35 downto 0) :=  (others => 'X');

  signal SRVA_A_sig         : std_logic_vector (35 downto 0) :=  (others => 'X');
  signal SRVA_B_sig         : std_logic_vector (35 downto 0) :=  (others => 'X');

begin
  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  ADDRA_dly      	 <= ADDRA          	after 0 ps;
  ADDRB_dly      	 <= ADDRB          	after 0 ps;
  CLKA_dly       	 <= CLKA           	after 0 ps;
  CLKB_dly       	 <= CLKB           	after 0 ps;
  DIA_dly        	 <= DIA            	after 0 ps;
  DIB_dly        	 <= DIB            	after 0 ps;
  DIPA_dly       	 <= DIPA           	after 0 ps;
  DIPB_dly       	 <= DIPB           	after 0 ps;
  ENA_dly        	 <= ENA            	after 0 ps;
  ENB_dly        	 <= ENB            	after 0 ps;
  GSR_dly        	 <= GSR            	after 0 ps;
  SSRA_dly       	 <= SSRA           	after 0 ps;
  SSRB_dly       	 <= SSRB           	after 0 ps;
  WEA_dly        	 <= WEA            	after 0 ps;
  WEB_dly        	 <= WEB            	after 0 ps;
  GSR_CLKA_dly           <= GSR                 after 0 ps;
  GSR_CLKB_dly           <= GSR                 after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

   prcs_initialize:process
    variable INI_A         : std_logic_vector (35 downto 0) :=  (others => 'X');
    variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B         : std_logic_vector (35 downto 0) :=  (others => 'X');
    variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0);

    variable SRVA_A            : std_logic_vector (35 downto 0) :=  (others => 'X');
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (35 downto 0) :=  (others => 'X');
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);

    variable DIAW_var              : integer;
    variable DIAW_1_var            : integer;
    variable DIBW_var              : integer;
    variable DIBW_1_var            : integer;
    variable DIPAW_var             : integer;
    variable DIPAW_1_var           : integer;
    variable DIPBW_var             : integer;
    variable DIPBW_1_var           : integer;

    variable DOAW_var              : integer;
    variable DOAW_1_var            : integer;
    variable DOBW_var              : integer;
    variable DOBW_1_var            : integer;
    variable DOPAW_var             : integer;
    variable DOPAW_1_var           : integer;
    variable DOPBW_var             : integer;
    variable DOPBW_1_var           : integer;

   begin
      DIPAW_var   := 0;
      DIPAW_1_var := -1;
      DIPBW_var   := 0;
      DIPBW_1_var := -1;

      DOPAW_var   := 0;
      DOPAW_1_var := -1;
      DOPBW_var   := 0;
      DOPBW_1_var := -1;

     
--------------------------------------------------------------------
--    Additional Checks Added Later
--------------------------------------------------------------------
      if((DATA_WIDTH_A = 0) and (DATA_WIDTH_B = 0 )) then
        assert false
        report "Attribute Syntax Error: Both DATA_WIDTH_A and DATA_WIDTH_B can not be 0."
        severity Failure;
      end if;

      case DATA_WIDTH_A is

            when 0 =>
                 DOAW_var    := 1;
                 DOAW_1_var  := DOAW_var -1;
                 DIAW_var    := 1;
                 DIAW_1_var  := DIAW_var -1;

            when 1 =>
                 DOAW_var    := 1;
                 DOAW_1_var  := DOAW_var -1;
                 DIAW_var    := 1;
                 DIAW_1_var  := DIAW_var -1;

            when 2 =>
                 DOAW_var    := 2;
                 DOAW_1_var  := DOAW_var -1;
                 DIAW_var    := 2;
                 DIAW_1_var  := DIAW_var -1;

            when 4 =>
                 DOAW_var    := 4;
                 DOAW_1_var  := DOAW_var -1;
                 DIAW_var    := 4;
                 DIAW_1_var  := DIAW_var -1;

            when 9 =>
                 DOAW_var    := 8;
                 DOAW_1_var  := DOAW_var -1;
                 DOPAW_var   := 1;
                 DOPAW_1_var := DOPAW_var -1;
                 DIAW_var    := 8;
                 DIAW_1_var  := DIAW_var -1;
                 DIPAW_var   := 1;
                 DIPAW_1_var := DIPAW_var -1;

            when 18  =>
                 DOAW_var    := 16;
                 DOAW_1_var  := DOAW_var -1;
                 DOPAW_var   := 2;
                 DOPAW_1_var := DOPAW_var -1;
                 DIAW_var    := 16;
                 DIAW_1_var  := DIAW_var -1;
                 DIPAW_var   := 2;
                 DIPAW_1_var := DIPAW_var -1;

            when 36  =>
                 DOAW_var    := 32;
                 DOAW_1_var  := DOAW_var -1;
                 DOPAW_var   := 4;
                 DOPAW_1_var := DOPAW_var -1;
                 DIAW_var    := 32;
                 DIAW_1_var  := DIAW_var -1;
                 DIPAW_var   := 4;
                 DIPAW_1_var := DIPAW_var -1;

            when others =>
                 GenericValueCheckMessage
                 (  HeaderMsg            => " Attribute Syntax Error : ",
                    GenericName          => " DATA_WIDTH_A ",
                    EntityName           => "/RAMB16BWE",
                    GenericValue         => DATA_WIDTH_A,
                    Unit                 => "",
                    ExpectedValueMsg     => " The Legal values for this attribute are ",
                    ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.",
                    TailMsg              => "",
                    MsgSeverity          => failure
                 );
      end case;


      case DATA_WIDTH_B is

            when 0 =>
                 DOBW_var    := 1;
                 DOBW_1_var  := DOBW_var -1;
                 DIBW_var    := 1;
                 DIBW_1_var  := DIBW_var -1;

            when 1 =>
                 DOBW_var    := 1;
                 DOBW_1_var  := DOBW_var -1;
                 DIBW_var    := 1;
                 DIBW_1_var  := DIBW_var -1;

            when 2 =>
                 DOBW_var    := 2;
                 DOBW_1_var  := DOBW_var -1;
                 DIBW_var    := 2;
                 DIBW_1_var  := DIBW_var -1;

            when 4 =>
                 DOBW_var    := 4;
                 DOBW_1_var  := DOBW_var -1;
                 DIBW_var    := 4;
                 DIBW_1_var  := DIBW_var -1;

            when 9 =>
                 DOBW_var    := 8;
                 DOBW_1_var  := DOBW_var -1;
                 DOPBW_var   := 1;
                 DOPBW_1_var := DOPBW_var -1;
                 DIBW_var    := 8;
                 DIBW_1_var  := DIBW_var -1;
                 DIPBW_var   := 1;
                 DIPBW_1_var := DIPBW_var -1;

            when 18  =>
                 DOBW_var    := 16;
                 DOBW_1_var  := DOBW_var -1;
                 DOPBW_var   := 2;
                 DOPBW_1_var := DOPBW_var -1;
                 DIBW_var    := 16;
                 DIBW_1_var  := DIBW_var -1;
                 DIPBW_var   := 2;
                 DIPBW_1_var := DIPBW_var -1;

            when 36  =>
                 DOBW_var    := 32;
                 DOBW_1_var  := DOBW_var -1;
                 DOPBW_var   := 4;
                 DOPBW_1_var := DOPBW_var -1;
                 DIBW_var    := 32;
                 DIBW_1_var  := DIBW_var -1;
                 DIPBW_var   := 4;
                 DIPBW_1_var := DIPBW_var -1;

            when others =>
                 GenericValueCheckMessage
                 (  HeaderMsg            => " Attribute Syntax Error : ",
                    GenericName          => " DATA_WIDTH_B ",
                    EntityName           => "/RAMB16BWE",
                    GenericValue         => DATA_WIDTH_B,
                    Unit                 => "",
                    ExpectedValueMsg     => " The Legal values for this attribute are ",
                    ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.",
                    TailMsg              => "",
                    MsgSeverity          => failure
                 );
                 null;

      end case;


      if (INIT_A'length > 36) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A );
        INI_A(35 downto 0)                      := INI_A_UNBOUND(35 downto 0);
      elsif (INIT_A'length < 36) then
        INI_A(INIT_A'length-1 downto 0)         := To_StdLogicVector(INIT_A );
      elsif (INIT_A'length = 36) then
        INI_A(INIT_A'length-1 downto 0)         := To_StdLogicVector(INIT_A );
      end if;

      if (INIT_B'length > 36) then
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B );
        INI_B(35 downto 0)                      := INI_B_UNBOUND(35 downto 0);
      elsif (INIT_B'length < 36) then
        INI_B(INIT_B'length-1 downto 0)         := To_StdLogicVector(INIT_B );
      elsif (INIT_B'length = 36) then
        INI_B(INIT_B'length-1 downto 0)         := To_StdLogicVector(INIT_B );
      end if;

      if (SRVAL_A'length > 36) then
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A );
        SRVA_A(35 downto 0)                       := SRVA_A_UNBOUND(35 downto 0);
      elsif (SRVAL_A'length < 36) then
        SRVA_A(SRVAL_A'length-1 downto 0)         := To_StdLogicVector(SRVAL_A );
      elsif (SRVAL_A'length = 36) then
        SRVA_A(SRVAL_A'length-1 downto 0)         := To_StdLogicVector(SRVAL_A );
      end if;

      if (SRVAL_B'length > 36) then
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B );
        SRVA_B(35 downto 0)                       := SRVA_B_UNBOUND(35 downto 0);
      elsif (SRVAL_B'length < 36) then
        SRVA_B(SRVAL_B'length-1 downto 0)         := To_StdLogicVector(SRVAL_B );
      elsif (SRVAL_B'length = 36) then
        SRVA_B(SRVAL_B'length-1 downto 0)         := To_StdLogicVector(SRVAL_B );
      end if;

      DIAW     <= DIAW_var;
      DIAW_1   <= DIAW_1_var;
      DIBW     <= DIBW_var;
      DIBW_1   <= DIBW_1_var;
      DIPAW    <= DIPAW_var;
      DIPAW_1  <= DIPAW_1_var;
      DIPBW    <= DIPBW_var;
      DIPBW_1  <= DIPBW_1_var;

      DOAW     <= DOAW_var;
      DOAW_1   <= DOAW_1_var;
      DOBW     <= DOBW_var;
      DOBW_1   <= DOBW_1_var;
      DOPAW    <= DOPAW_var;
      DOPAW_1  <= DOPAW_1_var;
      DOPBW    <= DOPBW_var;
      DOPBW_1  <= DOPBW_1_var;

      SRVA_A_sig <= SRVA_A;
      SRVA_B_sig <= SRVA_B;
      INI_A_sig  <= INI_A;
      INI_B_sig  <= INI_B;

      wait;
  end process prcs_initialize;
---------------------------------------------------------------------------------------
  VITALBehavior                         : process

    variable MEM : std_logic_vector(18431 downto 0) := To_StdLogicVector(INITP_07) &
                                                       To_StdLogicVector(INITP_06) &
                                                       To_StdLogicVector(INITP_05) &
                                                       To_StdLogicVector(INITP_04) &
                                                       To_StdLogicVector(INITP_03) &
                                                       To_StdLogicVector(INITP_02) &
                                                       To_StdLogicVector(INITP_01) &
                                                       To_StdLogicVector(INITP_00) & 

                                                       To_StdLogicVector(INIT_3F)  &
                                                       To_StdLogicVector(INIT_3E)  &
                                                       To_StdLogicVector(INIT_3D)  &
                                                       To_StdLogicVector(INIT_3C)  &
                                                       To_StdLogicVector(INIT_3B)  &
                                                       To_StdLogicVector(INIT_3A)  &
                                                       To_StdLogicVector(INIT_39)  &
                                                       To_StdLogicVector(INIT_38)  &
                                                       To_StdLogicVector(INIT_37)  &
                                                       To_StdLogicVector(INIT_36)  &
                                                       To_StdLogicVector(INIT_35)  &
                                                       To_StdLogicVector(INIT_34)  &
                                                       To_StdLogicVector(INIT_33)  &
                                                       To_StdLogicVector(INIT_32)  &
                                                       To_StdLogicVector(INIT_31)  &
                                                       To_StdLogicVector(INIT_30)  &
                                                       To_StdLogicVector(INIT_2F)  &
                                                       To_StdLogicVector(INIT_2E)  &
                                                       To_StdLogicVector(INIT_2D)  &
                                                       To_StdLogicVector(INIT_2C)  &
                                                       To_StdLogicVector(INIT_2B)  &
                                                       To_StdLogicVector(INIT_2A)  &
                                                       To_StdLogicVector(INIT_29)  &
                                                       To_StdLogicVector(INIT_28)  &
                                                       To_StdLogicVector(INIT_27)  &
                                                       To_StdLogicVector(INIT_26)  &
                                                       To_StdLogicVector(INIT_25)  &
                                                       To_StdLogicVector(INIT_24)  &
                                                       To_StdLogicVector(INIT_23)  &
                                                       To_StdLogicVector(INIT_22)  &
                                                       To_StdLogicVector(INIT_21)  &
                                                       To_StdLogicVector(INIT_20)  &
                                                       To_StdLogicVector(INIT_1F)  &
                                                       To_StdLogicVector(INIT_1E)  &
                                                       To_StdLogicVector(INIT_1D)  &
                                                       To_StdLogicVector(INIT_1C)  &
                                                       To_StdLogicVector(INIT_1B)  &
                                                       To_StdLogicVector(INIT_1A)  &
                                                       To_StdLogicVector(INIT_19)  &
                                                       To_StdLogicVector(INIT_18)  &
                                                       To_StdLogicVector(INIT_17)  &
                                                       To_StdLogicVector(INIT_16)  &
                                                       To_StdLogicVector(INIT_15)  &
                                                       To_StdLogicVector(INIT_14)  &
                                                       To_StdLogicVector(INIT_13)  &
                                                       To_StdLogicVector(INIT_12)  &
                                                       To_StdLogicVector(INIT_11)  &
                                                       To_StdLogicVector(INIT_10)  &
                                                       To_StdLogicVector(INIT_0F)  &
                                                       To_StdLogicVector(INIT_0E)  &
                                                       To_StdLogicVector(INIT_0D)  &
                                                       To_StdLogicVector(INIT_0C)  &
                                                       To_StdLogicVector(INIT_0B)  &
                                                       To_StdLogicVector(INIT_0A)  &
                                                       To_StdLogicVector(INIT_09)  &
                                                       To_StdLogicVector(INIT_08)  &
                                                       To_StdLogicVector(INIT_07)  &
                                                       To_StdLogicVector(INIT_06)  &
                                                       To_StdLogicVector(INIT_05)  &
                                                       To_StdLogicVector(INIT_04)  &
                                                       To_StdLogicVector(INIT_03)  &
                                                       To_StdLogicVector(INIT_02)  &
                                                       To_StdLogicVector(INIT_01)  &
                                                       To_StdLogicVector(INIT_00) ;
 
    variable INI_A         : std_logic_vector (35 downto 0) := (others => 'X');
    variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B         : std_logic_vector (35 downto 0) := (others => 'X');
    variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0);

    variable DIAW              : integer;
    variable DIAW_1            : integer;
    variable DIBW              : integer;
    variable DIBW_1            : integer;
    variable DIPAW             : integer;
    variable DIPAW_1           : integer;
    variable DIPBW             : integer;
    variable DIPBW_1           : integer;

    variable DOAW              : integer;
    variable DOAW_1            : integer;
    variable DOBW              : integer;
    variable DOBW_1            : integer;
    variable DOPAW             : integer;
    variable DOPAW_1           : integer;
    variable DOPBW             : integer;
    variable DOPBW_1           : integer;

    variable ADDRA_dly_sampled : std_logic_vector(MAX_ADDR downto 0)   := (others => 'X');
    variable ADDRB_dly_sampled : std_logic_vector(MAX_ADDR downto 0)   := (others => 'X');
    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;

    variable ADDRESS_READ_A, ADDRESS_WRITE_A, ADDRESS_READ_B, ADDRESS_WRITE_B : integer;
    variable ADDRESS_PARITY_READ_A, ADDRESS_PARITY_WRITE_A, ADDRESS_PARITY_READ_B, ADDRESS_PARITY_WRITE_B : integer;

    variable DOA_INDEX, DOPA_INDEX : integer := -1;
    variable DOB_INDEX, DOPB_INDEX : integer := -1;

    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOA_zd            : std_logic_vector(MAX_DI downto 0)  := INI_A(MAX_DI downto 0);
    variable DOA_zd_buf        : std_logic_vector(MAX_DI downto 0)  := INI_A(MAX_DI downto 0);
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable DOB_zd            : std_logic_vector(MAX_DI downto 0)  := INI_B(MAX_DI downto 0);
    variable DOB_zd_buf        : std_logic_vector(MAX_DI downto 0)  := INI_B(MAX_DI downto 0);
    variable DOPA_OV_LSB       : integer;
    variable DOPA_OV_MSB       : integer;
    variable DOPA_zd           : std_logic_vector(3 downto 0)   := INI_A(35 downto 32);
    variable DOPA_zd_buf       : std_logic_vector(3 downto 0)   := INI_A(35 downto 32);
    variable DOPB_OV_LSB       : integer;
    variable DOPB_OV_MSB       : integer;
    variable DOPB_zd           : std_logic_vector(3 downto 0)   := INI_B(35 downto 32);
    variable DOPB_zd_buf       : std_logic_vector(3 downto 0)   := INI_B(35 downto 32);
    variable ENA_dly_sampled   : std_ulogic                      := 'X';
    variable ENB_dly_sampled   : std_ulogic                      := 'X';
    variable FIRST_TIME        : boolean                        := true;
    variable HAS_OVERLAP       : boolean                        := false;
    variable HAS_OVERLAP_P     : boolean                        := false;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVA_A            : std_logic_vector (35 downto 0) := (others => 'X');
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (35 downto 0) := (others => 'X');
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable SSRA_dly_sampled  : std_ulogic                      := 'X';
    variable SSRB_dly_sampled  : std_ulogic                      := 'X';
    variable VALID_ADDRA       : boolean                        := true;
    variable VALID_ADDRB       : boolean                        := true;
    variable ViolationA        : std_ulogic                     := '0';
    variable ViolationB        : std_ulogic                     := '0';
    variable ViolationCLKAB    : std_ulogic                     := '0';
    variable ViolationCLKAB_S0 : boolean                        := false;
    variable Violation_S1      : boolean                        := false;
    variable Violation_S3      : boolean                        := false;
    variable WEA_dly_sampled   : std_logic_vector(MAX_WE downto 0) := (others => 'X');
    variable WEB_dly_sampled   : std_logic_vector(MAX_WE downto 0) := (others => 'X');
    variable wr_mode_a         : std_logic_vector(1 downto 0)   := "00";
    variable wr_mode_b         : std_logic_vector(1 downto 0)   := "00";

--FP
    variable wea_index          : integer                       := -1;
    variable web_index          : integer                       := -1;

    variable tmp_we                  : std_logic_vector(1 downto 0)             := (others => '1');
    variable xout_we_seg1            : std_logic_vector(1 downto 0)             := (others => '0');
    variable xout_we_seg2            : std_logic_vector(1 downto 0)             := (others => '0');

    variable tmp_zero_write_a        : std_logic_vector(MAX_ADDR downto 0)      := (others => '1');
    variable tmp_zero_read_a         : std_logic_vector(MAX_ADDR downto 0)      := (others => '1');
    variable tmp_zero_parity_write_a : std_logic_vector((MAX_ADDR-3) downto 0)  := (others => '0');
    variable tmp_zero_parity_read_a  : std_logic_vector((MAX_ADDR-3) downto 0)  := (others => '0');

    variable tmp_zero_write_b        : std_logic_vector(MAX_ADDR downto 0)      := (others => '1');
    variable tmp_zero_read_b         : std_logic_vector(MAX_ADDR downto 0)      := (others => '1');
    variable tmp_zero_parity_write_b : std_logic_vector((MAX_ADDR-3) downto 0)  := (others => '0');
    variable tmp_zero_parity_read_b  : std_logic_vector((MAX_ADDR-3) downto 0)  := (others => '0');

    variable zero_write_a        : std_logic_vector(MAX_ADDR downto 0)      := (others => '1');
    variable zero_read_a         : std_logic_vector(MAX_ADDR downto 0)      := (others => '1');
    variable zero_parity_write_a : std_logic_vector((MAX_ADDR-3) downto 0)  := (others => '1');
    variable zero_parity_read_a  : std_logic_vector((MAX_ADDR-3) downto 0)  := (others => '1');

    variable zero_write_b        : std_logic_vector(MAX_ADDR downto 0)      := (others => '1');
    variable zero_read_b         : std_logic_vector(MAX_ADDR downto 0)      := (others => '1');
    variable zero_parity_write_b : std_logic_vector((MAX_ADDR-3) downto 0)  := (others => '1');
    variable zero_parity_read_b  : std_logic_vector((MAX_ADDR-3) downto 0)  := (others => '1');


    variable addra_in_14 : std_ulogic := '0';
    variable addrb_in_14 : std_ulogic := '0';

    variable SimCollisionCheck_var : integer := 3;
    variable collision_clka_clkb   : integer := 0;
    variable addr_overlap          : boolean := false;

    variable CLKA_time             : time := 0 ps;
    variable CLKB_time             : time := 0 ps;

    variable DOA_clsn              : std_logic_vector(31 downto 0) := (others => '0');
    variable DOPA_clsn             : std_logic_vector(3 downto 0) := (others => '0');
    variable DOA_clsn_sav          : std_logic_vector(31 downto 0) := (others => '0');
    variable DOPA_clsn_sav         : std_logic_vector(3 downto 0) := (others => '0');
    variable DOA_clsn_zero         : std_logic_vector(31 downto 0) := (others => '0');
    variable DOPA_clsn_zero        : std_logic_vector(3 downto 0) := (others => '0');

    variable DOB_clsn              : std_logic_vector(31 downto 0) := (others => '0');
    variable DOPB_clsn             : std_logic_vector(3 downto 0) := (others => '0');
    variable DOB_clsn_sav          : std_logic_vector(31 downto 0) := (others => '0');
    variable DOPB_clsn_sav         : std_logic_vector(3 downto 0) := (others => '0');
    variable DOB_clsn_zero         : std_logic_vector(31 downto 0) := (others => '0');
    variable DOPB_clsn_zero        : std_logic_vector(3 downto 0) := (others => '0');

    variable DOA_clsn_slice        : std_logic_vector(31 downto 0) := (others => '0');
    variable DOPA_clsn_slice       : std_logic_vector(3 downto 0) := (others => '0');
    variable DOB_clsn_slice        : std_logic_vector(31 downto 0) := (others => '0');
    variable DOPB_clsn_slice       : std_logic_vector(3 downto 0) := (others => '0');

    variable tmp_membuf            : std_logic_vector(31 downto 0) := (others => '0');

    variable DOA_clsn_read_index, DOPA_clsn_read_index : integer := -1;
    variable DOB_clsn_read_index, DOPB_clsn_read_index : integer := -1;

    variable DOA_clsn_write_index, DOPA_clsn_write_index : integer := -1;
    variable DOB_clsn_write_index, DOPB_clsn_write_index : integer := -1;

    variable clsn_type       : CollisionFlagType;
    variable data_widths     : DataWidthType;
    variable clsn_xbufs      : ClsnXbufType;

    variable collision_msg   : memory_collision_type;

    variable Write_A_Write_B : memory_collision_type := Write_A_Write_B;
    variable Read_A_Write_B  : memory_collision_type := Read_A_Write_B;
    variable Write_A_Read_B  : memory_collision_type := Write_A_Read_B;
    variable Write_B_Write_A : memory_collision_type := Write_B_Write_A;
    variable Read_B_Write_A  : memory_collision_type := Read_B_Write_A;
    variable Write_B_Read_A  : memory_collision_type := Write_B_Read_A;

    variable msg_addr1       : std_logic_vector(MAX_ADDR downto 0)      := (others => '0');
    variable msg_addr2       : std_logic_vector(MAX_ADDR downto 0)      := (others => '0');

  begin


    if (FIRST_TIME) then

      DIPAW   := 0;
      DIPAW_1 := -1;
      DIPBW   := 0;
      DIPBW_1 := -1;

      DOPAW   := 0;
      DOPAW_1 := -1;
      DOPBW   := 0;
      DOPBW_1 := -1;

      case DATA_WIDTH_A is

            when 0 =>
                 DOAW    := 1;
                 DOAW_1  := DOAW -1;
                 DIAW    := 1;
                 DIAW_1  := DIAW -1;

            when 1 =>
                 zero_read_a(13 downto 0) := (others => '1');
                 DOAW    := 1;
                 DOAW_1  := DOAW -1;
                 zero_write_a(13 downto 0) := (others => '1');
                 DIAW    := 1;
                 DIAW_1  := DIAW -1;

            when 2 =>
                 zero_read_a(0 downto 0) := (others => '0');
                 DOAW    := 2;
                 DOAW_1  := DOAW -1;
                 zero_write_a(0 downto 0) := (others => '0');
                 DIAW    := 2;
                 DIAW_1  := DIAW -1;

            when 4 =>
                 zero_read_a(1 downto 0) := (others => '0');
                 DOAW    := 4;
                 DOAW_1  := DOAW -1;
                 zero_write_a(1 downto 0) := (others => '0');
                 DIAW    := 4;
                 DIAW_1  := DIAW -1;

            when 9 =>
                 zero_read_a(2 downto 0) := (others => '0');
                 DOAW    := 8;
                 DOAW_1  := DOAW -1;
                 DOPAW   := 1;
                 DOPAW_1 := DOPAW -1;
                 zero_write_a(2 downto 0) := (others => '0');
                 DIAW    := 8;
                 DIAW_1  := DIAW -1;
                 DIPAW   := 1;
                 DIPAW_1 := DIPAW -1;

            when 18  =>
                 zero_read_a(3 downto 0) := (others => '0');
                 zero_parity_read_a(0 downto 0) := (others => '0');
                 DOAW    := 16;
                 DOAW_1  := DOAW -1;
                 DOPAW   := 2;
                 DOPAW_1 := DOPAW -1;
                 zero_write_a(3 downto 0) := (others => '0');
                 zero_parity_write_a(0 downto 0) := (others => '0');
                 DIAW    := 16;
                 DIAW_1  := DIAW -1;
                 DIPAW   := 2;
                 DIPAW_1 := DIPAW -1;

            when 36  =>
                 zero_read_a(4 downto 0) := (others => '0');
                 zero_parity_read_a(1 downto 0) := (others => '0');
                 DOAW    := 32;
                 DOAW_1  := DOAW -1;
                 DOPAW   := 4;
                 DOPAW_1 := DOPAW -1;
                 zero_write_a(4 downto 0) := (others => '0');
                 zero_parity_write_a(1 downto 0) := (others => '0');
                 DIAW    := 32;
                 DIAW_1  := DIAW -1;
                 DIPAW   := 4;
                 DIPAW_1 := DIPAW -1;

            when others =>
                 null;

      end case;

      case DATA_WIDTH_B is

            when 0 =>
                 DOBW    := 1;
                 DOBW_1  := DOBW -1;
                 DIBW    := 1;
                 DIBW_1  := DIBW -1;

            when 1 =>
                 zero_read_b(13 downto 0) := (others => '1');
                 DOBW    := 1;
                 DOBW_1  := DOBW -1;
                 zero_write_b(13 downto 0) := (others => '1');
                 DIBW    := 1;
                 DIBW_1  := DIBW -1;

            when 2 =>
                 zero_read_b(0 downto 0) := (others => '0');
                 DOBW    := 2;
                 DOBW_1  := DOBW -1;
                 zero_write_b(0 downto 0) := (others => '0');
                 DIBW    := 2;
                 DIBW_1  := DIBW -1;

            when 4 =>
                 zero_read_b(1 downto 0) := (others => '0');
                 DOBW    := 4;
                 DOBW_1  := DOBW -1;
                 zero_write_b(1 downto 0) := (others => '0');
                 DIBW    := 4;
                 DIBW_1  := DIBW -1;

            when 9 =>
                 zero_read_b(2 downto 0) := (others => '0');
                 DOBW    := 8;
                 DOBW_1  := DOBW -1;
                 DOPBW   := 1;
                 DOPBW_1 := DOPBW -1;
                 zero_write_b(2 downto 0) := (others => '0');
                 DIBW    := 8;
                 DIBW_1  := DIBW -1;
                 DIPBW   := 1;
                 DIPBW_1 := DIPBW -1;

            when 18  =>
                 zero_read_b(3 downto 0) := (others => '0');
                 zero_parity_read_b(0 downto 0) := (others => '0');
                 DOBW    := 16;
                 DOBW_1  := DOBW -1;
                 DOPBW   := 2;
                 DOPBW_1 := DOPBW -1;
                 zero_write_b(3 downto 0) := (others => '0');
                 zero_parity_write_b(0 downto 0) := (others => '0');
                 DIBW    := 16;
                 DIBW_1  := DIBW -1;
                 DIPBW   := 2;
                 DIPBW_1 := DIPBW -1;

            when 36  =>
                 zero_read_b(4 downto 0) := (others => '0');
                 zero_parity_read_b(1 downto 0) := (others => '0');
                 DOBW    := 32;
                 DOBW_1  := DOBW -1;
                 DOPBW   := 4;
                 DOPBW_1 := DOPBW -1;
                 zero_write_b(4 downto 0) := (others => '0');
                 zero_parity_write_b(1 downto 0) := (others => '0');
                 DIBW    := 32;
                 DIBW_1  := DIBW -1;
                 DIPBW   := 4;
                 DIPBW_1 := DIPBW -1;

            when others =>
                 null;

      end case;

      if (INIT_A'length > 36) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A );
        INI_A(35 downto 0)                      := INI_A_UNBOUND(35 downto 0);
      elsif (INIT_A'length < 36) then
        INI_A(INIT_A'length-1 downto 0)         := To_StdLogicVector(INIT_A );
      elsif (INIT_A'length = 36) then
        INI_A(INIT_A'length-1 downto 0)         := To_StdLogicVector(INIT_A );
      end if;

      if (INIT_B'length > 36) then
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B );
        INI_B(35 downto 0)                      := INI_B_UNBOUND(35 downto 0);
      elsif (INIT_B'length < 36) then
        INI_B(INIT_B'length-1 downto 0)         := To_StdLogicVector(INIT_B );
      elsif (INIT_B'length = 36) then
        INI_B(INIT_B'length-1 downto 0)         := To_StdLogicVector(INIT_B );
      end if;

      if (SRVAL_A'length > 36) then
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A );
        SRVA_A(35 downto 0)                       := SRVA_A_UNBOUND(35 downto 0);
      elsif (SRVAL_A'length < 36) then
        SRVA_A(SRVAL_A'length-1 downto 0)         := To_StdLogicVector(SRVAL_A );
      elsif (SRVAL_A'length = 36) then
        SRVA_A(SRVAL_A'length-1 downto 0)         := To_StdLogicVector(SRVAL_A );
      end if;

      if (SRVAL_B'length > 36) then
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B );
        SRVA_B(35 downto 0)                       := SRVA_B_UNBOUND(35 downto 0);
      elsif (SRVAL_B'length < 36) then
        SRVA_B(SRVAL_B'length-1 downto 0)         := To_StdLogicVector(SRVAL_B );
      elsif (SRVAL_B'length = 36) then
        SRVA_B(SRVAL_B'length-1 downto 0)         := To_StdLogicVector(SRVAL_B );
      end if;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := "00";
      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := "01";
      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := "10";
      else
        GenericValueCheckMessage
          ( HeaderMsg            => " Attribute Syntax Error : ",
            GenericName          => " WRITE_MODE_A ",
            EntityName           => "/RAMB16BWE",
            GenericValue         => WRITE_MODE_A,
            Unit                 => "",
            ExpectedValueMsg     => " The Legal values for this attribute are ",
            ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
            TailMsg              => "",
            MsgSeverity          => error
            );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := "00";
      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := "01";
      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := "10";
      else
        GenericValueCheckMessage
          ( HeaderMsg            => " Attribute Syntax Error : ",
            GenericName          => " WRITE_MODE_B ",
            EntityName           => "/RAMB16BWE",
            GenericValue         => WRITE_MODE_B,
            Unit                 => "",
            ExpectedValueMsg     => " The Legal values for this attribute are ",
            ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
            TailMsg              => "",
            MsgSeverity          => error
            );
      end if;

      if((SIM_COLLISION_CHECK = "ALL") or (SIM_COLLISION_CHECK = "all")) then
          SimCollisionCheck_var := 3;
      elsif((SIM_COLLISION_CHECK = "NONE") or (SIM_COLLISION_CHECK = "none")) then
          SimCollisionCheck_var := 0;
      elsif((SIM_COLLISION_CHECK = "WARNING_ONLY") or (SIM_COLLISION_CHECK = "warning_only")) then
          SimCollisionCheck_var := 1;
      elsif((SIM_COLLISION_CHECK = "GENERATE_X_ONLY") or (SIM_COLLISION_CHECK = "generate_x_only")) then
          SimCollisionCheck_var := 2;
     else
        GenericValueCheckMessage
         ( HeaderMsg            => " Attribute Syntax Error : ",
           GenericName          => " SIM_COLLISION_CHECK ",
           EntityName           => "/RAMB16BWE",
           GenericValue         => SIM_COLLISION_CHECK,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY ",
           TailMsg              => "",
           MsgSeverity          => error
           );
     end if;


      wait until (GSR_CLKA_dly = '1' or GSR_CLKB_dly = '1' or ((CLKA_dly = '0' or CLKA_dly = '1') or (CLKB_dly = '0' or CLKB_dly = '1')));
---################################################################################
        DOA_zd(DOAW_1 downto 0) := INI_A(DOAW_1 downto 0);
        DOB_zd(DOBW_1 downto 0) := INI_B(DOBW_1 downto 0);

        if(DOPAW_1 /= -1) then
           DOPA_zd(DOPAW_1 downto 0) := INI_A((DOPAW_1 + DOAW) downto DOAW);
        end if;

        if(DOPBW_1 /= -1) then
           DOPB_zd(DOPBW_1 downto 0) := INI_B((DOPBW_1 + DOBW) downto DOBW);
        end if;

----- Port A
--        DOA <= DOA_zd;
--        if(DOPAW_1 /= -1) then
--           DOPA <= DOPA_zd;
--        end if;

----- Port B
--        DOB <= DOB_zd;
--        if(DOPBW_1 /= -1) then
--           DOPB <= DOPB_zd;
--        end if;

      data_widths.diaw  := DIAW; 
      data_widths.dipaw := DIPAW; 
      data_widths.doaw  := DOAW; 
      data_widths.dopaw := DOPAW; 

      data_widths.dibw  := DIBW; 
      data_widths.dipbw := DIPBW; 
      data_widths.dobw  := DOBW; 
      data_widths.dopbw := DOPBW; 

      FIRST_TIME  := false;
    end if;
----------------  END FIRST_TIME

--    addra_in_14 := ADDRA_dly(14);

    if (CLKA_dly'event) then
      ENA_dly_sampled   := ENA_dly;
      SSRA_dly_sampled  := SSRA_dly;
      WEA_dly_sampled   := WEA_dly;
      ADDRA_dly_sampled := ADDRA_dly;
    end if;

-------------------------------------------------------------

--    addrb_in_14 := ADDRB_dly(14);

    if (CLKB_dly'event) then
      ENB_dly_sampled   := ENB_dly;
      SSRB_dly_sampled  := SSRB_dly;
      WEB_dly_sampled   := WEB_dly;
      ADDRB_dly_sampled := ADDRB_dly;
    end if;



--------------------------------    A    ----------------------------------------
        tmp_zero_write_a  := (addra_dly_sampled(13 downto 0) and zero_write_a);
        ADDRESS_WRITE_A := SLV_TO_INT(tmp_zero_write_a);

        tmp_zero_read_a  := (addra_dly_sampled(13 downto 0) and zero_read_a);
        ADDRESS_READ_A  := SLV_TO_INT(tmp_zero_read_a);

        tmp_zero_parity_write_a(10 downto 0) := addra_dly_sampled( 13 downto 3) and zero_parity_write_a;
        ADDRESS_PARITY_WRITE_A := SLV_TO_INT(tmp_zero_parity_write_a);

        tmp_zero_parity_read_a(10 downto 0) := addra_dly_sampled( 13 downto 3) and zero_parity_read_a;
        ADDRESS_PARITY_READ_A := SLV_TO_INT(tmp_zero_parity_read_a);
--------------------------------    B    ----------------------------------------
        tmp_zero_write_b  := (addrb_dly_sampled(13 downto 0) and zero_write_b);
        ADDRESS_WRITE_B := SLV_TO_INT(tmp_zero_write_b);

        tmp_zero_read_b  := (addrb_dly_sampled(13 downto 0) and zero_read_b);
        ADDRESS_READ_B  := SLV_TO_INT(tmp_zero_read_b);

        tmp_zero_parity_write_b(10 downto 0) := addrb_dly_sampled( 13 downto 3) and zero_parity_write_b;
        ADDRESS_PARITY_WRITE_B := SLV_TO_INT(tmp_zero_parity_write_b);

        tmp_zero_parity_read_b(10 downto 0) := addrb_dly_sampled( 13 downto 3) and zero_parity_read_b;
        ADDRESS_PARITY_READ_B := SLV_TO_INT(tmp_zero_parity_read_b);


--    VALID_ADDRA           := ADDR_IS_VALID(addra_dly_sampled);
--    if (VALID_ADDRA) then
--    end if;

--    VALID_ADDRB           := ADDR_IS_VALID(addrb_dly_sampled);
--    if (VALID_ADDRB) then
--    end if;

--  DOA_INDEX /  DOPA_INDEX

    if(DIAW <= DOAW) then
       case DIAW is
          when 1 =>
             case DOAW is
                when 1  => DOA_INDEX := 0;
                when 2  => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(0 downto 0));
                when 4  => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(1 downto 0));
                when 8  => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(2 downto 0));
                when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(3 downto 0));
                when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(4 downto 0));
                when others => null;
             end case;

          when 2 =>
             case DOAW is
                when 2  => DOA_INDEX := 0;
                when 4  => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(1 downto 1));
                when 8  => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(2 downto 1));
                when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(3 downto 1));
                when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(4 downto 1));
                when others => null;
             end case;

          when 4 =>
             case DOAW is
                when 4  => DOA_INDEX := 0;
                when 8  => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(2 downto 2));
                when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(3 downto 2));
                when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(4 downto 2));
                when others => null;
             end case;

          when 8 =>
             case DOAW is
                when 8  => DOA_INDEX := 0;
                           DOPA_INDEX := 0;
                when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(3 downto 3));
                           DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_write_a(0 downto 0));
                when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(4 downto 3));
                           DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_write_a(1 downto 0));
                when others => null;
             end case;

          when 16 =>
             case DOAW is
                when 16 => DOA_INDEX := 0;
                           DOPA_INDEX := 0;
                when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(4 downto 4));
                           DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_write_a(1 downto 1));
                when others => null;
             end case;

          when 32 =>
             case DOAW is
                when 32 => DOA_INDEX := 0;
                           DOPA_INDEX := 0;
                when others => null;
             end case;
       
          when others => null;
       end case;

    elsif(DIAW > DOAW) then
       case DOAW is
          when 1 =>
             case DIAW is
                when 2  => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(0 downto 0));
                when 4  => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(1 downto 0));
                when 8  => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(2 downto 0));
                when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(3 downto 0));
                when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(4 downto 0));
                when others => null;
             end case;
          when 2 =>
             case DIAW is
                when 4  => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(1 downto 1));
                when 8  => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(2 downto 1));
                when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(3 downto 1));
                when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(4 downto 1));
                when others => null;
             end case;

          when 4 =>
             case DIAW is
                when 8  => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(2 downto 2));
                when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(3 downto 2));
                when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(4 downto 2));
                when others => null;
             end case;
          when 8 =>
             case DIAW is
                when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(3 downto 3));
                           DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_read_a(0 downto 0));
                when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(4 downto 3));
                           DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 0));
                when others => null;
             end case;

          when 16 =>
             case DIAW is
                when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(4 downto 4));
                           DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 1));
                when others => null;
             end case;

          when others => null;
       end case;
    end if;

--  DOB_INDEX /  DOPB_INDEX

    if(DIBW <= DOBW) then
       case DIBW is
          when 1 =>
             case DOBW is
                when 1  => DOB_INDEX := 0;
                when 2  => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(0 downto 0));
                when 4  => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(1 downto 0));
                when 8  => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(2 downto 0));
                when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(3 downto 0));
                when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(4 downto 0));
                when others => null;
             end case;

          when 2 =>
             case DOBW is
                when 2  => DOB_INDEX := 0;
                when 4  => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(1 downto 1));
                when 8  => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(2 downto 1));
                when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(3 downto 1));
                when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(4 downto 1));
                when others => null;
             end case;

          when 4 =>
             case DOBW is
                when 4  => DOB_INDEX := 0;
                when 8  => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(2 downto 2));
                when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(3 downto 2));
                when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(4 downto 2));
                when others => null;
             end case;

          when 8 =>
             case DOBW is
                when 8  => DOB_INDEX := 0;
                           DOPB_INDEX := 0;
                when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(3 downto 3));
                           DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_write_b(0 downto 0));
                when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(4 downto 3));
                           DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_write_b(1 downto 0));
                when others => null;
             end case;

          when 16 =>
             case DOBW is
                when 16 => DOB_INDEX := 0;
                           DOPB_INDEX := 0;
                when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(4 downto 4));
                           DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_write_b(1 downto 1));
                when others => null;
             end case;

          when 32 =>
             case DOBW is
                when 32 => DOB_INDEX := 0;
                           DOPB_INDEX := 0;
                when others => null;
             end case;
       
          when others => null;
       end case;

    elsif(DIBW > DOBW) then
       case DOBW is
          when 1 =>
             case DIBW is
                when 2  => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(0 downto 0));
                when 4  => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(1 downto 0));
                when 8  => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(2 downto 0));
                when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(3 downto 0));
                when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(4 downto 0));
                when others => null;
             end case;
          when 2 =>
             case DIBW is
                when 4  => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(1 downto 1));
                when 8  => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(2 downto 1));
                when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(3 downto 1));
                when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(4 downto 1));
                when others => null;
             end case;

          when 4 =>
             case DIBW is
                when 8  => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(2 downto 2));
                when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(3 downto 2));
                when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(4 downto 2));
                when others => null;
             end case;
          when 8 =>
             case DIBW is
                when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(3 downto 3));
                           DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_read_b(0 downto 0));
                when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(4 downto 3));
                           DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 0));
                when others => null;
             end case;

          when 16 =>
             case DIBW is
                when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(4 downto 4));
                           DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 1));
                when others => null;
             end case;

          when others => null;
       end case;
    end if;



----- ######################################################################################################

        if(rising_edge(CLKA_dly)) then
           CLKA_time := now;
        end if;

        if(rising_edge(CLKB_dly)) then
           CLKB_time := now;
        end if;


----- ######################################################################################################
------------------------------------------------------------------------                       
------------ Port A ----------------------------------------------------
------------------------------------------------------------------------                       
    if(GSR_CLKA_dly = '1') then
       DOA_zd(DOAW_1 downto 0) := INI_A(DOAW_1 downto 0);
       if(DOPAW_1 /= -1) then
         DOPA_zd(DOPAW_1 downto 0) := INI_A((DOPAW_1 + DOAW) downto DOAW);
       end if;
    elsif(CLKA_dly'event AND CLKA_dly'last_value = '0') then

        if (ena_dly_sampled = '1') then
            if (ssra_dly_sampled = '1') then
                   DOA_zd(DOAW_1 downto 0) := SRVA_A(DOAW_1 downto 0);
                   DOA_clsn_zero := (others => '0');
                   DOA_clsn := (others => '0');
                   if(DOPAW_1 /= -1) then
                      DOPA_zd(DOPAW_1 downto 0) := SRVA_A((DOPAW_1 + DOAW) downto DOAW);
                      DOPA_clsn_zero := (others => '0');
                      DOPA_clsn := (others => '0');
                   end if;
            else
-----------------------  Start COLLISION A ------------------------------

        if(SimCollisionCheck_var /= 0) then
           DOA_clsn_sav          := DOA_clsn;
           DOPA_clsn_sav         := DOPA_clsn;

           DOA_clsn              := (others => '0');
           DOPA_clsn             := (others => '0');
           clsn_xbufs.DO1_clsn   := (others => '0');
           clsn_xbufs.DOP1_clsn  := (others => '0');
           clsn_xbufs.MEM1_clsn  := (others => '0');
           clsn_xbufs.MEMP1_clsn := (others => '0');

           clsn_xbufs.DO2_clsn   := (others => '0');
           clsn_xbufs.DOP2_clsn  := (others => '0');
           clsn_xbufs.MEM2_clsn  := (others => '0');
           clsn_xbufs.MEMP2_clsn := (others => '0');
        
           clsn_type.active_port := 1;
           addr_overlap := false;
           clsn_type.read_write  := false;
           clsn_type.write_read  := false;
           clsn_type.write_write := false;

--           CLKA_time := now;

           ClkCollisionCheck(
              violation => collision_clka_clkb,
              CheckEnabled => ((TO_X01(ena_dly_sampled) = '1') and (TO_X01(enb_dly_sampled) = '1')), 
              CLK1_time => CLKA_time,
              CLK2_time => CLKB_time,
              SETUP_All => SETUP_ALL,
              SETUP_READ_FIRST => SETUP_READ_FIRST
           );

           if(collision_clka_clkb /= 0) then
              QkAddrOverlapChk(
                addr_overlap => addr_overlap,
                data_widths  => data_widths,
                addra        => addra_dly_sampled,
                addrb        => addrb_dly_sampled
              );
           end if;
        
           if(addr_overlap) then
              PreProcessWe1We2(
                clsn_bufs     => clsn_xbufs,
                clsn_type     => clsn_type,
                memory        => MEM,
                di1           => dia_dly,
                di2           => dib_dly,
                dip1          => dipa_dly,
                dip2          => dipb_dly,
                addr1         => addra_dly_sampled,
                addr2         => addrb_dly_sampled,
                we1           => wea_dly_sampled,
                we2           => web_dly_sampled,
                zero_read_1   => zero_read_a,
                zero_readp_1  => zero_parity_read_a,
                zero_write_1  => zero_write_a,
                zero_writep_1 => zero_parity_write_a,
                zero_read_2   => zero_read_b,
                zero_readp_2  => zero_parity_read_b,
                zero_write_2  => zero_write_b,
                zero_writep_2 => zero_parity_write_b,
                wr_mode_1     => wr_mode_a,
                wr_mode_2     => wr_mode_b,
                violation     => collision_clka_clkb,
                DI1W          => DIAW,
                DIP1W         => DIPAW,
                DI2W          => DIBW,
                DIP2W         => DIPBW,
                DO1W          => DOAW,
                DOP1W         => DOPAW,
                DO2W          => DOBW,
                DOP2W         => DOPBW
              );
           end if;
           
           if(clsn_type.read_write or clsn_type.write_write or clsn_type.write_read) then
               
              if(clsn_type.write_write) then
                  collision_msg := Write_A_Write_B; 
                  msg_addr1 := tmp_zero_write_a; 
                  msg_addr2 := tmp_zero_write_b; 
              elsif(clsn_type.read_write) then
                  collision_msg :=  Read_A_Write_B; 
                  msg_addr1 := tmp_zero_read_a; 
                  msg_addr2 := tmp_zero_write_b; 
              elsif(clsn_type.write_read) then
                  collision_msg :=  Write_A_Read_B; 
--                  msg_addr1 := tmp_zero_write_a; 
--                  msg_addr2 := tmp_zero_read_b; 
                  msg_addr1 := tmp_zero_read_b;
                  msg_addr2 := tmp_zero_write_a;
              end if;

              if(SimCollisionCheck_var = 1) then
                 --- Message 
                 Memory_Collision_Msg_ramb16
                 (  collision_type => collision_msg,
                   EntityName => "RAMB16BWE",
                   InstanceName => RAMB16BWE'path_name,
                   address_1 => msg_addr1,
                   address_2 => msg_addr2
                 );

              DOA_clsn  := (others => '0');
              DOPA_clsn := (others => '0');
              DOA_clsn_sav  := DOA_clsn;
              DOPA_clsn_sav := DOPA_clsn;

              elsif(SimCollisionCheck_var = 2) then

                 DOA_clsn_read_index  := SLV_TO_INT(tmp_zero_read_a(4 downto 0));
                 DOB_clsn_read_index := SLV_TO_INT(tmp_zero_read_b(4 downto 0));
                 DOA_clsn(DOAW_1 downto 0) := clsn_xbufs.DO1_clsn((DOA_clsn_read_index+DOAW_1) downto DOA_clsn_read_index);
                 DOB_clsn(DOBW_1 downto 0) := clsn_xbufs.DO2_clsn((DOB_clsn_read_index+DOBW_1) downto DOB_clsn_read_index);
                 if(DOPAW_1 /= -1) then
                    DOPA_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 0));
                    DOPA_clsn(DOPAW_1 downto 0) := clsn_xbufs.DOP1_clsn((DOPA_clsn_read_index+DOPAW_1) downto DOPA_clsn_read_index);
                 end if;

                 if(DOPBW_1 /= -1) then
                    DOPB_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 0));
                    DOPB_clsn(DOPBW_1 downto 0) := clsn_xbufs.DOP2_clsn((DOPB_clsn_read_index+DOPBW_1) downto DOPB_clsn_read_index);
                 end if;

                 if(wr_mode_a = "10") then
                    DOA_clsn(DOAW_1 downto 0) := DOA_clsn(DOAW_1 downto 0) xor DOA_clsn_sav(DOAW_1 downto 0);
                    if(DOPAW_1 /= -1) then
                       DOPA_clsn(DOPAW_1 downto 0) := DOPA_clsn(DOPAW_1 downto 0) xor DOPA_clsn_sav(DOPAW_1 downto 0);
                    end if;
                 end if;

                 if(wr_mode_b = "10") then
                    DOB_clsn(DOBW_1 downto 0) := DOB_clsn(DOBW_1 downto 0) xor DOB_clsn_sav(DOBW_1 downto 0);
                    if(DOPBW_1 /= -1) then
                       DOPB_clsn(DOPBW_1 downto 0) := DOPB_clsn(DOPBW_1 downto 0) xor DOPB_clsn_sav(DOPBW_1 downto 0);
                    end if;
                 end if;

              elsif(SimCollisionCheck_var = 3) then
                 --- Message 
                 Memory_Collision_Msg_ramb16
                 (  collision_type => collision_msg,
                   EntityName => "RAMB16BWE",
                   InstanceName => RAMB16BWE'path_name,
                   address_1 => msg_addr1,
                   address_2 => msg_addr2
                 );

                 DOA_clsn_read_index := SLV_TO_INT(tmp_zero_read_a(4 downto 0));
                 DOB_clsn_read_index := SLV_TO_INT(tmp_zero_read_b(4 downto 0));
                 DOA_clsn(DOAW_1 downto 0) := clsn_xbufs.DO1_clsn((DOA_clsn_read_index+DOAW_1) downto DOA_clsn_read_index);
                 DOB_clsn(DOBW_1 downto 0) := clsn_xbufs.DO2_clsn((DOB_clsn_read_index+DOBW_1) downto DOB_clsn_read_index);
                 if(DOPAW_1 /= -1) then
                    DOPA_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 0));
                    DOPA_clsn(DOPAW_1 downto 0) := clsn_xbufs.DOP1_clsn((DOPA_clsn_read_index+DOPAW_1) downto DOPA_clsn_read_index);
                 end if;

                 if(DOPBW_1 /= -1) then
                    DOPB_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 0));
                    DOPB_clsn(DOPBW_1 downto 0) := clsn_xbufs.DOP2_clsn((DOPB_clsn_read_index+DOPBW_1) downto DOPB_clsn_read_index);
                 end if;

                 if(wr_mode_a = "10") then
                    DOA_clsn(DOAW_1 downto 0) := DOA_clsn(DOAW_1 downto 0) xor DOA_clsn_sav(DOAW_1 downto 0);
                    if(DOPAW_1 /= -1) then
                       DOPA_clsn(DOPAW_1 downto 0) := DOPA_clsn(DOPAW_1 downto 0) xor DOPA_clsn_sav(DOPAW_1 downto 0);
                    end if;
                 end if;

                 if(wr_mode_b = "10") then
                    DOB_clsn(DOBW_1 downto 0) := DOB_clsn(DOBW_1 downto 0) xor DOB_clsn_sav(DOBW_1 downto 0);
                    if(DOPBW_1 /= -1) then
                       DOPB_clsn(DOPBW_1 downto 0) := DOPB_clsn(DOPBW_1 downto 0) xor DOPB_clsn_sav(DOPBW_1 downto 0);
                    end if;
                 end if;


              end if;

           end if;

           DOA_clsn_zero  := DOA_clsn;
           DOPA_clsn_zero := DOPA_clsn;
           if(ssrb_dly_sampled = '0') then
              DOB_clsn_zero  := DOB_clsn;
              DOPB_clsn_zero := DOPB_clsn;
           end if;

        end if;

----------------  END COLLISION A ------------------------------
            if  (wr_mode_a = "00") then

               case DIAW is
               ---------
               when 1|2|4|8 =>
               ---------
                  tmp_we(1 downto 0) := addra_dly_sampled( 4 downto 3);
                  wea_index := SLV_TO_INT(tmp_we);
                  if(wea_dly_sampled(wea_index) = '1') then
                     if(DOAW > DIAW) then
                        DOA_zd_buf(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto  ADDRESS_READ_A);
                        DOA_zd_buf(((DOA_INDEX *DIAW) + DIAW_1) downto (DOA_INDEX *DIAW)) := DIA_dly(DIAW_1 downto 0);
                        DOA_zd(DOAW_1 downto 0) := DOA_zd_buf(DOAW_1 downto 0);
                              
                        if(DOPAW_1 /= -1) then
                          DOPA_zd_buf(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto  (16384 + ADDRESS_PARITY_READ_A));
                          DOPA_zd_buf(((DOPA_INDEX *DIPAW) + DIPAW_1) downto (DOPA_INDEX *DIPAW)) := DIPA_dly(DIPAW_1 downto 0);
                          DOPA_zd(DOPAW_1 downto 0) := DOPA_zd_buf(DOPAW_1 downto 0);
                        end if;
                     elsif(DOAW <= DIAW) then
--FP                        DOA_zd(DOAW_1 downto 0)   := DIA_dly(DOAW_1 downto 0);
                        DOA_zd(DOAW_1 downto 0)   := DIA_dly((((DOA_INDEX)*DOAW)+ DOAW_1) downto ((DOA_INDEX)*DOAW));
                        if(DOPAW_1 /= -1) then
                           DOPA_zd(DOPAW_1 downto 0)   := DIPA_dly(DOPAW_1 downto 0);
                        end if;
                     end if;
                  elsif(wea_dly_sampled(wea_index) = '0') then
                     DOA_zd(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto (ADDRESS_READ_A));
                     if(DOPAW_1 /= -1) then
                        DOPA_zd(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto (16384 + ADDRESS_PARITY_READ_A));
                     end if;
                  end if;
                     
               ---------
               when 16 =>
               ---------
                  if(DOAW > DIAW) then
                     DOA_zd_buf(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto  ADDRESS_READ_A);
                     DOPA_zd_buf(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto  (16384 + ADDRESS_PARITY_READ_A));
                     
-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's    
                     
                     xout_we_seg1(1) := addra_dly_sampled(4);
                     xout_we_seg1(0) := '0';
                     xout_we_seg2(1) := addra_dly_sampled(4);
                     xout_we_seg2(0) := '1';

                     if(wea_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= wea_dly_sampled(SLV_TO_INT(xout_we_seg2))) then 
                        DOA_zd_buf(DOAW_1 downto 0) := (others => 'X');
                        DOPA_zd_buf(DOPAW_1 downto 0) := (others => 'X');
                     else
                        tmp_we(1) := addra_dly_sampled(4);
                        tmp_we(0) := '0';
                        wea_index := SLV_TO_INT(tmp_we);
                        if(wea_dly_sampled(wea_index) = '1') then
                           DOA_zd_buf(((DOA_INDEX *DIAW) + (DIAW/2 - 1)) downto (DOA_INDEX *DIAW)) := DIA_dly((DIAW/2 - 1) downto 0);
                           DOPA_zd_buf(((DOPA_INDEX *DIPAW) + (DIPAW/2 - 1)) downto (DOPA_INDEX *DIPAW)) := DIPA_dly((DIPAW/2 - 1) downto 0);
                        end if;

                        tmp_we(1) := addra_dly_sampled(4);
                        tmp_we(0) := '1';
                        wea_index := SLV_TO_INT(tmp_we);
                        if(wea_dly_sampled(wea_index) = '1') then
                          DOA_zd_buf(((DOA_INDEX *DIAW) + DIAW_1) downto ((DOA_INDEX *DIAW) + DIAW/2 )) := DIA_dly(DIAW_1 downto DIAW/2);
                          DOPA_zd_buf(((DOPA_INDEX *DIPAW) + DIPAW_1) downto ((DOPA_INDEX *DIPAW) + DIPAW/2 )) := DIPA_dly(DIPAW_1 downto DIPAW/2);
                        end if;

                     end if;

                     DOA_zd(DOAW_1 downto 0)   := DOA_zd_buf(DOAW_1 downto 0);
                     DOPA_zd(DOPAW_1 downto 0) := DOPA_zd_buf(DOPAW_1 downto 0);

                  end if;

-------------------
                  if(DOAW <= DIAW) then
                     DOA_zd_buf(DIAW_1 downto 0) := MEM((ADDRESS_WRITE_A + DIAW_1) downto  ADDRESS_WRITE_A);
                     if(DOPAW_1 /= -1) then
                       DOPA_zd_buf(DIPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto  (16384 + ADDRESS_PARITY_WRITE_A));
                     end if;
-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's    
                     
                     xout_we_seg1(1) := addra_dly_sampled(4);
                     xout_we_seg1(0) := '0';
                     xout_we_seg2(1) := addra_dly_sampled(4);
                     xout_we_seg2(0) := '1';

                     tmp_we(1) := addra_dly_sampled(4);
                     tmp_we(0) := '0';
                     wea_index := SLV_TO_INT(tmp_we);
                     if(wea_dly_sampled(wea_index) = '1') then
                        DOA_zd_buf((DIAW/2 - 1) downto 0)   := DIA_dly((DIAW/2 -1 ) downto 0);
                        if(DOPAW_1 /= -1) then
                           DOPA_zd_buf((DIPAW/2 - 1) downto 0)   := DIPA_dly((DIPAW/2 -1 ) downto 0);
                        end if;
                     elsif(wea_dly_sampled(wea_index) = '0') then
                        if(wea_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= wea_dly_sampled(SLV_TO_INT(xout_we_seg2))) then
                           DOA_zd_buf((DIAW/2 - 1) downto 0)   := (others => 'X');
                           if(DOPAW_1 /= -1) then
                              DOPA_zd_buf((DIPAW/2 - 1) downto 0)   := (others => 'X');
                           end if;
                        end if;
                     end if;

                     tmp_we(1) := addra_dly_sampled(4);
                     tmp_we(0) := '1';
                     wea_index := SLV_TO_INT(tmp_we);
                     if(wea_dly_sampled(wea_index) = '1') then
                        DOA_zd_buf(DIAW_1 downto DIAW/2 )   := DIA_dly(DIAW_1 downto DIAW/2);
                        if(DOPAW_1 /= -1) then
                           DOPA_zd_buf(DIPAW_1 downto DIPAW/2 )   := DIPA_dly(DIPAW_1 downto DIPAW/2);
                        end if;
                     elsif(wea_dly_sampled(wea_index) = '0') then
                        if(wea_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= wea_dly_sampled(SLV_TO_INT(xout_we_seg2))) then
                           DOA_zd_buf(DIAW_1 downto DIAW/2 )   := (others => 'X');
                           if(DOPAW_1 /= -1) then
                              DOPA_zd_buf(DIPAW_1 downto DIPAW/2 )   := (others => 'X');
                           end if;
                        end if;
                     end if;

-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's    
                     if((wea_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= wea_dly_sampled(SLV_TO_INT(xout_we_seg2))) and (DOAW /= DIAW)) then 
                        DOA_zd_buf(DIAW_1 downto 0) := (others => 'X');
                        DOPA_zd_buf(DIPAW_1 downto 0) := (others => 'X');
                     end if;

                     DOA_zd(DOAW_1 downto 0)   := DOA_zd_buf(((DOA_INDEX * DOAW) + DOAW_1) downto (DOA_INDEX * DOAW));
                     if(DOPAW_1 /= -1) then
                        DOPA_zd(DOPAW_1 downto 0) :=  DOPA_zd_buf(((DOPA_INDEX * DOPAW) + DOPAW_1) downto (DOPA_INDEX * DOPAW));
                     end if;

                  end if;

               ---------
               when 32 =>
               ---------

                  for i in 0 to 3 loop
                     if (wea_dly_sampled(i) = '1') then
                        DOA_zd_buf(((DIAW/4)*(i+1) - 1) downto (DIAW/4)*i)   := DIA_dly(((DIAW/4)*(i+1) - 1) downto (DIAW/4)*i);
                        if(DOPAW_1 /= -1) then
                           DOPA_zd_buf(((DIPAW/4)*(i+1) - 1) downto (DIPAW/4)*i) := DIPA_dly(((DIPAW/4)*(i+1) - 1) downto (DIPAW/4)*i);
                        end if;
                     elsif (wea_dly_sampled(i) = '0') then
-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's    
                        DOA_zd_buf(((DIAW/4)*(i+1) - 1) downto (DIAW/4)*i)   := (others => 'X');
                        if(DOPAW_1 /= -1) then
                           DOPA_zd_buf(((DIPAW/4)*(i+1) - 1) downto (DIPAW/4)*i) := (others => 'X');
                        end if;
                     end if;
                  end loop;

-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's    
                  if((wea_dly_sampled(0) = '0') and (wea_dly_sampled(1) = '0') and (wea_dly_sampled(2) = '0') and  (wea_dly_sampled(3) = '0')) then 
                     DOA_zd_buf(DIAW_1 downto 0) := MEM((ADDRESS_WRITE_A + DIAW_1) downto  ADDRESS_WRITE_A);
                     if(DOPAW_1 /= -1) then
                        DOPA_zd_buf(DIPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto  (16384 + ADDRESS_PARITY_WRITE_A));
                     end if;
                  
                  elsif(not((wea_dly_sampled(0) = '1') and (wea_dly_sampled(1) = '1') and (wea_dly_sampled(2) = '1') and  (wea_dly_sampled(3) = '1'))) then 
                      if(DOAW /= DIAW) then
                         DOA_zd_buf(DIAW_1 downto 0) := (others => 'X');
                         if(DOPAW_1 /= -1) then
                            DOPA_zd_buf(DIPAW_1 downto 0) := (others => 'X');
                         end if;
                      end if;
                  end if;

                  DOA_zd(DOAW_1 downto 0)   := DOA_zd_buf(((DOA_INDEX * DOAW) + DOAW_1) downto (DOA_INDEX * DOAW));
                  if(DOPAW_1 /= -1) then
                     DOPA_zd(DOPAW_1 downto 0) :=  DOPA_zd_buf(((DOPA_INDEX * DOPAW) + DOPAW_1) downto (DOPA_INDEX * DOPAW));
                  end if;

                  when others =>
                     null;
               end case;

            elsif(wr_mode_a = "01") then
              DOA_zd(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto (ADDRESS_READ_A));
              if(DOPAW_1 /= -1) then
                  DOPA_zd(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto (16384 + ADDRESS_PARITY_READ_A));
              end if;
            elsif(wr_mode_a = "10") then
              case DIAW is
                 when 1|2|4|8 =>
                    tmp_we(1 downto 0) := addra_dly_sampled( 4 downto 3);
                    wea_index := SLV_TO_INT(tmp_we);
                    if (wea_dly_sampled(wea_index) = '0') then
                       DOA_zd(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto (ADDRESS_READ_A));
                       if(DOPAW_1 /= -1) then
                           DOPA_zd(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto (16384 + ADDRESS_PARITY_READ_A));
                       end if;
                    end if;
                 ----------
                 when 16|32 =>
                 ----------
                    if ((wea_dly_sampled(0) = '0') and (wea_dly_sampled(1) = '0') and (wea_dly_sampled(2) = '0') and (wea_dly_sampled(3) = '0'))then
                       DOA_zd(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto (ADDRESS_READ_A));
                       if(DOPAW_1 /= -1) then
                           DOPA_zd(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto (16384 + ADDRESS_PARITY_READ_A));
                       end if;
                    end if;
                 ----------
                 when others =>
                 ----------
                    null;
               end case;
          end if;
          end if;
            end if; -- /* end ena_dly_sampled = '1' */
      end if;

------------------------------------------------------------------------                       
------------ Port B ----------------------------------------------------
------------------------------------------------------------------------                       
    if(GSR_CLKB_dly = '1') then
       DOB_zd(DOBW_1 downto 0) := INI_B(DOBW_1 downto 0);
       if(DOPBW_1 /= -1) then
         DOPB_zd(DOPBW_1 downto 0) := INI_B((DOPBW_1 + DOBW) downto DOBW);
       end if;
    elsif(CLKB_dly'event AND CLKB_dly'last_value = '0') then
        if (enb_dly_sampled = '1') then
            if (ssrb_dly_sampled = '1') then
                   DOB_zd(DOBW_1 downto 0) := SRVA_B(DOBW_1 downto 0);
                   DOB_clsn_zero := (others => '0');
                   DOB_clsn := (others => '0');
                   if(DOPBW_1 /= -1) then
                      DOPB_zd(DOPBW_1 downto 0) := SRVA_B((DOPBW_1 + DOBW) downto DOBW);
                      DOPB_clsn_zero := (others => '0');
                      DOPB_clsn := (others => '0');
                   end if;
            else
-----------------------  Start COLLISION B ------------------------------
        if(SimCollisionCheck_var /= 0) then
           DOB_clsn_sav          := DOB_clsn;
           DOPB_clsn_sav         := DOPB_clsn;

           DOB_clsn              := (others => '0');
           DOPB_clsn             := (others => '0');
           clsn_xbufs.DO1_clsn   := (others => '0');
           clsn_xbufs.DOP1_clsn  := (others => '0');
           clsn_xbufs.MEM1_clsn  := (others => '0');
           clsn_xbufs.MEMP1_clsn := (others => '0');

           clsn_xbufs.DO2_clsn   := (others => '0');
           clsn_xbufs.DOP2_clsn  := (others => '0');
           clsn_xbufs.MEM2_clsn  := (others => '0');
           clsn_xbufs.MEMP2_clsn := (others => '0');
        
           clsn_type.active_port := 2;
           addr_overlap := false;
           clsn_type.read_write  := false;
           clsn_type.write_read  := false;
           clsn_type.write_write := false;

--           CLKB_time := now;

           ClkCollisionCheck(
              violation => collision_clka_clkb,
              CheckEnabled => ((TO_X01(ena_dly_sampled) = '1') and (TO_X01(enb_dly_sampled) = '1')), 
              CLK1_time => CLKB_time,
              CLK2_time => CLKA_time,
              SETUP_All => SETUP_ALL,
              SETUP_READ_FIRST => SETUP_READ_FIRST
           );

           if(collision_clka_clkb /= 0) then
              QkAddrOverlapChk(
                addr_overlap => addr_overlap,
                data_widths  => data_widths,
                addra        => addra_dly_sampled,
                addrb        => addrb_dly_sampled
              );
           end if;
        
           if(addr_overlap) then
              PreProcessWe1We2(
                clsn_bufs     => clsn_xbufs,
                clsn_type     => clsn_type,
                memory        => MEM,
                di1           => dib_dly,
                di2           => dia_dly,
                dip1          => dipb_dly,
                dip2          => dipa_dly,
                addr1         => addrb_dly_sampled,
                addr2         => addra_dly_sampled,
                we1           => web_dly_sampled,
                we2           => wea_dly_sampled,
                zero_read_1   => zero_read_b,
                zero_readp_1  => zero_parity_read_b,
                zero_write_1  => zero_write_b,
                zero_writep_1 => zero_parity_write_b,
                zero_read_2   => zero_read_a,
                zero_readp_2  => zero_parity_read_a,
                zero_write_2  => zero_write_a,
                zero_writep_2 => zero_parity_write_a,
                wr_mode_1     => wr_mode_b,
                wr_mode_2     => wr_mode_a,
                violation     => collision_clka_clkb,
                DI1W          => DIBW,
                DIP1W         => DIPBW,
                DI2W          => DIAW,
                DIP2W         => DIPAW,
                DO1W          => DOBW,
                DOP1W         => DOPBW,
                DO2W          => DOAW,
                DOP2W         => DOPAW
              );
           end if;
           
           if(clsn_type.read_write or clsn_type.write_write or clsn_type.write_read) then
               
              if(clsn_type.write_write) then
                  collision_msg := Write_B_Write_A; 
--                  msg_addr1 := tmp_zero_write_b; 
--                  msg_addr2 := tmp_zero_write_a; 
                  msg_addr1 := tmp_zero_write_a; 
                  msg_addr2 := tmp_zero_write_b; 
              elsif(clsn_type.read_write) then
                  collision_msg :=  Read_B_Write_A; 
                  msg_addr1 := tmp_zero_read_b; 
                  msg_addr2 := tmp_zero_write_a; 
              elsif(clsn_type.write_read) then
                  collision_msg :=  Write_B_Read_A; 
--                  msg_addr1 := tmp_zero_write_b; 
--                  msg_addr2 := tmp_zero_read_a; 
                  msg_addr1 := tmp_zero_read_a;
                  msg_addr2 := tmp_zero_write_b;
              end if;

              if(SimCollisionCheck_var = 1) then
                 --- Message 
                 Memory_Collision_Msg_ramb16
                 (  collision_type => collision_msg,
                   EntityName => "RAMB16BWE",
                   InstanceName => RAMB16BWE'path_name,
                   address_1 => msg_addr1,
                   address_2 => msg_addr2
                 );

              DOB_clsn  := (others => '0');
              DOPB_clsn := (others => '0');
              DOB_clsn_sav  := DOB_clsn;
              DOPB_clsn_sav := DOPB_clsn;

              elsif(SimCollisionCheck_var = 2) then

                 DOB_clsn_read_index := SLV_TO_INT(tmp_zero_read_b(4 downto 0));
                 DOA_clsn_read_index := SLV_TO_INT(tmp_zero_read_a(4 downto 0));

                 DOB_clsn(DOBW_1 downto 0) := clsn_xbufs.DO1_clsn((DOB_clsn_read_index+DOBW_1) downto DOB_clsn_read_index);
                 DOA_clsn(DOAW_1 downto 0) := clsn_xbufs.DO2_clsn((DOA_clsn_read_index+DOAW_1) downto DOA_clsn_read_index);

                 if(DOPBW_1 /= -1) then
                    DOPB_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 0));
                    DOPB_clsn(DOPBW_1 downto 0) := clsn_xbufs.DOP1_clsn((DOPB_clsn_read_index+DOPBW_1) downto DOPB_clsn_read_index);
                 end if;

                 if(DOPAW_1 /= -1) then
                    DOPA_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 0));
                    DOPA_clsn(DOPAW_1 downto 0) := clsn_xbufs.DOP2_clsn((DOPA_clsn_read_index+DOPAW_1) downto DOPA_clsn_read_index);
                 end if;

                 if(wr_mode_b = "10") then
                    DOB_clsn(DOBW_1 downto 0) := DOB_clsn(DOBW_1 downto 0) xor DOB_clsn_sav(DOBW_1 downto 0);
                    if(DOPBW_1 /= -1) then
                       DOPB_clsn(DOPBW_1 downto 0) := DOPB_clsn(DOPBW_1 downto 0) xor DOPB_clsn_sav(DOPBW_1 downto 0);
                    end if;
                 end if;

                 if(wr_mode_a = "10") then
                    DOA_clsn(DOAW_1 downto 0) := DOA_clsn(DOAW_1 downto 0) xor DOA_clsn_sav(DOAW_1 downto 0);
                    if(DOPAW_1 /= -1) then
                       DOPA_clsn(DOPAW_1 downto 0) := DOPA_clsn(DOPAW_1 downto 0) xor DOPA_clsn_sav(DOPAW_1 downto 0);
                    end if;
                 end if;


              elsif(SimCollisionCheck_var = 3) then
                 --- Message 
                 Memory_Collision_Msg_ramb16
                 (  collision_type => collision_msg,
                   EntityName => "RAMB16BWE",
                   InstanceName => RAMB16BWE'path_name,
                   address_1 => msg_addr1,
                   address_2 => msg_addr2
                 );


                 DOB_clsn_read_index := SLV_TO_INT(tmp_zero_read_b(4 downto 0));
                 DOA_clsn_read_index := SLV_TO_INT(tmp_zero_read_a(4 downto 0));

                 DOB_clsn(DOBW_1 downto 0) := clsn_xbufs.DO1_clsn((DOB_clsn_read_index+DOBW_1) downto DOB_clsn_read_index);
                 DOA_clsn(DOAW_1 downto 0) := clsn_xbufs.DO2_clsn((DOA_clsn_read_index+DOAW_1) downto DOA_clsn_read_index);

                 if(DOPBW_1 /= -1) then
                    DOPB_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 0));
                    DOPB_clsn(DOPBW_1 downto 0) := clsn_xbufs.DOP1_clsn((DOPB_clsn_read_index+DOPBW_1) downto DOPB_clsn_read_index);
                 end if;

                 if(DOPAW_1 /= -1) then
                    DOPA_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 0));
                    DOPA_clsn(DOPAW_1 downto 0) := clsn_xbufs.DOP2_clsn((DOPA_clsn_read_index+DOPAW_1) downto DOPA_clsn_read_index);
                 end if;

                 if(wr_mode_b = "10") then
                    DOB_clsn(DOBW_1 downto 0) := DOB_clsn(DOBW_1 downto 0) xor DOB_clsn_sav(DOBW_1 downto 0);
                    if(DOPBW_1 /= -1) then
                       DOPB_clsn(DOPBW_1 downto 0) := DOPB_clsn(DOPBW_1 downto 0) xor DOPB_clsn_sav(DOPBW_1 downto 0);
                    end if;
                 end if;

                 if(wr_mode_a = "10") then
                    DOA_clsn(DOAW_1 downto 0) := DOA_clsn(DOAW_1 downto 0) xor DOA_clsn_sav(DOAW_1 downto 0);
                    if(DOPAW_1 /= -1) then
                       DOPA_clsn(DOPAW_1 downto 0) := DOPA_clsn(DOPAW_1 downto 0) xor DOPA_clsn_sav(DOPAW_1 downto 0);
                    end if;
                 end if;

              end if;

           end if;

           DOB_clsn_zero  := DOB_clsn;
           DOPB_clsn_zero := DOPB_clsn;
           if(ssra_dly_sampled = '0') then
             DOA_clsn_zero  := DOA_clsn;
             DOPA_clsn_zero := DOPA_clsn;
           end if;

        end if;

----------------  END COLLISION B ------------------------------
            if (wr_mode_b = "00") then

               case DIBW is
               ---------
               when 1|2|4|8 =>
               ---------
                  tmp_we(1 downto 0) := addrb_dly_sampled( 4 downto 3);
                  web_index := SLV_TO_INT(tmp_we);
                  if(web_dly_sampled(web_index) = '1') then
                     if(DOBW > DIBW) then
                        DOB_zd_buf(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto  ADDRESS_READ_B);
                        DOB_zd_buf(((DOB_INDEX *DIBW) + DIBW_1) downto (DOB_INDEX *DIBW)) := DIB_dly(DIBW_1 downto 0);
                        DOB_zd(DOBW_1 downto 0) := DOB_zd_buf(DOBW_1 downto 0);
                              
                        if(DOPBW_1 /= -1) then
                          DOPB_zd_buf(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto  (16384 + ADDRESS_PARITY_READ_B));
                          DOPB_zd_buf(((DOPB_INDEX *DIPBW) + DIPBW_1) downto (DOPB_INDEX *DIPBW)) := DIPB_dly(DIPBW_1 downto 0);
                          DOPB_zd(DOPBW_1 downto 0) := DOPB_zd_buf(DOPBW_1 downto 0);
                        end if;
                     elsif(DOBW <= DIBW) then
--FP                        DOB_zd(DOBW_1 downto 0)   := DIB_dly(DOBW_1 downto 0);
                        DOB_zd(DOBW_1 downto 0)   := DIB_dly((((DOB_INDEX)*DOBW)+ DOBW_1) downto ((DOB_INDEX)*DOBW));
                        if(DOPBW_1 /= -1) then
                           DOPB_zd(DOPBW_1 downto 0)   := DIPB_dly(DOPBW_1 downto 0);
                        end if;
                     end if;
                  elsif(web_dly_sampled(web_index) = '0') then
                     DOB_zd(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto (ADDRESS_READ_B));
                     if(DOPBW_1 /= -1) then
                        DOPB_zd(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto (16384 + ADDRESS_PARITY_READ_B));
                     end if;
                  end if;
                     
               ---------
               when 16 =>
               ---------
                  if(DOBW > DIBW) then
                     DOB_zd_buf(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto  ADDRESS_READ_B);
                     DOPB_zd_buf(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto  (16384 + ADDRESS_PARITY_READ_B));
-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's  or all 1's

                     xout_we_seg1(1) := addrb_dly_sampled(4);
                     xout_we_seg1(0) := '0';
                     xout_we_seg2(1) := addrb_dly_sampled(4);
                     xout_we_seg2(0) := '1';

                     if(web_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= web_dly_sampled(SLV_TO_INT(xout_we_seg2))) then
                        DOB_zd_buf(DOBW_1 downto 0) := (others => 'X');
                        DOPB_zd_buf(DOPBW_1 downto 0) := (others => 'X');
                     else
                        tmp_we(1) := addrb_dly_sampled(4);
                        tmp_we(0) := '0';
                        web_index := SLV_TO_INT(tmp_we);
                        if(web_dly_sampled(web_index) = '1') then
                           DOB_zd_buf(((DOB_INDEX *DIBW) + (DIBW/2 - 1)) downto (DOB_INDEX *DIBW)) := DIB_dly((DIBW/2 - 1) downto 0);
                           DOPB_zd_buf(((DOPB_INDEX *DIPBW) + (DIPBW/2 - 1)) downto (DOPB_INDEX *DIPBW)) := DIPB_dly((DIPBW/2 - 1) downto 0);
                        end if;

                        tmp_we(1) := addrb_dly_sampled(4);
                        tmp_we(0) := '1';
                        web_index := SLV_TO_INT(tmp_we);
                        if(web_dly_sampled(web_index) = '1') then
                          DOB_zd_buf(((DOB_INDEX *DIBW) + DIBW_1) downto ((DOB_INDEX *DIBW) + DIBW/2 )) := DIB_dly(DIBW_1 downto DIBW/2);
                          DOPB_zd_buf(((DOPB_INDEX *DIPBW) + DIPBW_1) downto ((DOPB_INDEX *DIPBW) + DIPBW/2 )) := DIPB_dly(DIPBW_1 downto DIPBW/2);
                        end if;

                     end if;

                     DOB_zd(DOBW_1 downto 0)   := DOB_zd_buf(DOBW_1 downto 0);
                     DOPB_zd(DOPBW_1 downto 0) := DOPB_zd_buf(DOPBW_1 downto 0);

                  end if;

-------------------
                  if(DOBW <= DIBW) then
                     DOB_zd_buf(DIBW_1 downto 0) := MEM((ADDRESS_WRITE_B + DIBW_1) downto  ADDRESS_WRITE_B);
                     if(DOPBW_1 /= -1) then
                        DOPB_zd_buf(DIPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto  (16384 + ADDRESS_PARITY_WRITE_B));
                     end if;
-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's  or all 1's
                          
                     xout_we_seg1(1) := addrb_dly_sampled(4);
                     xout_we_seg1(0) := '0';
                     xout_we_seg2(1) := addrb_dly_sampled(4);
                     xout_we_seg2(0) := '1';

                     tmp_we(1) := addrb_dly_sampled(4);
                     tmp_we(0) := '0';
                     web_index := SLV_TO_INT(tmp_we);
                     if(web_dly_sampled(web_index) = '1') then
                        DOB_zd_buf((DIBW/2 - 1) downto 0)   := DIB_dly((DIBW/2 -1 ) downto 0);
                        if(DOPBW_1 /= -1) then
                           DOPB_zd_buf((DIPBW/2 - 1) downto 0)   := DIPB_dly((DIPBW/2 -1 ) downto 0);
                        end if;
                     elsif(web_dly_sampled(web_index) = '0') then
                        if(web_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= web_dly_sampled(SLV_TO_INT(xout_we_seg2))) then
                           DOB_zd_buf((DIBW/2 - 1) downto 0)   := (others => 'X');
                           if(DOPBW_1 /= -1) then
                              DOPB_zd_buf((DIPBW/2 - 1) downto 0)   := (others => 'X');
                           end if;
                        end if;
                     end if;

                     tmp_we(1) := addrb_dly_sampled(4);
                     tmp_we(0) := '1';
                     web_index := SLV_TO_INT(tmp_we);
                     if(web_dly_sampled(web_index) = '1') then
                        DOB_zd_buf(DIBW_1 downto DIBW/2 )   := DIB_dly(DIBW_1 downto DIBW/2);
                        if(DOPBW_1 /= -1) then
                           DOPB_zd_buf(DIPBW_1 downto DIPBW/2 )   := DIPB_dly(DIPBW_1 downto DIPBW/2);
                        end if;
                     elsif(web_dly_sampled(web_index) = '0') then
                        if(web_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= web_dly_sampled(SLV_TO_INT(xout_we_seg2))) then
                           DOB_zd_buf(DIBW_1 downto DIBW/2 )   := (others => 'X');
                           if(DOPBW_1 /= -1) then
                              DOPB_zd_buf(DIPBW_1 downto DIPBW/2 )   := (others => 'X');
                           end if;
                        end if;
                     end if;

-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's  or all 1's
                     if((web_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= web_dly_sampled(SLV_TO_INT(xout_we_seg2))) and (DOBW /= DIBW)) then
                        DOB_zd_buf(DIBW_1 downto 0) := (others => 'X');
                        DOPB_zd_buf(DIPBW_1 downto 0) := (others => 'X');
                     end if;

                     DOB_zd(DOBW_1 downto 0)   := DOB_zd_buf(((DOB_INDEX * DOBW) + DOBW_1) downto (DOB_INDEX * DOBW));
                     if(DOPBW_1 /= -1) then
                        DOPB_zd(DOPBW_1 downto 0) :=  DOPB_zd_buf(((DOPB_INDEX * DOPBW) + DOPBW_1) downto (DOPB_INDEX * DOPBW));
                     end if;

                  end if;

               ---------
               when 32 =>
               ---------
                  for i in 0 to 3 loop
                     if (web_dly_sampled(i) = '1') then
                        DOB_zd_buf(((DIBW/4)*(i+1) - 1) downto (DIBW/4)*i)   := DIB_dly(((DIBW/4)*(i+1) - 1) downto (DIBW/4)*i);
                        if(DOPBW_1 /= -1) then
                           DOPB_zd_buf(((DIPBW/4)*(i+1) - 1) downto (DIPBW/4)*i) := DIPB_dly(((DIPBW/4)*(i+1) - 1) downto (DIPBW/4)*i);
                        end if;
                     elsif (web_dly_sampled(i) = '0') then
-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's  or all 1's
                        DOB_zd_buf(((DIBW/4)*(i+1) - 1) downto (DIBW/4)*i)   := (others => 'X');
                        if(DOPBW_1 /= -1) then
                           DOPB_zd_buf(((DIPBW/4)*(i+1) - 1) downto (DIPBW/4)*i) := (others => 'X');
                        end if;
                     end if;
                  end loop;
-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's  or all 1's
                  if((web_dly_sampled(0) = '0') and (web_dly_sampled(1) = '0') and (web_dly_sampled(2) = '0') and  (web_dly_sampled(3) = '0')) then
                     DOB_zd_buf(DIBW_1 downto 0) := MEM((ADDRESS_WRITE_B + DIBW_1) downto  ADDRESS_WRITE_B);
                     if(DOPBW_1 /= -1) then
                        DOPB_zd_buf(DIPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto  (16384 + ADDRESS_PARITY_WRITE_B));
                     end if;
                  elsif(not((web_dly_sampled(0) = '1') and (web_dly_sampled(1) = '1') and (web_dly_sampled(2) = '1') and  (web_dly_sampled(3) = '1'))) then
                      if(DOBW /= DIBW) then
                         DOB_zd_buf(DIBW_1 downto 0) := (others => 'X');
                         if(DOPBW_1 /= -1) then
                            DOPB_zd_buf(DIPBW_1 downto 0) := (others => 'X');
                         end if;
                      end if;
                  end if;

                  DOB_zd(DOBW_1 downto 0)   := DOB_zd_buf(((DOB_INDEX * DOBW) + DOBW_1) downto (DOB_INDEX * DOBW));
                  if(DOPBW_1 /= -1) then
                     DOPB_zd(DOPBW_1 downto 0) :=  DOPB_zd_buf(((DOPB_INDEX * DOPBW) + DOPBW_1) downto (DOPB_INDEX * DOPBW));
                  end if;

                  when others =>
                     null;
               end case;

            elsif(wr_mode_b = "01") then
              DOB_zd(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto (ADDRESS_READ_B));
              if(DOPBW_1 /= -1) then
                  DOPB_zd(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto (16384 + ADDRESS_PARITY_READ_B));
              end if;
            elsif(wr_mode_b = "10") then
              case DIBW is
                 when 1|2|4|8 =>
                    tmp_we(1 downto 0) := addrb_dly_sampled( 4 downto 3);
                    web_index := SLV_TO_INT(tmp_we);
                    if (web_dly_sampled(web_index) = '0') then
                       DOB_zd(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto (ADDRESS_READ_B));
                       if(DOPBW_1 /= -1) then
                           DOPB_zd(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto (16384 + ADDRESS_PARITY_READ_B));
                       end if;
                    end if;
                 ----------
                 when 16|32 =>
                 ----------
                    if ((web_dly_sampled(0) = '0') and (web_dly_sampled(1) = '0') and (web_dly_sampled(2) = '0') and (web_dly_sampled(3) = '0'))then
                       DOB_zd(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto (ADDRESS_READ_B));
                       if(DOPBW_1 /= -1) then
                           DOPB_zd(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto (16384 + ADDRESS_PARITY_READ_B));
                       end if;
                    end if;
                 ----------
                 when others =>
                 ----------
                    null;
               end case;
          end if;
          end if;
            end if; -- /* end enb_dly_sampled = '1' */
      end if;

------------------------------------------------------------------------                       
------------ Port A  -- Memory Update ----------------------------------
------------------------------------------------------------------------                       

    if((GSR_CLKA_dly = '0') and rising_edge(CLKA_dly)) then
        if (ena_dly_sampled = '1') then
                case DIAW is
                  --------------
                  when 1|2|4|8 =>
                  --------------
                      tmp_we(1 downto 0) := addra_dly_sampled( 4 downto 3);
                      wea_index := SLV_TO_INT(tmp_we);
                      if (wea_dly_sampled(wea_index) = '1') then
                         if (VALID_ADDRA) then
                            MEM((ADDRESS_WRITE_A + DIAW_1) downto (ADDRESS_WRITE_A)) := DIA_dly(DIAW_1 downto 0);
                            if(DIPAW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto (16384 + ADDRESS_PARITY_WRITE_A)) := DIPA_dly(DIPAW_1 downto 0);
                            end if;
                         else
                          DOA_zd(DOAW_1 downto 0) := (others => 'X');
                          if(DOPAW_1 /= -1) then
                             DOPA_zd(DOPAW_1 downto 0) := (others => 'X');
                          end if;
                         end if; -- /* VAILD ADDRA */
                      end if; -- /*  wea_dly_sampled = '1' */ 

                  ---------
                  when 16 =>
                  ---------
                      tmp_we(1) := addra_dly_sampled(4);
                      tmp_we(0) := '0';
                      wea_index := SLV_TO_INT(tmp_we);
                      if (wea_dly_sampled(wea_index) = '1') then
                         if (VALID_ADDRA) then
                            MEM((ADDRESS_WRITE_A + DIAW/2 -1) downto (ADDRESS_WRITE_A)) := DIA_dly((DIAW/2 - 1) downto 0);
                            if(DIPAW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW/2 - 1) downto (16384 + ADDRESS_PARITY_WRITE_A)) := DIPA_dly((DIPAW/2 -1) downto 0);
                            end if;
                         end if; -- /* VAILD ADDRA */
                      end if; -- /*  wea_dly_sampled = '1' */ 

                      tmp_we(0) := '1';
                      wea_index := SLV_TO_INT(tmp_we);
                      if (wea_dly_sampled(wea_index) = '1') then
                         if (VALID_ADDRA) then
                            MEM((ADDRESS_WRITE_A + DIAW_1) downto (ADDRESS_WRITE_A + DIAW/2)) := DIA_dly(DIAW_1 downto DIAW/2);
                            if(DIPAW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto (16384 + ADDRESS_PARITY_WRITE_A + DIPAW/2)) := DIPA_dly(DIPAW_1 downto DIPAW/2);
                            end if;
                         end if; -- /* VAILD ADDRA */
                      end if; -- /*  wea_dly_sampled = '1' */ 

                  ---------
                  when 32 =>
                  ---------
                      wea_index := 0;
                      if (wea_dly_sampled(wea_index) = '1') then
                         if (VALID_ADDRA) then
                            MEM((ADDRESS_WRITE_A + (DIAW/4)*1 -1) downto (ADDRESS_WRITE_A)) := DIA_dly((((DIAW/4)*1) - 1) downto 0);
                            if(DIPAW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*1 - 1) downto (16384 + ADDRESS_PARITY_WRITE_A)) := DIPA_dly(((DIPAW/4)*1 -1) downto 0);
                            end if;
                         end if; -- /* VAILD ADDRA */
                      end if; -- /*  wea_dly_sampled = '1' */ 

                      wea_index := 1;
                      if (wea_dly_sampled(wea_index) = '1') then
                         if (VALID_ADDRA) then
                            MEM((ADDRESS_WRITE_A + (DIAW/4)*2 -1) downto (ADDRESS_WRITE_A + (DIAW/4)*1)) := DIA_dly((((DIAW/4)*2) - 1) downto (DIAW/4)*1);
                            if(DIPAW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*2 - 1) downto (16384 + ADDRESS_PARITY_WRITE_A  + (DIPAW/4)*1)) := DIPA_dly(((DIPAW/4)*2 -1) downto ((DIPAW/4)*1));
                            end if;
                         end if; -- /* VAILD ADDRA */
                      end if; -- /*  wea_dly_sampled = '1' */ 

                      wea_index := 2;
                      if (wea_dly_sampled(wea_index) = '1') then
                         if (VALID_ADDRA) then
                            MEM((ADDRESS_WRITE_A + (DIAW/4)*3 -1) downto (ADDRESS_WRITE_A + (DIAW/4)*2)) := DIA_dly((((DIAW/4)*3) - 1) downto (DIAW/4)*2);
                            if(DIPAW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*3 - 1) downto (16384 + ADDRESS_PARITY_WRITE_A  + (DIPAW/4)*2)) := DIPA_dly(((DIPAW/4)*3 -1) downto ((DIPAW/4)*2));
                            end if;
                         end if; -- /* VAILD ADDRA */
                      end if; -- /*  wea_dly_sampled = '1' */ 

                      wea_index := 3;
                      if (wea_dly_sampled(wea_index) = '1') then
                         if (VALID_ADDRA) then
                            MEM((ADDRESS_WRITE_A + (DIAW/4)*4 -1) downto (ADDRESS_WRITE_A + (DIAW/4)*3)) := DIA_dly((((DIAW/4)*4) - 1) downto (DIAW/4)*3);
                            if(DIPAW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*4 - 1) downto (16384 + ADDRESS_PARITY_WRITE_A  + (DIPAW/4)*3)) := DIPA_dly(((DIPAW/4)*4 -1) downto ((DIPAW/4)*3));
                            end if;
                         end if; -- /* VAILD ADDRA */
                      end if; -- /*  wea_dly_sampled = '1' */ 
                  when others =>
                     null;
                end case;

-----------------------  Start COLLISION MEMORY UPDATE A ------------------------------

        if(SimCollisionCheck_var /= 0) then
           if(clsn_type.write_write) then
              tmp_membuf := (others => '0');
              DOA_clsn_write_index := SLV_TO_INT(tmp_zero_write_a(4 downto 0));
              tmp_membuf(DIAW_1 downto 0) := MEM((ADDRESS_WRITE_A + DIAW_1) downto (ADDRESS_WRITE_A));
              MEM((ADDRESS_WRITE_A + DIAW_1) downto (ADDRESS_WRITE_A)) := tmp_membuf(DIAW_1 downto 0) xor clsn_xbufs.MEM1_clsn((DOA_clsn_write_index+DIAW_1) downto DOA_clsn_write_index);

             if((DIPAW_1 /= -1) and (DIPBW_1 /= -1)) then
                tmp_membuf := (others => '0');
                DOPA_clsn_write_index := SLV_TO_INT(tmp_zero_parity_write_a(1 downto 0));
                tmp_membuf(DIPAW_1 downto 0) :=  MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto (16384 + ADDRESS_PARITY_WRITE_A));
                MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto (16384 + ADDRESS_PARITY_WRITE_A)) := tmp_membuf(DIPAW_1 downto 0) xor clsn_xbufs.MEMP1_clsn((DOPA_clsn_write_index + DIPAW_1) downto DOPA_clsn_write_index);
              end if;
           end if;
        end if;
                
-----------------------  END COLLISION MEMORY UPDATE A   ------------------------------
                 
            end if; -- /* end ena_dly_sampled = '1' */
      end if;
------------------------------------------------------------------------                       
------------ Port B  -- Memory Update ----------------------------------
------------------------------------------------------------------------                       

    if((GSR_CLKB_dly = '0') and rising_edge(CLKB_dly)) then
        if (enb_dly_sampled = '1') then
                case DIBW is
                  --------------
                  when 1|2|4|8 =>
                  --------------
                      tmp_we(1 downto 0) := addrb_dly_sampled( 4 downto 3);
                      web_index := SLV_TO_INT(tmp_we);
                      if (web_dly_sampled(web_index) = '1') then
                         if (VALID_ADDRB) then
                            MEM((ADDRESS_WRITE_B + DIBW_1) downto (ADDRESS_WRITE_B)) := DIB_dly(DIBW_1 downto 0);
                            if(DIPBW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto (16384 + ADDRESS_PARITY_WRITE_B)) := DIPB_dly(DIPBW_1 downto 0);
                            end if;
                         else
                          DOB_zd(DOBW_1 downto 0) := (others => 'X');
                          if(DOPBW_1 /= -1) then
                             DOPB_zd(DOPBW_1 downto 0) := (others => 'X');
                          end if;
                         end if; -- /* VAILD ADDRB */
                      end if; -- /*  web_dly_sampled = '1' */ 

                  ---------
                  when 16 =>
                  ---------
                      tmp_we(1) := addrb_dly_sampled(4);
                      tmp_we(0) := '0';
                      web_index := SLV_TO_INT(tmp_we);
                      if (web_dly_sampled(web_index) = '1') then
                         if (VALID_ADDRB) then
                            MEM((ADDRESS_WRITE_B + DIBW/2 -1) downto (ADDRESS_WRITE_B)) := DIB_dly((DIBW/2 - 1) downto 0);
                            if(DIPBW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW/2 - 1) downto (16384 + ADDRESS_PARITY_WRITE_B)) := DIPB_dly((DIPBW/2 -1) downto 0);
                            end if;
                         end if; -- /* VAILD ADDRB */
                      end if; -- /*  web_dly_sampled = '1' */ 

                      tmp_we(0) := '1';
                      web_index := SLV_TO_INT(tmp_we);
                      if (web_dly_sampled(web_index) = '1') then
                         if (VALID_ADDRB) then
                            MEM((ADDRESS_WRITE_B + DIBW_1) downto (ADDRESS_WRITE_B + DIBW/2)) := DIB_dly(DIBW_1 downto DIBW/2);
                            if(DIPBW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto (16384 + ADDRESS_PARITY_WRITE_B + DIPBW/2)) := DIPB_dly(DIPBW_1 downto DIPBW/2);
                            end if;
                         end if; -- /* VAILD ADDRB */
                      end if; -- /*  web_dly_sampled = '1' */ 

                  ---------
                  when 32 =>
                  ---------
                      web_index := 0;
                      if (web_dly_sampled(web_index) = '1') then
                         if (VALID_ADDRB) then
                            MEM((ADDRESS_WRITE_B + (DIBW/4)*1 -1) downto (ADDRESS_WRITE_B)) := DIB_dly((((DIBW/4)*1) - 1) downto 0);
                            if(DIPBW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*1 - 1) downto (16384 + ADDRESS_PARITY_WRITE_B)) := DIPB_dly(((DIPBW/4)*1 -1) downto 0);
                            end if;
                         end if; -- /* VAILD ADDRB */
                      end if; -- /*  web_dly_sampled = '1' */ 

                      web_index := 1;
                      if (web_dly_sampled(web_index) = '1') then
                         if (VALID_ADDRB) then
                            MEM((ADDRESS_WRITE_B + (DIBW/4)*2 -1) downto (ADDRESS_WRITE_B + (DIBW/4)*1)) := DIB_dly((((DIBW/4)*2) - 1) downto (DIBW/4)*1);
                            if(DIPBW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*2 - 1) downto (16384 + ADDRESS_PARITY_WRITE_B  + (DIPBW/4)*1)) := DIPB_dly(((DIPBW/4)*2 -1) downto ((DIPBW/4)*1));
                            end if;
                         end if; -- /* VAILD ADDRB */
                      end if; -- /*  web_dly_sampled = '1' */ 

                      web_index := 2;
                      if (web_dly_sampled(web_index) = '1') then
                         if (VALID_ADDRB) then
                            MEM((ADDRESS_WRITE_B + (DIBW/4)*3 -1) downto (ADDRESS_WRITE_B + (DIBW/4)*2)) := DIB_dly((((DIBW/4)*3) - 1) downto (DIBW/4)*2);
                            if(DIPBW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*3 - 1) downto (16384 + ADDRESS_PARITY_WRITE_B  + (DIPBW/4)*2)) := DIPB_dly(((DIPBW/4)*3 -1) downto ((DIPBW/4)*2));
                            end if;
                         end if; -- /* VAILD ADDRB */
                      end if; -- /*  web_dly_sampled = '1' */ 

                      web_index := 3;
                      if (web_dly_sampled(web_index) = '1') then
                         if (VALID_ADDRB) then
                            MEM((ADDRESS_WRITE_B + (DIBW/4)*4 -1) downto (ADDRESS_WRITE_B + (DIBW/4)*3)) := DIB_dly((((DIBW/4)*4) - 1) downto (DIBW/4)*3);
                            if(DIPBW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*4 - 1) downto (16384 + ADDRESS_PARITY_WRITE_B  + (DIPBW/4)*3)) := DIPB_dly(((DIPBW/4)*4 -1) downto ((DIPBW/4)*3));
                            end if;
                         end if; -- /* VAILD ADDRB */
                      end if; -- /*  web_dly_sampled = '1' */ 
                  when others =>
                     null;
                end case;
                 
-----------------------  Start COLLISION MEMORY UPDATE B ------------------------------

        if(SimCollisionCheck_var /= 0) then
           if(clsn_type.write_write) then
              tmp_membuf := (others => '0');
              DOB_clsn_write_index := SLV_TO_INT(tmp_zero_write_b(4 downto 0));
              tmp_membuf(DIBW_1 downto 0) := MEM((ADDRESS_WRITE_B + DIBW_1) downto (ADDRESS_WRITE_B));
              MEM((ADDRESS_WRITE_B + DIBW_1) downto (ADDRESS_WRITE_B)) := tmp_membuf(DIBW_1 downto 0) xor clsn_xbufs.MEM1_clsn((DOB_clsn_write_index+DIBW_1) downto DOB_clsn_write_index);

             if((DIPBW_1 /= -1) and (DIPAW_1 /= -1)) then
                tmp_membuf := (others => '0');
                DOPB_clsn_write_index := SLV_TO_INT(tmp_zero_parity_write_b(1 downto 0));
                tmp_membuf(DIPBW_1 downto 0) :=  MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto (16384 + ADDRESS_PARITY_WRITE_B));
                MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto (16384 + ADDRESS_PARITY_WRITE_B)) := tmp_membuf(DIPBW_1 downto 0) xor clsn_xbufs.MEMP1_clsn((DOPB_clsn_write_index + DIPBW_1) downto DOPB_clsn_write_index);
              end if;
           end if;
        end if;
                
-----------------------  END COLLISION MEMORY UPDATE B   ------------------------------

            end if; -- /* end enb_dly_sampled = '1' */
      end if;
--=======================================================================================
----- Port A

    DOA_viol(0)  <= ViolationA xor DOA_zd(0) xor DOA_clsn_zero(0);
    DOA_viol(1)  <= ViolationA xor DOA_zd(1) xor DOA_clsn_zero(1);
    DOA_viol(2)  <= ViolationA xor DOA_zd(2) xor DOA_clsn_zero(2);
    DOA_viol(3)  <= ViolationA xor DOA_zd(3) xor DOA_clsn_zero(3);
    DOA_viol(4)  <= ViolationA xor DOA_zd(4) xor DOA_clsn_zero(4);
    DOA_viol(5)  <= ViolationA xor DOA_zd(5) xor DOA_clsn_zero(5);
    DOA_viol(6)  <= ViolationA xor DOA_zd(6) xor DOA_clsn_zero(6);
    DOA_viol(7)  <= ViolationA xor DOA_zd(7) xor DOA_clsn_zero(7);
    DOA_viol(8)  <= ViolationA xor DOA_zd(8) xor DOA_clsn_zero(8);
    DOA_viol(9)  <= ViolationA xor DOA_zd(9) xor DOA_clsn_zero(9);
    DOA_viol(10) <= ViolationA xor DOA_zd(10) xor DOA_clsn_zero(10);
    DOA_viol(11) <= ViolationA xor DOA_zd(11) xor DOA_clsn_zero(11);
    DOA_viol(12) <= ViolationA xor DOA_zd(12) xor DOA_clsn_zero(12);
    DOA_viol(13) <= ViolationA xor DOA_zd(13) xor DOA_clsn_zero(13);
    DOA_viol(14) <= ViolationA xor DOA_zd(14) xor DOA_clsn_zero(14);
    DOA_viol(15) <= ViolationA xor DOA_zd(15) xor DOA_clsn_zero(15);
    DOA_viol(16) <= ViolationA xor DOA_zd(16) xor DOA_clsn_zero(16);
    DOA_viol(17) <= ViolationA xor DOA_zd(17) xor DOA_clsn_zero(17);
    DOA_viol(18) <= ViolationA xor DOA_zd(18) xor DOA_clsn_zero(18);
    DOA_viol(19) <= ViolationA xor DOA_zd(19) xor DOA_clsn_zero(19);
    DOA_viol(20) <= ViolationA xor DOA_zd(20) xor DOA_clsn_zero(20);
    DOA_viol(21) <= ViolationA xor DOA_zd(21) xor DOA_clsn_zero(21);
    DOA_viol(22) <= ViolationA xor DOA_zd(22) xor DOA_clsn_zero(22);
    DOA_viol(23) <= ViolationA xor DOA_zd(23) xor DOA_clsn_zero(23);
    DOA_viol(24) <= ViolationA xor DOA_zd(24) xor DOA_clsn_zero(24);
    DOA_viol(25) <= ViolationA xor DOA_zd(25) xor DOA_clsn_zero(25);
    DOA_viol(26) <= ViolationA xor DOA_zd(26) xor DOA_clsn_zero(26);
    DOA_viol(27) <= ViolationA xor DOA_zd(27) xor DOA_clsn_zero(27);
    DOA_viol(28) <= ViolationA xor DOA_zd(28) xor DOA_clsn_zero(28);
    DOA_viol(29) <= ViolationA xor DOA_zd(29) xor DOA_clsn_zero(29);
    DOA_viol(30) <= ViolationA xor DOA_zd(30) xor DOA_clsn_zero(30);
    DOA_viol(31) <= ViolationA xor DOA_zd(31) xor DOA_clsn_zero(31);
    DOPA_viol(0) <= ViolationA xor DOPA_zd(0) xor DOPA_clsn_zero(0);
    DOPA_viol(1) <= ViolationA xor DOPA_zd(1) xor DOPA_clsn_zero(1);
    DOPA_viol(2) <= ViolationA xor DOPA_zd(2) xor DOPA_clsn_zero(2);
    DOPA_viol(3) <= ViolationA xor DOPA_zd(3) xor DOPA_clsn_zero(3);

----- Port B

    DOB_viol(0)  <= ViolationB xor DOB_zd(0) xor DOB_clsn_zero(0);
    DOB_viol(1)  <= ViolationB xor DOB_zd(1) xor DOB_clsn_zero(1);
    DOB_viol(2)  <= ViolationB xor DOB_zd(2) xor DOB_clsn_zero(2);
    DOB_viol(3)  <= ViolationB xor DOB_zd(3) xor DOB_clsn_zero(3);
    DOB_viol(4)  <= ViolationB xor DOB_zd(4) xor DOB_clsn_zero(4);
    DOB_viol(5)  <= ViolationB xor DOB_zd(5) xor DOB_clsn_zero(5);
    DOB_viol(6)  <= ViolationB xor DOB_zd(6) xor DOB_clsn_zero(6);
    DOB_viol(7)  <= ViolationB xor DOB_zd(7) xor DOB_clsn_zero(7);
    DOB_viol(8)  <= ViolationB xor DOB_zd(8) xor DOB_clsn_zero(8);
    DOB_viol(9)  <= ViolationB xor DOB_zd(9) xor DOB_clsn_zero(9);
    DOB_viol(10) <= ViolationB xor DOB_zd(10) xor DOB_clsn_zero(10);
    DOB_viol(11) <= ViolationB xor DOB_zd(11) xor DOB_clsn_zero(11);
    DOB_viol(12) <= ViolationB xor DOB_zd(12) xor DOB_clsn_zero(12);
    DOB_viol(13) <= ViolationB xor DOB_zd(13) xor DOB_clsn_zero(13);
    DOB_viol(14) <= ViolationB xor DOB_zd(14) xor DOB_clsn_zero(14);
    DOB_viol(15) <= ViolationB xor DOB_zd(15) xor DOB_clsn_zero(15);
    DOB_viol(16) <= ViolationB xor DOB_zd(16) xor DOB_clsn_zero(16);
    DOB_viol(17) <= ViolationB xor DOB_zd(17) xor DOB_clsn_zero(17);
    DOB_viol(18) <= ViolationB xor DOB_zd(18) xor DOB_clsn_zero(18);
    DOB_viol(19) <= ViolationB xor DOB_zd(19) xor DOB_clsn_zero(19);
    DOB_viol(20) <= ViolationB xor DOB_zd(20) xor DOB_clsn_zero(20);
    DOB_viol(21) <= ViolationB xor DOB_zd(21) xor DOB_clsn_zero(21);
    DOB_viol(22) <= ViolationB xor DOB_zd(22) xor DOB_clsn_zero(22);
    DOB_viol(23) <= ViolationB xor DOB_zd(23) xor DOB_clsn_zero(23);
    DOB_viol(24) <= ViolationB xor DOB_zd(24) xor DOB_clsn_zero(24);
    DOB_viol(25) <= ViolationB xor DOB_zd(25) xor DOB_clsn_zero(25);
    DOB_viol(26) <= ViolationB xor DOB_zd(26) xor DOB_clsn_zero(26);
    DOB_viol(27) <= ViolationB xor DOB_zd(27) xor DOB_clsn_zero(27);
    DOB_viol(28) <= ViolationB xor DOB_zd(28) xor DOB_clsn_zero(28);
    DOB_viol(29) <= ViolationB xor DOB_zd(29) xor DOB_clsn_zero(29);
    DOB_viol(30) <= ViolationB xor DOB_zd(30) xor DOB_clsn_zero(30);
    DOB_viol(31) <= ViolationB xor DOB_zd(31) xor DOB_clsn_zero(31);
    DOPB_viol(0) <= ViolationB xor DOPB_zd(0) xor DOPB_clsn_zero(0);
    DOPB_viol(1) <= ViolationB xor DOPB_zd(1) xor DOPB_clsn_zero(1);
    DOPB_viol(2) <= ViolationB xor DOPB_zd(2) xor DOPB_clsn_zero(2);
    DOPB_viol(3) <= ViolationB xor DOPB_zd(3) xor DOPB_clsn_zero(3);

    wait on ADDRA_dly, ADDRB_dly, CLKA_dly, CLKB_dly, DIA_dly, DIB_dly, DIPA_dly, DIPB_dly, ENA_dly, ENB_dly, GSR_ipd, GSR_CLKA_dly, GSR_CLKB_dly, SSRA_dly, SSRB_dly, WEA_dly, WEB_dly;
  end process VITALBehavior;
----- ###############################################################################

   prcs_output:process (DOA_viol, DOPA_viol, DOB_viol, DOPB_viol)
   begin
       DOA    <= DOA_viol after SYNC_PATH_DELAY;
       DOPA   <= DOPA_viol after SYNC_PATH_DELAY;
       DOB    <= DOB_viol after SYNC_PATH_DELAY;
       DOPB   <= DOPB_viol after SYNC_PATH_DELAY;
   end process prcs_output;

end RAMB16BWE_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Function Simulation Library Component
--  /   /                  Configuration Simulation Model
-- /___/   /\     Filename : sim_config_s3a.vhd
-- \   \  /  \    Timestamp : 
--  \___\/\___\
--
-- Revision:
--    03/07/07 - Initial version.
--    06/11/07 - Change DEVICE_ID to bit vector (CR441606).
-- End Revision

----- CELL SIM_CONFIG_S3A  -----
library IEEE;
use IEEE.std_logic_1164.all;




library STD;
use STD.TEXTIO.all;

library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;

entity SIM_CONFIG_S3A is
  generic (

    DEVICE_ID : bit_vector := X"00000000"

    );

  port (
                   CSOB : out std_ulogic := '1';
                   DONE : inout std_ulogic;
                   CCLK : in  std_ulogic := '0';
                   D : inout std_logic_vector(7 downto 0);
                   DCMLOCK : in  std_ulogic := '0';
                   CSIB : in  std_ulogic := '0';
                   INITB : inout std_ulogic := 'H';
                   M : in  std_logic_vector(2 downto 0) := "000";
                   PROGB : in  std_ulogic := '0';
                   RDWRB : in  std_ulogic := '0'
                   );
 


end SIM_CONFIG_S3A;

architecture SIM_CONFIG_S3A_V of SIM_CONFIG_S3A is

  function crc_next (
      crc_currf : in std_logic_vector(21 downto 0);
      crc_inputf : in std_logic_vector(21 downto 0)
      ) return  std_logic_vector 
   is
      variable i_crc : integer;
      variable crc_next_v : std_logic_vector(21 downto 0);
  begin
    i_crc := 21;
    for i in 21 downto 16 loop
       crc_next_v(i_crc) := crc_currf(i_crc-1) xor crc_inputf(i_crc);
        i_crc := i_crc -1;
    end loop;

    crc_next_v(15) := crc_currf(14) xor crc_inputf(15) xor crc_currf(21);

    i_crc := 14;
   for i in 14 downto 13 loop
       crc_next_v(i_crc) := crc_currf(i_crc-1) xor crc_inputf(i_crc);
       i_crc := i_crc -1;
   end loop;

   crc_next_v(12) := crc_currf(11) xor crc_inputf(12) xor crc_currf(21);

   i_crc := 11;
   for i in 11 downto 8 loop 
       crc_next_v(i_crc) := crc_currf(i_crc-1) xor crc_inputf(i_crc);
       i_crc := i_crc -1;
   end loop;

   crc_next_v(7) := crc_currf(6) xor crc_inputf(7) xor crc_currf(21);

   i_crc := 6;
   for i in 6 downto 1 loop 
       crc_next_v(i_crc) := crc_currf(i_crc-1) xor crc_inputf(i_crc);
       i_crc := i_crc -1;
   end loop;

   crc_next_v(0) :=  crc_inputf(0) xor crc_currf(21);

   return crc_next_v;
  end crc_next;

function bit_revers8 ( din8 : in std_logic_vector(7 downto 0)) 
                   return  std_logic_vector is 
  variable bit_rev8 : std_logic_vector(7 downto 0);
  begin
      bit_rev8(0) := din8(7);
      bit_rev8(1) := din8(6);
      bit_rev8(2) := din8(5);
      bit_rev8(3) := din8(4);
      bit_rev8(4) := din8(3);
      bit_rev8(5) := din8(2);
      bit_rev8(6) := din8(1);
      bit_rev8(7) := din8(0);

     return bit_rev8;
  end bit_revers8;


  constant cfg_Tprog : time := 300000 ps;   -- min PROG must be low, 300 ns
  constant cfg_Tpl : time :=   100000 ps;  -- max program latency us.
  constant STARTUP_PH0 : std_logic_vector(2 downto 0) := "000";
  constant STARTUP_PH1 : std_logic_vector(2 downto 0) := "001";
  constant STARTUP_PH2 : std_logic_vector(2 downto 0) := "010";
  constant STARTUP_PH3 : std_logic_vector(2 downto 0) := "011";
  constant STARTUP_PH4 : std_logic_vector(2 downto 0) := "100";
  constant STARTUP_PH5 : std_logic_vector(2 downto 0) := "101";
  constant STARTUP_PH6 : std_logic_vector(2 downto 0) := "110";
  constant STARTUP_PH7 : std_logic_vector(2 downto 0) := "111";
  signal GSR : std_ulogic := '1';
  signal GTS : std_ulogic := '1';
  signal GWE : std_ulogic := '0';
  signal cclk_in : std_ulogic;
  signal csi_b_in : std_ulogic;
  signal prog_b_in : std_ulogic;
  signal rdwr_b_in : std_ulogic;
  signal crc_err_flag_reg : std_ulogic := '0';
  signal crc_err_flag_tot : std_ulogic;
  signal mode_sample_flag : std_ulogic := '0';
  signal init_b_p : std_ulogic := '1';
  signal done_o : std_ulogic := '0';
  signal done_in : std_ulogic ;
  signal por_b : std_ulogic := '0';
  signal prog_b_t : std_ulogic;
  signal m_in : std_logic_vector(2 downto 0);
  signal mode_pin_in : std_logic_vector(2 downto 0) := "000";
  signal d_in : std_logic_vector(7 downto 0) := "00000000";
  signal d_out : std_logic_vector(7 downto 0) := "00000000";
  signal prog_pulse_low_edge : time := 0 ps;
  signal prog_pulse_low : time := 0 ps;
  signal wr_cnt : integer := 0;
  signal conti_data_cnt : integer := 0; 
  signal rd_data_cnt : integer := 0;
  signal abort_cnt : integer := 0;
  signal csbo_flag : std_ulogic := '0';
  signal pack_in_reg : std_logic_vector(15 downto 0) := X"0000";
  signal reg_addr : std_logic_vector(5 downto 0) := "000000";
  signal rd_reg_addr : std_logic_vector(5 downto 0) := "000000";
  signal  new_data_in_flag : std_ulogic := '0';
  signal wr_flag : std_ulogic := '0';
  signal rd_flag : std_ulogic := '0';
  signal cmd_wr_flag : std_ulogic := '0';
  signal cmd_rd_flag : std_ulogic := '0';
  signal bus_sync_flag : std_ulogic := '0';
  signal csi_sync : std_ulogic := '0';
  signal rd_sw_en : std_ulogic := '0';
  signal conti_data_flag : std_ulogic := '0';
  signal conti_data_flag_set : std_ulogic := '0';
  signal st_state :  std_logic_vector(2 downto 0) := STARTUP_PH0;
  signal nx_st_state :  std_logic_vector(2 downto 0) := STARTUP_PH0;
  signal startup_begin_flag : std_ulogic := '0';
  signal startup_end_flag : std_ulogic := '0';
  signal cmd_reg_new_flag : std_ulogic := '0'; 
  signal far_maj_min_flag : std_ulogic := '0';
  signal crc_reset : std_ulogic := '0';
  signal crc_rst : std_ulogic := '0';
  signal crc_ck : std_ulogic := '0';
  signal crc_err_flag : std_ulogic := '0';
  signal crc_en : std_ulogic := '0';
  signal desync_flag : std_ulogic := '0';
  signal  crc_curr : std_logic_vector(21 downto 0) := "0000000000000000000000";
  signal gwe_out : std_ulogic := '0';
  signal gts_out : std_ulogic := '1';
  signal d_o : std_logic_vector(7 downto 0) := "00000000";
  signal outbus : std_logic_vector(7 downto 0) := "00000000";
  signal reboot_set : std_ulogic := '0';
  signal gsr_set : std_ulogic := '0';
  signal  gts_usr_b : std_ulogic := '1';
  signal done_pin_drv : std_ulogic := '0';
  signal crc_bypass : std_ulogic := '0';
  signal reset_on_err : std_ulogic := '0';
  signal sync_timeout : std_ulogic := '0';
  signal crc_reg : std_logic_vector (31 downto 0); 
  signal idcode_reg : std_logic_vector (31 downto 0); 
  signal idcode_tmp : std_logic_vector (31 downto 0); 
  signal far_min_reg : std_logic_vector (15 downto 0);
  signal far_maj_reg : std_logic_vector (15 downto 0);
  signal fdri_reg    : std_logic_vector (15 downto 0);
  signal fdro_reg    : std_logic_vector (15 downto 0);
  signal ctl_reg     : std_logic_vector (15 downto 0);
  signal cmd_reg     : std_logic_vector (4 downto 0);
  signal general1_reg : std_logic_vector (15 downto 0);
  signal mask_reg    : std_logic_vector (15 downto 0);
  signal lout_reg    : std_logic_vector (15 downto 0);
  signal cor1_reg    : std_logic_vector (15 downto 0);
  signal cor2_reg    : std_logic_vector (15 downto 0);
  signal pwrdn_reg   : std_logic_vector (15 downto 0);
  signal flr_reg     : std_logic_vector (15 downto 0);
  signal snowplow_reg : std_logic_vector (15 downto 0);
  signal hc_opt_reg  : std_logic_vector (15 downto 0);
  signal csbo_reg    : std_logic_vector (15 downto 0);
  signal general2_reg : std_logic_vector (15 downto 0);
  signal mode_reg    : std_logic_vector (15 downto 0);
  signal pu_gwe_reg  : std_logic_vector (15 downto 0);
  signal pu_gts_reg  : std_logic_vector (15 downto 0);
  signal mfwr_reg    : std_logic_vector (15 downto 0);
  signal cclk_freq_reg : std_logic_vector (15 downto 0);
  signal seu_opt_reg : std_logic_vector (15 downto 0);
  signal exp_sign_reg : std_logic_vector (31 downto 0);
  signal rdbk_sign_reg : std_logic_vector (31 downto 0);
  signal shutdown_set : std_ulogic := '0';
  signal desynch_set : std_ulogic := '0';
  signal done_cycle_reg : std_logic_vector (2 downto 0) := "100";
  signal gts_cycle_reg : std_logic_vector (2 downto 0) := "101";
  signal gwe_cycle_reg : std_logic_vector (2 downto 0) := "110";
  signal ghigh_b : std_ulogic := '0';
  signal eos_startup : std_ulogic := '0';
  signal startup_set : std_ulogic := '0';
  signal startup_set_pulse  : std_logic_vector (1 downto 0) := "00";
  signal abort_out_en : std_ulogic := '0';
  signal id_error_flag : std_ulogic := '0';
  signal iprog_b : std_ulogic := '1';
  signal abort_flag_wr : std_ulogic := '0';
  signal abort_flag_rd : std_ulogic := '0';
  signal abort_status : std_logic_vector (7 downto 0) := "00000000";
  signal persist_en : std_ulogic := '0';
  signal rst_sync : std_ulogic := '0';
  signal  abort_dis: std_ulogic := '0';
  signal lock_cycle_reg : std_logic_vector (2 downto 0) := "000";
  signal rbcrc_no_pin : std_ulogic := '0';
  signal abort_flag_rst : std_ulogic := '0';
  signal gsr_st_out : std_ulogic := '1';
  signal gsr_cmd_out : std_ulogic := '0';
  signal d_o_en : std_ulogic := '0';
  signal stat_reg : std_logic_vector (15 downto 0) := X"0000";
  signal rst_intl : std_ulogic := '0';
  signal rw_en : std_ulogic := '0';
  signal gsr_out : std_ulogic;
  signal cfgerr_b_flag : std_ulogic;
  signal abort_flag : std_ulogic := '0';
  signal  downcont : std_logic_vector (27 downto 0)  := "0000000000000000000000000000";
  signal  downcont_int : integer := 0;
  signal type2_flag : std_ulogic := '0';
  signal rst_en : std_ulogic := '1';
  signal prog_b_a : std_ulogic := '1';
  signal csbo_b_out : std_ulogic := '1';
  signal dcm_locked : std_ulogic;
  signal d_out_en : std_ulogic := '0';
  signal device_id_reg : std_logic_vector (31 downto 0)  := TO_STDLOGICVECTOR(DEVICE_ID);


begin

    CSOB <= csbo_b_out;
    INITB <=  (not crc_err_flag_tot) when mode_sample_flag = '1' else init_b_p when init_b_p ='0' else 'H';
    DONE <= done_o;
    done_in <= DONE;


    cclk_in <= CCLK;
    dcm_locked <= DCMLOCK;
    csi_b_in <= CSIB;
    d_in <= D;
    D <=  d_out when d_out_en = '1' else "ZZZZZZZZ";

    m_in <= M;
    prog_b_in <= PROGB;
    rdwr_b_in <= RDWRB;
    

        INIPROC : process
        begin
          if (DEVICE_ID = X"00000000") then
             assert FALSE report "Attribute Syntax Error : The attribute DEVICE_ID on  SIM_CONFIG_S3A is not set." severity error;
          end if;
          wait;
        end process;



    GSR <= gsr_out;
    GTS <= gts_out;
    GWE <= gwe_out;
    csbo_b_out <= '0' when (csbo_flag= '1') else '1';
    cfgerr_b_flag <= rw_en and (not id_error_flag) and (not crc_err_flag_reg);
    crc_err_flag_tot <= id_error_flag or crc_err_flag_reg;
    d_out <= abort_status when (abort_out_en = '1') else outbus;
    d_out_en <= d_o_en;
    crc_en <=  '1';

    process (abort_out_en, csi_b_in, rdwr_b_in, rd_flag) begin
    if (abort_out_en='1') then
       d_o_en <= '1';
    else
       d_o_en <= rdwr_b_in and (not csi_b_in) and rd_flag;
    end if;
    end process;


    process  begin
      if (prog_b_in'event and prog_b_in = '0') then 
         rst_en <= '0';
         wait for cfg_Tprog;
         wait for 1 ps;
         rst_en <= '1';
      end if;
      wait on prog_b_in;
    end process;

  process  begin
   if (rising_edge(rst_en)) then
             init_b_p <= '0';
             wait until (rising_edge (prog_b_in));
             init_b_p <= '1' after cfg_Tpl;
   end if;
   wait on rst_en;
  end process;
      

  process  begin
    if (rst_en = '0') then
       prog_b_a <= '1';
    elsif (rising_edge(rst_en)) then 
       if (prog_b_in = '1' and prog_pulse_low=cfg_Tprog) then 
           prog_b_a <= '0';
           wait for 500 ps;
           prog_b_a <= '1';
       elsif (prog_b_in = '0') then
          prog_b_a <= '0';
          wait until (rising_edge(prog_b_in));
          prog_b_a <= '1';
       end if;
    end if;
   wait on rst_en, prog_b_in;
  end process;

  process 
  begin
    por_b <= '0';
    por_b <=  '1' after 400 ns;
  wait;
  end process;

  prog_b_t <= prog_b_a  and iprog_b  and  por_b;

  rst_intl <=  '0' when (prog_b_t='0') else '1';

  process (INITB, prog_b_t)
    variable Message : line;
  begin
   if (falling_edge (prog_b_t)) then
      mode_sample_flag <= '0';
   elsif (rising_edge(INITB)) then
      if (mode_sample_flag = '0') then
        if(prog_b_t = '1') then
           mode_pin_in <= m_in;
           mode_sample_flag <= '1' after 1 ps;
           if (m_in /= "110") then
              Write ( Message, string'(" Error: input M is "));
              Write ( Message, string'(SLV_TO_STR(m_in)));
              Write ( Message, string'(" . Only Slave SelectMAP mode M=110 supported on SIM_CONFIG_S3A."));
              assert false report Message.all severity error;
              DEALLOCATE (Message);
           end if;   
        elsif (NOW > 0 ps) then
            assert false report "Error: PROGB is not high when INITB goes high on SIM_CONFIG_S3A." severity error;
       end if;
    end if;
   end if;
  end process;
           

  process (m_in) begin
    if (mode_sample_flag = '1' and persist_en = '1') then
       assert false report "Error : Mode pine M[2:0] changed after rising edge of INITB on SIM_CONFIG_S3A." severity error;
    end if;
  end process;

  prog_pulse_P : process (prog_b_in)
     variable prog_pulse_low : time;
     variable Message : line;
  begin
    if (falling_edge (prog_b_in)) then
       prog_pulse_low_edge <= NOW;
    else
      if (NOW > 0 ps ) then
         prog_pulse_low := NOW - prog_pulse_low_edge;
         if (prog_pulse_low < cfg_Tprog ) then
             Write ( Message, string'(" Error: Low time of PROGB is less than required minimum Tprogram time "));
             Write ( Message, prog_pulse_low);
             Write ( Message, string'(" ."));
             assert false report Message.all severity error;
         end if;
      end if;
    end if;
  end process;


     rw_en <= '1' when ((mode_sample_flag = '1') and  (csi_b_in = '0')) else  '0';
     desync_flag <= (not rst_intl) or desynch_set or crc_err_flag or id_error_flag;
 
   process (cclk_in) begin
   if (rising_edge(cclk_in)) then
       csi_sync <= csi_b_in;
     end if;
   end process;
 
   process (cclk_in, rdwr_b_in) begin
      if (rdwr_b_in = '0') then
           rd_sw_en <= '0';
      elsif (rising_edge(cclk_in)) then
           if (csi_sync = '1' and rdwr_b_in = '1') then
              rd_sw_en <= '1';
           end if;
      end if;
   end process;


    bus_sync_p : process (cclk_in, desync_flag)
      variable tmp_byte  : std_logic_vector (7 downto 0);
    begin
      if (desync_flag = '1') then
          pack_in_reg <= "0000000000000000";
          new_data_in_flag <= '0';
          bus_sync_flag <= '0';
          wr_cnt <= 0;
          wr_flag <= '0';
          rd_flag <= '0';
      elsif (rising_edge(cclk_in)) then
       if (rw_en  =  '1' ) then
         if (rdwr_b_in  =  '0') then
           wr_flag <= '1';
           rd_flag <= '0';
               tmp_byte := bit_revers8(d_in(7 downto 0));
               if (bus_sync_flag  =  '0') then
                  if (pack_in_reg(7 downto 0) = "10101010" and tmp_byte = "10011001") then
                          bus_sync_flag <= '1';
                          new_data_in_flag <= '0';
                          wr_cnt <= 0;
                   else 
                      pack_in_reg(7 downto 0) <= tmp_byte;
                   end if;
               else 
                 if (wr_cnt  =  0) then
                    pack_in_reg(15 downto 8) <= tmp_byte;
                     new_data_in_flag <= '0';
                     wr_cnt <=  1;
                 elsif (wr_cnt  =  1) then
                     pack_in_reg(7 downto 0) <= tmp_byte;
                     new_data_in_flag <= '1';
                     wr_cnt <= 0;
                 end if;
             end if;
        else                      --rdwr_b_in <= '1'
            wr_flag <= '0';
            new_data_in_flag <= '0';
            if (rd_sw_en = '1') then
               rd_flag <= '1';
            end if;
       end if;
     else                        --rw_en <= '0'
            wr_flag <= '0';
            rd_flag <= '0';
            new_data_in_flag <= '0';
     end if;
    end if;
   end process;
           
   pack_decode_p :  process (cclk_in, rst_intl) 
      variable tmp_v : std_logic_vector(5 downto 0);
      variable tmp_v28 : std_logic_vector(27 downto 0);
      variable idcode_tmp : std_logic_vector(31 downto 0);
      variable message_line : line;
      variable csbo_cnt : integer := 0;
      variable crc_new : std_logic_vector(21 downto 0) := "0000000000000000000000";
      variable crc_input : std_logic_vector(21 downto 0) := "0000000000000000000000";
   begin
      if (rst_intl  =  '0') then
         conti_data_flag <= '0';
         conti_data_cnt <= 0;
         cmd_wr_flag <= '0';
         cmd_rd_flag <= '0';
         id_error_flag <= '0';
         far_maj_min_flag <= '0';
         cmd_reg_new_flag <= '0';
         crc_curr(21 downto 0) <= "0000000000000000000000";
         crc_ck <= '0';
         csbo_cnt := 0;
         csbo_flag <= '0';
         downcont <= "0000000000000000000000000000";
         downcont_int <= 0;
         rd_data_cnt <= 0;
      elsif (falling_edge(cclk_in)) then 
        if (crc_reset  =  '1' ) then
            crc_reg(31 downto 0) <= X"00000000";
            exp_sign_reg(31 downto 0) <= X"00000000";
            crc_ck <= '0';
            crc_curr(21 downto 0) <= "0000000000000000000000";
        end if;
        if (desynch_set = '1'  or  crc_err_flag = '1') then
           conti_data_flag <= '0';
           conti_data_cnt <= 0;
           cmd_wr_flag <= '0';
           cmd_rd_flag <= '0';
           far_maj_min_flag <= '0';
           cmd_reg_new_flag <= '0';
           crc_ck <= '0';
           csbo_cnt := 0;
           csbo_flag <= '0';
         downcont <= "0000000000000000000000000000";
         downcont_int <= 0;
           rd_data_cnt <= 0;
        end if;

        if (new_data_in_flag = '1'  and  wr_flag = '1') then
           if (conti_data_flag  =  '1' ) then
             if (type2_flag  =  '0') then
               case (reg_addr) is
               when "000000"  =>      if (conti_data_cnt = 1) then
                             crc_reg(15 downto 0) <= pack_in_reg;
                             crc_ck <= '1';
                          elsif (conti_data_cnt = 2) then
                             crc_reg(31 downto 16) <= pack_in_reg;
                             crc_ck <= '0';
                          end if;
               when "000001"  =>      if (conti_data_cnt = 2) then
                              far_maj_reg <= pack_in_reg;
                              far_maj_min_flag <= '1';
                           elsif (conti_data_cnt = 1) then
                               if (far_maj_min_flag  = '1') then
                                  far_min_reg <= pack_in_reg;
                                  far_maj_min_flag <= '0';
                               else
                                  far_maj_reg <= pack_in_reg;
                               end if;
                           end if;
               when "000010"  =>      far_min_reg <= pack_in_reg;
               when "000011"  =>      fdri_reg <= pack_in_reg;
               when "000101"  =>      cmd_reg <= pack_in_reg(4 downto 0);
               when "000110"  =>      ctl_reg <= (pack_in_reg and  (not mask_reg)) or (ctl_reg and mask_reg);
               when "000111"  =>      mask_reg <= pack_in_reg;
               when "001001"  =>      lout_reg <= pack_in_reg;
               when "001010"  =>      cor1_reg <= pack_in_reg;
               when "001011"  =>      cor2_reg <= pack_in_reg;
               when "001100"  =>      pwrdn_reg <= pack_in_reg;
               when "001101"  =>      flr_reg <= pack_in_reg;
               when "001110"  =>      
                          if (conti_data_cnt = 1) then
                             idcode_reg(15 downto 0) <= pack_in_reg;
                             idcode_tmp := (idcode_reg(31 downto 16) & pack_in_reg); 
                             if (idcode_tmp(27 downto 0)  /=  device_id_reg(27 downto 0)) then
                                id_error_flag <= '1';
                                write(message_line, string'("Error : written value to IDCODE register is "));
                                write(message_line, string'(SLV_TO_STR(idcode_tmp)));
                                write(message_line, string'(" which does not match DEVICE ID "));
                                write(message_line, string'(SLV_TO_STR(device_id_reg)));
                                write(message_line, string'("."));
                                assert false report message_line.all  severity error;
                                DEALLOCATE(message_line);
                             else
                                id_error_flag <= '0';
                             end if;
                          elsif (conti_data_cnt = 2) then
                             idcode_reg(31 downto 16) <= pack_in_reg;
                          end if;
                          
               when "001111"  =>      snowplow_reg <= pack_in_reg;
               when "010000"  =>      hc_opt_reg <= pack_in_reg;
               when "010010"  =>      csbo_reg <= pack_in_reg; 
               when "010011"  =>      general1_reg <= pack_in_reg;
               when "010100"  =>      general2_reg <= pack_in_reg;
               when "010101"  =>      mode_reg <= pack_in_reg;
               when "010110"  =>      pu_gwe_reg <= pack_in_reg;
               when "010111"  =>      pu_gts_reg <= pack_in_reg;
               when "011000"  =>      mfwr_reg <= pack_in_reg;
               when "011001"  =>      cclk_freq_reg <= pack_in_reg;
               when "011010"  =>      seu_opt_reg <= pack_in_reg;
               when "011011"  =>      if (conti_data_cnt = 1) then
                                        exp_sign_reg(15 downto 0) <= pack_in_reg;
                                      elsif (conti_data_cnt = 2) then
                                        exp_sign_reg(31 downto 16) <= pack_in_reg;
                                      end if;
               when others => NULL;
               end case;

             if (reg_addr  =  "000101") then
                 cmd_reg_new_flag <= '1';
             else
                 cmd_reg_new_flag <= '0';
             end if;

             if (crc_en  =  '1') then
               if ((reg_addr  =  "000101") and  (pack_in_reg(4 downto 0)  =  "00111")) then
                    
                   crc_curr(21 downto 0) <= "0000000000000000000000";
               else 
                  if ((reg_addr /= "000100") and (reg_addr /= "001000") and (reg_addr /= "011100") and 
                  (reg_addr /= "000000") and (reg_addr /= "001001") and  (reg_addr  /= "010010")) then
                     crc_input(21 downto 0) := (reg_addr(5 downto 0) & pack_in_reg); 
                     crc_new(21 downto 0) := crc_next(crc_curr, crc_input);
                     crc_curr(21 downto 0) <= crc_new;
                   end if;
               end if;
             end if;
             else      -- type2_flag
                if (conti_data_cnt  = 2) then
                   downcont(27 downto 16) <= pack_in_reg(11 downto 0);
                elsif (conti_data_cnt  = 1) then
                   downcont(15 downto 0) <= pack_in_reg;
                   tmp_v28 := (downcont(27 downto 16) & pack_in_reg );
                   downcont_int <= SLV_TO_INT(tmp_v28);
                end if;
             end if;

             if (conti_data_cnt <= 1) then
                conti_data_cnt <= 0;
                type2_flag <= '0';
             else
                conti_data_cnt <= conti_data_cnt - 1;
             end if;
           else               --if (conti_data_flag  =  '0' )
             if ( downcont_int >= 1) then
                   if (crc_en  =  '1') then
                     crc_input(21 downto 0) := ("000011" & pack_in_reg);  --FDRI address plus data
                     crc_new(21 downto 0) := crc_next(crc_curr, crc_input);
                     crc_curr(21 downto 0) <= crc_new;
                   end if;
             end if;

             if ((pack_in_reg(15 downto 13) /= "001") and  (downcont_int  =  0)) then
--                assert false report "Warning : only Type 1 Packet supported on SIM_CONFIG_S3A." 
--                 severity warning;
                cmd_wr_flag <= '0';
                type2_flag <= '1';
                conti_data_flag <= '1';
                conti_data_cnt <= 2;
             else
                if ((pack_in_reg(12 downto 11) = "01") and  (downcont_int = 0)) then
                    if (pack_in_reg(4 downto 0) /= "00000") then
                       cmd_rd_flag <= '1';
                       cmd_wr_flag <= '0';
                       tmp_v := (pack_in_reg(4 downto 0) & '0');
--                       rd_data_cnt <= SLV_TO_INT(SLV=>tmp_v);
                       rd_data_cnt <= 4;
                       conti_data_cnt <= 0;
                       conti_data_flag <= '0';
                       rd_reg_addr <= pack_in_reg(10 downto 5);
                    end if;
                elsif ((pack_in_reg(12 downto 11) = "10") and (downcont_int = 0)) then
                    if (pack_in_reg(15 downto 5)  =  "00110010010") then
                           csbo_reg <= pack_in_reg;
                           csbo_cnt := SLV_TO_INT(SLV=>pack_in_reg(4 downto 0));
                           csbo_flag <= '1';
                           conti_data_flag <= '0';
                           reg_addr <= pack_in_reg(10 downto 5);
                           cmd_wr_flag <= '1';
                           conti_data_cnt <= 0;
                    elsif (pack_in_reg(4 downto 0)  /=  "00000") then
                       cmd_wr_flag <= '1';
                       conti_data_flag <= '1';
                       conti_data_cnt <= SLV_TO_INT(SLV=>pack_in_reg(4 downto 0));
                       reg_addr <= pack_in_reg(10 downto 5);
                    end if;
                else 
                    cmd_wr_flag <= '0';
                    conti_data_flag <= '0';
                    conti_data_cnt <= 0;
                end if;
             end if;
             cmd_reg_new_flag <= '0';
             crc_ck <= '0';
          end if;   -- if (conti_data_flag  =  '0' ) 

         if (csbo_cnt /= 0 ) then 
             if (csbo_flag = '1') then
              csbo_cnt := csbo_cnt - 1;
              end if;
          else
              csbo_flag <= '0';
         end if;


          if (conti_data_cnt  =  1) then
                conti_data_flag <= '0';
          end if; 
      end if;

      if (rw_en  = '1') then
         if (rd_data_cnt  =  1) then
            rd_data_cnt <= 0;
         elsif (rd_data_cnt = 0 and  rd_flag = '1') then
               cmd_rd_flag <= '0';        
         elsif ((cmd_rd_flag = '1')  and  (rd_flag = '1')) then
             rd_data_cnt <= rd_data_cnt - 1;
         end if;
 
         if ((downcont_int >= 1) and (conti_data_flag  =  '0') and (new_data_in_flag = '1') and (wr_flag = '1')) then
              downcont_int <= downcont_int - 1;
         end if;
     end if;
   end if;
   end process;

   rd_back_p : process ( cclk_in, rst_intl) begin
    if (rst_intl  = '0') then
         outbus <= "00000000";
    elsif (rising_edge(cclk_in)) then
        if (cmd_rd_flag  =  '1'  and  rdwr_b_in  =  '1') then
               case (rd_reg_addr) is
               when "000000" =>      if (rd_data_cnt = 1) then
                             outbus <= crc_reg(7 downto 0);
                          elsif (rd_data_cnt = 2) then
                             outbus <= crc_reg(15 downto 8);
                          elsif (rd_data_cnt = 3) then
                             outbus <= crc_reg(23 downto 16);
                          elsif (rd_data_cnt = 4) then
                             outbus <= crc_reg(31 downto 24);
                          end if;
               when "001000" =>      if (rd_data_cnt = 1) then
                             outbus <= stat_reg(7 downto 0);
                          elsif (rd_data_cnt = 2) then
                             outbus <= stat_reg(15 downto 8);
                          elsif (rd_data_cnt = 3) then
                             outbus <= stat_reg(7 downto 0);
                          elsif (rd_data_cnt = 4) then
                             outbus <= stat_reg(15 downto 8);
                          end if;
               when "001110" =>      if (rd_data_cnt = 1) then
                             outbus <= idcode_reg(7 downto 0);
                          elsif (rd_data_cnt = 2) then
                             outbus <= idcode_reg(15 downto 8);
                          elsif (rd_data_cnt = 3) then
                             outbus <= idcode_reg(23 downto 16);
                          elsif (rd_data_cnt = 4) then
                             outbus <= idcode_reg(31 downto 24);
                          end if;
               when "011011" =>      if (rd_data_cnt = 1) then
                             outbus <= exp_sign_reg(7 downto 0);
                          elsif (rd_data_cnt = 2) then
                             outbus <= exp_sign_reg(15 downto 8);
                          elsif (rd_data_cnt = 3) then
                             outbus <= exp_sign_reg(23 downto 16);
                          elsif (rd_data_cnt = 4) then
                             outbus <= exp_sign_reg(31 downto 24);
                          end if;
               when others => NULL;
               end case;

       else
          outbus <= "00000000";
       end if;
     
   end if;
   end process;

        
     crc_rst <= crc_reset or (not rst_intl);

    process ( cclk_in,  crc_rst ) begin
     if (crc_rst = '1') then
         crc_err_flag <= '0';
     elsif (rising_edge(cclk_in)) then
        if (crc_ck = '1') then
          if (crc_bypass = '1') then
             if (crc_reg(31 downto 0)  /=  X"9876defc") then
                 crc_err_flag <= '1';
             else
                 crc_err_flag <= '0';
             end if;
          else 
            if (crc_curr(21 downto 0)  /=  crc_reg(21 downto 0)) then
                crc_err_flag <= '1';
            else
                 crc_err_flag <= '0';
            end if;
          end if;
       else
           crc_err_flag <= '0';
       end if;
    end if;
   end process;

    process ( crc_err_flag,  rst_intl,  bus_sync_flag) begin
     if (rst_intl  =  '0') then
         crc_err_flag_reg <= '0';
     elsif (rising_edge(crc_err_flag)) then
         crc_err_flag_reg <= '1';
     elsif (rising_edge(bus_sync_flag)) then
         crc_err_flag_reg <= '0';
     end if;
    end process;

    process ( cclk_in,  rst_intl) begin
    if (rst_intl  = '0') then
         startup_set <= '0';
         crc_reset  <= '0';
         gsr_set <= '0';
         shutdown_set <= '0';
         desynch_set <= '0';
         reboot_set <= '0';
         ghigh_b <= '0';
    elsif (rising_edge(cclk_in)) then
      if (cmd_reg_new_flag  = '1') then
         if (cmd_reg  =  "00011") then
             ghigh_b <= '1';
         elsif (cmd_reg  =  "01000") then
             ghigh_b <= '0';
         end if;

         if (cmd_reg  =  "00101") then
             startup_set <= '1';
         end if;
         if (cmd_reg  =  "00111") then
              crc_reset <= '1';
         end if;
         if (cmd_reg  =  "01010") then
              gsr_set <= '1';
         end if;
         if (cmd_reg  =  "01011") then
              shutdown_set <= '1';
         end if;
         if (cmd_reg  =  "01101") then
              desynch_set <= '1';
         end if;
         if (cmd_reg  =  "01110") then
             reboot_set <= '1';
         end if;
      else  
             startup_set <= '0';
              crc_reset <= '0';
              gsr_set <= '0';
              shutdown_set <= '0';
              desynch_set <= '0';
             reboot_set <= '0';
      end if;
    end if;
    end process;


   startup_set_pulse_p : process  begin
    if (rw_en  =  '0') then
       startup_set_pulse <= "00";
    elsif (rising_edge(startup_set)) then
      if (startup_set_pulse  =  "00") then
         startup_set_pulse <= "01";
      end if;
    elsif (rising_edge(desynch_set)) then
      if (startup_set_pulse  =  "01") then
          startup_set_pulse <= "11";
          wait until (rising_edge(cclk_in ));
          startup_set_pulse <= "00";
      end if;
    end if;
      wait on startup_set, desynch_set, rw_en;
    end process;


    process (ctl_reg) begin
      if (ctl_reg(3)  =  '1') then
         persist_en <= '1';
      else
         persist_en <= '0';
      end if;

      if (ctl_reg(0)  =  '1') then
         gts_usr_b <= '1';
      else
         gts_usr_b <= '0';
      end if;
    end process;

    process (cor1_reg) begin
      if (cor1_reg(2)  = '1') then
         done_pin_drv <= '1';
      else
         done_pin_drv <= '0';
      end if;

      if (cor1_reg(4)  =  '1') then
         crc_bypass <= '1';
      else
         crc_bypass <= '0';
      end if;
    end process;
    
    process (cor2_reg) begin
      if (cor2_reg(15)  = '1') then
        reset_on_err <= '1';
      else
        reset_on_err <= '0';
      end if;

      done_cycle_reg <= cor2_reg(11 downto 9);
      lock_cycle_reg <= cor2_reg(8 downto 6);
      gts_cycle_reg <= cor2_reg(5 downto 3);
      gwe_cycle_reg <= cor2_reg(2 downto 0);
    end process;


     stat_reg(15) <= sync_timeout;
     stat_reg(14) <= '0';
     stat_reg(13) <= DONE;
     stat_reg(12) <= INITB;
     stat_reg(11 downto 9) <= mode_pin_in;
     stat_reg(5) <= ghigh_b;
     stat_reg(4) <= gwe_out;
     stat_reg(3) <= gts_out;
     stat_reg(2) <= dcm_locked;
     stat_reg(1) <= id_error_flag;
     stat_reg(0) <= crc_err_flag_reg; 


    st_state_p : process ( cclk_in, rst_intl) begin
      if (rst_intl  =  '0') then
        st_state <= STARTUP_PH0;
        startup_begin_flag <= '0';
        startup_end_flag <= '0';
      elsif (rising_edge(cclk_in)) then
           if (nx_st_state  =  STARTUP_PH1) then
              startup_begin_flag <= '1';
              startup_end_flag <= '0';
           elsif (st_state  =  STARTUP_PH7) then
              startup_end_flag <= '1';
              startup_begin_flag <= '0';
           end if;
           if  ((lock_cycle_reg = "111") or (dcm_locked  =  '1') or (st_state /= lock_cycle_reg)) then
                st_state <= nx_st_state;
           else
              st_state <= st_state;
           end if;
      end if;
    end process;

    nx_st_state_p : process (st_state, startup_set_pulse, done_in ) begin
    if ((( st_state  =  done_cycle_reg) and (done_in /= '0')) or ( st_state /= done_cycle_reg)) then
      case (st_state) is
      when STARTUP_PH0  =>      if (startup_set_pulse  =  "11" ) then
                                     nx_st_state <= STARTUP_PH1;
                                else
                                     nx_st_state <= STARTUP_PH0;
                                end if;
      when STARTUP_PH1  =>      nx_st_state <= STARTUP_PH2;

      when STARTUP_PH2  =>      nx_st_state <= STARTUP_PH3;

      when STARTUP_PH3  =>      nx_st_state <= STARTUP_PH4;

      when STARTUP_PH4  =>      nx_st_state <= STARTUP_PH5;

      when STARTUP_PH5  =>      nx_st_state <= STARTUP_PH6;

      when STARTUP_PH6  =>      nx_st_state <= STARTUP_PH7;

      when STARTUP_PH7  =>      nx_st_state <= STARTUP_PH0;
      when others => NULL;
      end case;
   end if;
   end process;

    start_out_p : process ( cclk_in, rst_intl ) begin
      if (rst_intl  =  '0') then
          gwe_out <= '0';
          gts_out <= '1';
          eos_startup <= '0';
          gsr_st_out <= '1';
          done_o <= '0';
      elsif (rising_edge(cclk_in)) then

         if (nx_st_state  =  done_cycle_reg) then
            if (done_in  /=  '0' or done_pin_drv = '1') then
               done_o <= '1';
            else
               done_o <= 'H';
            end if;
         else
             if (done_in  /=  '0') then
                     done_o <= '1';
             end if;
         end if;

         if (nx_st_state  =  gwe_cycle_reg) then
             gwe_out <= '1';
         end if;

         if (nx_st_state  =  gts_cycle_reg) then
             gts_out <= '0';
         end if;

         if (nx_st_state  =  STARTUP_PH6) then
             gsr_st_out <= '0';
         end if;

         if (nx_st_state  =  STARTUP_PH7) then
            eos_startup <= '1';
         end if;

      end if;
    end process;


    gsr_out <= gsr_st_out or gsr_cmd_out;
     

    process (rdwr_b_in ,  rst_intl, abort_flag_rst , csi_b_in)
    begin
      if (rst_intl = '0'  or  abort_flag_rst = '1'  or  csi_b_in  =  '1') then
          abort_flag_wr <= '0';
      elsif (rising_edge(rdwr_b_in)) then 
        if (abort_dis  =  '0'  and  csi_b_in  =  '0') then
             if (NOW  /=  0 ps) then
               abort_flag_wr <= '1';
               assert false report " Warning : RDWRB changes when CS_B low, which causes Configuration abort on SIM_CONFIG_S3A."
               severity warning;
             end if;
        else
           abort_flag_wr <= '0';
        end if;
     end if;
    end process;

    process ( rdwr_b_in,  rst_intl,  abort_flag_rst,  csi_b_in) begin
      if (rst_intl = '0'  or   csi_b_in  =  '1'  or  abort_flag_rst = '1') then
          abort_flag_rd <= '0';
      elsif (falling_edge(rdwr_b_in)) then 
       if (abort_dis  =  '0'  and  csi_b_in  =  '0') then
         if (NOW  /=  0 ps) then
          abort_flag_rd <= '1';
          assert false report " Warning :  RDWRB changes when CS_B low, which causes Configuration abort on SIM_CONFIG_S3A."
          severity warning;
         end if;
       else
         abort_flag_rd <= '0';
       end if;
     end if;
    end process;

     abort_flag <= abort_flag_wr or abort_flag_rd;


    process ( cclk_in,  rst_intl) begin
      if (rst_intl  =  '0') then
         abort_cnt <= 0;
         abort_out_en <= '0';
      elsif (rising_edge(cclk_in)) then
         if ( abort_flag  = '1' ) then
             if (abort_cnt < 4) then
                 abort_cnt <= abort_cnt + 1;
                 abort_out_en <= '1';
             else 
                abort_flag_rst <= '1';
             end if;
         else 
                abort_cnt <=  0;
                abort_out_en <= '0';
                abort_flag_rst <= '0';
         end if;
    
         if (abort_cnt =  0) then
            abort_status <= (cfgerr_b_flag & bus_sync_flag &  "011111");
         elsif (abort_cnt =  1) then
            abort_status <= (cfgerr_b_flag & "1001111");
         elsif (abort_cnt =  2) then
            abort_status <= (cfgerr_b_flag & "0001111");
         elsif (abort_cnt =  3) then
            abort_status <= (cfgerr_b_flag & "0011111");
         end if;
      end if;
    end process;

end SIM_CONFIG_S3A_V;
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/trilogy/VITAL/Attic/spi_access.vhd,v 1.20.2.2 2008/07/09 22:30:10 robh Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2008 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Internal logic access to the Serial Peripheral Interface (SPI) PROM data
-- /___/   /\     SPI_ACCESS.vhd 
-- \   \  /  \    Timestamp : Fri Oct 12 10:43:26 PDT 2007
--  \___\/\___\
--
--
-- Revision:
--    10/12/07 - Initial version
--    06/03/08 - Fixed vcs compiler warning message about synopsys_off
--    07/09/08 - CR476247 - shorten simulation delays.
--               Change MISO out off state from H to 1.
-- End Revision

----- CELL SPI_ACCESS -----

library std;
    use std.textio.all;
library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_textio.all;
    use IEEE.Std_logic_unsigned.all;
    use IEEE.numeric_std.all;

---entity declarations--------------
entity SPI_ACCESS is
  generic(
       
    SIM_DELAY_TYPE  : string := "SCALED";
    SIM_DEVICE      : string := "3S1400AN";  
    SIM_FACTORY_ID  : bit_vector :=X"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
    SIM_USER_ID     : bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
    SIM_MEM_FILE    : string := "NONE"
     
    );

port(
    MISO            : out std_ulogic;
    CLK             : in std_ulogic;
    CSB             : in std_ulogic;
    MOSI            : in std_ulogic
    );

end SPI_ACCESS;

----architecture declarations------
architecture SPI_ACCESS_V of SPI_ACCESS is

constant SYNC_PATH_DELAY : time := 100 ps;

constant    InstancePath    : string := "SPI_ACCESS";
    
constant    binary_opt      : std_logic := '0';
--  unchanged time delays
constant     Tdis            : TIME := 0 ps ;
constant     Tv              : TIME := 0 ps ;
constant      Tspickh        : TIME := 6800 ps ;
constant      Tspickl        : TIME := 6800 ps ;

-- divided delays
constant    Tspiclkl        : STRING := "Tspiclkl";                     
constant    Tspiclkh        : STRING := "Tspiclkh";                     
constant    TCOMP           : STRING := "   tCOMP";     
constant    TXFR            : STRING := "    tXFR";
constant    TPEP            : STRING := "    tPEP";
constant    TP              : STRING := "      tP";
constant    TPE             : STRING := "     tPE";
constant    TSE             : STRING := "     tSE";
constant    TVCSL           : STRING := "   tVCSL";
constant    TPUW            : STRING := "    tPUW";

constant    Tsck            : Time := 15152 ps;   -- period of 66 MHz 
constant    Tsck33          : Time := 30304 ps;   --clk_period for 33 MHz 
constant    Tcs             : TIME := 50  ns;     -- 50 ns  Minimum CSB High Time
signal      scaled_flag     : boolean;

procedure validate_input(   
              SIM_DEVICE : in string;
               accuracy  : in string;
    signal     scal_flag : inout boolean
    ) is
    variable ln : Line;
begin
   if (accuracy = "SCALED" ) then
       scal_flag <= TRUE;
       wait for 1 ps;
   elsif  (accuracy ="ACCURATE") then 
       scal_flag <= FALSE;
       wait for 1 ps;
   else
        write(ln, string'(" Attribute Syntax Error : "));
        write(ln, string'(" SIM_DELAY_TYPE "));
        write(ln, string'( " in "));
        write(ln, InstancePath);
        write(ln, string'( " The Legal values for this attribute are ACCURATE or SCALED "));
        assert false report ln.all severity failure;
        DEALLOCATE (ln);        
    end if;
    if (SIM_DEVICE /=  "3S50AN")and(SIM_DEVICE /=  "3S200AN")and(SIM_DEVICE /=  "3S400AN")and(SIM_DEVICE /=  "3S700AN")and(SIM_DEVICE /= "3S1400AN") then
        write(ln, string'(" Attribute Syntax Error :  The allowed values for SIM_DEVICE in "));
        write(ln, InstancePath);
        write(ln, string'(" are 3S50AN, 3S200AN, 3S400AN, 3S700AN or 3S1400AN"));
        assert false report ln.all severity failure;
        DEALLOCATE (ln);        
    end if;
end validate_input ;   



----------------------Convert integer subroutine -------------------------------------------
subtype SMALL_INT is INTEGER range 0 to 1;
-- synopsys synthesis_off
type tbl_type is array (STD_ULOGIC) of STD_ULOGIC;
constant tbl_BINARY : tbl_type :=
('X', 'X', '0', '1', 'X', 'X', '0', '1', 'X');
-- synopsys synthesis_on
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT;
-- attribute foreign of CONV_INTEGER[UNSIGNED return INTEGER]:function is "Conv_Integer_Unsigned";
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT is
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_FEED_THRU
-- synopsys subpgm_id 370
begin
-- synopsys synthesis_off
tmp := tbl_BINARY(ARG);
if tmp = '1' then
    return 1;
else
    return 0;
end if;
-- synopsys synthesis_on
end;
-----------------------------------------------------------------------------------------------------


function delay_cal (DELAY_NAME : in string(1 to 8);
                    scaled_flag : in boolean
                    ) return TIME is
variable delay_time  : TIME := 50 ns;
begin
   case scaled_flag is
       when  FALSE =>
         case DELAY_NAME is
            when "Tspiclkl" => delay_time :=     6800 ps;      
            when "Tspiclkh" => delay_time :=     6800 ps;        
            when "   tCOMP" => delay_time :=    400000 ns;  -- 400 us Buffer Compare Time     
            when "    tXFR" => delay_time :=    400000 ns;  -- 400 us Page to Bufer Xfer UG pg 33,34
            when "    tPEP" => delay_time :=  40000000 ns;  -- 40 ms
            when "      tP" => delay_time :=   6000000 ns;  -- 6 ms
            when "     tPE" => delay_time :=  35000000 ns;  -- 32 ms
            when "     tSE" => delay_time := 500000000 ns;  -- 5 s divided by 10 since num too large, loop 10x
            when "   tVCSL" => delay_time :=        50 ns;  -- 50 us
            when "    tPUW" => delay_time :=        50 ns;  --          20000000 ns;  -- 20 ms
            when OTHERS    => delay_time := 500000000 ns;  -- maximum
         end case;
      when  TRUE => -- arbitrary
         case DELAY_NAME is
             when "Tspiclkl" => delay_time :=    6800 ps;      
            when "Tspiclkh" => delay_time :=    6800 ps;        
            when "   tCOMP" => delay_time :=      500 ns;  -- = tXFR
            when "    tXFR" => delay_time :=      500 ns;  -- = tCOMP
            when "    tPEP" => delay_time :=     2500 ns;  -- > tPE + tP
            when "      tP" => delay_time :=     1000 ns;  -- 2 x tCOMP
            when "     tPE" => delay_time :=     1000 ns;  -- 2 x tCOMP
            when "     tSE" => delay_time :=     4000 ns;  -- 4 x tPE
            when "   tVCSL" => delay_time :=       50 ns;  -- 
            when "    tPUW" => delay_time :=       50 ns;  -- 
            when OTHERS     => delay_time :=    40000 ns;  -- 10 x tSE
         end case;
    end case;         
    return  delay_time;
end delay_cal;

function device_Sel1  (SIM_DEVICE : in string
                         ) return std_logic is
    variable status3  : std_logic;
begin
    if    (SIM_DEVICE =   "3S50AN") then  status3 := '1';
    elsif (SIM_DEVICE =  "3S200AN") then  status3 := '1';
    elsif (SIM_DEVICE =  "3S400AN") then  status3 := '1';
    elsif (SIM_DEVICE =  "3S700AN") then  status3 := '0';
    elsif (SIM_DEVICE = "3S1400AN") then  status3 := '1' ;
    else                                  status3 := '1';
    end if;                               
return status3;
end device_sel1;

function device_Sel2  (SIM_DEVICE : in string
                         ) return std_logic is
    variable status4  : std_logic;
begin
    if    (SIM_DEVICE =   "3S50AN") then  status4 := '0';     
    elsif (SIM_DEVICE =  "3S200AN") then  status4 := '1';     
    elsif (SIM_DEVICE =  "3S400AN") then  status4 := '1';      
    elsif (SIM_DEVICE =  "3S700AN") then  status4 := '0';     
    elsif (SIM_DEVICE = "3S1400AN") then  status4 := '0' ;        
    else                                  status4 := '0';     
    end if;                               
    return status4;
end device_sel2;

function device_Sel3         (SIM_DEVICE : in string
                         ) return std_logic is
    variable status5  : std_logic;
begin
    if    (SIM_DEVICE =   "3S50AN") then  status5 := '0';
    elsif (SIM_DEVICE =  "3S200AN") then  status5 := '0';
    elsif (SIM_DEVICE =  "3S400AN") then  status5 := '0';
    elsif (SIM_DEVICE =  "3S700AN") then  status5 := '1';
    elsif (SIM_DEVICE = "3S1400AN") then  status5 := '1' ;
    else                                  status5 := '0';
    end if;                               
    return status5;
end device_sel3;

function page_cal        (SIM_DEVICE : in string
                         ) return integer is
    variable pages  : integer range 1 to 8192 := 2048;
begin
    if    (SIM_DEVICE =   "3S50AN") then  pages := 512;
    elsif (SIM_DEVICE =  "3S200AN") then  pages := 2048;   
    elsif (SIM_DEVICE =  "3S400AN") then  pages := 2048;
    elsif (SIM_DEVICE =  "3S700AN") then  pages := 4096;
    elsif (SIM_DEVICE = "3S1400AN") then  pages := 4096;
    else                                  pages := 512;
    end if;                               
    return  pages;
end page_cal;

function pageper_sector (SIM_DEVICE : in string
                  ) return integer is
    variable page_per_sector :  integer range 1 to 256 :=256;
begin
    if    (SIM_DEVICE =   "3S50AN") then  page_per_sector := 128;  
    elsif (SIM_DEVICE =  "3S200AN") then  page_per_sector := 256;   
    elsif (SIM_DEVICE =  "3S400AN") then  page_per_sector := 256;  
    elsif (SIM_DEVICE =  "3S700AN") then  page_per_sector := 256;  
    elsif (SIM_DEVICE = "3S1400AN") then  page_per_sector := 256;  
    else                                  page_per_sector := 128;  
    end if;                               
    return  page_per_sector;
end pageper_sector;

function sec_tors (SIM_DEVICE : in string
                  ) return integer is
    variable sectors :  integer range 1 to 64 :=8;
begin
    if    (SIM_DEVICE =   "3S50AN") then  sectors := 4;
    elsif (SIM_DEVICE =  "3S200AN") then  sectors := 8;   
    elsif (SIM_DEVICE =  "3S400AN") then  sectors := 8;
    elsif (SIM_DEVICE =  "3S700AN") then  sectors := 16;
    elsif (SIM_DEVICE = "3S1400AN") then  sectors := 16;
    else                                  sectors := 4;
    end if;                               
    return  sectors;
end sec_tors;          

function pagesize_forbuffer (SIM_DEVICE : in string
                  ) return integer is
    variable page_size :  integer range 1 to 1056 :=264;
begin
    if    (SIM_DEVICE =   "3S50AN") then  page_size := 264;
    elsif (SIM_DEVICE =  "3S200AN") then  page_size := 264;
    elsif (SIM_DEVICE =  "3S400AN") then  page_size := 264;
    elsif (SIM_DEVICE =  "3S700AN") then  page_size := 264;
    elsif (SIM_DEVICE = "3S1400AN") then  page_size := 528;
    else                                  page_size := 264;
    end if;
    return  page_size;
end pagesize_forbuffer;


function pagesize (SIM_DEVICE : in string;
    binary_page : in std_logic
) return integer is
variable page_size :  integer range 1 to 1056 :=264;
begin
    if    (SIM_DEVICE =   "3S50AN") then  page_size := (264 - (conv_integer(binary_page) * 8));
    elsif (SIM_DEVICE =  "3S200AN") then  page_size := (264 - (conv_integer(binary_page) * 8));
    elsif (SIM_DEVICE =  "3S400AN") then  page_size := (264 - (conv_integer(binary_page) * 8));
    elsif (SIM_DEVICE =  "3S700AN") then  page_size := (264 - (conv_integer(binary_page) * 8));
    elsif (SIM_DEVICE = "3S1400AN") then  page_size := (528 - (conv_integer(binary_page) * 16));
    else                                  page_size:=  (264 - (conv_integer(binary_page) * 8));
    end if;                               
    return  page_size;
end pagesize;


function buffers  (
            SIM_DEVICE : in string
          ) return integer is
variable buf  : integer := 2;
begin
    if    (SIM_DEVICE =   "3S50AN") then  buf := 1;
    elsif (SIM_DEVICE =  "3S200AN") then  buf := 2;
    elsif (SIM_DEVICE =  "3S400AN") then  buf := 2;
    elsif (SIM_DEVICE =  "3S700AN") then  buf := 2;
    elsif (SIM_DEVICE = "3S1400AN") then  buf := 2;
    else                                  buf := 1;
    end if;                               
    return  buf;
end buffers;

function b_address (SIM_DEVICE : in string;
            binary_opt : in std_logic
                     ) return integer is
variable baddress : integer range 1 to 11 := 9; 
begin
    if    (SIM_DEVICE =   "3S50AN") then  baddress := (9 - (conv_integer(binary_opt) * 1));
    elsif (SIM_DEVICE =  "3S200AN") then  baddress := (9 - (conv_integer(binary_opt) * 1));   
    elsif (SIM_DEVICE =  "3S400AN") then  baddress := (9 - (conv_integer(binary_opt) * 1));
    elsif (SIM_DEVICE =  "3S700AN") then  baddress := (9 - (conv_integer(binary_opt) * 1));
    elsif (SIM_DEVICE = "3S1400AN") then  baddress := (10 -(conv_integer(binary_opt) * 1));
    else                                  baddress := (9 - (conv_integer(binary_opt) * 1));
    end if;                               
    return  baddress;
end b_address;
    
function p_address (SIM_DEVICE : in string
                             ) return integer is
variable paddress : integer range 1 to 14 := 11; 
begin
    if    (SIM_DEVICE =   "3S50AN") then  paddress := 9;
    elsif (SIM_DEVICE =  "3S200AN") then  paddress := 11;   
    elsif (SIM_DEVICE =  "3S400AN") then  paddress := 11;
    elsif (SIM_DEVICE =  "3S700AN") then  paddress := 12;
    elsif (SIM_DEVICE = "3S1400AN") then  paddress := 12;
    else                                  paddress := 9;
    end if;                               
    return  paddress;
end p_address;

function s_address (SIM_DEVICE : in string
                             ) return integer is
variable saddress : integer range 1 to 6 := 3; 
begin
    if    (SIM_DEVICE =   "3S50AN") then  saddress := 2;
    elsif (SIM_DEVICE =  "3S200AN") then  saddress := 3;   
    elsif (SIM_DEVICE =  "3S400AN") then  saddress := 3;
    elsif (SIM_DEVICE =  "3S700AN") then  saddress := 4;
    elsif (SIM_DEVICE = "3S1400AN") then  saddress := 4;
    else                                  saddress := 2;
    end if;                               
    return  saddress;
end s_address;

function manid (SIM_DEVICE : in string
                             ) return std_logic_vector is
variable man_id : std_logic_vector(31 downto 0); 
begin
    if    (SIM_DEVICE =   "3S50AN") then  man_id := X"1F_22_00_00";
    elsif (SIM_DEVICE =  "3S200AN") then  man_id := X"1F_24_00_00";   
    elsif (SIM_DEVICE =  "3S400AN") then  man_id := X"1F_24_00_00";
    elsif (SIM_DEVICE =  "3S700AN") then  man_id := X"1F_25_00_00";
    elsif (SIM_DEVICE = "3S1400AN") then  man_id := X"1F_26_00_00";
    else                                  man_id := X"1F_22_01_00";
    end if;                               
    return  man_id;
end manid;


function memsize (page_size : in integer range 1 to 1056;
                  pages    : in integer range 1 to 8192
             ) return integer is
variable mem_size : integer range 1 to 69206016;
begin
    mem_size := page_size * pages;
    return mem_size;
end memsize;

constant binary_page : std_logic :='0';    
signal status2 : std_logic :='1';
signal status3 : std_logic ;
signal status4 : std_logic ;
signal status5 : std_logic ;

------------------------------------------------ 
signal  TsckRp,TsckRpa , TsckRp33, TsckRpx ,TsckFp, TsckRw , TsckF , TcsR , TcsF , Tsckm , Tsim , TsckRh  : time := 0 ns ;
signal  TsckRpcsb  , TsckFcsb  : time := 0 ns ;

signal  clk_err: std_logic;
signal  clk_err33: std_logic;
signal  csb_err: std_logic;
signal  clk_erra: std_logic;
signal  backgnd_while_busy_err: std_logic;


------------- global signal declarations---------

signal  MMCAR : std_logic;        
signal  MMPTBT : std_logic;      
signal  MMPTBC : std_logic;      
signal  B1W : std_logic;          
signal  B2W : std_logic;          
signal  BTMMPP : std_logic;
signal  PE : std_logic;           
signal  SE : std_logic;           
signal  MMPPB : std_logic;       
signal  security_flag : std_logic:='0'; 
signal tmp_reg1 : std_logic_vector(7 downto 0);
signal tmp_reg2 : std_logic_vector(7 downto 0);
signal buff_num : std_logic_vector(1 downto 0);  -- buffer number
signal buff_nump : std_logic_vector(1 downto 0);  -- buffer number
signal erase_flag: std_logic;   -- Flag for whether command performs erase
signal cmd_name  : string(1 to 40) :="        Initialize                      ";  
signal cycle_mode  : string(1 to 5) :="idle ";  
signal test_33mhz  : Boolean := FALSE ;  -- flag to on 33 MHz 
signal random     : Boolean :=   FALSE;  -- flag for random read

------------------------------------------------------------------------------
-- Signal       ____/------\_______/----
--              <-------------->
procedure checkclk(
    signal      TestSignal          : in std_logic;
                TestSignalName      : in string; 
                expectedDelay       : in time;
                expectedDelayName   : in string;
    signal      LastSignalRise      : inout time;
    signal      LastSignalFall      : inout time;    
    signal      clk_err             :inout std_logic;
                fullPathName        : in string;
    signal      valid               :in Boolean;
    signal      pos_check           :in Boolean;
    signal      neg_check           :in Boolean    
              )  is
    variable ln : Line;
    variable  per_flag: boolean;
    
begin

if (TestSignal'event ) then
    if ((((now - LastSignalRise) < expectedDelay and pos_check )or (now - LastSignalFall < expectedDelay and neg_check))
          and (clk_err /= '1' and (valid = TRUE) and (now > expectedDelay))) then
        write(ln, string'("DRC Error : In "));
        write(ln, fullPathName);
        write(ln, string'(": '"));
        write(ln, string'(TestSignalName));
        write(ln, string'("' high/low time violation at: "));
        write(ln, now);
        write(ln, string'(", "));
        write(ln, string'(" signal width: "));
        if (now - LastSignalFall <  delay_cal(Tspiclkl,scaled_flag)) then 
            write(ln, now - LastSignalFall);
        else
            write(ln, now - LastSignalRise);
        end if;  
        write(ln, string'(" Minimum Width: "));          
            write(ln, expectedDelay);
        writeline(output, ln);
        clk_err <= '1';
        assert false report ln.all severity warning;
        DEALLOCATE (ln);        
    else
        clk_err <= '0';
    end if;     
    if (TestSignal = '1'    ) then
        LastSignalRise <= now;
    else
      LastSignalFall <= now;
    end if;
end if;
end checkclk;


procedure checkPeriod(
    signal      TestSignal      : in std_logic;
                TestSignalName      : in string;
                expectedDelay       : in time;
                expectedDelayName   : in string;
    signal      LastSignalRise      : inout time;
    signal      clk_err             :inout std_logic;
                fullPathName        : in string;
    signal      valid          :in Boolean
              )  is
    variable ln : Line;
    variable  per_flag: boolean;
    
begin

if (TestSignal'event and TestSignal = '1') then
   if   (now - lastSignalRise < expectedDelay) and ( lastSignalRise /= 0 ns ) and
       (now > 0 ns) and (expectedDelay /= 0 ns) and (clk_err /= '1') and (valid = TRUE) then 
      write(ln, string'("DRC Error : In "));
      write(ln, fullPathName);
      write(ln, string'(": '"));
      write(ln, string'(TestSignalName));
      write(ln, string'("' Period violation at: "));
      write(ln, now);
      write(ln, string'(", "));
      write(ln, string'(expectedDelayName));
      write(ln, string'(" expected: "));
      write(ln, expectedDelay);
      write(ln, string'(", "));
      write(ln, string'(expectedDelayName));
      write(ln, string'(" actual: "));
      write(ln, now - lastSignalRise);
      writeline(output, ln);
      clk_err <= '1';
      assert false report ln.all severity warning;
      DEALLOCATE (ln);        
    end if;
    if (now - lastSignalRise > expectedDelay) and ( lastSignalRise /= 0 ns ) and
       (now > 0 ns) and (expectedDelay /= 0 ns)then 
        clk_err <= '0';
    end if;     
    if (valid = FALSE) then 
        clk_err <= '0';
    end if;     
    LastSignalRise <= now;
end if;
end checkPeriod;

procedure write_busy_message is 
variable Message :line;
begin
    Write ( Message, string'("DRC Error : In "));
    Write ( Message, InstancePath); 
    Write ( Message, string'(" access not allowed -- busy"));
    assert false report Message.all severity failure;
    DEALLOCATE (Message);       
end write_busy_message; 


procedure write_opcode_message is
variable Message :line;
begin
    Write ( Message, string'("DRC Error : In "));
    Write ( Message, InstancePath); 
    Write ( Message, string'(" opcode is not supported in the simulation model"));
    assert false report Message.all severity warning;
    DEALLOCATE (Message);       
end write_opcode_message;
    
    
procedure write_tpuw_message is
variable Message:line;
begin
    Write ( Message, string'("DRC Error : In "));
    Write ( Message, InstancePath); 
    Write ( Message, string'(" write operations are not allowed before a delay of :")); 
    Write ( Message, delay_cal(TPUW,scaled_flag) );
    Write ( Message,string'(" ms"));
    assert false report Message.all severity failure;
    DEALLOCATE (Message);       
end write_tpuw_message;
-------------------------------------------------------------------
-------------------------------------------------------------------
    FUNCTION integer_to_bit_vector   (VAL, width    : INTEGER)      RETURN BIT_VECTOR IS
    VARIABLE result : BIT_VECTOR (width-1 downto 0) := (OTHERS=>'0');
        VARIABLE bits   : INTEGER := width;
    BEGIN
        IF (bits > 31) THEN              --  Avoid overflow errors.
          bits := 31;
        ELSE
      ASSERT 2**bits > VAL REPORT
        "Value too big FOR BIT_VECTOR width"
        SEVERITY WARNING;
        END IF;
    FOR i IN 0 TO bits - 1 LOOP
        IF ((val/(2**i)) MOD 2 = 1) THEN
        result(i) := '1';
        END IF;
    END LOOP;
    RETURN (result);
    END integer_to_bit_vector ;  

 PROCEDURE removespace(VARIABLE l : IN line; pos : OUT integer) IS
    BEGIN
         pos := l'low;
         FOR i IN l'low TO l'high LOOP
              CASE l(i) IS
                  WHEN ' ' | ht  =>
                      pos := i + 1;
                  WHEN OTHERS =>
                      EXIT;
              END CASE;
         END LOOP;
    END;
    PROCEDURE removeline(l : INOUT line; pos : integer) IS
        VARIABLE tmpl : line;
    BEGIN
        tmpl := l;
        l := NEW string'(tmpl(pos TO tmpl'high));
        deallocate(tmpl);
    END;
    PROCEDURE hexa_to_bit_vector(l: INOUT line; u: in integer; value: OUT bit_vector) IS
        CONSTANT not_digit : integer := -999;
        FUNCTION digit_value(c : character) RETURN integer IS
        BEGIN
            IF (c >= '0') AND (c <= '9') THEN
                RETURN (character'pos(c) - character'pos('0'));
            ELSIF (c >= 'a') AND (c <= 'f') THEN
                RETURN (character'pos(c) - character'pos('a') + 10);
            ELSIF (c >= 'A') AND (c <= 'F') THEN
                RETURN (character'pos(c) - character'pos('A') + 10);
            ELSE
                RETURN not_digit;
            END IF;
        END;
        VARIABLE digit  : bit_vector(4 downto 1);
        VARIABLE digit1 : bit_vector(u downto 1);
        VARIABLE digitx : integer;
        VARIABLE pos    : integer;
        VARIABLE t      : integer := u/4;
    BEGIN
        removespace(l, pos);
        FOR i IN pos TO l'right LOOP
            digitx := digit_value(l(i));
            EXIT WHEN (digitx = not_digit) OR (digitx >= 16);
            digit := integer_to_bit_vector(digitx,4);
            if t >= 1 then
                digit1 := digit1(u-4 downto 1) & digit;
                t := t - 1;
            else
            end if;
            pos := i + 1;
        END LOOP;
        value := digit1;
        removeline(l, pos);
    END;    

--******************************************---
--******************************************--
signal page : std_logic_vector(p_address(SIM_DEVICE)-1 downto 0) := (others=> '0');
--signal temp_reg2 : std_logic_vector(7 downto 0);
--signal temp_page : std_logic_vector(p_address(SIM_DEVICE)-1 downto 0);
signal byte : integer;
---protected/locked status reg-----
signal sector : std_logic_vector(s_address(SIM_DEVICE)-1 downto 0);
type buffer1 is array(pagesize_forbuffer(SIM_DEVICE)-1 downto 0) of std_logic_vector(7 downto 0);
type buffer2 is array(pagesize_forbuffer(SIM_DEVICE)-1 downto 0) of std_logic_vector(7 downto 0);
--memory initalization--
constant N : integer range 1 to 69206016 := memsize(pagesize_forbuffer(SIM_DEVICE),page_cal(SIM_DEVICE));
constant M : integer := 8;
type memtype is array(N-1 downto 0) of std_logic_vector(7 downto 0);
constant p : integer := sec_tors(SIM_DEVICE);
type factory_type is array(63 downto 0 ) of std_logic_vector(7 downto 0);
signal factory_reg : factory_type;

--security reg--
type security_type is array(63 downto 0) of std_logic_vector(7 downto 0);
signal security_reg : security_type;

--------------comp page address function implementation---------------
function comp_page_addr     (    paddress : in integer range 1 to 14;
                    binary_page : in std_logic;
                    page_addr0 : in std_logic_vector( 7 downto 0);
                    page_addr1 : in std_logic_vector( 7 downto 0);
                    man_id : in std_logic_vector(31 downto 0)      
                ) return std_logic_vector is
variable page1 : std_logic_vector((P_ADDRESS(SIM_DEVICE))-1 DOWNTO 0);
begin
    case(PADDRESS) is
        when 12=>
                                         ---16mb----
            if (MAN_ID = X"1F260000") then
                if (binary_page = '1') then
                    page1 := page_addr0(4 downto 0) & page_addr1(7 downto 1);
                else        
                    page1 := page_addr0(5 downto 0) & page_addr1(7 downto 2);
                end if;
            end if;
                                            --8mb--
            if (MAN_ID = X"1F250000") then
                if (binary_page = '1') then
                    page1 := page_addr0(3 downto 0) & page_addr1(7 downto 0);
                else        
                    page1 := page_addr0(4 downto 0) &  page_addr1(7 downto 1);
                end if;
            end if;
                                          ---4 mb---
        when 11=>
            if (binary_page = '1') then
                page1 := page_addr0(2 downto 0) &  page_addr1(7 downto 0);
            else        
                page1 := page_addr0(3 downto 0) &  page_addr1(7 downto 1);
            end if;
                                          --1mb---
        when 9=>
            if (binary_page ='1') then
                 page1 := page_addr0(0) & page_addr1(7 downto 0);
            else  
                page1 := page_addr0(1 downto 0) & page_addr1(7 downto 1);   
            end if;
        when others =>
    end case;
    return page1;
end comp_page_addr;


----------------------------
function comp_byte_addr
    (baddress : integer range 1 to 11 ;
    signal page_addr1 : in std_logic_vector( 7 downto 0);
    signal byte_addr : in std_logic_vector( 7 downto 0);
     binary_opt : in std_logic
    ) return integer is
variable byte_ad : integer;-- range 1 to 11 := 8;              
begin
    case(baddress)is
        when 11 =>  byte_ad :=  conv_integer(page_addr1(2 downto 0)  &  byte_addr) ;
        when 10 =>  byte_ad := conv_integer(page_addr1(1 downto 0) &  byte_addr) ; 
        when 9 =>   byte_ad := conv_integer(page_addr1(0) &  byte_addr) ; 
        when others=>  byte_ad := conv_integer(byte_addr) ;
    end case;
    return byte_ad;
end comp_byte_addr;     


procedure compute_address  ( 
    page : in std_logic_vector((P_ADDRESS(SIM_DEVICE))-1 DOWNTO 0);
    page_size : in integer range 1 to 1056;
    byte : in integer;
    page_boundary_low : out integer;
    page_boundary_high : out integer;
    current_address : out integer;
    mem_no : out integer;
    binary_page : in std_logic
) is
variable temp_low : integer ;
begin
    temp_low := (conv_integer(page) * pagesize(SIM_DEVICE,binary_page));
    page_boundary_low := temp_low;
    page_boundary_high := temp_low + (pagesize(SIM_DEVICE,binary_page) - 1);
    current_address := temp_low + byte;
    --memno 10 is for memory access---
    mem_no := 10;
end compute_address;


procedure read_out_array 
                (signal CLK,CSB : in std_logic;
                page_size : in integer range 1 to 1056;
                mem_size  : in integer range 1 to 69206016;
                page_boundary_low : in integer;
                page_boundary_high :in integer;
                current_address : in integer;
                memory : in memtype;
                signal so_reg : out std_logic;
                binary_page : in std_logic;
                signal so_on1  : out std_logic
                )
                 is
variable temp_reg1 : std_logic_vector(7 downto 0);
variable temp_high : integer;
variable temp_low  : integer;
variable temp_add  : integer;
begin               
    temp_high := page_boundary_high;
    temp_low := page_boundary_low;
    temp_add := current_address;
    temp_reg1 :=  memory(temp_add);
    read_array_loop : loop
        for i in 7 downto 0 loop
            wait until (CLK'EVENT and CLK ='0') or (CSB'EVENT and CSB='1');
            exit read_array_loop when (CSB='1' ) ;
            SO_reg <= temp_reg1(i); 
            so_on1 <= '1';
        end loop;
        temp_add := temp_add + 1;
        if (temp_add >= N)then  -- N = size of memory
            temp_add := 0; --Note that rollover occurs at end of memory,
            temp_high := pagesize(SIM_DEVICE,binary_page) - 1; -- and not at the end of the page
            temp_low := 0;
        end if;
        if (temp_add > temp_high) then-- going to next page
            temp_high := temp_high + pagesize(SIM_DEVICE,binary_page);
            temp_low  := temp_low + pagesize(SIM_DEVICE,binary_page);
        end if;
        temp_reg1 :=  memory(temp_add);
    end loop;
    SO_reg <= '0';
    so_on1 <= '0';  
end read_out_array;


procedure transfer_to_buffer  
            (
             buf_type : in std_logic_vector(1 downto 0);
             page_boundary_low : in integer;
            memory : in memtype;
            buf1 : inout buffer1;
            binary_page : in std_logic;
            buf2 : inout buffer2
            ) is    
begin   
if (buf_type = "01") then
    for i in 0 to pagesize(SIM_DEVICE,binary_page)-1 LOOP
       buf1(i) := memory(page_boundary_low + i);
    end loop;   
  elsif (buf_type = "10") then
    for  i in 0 to pagesize(SIM_DEVICE,binary_page)-1 loop
       buf2(i) := memory(page_boundary_low + i);
       end loop;
end if;
end transfer_to_buffer;


procedure compare_with_buffer
(
    buf_type : in std_logic_vector(1 downto 0);
    page_boundary_low : in integer;
    memory : in memtype;
    buf1 : in buffer1;
    buf2 : in buffer2;
    binary_page : in std_logic;
    signal status : out std_logic
) is
variable tmp1,tmp2 : std_logic_vector(7 downto 0);
begin
    status <='0';
    if(buf_type = "01")then
        for i in 0 to pagesize(SIM_DEVICE,binary_page)-1 loop
        tmp1 := memory(page_boundary_low  + i);
        tmp2 := buf1(i);
        for k in 0 to 7 loop
        if(tmp1(k) /= tmp2(k) ) then
            status <= '1';
            exit;
            end if;
            end loop;
        end loop;
        elsif  (buf_type = "10") then
        for i in 0 to pagesize(SIM_DEVICE,binary_page)-1 loop
            tmp1 := memory(page_boundary_low  + i);
            tmp2 := buf2(i);
            for k in 0 to 7 loop
                if(tmp1(k) /= tmp2(k) ) then
                    status <= '1';
                    exit;
                end if;
            end loop;
        end loop;
    end if;
end compare_with_buffer;


-----------write_data------------
procedure write_data 
            ( current_address : inout integer;
             page_boundary_low : in integer;
             page_boundary_high : in integer;
             buf1 : inout buffer1;
             buf2 : inout buffer2; 
             buf_type : in std_logic_vector(1 downto 0);
             signal CSB,CLK,MOSI   : in std_logic
             ) is
variable buf_temp_reg : std_logic_vector(7 downto 0);
variable temp :std_logic := '0';
begin
    write_loop : loop
        for i in 7 downto 0 loop
            wait until (CLK'EVENT and CLK ='1') or (CSB'EVENT and CSB='1');
            if (CSB='1') then
                exit write_loop;
            end if;
            buf_temp_reg(i):=MOSI;
        end loop;   
        if (buf_type="01") then
            buf1(current_address):= buf_temp_reg;  
        elsif(buf_type="10") then
            buf2(current_address):= buf_temp_reg;  
        end if;
        current_address := current_address + 1;
        wait for 1 ps;
        if (current_address > page_boundary_high) then  
            current_address := page_boundary_low;
            wait for 1 ps;
        end if;
    end loop;
end write_data;


procedure write_to_memory 
                (
                buf_type : in std_logic_vector(1 downto 0);
                 page : in std_logic_vector((P_ADDRESS(SIM_DEVICE))-1 DOWNTO 0);
                 page_size : in integer range 1 to 1056;
                buf1 : in buffer1;
                buf2 : in  buffer2;
                
                 page_boundary_low : in integer;
                memory : inout memtype
                    ) is
begin
if (buf_type = "01") then
    for i in 0 to page_size-1 loop
       memory(page_boundary_low+i) := buf1(i);
    end loop;   
  elsif (buf_type = "10") then
    for i in 0 to page_size-1 loop
       memory(page_boundary_low+i) := buf2(i);
    end loop;
end if;
end write_to_memory;


procedure erase_page  
            (
            page : in std_logic_vector((P_ADDRESS(SIM_DEVICE))-1 DOWNTO 0);
            page_size : in integer range 1 to 1056;
            page_boundary_low : in integer;
            memory : inout memtype;
            binary_page : in std_logic;
            page_status : out std_logic 
            ) is
variable buf1 : buffer1;
variable buf2 : buffer2;
begin
for i in 0 to pagesize(SIM_DEVICE,binary_page)-1 loop
    memory(page_boundary_low + i ) := X"FF";
    page_status :='0';
end loop;
end erase_page;


----------read_out_reg--------
procedure read_out_reg 
            ( reg_type : in integer;
              add      : in integer;
              high     : in integer;
            security_reg : in security_type ;    
            signal CSB,CLK       : in std_logic;
            signal so_reg    : out std_logic;
            signal  so_on1     : out std_logic
            ) is
variable temp_add : integer;
variable t_reg1 : std_logic_vector(7 downto 0);
begin
    temp_add := add;
    t_reg1 := security_reg(temp_add);
    read_out_reg_loop : loop
        for i in 7 downto 0 loop
            wait until (CLK'EVENT and CLK ='0') or (CSB'EVENT and CSB='1');
            exit read_out_reg_loop when (CSB='1' ) ;
            so_reg <= t_reg1(i);
            so_on1   <= '1';
        end loop;   
        temp_add := temp_add + 1;
        if ( temp_add > high)then
            t_reg1 := (others => 'X' );
        else
            if (reg_type=23) then 
                if (temp_add < 64) then
                    t_reg1 := security_reg(temp_add);   
                else
                    t_reg1 := factory_reg(temp_add-64); 
                end if;
            end if;
        end if;     
     end loop;
     so_reg <= '1';
     so_on1 <= '0';
end read_out_reg;       


function getbyte    (
            IP : in bit_vector(511 downto 0);
            byte_num  : in integer
            ) return bit_vector is

variable temp : bit_vector( 7 downto 0);                
begin

    for i in 0 to 7 loop
    temp(i) := IP((byte_num-1)*8+i);
    end loop;           
return temp;

end getbyte;

procedure read_mem_file (
            --signal memory : inout memtype;
            memory : inout memtype;
            inbuf : inout line
            )is                
     file LOAD_FILE1 : text open read_mode is SIM_MEM_FILE;
     variable numword : integer := 0;
     variable value : bit_vector(7 downto 0);
begin                          
    if(SIM_MEM_FILE /= "NONE")then 
        while not ENDFILE(LOAD_FILE1) loop 
            READLINE(LOAD_FILE1,inbuf);
            hexa_to_bit_vector(inbuf, 8, value);
            memory(numword) := to_stdlogicvector(value);
            numword := numword + 1;
            if(numword = (N-1)) then
                 exit;         
            end if;            
        end loop;              
    end if;                    
end read_mem_file;             
                               
--******************************************---
--******************************************--
signal temp_reg1 : std_logic_vector(7 downto 0);
signal reset_sig : std_logic:= '0';
signal skip : std_logic := '1';
signal skip_be : std_logic := '0';
signal skip_end : std_logic := '0';
signal opcode_temp : std_logic_vector(7 downto 0) := "00000000";
signal page_addr0 : std_logic_vector(7 downto 0) := "00000000";
signal page_addr1 : std_logic_vector(7 downto 0) := "00000000";
signal byte_addr  : std_logic_vector(7 downto 0) := "00000000";
signal t : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
signal rd_data1 : std_logic_vector(7 downto 0);
signal arr_rd_dummybyte : integer := 0;
signal buff_rd_dummybyte : integer:= 0;

signal valid : Boolean := TRUE;
signal no_test : Boolean := FALSE;
signal  MIR : std_logic :='0';  
signal  SRR : std_logic:='0';  
signal  SRP : std_logic:='0';  
signal  err_flg : std_logic:='0';
signal mem_initialized : std_logic;
signal deep_power_down : std_logic := '0';
signal  SR : std_logic:= '0';  
signal RDYBSY_reg : std_logic :='1'; 
signal foreground_op_enable : std_logic :='0';
signal background_op_enable : std_logic:='0';
signal status_read : std_logic :='0';
signal so_reg : std_logic := '1';
signal so_on : std_logic :='0';
signal so_reg1 : std_logic := '1';
signal so_on1 : std_logic :='0';
signal so_reg2 : std_logic := '1';
signal so_on2 : std_logic :='0';
signal so_reg3 : std_logic := '1';
signal so_on3 : std_logic :='0';
signal status : std_logic_vector(7 downto 0):= ('1' & '0' &  Device_sel3(SIM_DEVICE) & Device_sel2(SIM_DEVICE) & Device_sel1(SIM_DEVICE)& '1' & '0' & '0');

-----------status signal-------------

signal status_B1C_s6 : std_logic;
signal status_B2C_s6 : std_logic;


  signal        MISO_zd          : std_ulogic := '1';

  signal        CLK_ipd          : std_ulogic := '0';
  signal        CSB_ipd          : std_ulogic := '0';
  signal        MOSI_ipd         : std_ulogic := '0';

  signal        CLK_dly          : std_ulogic := 'X';
  signal        CSB_dly          : std_ulogic := 'X';
  signal        csbx             : std_ulogic := 'X';
  
  signal        MOSI_dly         : std_ulogic := '0';
  signal        Violation        : std_ulogic := '0';

--**************** begin of Architecture **************---


begin

  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  prcs_input:process(MOSI,CSB,CLK)
  begin
      MOSI_dly   <= MOSI ;
      CSB_dly    <= CSB ; 
      CLK_dly    <= CLK ;
  end process prcs_input;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--comparing the opcodes--
process(CLK_dly,MOSI_dly,CSB_dly)
begin
    if ( CSB_dly ='1') then
        t <="00000000000000000000000000000000";
        rd_data1 <= "00000000";
    elsif(CLK_dly = '1' and CLK_dly'event) then
        t(0) <= '1';
        t(1) <= t(0);
        t(2) <= t(1);
        t(3) <= t(2);
        t(4) <= t(3);
        t(5) <= t(4);
        t(6) <= t(5); 
        t(7) <= t(6);         -- t(6) == 1 and t(7) ==0 opcode
        t(8) <= t(7);
        t(9) <= t(8);
        t(10) <= t(9);
        t(11) <= t(10);
        t(12) <= t(11);
        t(13) <= t(12);
        t(14) <= t(13);
        t(15) <= t(14);       -- t(14) == 1 and t(15) ==0 page address 
        t(16) <= t(15);      
        t(17) <= t(16);
        t(18) <= t(17);
        t(19) <= t(18);
        t(20) <= t(19);
        t(21) <= t(20);
        t(22) <= t(21);
        t(23) <= t(22);     -- t(22) == 1 and t(23) ==0 page address 
        t(24) <= t(23);
        t(25) <= t(24);
        t(26) <= t(25);
        t(27) <= t(26);
        t(28) <= t(27);
        t(29) <= t(28);
        t(30) <= t(29);
        t(31) <= t(30);     -- t(30) == 1 and t(31) == 0  byte address 
            rd_data1(0) <= MOSI_dly;
            rd_data1(1) <= rd_data1(0);
            rd_data1(2) <= rd_data1(1);
            rd_data1(3) <= rd_data1(2);
            rd_data1(4) <= rd_data1(3);
            rd_data1(5) <= rd_data1(4);
            rd_data1(6) <= rd_data1(5);
            rd_data1(7) <= rd_data1(6);
        
        end if;
end process ;

opcode_temp  <=   rd_data1(6) & rd_data1(5) & rd_data1(4) & rd_data1(3) & rd_data1(2) & rd_data1(1) & rd_data1(0) & MOSI_dly ; 
process(CLK_dly,opcode_temp, t)
begin
    if (CSB_dly = '1' ) then
    page_addr0 <= "00000000";
    page_addr1 <= "00000000";
    byte_addr <= "00000000";

    elsif ((CLK_dly = '1' and CLK_dly'event)) then
        if (t(14) = '1' and t(15) = '0') then    
        page_addr0 <= opcode_temp;
        end if;
        if (t(22) = '1' and t(23) = '0') then    
        page_addr1 <= opcode_temp;
        end if;
        if (t(30) = '1' and t(31) = '0') then    
        byte_addr <= opcode_temp;
        end if;
    end if;
end process;


process(CLK_dly,opcode_temp, t)
variable opcode_message : string(1 to 52);
variable Message : line;
begin
    if (CSB_dly = '1' )  then
            skip <='1';
            arr_rd_dummybyte <= 0;  --not used in their code
            buff_rd_dummybyte <= 0;
            MMCAR <='0';
            MMPTBT <='0'; --Main Memory Page To Buffer 1 Transfer
            MMPTBC <='0';--Main Memory Page To Buffer 1 Compare
            B1W <='0'; -- Buffer 1 Write
            B2W <='0'; 
            BTMMPP <= '0' ;--Buffer 1 To Main Memory Page Prog With Built-In Erase
            PE<='0';  -- Page Erase
            SE <='0';  -- Sector Erase
            MMPPB<='0';   -- Main Memory Page Prog. Through Buffer 1
            SR<='0' ; -- Status Register Read
            MIR<='0'; -- Manufecturing ID Read
            SRR<='0';  -- Security Register Read
            SRP<='0';  -- Secturity Register Program
            backgnd_while_busy_err<='0';
    elsif (CLK_dly = '1' and CLK_dly'event) then
        if (t(6) = '1' and t(7) = '0' ) then    
            if(foreground_op_enable='0')then
                Write ( Message, string'("DRC Error : In "));
                Write ( Message, InstancePath); 
                Write ( Message, string'(" No opcode is allowed. "));
                Write ( Message, delay_cal(TVCSL,scaled_flag) );
                Write ( Message, string'( "delay is required before device can be selected"));
                assert false report Message.all severity warning;
                DEALLOCATE (Message);        
            elsif(cycle_mode="MODE0")then
                Write ( Message, string'("DRC Error : In "));
                Write ( Message, InstancePath); 
                Write ( Message, string'( " must drive CSB LOW while CLK is HIGH."));
                assert false report Message.all severity failure;
                DEALLOCATE (Message);        
            else    
                case opcode_temp is
                    when X"03" =>
                        cmd_name <="Random Read                             ";
                        random <= TRUE;
                        if(RDYBSY_reg='0')then
                           backgnd_while_busy_err<='1';
                           write_busy_message;
                        else
                            skip <='0';
                            arr_rd_dummybyte <= 0;
                            MMCAR <='1';
                        end if;
                     when X"0B" =>
                        cmd_name<="Main Memory Continuous Array Read       ";
                        random <= FALSE;
                        if(RDYBSY_reg='0')then 
                           backgnd_while_busy_err<='1';
                           write_busy_message;
                        else
                            skip <='0';
                            arr_rd_dummybyte <= 1;
                            MMCAR <='1';
                        end if;
                    when X"53" =>
                        cmd_name<="Main Memory Page To Buffer 1 Transfer   ";
                        if(background_op_enable='0') then
                            write_tpuw_message;
                        elsif(RDYBSY_reg='0')then 
                           backgnd_while_busy_err<='1';
                           write_busy_message;
                        else
                           buff_num <= "01";  -- buffer 1
                           MMPTBT <='1'; --Main Memory Page To Buffer 1 Transfer
                        end if;
                    when X"55" =>
                        cmd_name<="Main Memory Page To Buffer Transfer     ";
                        if(buffers(SIM_DEVICE) = 1 )then
                            write_opcode_message;
                        elsif(background_op_enable='0') then
                            write_tpuw_message;
                        elsif(RDYBSY_reg='0')then 
                            backgnd_while_busy_err<='1';
                            write_busy_message;
                        else
                            buff_num <= "10";  --buffer 2
                            MMPTBT<='1'; --Main Memory Page To Buffer 2 Transfer
                        end if;
                    when X"60" =>
                        cmd_name<="Main Memory Page To Buffer 1 Compare    ";
                        if(background_op_enable='0') then
                            write_tpuw_message;
                        elsif(RDYBSY_reg='0')then 
                            backgnd_while_busy_err<='1';
                            write_busy_message;
                        else
                           buff_num <= "01";  -- buffer 1
                           MMPTBC <='1';--Main Memory Page To Buffer Compare
                        end if;
                    when X"61" =>
                          cmd_name<="Main Memory Page To Buffer 2 Compare    ";
                        if(buffers(SIM_DEVICE) = 1 )then
                            write_opcode_message;
                        elsif(background_op_enable='0') then
                            write_tpuw_message;
                        elsif(RDYBSY_reg='0')then 
                           backgnd_while_busy_err<='1';
                           write_busy_message;
                        else
                            buff_num <= "10";  --buffer 2
                            MMPTBC <='1';--Main Memory Page To Buffer Compare
                        end if;
                    when X"84" =>
                           cmd_name <= "Buffer 1 Write                          ";
                           buff_num<= "01"; -- use buffer 1
                           B1W <='1'; -- Buffer 1 Write
                    when X"87" =>
                        cmd_name<="Buffer 2 Write                          ";
                        if(buffers(SIM_DEVICE) = 1 )then
                            write_opcode_message;
                        else   
                           buff_num<= "10"; -- use buffer 2
                           B2W <='1'; -- Buffer 2 Write
                        end if;     
                    when X"83" =>
                        cmd_name <="Buffer 1 To Main Memory Page Prog Erase ";
                        if(background_op_enable='0') then
                            write_tpuw_message;
                        elsif(RDYBSY_reg='0')then 
                           backgnd_while_busy_err<='1';
                           write_busy_message;
                        else
                             erase_flag <= '1';
                             buff_nump<= "01"; -- use buffer 1
                           BTMMPP <= '1' ;--Buffer 1 To Main Memory Page Prog With Built-In Erase
                        end if;
                    when X"86" =>
                        cmd_name <="Buffer 2 To Main Memory Page Prog Erase ";
                        if(buffers(SIM_DEVICE) = 1 )then
                            write_opcode_message;
                        elsif(background_op_enable='0') then
                            write_tpuw_message;
                        elsif(RDYBSY_reg='0')then 
                            backgnd_while_busy_err<='1';
                            write_busy_message;
                        else
                            erase_flag <= '1';
                            buff_nump<= "10"; -- use buffer 2
                            BTMMPP <= '1';-- t(14) == 1 and t(15) ==0 page address --Buffer 2 To
                                  -- Main Memory Page Prog With Built-In Erase
                        end if;
                    when X"88" =>
                        cmd_name <="Buffer 1 To Main Memory Page Prog       ";
                        if(background_op_enable='0') then
                            write_tpuw_message;
                        elsif(RDYBSY_reg='0')then 
                           backgnd_while_busy_err<='1';
                           write_busy_message;
                        else
                             erase_flag <= '0';
                             buff_nump<= "01"; -- use buffer 1
                             BTMMPP<='1';--- t(14) == 1 and t(15) ==0 page address -Buffer 1 To 
                                  --Main Memory Page Prog Without Built-In Erase
                        end if;
                    when X"89" =>
                        cmd_name <="Buffer 2 To Main Memory Page Prog       ";
                        if(buffers(SIM_DEVICE) = 1 )then
                            write_opcode_message;
                        elsif(background_op_enable='0') then
                            write_tpuw_message;
                        elsif(RDYBSY_reg='0')then 
                            backgnd_while_busy_err<='1';
                            write_busy_message;
                        else
                            erase_flag <= '0';
                            buff_nump<= "10"; -- use buffer 2
                            BTMMPP<='1' ;--Buffer 2 To Main Memory Page Prog Without Built-In Erase
                        end if;
                    when X"81" =>
                        cmd_name <="Page Erase                              ";
                        if(background_op_enable='0') then
                            write_tpuw_message;
                        elsif(RDYBSY_reg='0')then 
                           backgnd_while_busy_err<='1';
                           write_busy_message;
                        else
                           PE<='1';  -- Page Erase
                        end if;
                    when X"82" =>
                        cmd_name <="Main Memory Page Prog. Through Buffer 1 ";
                        if(background_op_enable='0') then
                            write_tpuw_message;
                        elsif(RDYBSY_reg='0')then 
                           backgnd_while_busy_err<='1';
                           write_busy_message;
                        else
                             buff_num <= "01";
                           MMPPB<='1';   -- Main Memory Page Prog. Through Buffer 1
                        end if;
                    when X"7C" =>
                        cmd_name <="Sector Erase                            ";
                        if(background_op_enable='0') then
                            write_tpuw_message;
                        elsif(RDYBSY_reg='0')then 
                           backgnd_while_busy_err<='1';
                           write_busy_message;
                        else
                           SE <='1';  -- Sector Erase
                        end if;
                    when X"85" =>
                        cmd_name <="Main Memory Page Prog. Through Buffer 2 ";
                        if(buffers(SIM_DEVICE) = 1 )then
                             write_opcode_message;
                        elsif(background_op_enable='0') then
                            write_tpuw_message;
                        elsif(RDYBSY_reg='0')then 
                           backgnd_while_busy_err<='1';
                           write_busy_message;
                        else
                            buff_num <= "10";
                            MMPPB<='1' ;  -- Main Memory Page Prog. Through Buffer 2
                        end if;
                    when X"D7" =>
                        cmd_name <="Status Register Read                    ";
                        skip <='0';
                        SR<='1'; -- Status Register Read
                    when X"9F" =>
                        cmd_name <="Manufacturer ID Read                    ";
                        skip <='0';
                        MIR<='1'; -- Manufacturing ID Read
                    when X"9B" =>
                        cmd_name <="Security Register Program               ";
                        if(background_op_enable='0') then
                            write_tpuw_message;
                        elsif(RDYBSY_reg='0')then 
                           backgnd_while_busy_err<='1';
                           write_busy_message;
                        else
                            SRP<='1';  -- 4-Byte Opcode Starting From 9B this is for Security register program
                        end if;
                    when X"77" =>
                        cmd_name <="Security Register Read                  ";
                        if(RDYBSY_reg='0')then 
                           backgnd_while_busy_err<='1';
                           write_busy_message;
                        else
                            SRR<='1';  -- Security Register Read
                        end if;
                    when others =>
                        if (opcode_temp=X"D2" or opcode_temp=X"E8" or opcode_temp=X"D4" or opcode_temp=X"D6" or 
                          opcode_temp=X"D1" or opcode_temp=X"D3" or opcode_temp=X"54" or opcode_temp=X"56" or 
                          opcode_temp=X"52" or opcode_temp=X"59" or opcode_temp=X"68" or opcode_temp=X"50" or 
                          opcode_temp=X"B9" or opcode_temp=X"AB" or opcode_temp=X"3D" or opcode_temp=X"80" or 
                          opcode_temp=X"A6" or opcode_temp=X"58" or opcode_temp=X"30" or opcode_temp=X"35" or
                          opcode_temp=X"9A" or opcode_temp=X"32" ) then
                            write_opcode_message;
                        else
                            Write ( Message, string'("DRC Error : In "));
                            Write ( Message, InstancePath); 
                            Write ( Message, string'(" opcode is not recognized "));
                            assert false report Message.all severity failure;
                            DEALLOCATE (Message);       
                        end if;
                end case;
            end if;
        end if;
    end if;
end process;

-------------------------------------------------------------------------------------
----------------------------------------Main Process --------------------------------
process(CLK_dly,CSB_dly)
begin
   if(CSB_dly='0' and CSB_dly'event)then
      if (CLK_dly = '0') then
      skip_be <= '1';
      cycle_mode <= "MODE0";
      else 
      skip_be <= '0';
      cycle_mode <= "MODE3";
      end if;
  elsif(CSB_dly='1') then
      cycle_mode <= "idle ";
  end if;   
end process ;
skip_end <= skip_be and skip;
background_op_enable <= '1'  after delay_cal(TPUW,scaled_flag) ;
reset_sig <=  '0', '1' after  1 ns;
process
variable tbuffer1 : buffer1;
variable tbuffer2 : buffer2;
variable inbuf : line;
variable word : string(1 to 8);
variable i : integer;
----------
variable inbuf1 : line;
variable numword1 : integer := 0;
variable value1 : bit_vector(7 downto 0);

variable jerase : integer;
 ---------------
variable inbuf2 : line;
variable outbuf12 : line;
variable numword2 : integer := 0;
variable value2 : bit_vector(7 downto 0);
---------------------
variable inbuf3 : line;
variable numword3 : integer := 0;
variable value3 : bit_vector(7 downto 0);
------------------
variable MMPPB_mem_page : std_logic_vector(p_address(SIM_DEVICE)-1 downto 0);
variable MMPPB_buf_page : std_logic_vector(p_address(SIM_DEVICE)-1 downto 0);
variable buf_temp_reg1 : std_logic_vector(7 downto 0);
variable message1 : string(1 to 45);
variable message2 : string(1 to 30); 
variable current_address : integer; 
variable page_boundary_low : integer := 0;
variable page_boundary_high : integer;
variable mem_no : integer;
variable memory : memtype;
-- variable security_reg : security_type;

-- variable binary_page : std_logic;
variable never_set : std_logic := '0';
variable temp_page_status : std_logic;
variable buffer_number : integer;
variable page_status : std_logic_vector(page_cal(SIM_DEVICE)-1 downto 0);
variable Message : line;
variable value_fact : bit_vector(511 downto 0);
variable value_user : bit_vector(511 downto 0);

begin

if (foreground_op_enable = '0') then  ---- Enable foreground op_codes
wait on reset_sig ;
wait for 1 ps;
for i in 0 to (memsize(pagesize(SIM_DEVICE,binary_page),page_cal(SIM_DEVICE))-1) loop  
memory(i) := (others=>'1');
end loop;

mem_initialized <= '0';
wait for 1 ps;
If(SIM_MEM_FILE /= "NONE") then
    read_mem_file(memory,inbuf);
mem_initialized <= '1';
end if;
wait for 1 ps;
if (mem_initialized = '1') then
  for j in 0 to page_cal(SIM_DEVICE)-1 loop
    page_status(j) := '1'; -- memory was initialized, so, Pages are Not Erased.
  end loop;
  else
  for j in 0 to page_cal(SIM_DEVICE)-1 loop
    page_status(j) := '0';
  end loop;
  
end if;
wait for 1 ps;

---------------initialization of factory reg------------

wait for 1 ps;
--hexa_to_bit_vector(SIM_FACTORY_ID, 512, value_fact);
--hexa_to_bit_vector(SIM_USER_ID, 512, value_user);
for j in 0 to 63 loop
--    factory_reg(j)  <= To_stdlogicvector(getbyte(to_bitvector(SIM_FACTORY_ID),j+1));
--    security_reg(j) <= To_stdlogicvector(getbyte(to_bitvector(SIM_USER_ID),j+1));
    factory_reg(j)  <= To_stdlogicvector(getbyte(SIM_FACTORY_ID,j+1));
    security_reg(j) <= To_stdlogicvector(getbyte(SIM_USER_ID,j+1));
    wait for 1 ps;
         security_flag <='0';
     if(security_reg(j) /= X"FF")then
        security_flag <= '1';
      end if;
end loop;     

wait for 1 ps;


--**************************
--wait for delay_cal(TVCSL,scaled_flag);
foreground_op_enable <= '1' ; ---- Enable foreground op_codes
end if;
--**************************
    
    wait on t(31);
if(MMCAR='1' and t(31) = '1')then
    if (random=TRUE) then
      test_33mhz <= TRUE;
      wait for 1 ps;
    end if;
    compute_address(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),pagesize(SIM_DEVICE,binary_page),
        comp_byte_addr(b_address(SIM_DEVICE,binary_opt),page_addr1,byte_addr,binary_page),
        page_boundary_low,page_boundary_high,current_address,mem_no,binary_page);
    if (arr_rd_dummybyte = 1) then
        for j in 1 to 8 loop
            wait until CLK_dly'event and CLK_dly ='1';
        end loop; 
    end if;
    read_out_array(CLK_dly,CSB_dly,pagesize(SIM_DEVICE,binary_page),memsize(pagesize(SIM_DEVICE,binary_page),page_cal(SIM_DEVICE)),page_boundary_low,
               page_boundary_high,current_address,memory,so_reg,binary_page,so_on);
    test_33mhz <= FALSE ;  -- leave the test on long enough to capture an error
    wait for 1 ps;
elsif(MMPTBT='1'and t(31) = '1')then
    test_33mhz <= TRUE;  -- test for 33 Mhz
    compute_address(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),pagesize(SIM_DEVICE,binary_page),
                           comp_byte_addr(b_address(SIM_DEVICE,binary_opt),page_addr1,byte_addr,binary_page),page_boundary_low,
                           page_boundary_high, current_address,mem_no,binary_page);
    if (CSB_dly ='0')then
       wait until CSB_dly'event and CSB_dly ='1';
    end if; 
    RDYBSY_reg <= '0';  --SIM_DEVICE is busy
    status(7)  <= '0';
    transfer_to_buffer(buff_num, page_boundary_low,memory,tbuffer1,binary_page,tbuffer2);
    wait for 1 ps;
    RDYBSY_reg <= '1' after delay_cal(TXFR,scaled_flag);  
    status(7)  <= '1' after delay_cal(TXFR,scaled_flag);
    test_33mhz <= FALSE  after delay_cal(TXFR,scaled_flag) ;
    wait for 1 ps;
elsif(MMPTBC='1' and t(31) = '1')then
    compute_address(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),pagesize(SIM_DEVICE,binary_page),
    comp_byte_addr(b_address(SIM_DEVICE,binary_opt),page_addr1,byte_addr,binary_page),
        page_boundary_low,page_boundary_high, current_address,mem_no,binary_page);
    if (CSB_dly ='0')then
       wait until CSB_dly'event and CSB_dly = '1';
    end if; 
    RDYBSY_reg <= '0';  --device is busy
    status(7)  <= '0';
    wait for 1 ps; --assignments won't take hold without a delay
    compare_with_buffer(buff_num,page_boundary_low,memory,tbuffer1,tbuffer2,binary_page,status_B1C_s6);
    wait for 1 ps;
    RDYBSY_reg <= '1'after delay_cal(TCOMP,scaled_flag);   -- device is now ready
    status(7) <= '1' after delay_cal(TCOMP,scaled_flag);
    status(6)  <= status_B1C_s6 after delay_cal(TCOMP,scaled_flag);
    wait for 1 ps;
elsif(B1W='1' and t(31) = '1')then
    byte <= comp_byte_addr(b_address(SIM_DEVICE,binary_opt),page_addr1,byte_addr,binary_page);
    compute_address(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),pagesize(SIM_DEVICE,binary_page),
              comp_byte_addr(b_address(SIM_DEVICE,binary_opt),page_addr1,byte_addr,binary_page),
              page_boundary_low,page_boundary_high, current_address,mem_no,binary_page);
    write_data(current_address,page_boundary_low,page_boundary_high,tbuffer1,tbuffer2,"01",CSB_dly,CLK_dly,MOSI_dly);
elsif(B2W='1' and t(31) = '1')then
    byte <= comp_byte_addr(b_address(SIM_DEVICE,binary_opt),page_addr1,byte_addr,binary_page);
    compute_address(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),pagesize(SIM_DEVICE,binary_page),
              comp_byte_addr(b_address(SIM_DEVICE,binary_opt),page_addr1,byte_addr,binary_page),
              page_boundary_low,page_boundary_high, current_address,mem_no,binary_page);
    write_data(current_address,page_boundary_low,page_boundary_high,tbuffer1,tbuffer2,"10",CSB_dly,CLK_dly,MOSI_dly);
elsif(BTMMPP='1'and t(31) = '1')then
    compute_address(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),pagesize(SIM_DEVICE,binary_page),
            comp_byte_addr(b_address(SIM_DEVICE,binary_opt),page_addr1,byte_addr,binary_page),
            page_boundary_low,page_boundary_high, current_address,mem_no,binary_page);
    if (CSB_dly ='0')then
       wait until CSB_dly'event and CSB_dly ='1';
    end if; 
    RDYBSY_reg <= '0'; -- device is busy
    status(7) <= '0';
    write_to_memory(buff_nump,comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),
         pagesize(SIM_DEVICE,binary_page),tbuffer1,tbuffer2,page_boundary_low,memory);
    if (erase_flag = '0') then
        if (page_status(conv_integer(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,
                                           page_addr1,manid(SIM_DEVICE)))) = '1') then  --page is not erased
            Write ( Message, string'("DRC Error : In "));
            Write ( Message, InstancePath); 
            Write ( Message, string'(" trying to write into a Page which is not erased"));
            assert false report Message.all severity failure;
            DEALLOCATE (Message);       
        end if;
        wait for 1 ps;
        RDYBSY_reg <= '1' after delay_cal(TP,scaled_flag);   -- device is now ready
        status(7) <= '1'  after delay_cal(TP,scaled_flag);
        wait for 1 ps;
    else
        page_status(conv_integer(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)))) := '1';
        wait for 1 ps;
        RDYBSY_reg <= '1' after delay_cal(TPEP,scaled_flag) ;   -- device is now ready
        status(7) <= '1'  after delay_cal(TPEP,scaled_flag) ;
        wait for 1 ps;   
    end if;
elsif(MMPPB='1' and t(31)='1' and RDYBSY_reg='1')then
    MMPPB_mem_page := comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE));
    -- page value has been stored for main memory page program
    MMPPB_buf_page := (others=>'0');--buffer has zero pages
    compute_address(MMPPB_buf_page,pagesize(SIM_DEVICE,binary_page),comp_byte_addr(b_address(SIM_DEVICE,binary_opt),
                   page_addr1,byte_addr,binary_page),page_boundary_low,page_boundary_high,current_address,mem_no,binary_page);
    write_data(current_address,page_boundary_low,page_boundary_high,tbuffer1,tbuffer2,buff_num,CSB_dly,CLK_dly,MOSI_dly);
          -- this will write to buffer  -- it will proceed to next step, when, posedge of CSB.
          -- This is complicated, and, hence, explained here: At posedge of CSB, the write_data will get disabled.
          -- At this time, writing to buffer needs to stop, and, writing into memory should start.

    compute_address(MMPPB_mem_page,pagesize(SIM_DEVICE,binary_page),comp_byte_addr(b_address(SIM_DEVICE,binary_opt),page_addr1,byte_addr,
                    binary_page),page_boundary_low,page_boundary_high,current_address,mem_no,binary_page);
    RDYBSY_reg <= '0'; -- device is busy
    status(7) <='0';
    write_to_memory(buff_num,comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),
                    pagesize(SIM_DEVICE,binary_page),tbuffer1,tbuffer2,page_boundary_low,memory);
    page_status(conv_integer(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)))) := '1';
    wait for 1 ps;
    RDYBSY_reg <= '1' after delay_cal(TPEP,scaled_flag) ;    -- device is now ready
    status(7) <= '1'  after delay_cal(TPEP,scaled_flag);
    wait for 1 ps;
----------------page erase------------------

elsif (PE = '1')then
        compute_address(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),pagesize(SIM_DEVICE,binary_page),
        comp_byte_addr(b_address(SIM_DEVICE,binary_opt),page_addr1,byte_addr,binary_page),page_boundary_low,page_boundary_high,
        current_address,mem_no,binary_page);
        if (CSB_dly ='0')then
           wait until CSB_dly'event and CSB_dly='1';
        end if; 
        RDYBSY_reg <= '0';  --device is busy
        status(7) <= '0';
        erase_page(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),
            pagesize(SIM_DEVICE,binary_page),page_boundary_low,memory,binary_page,temp_page_status);
        page_status(conv_integer(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)))) := temp_page_status;
        wait for 1 ps;
        RDYBSY_reg <= '1'  after delay_cal(TPE,scaled_flag)  ; --device is now ready
        status(7) <= '1'   after delay_cal(TPE,scaled_flag)   ;
        wait for 1 ps;
----------------sector erase------------------
    
elsif (SE = '1')then
    compute_address(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),pagesize(SIM_DEVICE,binary_page),
                          comp_byte_addr(b_address(SIM_DEVICE,binary_page),page_addr1,byte_addr,binary_page),page_boundary_low,
                          page_boundary_high,current_address,mem_no,binary_page);
    if (CSB_dly ='0')then
       wait until CSB_dly'event and CSB_dly = '1';  
    end if; 
    RDYBSY_reg <= '0';  --device is busy
    status(7) <= '0';
               --******************************--
    if (conv_integer(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE))) < 8 ) then
        page_boundary_low := 0;
        jerase := page_boundary_low;
        loop_sectorerase: loop 
            if (jerase < page_boundary_low+8*pagesize(SIM_DEVICE,binary_page) ) then
                erase_page(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),
                               pagesize(SIM_DEVICE,binary_page),jerase,memory,binary_page,temp_page_status);   -- erase 8 pages, i.e. a block
                page_status(conv_integer(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)))) := temp_page_status;
                jerase := jerase+pagesize(SIM_DEVICE,binary_page);
            else
                exit loop_sectorerase;  -------------sector Eraseexit ----------------------
            end if; 
        end loop;
        for j in 0 to 7 loop  -- erase_page will only change the status of one-page 
            page_status(j) := '0'; 
        end loop;
         --************************************----
    elsif (comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)) < pageper_sector(SIM_DEVICE)) then
        page_boundary_low := 8*pagesize(SIM_DEVICE,binary_page);
        jerase := page_boundary_low;
        loop_sector1erase : loop
            if (jerase < page_boundary_low+((pageper_sector(SIM_DEVICE)-8)*pagesize(SIM_DEVICE,binary_page)) ) then
                erase_page(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),
                pagesize(SIM_DEVICE,binary_page),jerase,memory,binary_page,temp_page_status);   --erase 248/120 pages, i.e. a block
            page_status(conv_integer(comp_page_addr(p_address(SIM_DEVICE),binary_page,
            page_addr0,page_addr1,manid(SIM_DEVICE)))) := temp_page_status;
            jerase := jerase+pagesize(SIM_DEVICE,binary_page);
            else
                exit loop_sector1erase;  -----------sector1 Eraseexit ------------------------
            end if; 
        end loop;   
        for j in 8 to pageper_sector(SIM_DEVICE)-1 loop    --erase_page will only change the status of one-page 
            page_status(j) := '0'; 
        end loop;
        --**************************** 
    else
        page((p_address(SIM_DEVICE)- s_address(SIM_DEVICE))-1) <= '0';
        jerase := page_boundary_low;
        loop_sector2erase : loop
            if (jerase < page_boundary_low+(pageper_sector(SIM_DEVICE)*pagesize(SIM_DEVICE,binary_page))) then
                erase_page(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),
                                  pagesize(SIM_DEVICE,binary_page),jerase,memory,binary_page,temp_page_status);   --erase 256/128 pages, i.e. a block
                page_status(conv_integer(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)))) := temp_page_status;
                jerase := jerase +pagesize(SIM_DEVICE,binary_page);
            else
                exit loop_sector2erase;   ----------sector2 Eraseexit ------------------------
            end if;
        end loop;
        for j in 0 to pageper_sector(SIM_DEVICE)-1 loop 
                page_status(conv_integer(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)))+j) := '0'; 
        end loop;
    end if;
    wait for 1 ps;
    RDYBSY_reg <= '1' after delay_cal(TSE,scaled_flag)  ; --device is now ready
    status(7) <= '1' after delay_cal(TSE,scaled_flag)  ;
elsif(SRR='1' and t(31)='1')then
      read_out_reg(23,0,127,security_reg,CSB_dly,CLK_dly,so_reg,so_on);
elsif(SRP ='1' and t(31)='1' and page_addr0=X"00" and page_addr1= X"00" and byte_addr = X"00" )then
        current_address :=0;
        page_boundary_low :=0;
        page_boundary_high := 63;
        write_data(current_address,page_boundary_low,page_boundary_high,tbuffer1,tbuffer2,"01",CSB_dly,CLK_dly,MOSI_dly);    
                    -- this will write to buffer
                      -- it will proceed to next step, when, posedge of CSB.
                       -- This is complicated, and, hence, explained here:
                       -- At posedge of CSB, the write_data will get disabled.
                       -- At this time, writing to buffer needs to stop, and,
                       -- writing into memory should start.
        --writing in to security_reg
        if (security_flag = '0') then  --Security Register has not been programmed before
            for j in 0 to 63 loop
                security_reg(j) <= tbuffer1(j);
            end loop;  
            security_flag <= '1';
            RDYBSY_reg <= '0'; --device is busy
            status(7) <= '0';
            wait for 1 ps;
            RDYBSY_reg <= '1' after delay_cal(TP,scaled_flag) ; --device is now ready
            status(7) <= '1'  after delay_cal(TP,scaled_flag) ;
            wait for 1 ps;
        else
            Write ( Message, string'("DRC Error : In "));
            Write ( Message, InstancePath); 
            Write ( Message, string'(" Security register can only be programmed once")); 
            assert false report Message.all severity failure;
            DEALLOCATE (Message);
        end if;
end if;
end process;

--------------------status register read--------
process    
    variable j_tmp : integer := 8;
begin
    wait on SR ;
    if( SR = '1' ) then
        status_read <='1';--reading status reg
    --    for i in 0 to 7 loop
    --    wait until CLK_dly'event and CLK_dly='0';
    --    so_reg1 <= '1'; -- the reg is set to one when data is invalid
    --    so_on1  <= '1';
    --    end loop;
        status_loop : loop
            wait until ((CLK_dly'event and CLK_dly ='0') or  (CSB_dly'event and CSB_dly='1'));
            if(CSB_dly='1') then 
                j_tmp:=0;
                exit status_loop;
            end if;
            if(j_tmp > 0)then
                j_tmp := j_tmp - 1; 
            else
                j_tmp := 7;
            end if;
                so_reg1 <= status(j_tmp);
                so_on1  <= '1';
           end loop;
           so_on1  <= '0';
           status_read <='0';
    end if;
end process;

------------manufacturing ID-----------
process   --(MIR)--,MANID(SIM_DEVICE))
    variable j : integer:= 32 ;
    variable m_id : std_logic_vector(31 downto 0):= manid(SIM_DEVICE); 
begin
wait on MIR;
    if(MIR='1')then
        MIR_loop : loop
            wait until ((CLK_dly'event and CLK_dly ='0') or  (CSB_dly'event and CSB_dly='1'));
            exit MIR_loop when CSB_dly = '1';
            if(J > 0)then
                SO_reg2 <= m_id(j-1);
                so_on2 <= '1';
                J := J - 1;
            elsif( j = 0) then
                So_on2 <= '1';
                So_reg2 <= 'X'; -- only if the cs extends more than available man ID
            end if;
        end loop;
    so_on2 <= '0';
    So_reg2 <= '0';   
    end if;
end process;

        ------------------------ CLK check
checkPeriod ( CLK_dly  , "CLK" , Tsck    , "Tsck" , TsckRp  , clk_err   , InstancePath, valid ) ;
checkPeriod ( CLK_dly  , "CLK" , Tsck33  , "Tsck" , TsckRp33, clk_err33 , InstancePath, test_33mhz ) ;
checkclk    ( CLK_dly  , "CLK" , Tspickh , "Tsck" ,TsckRpx  , TsckFp , clk_erra , InstancePath, valid, valid, valid ) ;
checkclk    ( CSB_dly  , "CSB" , Tcs     , "Tsck" ,TsckRpcsb , TsckFcsb , csb_err , InstancePath, valid, valid, no_test) ;
validate_input(SIM_DEVICE, SIM_DELAY_TYPE , scaled_flag);  -- validates inputs and set scaled_flag

process(so_on1,so_reg1,so_on2,so_reg2,so_reg, so_on)
begin
    if(so_on1='1')then
        MISO_zd <= so_reg1 after SYNC_PATH_DELAY;
    elsif(so_on2='1')then
        MISO_zd <= so_reg2 after SYNC_PATH_DELAY;
    elsif (so_on='1') then
        MISO_zd <= so_reg after SYNC_PATH_DELAY;
    else  
        MISO_zd <= '1' after Tdis;
    end if;
end process;   

--####################################################################
--#####                   TIMING CHECKS & OUTPUT                 #####
--####################################################################

--####################################################################
--#####                           OUTPUT                         #####
--####################################################################
  prcs_output:process(MISO_zd)
  begin
      MISO     <= MISO_zd ;
  end process prcs_output;


end SPI_ACCESS_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  User Interface to Global Clock, Reset and 3-State Controls for SPARTAN3A
-- /___/   /\     Filename : STARTUP_SPARTAN3A.vhd
-- \   \  /  \    Timestamp : Tue Jul  5 15:01:35 PDT 2005
--  \___\/\___\
--
-- Revision:
--    07/05/05 - Initial version.

----- CELL STARTUP_SPARTAN3A -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity STARTUP_SPARTAN3A is
  port(
    CLK : in std_ulogic := 'X';
    GSR : in std_ulogic := 'X';
    GTS : in std_ulogic := 'X'
    );
end STARTUP_SPARTAN3A;

architecture STARTUP_SPARTAN3A_V of STARTUP_SPARTAN3A is
begin
end STARTUP_SPARTAN3A_V;
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  Multifunctional, Cascadable, 48-bit Output Arithmetic Block
-- /___/   /\     Filename : DSP48A.vhd
-- \   \  /  \    Timestamp : Mon Mar 20 17:25:10 PST 2006
--  \___\/\___\
--
-- Revision:
--    03/25/06 - Initial version.
--    09/22/06 - fixed CR 421339
--    01/17/07 - fixed CR 431766
-- End Revision
----- CELL DSP48A -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_SIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;

library STD;
use STD.TEXTIO.all;


library unisim;
use unisim.vpkg.all;

entity DSP48A is

  generic(

        A0REG           : integer       := 0;
        A1REG           : integer       := 1;
        B0REG           : integer       := 0;
        B1REG           : integer       := 1;
        CARRYINREG      : integer       := 1;
        CARRYINSEL      : string        := "CARRYIN";
        CREG            : integer       := 1;
        DREG            : integer       := 1;
        MREG            : integer       := 1;
        OPMODEREG       : integer       := 1;
        PREG            : integer       := 1;
        RSTTYPE         : string        := "SYNC"
        );

  port(
        BCOUT                   : out std_logic_vector(17 downto 0);
        CARRYOUT                : out std_ulogic;
        P                       : out std_logic_vector(47 downto 0);
        PCOUT                   : out std_logic_vector(47 downto 0);

        A                       : in  std_logic_vector(17 downto 0);
        B                       : in  std_logic_vector(17 downto 0);
        
        C                       : in  std_logic_vector(47 downto 0);
        CARRYIN                 : in  std_ulogic;
        CEA                     : in  std_ulogic;
        CEB                     : in  std_ulogic;
        CEC                     : in  std_ulogic;
        CECARRYIN               : in  std_ulogic;
        CED                     : in  std_ulogic;
        CEM                     : in  std_ulogic;
        CEOPMODE                : in  std_ulogic;
        CEP                     : in  std_ulogic;
        CLK                     : in  std_ulogic;
        D                       : in  std_logic_vector(17 downto 0);
        OPMODE                  : in  std_logic_vector(7 downto 0);
        PCIN                    : in  std_logic_vector(47 downto 0);
        RSTA                    : in  std_ulogic;
        RSTB                    : in  std_ulogic;
        RSTC                    : in  std_ulogic;
        RSTCARRYIN              : in  std_ulogic;
        RSTD                    : in  std_ulogic;
        RSTM                    : in  std_ulogic;
        RSTOPMODE               : in  std_ulogic;
        RSTP                    : in  std_ulogic
      );

end DSP48A;

-- architecture body                    --

architecture DSP48A_V of DSP48A is

    procedure invalid_opmode_preg_msg( OPMODE : IN string ; 
                                   CARRYINSEL : IN string ) is
    variable Message : line;
    begin
       Write ( Message, string'("OPMODE Input Warning : The OPMODE "));
       Write ( Message,  OPMODE);
       Write ( Message, string'(" with CARRYINSEL "));
       Write ( Message,  CARRYINSEL);
       Write ( Message, string'(" to DSP48A instance "));
       Write ( Message, string'("requires attribute PREG set to 1."));
       assert false report Message.all severity Warning;
       DEALLOCATE (Message);
    end invalid_opmode_preg_msg;

    procedure invalid_opmode_mreg_msg( OPMODE : IN string ; 
                                   CARRYINSEL : IN string ) is
    variable Message : line;
    begin
       Write ( Message, string'("OPMODE Input Warning : The OPMODE "));
       Write ( Message,  OPMODE);
       Write ( Message, string'(" with CARRYINSEL "));
       Write ( Message,  CARRYINSEL);
       Write ( Message, string'(" to DSP48A instance "));
       Write ( Message, string'("requires attribute MREG set to 1."));
       assert false report Message.all severity Warning;
       DEALLOCATE (Message);
    end invalid_opmode_mreg_msg;

    procedure invalid_opmode_no_mreg_msg( OPMODE : IN string ; 
                                      CARRYINSEL : IN string ) is
    variable Message : line;
    begin
       Write ( Message, string'("OPMODE Input Warning : The OPMODE "));
       Write ( Message,  OPMODE);
       Write ( Message, string'(" with CARRYINSEL "));
       Write ( Message,  CARRYINSEL);
       Write ( Message, string'(" to DSP48A instance "));
       Write ( Message, string'("requires attribute MREG set to 0."));
       assert false report Message.all severity Warning;
       DEALLOCATE (Message);
    end invalid_opmode_no_mreg_msg;




  constant SYNC_PATH_DELAY : time := 100 ps;

  constant MAX_ACCUM      : integer    := 48;
  constant MAX_BCOUT      : integer    := 18;
  constant MAX_P          : integer    := 48;
  constant MAX_PCOUT      : integer    := 48;
  constant MSB_ACCUM      : integer    := MAX_ACCUM - 1;
  constant MSB_BCOUT      : integer    := MAX_BCOUT - 1;
  constant MSB_P          : integer    := MAX_P     - 1;
  constant MSB_PCOUT      : integer    := MAX_PCOUT - 1;

  constant MAX_A          : integer    := 18;
  constant MAX_B          : integer    := 18;
  constant MAX_BCIN       : integer    := 18;
  constant MAX_C          : integer    := 48;
  constant MAX_D          : integer    := 18;
  constant MAX_PREADD     : integer    := 18;
  constant MAX_OPMODE     : integer    := 8;
  constant MAX_PCIN       : integer    := 48;
  constant MSB_A          : integer    := MAX_A      - 1;
  constant MSB_B          : integer    := MAX_B      - 1;
  constant MSB_BCIN       : integer    := MAX_BCIN   - 1;
  constant MSB_C          : integer    := MAX_C      - 1;
  constant MSB_D          : integer    := MAX_D      - 1;
  constant MSB_PREADD     : integer    := MAX_PREADD - 1;
  constant MSB_OPMODE     : integer    := MAX_OPMODE - 1;
  constant MSB_PCIN       : integer    := MAX_PCIN   - 1;


  constant SHIFT_MUXZ     : integer    := 17;

  signal 	A_ipd		: std_logic_vector(MSB_A downto 0) := (others => '0');
  signal 	B_ipd		: std_logic_vector(MSB_B downto 0) := (others => '0');
  signal 	BCIN_ipd	: std_logic_vector(MSB_BCIN downto 0) := (others => '0');
  signal 	C_ipd		: std_logic_vector(MSB_C downto 0)    := (others => '0');
  signal 	CARRYIN_ipd	: std_ulogic := '0';
  signal 	CEA_ipd		: std_ulogic := '0';
  signal 	CEB_ipd		: std_ulogic := '0';
  signal 	CEC_ipd		: std_ulogic := '0';
  signal 	CECARRYIN_ipd	: std_ulogic := '0';
  signal 	CED_ipd		: std_ulogic := '0';
  signal 	CEM_ipd		: std_ulogic := '0';
  signal 	CEOPMODE_ipd	: std_ulogic := '0';
  signal 	CEP_ipd		: std_ulogic := '0';
  signal 	CLK_ipd		: std_ulogic := '0';
  signal 	D_ipd		: std_logic_vector(MSB_D downto 0) := (others => '0');
  signal        GSR             : std_ulogic := '0';
  signal 	GSR_ipd		: std_ulogic := '0';
  signal 	OPMODE_ipd	: std_logic_vector(MSB_OPMODE downto 0)  := (others => '0');
  signal 	PCIN_ipd	: std_logic_vector(MSB_PCIN downto 0) := (others => '0');
  signal 	RSTA_ipd	: std_ulogic := '0';
  signal 	RSTB_ipd	: std_ulogic := '0';
  signal 	RSTC_ipd	: std_ulogic := '0';
  signal 	RSTCARRYIN_ipd	: std_ulogic := '0';
  signal 	RSTD_ipd	: std_ulogic := '0';
  signal 	RSTM_ipd	: std_ulogic := '0';
  signal 	RSTOPMODE_ipd	: std_ulogic := '0';
  signal 	RSTP_ipd	: std_ulogic := '0';

  signal 	A_dly		: std_logic_vector(MSB_A downto 0) := (others => '0');
  signal 	B_dly		: std_logic_vector(MSB_B downto 0) := (others => '0');
  signal 	BCIN_dly	: std_logic_vector(MSB_BCIN downto 0) := (others => '0');
  signal 	C_dly		: std_logic_vector(MSB_C downto 0)    := (others => '0');
  signal 	CARRYIN_dly	: std_ulogic := '0';
  signal 	CEA_dly		: std_ulogic := '0';
  signal 	CEB_dly		: std_ulogic := '0';
  signal 	CEC_dly		: std_ulogic := '0';
  signal 	CECARRYIN_dly	: std_ulogic := '0';
  signal 	CED_dly		: std_ulogic := '0';
  signal 	CEM_dly		: std_ulogic := '0';
  signal 	CEOPMODE_dly	: std_ulogic := '0';
  signal 	CEP_dly		: std_ulogic := '0';
  signal 	CLK_dly		: std_ulogic := '0';
  signal 	D_dly		: std_logic_vector(MSB_D downto 0) := (others => '0');
  signal 	GSR_dly		: std_ulogic := '0';
  signal 	OPMODE_dly	: std_logic_vector(MSB_OPMODE downto 0)  := (others => '0');
  signal 	PCIN_dly	: std_logic_vector(MSB_PCIN downto 0) := (others => '0');
  signal 	RSTA_dly	: std_ulogic := '0';
  signal 	RSTB_dly	: std_ulogic := '0';
  signal 	RSTC_dly	: std_ulogic := '0';
  signal 	RSTCARRYIN_dly	: std_ulogic := '0';
  signal 	RSTD_dly	: std_ulogic := '0';
  signal 	RSTM_dly	: std_ulogic := '0';
  signal 	RSTOPMODE_dly	: std_ulogic := '0';
  signal 	RSTP_dly	: std_ulogic := '0';


  signal	BCOUT_zd	: std_logic_vector(MSB_BCOUT downto 0) := (others => '0');
  signal 	CARRYOUT_zd	: std_ulogic := '0';
  signal	P_zd		: std_logic_vector(MSB_P downto 0) := (others => '0');
  signal	PCOUT_zd	: std_logic_vector(MSB_PCOUT downto 0) := (others => '0');
  
  --- Internal Signal Declarations
  signal	qa_o_reg1	: std_logic_vector(MSB_A downto 0) := (others => '0');
  signal	qa_o_reg2	: std_logic_vector(MSB_A downto 0) := (others => '0');
  signal	qa_o_mux	: std_logic_vector(MSB_A downto 0) := (others => '0');

  signal	b_o_mux		: std_logic_vector(MSB_B downto 0) := (others => '0');
  signal	qb_o_reg1	: std_logic_vector(MSB_B downto 0) := (others => '0');
  signal	qb_o_reg2	: std_logic_vector(MSB_B downto 0) := (others => '0');
  signal	qb_o_mux0	: std_logic_vector(MSB_B downto 0) := (others => '0');
  signal	qb_o_mux	: std_logic_vector(MSB_B downto 0) := (others => '0');

  signal	qc_o_reg        : std_logic_vector(MSB_C downto 0) := (others => '0');
  signal	qc_o_mux	: std_logic_vector(MSB_C downto 0) := (others => '0');

  signal	qd_o_reg        : std_logic_vector(MSB_D downto 0) := (others => '0');
  signal	qd_o_mux	: std_logic_vector(MSB_D downto 0) := (others => '0');

  signal	preadd		: std_logic_vector(MSB_PREADD downto 0) := (others => '0');
  signal	mux_preadd	: std_logic_vector(MSB_PREADD downto 0) := (others => '0');

  signal	mult_o_int	: std_logic_vector((MSB_A + MSB_B + 1) downto 0) := (others => '0');
  signal	mult_o_reg	: std_logic_vector((MSB_A + MSB_B + 1) downto 0) := (others => '0');
  signal	mult_o_mux	: std_logic_vector((MSB_A + MSB_B + 1) downto 0) := (others => '0');

  signal	opmode_o_reg	: std_logic_vector(MSB_OPMODE downto 0) := (others => '0');
  signal	opmode_o_mux	: std_logic_vector(MSB_OPMODE downto 0) := (others => '0');

  signal	muxx_o_mux	: std_logic_vector(MSB_P downto 0) := (others => '0');
  signal	muxy_o_mux	: std_logic_vector(MSB_P downto 0) := (others => '0');
  signal	muxz_o_mux	: std_logic_vector(MSB_P downto 0) := (others => '0');

  signal	subtract_o_reg	: std_ulogic := '0';
  signal	subtract_o_mux	: std_ulogic := '0';

  signal	carryinsel_o_reg	: std_ulogic := '0';
  signal	carryinsel_o_mux	: std_ulogic := '0';

  signal	qcarryin_o_reg1	: std_ulogic := '0';
  signal	carryin0_o_mux	: std_ulogic := '0';
  signal	carryin1_o_mux	: std_ulogic := '0';
  signal	carryin2_o_mux	: std_ulogic := '0';

  signal	qcarryin_o_reg2	: std_ulogic := '0';

  signal	carryin_o_mux	: std_ulogic := '0';

  signal	accum_o		: std_logic_vector(MSB_P downto 0) := (others => '0');
  signal	qp_o_reg	: std_logic_vector(MSB_P downto 0) := (others => '0');
  signal	qp_o_mux	: std_logic_vector(MSB_P downto 0) := (others => '0');

  signal	add_i_int      : std_logic_vector(47 downto 0) := (others => '0');
  signal	add_o_int      : std_logic_vector(47 downto 0) := (others => '0');

  signal	reg_p_int         : std_logic_vector(47 downto 0) := (others => '0');
  signal	p_o_int         : std_logic_vector(47 downto 0) := (others => '0');

  signal	subtract1_o_int : std_ulogic := '0';
  signal	carryinsel1_o_int : std_logic_vector(1 downto 0) := (others => '0');
  signal	carry1_o_int     : std_ulogic := '0';
  signal	carry2_o_int     : std_ulogic := '0';


  signal	output_x_sig	  : std_ulogic := '0';

  signal	RST_META          : std_ulogic := '0';

  signal	DefDelay          : time := 10 ps;

  signal	rst_async_flag    : std_ulogic := '0';
  signal	carryinsel_attr   : std_ulogic := '0';

  signal	opmode_valid_flg  : boolean := true;

begin

  ---------------------
  --  INPUT PATH DELAYs
  ---------------------

  A_dly          	 <= A              	after 0 ps;
  B_dly          	 <= B              	after 0 ps;
  
  C_dly          	 <= C              	after 0 ps;
  CARRYIN_dly    	 <= CARRYIN        	after 0 ps;
  CEA_dly        	 <= CEA            	after 0 ps;
  CEB_dly        	 <= CEB            	after 0 ps;
  CEC_dly        	 <= CEC            	after 0 ps;
  CECARRYIN_dly  	 <= CECARRYIN      	after 0 ps;
  CED_dly        	 <= CED            	after 0 ps;
  CEM_dly        	 <= CEM            	after 0 ps;
  CEOPMODE_dly   	 <= CEOPMODE       	after 0 ps;
  CEP_dly        	 <= CEP            	after 0 ps;
  CLK_dly        	 <= CLK            	after 0 ps;
  D_dly          	 <= D              	after 0 ps;
  OPMODE_dly     	 <= OPMODE         	after 0 ps;
  PCIN_dly       	 <= PCIN           	after 0 ps;
  RSTA_dly       	 <= RSTA           	after 0 ps;
  RSTB_dly       	 <= RSTB           	after 0 ps;
  RSTC_dly       	 <= RSTC           	after 0 ps;
  RSTCARRYIN_dly 	 <= RSTCARRYIN     	after 0 ps;
  RSTD_dly       	 <= RSTD           	after 0 ps;
  RSTM_dly       	 <= RSTM           	after 0 ps;
  RSTOPMODE_dly  	 <= RSTOPMODE      	after 0 ps;
  RSTP_dly       	 <= RSTP           	after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

--####################################################################
--#####                        Initialization                      ###
--####################################################################
  prcs_init:process
  begin

-------- A0REG/A1REG  & B0REG/B1REG ------

     if((A0REG /= 0) and (A0REG /= 1 )) then
        assert false
        report "Attribute Syntax Error: Legal values for attribute A0REG on instance DSP48A are 0 or 1."
        severity Failure;
     end if;

     if((A1REG /= 0) and (A1REG /= 1 )) then
        assert false
        report "Attribute Syntax Error: Legal values for attribute A1REG on instance DSP48A are 0 or 1."
        severity Failure;
     end if;

     if((B0REG /= 0) and (B0REG /= 1 )) then
        assert false
        report "Attribute Syntax Error: Legal values for attribute B0REG on instance DSP48A are 0 or 1."
        severity Failure;
     end if;

     if((B1REG /= 0) and (B1REG /= 1 )) then
        assert false
        report "Attribute Syntax Error: Legal values for attribute B1REG on instance DSP48A are 0 or 1."
        severity Failure;
     end if;

-------- RSTTYPE ----------

     if((RSTTYPE = "SYNC") or (RSTTYPE = "sync")) then
        rst_async_flag  <= '0';
     elsif((RSTTYPE = "ASYNC") or (RSTTYPE = "async")) then
        rst_async_flag  <= '1';
     else
        assert false
        report "Attribute Syntax Error: The attribute RSTTYPE on DSP48A is incorrect. Legal values for this attribute are SYNC or ASYNC."
        severity Failure;
     end if;

-------- CARRYINSEL ---------

     if((CARRYINSEL = "CARRYIN") or (CARRYINSEL = "carryin")) then
        carryinsel_attr  <= '0';
     elsif((CARRYINSEL = "OPMODE5") or (CARRYINSEL = "opmode5")) then
        carryinsel_attr  <= '1';
     else
        assert false
        report "Attribute Syntax Error: The attribute RSTTYPE on DSP48A is incorrect. Legal values for this attribute are SYNC or ASYNC."
        severity Failure;
     end if;

     wait;

  end process prcs_init;
--####################################################################
--#####      Input Register A with two levels of registers         ###
--####################################################################

  prcs_qa_2lvl:process(CLK_dly, GSR_dly, RSTA_dly)
  begin
      if(GSR_dly = '1') then
          qa_o_reg1 <= ( others => '0');
          qa_o_reg2 <= ( others => '0');
      elsif (GSR_dly = '0') then
         case rst_async_flag is
            when '1' => 
            -----------// async reset
               if(RSTA_dly = '1') then
                  qa_o_reg1 <= ( others => '0');
                  qa_o_reg2 <= ( others => '0');
               elsif ((RSTA_dly = '0') and (CEA_dly = '1')) then
                  if(rising_edge(CLK_dly)) then
                     qa_o_reg2 <= qa_o_reg1;
                     qa_o_reg1 <= A_dly;
                  end if;
               end if;
            when '0' => 
            -----------// sync reset
               if(rising_edge(CLK_dly)) then
                  if(RSTA_dly = '1') then
                     qa_o_reg1 <= ( others => '0');
                     qa_o_reg2 <= ( others => '0');
                  elsif ((RSTA_dly = '0') and (CEA_dly = '1')) then
                      qa_o_reg2 <= qa_o_reg1;
                      qa_o_reg1 <= A_dly;
                  end if;
               end if;
            when others => null;
         end case;
      end if;
  end process prcs_qa_2lvl;
------------------------------------------------------------------
  prcs_qa_o_mux:process(A_dly, qa_o_reg1, qa_o_reg2)
  begin
     if((A0REG=0) and (A1REG=0)) then
        qa_o_mux <= A_dly;
     elsif(((A0REG=1) and (A1REG=0)) or ((A0REG=0) and (A1REG=1))) then
        qa_o_mux <= qa_o_reg1;
     elsif((A0REG=1) and (A1REG=1)) then
        qa_o_mux <= qa_o_reg2;
     end if; 
  end process prcs_qa_o_mux;

--####################################################################
--#### Input Register B with two levels of registers and two muxes ###
--####################################################################
 prcs_qb_2lvl:process(CLK_dly, GSR_dly, RSTB_dly)
  begin
      if(GSR_dly = '1') then
          qb_o_reg1 <= ( others => '0');
          qb_o_reg2 <= ( others => '0');
      elsif (GSR_dly = '0') then
         case rst_async_flag is
            when '1' => 
            -----------// async reset
               if(RSTB_dly = '1') then
                  qb_o_reg1 <= ( others => '0');
                  qb_o_reg2 <= ( others => '0');
               elsif ((RSTB_dly = '0') and (CEB_dly = '1')) then
                   if(rising_edge(CLK_dly)) then
                      qb_o_reg2 <= mux_preadd;
                      qb_o_reg1 <= B_dly;
                   end if;
               end if;
            when '0' => 
            -----------// sync reset
               if(rising_edge(CLK_dly)) then
                  if(RSTB_dly = '1') then
                     qb_o_reg1 <= ( others => '0');
                     qb_o_reg2 <= ( others => '0');
                  elsif ((RSTB_dly = '0') and (CEB_dly = '1')) then
                      qb_o_reg2 <= mux_preadd;
                      qb_o_reg1 <= B_dly;
                  end if;
               end if;
            when others => null;
         end case;
      end if;
  end process prcs_qb_2lvl;

------- PRE ADD --------------------------------------------------

  prcs_qb_preadd:process(opmode_o_mux, B_dly, qd_o_mux, qb_o_reg1)
  begin
     if(((B0REG=0) and (B1REG=0)) or ((B0REG=0) and (B1REG=1))) then
        qb_o_mux0 <= B_dly;
        if(opmode_o_mux(6)='0') then
            preadd <= (qd_o_mux + B_dly );
         elsif(opmode_o_mux(6)='1') then
            preadd <= (qd_o_mux - B_dly );
         end if;
     elsif(((B0REG=1) and (B1REG=1)) or ((B0REG=1) and (B1REG=0))) then
        qb_o_mux0 <= qb_o_reg1;
        if(opmode_o_mux(6)='0') then
            preadd <= (qd_o_mux + qb_o_reg1);
         elsif(opmode_o_mux(6)='1') then
            preadd <= (qd_o_mux - qb_o_reg1);
         end if;
     end if; 
  end process prcs_qb_preadd;

------------------------------------------------------------------
  prcs_preadd_sel:process(opmode_o_mux(4), preadd, qb_o_mux0)
  begin
     if(opmode_o_mux(4)='1') then
        mux_preadd <= preadd;
     elsif(opmode_o_mux(4)='0') then
        mux_preadd <= qb_o_mux0;
     end if;
  end process prcs_preadd_sel;
------------------------------------------------------------------
  prcs_qb_o_mux:process(mux_preadd, qb_o_reg2)
  begin
     if(((B0REG=0) and (B1REG=0)) or ((B0REG=1) and (B1REG=0))) then
        qb_o_mux <= mux_preadd;
     elsif(((B0REG=1) and (B1REG=1)) or ((B0REG=0) and (B1REG=1))) then
        qb_o_mux <= qb_o_reg2;
     end if; 
  end process prcs_qb_o_mux;

--####################################################################
--#####    Input Register C with 0, 1, level of registers        #####
--####################################################################

  prcs_qc_1lvl:process(CLK_dly, GSR_dly, RSTC_dly)

  begin
      if(GSR_dly = '1') then
         qc_o_reg <= ( others => '0');
      elsif (GSR_dly = '0') then
         case rst_async_flag is
            when '1' => 
            -----------// async reset
               if(RSTC_dly = '1') then
                  qc_o_reg <= ( others => '0');
               elsif((RSTC_dly = '0') and (CEC_dly = '1'))then
                  if(rising_edge(CLK_dly)) then
                     qc_o_reg <= C_dly;
                  end if;
                end if;
            when '0' => 
            -----------// sync reset
               if(rising_edge(CLK_dly)) then
                  if(RSTC_dly = '1') then
                     qc_o_reg <= ( others => '0');
                  elsif ((RSTC_dly = '0') and (CEC_dly = '1')) then
                      qc_o_reg <= C_dly;
                  end if;
               end if;
            when others => null;
         end case;
      end if;
  end process prcs_qc_1lvl;
------------------------------------------------------------------
  prcs_qc_o_mux:process(C_dly, qc_o_reg)
  begin
     case CREG is
      when 0 => qc_o_mux <= C_dly;
      when 1 => qc_o_mux <= qc_o_reg;
      when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for CREG on instace DSP48A are 0 or 1"
           severity Failure;
      end case;
  end process prcs_qc_o_mux;

--####################################################################
--#####    Input Register D with 0, 1, level of registers        #####
--####################################################################

  prcs_qd_1lvl:process(CLK_dly, GSR_dly, RSTD_dly)

  begin
      if(GSR_dly = '1') then
         qd_o_reg <= ( others => '0');
      elsif (GSR_dly = '0') then
         case rst_async_flag is
            when '1' => 
            -----------// async reset
               if(RSTD_dly = '1') then
                  qd_o_reg <= ( others => '0');
               elsif((RSTD_dly = '0') and (CED_dly = '1'))then
                  if(rising_edge(CLK_dly)) then
                     qd_o_reg <= D_dly;
                  end if;
                end if;
            when '0' => 
            -----------// sync reset
               if(rising_edge(CLK_dly)) then
                  if(RSTD_dly = '1') then
                     qd_o_reg <= ( others => '0');
                  elsif ((RSTD_dly = '0') and (CED_dly = '1')) then
                      qd_o_reg <= D_dly;
                  end if;
               end if;
            when others => null;
         end case;
      end if;
  end process prcs_qd_1lvl;
------------------------------------------------------------------
  prcs_qd_o_mux:process(D_dly, qd_o_reg)
  begin
     case DREG is
      when 0 => qd_o_mux <= D_dly;
      when 1 => qd_o_mux <= qd_o_reg;
      when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for DREG on instace DSP48A are 0 or 1"
           severity Failure;
      end case;
  end process prcs_qd_o_mux;

--####################################################################
--#####                     Multiplier                           #####
--####################################################################
  prcs_mult:process(qa_o_mux, qb_o_mux)
  begin
     mult_o_int <=  qa_o_mux * qb_o_mux;
  end process prcs_mult;
------------------------------------------------------------------
  prcs_mult_reg:process(CLK_dly, GSR_dly, RSTM_dly)
  begin
      if(GSR_dly = '1') then
         mult_o_reg <= ( others => '0');
      elsif (GSR_dly = '0') then
         case rst_async_flag is
            when '1' => 
            -----------// async reset
               if(RSTM_dly = '1') then
                  mult_o_reg <= ( others => '0');
               elsif((RSTM_dly = '0') and (CEM_dly = '1'))then
                  if(rising_edge(CLK_dly)) then
                     mult_o_reg <= mult_o_int;
                  end if;
                end if;
            when '0' => 
            -----------// sync reset
               if(rising_edge(CLK_dly)) then
                  if(RSTM_dly = '1') then
                     mult_o_reg <= ( others => '0');
                  elsif ((RSTM_dly = '0') and (CEM_dly = '1')) then
                      mult_o_reg <= mult_o_int;
                  end if;
               end if;
            when others => null;
         end case;
      end if;
  end process prcs_mult_reg;
------------------------------------------------------------------
  prcs_mult_mux:process(mult_o_reg, mult_o_int)
  begin
     case MREG is
      when 0 => mult_o_mux <= mult_o_int;
      when 1 => mult_o_mux <= mult_o_reg;
      when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for MREG on instance DSP48A are 0 or 1"
           severity Failure;
      end case;
  end process prcs_mult_mux;

--####################################################################
--#####     OpMode Register with 0, 1, level of registers        #####
--####################################################################

  prcs_opmode_reg:process(CLK_dly, GSR_dly, RSTOPMODE_dly)
  begin
      if(GSR_dly = '1') then
         opmode_o_reg <= ( others => '0');
      elsif (GSR_dly = '0') then
         case rst_async_flag is
            when '1' => 
            -----------// async reset
               if(RSTOPMODE_dly = '1') then
                  opmode_o_reg <= ( others => '0');
               elsif((RSTOPMODE_dly = '0') and (CEOPMODE_dly = '1'))then
                  if(rising_edge(CLK_dly)) then
                     opmode_o_reg <= OPMODE_dly;
                  end if;
                end if;
            when '0' => 
            -----------// sync reset
               if(rising_edge(CLK_dly)) then
                  if(RSTOPMODE_dly = '1') then
                     opmode_o_reg <= ( others => '0');
                  elsif ((RSTOPMODE_dly = '0') and (CEOPMODE_dly = '1')) then
                      opmode_o_reg <= OPMODE_dly;
                  end if;
               end if;
            when others => null;
         end case;
      end if;
  end process prcs_opmode_reg;
------------------------------------------------------------------
  prcs_opmode_mux:process(opmode_o_reg, OPMODE_dly)
  begin
     case OPMODEREG is
      when 0 => opmode_o_mux <= OPMODE_dly;
      when 1 => opmode_o_mux <= opmode_o_reg;
      when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for OPMODEREG are 0 or 1"
           severity Failure;
      end case;
  end process prcs_opmode_mux;
--####################################################################
--#####                        MUX_XYZ                           #####
--####################################################################
  prcs_mux_xz:process(opmode_o_mux, qp_o_mux, qa_o_mux, qb_o_mux, mult_o_mux, 
                       qc_o_mux, qd_o_mux, PCIN_dly, output_x_sig)
  begin
    if(output_x_sig = '1') then
      muxx_o_mux(MSB_P downto 0) <= ( others => 'X');
      muxy_o_mux(MSB_P downto 0) <= ( others => 'X');
      muxz_o_mux(MSB_P downto 0) <= ( others => 'X');
    elsif(output_x_sig = '0') then
    --MUX_X -----
       case opmode_o_mux(1 downto 0) is
         when "00" => muxx_o_mux <= ( others => '0');
         when "01" => muxx_o_mux((MAX_A + MAX_B - 1) downto 0) <= mult_o_mux;
                   if(mult_o_mux(MAX_A + MAX_B - 1) = '1') then
                     muxx_o_mux(MSB_P downto (MAX_A + MAX_B)) <=  ( others => '1');
                   elsif (mult_o_mux(MSB_A + MSB_B + 1) = '0') then 
                     muxx_o_mux(MSB_P downto (MAX_A + MAX_B)) <=  ( others => '0');
                   end if;

         when "10" => muxx_o_mux <= qp_o_mux;
         when "11" => muxx_o_mux(MSB_P downto 0) <=  (qd_o_mux((MSB_P - (MAX_A + MAX_B)) downto 0) & qa_o_mux & qb_o_mux);
      when others => null;
       end case;

    --MUX_Z -----
       case opmode_o_mux(3 downto 2) is
         when "00" => muxz_o_mux <= ( others => '0');
         when "01" => muxz_o_mux <= PCIN_dly;
         when "10" => muxz_o_mux <= qp_o_mux;
         when "11" => muxz_o_mux <= qc_o_mux;
         when others => null;
       end case;
    end if;
  end process prcs_mux_xz;

--####################################################################
--#####        CarryIn   1 level of register                     #####
--####################################################################

  prcs_carryinsel_mux:process(opmode_o_mux(5), CARRYIN_dly)
  begin
     if((CARRYINSEL = "CARRYIN") or (CARRYINSEL = "carryin")) then
        carryinsel_o_mux <= CARRYIN_dly;
     elsif((CARRYINSEL = "OPMODE5") or (CARRYINSEL = "opmode5")) then
        carryinsel_o_mux <= opmode_o_mux(5);
     else
        assert false
            report "Attribute Syntax Error: The allowed values for CARRYINSEL on instance DSP48A are CARRYIN or OPMODES."
            severity Failure;
     end if;
  end process prcs_carryinsel_mux;
------------------------------------------
  prcs_carryin_reg:process(CLK_dly, GSR_dly, RSTCARRYIN_dly)
  begin
      if(GSR_dly = '1') then
         qcarryin_o_reg1 <= '0';
      elsif (GSR_dly = '0') then
         case rst_async_flag is
            when '1' => 
            -----------// async reset
               if(RSTCARRYIN_dly = '1') then
                  qcarryin_o_reg1 <= '0';
               elsif((RSTCARRYIN_dly = '0') and (CECARRYIN_dly = '1'))then
                  if(rising_edge(CLK_dly)) then
                     qcarryin_o_reg1 <= carryinsel_o_mux;
                  end if;
                end if;
            when '0' => 
            -----------// sync reset
               if(rising_edge(CLK_dly)) then
                  if(RSTCARRYIN_dly = '1') then
                     qcarryin_o_reg1 <= '0';
                  elsif ((RSTCARRYIN_dly = '0') and (CECARRYIN_dly = '1')) then
                      qcarryin_o_reg1 <= carryinsel_o_mux;
                  end if;
               end if;
            when others => null;
         end case;
      end if;
  end process prcs_carryin_reg;
------------------------------------------------------------------
  prcs_carryin_mux:process(qcarryin_o_reg1, carryinsel_o_mux)
  begin
     case CARRYINREG is
       when 0 => carryin_o_mux <= carryinsel_o_mux;
       when 1 => carryin_o_mux <= qcarryin_o_reg1;
       when others =>
            assert false
            report "Attribute Syntax Error: The allowed values for CARRYINREG on instance DSP48A are 0 or 1"
            severity Failure;
     end case;
  end process prcs_carryin_mux;
------------------------------------------------------------------
--####################################################################
--#####         Output register P with 1 level of register       #####
--####################################################################

  prcs_qp_reg:process(CLK_dly, GSR_dly, RSTP_dly)
  begin
      if(GSR_dly = '1') then
         qp_o_reg <= ( others => '0');
      elsif (GSR_dly = '0') then
         case rst_async_flag is
            when '1' => 
            -----------// async reset
               if(RSTP_dly = '1') then
                  qp_o_reg <= ( others => '0');
               elsif((RSTP_dly = '0') and (CEP_dly = '1'))then
                  if(rising_edge(CLK_dly)) then
                     qp_o_reg <= accum_o;
                  end if;
                end if;
            when '0' => 
            -----------// sync reset
               if(rising_edge(CLK_dly)) then
                  if(RSTP_dly = '1') then
                     qp_o_reg <= ( others => '0');
                  elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then
                      qp_o_reg <= accum_o;
                  end if;
               end if;
            when others => null;
         end case;
      end if;
  end process prcs_qp_reg;
------------------------------------------------------------------
  prcs_qp_mux:process(accum_o, qp_o_reg)
  begin
     case PREG is
       when 0 => qp_o_mux <= accum_o;
       when 1 => qp_o_mux <= qp_o_reg;
       when others =>
           assert false
           report "Attribute Syntax Error: The allowed values for PREG on instace X_MDPS1 are 0 or 1"
           severity Failure;
     end case;
   
  end process prcs_qp_mux;
--####################################################################
--#####                   ZERO_DELAY_OUTPUTS                     #####
--####################################################################
  prcs_zero_delay_outputs:process(qb_o_mux, qp_o_mux)
  begin
    BCOUT_zd <= qb_o_mux;
    P_zd     <= qp_o_mux;
    PCOUT_zd <= qp_o_mux;
  end process prcs_zero_delay_outputs;

--####################################################################
--#####                OPMODE DRC                                #####
--####################################################################

  prcs_opmode_drc:process(opmode_o_mux, carryinsel_attr,
                       muxx_o_mux, muxz_o_mux, carryin_o_mux)
  variable Message : line;
  variable invalid_opmode_flg : boolean := true;
  variable opmode_valid_var : boolean := true;
  variable opmode_carryinsel_var : std_logic_vector(8 downto 0) := (others => '0');
  variable accum_o_tmp : std_logic_vector(MAX_ACCUM downto 0) := (others => '0');
  begin
      opmode_carryinsel_var := opmode_o_mux & carryinsel_attr;
      case opmode_carryinsel_var is
               when "000000000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000100000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001000000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001100000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010000000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010100000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011000000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011100000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100000000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100100000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101000000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101100000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110000000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110100000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111000000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111100000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000000001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000100001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001000001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001100001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010000001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010100001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011000001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011100001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100000001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100100001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101000001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101100001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110000001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110100001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111000001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111100001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000000100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000000101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000100100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000100101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001000100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001000101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001100100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001100101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010000100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010000101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010100100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010100101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011000100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011000101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011100100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011100101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100000100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100000101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100100100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100100101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101000100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101000101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101100100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101100101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110000100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110000101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110100100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110100101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111000100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111000101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111100100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111100101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000000110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000000111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001000110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001000111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010000110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010000111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011000110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011000111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100000110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100000111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101000110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101000111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110000110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110000111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111000110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111000111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000100110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000100111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001100110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001100111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010100110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010100111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011100110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011100111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100100110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100100111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101100110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101100111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110100110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110100111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111100110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111100111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000000010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000000011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001000010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001000011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010000010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010000011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011000010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011000011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100000010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100000011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101000010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101000011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110000010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110000011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111000010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111000011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000100010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000100011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001100010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001100011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100100010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100100011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101100010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101100011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010100010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010100011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011100010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011100011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110100010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110100011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111100010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111100011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000001000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000001001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000101000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000101001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001001000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001001001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001101000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001101001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010001000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010001001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010101000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010101001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011001000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011001001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011101000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011101001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100001000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100001001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100101000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100101001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101001000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101001001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101101000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101101001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110001000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110001001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110101000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110101001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111001000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111001001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111101000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111101001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000001100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000001101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000101100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000101101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001001100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001001101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001101100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001101101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010001100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010001101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010101100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010101101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011001100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011001101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011101100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011101101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100001100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100001101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100101100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100101101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101001100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101001101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101101100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101101101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110001100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110001101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110101100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110101101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111001100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111001101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111101100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111101101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000001110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000001111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001001110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001001111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010001110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010001111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011001110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011001111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100001110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100001111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101001110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101001111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110001110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110001111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111001110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111001111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000101110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000101111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001101110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001101111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010101110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010101111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011101110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011101111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100101110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100101111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101101110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101101111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110101110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110101111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111101110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111101111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000001010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000001011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001001010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001001011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010001010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010001011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011001010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011001011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100001010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100001011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101001010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101001011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110001010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110001011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111001010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111001011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000101010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000101011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001101010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001101011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100101010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100101011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101101010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101101011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010101010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010101011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011101010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011101011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110101010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110101011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111101010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111101011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000010000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000010001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000110000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000110001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001010000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001010001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001110000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001110001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010010000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010010001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010110000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010110001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011010000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011010001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011110000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011110001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100010000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100010001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100110000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100110001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101010000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101010001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101110000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101110001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110010000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110010001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110110000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110110001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111010000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111010001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111110000" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111110001" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000010100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000010101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000110100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000110101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001010100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001010101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001110100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001110101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010010100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010010101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010110100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010110101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011010100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011010101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011110100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011110101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100010100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100010101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100110100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100110101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101010100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101010101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101110100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101110101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110010100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110010101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110110100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110110101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111010100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111010101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111110100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111110101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000010110" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000010111" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001010110" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001010111" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010010110" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010010111" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011010110" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011010111" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100010110" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100010111" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101010110" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101010111" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110010110" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110010111" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111010110" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111010111" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000110110" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000110111" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001110110" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001110111" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010110110" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010110111" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011110110" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011110111" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100110110" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100110111" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101110110" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101110111" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110110110" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110110111" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111110110" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111110111" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000010010" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000010011" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001010010" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001010011" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010010010" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010010011" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011010010" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011010011" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100010010" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100010011" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101010010" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101010011" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110010010" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110010011" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111010010" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111010011" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000110010" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000110011" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001110010" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001110011" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100110010" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100110011" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101110010" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101110011" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010110010" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010110011" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011110010" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011110011" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110110010" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110110011" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111110010" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111110011" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000011000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000011001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000111000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000111001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001011000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001011001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001111000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001111001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010011000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010011001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010111000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010111001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011011000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011011001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011111000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011111001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100011000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100011001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100111000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100111001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101011000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101011001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101111000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101111001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110011000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110011001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110111000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110111001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111011000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111011001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111111000" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111111001" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000011100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000011101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000111100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000111101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001011100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001011101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001111100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "001111101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010011100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010011101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010111100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "010111101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011011100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011011101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011111100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "011111101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100011100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100011101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100111100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "100111101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101011100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101011101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101111100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "101111101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110011100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110011101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110111100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "110111101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111011100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111011101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111111100" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "111111101" => 
                          if (PREG /= 1) then
                             accum_o <= (others => 'X');
                             opmode_valid_var := false;
                             if(invalid_opmode_flg) then
                                invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL);
                             end if;
                             invalid_opmode_flg := false;
                          else
                             invalid_opmode_flg := true;
                             opmode_valid_var := true;
                             output_x_sig <= '0';
                          end if;
               when "000011110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000011111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001011110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001011111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010011110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010011111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011011110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011011111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100011110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100011111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101011110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101011111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110011110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110011111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111011110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111011111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000011010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000011011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001011010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001011011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010011010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010011011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011011010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011011011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100011010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100011011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101011010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101011011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110011010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110011011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111011010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111011011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000111010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000111011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001111010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001111011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100111010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100111011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101111010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101111011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010111010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010111011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011111010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011111011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110111010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110111011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111111010" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111111011" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000111110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "000111111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001111110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "001111111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010111110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "010111111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011111110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "011111111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100111110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "100111111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101111110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "101111111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110111110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "110111111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111111110" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
               when "111111111" => 
                          invalid_opmode_flg := true ;
                          opmode_valid_var := true ;
                          output_x_sig <= '0';
                when others    =>
                          if(invalid_opmode_flg = true) then
                             invalid_opmode_flg := false;
                             opmode_valid_var := false;
                             output_x_sig <= '1';
                             accum_o <= (others => 'X');
                             Write ( Message, string'("OPMODE Input Warning : The OPMODE "));
                             Write ( Message,  slv_to_str(opmode_o_mux));
                             Write ( Message, string'(" with CARRYINSEL  "));
                             Write ( Message,  CARRYINSEL);
                             Write ( Message, string'(" to DSP48A instance"));
                             Write ( Message, string'(" is invalid for that specific OPMODE."));
                             assert false report Message.all severity Warning;
                             DEALLOCATE (Message);
                           end if;
      end case;

      opmode_valid_flg <= opmode_valid_var;

      if(opmode_valid_var) then 
         if(opmode_o_mux(7) = '0') then
            accum_o_tmp :=  ('0'& muxz_o_mux) + ('0'& muxx_o_mux) + carryin_o_mux;
         elsif(opmode_o_mux(7) = '1') then
            accum_o_tmp :=  ('0'& muxz_o_mux) - ('0'& muxx_o_mux) - carryin_o_mux;
         end if;

         accum_o <= accum_o_tmp(MSB_ACCUM downto 0);
         CARRYOUT_zd <= accum_o_tmp(MAX_ACCUM);
      end if;
  end process prcs_opmode_drc;

--####################################################################
--#####                         OUTPUT                           #####
--####################################################################
  prcs_output:process(BCOUT_zd, CARRYOUT_zd, PCOUT_zd, P_zd)
  begin
      BCOUT     <= BCOUT_zd after SYNC_PATH_DELAY;
      CARRYOUT  <= CARRYOUT_zd after SYNC_PATH_DELAY;
      P         <= P_zd     after SYNC_PATH_DELAY;
      PCOUT     <= PCOUT_zd after SYNC_PATH_DELAY;
  end process prcs_output;



end DSP48A_V;

-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor : Xilinx
-- \   \   \/     Version : 10.1i
--  \   \         Description : Xilinx Functional Simulation Library Component
--  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
-- /___/   /\     Filename : RAMB16BWER.vhd
-- \   \  /  \    Timestamp : Thu Jan 26 16:47:05 PST 2006
--  \___\/\___\
--
-- Revision:
--    01/26/06 - Initial version.
--    08/23/06 - fixed CR 422403.
--    10/16/06 - fixed CR 426962
--    10/19/06 - fixed CR 427370
--    10/26/06 - fixed CR 427914
--    12/07/06 - fixed CR 430517
-- End Revision

----- CELL RAMB16BWER -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library STD;
use STD.TEXTIO.all;



library unisim;
use unisim.vpkg.all;

entity RAMB16BWER is

  generic (

    DATA_WIDTH_A : integer := 0;
    DATA_WIDTH_B : integer := 0;

    DOA_REG : integer := 0 ;
    DOB_REG : integer := 0 ;

    INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    INIT_A : bit_vector := X"000000000";
    INIT_B : bit_vector := X"000000000";

    INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
    INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

    RSTTYPE  : string     := "SYNC"; 

    SIM_COLLISION_CHECK : string := "ALL";

    SRVAL_A  : bit_vector := X"000000000";
    SRVAL_B  : bit_vector := X"000000000";

    WRITE_MODE_A : string := "WRITE_FIRST";
    WRITE_MODE_B : string := "WRITE_FIRST"
    );

  port(
    DOA          : out std_logic_vector (31 downto 0);
    DOB          : out std_logic_vector (31 downto 0);
    DOPA         : out std_logic_vector (3 downto 0);
    DOPB         : out std_logic_vector (3 downto 0);

    ADDRA        : in  std_logic_vector (13 downto 0);
    ADDRB        : in  std_logic_vector (13 downto 0);
    CLKA         : in  std_ulogic;
    CLKB         : in  std_ulogic;
    DIA          : in  std_logic_vector (31 downto 0);
    DIB          : in  std_logic_vector (31 downto 0);
    DIPA         : in  std_logic_vector (3 downto 0);
    DIPB         : in  std_logic_vector (3 downto 0);
    ENA          : in  std_ulogic;
    ENB          : in  std_ulogic;
    RSTA         : in  std_ulogic;
    RSTB         : in  std_ulogic;
    REGCEA       : in  std_ulogic;
    REGCEB       : in  std_ulogic;
    WEA          : in  std_logic_vector (3 downto 0);
    WEB          : in  std_logic_vector (3 downto 0)
    );

end RAMB16BWER;

architecture RAMB16BWER_V of RAMB16BWER is


-- Constants

  constant MAX_ADDR: integer := 13;

  constant MAX_DI:   integer := 31;
  constant MAX_DIP:  integer := 3;
  constant MAX_WE:   integer := 3;

  constant SYNC_PATH_DELAY : time  := 100 ps;

  TYPE CollisionFlagType IS RECORD
     active_port : integer; 
     read_write  : boolean; 
     write_read  : boolean; 
     write_write : boolean; 
     we          : std_logic_vector(MAX_WE downto 0);
  END RECORD;

  TYPE DataWidthType IS RECORD
     diaw  : integer; 
     dipaw : integer; 
     doaw  : integer; 
     dopaw : integer; 
     dibw  : integer; 
     dipbw : integer; 
     dobw  : integer; 
     dopbw : integer; 
  END RECORD;

  TYPE ClsnXbufType IS RECORD
     DO1_clsn   : std_logic_vector(31 downto 0);
     DOP1_clsn  : std_logic_vector(3 downto 0);
     MEM1_clsn  : std_logic_vector(31 downto 0);
     MEMP1_clsn : std_logic_vector(3 downto 0);

     DO2_clsn   : std_logic_vector(31 downto 0);
     DOP2_clsn  : std_logic_vector(3 downto 0);
     MEM2_clsn  : std_logic_vector(31 downto 0);
     MEMP2_clsn : std_logic_vector(3 downto 0);
  END RECORD;

  TYPE memory_collision_type is (Read_A_Write_B,
                                 Write_A_Read_B,
                                 Write_A_Write_B,
                                 Read_B_Write_A,
                                 Write_B_Read_A,
                                 Write_B_Write_A);

  constant SETUP_ALL       : time  := 1000 ps;
  constant SETUP_READ_FIRST : time := 3000 ps;

-- Procedures and Functions

------------------------------------------------
-- procedure ClkCollisionCheck
------------------------------------------------
--
--  Checks whether the time duration of rising
--  clka and clkb violates required setup time
--  between these clocks.
--
   procedure ClkCollisionCheck(
             variable violation        : out integer;
             constant CheckEnabled     : in boolean := false;
             variable CLK1_time        : in time := 0 ns;
             variable CLK2_time        : in time := 0 ns;
             constant SETUP_ALL        : in time := 0 ns;
             constant SETUP_READ_FIRST : in time := 0 ns
   ) is

   begin

     violation := 0;
     if(CheckEnabled) then
        if((CLK1_time > 0 ns ) and (CLK2_time > 0 ns )) then
           if((CLK1_time - CLK2_time) = 0 ns ) then
              violation := 3;
           elsif ((CLK1_time - CLK2_time) < SETUP_ALL) then
              violation := 11;
           elsif ((CLK1_time - CLK2_time) < SETUP_READ_FIRST) then
              violation := 12;
           end if;
        end if;
     end if;
   end ClkCollisionCheck;

------------------------------------------------
-- function AddrOverlapCheck
------------------------------------------------
--

   function AddrOverlapCheck(
                   d1w         : in integer := 0;
                   d2w         : in integer := 0;
                   addr1       : in  std_logic_vector(MAX_ADDR downto 0)   := (others => 'X');
                   addr2       : in  std_logic_vector(MAX_ADDR downto 0)   := (others => 'X');
                   zero_addr1  : in  std_logic_vector(MAX_ADDR downto 0)   := (others => 'X');
                   zero_addr2  : in  std_logic_vector(MAX_ADDR downto 0)   := (others => 'X');
                   we_segment  : in integer := 0
   ) return boolean is 
   variable collision, port1_overlap, port2_overlap : boolean := false;
   variable addr1_zero_int, addr2_zero_int, wea_index, INDEX1, INDEX2 : integer := -1;
   variable tmp_addr1_zero, tmp_addr2_zero : std_logic_vector(MAX_ADDR downto 0) := (others => 'X');
   variable zero_out                       : std_logic_vector(MAX_ADDR downto 0)   := (others => 'X');
   variable tmp_we                         : std_logic_vector(1 downto 0)          := (others => '0');


   
   
   begin
     INDEX1 := SLV_TO_INT(addr1(4 downto 0));
     INDEX2 := SLV_TO_INT(addr2(4 downto 0));

     if(D1W >= D2W) then  
        zero_out := zero_addr1;
     elsif(D1W < D2W) then
        zero_out := zero_addr2;
     end if;

     tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_out);
     tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_out);

     addr1_zero_int := SLV_TO_INT(tmp_addr1_zero); 
     addr2_zero_int := SLV_TO_INT(tmp_addr2_zero); 
   
--     if((addr1_zero_int = addr2_zero_int) and ((INDEX1 + D1W) > we_segment * 8 ) and ((INDEX2 + D2W) > we_segment * 8 )) then
     if(addr1_zero_int = addr2_zero_int) then

        case D1W is
           ---------
           when 1|2|4|8 =>
           ---------
              tmp_we(1 downto 0) := addr1( 4 downto 3);
              wea_index := SLV_TO_INT(tmp_we);
              if(wea_index = we_segment) then
                port1_overlap := true;
              end if;

           ---------
           when 16 =>
           ---------

              tmp_we(1) := addr1(4);
              tmp_we(0) := '0';
              wea_index := SLV_TO_INT(tmp_we);
              if(wea_index = we_segment) then
                port1_overlap := true;
              end if;
   
              tmp_we(1) := addr1(4);
              tmp_we(0) := '1';
              wea_index := SLV_TO_INT(tmp_we);
              if(wea_index = we_segment) then
                port1_overlap := true;
              end if;
            
           ---------
           when 32 =>
           ---------

                port1_overlap := true;

           ---------
           when others => null;
           ---------
        end case;



        case D2W is
           ---------
           when 1|2|4|8 =>
           ---------
              tmp_we(1 downto 0) := addr2( 4 downto 3);
              wea_index := SLV_TO_INT(tmp_we);
              if(wea_index = we_segment) then
                port2_overlap := true;
              end if;

           ---------
           when 16 =>
           ---------

              tmp_we(1) := addr2(4);
              tmp_we(0) := '0';
              wea_index := SLV_TO_INT(tmp_we);
              if(wea_index = we_segment) then
                port2_overlap := true;
              end if;
   
              tmp_we(1) := addr2(4);
              tmp_we(0) := '1';
              wea_index := SLV_TO_INT(tmp_we);
              if(wea_index = we_segment) then
                port2_overlap := true;
              end if;
            
           ---------
           when 32 =>
           ---------

                port2_overlap := true;

           ---------
           when others => null;
           ---------
        end case;

     end if;

     collision :=  (port1_overlap and port2_overlap);
     return collision;
   end;
------------------------------------------------
-- procedure QkAddrOverlapChk
------------------------------------------------
--

   procedure QkAddrOverlapChk(
                   variable addr_overlap : out boolean;
                   variable data_widths  : in DataWidthType;
                   variable addra        : in  std_logic_vector(MAX_ADDR downto 0) := (others => 'X');
                   variable addrb        : in  std_logic_vector(MAX_ADDR downto 0) := (others => 'X')
   ) is
   variable addra_int, addrb_int, max_width : integer := -1;
   variable tmp_addra_zero, tmp_addrb_zero  : std_logic_vector(MAX_ADDR downto 0) := (others => 'X');
   variable zero_data_out                   : std_logic_vector(MAX_ADDR downto 0) := (others => 'X');
   variable zero_parity_out                 : std_logic_vector((MAX_ADDR-3) downto 0) := (others => 'X');
 
   begin
     addr_overlap := false;
     zero_data_out   := (others => '1');
     zero_parity_out := (others => '1');

     max_width := data_widths.diaw;

     if(data_widths.doaw > max_width) then
        max_width := data_widths.doaw;
     end if;
   
     if(data_widths.dibw > max_width) then
        max_width := data_widths.dibw;
     end if;

     if(data_widths.dobw > max_width) then
        max_width := data_widths.dobw;
     end if;

    
     case max_width is

        -------
        when 32 =>
        -------
            zero_data_out(4 downto 0) := (others => '0'); 
            zero_parity_out(1 downto 0) := (others => '0'); 

        -------
        when 16 =>
        -------
            zero_data_out(3 downto 0) := (others => '0'); 
            zero_parity_out(0 downto 0) := (others => '0'); 

        -------
        when 8 =>
        -------
            zero_data_out(2 downto 0) := (others => '0'); 

        -------
        when 4 =>
        -------
            zero_data_out(1 downto 0) := (others => '0'); 

        -------
        when 2 =>
        -------
            zero_data_out(0 downto 0) := (others => '0'); 

        -------
        when others =>
        -------
           null;


     end case;

     tmp_addra_zero := (addra(MAX_ADDR downto 0) and zero_data_out);
     tmp_addrb_zero := (addrb(MAX_ADDR downto 0) and zero_data_out);

     addra_int := SLV_TO_INT(tmp_addra_zero); 
     addrb_int := SLV_TO_INT(tmp_addrb_zero); 
   
     if(addra_int = addrb_int) then
          addr_overlap := true;
     end if;

   end QkAddrOverlapChk;

------------------------------------------------
-- procedure SameDataChk 
------------------------------------------------
--
--  Checks whether the data written is the same
--  as in the memory, or in the case of both ports
--  writing whether the inputs are the same.
--  If true, then there is no collision
--
   procedure SameDataChk(
             variable same_data  : out boolean;
             variable same_datap : out boolean;
             constant MEM        : in std_logic_vector(18431 downto 0); 
             constant di1        : in std_logic_vector(31 downto 0);
             constant di2        : in std_logic_vector(31 downto 0);
             constant dip1       : in std_logic_vector(3 downto 0);
             constant dip2       : in std_logic_vector(3 downto 0);
             variable addr1      : in std_logic_vector(13 downto 0) := (others => 'X');
             variable addr2      : in std_logic_vector(13 downto 0) := (others => 'X');
             variable addrp1     : in std_logic_vector(10 downto 0) := (others => 'X');
             variable addrp2     : in std_logic_vector(10 downto 0) := (others => 'X');
             variable wr_mode_1  : in std_logic_vector(1 downto 0) := "00";
             variable wr_mode_2  : in std_logic_vector(1 downto 0) := "00";
             constant we_segment : in integer := -1;
             variable we1        : in std_ulogic := 'X';
             variable we2        : in std_ulogic := 'X';
             variable D1W       : in integer := -1;
             variable D1PW      : in integer := -1;
             variable D2W       : in integer := -1;
             variable D2PW      : in integer := -1
   ) is
   variable REM1 : integer := -1;
   variable REM2 : integer := -1;
   variable XOUT_BITS : integer := -1;
   variable XOUT_BITS_1 : integer := -1;
   variable XOUT_PBITS_1 : integer := 0;
   variable INDEX, INDEXP, DATA_INDEX : integer := -1;
   variable ADDRESS, ADDRESS_P, ADDRESS32_1, ADDRESS32P_1, ADDRESS32_2, ADDRESS32P_2 : integer := -1;
   variable SMALL_ADDRESS32, SMALL_ADDRESS32P : integer := -1;
   variable SMALL_DW : integer := -1;

  
   variable TableRow : std_logic_vector(1 downto 0) := (others => '0');

   variable cmp_d1_buf   : std_logic_vector(7 downto 0) := (others => '0');
   variable cmp_d1p_buf  : std_logic_vector(0 downto 0) := (others => '0');
   variable cmp_d2_buf   : std_logic_vector(7 downto 0) := (others => '0');
   variable cmp_d2p_buf  : std_logic_vector(0 downto 0) := (others => '0');
   variable cmp_mem_buf  : std_logic_vector(7 downto 0) := (others => '0');
   variable cmp_memp_buf : std_logic_vector(0 downto 0) := (others => '0');

   variable cmp_d1_buf32 : std_logic_vector(31 downto 0) := (others => '0');
   variable cmp_d1p_buf4 : std_logic_vector(3 downto 0)  := (others => '0');
   variable cmp_d2_buf32 : std_logic_vector(31 downto 0) := (others => '0');
   variable cmp_d2p_buf4 : std_logic_vector(3 downto 0)  := (others => '0');

   variable tmp_cmp_d1_buf  : std_logic_vector(7 downto 0) := (others => '0');
   variable tmp_cmp_d1p_buf : std_logic_vector(0 downto 0) := (others => '0');
   variable tmp_cmp_d2_buf  : std_logic_vector(7 downto 0) := (others => '0');
   variable tmp_cmp_d2p_buf : std_logic_vector(0 downto 0) := (others => '0');

   variable memp_fp      :  std_logic_vector(3 downto 0)  := (others => '0');

   begin

-- ##################################################################
-----------------------------------------------------------------------
------------ Port 1  Active Clock -------------------------------------
-----------------------------------------------------------------------

      same_data  := false;
      same_datap := false;

      if((D1W >= D2W) and (D2W < 8)) then
         INDEX := SLV_TO_INT(addr2(4 downto 0));
      elsif((D2W >= D1W) and (D1W < 8)) then
         INDEX := SLV_TO_INT(addr1(4 downto 0));
      else
         INDEX := we_segment * 8;
      end if;


      ---  Data Bits ---

      REM1 := D1W REM 8;
      REM2 := D2W REM 8;

      -- find the minimum data bits to overlap
      if((REM1 = 0) and (REM2 = 0)) then
          XOUT_BITS := 8 ;
      elsif(REM1 = 0) then
          XOUT_BITS := REM2;
      elsif(REM2 = 0) then
          XOUT_BITS := REM1;
      elsif(REM1 > REM2) then
          XOUT_BITS := REM2 ;
      elsif (REM1 <= REM2) then
          XOUT_BITS := REM1 ;
      end if;

      XOUT_BITS_1 := XOUT_BITS - 1 ;


      if(D1W <= D2W) then
         SMALL_DW := D1W;
         ADDRESS  := SLV_TO_INT(addr1);
         SMALL_ADDRESS32:= SLV_TO_INT(addr1(4 downto 0));
      elsif(D1W > D2W) then
         SMALL_DW := D2W;
         ADDRESS  := SLV_TO_INT(addr2);
         SMALL_ADDRESS32:= SLV_TO_INT(addr2(4 downto 0));
      end if;

      if(D1PW <= D2PW) then
         ADDRESS_P := SLV_TO_INT(addrp1);
         SMALL_ADDRESS32P:= SLV_TO_INT(addrp1(1 downto 0));
      elsif(D1PW > D2PW) then
         ADDRESS_P := SLV_TO_INT(addrp2);
         SMALL_ADDRESS32P:= SLV_TO_INT(addrp2(1 downto 0));
      end if;
  
      INDEXP  := we_segment;
 
      TableRow := (we1 & we2);

      cmp_d1_buf   := (others => '0'); 
      cmp_d1p_buf  := (others => '0'); 
      cmp_d2_buf   := (others => '0'); 
      cmp_d2p_buf  := (others => '0'); 
      cmp_mem_buf  := (others => '0'); 
      cmp_memp_buf := (others => '0'); 

--==================================================================================================
      ADDRESS32_1  := SLV_TO_INT(addr1(4 downto 0));
      ADDRESS32P_1 := SLV_TO_INT(addrp1(1 downto 0));
      cmp_d1_buf32(((D1W - 1) + ADDRESS32_1) downto ADDRESS32_1)   :=  di1((D1W - 1) downto 0);
      cmp_d1p_buf4(((D1PW - 1) + ADDRESS32P_1) downto ADDRESS32P_1) :=  dip1((D1PW - 1) downto 0);

      ADDRESS32_2  := SLV_TO_INT(addr2(4 downto 0));
      ADDRESS32P_2 := SLV_TO_INT(addrp2(1 downto 0));
      cmp_d2_buf32(((D2W - 1) + ADDRESS32_2) downto ADDRESS32_2)    :=  di2((D2W - 1) downto 0);
      cmp_d2p_buf4(((D2PW - 1) + ADDRESS32P_2) downto ADDRESS32P_2) :=  dip2((D2PW - 1 ) downto 0);

      case SMALL_DW is
         when 1|2|4 =>
            cmp_mem_buf(XOUT_BITS_1 downto 0)      := MEM((XOUT_BITS_1 + ADDRESS ) downto (ADDRESS)); 
               
            tmp_cmp_d1_buf(XOUT_BITS_1 downto 0)   :=  cmp_d1_buf32((XOUT_BITS_1 + SMALL_ADDRESS32 ) downto SMALL_ADDRESS32);
            tmp_cmp_d2_buf(XOUT_BITS_1 downto 0)   :=  cmp_d2_buf32((XOUT_BITS_1 + SMALL_ADDRESS32 ) downto SMALL_ADDRESS32);

         when 8 =>
            cmp_mem_buf(XOUT_BITS_1 downto 0)      := MEM((XOUT_BITS_1 + ADDRESS ) downto (ADDRESS)); 
            cmp_memp_buf(XOUT_PBITS_1 downto 0)    := MEM((XOUT_PBITS_1 + 16384 + ADDRESS_P) downto (ADDRESS_P + 16384)); 

            tmp_cmp_d1_buf(XOUT_BITS_1 downto 0)   := cmp_d1_buf32((XOUT_BITS_1 + SMALL_ADDRESS32 ) downto SMALL_ADDRESS32);
            tmp_cmp_d1p_buf(XOUT_PBITS_1 downto 0) := cmp_d1p_buf4((XOUT_PBITS_1 + SMALL_ADDRESS32P) downto SMALL_ADDRESS32P);  

            tmp_cmp_d2_buf(XOUT_BITS_1 downto 0)   := cmp_d2_buf32((XOUT_BITS_1 + SMALL_ADDRESS32 ) downto SMALL_ADDRESS32);
            tmp_cmp_d2p_buf(XOUT_PBITS_1 downto 0) := cmp_d2p_buf4((XOUT_PBITS_1 + SMALL_ADDRESS32P) downto SMALL_ADDRESS32P);  

         when 16 =>
            if((we_segment = 0) or (we_segment = 2)) then
                DATA_INDEX := 0;
            elsif((we_segment = 1) or (we_segment = 3))then
                DATA_INDEX := 1;
            end if;

            cmp_mem_buf(XOUT_BITS_1 downto 0)   := MEM((XOUT_BITS_1 + ADDRESS + DATA_INDEX*8 ) downto (DATA_INDEX*8 + ADDRESS)); 
            cmp_memp_buf(XOUT_PBITS_1 downto 0) := MEM((XOUT_PBITS_1 + 16384 + DATA_INDEX + ADDRESS_P) downto (DATA_INDEX + ADDRESS_P + 16384)); 
            tmp_cmp_d1_buf(XOUT_BITS_1 downto 0)   := cmp_d1_buf32((XOUT_BITS_1 + we_segment*8 ) downto we_segment*8);
            tmp_cmp_d1p_buf(XOUT_PBITS_1 downto 0) := cmp_d1p_buf4((XOUT_PBITS_1 + we_segment*1) downto we_segment*1);  

            tmp_cmp_d2_buf(XOUT_BITS_1 downto 0)   := cmp_d2_buf32((XOUT_BITS_1 + we_segment*8 ) downto we_segment*8);
            tmp_cmp_d2p_buf(XOUT_PBITS_1 downto 0) := cmp_d2p_buf4((XOUT_PBITS_1 + we_segment*1) downto we_segment*1);  

         when 32 =>
            cmp_mem_buf(XOUT_BITS_1 downto 0)   := MEM((XOUT_BITS_1 + INDEX + ADDRESS ) downto (INDEX + ADDRESS)); 
            cmp_memp_buf(XOUT_PBITS_1 downto 0) := MEM((XOUT_PBITS_1 + 16384 + INDEXP + ADDRESS_P) downto (INDEXP + ADDRESS_P + 16384)); 

            tmp_cmp_d1_buf(XOUT_BITS_1 downto 0)   := cmp_d1_buf32((XOUT_BITS_1 + we_segment*8 ) downto we_segment*8);
            tmp_cmp_d1p_buf(XOUT_PBITS_1 downto 0) := cmp_d1p_buf4((XOUT_PBITS_1 + we_segment*1) downto we_segment*1);  

            tmp_cmp_d2_buf(XOUT_BITS_1 downto 0)   := cmp_d2_buf32((XOUT_BITS_1 + we_segment*8 ) downto we_segment*8);
            tmp_cmp_d2p_buf(XOUT_PBITS_1 downto 0) := cmp_d2p_buf4((XOUT_PBITS_1 + we_segment*1) downto we_segment*1);  

         when  others => null; 

      end case;

      case TableRow is
---===============================================================================
---                           wea&web = 11
---===============================================================================
          ----
          when "11" =>
          ----
              
               memp_fp := MEM(( 3 + 16384 + ADDRESS_P) downto (16384 + ADDRESS_P)); 


               if((tmp_cmp_d1_buf = tmp_cmp_d2_buf) and (tmp_cmp_d2_buf = cmp_mem_buf)) then
                   same_data := true;
               end if;

           -- Parity
               if((D1PW /= 0) and (D2PW /= 0)) then
                  if((tmp_cmp_d1p_buf = tmp_cmp_d2p_buf) and (tmp_cmp_d2p_buf = cmp_memp_buf)) then
                      same_datap := true;
                  end if;
               end if;
---===============================================================================
---                           wea&web = 01
---===============================================================================
          ----
          when "01" =>
          ----

               if(tmp_cmp_d2_buf = cmp_mem_buf) then
                   same_data := true;
               end if;

               -- Parity
               if((D1PW /= 0) and (D2PW /= 0)) then
                  if(tmp_cmp_d2p_buf = cmp_memp_buf) then
                      same_datap := true;
                  end if;
               end if;
---===============================================================================
---                           wea&web = 10
---===============================================================================
          ----
          when "10" =>
          ----
               if(tmp_cmp_d1_buf = cmp_mem_buf) then
                   same_data := true;
               end if;

               -- Parity
               if((D1PW /= 0) and (D2PW /= 0)) then
                  if(tmp_cmp_d1p_buf = cmp_memp_buf) then
                      same_datap := true;
                  end if;
               end if;
---===============================================================================
---                           others 
---===============================================================================

          ---------
          when others =>
          ---------
                null;
      end case;

   end SameDataChk;

------------------------------------------------
-- procedure CollisionTableRest
------------------------------------------------
--
--  Checks whether the time duration of rising
--  clka and clkb violates required setup time
--  between these clocks.
--
   procedure CollisionTableRest(
             variable clsn_bufs      : out ClsnXbufType;
             variable same_data_flg  : out boolean;
             variable same_datap_flg : out boolean;
             constant MEM            : in std_logic_vector(18431 downto 0);
             constant di1            : in std_logic_vector(31 downto 0);
             constant di2            : in std_logic_vector(31 downto 0);
             constant dip1           : in std_logic_vector(3 downto 0);
             constant dip2           : in std_logic_vector(3 downto 0);
             variable addr1          : in std_logic_vector(13 downto 0) := (others => 'X');
             variable addr2          : in std_logic_vector(13 downto 0) := (others => 'X');
             variable addrp1         : in std_logic_vector(10 downto 0) := (others => 'X');
             variable addrp2         : in std_logic_vector(10 downto 0) := (others => 'X');
             variable wr_mode_1      : in std_logic_vector(1 downto 0) := "00";
             variable wr_mode_2      : in std_logic_vector(1 downto 0) := "00";
             constant we_segment     : in integer := -1;
             constant violation      : in integer := -1;
             variable we1            : in std_ulogic := 'X';
             variable we2            : in std_ulogic := 'X';
             variable D1W            : in integer := -1;
             variable D1PW           : in integer := -1;
             variable D2W            : in integer := -1;
             variable D2PW           : in integer := -1
   ) is
   variable REM1 : integer := -1;
   variable REM2 : integer := -1;
   variable XOUT_BITS : integer := -1;
   variable XOUT_BITS_1 : integer := -1;
   variable INDEX, INDEX_P : integer := -1;
  
   variable TableRow :  std_logic_vector(5 downto 0) := (others => '0');
   variable we1we2   :  std_logic_vector(1 downto 0) := (others => '0');

   variable same_data                : boolean    := false;
   variable same_datap               : boolean    := false;
   variable SAME_DATA_CHECK_DISABLED : boolean    := true;

   begin

-- ##################################################################
-----------------------------------------------------------------------
------------ Port 1  Active Clock -------------------------------------
-----------------------------------------------------------------------


   if((D1W >= D2W) and (D2W < 8)) then
      INDEX := SLV_TO_INT(addr2(4 downto 0));
   elsif((D2W >= D1W) and (D1W < 8)) then
      INDEX := SLV_TO_INT(addr1(4 downto 0));
   else
      INDEX := we_segment * 8;
   end if;


   ---  Data Bits ---

   REM1 := D1W REM 8;
   REM2 := D2W REM 8;

   -- find the minimum data bits to overlap
   if((REM1 = 0) and (REM2 = 0)) then
       XOUT_BITS := 8 ;
   elsif(REM1 = 0) then
       XOUT_BITS := REM2;
   elsif(REM2 = 0) then
       XOUT_BITS := REM1;
   elsif(REM1 > REM2) then
       XOUT_BITS := REM2 ;
   elsif (REM1 <= REM2) then
       XOUT_BITS := REM1 ;
   end if;

   XOUT_BITS_1 := XOUT_BITS - 1 ;



   ---  Parity Bits ---

   -- find the minimum parity bits to overlap

   if(D1PW >= D2PW) then
      INDEX_P := SLV_TO_INT(addrp2(1 downto 0));
   else
      INDEX_P := SLV_TO_INT(addrp1(1 downto 0));
   end if;
--===============================================================================
--   Same Data Check for both Data and Parity 
--   If Data/Parity_Data are the same in Ports A and B, and the contents of the 
--   Memory/Parity_memory are the same as the Data, then here is no collision
--===============================================================================


   SameDataChk(
      same_data  => same_data,
      same_datap => same_datap,
      mem        => mem,
      di1        => di1,
      di2        => di2,
      dip1       => dip1,
      dip2       => dip2,
      addr1      => addr1,
      addr2      => addr2,
      addrp1     => addrp1,
      addrp2     => addrp2,
      wr_mode_1  => wr_mode_1,
      wr_mode_2  => wr_mode_2,
      we_segment => we_segment,
      we1        => we1,
      we2        => we2,
      D1W        => D1W,
      D1PW       => D1PW,
      D2W        => D2W,
      D2PW       => D2PW
    );

---===============================================================================
---===============================================================================
-- DEBUG                    
if(SAME_DATA_CHECK_DISABLED) then
  same_data  := false;
  same_datap := false;
end if;

  same_data_flg  := same_data;
  same_datap_flg := same_datap;
 
   TableRow := (wr_mode_1 & wr_mode_2 & we1 & we2);
   case TableRow is
---===============================================================================
---                           wea&web = 11
---===============================================================================
          ----
          when "000011" | "010011"  =>
          ----
            if((violation = 3) or (violation = 11)) then
                if(not same_data) then
                   -- port 1
                   clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                   clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                   -- port 2
                   clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                   clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                end if;
                if(not same_datap) then
                   -- parity port 1
                   if((D1PW /= 0) and (D2PW /= 0)) then
--                       clsn_bufs.DOP1_clsn((INDEX_P + (we_segment * 1))  downto (INDEX_P + (we_segment * 1))) := (others => 'X');
                       clsn_bufs.DOP1_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                       clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;
                   -- parity port 2
                   if((D1PW /= 0) and (D2PW /= 0)) then
--                       clsn_bufs.DOP2_clsn((INDEX_P + (we_segment * 1))  downto (INDEX_P + (we_segment * 1))) := (others => 'X');
                       clsn_bufs.DOP2_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                       clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;

            end if;

          ----
          when "001011" | "011011" =>
          ----
            if((violation = 3) or (violation = 11)) then
                if(not same_data) then
                   -- port 1
                   clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                   clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                   -- port 2
                   clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                end if;
                if(not same_datap) then
                   -- parity port 1
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.DOP1_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                       clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;

                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;
            end if;
          ----
          when "000111" | "010111"  =>
          ----
            if((violation = 3) or (violation = 11) or (violation = 12)) then
                if(not same_data) then
                   -- port 1
                   clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                   clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                   -- port 2
                   clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                   clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                end if;
                if(not same_datap) then
                   -- parity port 1
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.DOP1_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                       clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;
                   -- parity port 2
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.DOP2_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                       clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;
            end if;

          ----
          when "100011" =>
          ----
             if((violation = 3) or (violation = 11)) then
                if(not same_data) then
                   -- port 1
                   clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                   -- port 2
                   clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                   clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                end if;

                if(not same_datap) then
                   -- parity port 1
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;
                   -- parity port 2
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.DOP2_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                       clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;

             end if;

          ----
          when "100111" =>
          ----
             if((violation = 3) or (violation = 11) or (violation = 12) ) then
                if(not same_data) then
                   -- port 1
                   clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                   -- port 2
                   clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                   clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                end if;

                if(not same_datap) then
                   -- parity port 1
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;
                   -- parity port 2
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.DOP2_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                       clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;

             end if;
          ----
          when "101011" =>
          ----
             if((violation = 3) or (violation = 11)) then
                if(not same_data) then
                   -- port 1
                   clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                   -- port 2
                   clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X');
                end if;
                if(not same_datap) then
                   if((D1PW /= 0) and (D2PW /= 0)) then
                        -- parity port 1
                       clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                        -- parity port 2
                       clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;
             end if;

---===============================================================================
---                           wea&web = 01
---===============================================================================
          ----
          when "000001" | "010001" | "100001"  =>
          ----
             if((violation = 3) or (violation = 11)) then
                if(not same_data) then
                   -- port 1
                   clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                end if;
                if(not same_datap) then
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.DOP1_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;
             end if;
          ----
          when "000101" | "010101" | "100101"  =>
          ----
             if((violation = 11)  or (violation = 12)) then
                if(not same_data) then
                   -- port 1
                   clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                end if;
                if(not same_datap) then
                   -- parity port 1
                   if((D1PW /= 0) and (D2PW /= 0)) then
                      clsn_bufs.DOP1_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;

             end if;
          ----
          when "001001" | "011001" | "101001"  =>
          ----
             if((violation = 3) or (violation = 11)) then
                if(not same_data) then
                   -- port 1
                   clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                end if;
                if(not same_datap) then
                   -- parity port 1
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.DOP1_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;
             end if;

---===============================================================================
---                           wea&web = 10
---===============================================================================

          ----
          when "000010" | "000110" | "001010"  =>
          ----
             if((violation = 3) or (violation = 11)) then
                if(not same_data) then
                   --  port 1
                   clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                end if;
                if(not same_datap) then
                   -- parity port 1
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.DOP2_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;
             end if;
          ----
          when "100010" | "100110" | "101010"  =>
          ----
             if((violation = 3) or (violation = 11)) then
                if(not same_data) then
                   --  port 1
                   clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X');
                end if;
                if(not same_datap) then
                   -- parity port 1
                   if((D1PW /= 0) and (D2PW /= 0)) then
                       clsn_bufs.DOP2_clsn((we_segment * 1)  downto (we_segment * 1)) := (others => 'X');
                   end if;
                end if;

             end if;

---===============================================================================
---                           others 
---===============================================================================

          ---------
          when others =>
          ---------
                null;
   end case;

   end CollisionTableRest;

------------------------------------------------
-- procedure PreProcessWe1We2
------------------------------------------------
--
--  Checks whether the time duration of rising
--  clka and clkb violates required setup time
--  between these clocks.
--
   procedure PreProcessWe1We2(
             variable clsn_bufs     : out ClsnXbufType;
             variable clsn_Type     : out CollisionFlagType;
             constant memory        : in std_logic_vector(18431 downto 0);
             constant di1           : in std_logic_vector(31 downto 0)   := (others => 'X');
             constant di2           : in std_logic_vector(31 downto 0)   := (others => 'X');
             constant dip1          : in std_logic_vector(3 downto 0)    := (others => 'X');
             constant dip2          : in std_logic_vector(3 downto 0)    := (others => 'X');
             variable addr1         : in std_logic_vector(13 downto 0)   := (others => 'X');
             variable addr2         : in std_logic_vector(13 downto 0)   := (others => 'X');
             variable we1           : in std_logic_vector(3 downto 0)    := (others => 'X');
             variable we2           : in std_logic_vector(3 downto 0)    := (others => 'X');
             variable zero_read_1   : in std_logic_vector(13 downto 0)   := (others => 'X');
             variable zero_readp_1  : in std_logic_vector(10 downto 0)   := (others => 'X');
             variable zero_write_1  : in std_logic_vector(13 downto 0)   := (others => 'X');
             variable zero_writep_1 : in std_logic_vector(10 downto 0)   := (others => 'X');
             variable zero_read_2   : in std_logic_vector(13 downto 0)   := (others => 'X');
             variable zero_readp_2  : in std_logic_vector(10 downto 0)   := (others => 'X');
             variable zero_write_2  : in std_logic_vector(13 downto 0)   := (others => 'X');
             variable zero_writep_2 : in std_logic_vector(10 downto 0)   := (others => 'X');
             variable wr_mode_1     : in std_logic_vector(1 downto 0)    := "00";
             variable wr_mode_2     : in std_logic_vector(1 downto 0)    := "00";
             constant violation     : in integer := -1;
             variable DI1W          : in integer := -1;
             variable DIP1W         : in integer := -1;
             variable DI2W          : in integer := -1;
             variable DIP2W         : in integer := -1;
             variable DO1W          : in integer := -1;
             variable DOP1W         : in integer := -1;
             variable DO2W          : in integer := -1;
             variable DOP2W         : in integer := -1
   ) is

   variable we1we2 : std_logic_vector(1 downto 0) := "XX";
   variable zero_addr1        : std_logic_vector(13 downto 0) := (others => 'X');
   variable zero_addr2        : std_logic_vector(13 downto 0) := (others => 'X');
   variable zero_parity_addr1 : std_logic_vector(10 downto 0) := (others => 'X');
   variable zero_parity_addr2 : std_logic_vector(10 downto 0) := (others => 'X');
   variable tmp_addr1_zero    : std_logic_vector(13 downto 0) := (others => 'X');
   variable tmp_addr2_zero    : std_logic_vector(13 downto 0) := (others => 'X');
   variable tmp_parity_addr1_zero    : std_logic_vector(10 downto 0) := (others => 'X');
   variable tmp_parity_addr2_zero    : std_logic_vector(10 downto 0) := (others => 'X');


   variable tmp_we1                  : std_ulogic := 'X';
   variable tmp_we2                  : std_ulogic := 'X';
   variable j                        : integer    := 0;

   variable same_data_flg            : boolean    := false;
   variable same_datap_flg           : boolean    := false;

   begin
      
      clsn_type.read_write  := false;
      clsn_type.write_read  := false;
      clsn_type.write_write := false;

      for i in  0 to 3 loop
         we1we2 := we1(i)&we2(i);
         clsn_type.we(i)  := '0';
         case we1we2 is
             ---------
             when "00" =>
             ---------
                null;
   
             ---------
             when "01" =>
             ---------
                same_data_flg  := false;
                same_datap_flg := false;

                zero_addr1 := zero_read_1;
                zero_addr2 := zero_write_2;
             
                zero_parity_addr1 := zero_readp_1;
                zero_parity_addr2 := zero_writep_2;

                tmp_we1 := '0';
                tmp_we2 := '1';

                if(AddrOverlapCheck(DO1W, DI2W, addr1, addr2, zero_addr1, zero_addr2,i)) then

                   tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_addr1);
                   tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_addr2);

                   tmp_parity_addr1_zero := addr1(13 downto 3) and zero_parity_addr1;
                   tmp_parity_addr2_zero := addr2(13 downto 3) and zero_parity_addr2;

-- FP fixed false message for DSP group 12/06/04

                      clsn_type.read_write := true;
                      clsn_type.we(i)  := '1';

                      if((wr_mode_2 = "01")) then
                        clsn_type.read_write := false;
                        clsn_type.we(i)  := '0';
                      end if;

	
                      CollisionTableRest(
                        same_data_flg  => same_data_flg,
                        same_datap_flg => same_datap_flg,
                        clsn_bufs      => clsn_bufs,
                        mem            => memory,
                        di1            => di1,
                        di2            => di2,
                        dip1           => dip1,
                        dip2           => dip2,
                        addr1          => tmp_addr1_zero,
                        addr2          => tmp_addr2_zero,
                        addrp1         => tmp_parity_addr1_zero,
                        addrp2         => tmp_parity_addr2_zero,
                        wr_mode_1      => wr_mode_1,
                        wr_mode_2      => wr_mode_2,
                        violation      => violation,
                        we_segment     => i,
                        we1            => tmp_we1,
                        we2            => tmp_we2,
                        D1W            => DO1W,
                        D1PW           => DOP1W,
                        D2W            => DI2W,
                        D2PW           => DIP2W
                      );
                end if;
             ---------
             when "10" =>
             ---------
                same_data_flg  := false;
                same_datap_flg := false;

                zero_addr1 := zero_write_1;
                zero_addr2 := zero_read_2;

                zero_parity_addr1 := zero_writep_1;
                zero_parity_addr2 := zero_readp_2;

                tmp_we1 := '1';
                tmp_we2 := '0';


                if(AddrOverlapCheck(DI1W, DO2W, addr1, addr2, zero_addr1, zero_addr2,i)) then

                   tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_addr1);
                   tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_addr2);

                   tmp_parity_addr1_zero := addr1(13 downto 3) and zero_parity_addr1;
                   tmp_parity_addr2_zero := addr2(13 downto 3) and zero_parity_addr2;

                      clsn_type.write_read := true;
                      clsn_type.we(i)  := '1';

-- FP fixed false message for DSP group 12/06/04
--                      if((violation = 12) or (wr_mode_1 = "01")) then
                      if((wr_mode_1 = "01")) then
                        clsn_type.write_read := false;
                        clsn_type.we(i)  := '0';
                      end if; 

                      CollisionTableRest(
                        same_data_flg  => same_data_flg,
                        same_datap_flg => same_datap_flg,
                        clsn_bufs      => clsn_bufs,
                        mem            => memory,
                        di1            => di1,
                        di2            => di2,
                        dip1           => dip1,
                        dip2           => dip2,
                        addr1          => tmp_addr1_zero,
                        addr2          => tmp_addr2_zero,
                        addrp1         => tmp_parity_addr1_zero,
                        addrp2         => tmp_parity_addr2_zero,
                        wr_mode_1      => wr_mode_1,
                        wr_mode_2      => wr_mode_2,
                        violation      => violation,
                        we_segment     => i,
                        we1            => tmp_we1,
                        we2            => tmp_we2,
                        D1W            => DI1W,
                        D1PW           => DIP1W,
                        D2W            => DO2W,
                        D2PW           => DOP2W
                      );
                end if;
             ---------
             when "11" =>
             ---------
                same_data_flg  := false;
                same_datap_flg := false;

                zero_addr1 := zero_write_1;
                zero_addr2 := zero_write_2;

                zero_parity_addr1 := zero_writep_1;
                zero_parity_addr2 := zero_writep_2;

                tmp_we1 := '1';
                tmp_we2 := '1';

                if(AddrOverlapCheck(DI1W, DI2W, addr1, addr2, zero_addr1, zero_addr2,i)) then

                   tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_addr1);
                   tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_addr2);

                   tmp_parity_addr1_zero := addr1(13 downto 3) and zero_parity_addr1;
                   tmp_parity_addr2_zero := addr2(13 downto 3) and zero_parity_addr2;

                      if(violation = 12) then
                         if(wr_mode_2 = "01") then
                            clsn_type.write_write := true;
                            clsn_type.we(i)  := '1';
                         end if; 
                      else 
                         clsn_type.write_write := true;
                         clsn_type.we(i)  := '1';
                      end if;

                      CollisionTableRest(
                        same_data_flg  => same_data_flg,
                        same_datap_flg => same_datap_flg,
                        clsn_bufs      => clsn_bufs,
                        mem            => memory,
                        di1            => di1,
                        di2            => di2,
                        dip1           => dip1,
                        dip2           => dip2,
                        addr1          => tmp_addr1_zero,
                        addr2          => tmp_addr2_zero,
                        addrp1         => tmp_parity_addr1_zero,
                        addrp2         => tmp_parity_addr2_zero,
                        wr_mode_1      => wr_mode_1,
                        wr_mode_2      => wr_mode_2,
                        violation      => violation,
                        we_segment     => i,
                        we1            => tmp_we1,
                        we2            => tmp_we2,
                        D1W            => DI1W,
                        D1PW           => DIP1W,
                        D2W            => DI2W,
                        D2PW           => DIP2W
                      );
                end if;

                if((DI1W /= DO1W) or (DI2W /= DO2W)) then
--FP disabled the cross check call
--                   tmp_we1 := '1';
--                   tmp_we2 := '0';
                   tmp_we1 := '0';
                   tmp_we2 := '0';

                   zero_addr1 := zero_write_1;
                   zero_addr2 := zero_read_2;

                   zero_parity_addr1 := zero_writep_1;
                   zero_parity_addr2 := zero_readp_2;

                   if(AddrOverlapCheck(DI1W, DO2W, addr1, addr2, zero_addr1, zero_addr2,i)) then

                      tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_addr1);
                      tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_addr2);

                      tmp_parity_addr1_zero := addr1(13 downto 3) and zero_parity_addr1;
                      tmp_parity_addr2_zero := addr2(13 downto 3) and zero_parity_addr2;

                      CollisionTableRest(
                        same_data_flg  => same_data_flg,
                        same_datap_flg => same_datap_flg,
                        clsn_bufs      => clsn_bufs,
                        mem            => memory,
                        di1            => di1,
                        di2            => di2,
                        dip1           => dip1,
                        dip2           => dip2,
                        addr1          => tmp_addr1_zero,
                        addr2          => tmp_addr2_zero,
                        addrp1         => tmp_parity_addr1_zero,
                        addrp2         => tmp_parity_addr2_zero,
                        wr_mode_1      => wr_mode_1,
                        wr_mode_2      => wr_mode_2,
                        violation      => violation,
                        we_segment     => i,
                        we1            => tmp_we1,
                        we2            => tmp_we2,
                        D1W            => DI1W,
                        D1PW           => DIP1W,
                        D2W            => DO2W,
                        D2PW           => DOP2W
                      );
                   end if;

--FP disabled the cross check call
--                   tmp_we1 := '0';
--                   tmp_we2 := '1';
                   tmp_we1 := '0';
                   tmp_we2 := '0';

                   zero_addr1 := zero_read_1;
                   zero_addr2 := zero_write_2;

                   zero_parity_addr1 := zero_readp_1;
                   zero_parity_addr2 := zero_writep_2;

                   if(AddrOverlapCheck(DO1W, DI2W, addr1, addr2, zero_addr1, zero_addr2,i)) then

                      tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_addr1);
                      tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_addr2);

                      tmp_parity_addr1_zero := addr1(13 downto 3) and zero_parity_addr1;
                      tmp_parity_addr2_zero := addr2(13 downto 3) and zero_parity_addr2;

                      CollisionTableRest(
                        same_data_flg  => same_data_flg,
                        same_datap_flg => same_datap_flg,
                        clsn_bufs      => clsn_bufs,
                        mem            => memory,
                        di1            => di1,
                        di2            => di2,
                        dip1           => dip1,
                        dip2           => dip2,
                        addr1          => tmp_addr1_zero,
                        addr2          => tmp_addr2_zero,
                        addrp1         => tmp_parity_addr1_zero,
                        addrp2         => tmp_parity_addr2_zero,
                        wr_mode_1      => wr_mode_1,
                        wr_mode_2      => wr_mode_2,
                        violation      => violation,
                        we_segment     => i,
                        we1            => tmp_we1,
                        we2            => tmp_we2,
                        D1W            => DO1W,
                        D1PW           => DOP1W,
                        D2W            => DI2W,
                        D2PW           => DIP2W
                      );

                   end if;
                end if;
  
             when others =>
                null;

         end case;

      end loop;

   end PreProcessWe1We2;
------------------------------------------------
-- procedure Memory_Collision_Msg_ramb16
------------------------------------------------
-- This is almost the same procedure as the procedure for V2 ram collision 
-- except that is is local to the model (since this is the only one that 
-- calls this procedure
  Procedure Memory_Collision_Msg_ramb16 (
    CONSTANT HeaderMsg      : IN STRING := " Memory Collision Error on ";        
    CONSTANT EntityName : IN STRING := "";
    CONSTANT InstanceName : IN STRING := "";
    constant collision_type : in memory_collision_type;
    constant address_1 : in std_logic_vector; 
    constant address_2 : in std_logic_vector; 
    CONSTANT MsgSeverity    : IN SEVERITY_LEVEL := Error
    
    
    ) IS
    variable current_time : time := NOW;
    variable string_length_1 : integer;
    variable string_length_2 : integer;    

    VARIABLE Message : LINE;
  BEGIN
    if ((address_1'length mod 4) = 0) then
      string_length_1 := address_1'length/4;
    elsif ((address_1'length mod 4) > 0) then
      string_length_1 := address_1'length/4 + 1;      
    end if;
    if ((address_2'length mod 4) = 0) then
      string_length_2 := address_2'length/4;
    elsif ((address_2'length mod 4) > 0) then
      string_length_2 := address_2'length/4 + 1;      
    end if;    
--    if ((collision_type = Read_A_Write_B) or (collision_type = Read_B_Write_A)) then
    if ((collision_type = Read_A_Write_B) or (collision_type = Write_A_Read_B) or
        (collision_type = Read_B_Write_A) or (collision_type = Write_B_Read_A)) then
      Write ( Message, HeaderMsg);
      Write ( Message, EntityName);    
      Write ( Message, STRING'(": "));
      Write ( Message, InstanceName);
      Write ( Message, STRING'(" at simulation time "));
      Write ( Message, current_time);
      Write ( Message, STRING'("."));
      Write ( Message, LF );            
      Write ( Message, STRING'(" A read was performed on address "));
      Write ( Message, SLV_TO_HEX(address_1, string_length_1));
      Write ( Message, STRING'(" (hex) "));            
--      if (collision_type = Read_A_Write_B) then
      if ((collision_type = Read_A_Write_B) or (collision_type = Write_B_Read_A))then
         Write ( Message, STRING'("of port A while a write was requested to the same address on Port B "));
         Write ( Message, STRING'(" The write will be successful however the read value is unknown until the next CLKA cycle  "));
--      elsif(collision_type = Read_B_Write_A) then
      elsif((collision_type = Read_B_Write_A) or (collision_type = Write_A_Read_B)) then
         Write ( Message, STRING'("of port B while a write was requested to the same address on Port A "));
         Write ( Message, STRING'(" The write will be successful however the read value is unknown until the next CLKB cycle  "));
      end if;
    elsif ((collision_type = Write_A_Write_B) or (collision_type = Write_B_Write_A)) then
      Write ( Message, HeaderMsg);
      Write ( Message, EntityName);    
      Write ( Message, STRING'(": "));
      Write ( Message, InstanceName);
      Write ( Message, STRING'(" at simulation time "));
      Write ( Message, current_time);
      Write ( Message, STRING'("."));
      Write ( Message, LF );            
      Write ( Message, STRING'(" A write was requested to the same address simultaneously at both Port A and Port B of the RAM."));
      Write ( Message, STRING'(" The contents written to the RAM at address location "));      
      Write ( Message, SLV_TO_HEX(address_1, string_length_1));
      Write ( Message, STRING'(" (hex) "));            
      Write ( Message, STRING'("of Port A and address location "));
      Write ( Message, SLV_TO_HEX(address_2, string_length_2));
      Write ( Message, STRING'(" (hex) "));            
      Write ( Message, STRING'("of Port B are unknown. "));
    end if;      
    ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;

    DEALLOCATE (Message);
  END Memory_Collision_Msg_ramb16;      

------------------ END Procedures/Functions ------------------------------

  signal ADDRA_ipd    : std_logic_vector(MAX_ADDR downto 0) := (others => 'X');
  signal CLKA_ipd     : std_ulogic                          := 'X';
  signal DIA_ipd      : std_logic_vector(MAX_DI  downto 0)  := (others => 'X');
  signal DIPA_ipd     : std_logic_vector(MAX_DIP downto 0)  := (others => 'X');
  signal ENA_ipd      : std_ulogic                          := 'X';
  signal RSTA_ipd      : std_ulogic                          := 'X';
  signal REGCEA_ipd   : std_ulogic                          := 'X';
  signal WEA_ipd      : std_logic_vector(MAX_WE downto 0)   := (others => 'X');

  signal ADDRB_ipd    : std_logic_vector(MAX_ADDR downto 0) := (others => 'X');
  signal CLKB_ipd     : std_ulogic                          := 'X';
  signal DIB_ipd      : std_logic_vector(MAX_DI  downto 0)  := (others => 'X');
  signal DIPB_ipd     : std_logic_vector(MAX_DIP downto 0)  := (others => 'X');
  signal ENB_ipd      : std_ulogic                          := 'X';
  signal RSTB_ipd      : std_ulogic                          := 'X';
  signal REGCEB_ipd   : std_ulogic                          := 'X';
  signal WEB_ipd      : std_logic_vector(MAX_WE downto 0)   := (others => 'X');

  signal GSR          : std_ulogic := '0';
  signal GSR_ipd      : std_ulogic                          := 'X';

  signal GSR_dly      : std_ulogic                          := 'X';

  signal ADDRA_dly    : std_logic_vector(MAX_ADDR downto 0) := (others => 'X');
  signal CLKA_dly     : std_ulogic                          := 'X';
  signal DIA_dly      : std_logic_vector(MAX_DI downto 0) := (others => 'X');
  signal DIPA_dly     : std_logic_vector(MAX_DIP downto 0)  := (others => 'X');
  signal ENA_dly      : std_ulogic                          := 'X';
  signal GSR_CLKA_dly : std_ulogic                          := 'X';
  signal RSTA_dly      : std_ulogic                          := 'X';
  signal REGCEA_dly   : std_ulogic                          := 'X';
  signal WEA_dly      : std_logic_vector(MAX_WE downto 0)   := (others => 'X');

  signal ADDRB_dly    : std_logic_vector(MAX_ADDR downto 0) := (others => 'X');
  signal CLKB_dly     : std_ulogic                          := 'X';
  signal DIB_dly      : std_logic_vector(MAX_DI downto 0) := (others => 'X');
  signal DIPB_dly     : std_logic_vector(MAX_DIP downto 0)  := (others => 'X');
  signal ENB_dly      : std_ulogic                          := 'X';
  signal GSR_CLKB_dly : std_ulogic                          := 'X';
  signal RSTB_dly      : std_ulogic                          := 'X';
  signal REGCEB_dly   : std_ulogic                          := 'X';
  signal WEB_dly      : std_logic_vector(MAX_WE downto 0)   := (others => 'X');

  signal DOA_viol     : std_logic_vector(MAX_DI downto 0);
  signal DOPA_viol    : std_logic_vector(3 downto 0);
  signal DOB_viol     : std_logic_vector(MAX_DI downto 0);
  signal DOPB_viol    : std_logic_vector(3 downto 0);

  signal DOA_regist   : std_logic_vector(MAX_DI downto 0);
  signal DOPA_regist  : std_logic_vector(3 downto 0);
  signal DOB_regist   : std_logic_vector(MAX_DI downto 0);
  signal DOPB_regist  : std_logic_vector(3 downto 0);

  signal DOA_mux      : std_logic_vector(MAX_DI downto 0);
  signal DOPA_mux     : std_logic_vector(3 downto 0);
  signal DOB_mux      : std_logic_vector(MAX_DI downto 0);
  signal DOPB_mux     : std_logic_vector(3 downto 0);


  signal DIAW              : integer;
  signal DIAW_1            : integer;
  signal DIBW              : integer;
  signal DIBW_1            : integer;
  signal DIPAW             : integer;
  signal DIPAW_1           : integer;
  signal DIPBW             : integer;
  signal DIPBW_1           : integer;

  signal DOAW              : integer;
  signal DOAW_1            : integer;
  signal DOBW              : integer;
  signal DOBW_1            : integer;
  signal DOPAW             : integer;
  signal DOPAW_1           : integer;
  signal DOPBW             : integer;
  signal DOPBW_1           : integer;

  signal INI_A_sig         : std_logic_vector (35 downto 0) :=  (others => 'X');
  signal INI_B_sig         : std_logic_vector (35 downto 0) :=  (others => 'X');

  signal SRVA_A_sig        : std_logic_vector (35 downto 0) :=  (others => 'X');
  signal SRVA_B_sig        : std_logic_vector (35 downto 0) :=  (others => 'X');

  signal rst_async_flag    : std_ulogic := '0';

  signal INIT_DONE         : boolean := false;

begin
  ---------------------
  --  INPUT PATH DELAYs
  --------------------

  ADDRA_dly      	 <= ADDRA          	after 0 ps;
  ADDRB_dly      	 <= ADDRB          	after 0 ps;
  CLKA_dly       	 <= CLKA           	after 0 ps;
  CLKB_dly       	 <= CLKB           	after 0 ps;
  DIA_dly        	 <= DIA            	after 0 ps;
  DIB_dly        	 <= DIB            	after 0 ps;
  DIPA_dly       	 <= DIPA           	after 0 ps;
  DIPB_dly       	 <= DIPB           	after 0 ps;
  ENA_dly        	 <= ENA            	after 0 ps;
  ENB_dly        	 <= ENB            	after 0 ps;
  GSR_dly        	 <= GSR            	after 0 ps;
  RSTA_dly       	 <= RSTA           	after 0 ps;
  RSTB_dly       	 <= RSTB           	after 0 ps;
  REGCEA_dly     	 <= REGCEA         	after 0 ps;
  REGCEB_dly     	 <= REGCEB         	after 0 ps;
  WEA_dly        	 <= WEA            	after 0 ps;
  WEB_dly        	 <= WEB            	after 0 ps;
  GSR_CLKA_dly           <= GSR                 after 0 ps;
  GSR_CLKB_dly           <= GSR                 after 0 ps;

  --------------------
  --  BEHAVIOR SECTION
  --------------------

   prcs_initialize:process
    variable INI_A         : std_logic_vector (35 downto 0) :=  (others => 'X');
    variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B         : std_logic_vector (35 downto 0) :=  (others => 'X');
    variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0);

    variable SRVA_A            : std_logic_vector (35 downto 0) :=  (others => 'X');
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (35 downto 0) :=  (others => 'X');
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);

    variable DIAW_var              : integer;
    variable DIAW_1_var            : integer;
    variable DIBW_var              : integer;
    variable DIBW_1_var            : integer;
    variable DIPAW_var             : integer;
    variable DIPAW_1_var           : integer;
    variable DIPBW_var             : integer;
    variable DIPBW_1_var           : integer;

    variable DOAW_var              : integer;
    variable DOAW_1_var            : integer;
    variable DOBW_var              : integer;
    variable DOBW_1_var            : integer;
    variable DOPAW_var             : integer;
    variable DOPAW_1_var           : integer;
    variable DOPBW_var             : integer;
    variable DOPBW_1_var           : integer;

   begin
      DIPAW_var   := 0;
      DIPAW_1_var := -1;
      DIPBW_var   := 0;
      DIPBW_1_var := -1;

      DOPAW_var   := 0;
      DOPAW_1_var := -1;
      DOPBW_var   := 0;
      DOPBW_1_var := -1;

     
--------------------------------------------------------------------
--    Additional Checks Added Later
--------------------------------------------------------------------
      if((DATA_WIDTH_A = 0) and (DATA_WIDTH_B = 0 )) then
        assert false
        report "Attribute Syntax Error: Both DATA_WIDTH_A and DATA_WIDTH_B can not be 0."
        severity Failure;
      end if;

      case DATA_WIDTH_A is

            when 0 =>
                 DOAW_var    := 1;
                 DOAW_1_var  := DOAW_var -1;
                 DIAW_var    := 1;
                 DIAW_1_var  := DIAW_var -1;

            when 1 =>
                 DOAW_var    := 1;
                 DOAW_1_var  := DOAW_var -1;
                 DIAW_var    := 1;
                 DIAW_1_var  := DIAW_var -1;

            when 2 =>
                 DOAW_var    := 2;
                 DOAW_1_var  := DOAW_var -1;
                 DIAW_var    := 2;
                 DIAW_1_var  := DIAW_var -1;

            when 4 =>
                 DOAW_var    := 4;
                 DOAW_1_var  := DOAW_var -1;
                 DIAW_var    := 4;
                 DIAW_1_var  := DIAW_var -1;

            when 9 =>
                 DOAW_var    := 8;
                 DOAW_1_var  := DOAW_var -1;
                 DOPAW_var   := 1;
                 DOPAW_1_var := DOPAW_var -1;
                 DIAW_var    := 8;
                 DIAW_1_var  := DIAW_var -1;
                 DIPAW_var   := 1;
                 DIPAW_1_var := DIPAW_var -1;

            when 18  =>
                 DOAW_var    := 16;
                 DOAW_1_var  := DOAW_var -1;
                 DOPAW_var   := 2;
                 DOPAW_1_var := DOPAW_var -1;
                 DIAW_var    := 16;
                 DIAW_1_var  := DIAW_var -1;
                 DIPAW_var   := 2;
                 DIPAW_1_var := DIPAW_var -1;

            when 36  =>
                 DOAW_var    := 32;
                 DOAW_1_var  := DOAW_var -1;
                 DOPAW_var   := 4;
                 DOPAW_1_var := DOPAW_var -1;
                 DIAW_var    := 32;
                 DIAW_1_var  := DIAW_var -1;
                 DIPAW_var   := 4;
                 DIPAW_1_var := DIPAW_var -1;

            when others =>
                 GenericValueCheckMessage
                 (  HeaderMsg            => " Attribute Syntax Error : ",
                    GenericName          => " DATA_WIDTH_A ",
                    EntityName           => "/RAMB16BWER",
                    GenericValue         => DATA_WIDTH_A,
                    Unit                 => "",
                    ExpectedValueMsg     => " The Legal values for this attribute are ",
                    ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.",
                    TailMsg              => "",
                    MsgSeverity          => failure
                 );
      end case;


      case DATA_WIDTH_B is

            when 0 =>
                 DOBW_var    := 1;
                 DOBW_1_var  := DOBW_var -1;
                 DIBW_var    := 1;
                 DIBW_1_var  := DIBW_var -1;

            when 1 =>
                 DOBW_var    := 1;
                 DOBW_1_var  := DOBW_var -1;
                 DIBW_var    := 1;
                 DIBW_1_var  := DIBW_var -1;

            when 2 =>
                 DOBW_var    := 2;
                 DOBW_1_var  := DOBW_var -1;
                 DIBW_var    := 2;
                 DIBW_1_var  := DIBW_var -1;

            when 4 =>
                 DOBW_var    := 4;
                 DOBW_1_var  := DOBW_var -1;
                 DIBW_var    := 4;
                 DIBW_1_var  := DIBW_var -1;

            when 9 =>
                 DOBW_var    := 8;
                 DOBW_1_var  := DOBW_var -1;
                 DOPBW_var   := 1;
                 DOPBW_1_var := DOPBW_var -1;
                 DIBW_var    := 8;
                 DIBW_1_var  := DIBW_var -1;
                 DIPBW_var   := 1;
                 DIPBW_1_var := DIPBW_var -1;

            when 18  =>
                 DOBW_var    := 16;
                 DOBW_1_var  := DOBW_var -1;
                 DOPBW_var   := 2;
                 DOPBW_1_var := DOPBW_var -1;
                 DIBW_var    := 16;
                 DIBW_1_var  := DIBW_var -1;
                 DIPBW_var   := 2;
                 DIPBW_1_var := DIPBW_var -1;

            when 36  =>
                 DOBW_var    := 32;
                 DOBW_1_var  := DOBW_var -1;
                 DOPBW_var   := 4;
                 DOPBW_1_var := DOPBW_var -1;
                 DIBW_var    := 32;
                 DIBW_1_var  := DIBW_var -1;
                 DIPBW_var   := 4;
                 DIPBW_1_var := DIPBW_var -1;

            when others =>
                 GenericValueCheckMessage
                 (  HeaderMsg            => " Attribute Syntax Error : ",
                    GenericName          => " DATA_WIDTH_B ",
                    EntityName           => "/RAMB16BWER",
                    GenericValue         => DATA_WIDTH_B,
                    Unit                 => "",
                    ExpectedValueMsg     => " The Legal values for this attribute are ",
                    ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.",
                    TailMsg              => "",
                    MsgSeverity          => failure
                 );
                 null;

      end case;


      if (INIT_A'length > 36) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A );
        INI_A(35 downto 0)                      := INI_A_UNBOUND(35 downto 0);
      elsif (INIT_A'length < 36) then
        INI_A(INIT_A'length-1 downto 0)         := To_StdLogicVector(INIT_A );
      elsif (INIT_A'length = 36) then
        INI_A(INIT_A'length-1 downto 0)         := To_StdLogicVector(INIT_A );
      end if;

      if (INIT_B'length > 36) then
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B );
        INI_B(35 downto 0)                      := INI_B_UNBOUND(35 downto 0);
      elsif (INIT_B'length < 36) then
        INI_B(INIT_B'length-1 downto 0)         := To_StdLogicVector(INIT_B );
      elsif (INIT_B'length = 36) then
        INI_B(INIT_B'length-1 downto 0)         := To_StdLogicVector(INIT_B );
      end if;

      if (SRVAL_A'length > 36) then
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A );
        SRVA_A(35 downto 0)                       := SRVA_A_UNBOUND(35 downto 0);
      elsif (SRVAL_A'length < 36) then
        SRVA_A(SRVAL_A'length-1 downto 0)         := To_StdLogicVector(SRVAL_A );
      elsif (SRVAL_A'length = 36) then
        SRVA_A(SRVAL_A'length-1 downto 0)         := To_StdLogicVector(SRVAL_A );
      end if;

      if (SRVAL_B'length > 36) then
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B );
        SRVA_B(35 downto 0)                       := SRVA_B_UNBOUND(35 downto 0);
      elsif (SRVAL_B'length < 36) then
        SRVA_B(SRVAL_B'length-1 downto 0)         := To_StdLogicVector(SRVAL_B );
      elsif (SRVAL_B'length = 36) then
        SRVA_B(SRVAL_B'length-1 downto 0)         := To_StdLogicVector(SRVAL_B );
      end if;

      DIAW     <= DIAW_var;
      DIAW_1   <= DIAW_1_var;
      DIBW     <= DIBW_var;
      DIBW_1   <= DIBW_1_var;
      DIPAW    <= DIPAW_var;
      DIPAW_1  <= DIPAW_1_var;
      DIPBW    <= DIPBW_var;
      DIPBW_1  <= DIPBW_1_var;

      DOAW     <= DOAW_var;
      DOAW_1   <= DOAW_1_var;
      DOBW     <= DOBW_var;
      DOBW_1   <= DOBW_1_var;
      DOPAW    <= DOPAW_var;
      DOPAW_1  <= DOPAW_1_var;
      DOPBW    <= DOPBW_var;
      DOPBW_1  <= DOPBW_1_var;

      SRVA_A_sig <= SRVA_A;
      SRVA_B_sig <= SRVA_B;
      INI_A_sig  <= INI_A;
      INI_B_sig  <= INI_B;

-------- RSTTYPE ----------

     if((RSTTYPE = "SYNC") or (RSTTYPE = "sync")) then
        rst_async_flag  <= '0';
     elsif((RSTTYPE = "ASYNC") or (RSTTYPE = "async")) then
        rst_async_flag  <= '1';
     else
        assert false
        report "Attribute Syntax Error: The attribute RSTTYPE on DSP48A is incorrect. Legal values for this attribute are SYNC or ASYNC."
        severity Failure;
     end if;
-----------------------------

      INIT_DONE  <= true;

      wait;
  end process prcs_initialize;
---------------------------------------------------------------------------------------
  VITALBehavior                         : process

    variable MEM : std_logic_vector(18431 downto 0) := To_StdLogicVector(INITP_07) &
                                                       To_StdLogicVector(INITP_06) &
                                                       To_StdLogicVector(INITP_05) &
                                                       To_StdLogicVector(INITP_04) &
                                                       To_StdLogicVector(INITP_03) &
                                                       To_StdLogicVector(INITP_02) &
                                                       To_StdLogicVector(INITP_01) &
                                                       To_StdLogicVector(INITP_00) & 

                                                       To_StdLogicVector(INIT_3F)  &
                                                       To_StdLogicVector(INIT_3E)  &
                                                       To_StdLogicVector(INIT_3D)  &
                                                       To_StdLogicVector(INIT_3C)  &
                                                       To_StdLogicVector(INIT_3B)  &
                                                       To_StdLogicVector(INIT_3A)  &
                                                       To_StdLogicVector(INIT_39)  &
                                                       To_StdLogicVector(INIT_38)  &
                                                       To_StdLogicVector(INIT_37)  &
                                                       To_StdLogicVector(INIT_36)  &
                                                       To_StdLogicVector(INIT_35)  &
                                                       To_StdLogicVector(INIT_34)  &
                                                       To_StdLogicVector(INIT_33)  &
                                                       To_StdLogicVector(INIT_32)  &
                                                       To_StdLogicVector(INIT_31)  &
                                                       To_StdLogicVector(INIT_30)  &
                                                       To_StdLogicVector(INIT_2F)  &
                                                       To_StdLogicVector(INIT_2E)  &
                                                       To_StdLogicVector(INIT_2D)  &
                                                       To_StdLogicVector(INIT_2C)  &
                                                       To_StdLogicVector(INIT_2B)  &
                                                       To_StdLogicVector(INIT_2A)  &
                                                       To_StdLogicVector(INIT_29)  &
                                                       To_StdLogicVector(INIT_28)  &
                                                       To_StdLogicVector(INIT_27)  &
                                                       To_StdLogicVector(INIT_26)  &
                                                       To_StdLogicVector(INIT_25)  &
                                                       To_StdLogicVector(INIT_24)  &
                                                       To_StdLogicVector(INIT_23)  &
                                                       To_StdLogicVector(INIT_22)  &
                                                       To_StdLogicVector(INIT_21)  &
                                                       To_StdLogicVector(INIT_20)  &
                                                       To_StdLogicVector(INIT_1F)  &
                                                       To_StdLogicVector(INIT_1E)  &
                                                       To_StdLogicVector(INIT_1D)  &
                                                       To_StdLogicVector(INIT_1C)  &
                                                       To_StdLogicVector(INIT_1B)  &
                                                       To_StdLogicVector(INIT_1A)  &
                                                       To_StdLogicVector(INIT_19)  &
                                                       To_StdLogicVector(INIT_18)  &
                                                       To_StdLogicVector(INIT_17)  &
                                                       To_StdLogicVector(INIT_16)  &
                                                       To_StdLogicVector(INIT_15)  &
                                                       To_StdLogicVector(INIT_14)  &
                                                       To_StdLogicVector(INIT_13)  &
                                                       To_StdLogicVector(INIT_12)  &
                                                       To_StdLogicVector(INIT_11)  &
                                                       To_StdLogicVector(INIT_10)  &
                                                       To_StdLogicVector(INIT_0F)  &
                                                       To_StdLogicVector(INIT_0E)  &
                                                       To_StdLogicVector(INIT_0D)  &
                                                       To_StdLogicVector(INIT_0C)  &
                                                       To_StdLogicVector(INIT_0B)  &
                                                       To_StdLogicVector(INIT_0A)  &
                                                       To_StdLogicVector(INIT_09)  &
                                                       To_StdLogicVector(INIT_08)  &
                                                       To_StdLogicVector(INIT_07)  &
                                                       To_StdLogicVector(INIT_06)  &
                                                       To_StdLogicVector(INIT_05)  &
                                                       To_StdLogicVector(INIT_04)  &
                                                       To_StdLogicVector(INIT_03)  &
                                                       To_StdLogicVector(INIT_02)  &
                                                       To_StdLogicVector(INIT_01)  &
                                                       To_StdLogicVector(INIT_00) ;
 
    variable INI_A         : std_logic_vector (35 downto 0) := (others => 'X');
    variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0);
    variable INI_B         : std_logic_vector (35 downto 0) := (others => 'X');
    variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0);

    variable DIAW              : integer;
    variable DIAW_1            : integer;
    variable DIBW              : integer;
    variable DIBW_1            : integer;
    variable DIPAW             : integer;
    variable DIPAW_1           : integer;
    variable DIPBW             : integer;
    variable DIPBW_1           : integer;

    variable DOAW              : integer;
    variable DOAW_1            : integer;
    variable DOBW              : integer;
    variable DOBW_1            : integer;
    variable DOPAW             : integer;
    variable DOPAW_1           : integer;
    variable DOPBW             : integer;
    variable DOPBW_1           : integer;

    variable ADDRA_dly_sampled : std_logic_vector(MAX_ADDR downto 0)   := (others => 'X');
    variable ADDRB_dly_sampled : std_logic_vector(MAX_ADDR downto 0)   := (others => 'X');
    variable ADDRESS_A         : integer;
    variable ADDRESS_B         : integer;

    variable ADDRESS_READ_A, ADDRESS_WRITE_A, ADDRESS_READ_B, ADDRESS_WRITE_B : integer;
    variable ADDRESS_PARITY_READ_A, ADDRESS_PARITY_WRITE_A, ADDRESS_PARITY_READ_B, ADDRESS_PARITY_WRITE_B : integer;

    variable DOA_INDEX, DOPA_INDEX : integer := -1;
    variable DOB_INDEX, DOPB_INDEX : integer := -1;

    variable DOA_OV_LSB        : integer;
    variable DOA_OV_MSB        : integer;
    variable DOA_zd            : std_logic_vector(MAX_DI downto 0)  := INI_A(MAX_DI downto 0);
    variable DOA_zd_buf        : std_logic_vector(MAX_DI downto 0)  := INI_A(MAX_DI downto 0);
    variable DOB_OV_LSB        : integer;
    variable DOB_OV_MSB        : integer;
    variable DOB_zd            : std_logic_vector(MAX_DI downto 0)  := INI_B(MAX_DI downto 0);
    variable DOB_zd_buf        : std_logic_vector(MAX_DI downto 0)  := INI_B(MAX_DI downto 0);
    variable DOPA_OV_LSB       : integer;
    variable DOPA_OV_MSB       : integer;
    variable DOPA_zd           : std_logic_vector(3 downto 0)   := INI_A(35 downto 32);
    variable DOPA_zd_buf       : std_logic_vector(3 downto 0)   := INI_A(35 downto 32);
    variable DOPB_OV_LSB       : integer;
    variable DOPB_OV_MSB       : integer;
    variable DOPB_zd           : std_logic_vector(3 downto 0)   := INI_B(35 downto 32);
    variable DOPB_zd_buf       : std_logic_vector(3 downto 0)   := INI_B(35 downto 32);
    variable ENA_dly_sampled   : std_ulogic                      := 'X';
    variable ENB_dly_sampled   : std_ulogic                      := 'X';
    variable FIRST_TIME        : boolean                        := true;
    variable HAS_OVERLAP       : boolean                        := false;
    variable HAS_OVERLAP_P     : boolean                        := false;
    variable OLPP_LSB          : integer;
    variable OLPP_MSB          : integer;
    variable OLP_LSB           : integer;
    variable OLP_MSB           : integer;
    variable SRVA_A            : std_logic_vector (35 downto 0) := (others => 'X');
    variable SRVA_A_UNBOUND    : std_logic_vector (SRVAL_A'length-1 downto 0);
    variable SRVA_B            : std_logic_vector (35 downto 0) := (others => 'X');
    variable SRVA_B_UNBOUND    : std_logic_vector (SRVAL_B'length-1 downto 0);
    variable RSTA_dly_sampled  : std_ulogic                      := 'X';
    variable RSTB_dly_sampled  : std_ulogic                      := 'X';
    variable VALID_ADDRA       : boolean                        := true;
    variable VALID_ADDRB       : boolean                        := true;
    variable ViolationA        : std_ulogic                     := '0';
    variable ViolationB        : std_ulogic                     := '0';
    variable ViolationCLKAB    : std_ulogic                     := '0';
    variable ViolationCLKAB_S0 : boolean                        := false;
    variable Violation_S1      : boolean                        := false;
    variable Violation_S3      : boolean                        := false;
    variable WEA_dly_sampled   : std_logic_vector(MAX_WE downto 0) := (others => 'X');
    variable WEB_dly_sampled   : std_logic_vector(MAX_WE downto 0) := (others => 'X');
    variable wr_mode_a         : std_logic_vector(1 downto 0)   := "00";
    variable wr_mode_b         : std_logic_vector(1 downto 0)   := "00";

--FP
    variable wea_index          : integer                       := -1;
    variable web_index          : integer                       := -1;

    variable tmp_we                  : std_logic_vector(1 downto 0)             := (others => '1');
    variable xout_we_seg1            : std_logic_vector(1 downto 0)             := (others => '0');
    variable xout_we_seg2            : std_logic_vector(1 downto 0)             := (others => '0');

    variable tmp_zero_write_a        : std_logic_vector(MAX_ADDR downto 0)      := (others => '1');
    variable tmp_zero_read_a         : std_logic_vector(MAX_ADDR downto 0)      := (others => '1');
    variable tmp_zero_parity_write_a : std_logic_vector((MAX_ADDR-3) downto 0)  := (others => '0');
    variable tmp_zero_parity_read_a  : std_logic_vector((MAX_ADDR-3) downto 0)  := (others => '0');

    variable tmp_zero_write_b        : std_logic_vector(MAX_ADDR downto 0)      := (others => '1');
    variable tmp_zero_read_b         : std_logic_vector(MAX_ADDR downto 0)      := (others => '1');
    variable tmp_zero_parity_write_b : std_logic_vector((MAX_ADDR-3) downto 0)  := (others => '0');
    variable tmp_zero_parity_read_b  : std_logic_vector((MAX_ADDR-3) downto 0)  := (others => '0');

    variable zero_write_a        : std_logic_vector(MAX_ADDR downto 0)      := (others => '1');
    variable zero_read_a         : std_logic_vector(MAX_ADDR downto 0)      := (others => '1');
    variable zero_parity_write_a : std_logic_vector((MAX_ADDR-3) downto 0)  := (others => '1');
    variable zero_parity_read_a  : std_logic_vector((MAX_ADDR-3) downto 0)  := (others => '1');

    variable zero_write_b        : std_logic_vector(MAX_ADDR downto 0)      := (others => '1');
    variable zero_read_b         : std_logic_vector(MAX_ADDR downto 0)      := (others => '1');
    variable zero_parity_write_b : std_logic_vector((MAX_ADDR-3) downto 0)  := (others => '1');
    variable zero_parity_read_b  : std_logic_vector((MAX_ADDR-3) downto 0)  := (others => '1');


    variable addra_in_14 : std_ulogic := '0';
    variable addrb_in_14 : std_ulogic := '0';

    variable SimCollisionCheck_var : integer := 3;
    variable collision_clka_clkb   : integer := 0;
    variable addr_overlap          : boolean := false;

    variable CLKA_time             : time := 0 ps;
    variable CLKB_time             : time := 0 ps;

    variable DOA_clsn              : std_logic_vector(31 downto 0) := (others => '0');
    variable DOPA_clsn             : std_logic_vector(3 downto 0) := (others => '0');
    variable DOA_clsn_sav          : std_logic_vector(31 downto 0) := (others => '0');
    variable DOPA_clsn_sav         : std_logic_vector(3 downto 0) := (others => '0');
    variable DOA_clsn_zero         : std_logic_vector(31 downto 0) := (others => '0');
    variable DOPA_clsn_zero        : std_logic_vector(3 downto 0) := (others => '0');

    variable DOB_clsn              : std_logic_vector(31 downto 0) := (others => '0');
    variable DOPB_clsn             : std_logic_vector(3 downto 0) := (others => '0');
    variable DOB_clsn_sav          : std_logic_vector(31 downto 0) := (others => '0');
    variable DOPB_clsn_sav         : std_logic_vector(3 downto 0) := (others => '0');
    variable DOB_clsn_zero         : std_logic_vector(31 downto 0) := (others => '0');
    variable DOPB_clsn_zero        : std_logic_vector(3 downto 0) := (others => '0');

    variable DOA_clsn_slice        : std_logic_vector(31 downto 0) := (others => '0');
    variable DOPA_clsn_slice       : std_logic_vector(3 downto 0) := (others => '0');
    variable DOB_clsn_slice        : std_logic_vector(31 downto 0) := (others => '0');
    variable DOPB_clsn_slice       : std_logic_vector(3 downto 0) := (others => '0');

    variable tmp_membuf            : std_logic_vector(31 downto 0) := (others => '0');

    variable DOA_clsn_read_index, DOPA_clsn_read_index : integer := -1;
    variable DOB_clsn_read_index, DOPB_clsn_read_index : integer := -1;

    variable DOA_clsn_write_index, DOPA_clsn_write_index : integer := -1;
    variable DOB_clsn_write_index, DOPB_clsn_write_index : integer := -1;

    variable clsn_type       : CollisionFlagType;
    variable data_widths     : DataWidthType;
    variable clsn_xbufs      : ClsnXbufType;

    variable collision_msg   : memory_collision_type;

    variable Write_A_Write_B : memory_collision_type := Write_A_Write_B;
    variable Read_A_Write_B  : memory_collision_type := Read_A_Write_B;
    variable Write_A_Read_B  : memory_collision_type := Write_A_Read_B;
    variable Write_B_Write_A : memory_collision_type := Write_B_Write_A;
    variable Read_B_Write_A  : memory_collision_type := Read_B_Write_A;
    variable Write_B_Read_A  : memory_collision_type := Write_B_Read_A;

    variable msg_addr1       : std_logic_vector(MAX_ADDR downto 0)      := (others => '0');
    variable msg_addr2       : std_logic_vector(MAX_ADDR downto 0)      := (others => '0');

  begin


    if (FIRST_TIME) then

      DIPAW   := 0;
      DIPAW_1 := -1;
      DIPBW   := 0;
      DIPBW_1 := -1;

      DOPAW   := 0;
      DOPAW_1 := -1;
      DOPBW   := 0;
      DOPBW_1 := -1;

      case DATA_WIDTH_A is

            when 0 =>
                 DOAW    := 1;
                 DOAW_1  := DOAW -1;
                 DIAW    := 1;
                 DIAW_1  := DIAW -1;

            when 1 =>
                 zero_read_a(13 downto 0) := (others => '1');
                 DOAW    := 1;
                 DOAW_1  := DOAW -1;
                 zero_write_a(13 downto 0) := (others => '1');
                 DIAW    := 1;
                 DIAW_1  := DIAW -1;

            when 2 =>
                 zero_read_a(0 downto 0) := (others => '0');
                 DOAW    := 2;
                 DOAW_1  := DOAW -1;
                 zero_write_a(0 downto 0) := (others => '0');
                 DIAW    := 2;
                 DIAW_1  := DIAW -1;

            when 4 =>
                 zero_read_a(1 downto 0) := (others => '0');
                 DOAW    := 4;
                 DOAW_1  := DOAW -1;
                 zero_write_a(1 downto 0) := (others => '0');
                 DIAW    := 4;
                 DIAW_1  := DIAW -1;

            when 9 =>
                 zero_read_a(2 downto 0) := (others => '0');
                 DOAW    := 8;
                 DOAW_1  := DOAW -1;
                 DOPAW   := 1;
                 DOPAW_1 := DOPAW -1;
                 zero_write_a(2 downto 0) := (others => '0');
                 DIAW    := 8;
                 DIAW_1  := DIAW -1;
                 DIPAW   := 1;
                 DIPAW_1 := DIPAW -1;

            when 18  =>
                 zero_read_a(3 downto 0) := (others => '0');
                 zero_parity_read_a(0 downto 0) := (others => '0');
                 DOAW    := 16;
                 DOAW_1  := DOAW -1;
                 DOPAW   := 2;
                 DOPAW_1 := DOPAW -1;
                 zero_write_a(3 downto 0) := (others => '0');
                 zero_parity_write_a(0 downto 0) := (others => '0');
                 DIAW    := 16;
                 DIAW_1  := DIAW -1;
                 DIPAW   := 2;
                 DIPAW_1 := DIPAW -1;

            when 36  =>
                 zero_read_a(4 downto 0) := (others => '0');
                 zero_parity_read_a(1 downto 0) := (others => '0');
                 DOAW    := 32;
                 DOAW_1  := DOAW -1;
                 DOPAW   := 4;
                 DOPAW_1 := DOPAW -1;
                 zero_write_a(4 downto 0) := (others => '0');
                 zero_parity_write_a(1 downto 0) := (others => '0');
                 DIAW    := 32;
                 DIAW_1  := DIAW -1;
                 DIPAW   := 4;
                 DIPAW_1 := DIPAW -1;

            when others =>
                 null;

      end case;

      case DATA_WIDTH_B is

            when 0 =>
                 DOBW    := 1;
                 DOBW_1  := DOBW -1;
                 DIBW    := 1;
                 DIBW_1  := DIBW -1;

            when 1 =>
                 zero_read_b(13 downto 0) := (others => '1');
                 DOBW    := 1;
                 DOBW_1  := DOBW -1;
                 zero_write_b(13 downto 0) := (others => '1');
                 DIBW    := 1;
                 DIBW_1  := DIBW -1;

            when 2 =>
                 zero_read_b(0 downto 0) := (others => '0');
                 DOBW    := 2;
                 DOBW_1  := DOBW -1;
                 zero_write_b(0 downto 0) := (others => '0');
                 DIBW    := 2;
                 DIBW_1  := DIBW -1;

            when 4 =>
                 zero_read_b(1 downto 0) := (others => '0');
                 DOBW    := 4;
                 DOBW_1  := DOBW -1;
                 zero_write_b(1 downto 0) := (others => '0');
                 DIBW    := 4;
                 DIBW_1  := DIBW -1;

            when 9 =>
                 zero_read_b(2 downto 0) := (others => '0');
                 DOBW    := 8;
                 DOBW_1  := DOBW -1;
                 DOPBW   := 1;
                 DOPBW_1 := DOPBW -1;
                 zero_write_b(2 downto 0) := (others => '0');
                 DIBW    := 8;
                 DIBW_1  := DIBW -1;
                 DIPBW   := 1;
                 DIPBW_1 := DIPBW -1;

            when 18  =>
                 zero_read_b(3 downto 0) := (others => '0');
                 zero_parity_read_b(0 downto 0) := (others => '0');
                 DOBW    := 16;
                 DOBW_1  := DOBW -1;
                 DOPBW   := 2;
                 DOPBW_1 := DOPBW -1;
                 zero_write_b(3 downto 0) := (others => '0');
                 zero_parity_write_b(0 downto 0) := (others => '0');
                 DIBW    := 16;
                 DIBW_1  := DIBW -1;
                 DIPBW   := 2;
                 DIPBW_1 := DIPBW -1;

            when 36  =>
                 zero_read_b(4 downto 0) := (others => '0');
                 zero_parity_read_b(1 downto 0) := (others => '0');
                 DOBW    := 32;
                 DOBW_1  := DOBW -1;
                 DOPBW   := 4;
                 DOPBW_1 := DOPBW -1;
                 zero_write_b(4 downto 0) := (others => '0');
                 zero_parity_write_b(1 downto 0) := (others => '0');
                 DIBW    := 32;
                 DIBW_1  := DIBW -1;
                 DIPBW   := 4;
                 DIPBW_1 := DIPBW -1;

            when others =>
                 null;

      end case;

      if (INIT_A'length > 36) then
        INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A );
        INI_A(35 downto 0)                      := INI_A_UNBOUND(35 downto 0);
      elsif (INIT_A'length < 36) then
        INI_A(INIT_A'length-1 downto 0)         := To_StdLogicVector(INIT_A );
      elsif (INIT_A'length = 36) then
        INI_A(INIT_A'length-1 downto 0)         := To_StdLogicVector(INIT_A );
      end if;

      if (INIT_B'length > 36) then
        INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B );
        INI_B(35 downto 0)                      := INI_B_UNBOUND(35 downto 0);
      elsif (INIT_B'length < 36) then
        INI_B(INIT_B'length-1 downto 0)         := To_StdLogicVector(INIT_B );
      elsif (INIT_B'length = 36) then
        INI_B(INIT_B'length-1 downto 0)         := To_StdLogicVector(INIT_B );
      end if;

      if (SRVAL_A'length > 36) then
        SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A );
        SRVA_A(35 downto 0)                       := SRVA_A_UNBOUND(35 downto 0);
      elsif (SRVAL_A'length < 36) then
        SRVA_A(SRVAL_A'length-1 downto 0)         := To_StdLogicVector(SRVAL_A );
      elsif (SRVAL_A'length = 36) then
        SRVA_A(SRVAL_A'length-1 downto 0)         := To_StdLogicVector(SRVAL_A );
      end if;

      if (SRVAL_B'length > 36) then
        SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B );
        SRVA_B(35 downto 0)                       := SRVA_B_UNBOUND(35 downto 0);
      elsif (SRVAL_B'length < 36) then
        SRVA_B(SRVAL_B'length-1 downto 0)         := To_StdLogicVector(SRVAL_B );
      elsif (SRVAL_B'length = 36) then
        SRVA_B(SRVAL_B'length-1 downto 0)         := To_StdLogicVector(SRVAL_B );
      end if;

      if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then
        wr_mode_a := "00";
      elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then
        wr_mode_a := "01";
      elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then
        wr_mode_a := "10";
      else
        GenericValueCheckMessage
          ( HeaderMsg            => " Attribute Syntax Error : ",
            GenericName          => " WRITE_MODE_A ",
            EntityName           => "/RAMB16BWER",
            GenericValue         => WRITE_MODE_A,
            Unit                 => "",
            ExpectedValueMsg     => " The Legal values for this attribute are ",
            ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
            TailMsg              => "",
            MsgSeverity          => error
            );
      end if;

      if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then
        wr_mode_b := "00";
      elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then
        wr_mode_b := "01";
      elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then
        wr_mode_b := "10";
      else
        GenericValueCheckMessage
          ( HeaderMsg            => " Attribute Syntax Error : ",
            GenericName          => " WRITE_MODE_B ",
            EntityName           => "/RAMB16BWER",
            GenericValue         => WRITE_MODE_B,
            Unit                 => "",
            ExpectedValueMsg     => " The Legal values for this attribute are ",
            ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ",
            TailMsg              => "",
            MsgSeverity          => error
            );
      end if;

      if((SIM_COLLISION_CHECK = "ALL") or (SIM_COLLISION_CHECK = "all")) then
          SimCollisionCheck_var := 3;
      elsif((SIM_COLLISION_CHECK = "NONE") or (SIM_COLLISION_CHECK = "none")) then
          SimCollisionCheck_var := 0;
      elsif((SIM_COLLISION_CHECK = "WARNING_ONLY") or (SIM_COLLISION_CHECK = "warning_only")) then
          SimCollisionCheck_var := 1;
      elsif((SIM_COLLISION_CHECK = "GENERATE_X_ONLY") or (SIM_COLLISION_CHECK = "generate_x_only")) then
          SimCollisionCheck_var := 2;
     else
        GenericValueCheckMessage
         ( HeaderMsg            => " Attribute Syntax Error : ",
           GenericName          => " SIM_COLLISION_CHECK ",
           EntityName           => "/RAMB16BWER",
           GenericValue         => SIM_COLLISION_CHECK,
           Unit                 => "",
           ExpectedValueMsg     => " The Legal values for this attribute are ",
           ExpectedGenericValue => " ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY ",
           TailMsg              => "",
           MsgSeverity          => error
           );
     end if;


      wait until (GSR_CLKA_dly = '1' or GSR_CLKB_dly = '1' or ((CLKA_dly = '0' or CLKA_dly = '1') or (CLKB_dly = '0' or CLKB_dly = '1')));
---################################################################################
        DOA_zd(DOAW_1 downto 0) := INI_A(DOAW_1 downto 0);
        DOB_zd(DOBW_1 downto 0) := INI_B(DOBW_1 downto 0);

        if(DOPAW_1 /= -1) then
           DOPA_zd(DOPAW_1 downto 0) := INI_A((DOPAW_1 + DOAW) downto DOAW);
        end if;

        if(DOPBW_1 /= -1) then
           DOPB_zd(DOPBW_1 downto 0) := INI_B((DOPBW_1 + DOBW) downto DOBW);
        end if;

----- Port A
--        DOA <= DOA_zd;
--        if(DOPAW_1 /= -1) then
--           DOPA <= DOPA_zd;
--        end if;

----- Port B
--        DOB <= DOB_zd;
--        if(DOPBW_1 /= -1) then
--           DOPB <= DOPB_zd;
--        end if;

      data_widths.diaw  := DIAW; 
      data_widths.dipaw := DIPAW; 
      data_widths.doaw  := DOAW; 
      data_widths.dopaw := DOPAW; 

      data_widths.dibw  := DIBW; 
      data_widths.dipbw := DIPBW; 
      data_widths.dobw  := DOBW; 
      data_widths.dopbw := DOPBW; 

      FIRST_TIME  := false;
    end if;
----------------  END FIRST_TIME

--    addra_in_14 := ADDRA_dly(14);

--    if (CLKA_dly'event) then
    if (rising_edge(CLKA_dly)) then
      ENA_dly_sampled   := ENA_dly;
      RSTA_dly_sampled  := RSTA_dly;
      WEA_dly_sampled   := WEA_dly;
      ADDRA_dly_sampled := ADDRA_dly;
    end if;

-------------------------------------------------------------

--    addrb_in_14 := ADDRB_dly(14);

--    if (CLKB_dly'event) then
    if (rising_edge(CLKB_dly)) then
      ENB_dly_sampled   := ENB_dly;
      RSTB_dly_sampled  := RSTB_dly;
      WEB_dly_sampled   := WEB_dly;
      ADDRB_dly_sampled := ADDRB_dly;
    end if;



--------------------------------    A    ----------------------------------------
        tmp_zero_write_a  := (addra_dly_sampled(13 downto 0) and zero_write_a);
        ADDRESS_WRITE_A := SLV_TO_INT(tmp_zero_write_a);

        tmp_zero_read_a  := (addra_dly_sampled(13 downto 0) and zero_read_a);
        ADDRESS_READ_A  := SLV_TO_INT(tmp_zero_read_a);

        tmp_zero_parity_write_a(10 downto 0) := addra_dly_sampled( 13 downto 3) and zero_parity_write_a;
        ADDRESS_PARITY_WRITE_A := SLV_TO_INT(tmp_zero_parity_write_a);

        tmp_zero_parity_read_a(10 downto 0) := addra_dly_sampled( 13 downto 3) and zero_parity_read_a;
        ADDRESS_PARITY_READ_A := SLV_TO_INT(tmp_zero_parity_read_a);
--------------------------------    B    ----------------------------------------
        tmp_zero_write_b  := (addrb_dly_sampled(13 downto 0) and zero_write_b);
        ADDRESS_WRITE_B := SLV_TO_INT(tmp_zero_write_b);

        tmp_zero_read_b  := (addrb_dly_sampled(13 downto 0) and zero_read_b);
        ADDRESS_READ_B  := SLV_TO_INT(tmp_zero_read_b);

        tmp_zero_parity_write_b(10 downto 0) := addrb_dly_sampled( 13 downto 3) and zero_parity_write_b;
        ADDRESS_PARITY_WRITE_B := SLV_TO_INT(tmp_zero_parity_write_b);

        tmp_zero_parity_read_b(10 downto 0) := addrb_dly_sampled( 13 downto 3) and zero_parity_read_b;
        ADDRESS_PARITY_READ_B := SLV_TO_INT(tmp_zero_parity_read_b);


--    VALID_ADDRA           := ADDR_IS_VALID(addra_dly_sampled);
--    if (VALID_ADDRA) then
--    end if;

--    VALID_ADDRB           := ADDR_IS_VALID(addrb_dly_sampled);
--    if (VALID_ADDRB) then
--    end if;

--  DOA_INDEX /  DOPA_INDEX

    if(DIAW <= DOAW) then
       case DIAW is
          when 1 =>
             case DOAW is
                when 1  => DOA_INDEX := 0;
                when 2  => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(0 downto 0));
                when 4  => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(1 downto 0));
                when 8  => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(2 downto 0));
                when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(3 downto 0));
                when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(4 downto 0));
                when others => null;
             end case;

          when 2 =>
             case DOAW is
                when 2  => DOA_INDEX := 0;
                when 4  => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(1 downto 1));
                when 8  => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(2 downto 1));
                when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(3 downto 1));
                when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(4 downto 1));
                when others => null;
             end case;

          when 4 =>
             case DOAW is
                when 4  => DOA_INDEX := 0;
                when 8  => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(2 downto 2));
                when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(3 downto 2));
                when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(4 downto 2));
                when others => null;
             end case;

          when 8 =>
             case DOAW is
                when 8  => DOA_INDEX := 0;
                           DOPA_INDEX := 0;
                when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(3 downto 3));
                           DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_write_a(0 downto 0));
                when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(4 downto 3));
                           DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_write_a(1 downto 0));
                when others => null;
             end case;

          when 16 =>
             case DOAW is
                when 16 => DOA_INDEX := 0;
                           DOPA_INDEX := 0;
                when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(4 downto 4));
                           DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_write_a(1 downto 1));
                when others => null;
             end case;

          when 32 =>
             case DOAW is
                when 32 => DOA_INDEX := 0;
                           DOPA_INDEX := 0;
                when others => null;
             end case;
       
          when others => null;
       end case;

    elsif(DIAW > DOAW) then
       case DOAW is
          when 1 =>
             case DIAW is
                when 2  => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(0 downto 0));
                when 4  => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(1 downto 0));
                when 8  => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(2 downto 0));
                when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(3 downto 0));
                when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(4 downto 0));
                when others => null;
             end case;
          when 2 =>
             case DIAW is
                when 4  => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(1 downto 1));
                when 8  => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(2 downto 1));
                when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(3 downto 1));
                when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(4 downto 1));
                when others => null;
             end case;

          when 4 =>
             case DIAW is
                when 8  => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(2 downto 2));
                when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(3 downto 2));
                when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(4 downto 2));
                when others => null;
             end case;
          when 8 =>
             case DIAW is
                when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(3 downto 3));
                           DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_read_a(0 downto 0));
                when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(4 downto 3));
                           DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 0));
                when others => null;
             end case;

          when 16 =>
             case DIAW is
                when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(4 downto 4));
                           DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 1));
                when others => null;
             end case;

          when others => null;
       end case;
    end if;

--  DOB_INDEX /  DOPB_INDEX

    if(DIBW <= DOBW) then
       case DIBW is
          when 1 =>
             case DOBW is
                when 1  => DOB_INDEX := 0;
                when 2  => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(0 downto 0));
                when 4  => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(1 downto 0));
                when 8  => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(2 downto 0));
                when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(3 downto 0));
                when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(4 downto 0));
                when others => null;
             end case;

          when 2 =>
             case DOBW is
                when 2  => DOB_INDEX := 0;
                when 4  => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(1 downto 1));
                when 8  => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(2 downto 1));
                when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(3 downto 1));
                when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(4 downto 1));
                when others => null;
             end case;

          when 4 =>
             case DOBW is
                when 4  => DOB_INDEX := 0;
                when 8  => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(2 downto 2));
                when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(3 downto 2));
                when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(4 downto 2));
                when others => null;
             end case;

          when 8 =>
             case DOBW is
                when 8  => DOB_INDEX := 0;
                           DOPB_INDEX := 0;
                when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(3 downto 3));
                           DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_write_b(0 downto 0));
                when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(4 downto 3));
                           DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_write_b(1 downto 0));
                when others => null;
             end case;

          when 16 =>
             case DOBW is
                when 16 => DOB_INDEX := 0;
                           DOPB_INDEX := 0;
                when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(4 downto 4));
                           DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_write_b(1 downto 1));
                when others => null;
             end case;

          when 32 =>
             case DOBW is
                when 32 => DOB_INDEX := 0;
                           DOPB_INDEX := 0;
                when others => null;
             end case;
       
          when others => null;
       end case;

    elsif(DIBW > DOBW) then
       case DOBW is
          when 1 =>
             case DIBW is
                when 2  => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(0 downto 0));
                when 4  => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(1 downto 0));
                when 8  => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(2 downto 0));
                when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(3 downto 0));
                when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(4 downto 0));
                when others => null;
             end case;
          when 2 =>
             case DIBW is
                when 4  => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(1 downto 1));
                when 8  => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(2 downto 1));
                when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(3 downto 1));
                when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(4 downto 1));
                when others => null;
             end case;

          when 4 =>
             case DIBW is
                when 8  => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(2 downto 2));
                when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(3 downto 2));
                when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(4 downto 2));
                when others => null;
             end case;
          when 8 =>
             case DIBW is
                when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(3 downto 3));
                           DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_read_b(0 downto 0));
                when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(4 downto 3));
                           DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 0));
                when others => null;
             end case;

          when 16 =>
             case DIBW is
                when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(4 downto 4));
                           DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 1));
                when others => null;
             end case;

          when others => null;
       end case;
    end if;



----- ######################################################################################################

        if(rising_edge(CLKA_dly)) then
           CLKA_time := now;
        end if;

        if(rising_edge(CLKB_dly)) then
           CLKB_time := now;
        end if;


----- ######################################################################################################
------------------------------------------------------------------------                       
------------ Port A ----------------------------------------------------
------------------------------------------------------------------------                       
    if(GSR_CLKA_dly = '1') then
       DOA_zd(DOAW_1 downto 0) := INI_A(DOAW_1 downto 0);
       if(DOPAW_1 /= -1) then
         DOPA_zd(DOPAW_1 downto 0) := INI_A((DOPAW_1 + DOAW) downto DOAW);
       end if;

-- CR 422403
    elsif((RSTA_dly = '1') and (rst_async_flag = '1') and (ena_dly_sampled = '1')) then
       DOA_zd(DOAW_1 downto 0) := SRVA_A(DOAW_1 downto 0);
       DOA_clsn_zero := (others => '0');
       DOA_clsn := (others => '0');
       if(DOPAW_1 /= -1) then
          DOPA_zd(DOPAW_1 downto 0) := SRVA_A((DOPAW_1 + DOAW) downto DOAW);
          DOPA_clsn_zero := (others => '0');
          DOPA_clsn := (others => '0');
       end if;
    elsif(CLKA_dly'event AND CLKA_dly'last_value = '0') then

        if (ena_dly_sampled = '1') then
            if (RSTA_dly_sampled = '1') then
                   DOA_zd(DOAW_1 downto 0) := SRVA_A(DOAW_1 downto 0);
                   DOA_clsn_zero := (others => '0');
                   DOA_clsn := (others => '0');
                   if(DOPAW_1 /= -1) then
                      DOPA_zd(DOPAW_1 downto 0) := SRVA_A((DOPAW_1 + DOAW) downto DOAW);
                      DOPA_clsn_zero := (others => '0');
                      DOPA_clsn := (others => '0');
                   end if;
            else
-----------------------  Start COLLISION A ------------------------------

        if(SimCollisionCheck_var /= 0) then
           DOA_clsn_sav          := DOA_clsn;
           DOPA_clsn_sav         := DOPA_clsn;

           DOA_clsn              := (others => '0');
           DOPA_clsn             := (others => '0');
           clsn_xbufs.DO1_clsn   := (others => '0');
           clsn_xbufs.DOP1_clsn  := (others => '0');
           clsn_xbufs.MEM1_clsn  := (others => '0');
           clsn_xbufs.MEMP1_clsn := (others => '0');

           clsn_xbufs.DO2_clsn   := (others => '0');
           clsn_xbufs.DOP2_clsn  := (others => '0');
           clsn_xbufs.MEM2_clsn  := (others => '0');
           clsn_xbufs.MEMP2_clsn := (others => '0');
        
           clsn_type.active_port := 1;
           addr_overlap := false;
           clsn_type.read_write  := false;
           clsn_type.write_read  := false;
           clsn_type.write_write := false;

--           CLKA_time := now;

           ClkCollisionCheck(
              violation => collision_clka_clkb,
              CheckEnabled => ((TO_X01(ena_dly_sampled) = '1') and (TO_X01(enb_dly_sampled) = '1')), 
              CLK1_time => CLKA_time,
              CLK2_time => CLKB_time,
              SETUP_All => SETUP_ALL,
              SETUP_READ_FIRST => SETUP_READ_FIRST
           );

           if(collision_clka_clkb /= 0) then
              QkAddrOverlapChk(
                addr_overlap => addr_overlap,
                data_widths  => data_widths,
                addra        => addra_dly_sampled,
                addrb        => addrb_dly_sampled
              );
           end if;
        
           if(addr_overlap) then
              PreProcessWe1We2(
                clsn_bufs     => clsn_xbufs,
                clsn_type     => clsn_type,
                memory        => MEM,
                di1           => dia_dly,
                di2           => dib_dly,
                dip1          => dipa_dly,
                dip2          => dipb_dly,
                addr1         => addra_dly_sampled,
                addr2         => addrb_dly_sampled,
                we1           => wea_dly_sampled,
                we2           => web_dly_sampled,
                zero_read_1   => zero_read_a,
                zero_readp_1  => zero_parity_read_a,
                zero_write_1  => zero_write_a,
                zero_writep_1 => zero_parity_write_a,
                zero_read_2   => zero_read_b,
                zero_readp_2  => zero_parity_read_b,
                zero_write_2  => zero_write_b,
                zero_writep_2 => zero_parity_write_b,
                wr_mode_1     => wr_mode_a,
                wr_mode_2     => wr_mode_b,
                violation     => collision_clka_clkb,
                DI1W          => DIAW,
                DIP1W         => DIPAW,
                DI2W          => DIBW,
                DIP2W         => DIPBW,
                DO1W          => DOAW,
                DOP1W         => DOPAW,
                DO2W          => DOBW,
                DOP2W         => DOPBW
              );
           end if;
           
           if(clsn_type.read_write or clsn_type.write_write or clsn_type.write_read) then
               
              if(clsn_type.write_write) then
                  collision_msg := Write_A_Write_B; 
                  msg_addr1 := tmp_zero_write_a; 
                  msg_addr2 := tmp_zero_write_b; 
              elsif(clsn_type.read_write) then
                  collision_msg :=  Read_A_Write_B; 
                  msg_addr1 := tmp_zero_read_a; 
                  msg_addr2 := tmp_zero_write_b; 
              elsif(clsn_type.write_read) then
                  collision_msg :=  Write_A_Read_B; 
--                  msg_addr1 := tmp_zero_write_a; 
--                  msg_addr2 := tmp_zero_read_b; 
                  msg_addr1 := tmp_zero_read_b;
                  msg_addr2 := tmp_zero_write_a;
              end if;

              if(SimCollisionCheck_var = 1) then
                 --- Message 
                 Memory_Collision_Msg_ramb16
                 (  collision_type => collision_msg,
                   EntityName => "RAMB16BWER",
                   InstanceName => RAMB16BWER'path_name,
                   address_1 => msg_addr1,
                   address_2 => msg_addr2
                 );

              DOA_clsn  := (others => '0');
              DOPA_clsn := (others => '0');
              DOA_clsn_sav  := DOA_clsn;
              DOPA_clsn_sav := DOPA_clsn;

              elsif(SimCollisionCheck_var = 2) then

                 DOA_clsn_read_index  := SLV_TO_INT(tmp_zero_read_a(4 downto 0));
                 DOB_clsn_read_index := SLV_TO_INT(tmp_zero_read_b(4 downto 0));
                 DOA_clsn(DOAW_1 downto 0) := clsn_xbufs.DO1_clsn((DOA_clsn_read_index+DOAW_1) downto DOA_clsn_read_index);
                 DOB_clsn(DOBW_1 downto 0) := clsn_xbufs.DO2_clsn((DOB_clsn_read_index+DOBW_1) downto DOB_clsn_read_index);
                 if(DOPAW_1 /= -1) then
                    DOPA_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 0));
                    DOPA_clsn(DOPAW_1 downto 0) := clsn_xbufs.DOP1_clsn((DOPA_clsn_read_index+DOPAW_1) downto DOPA_clsn_read_index);
                 end if;

                 if(DOPBW_1 /= -1) then
                    DOPB_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 0));
                    DOPB_clsn(DOPBW_1 downto 0) := clsn_xbufs.DOP2_clsn((DOPB_clsn_read_index+DOPBW_1) downto DOPB_clsn_read_index);
                 end if;

                 if(wr_mode_a = "10") then
                    DOA_clsn(DOAW_1 downto 0) := DOA_clsn(DOAW_1 downto 0) xor DOA_clsn_sav(DOAW_1 downto 0);
                    if(DOPAW_1 /= -1) then
                       DOPA_clsn(DOPAW_1 downto 0) := DOPA_clsn(DOPAW_1 downto 0) xor DOPA_clsn_sav(DOPAW_1 downto 0);
                    end if;
                 end if;

                 if(wr_mode_b = "10") then
                    DOB_clsn(DOBW_1 downto 0) := DOB_clsn(DOBW_1 downto 0) xor DOB_clsn_sav(DOBW_1 downto 0);
                    if(DOPBW_1 /= -1) then
                       DOPB_clsn(DOPBW_1 downto 0) := DOPB_clsn(DOPBW_1 downto 0) xor DOPB_clsn_sav(DOPBW_1 downto 0);
                    end if;
                 end if;

              elsif(SimCollisionCheck_var = 3) then
                 --- Message 
                 Memory_Collision_Msg_ramb16
                 (  collision_type => collision_msg,
                   EntityName => "RAMB16BWER",
                   InstanceName => RAMB16BWER'path_name,
                   address_1 => msg_addr1,
                   address_2 => msg_addr2
                 );

                 DOA_clsn_read_index := SLV_TO_INT(tmp_zero_read_a(4 downto 0));
                 DOB_clsn_read_index := SLV_TO_INT(tmp_zero_read_b(4 downto 0));
                 DOA_clsn(DOAW_1 downto 0) := clsn_xbufs.DO1_clsn((DOA_clsn_read_index+DOAW_1) downto DOA_clsn_read_index);
                 DOB_clsn(DOBW_1 downto 0) := clsn_xbufs.DO2_clsn((DOB_clsn_read_index+DOBW_1) downto DOB_clsn_read_index);
                 if(DOPAW_1 /= -1) then
                    DOPA_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 0));
                    DOPA_clsn(DOPAW_1 downto 0) := clsn_xbufs.DOP1_clsn((DOPA_clsn_read_index+DOPAW_1) downto DOPA_clsn_read_index);
                 end if;

                 if(DOPBW_1 /= -1) then
                    DOPB_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 0));
                    DOPB_clsn(DOPBW_1 downto 0) := clsn_xbufs.DOP2_clsn((DOPB_clsn_read_index+DOPBW_1) downto DOPB_clsn_read_index);
                 end if;

                 if(wr_mode_a = "10") then
                    DOA_clsn(DOAW_1 downto 0) := DOA_clsn(DOAW_1 downto 0) xor DOA_clsn_sav(DOAW_1 downto 0);
                    if(DOPAW_1 /= -1) then
                       DOPA_clsn(DOPAW_1 downto 0) := DOPA_clsn(DOPAW_1 downto 0) xor DOPA_clsn_sav(DOPAW_1 downto 0);
                    end if;
                 end if;

                 if(wr_mode_b = "10") then
                    DOB_clsn(DOBW_1 downto 0) := DOB_clsn(DOBW_1 downto 0) xor DOB_clsn_sav(DOBW_1 downto 0);
                    if(DOPBW_1 /= -1) then
                       DOPB_clsn(DOPBW_1 downto 0) := DOPB_clsn(DOPBW_1 downto 0) xor DOPB_clsn_sav(DOPBW_1 downto 0);
                    end if;
                 end if;


              end if;

           end if;

           DOA_clsn_zero  := DOA_clsn;
           DOPA_clsn_zero := DOPA_clsn;
           if(RSTB_dly_sampled = '0') then
              DOB_clsn_zero  := DOB_clsn;
              DOPB_clsn_zero := DOPB_clsn;
           end if;

        end if;

----------------  END COLLISION A ------------------------------
            if  (wr_mode_a = "00") then

               case DIAW is
               ---------
               when 1|2|4|8 =>
               ---------
                  tmp_we(1 downto 0) := addra_dly_sampled( 4 downto 3);
                  wea_index := SLV_TO_INT(tmp_we);
                  if(wea_dly_sampled(wea_index) = '1') then
                     if(DOAW > DIAW) then
                        DOA_zd_buf(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto  ADDRESS_READ_A);
                        DOA_zd_buf(((DOA_INDEX *DIAW) + DIAW_1) downto (DOA_INDEX *DIAW)) := DIA_dly(DIAW_1 downto 0);
                        DOA_zd(DOAW_1 downto 0) := DOA_zd_buf(DOAW_1 downto 0);
                              
                        if(DOPAW_1 /= -1) then
                          DOPA_zd_buf(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto  (16384 + ADDRESS_PARITY_READ_A));
                          DOPA_zd_buf(((DOPA_INDEX *DIPAW) + DIPAW_1) downto (DOPA_INDEX *DIPAW)) := DIPA_dly(DIPAW_1 downto 0);
                          DOPA_zd(DOPAW_1 downto 0) := DOPA_zd_buf(DOPAW_1 downto 0);
                        end if;
                     elsif(DOAW <= DIAW) then
--FP                        DOA_zd(DOAW_1 downto 0)   := DIA_dly(DOAW_1 downto 0);
                        DOA_zd(DOAW_1 downto 0)   := DIA_dly((((DOA_INDEX)*DOAW)+ DOAW_1) downto ((DOA_INDEX)*DOAW));
                        if(DOPAW_1 /= -1) then
                           DOPA_zd(DOPAW_1 downto 0)   := DIPA_dly(DOPAW_1 downto 0);
                        end if;
                     end if;
                  elsif(wea_dly_sampled(wea_index) = '0') then
                     DOA_zd(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto (ADDRESS_READ_A));
                     if(DOPAW_1 /= -1) then
                        DOPA_zd(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto (16384 + ADDRESS_PARITY_READ_A));
                     end if;
                  end if;
                     
               ---------
               when 16 =>
               ---------
                  if(DOAW > DIAW) then
                     DOA_zd_buf(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto  ADDRESS_READ_A);
                     DOPA_zd_buf(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto  (16384 + ADDRESS_PARITY_READ_A));
                     
-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's    
                     
                     xout_we_seg1(1) := addra_dly_sampled(4);
                     xout_we_seg1(0) := '0';
                     xout_we_seg2(1) := addra_dly_sampled(4);
                     xout_we_seg2(0) := '1';

                     if(wea_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= wea_dly_sampled(SLV_TO_INT(xout_we_seg2))) then 
                        DOA_zd_buf(DOAW_1 downto 0) := (others => 'X');
                        DOPA_zd_buf(DOPAW_1 downto 0) := (others => 'X');
                     else
                        tmp_we(1) := addra_dly_sampled(4);
                        tmp_we(0) := '0';
                        wea_index := SLV_TO_INT(tmp_we);
                        if(wea_dly_sampled(wea_index) = '1') then
                           DOA_zd_buf(((DOA_INDEX *DIAW) + (DIAW/2 - 1)) downto (DOA_INDEX *DIAW)) := DIA_dly((DIAW/2 - 1) downto 0);
                           DOPA_zd_buf(((DOPA_INDEX *DIPAW) + (DIPAW/2 - 1)) downto (DOPA_INDEX *DIPAW)) := DIPA_dly((DIPAW/2 - 1) downto 0);
                        end if;

                        tmp_we(1) := addra_dly_sampled(4);
                        tmp_we(0) := '1';
                        wea_index := SLV_TO_INT(tmp_we);
                        if(wea_dly_sampled(wea_index) = '1') then
                          DOA_zd_buf(((DOA_INDEX *DIAW) + DIAW_1) downto ((DOA_INDEX *DIAW) + DIAW/2 )) := DIA_dly(DIAW_1 downto DIAW/2);
                          DOPA_zd_buf(((DOPA_INDEX *DIPAW) + DIPAW_1) downto ((DOPA_INDEX *DIPAW) + DIPAW/2 )) := DIPA_dly(DIPAW_1 downto DIPAW/2);
                        end if;

                     end if;

                     DOA_zd(DOAW_1 downto 0)   := DOA_zd_buf(DOAW_1 downto 0);
                     DOPA_zd(DOPAW_1 downto 0) := DOPA_zd_buf(DOPAW_1 downto 0);

                  end if;

-------------------
                  if(DOAW <= DIAW) then
                     DOA_zd_buf(DIAW_1 downto 0) := MEM((ADDRESS_WRITE_A + DIAW_1) downto  ADDRESS_WRITE_A);
                     if(DOPAW_1 /= -1) then
                       DOPA_zd_buf(DIPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto  (16384 + ADDRESS_PARITY_WRITE_A));
                     end if;
-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's    
                     
                     xout_we_seg1(1) := addra_dly_sampled(4);
                     xout_we_seg1(0) := '0';
                     xout_we_seg2(1) := addra_dly_sampled(4);
                     xout_we_seg2(0) := '1';

                     tmp_we(1) := addra_dly_sampled(4);
                     tmp_we(0) := '0';
                     wea_index := SLV_TO_INT(tmp_we);
                     if(wea_dly_sampled(wea_index) = '1') then
                        DOA_zd_buf((DIAW/2 - 1) downto 0)   := DIA_dly((DIAW/2 -1 ) downto 0);
                        if(DOPAW_1 /= -1) then
                           DOPA_zd_buf((DIPAW/2 - 1) downto 0)   := DIPA_dly((DIPAW/2 -1 ) downto 0);
                        end if;
                     elsif(wea_dly_sampled(wea_index) = '0') then
                        if(wea_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= wea_dly_sampled(SLV_TO_INT(xout_we_seg2))) then
                           DOA_zd_buf((DIAW/2 - 1) downto 0)   := (others => 'X');
                           if(DOPAW_1 /= -1) then
                              DOPA_zd_buf((DIPAW/2 - 1) downto 0)   := (others => 'X');
                           end if;
                        end if;
                     end if;

                     tmp_we(1) := addra_dly_sampled(4);
                     tmp_we(0) := '1';
                     wea_index := SLV_TO_INT(tmp_we);
                     if(wea_dly_sampled(wea_index) = '1') then
                        DOA_zd_buf(DIAW_1 downto DIAW/2 )   := DIA_dly(DIAW_1 downto DIAW/2);
                        if(DOPAW_1 /= -1) then
                           DOPA_zd_buf(DIPAW_1 downto DIPAW/2 )   := DIPA_dly(DIPAW_1 downto DIPAW/2);
                        end if;
                     elsif(wea_dly_sampled(wea_index) = '0') then
                        if(wea_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= wea_dly_sampled(SLV_TO_INT(xout_we_seg2))) then
                           DOA_zd_buf(DIAW_1 downto DIAW/2 )   := (others => 'X');
                           if(DOPAW_1 /= -1) then
                              DOPA_zd_buf(DIPAW_1 downto DIPAW/2 )   := (others => 'X');
                           end if;
                        end if;
                     end if;

-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's    
                     if((wea_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= wea_dly_sampled(SLV_TO_INT(xout_we_seg2))) and (DOAW /= DIAW)) then 
                        DOA_zd_buf(DIAW_1 downto 0) := (others => 'X');
                        DOPA_zd_buf(DIPAW_1 downto 0) := (others => 'X');
                     end if;

                     DOA_zd(DOAW_1 downto 0)   := DOA_zd_buf(((DOA_INDEX * DOAW) + DOAW_1) downto (DOA_INDEX * DOAW));
                     if(DOPAW_1 /= -1) then
                        DOPA_zd(DOPAW_1 downto 0) :=  DOPA_zd_buf(((DOPA_INDEX * DOPAW) + DOPAW_1) downto (DOPA_INDEX * DOPAW));
                     end if;

                  end if;

               ---------
               when 32 =>
               ---------

                  for i in 0 to 3 loop
                     if (wea_dly_sampled(i) = '1') then
                        DOA_zd_buf(((DIAW/4)*(i+1) - 1) downto (DIAW/4)*i)   := DIA_dly(((DIAW/4)*(i+1) - 1) downto (DIAW/4)*i);
                        if(DOPAW_1 /= -1) then
                           DOPA_zd_buf(((DIPAW/4)*(i+1) - 1) downto (DIPAW/4)*i) := DIPA_dly(((DIPAW/4)*(i+1) - 1) downto (DIPAW/4)*i);
                        end if;
                     elsif (wea_dly_sampled(i) = '0') then
-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's    
                        DOA_zd_buf(((DIAW/4)*(i+1) - 1) downto (DIAW/4)*i)   := (others => 'X');
                        if(DOPAW_1 /= -1) then
                           DOPA_zd_buf(((DIPAW/4)*(i+1) - 1) downto (DIPAW/4)*i) := (others => 'X');
                        end if;
                     end if;
                  end loop;

-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's    
                  if((wea_dly_sampled(0) = '0') and (wea_dly_sampled(1) = '0') and (wea_dly_sampled(2) = '0') and  (wea_dly_sampled(3) = '0')) then 
                     DOA_zd_buf(DIAW_1 downto 0) := MEM((ADDRESS_WRITE_A + DIAW_1) downto  ADDRESS_WRITE_A);
                     if(DOPAW_1 /= -1) then
                        DOPA_zd_buf(DIPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto  (16384 + ADDRESS_PARITY_WRITE_A));
                     end if;
                  
                  elsif(not((wea_dly_sampled(0) = '1') and (wea_dly_sampled(1) = '1') and (wea_dly_sampled(2) = '1') and  (wea_dly_sampled(3) = '1'))) then 
                      if(DOAW /= DIAW) then
                         DOA_zd_buf(DIAW_1 downto 0) := (others => 'X');
                         if(DOPAW_1 /= -1) then
                            DOPA_zd_buf(DIPAW_1 downto 0) := (others => 'X');
                         end if;
                      end if;
                  end if;

                  DOA_zd(DOAW_1 downto 0)   := DOA_zd_buf(((DOA_INDEX * DOAW) + DOAW_1) downto (DOA_INDEX * DOAW));
                  if(DOPAW_1 /= -1) then
                     DOPA_zd(DOPAW_1 downto 0) :=  DOPA_zd_buf(((DOPA_INDEX * DOPAW) + DOPAW_1) downto (DOPA_INDEX * DOPAW));
                  end if;

                  when others =>
                     null;
               end case;

            elsif(wr_mode_a = "01") then
              DOA_zd(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto (ADDRESS_READ_A));
              if(DOPAW_1 /= -1) then
                  DOPA_zd(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto (16384 + ADDRESS_PARITY_READ_A));
              end if;
            elsif(wr_mode_a = "10") then
              case DIAW is
                 when 1|2|4|8 =>
                    tmp_we(1 downto 0) := addra_dly_sampled( 4 downto 3);
                    wea_index := SLV_TO_INT(tmp_we);
                    if (wea_dly_sampled(wea_index) = '0') then
                       DOA_zd(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto (ADDRESS_READ_A));
                       if(DOPAW_1 /= -1) then
                           DOPA_zd(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto (16384 + ADDRESS_PARITY_READ_A));
                       end if;
                    end if;
                 ----------
                 when 16|32 =>
                 ----------
                    if ((wea_dly_sampled(0) = '0') and (wea_dly_sampled(1) = '0') and (wea_dly_sampled(2) = '0') and (wea_dly_sampled(3) = '0'))then
                       DOA_zd(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto (ADDRESS_READ_A));
                       if(DOPAW_1 /= -1) then
                           DOPA_zd(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto (16384 + ADDRESS_PARITY_READ_A));
                       end if;
                    end if;
                 ----------
                 when others =>
                 ----------
                    null;
               end case;
          end if;
          end if;
            end if; -- /* end ena_dly_sampled = '1' */
      end if;

------------------------------------------------------------------------                       
------------ Port B ----------------------------------------------------
------------------------------------------------------------------------                       
    if(GSR_CLKB_dly = '1') then
       DOB_zd(DOBW_1 downto 0) := INI_B(DOBW_1 downto 0);
       if(DOPBW_1 /= -1) then
         DOPB_zd(DOPBW_1 downto 0) := INI_B((DOPBW_1 + DOBW) downto DOBW);
       end if;

-- CR 422403
    elsif((RSTB_dly = '1') and (rst_async_flag = '1') and (enb_dly_sampled = '1')) then
       DOB_zd(DOBW_1 downto 0) := SRVA_B(DOBW_1 downto 0);
       DOB_clsn_zero := (others => '0');
       DOB_clsn := (others => '0');
       if(DOPBW_1 /= -1) then
          DOPB_zd(DOPBW_1 downto 0) := SRVA_B((DOPBW_1 + DOBW) downto DOBW);
          DOPB_clsn_zero := (others => '0');
          DOPB_clsn := (others => '0');
       end if;
    elsif(CLKB_dly'event AND CLKB_dly'last_value = '0') then
        if (enb_dly_sampled = '1') then
            if (RSTB_dly_sampled = '1') then
                   DOB_zd(DOBW_1 downto 0) := SRVA_B(DOBW_1 downto 0);
                   DOB_clsn_zero := (others => '0');
                   DOB_clsn := (others => '0');
                   if(DOPBW_1 /= -1) then
                      DOPB_zd(DOPBW_1 downto 0) := SRVA_B((DOPBW_1 + DOBW) downto DOBW);
                      DOPB_clsn_zero := (others => '0');
                      DOPB_clsn := (others => '0');
                   end if;
            else
-----------------------  Start COLLISION B ------------------------------
        if(SimCollisionCheck_var /= 0) then
           DOB_clsn_sav          := DOB_clsn;
           DOPB_clsn_sav         := DOPB_clsn;

           DOB_clsn              := (others => '0');
           DOPB_clsn             := (others => '0');
           clsn_xbufs.DO1_clsn   := (others => '0');
           clsn_xbufs.DOP1_clsn  := (others => '0');
           clsn_xbufs.MEM1_clsn  := (others => '0');
           clsn_xbufs.MEMP1_clsn := (others => '0');

           clsn_xbufs.DO2_clsn   := (others => '0');
           clsn_xbufs.DOP2_clsn  := (others => '0');
           clsn_xbufs.MEM2_clsn  := (others => '0');
           clsn_xbufs.MEMP2_clsn := (others => '0');
        
           clsn_type.active_port := 2;
           addr_overlap := false;
           clsn_type.read_write  := false;
           clsn_type.write_read  := false;
           clsn_type.write_write := false;

--           CLKB_time := now;

           ClkCollisionCheck(
              violation => collision_clka_clkb,
              CheckEnabled => ((TO_X01(ena_dly_sampled) = '1') and (TO_X01(enb_dly_sampled) = '1')), 
              CLK1_time => CLKB_time,
              CLK2_time => CLKA_time,
              SETUP_All => SETUP_ALL,
              SETUP_READ_FIRST => SETUP_READ_FIRST
           );

           if(collision_clka_clkb /= 0) then
              QkAddrOverlapChk(
                addr_overlap => addr_overlap,
                data_widths  => data_widths,
                addra        => addra_dly_sampled,
                addrb        => addrb_dly_sampled
              );
           end if;
        
           if(addr_overlap) then
              PreProcessWe1We2(
                clsn_bufs     => clsn_xbufs,
                clsn_type     => clsn_type,
                memory        => MEM,
                di1           => dib_dly,
                di2           => dia_dly,
                dip1          => dipb_dly,
                dip2          => dipa_dly,
                addr1         => addrb_dly_sampled,
                addr2         => addra_dly_sampled,
                we1           => web_dly_sampled,
                we2           => wea_dly_sampled,
                zero_read_1   => zero_read_b,
                zero_readp_1  => zero_parity_read_b,
                zero_write_1  => zero_write_b,
                zero_writep_1 => zero_parity_write_b,
                zero_read_2   => zero_read_a,
                zero_readp_2  => zero_parity_read_a,
                zero_write_2  => zero_write_a,
                zero_writep_2 => zero_parity_write_a,
                wr_mode_1     => wr_mode_b,
                wr_mode_2     => wr_mode_a,
                violation     => collision_clka_clkb,
                DI1W          => DIBW,
                DIP1W         => DIPBW,
                DI2W          => DIAW,
                DIP2W         => DIPAW,
                DO1W          => DOBW,
                DOP1W         => DOPBW,
                DO2W          => DOAW,
                DOP2W         => DOPAW
              );
           end if;
           
           if(clsn_type.read_write or clsn_type.write_write or clsn_type.write_read) then
               
              if(clsn_type.write_write) then
                  collision_msg := Write_B_Write_A; 
--                  msg_addr1 := tmp_zero_write_b; 
--                  msg_addr2 := tmp_zero_write_a; 
                  msg_addr1 := tmp_zero_write_a; 
                  msg_addr2 := tmp_zero_write_b; 
              elsif(clsn_type.read_write) then
                  collision_msg :=  Read_B_Write_A; 
                  msg_addr1 := tmp_zero_read_b; 
                  msg_addr2 := tmp_zero_write_a; 
              elsif(clsn_type.write_read) then
                  collision_msg :=  Write_B_Read_A; 
--                  msg_addr1 := tmp_zero_write_b; 
--                  msg_addr2 := tmp_zero_read_a; 
                  msg_addr1 := tmp_zero_read_a;
                  msg_addr2 := tmp_zero_write_b;
              end if;

              if(SimCollisionCheck_var = 1) then
                 --- Message 
                 Memory_Collision_Msg_ramb16
                 (  collision_type => collision_msg,
                   EntityName => "RAMB16BWER",
                   InstanceName => RAMB16BWER'path_name,
                   address_1 => msg_addr1,
                   address_2 => msg_addr2
                 );

              DOB_clsn  := (others => '0');
              DOPB_clsn := (others => '0');
              DOB_clsn_sav  := DOB_clsn;
              DOPB_clsn_sav := DOPB_clsn;

              elsif(SimCollisionCheck_var = 2) then

                 DOB_clsn_read_index := SLV_TO_INT(tmp_zero_read_b(4 downto 0));
                 DOA_clsn_read_index := SLV_TO_INT(tmp_zero_read_a(4 downto 0));

                 DOB_clsn(DOBW_1 downto 0) := clsn_xbufs.DO1_clsn((DOB_clsn_read_index+DOBW_1) downto DOB_clsn_read_index);
                 DOA_clsn(DOAW_1 downto 0) := clsn_xbufs.DO2_clsn((DOA_clsn_read_index+DOAW_1) downto DOA_clsn_read_index);

                 if(DOPBW_1 /= -1) then
                    DOPB_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 0));
                    DOPB_clsn(DOPBW_1 downto 0) := clsn_xbufs.DOP1_clsn((DOPB_clsn_read_index+DOPBW_1) downto DOPB_clsn_read_index);
                 end if;

                 if(DOPAW_1 /= -1) then
                    DOPA_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 0));
                    DOPA_clsn(DOPAW_1 downto 0) := clsn_xbufs.DOP2_clsn((DOPA_clsn_read_index+DOPAW_1) downto DOPA_clsn_read_index);
                 end if;

                 if(wr_mode_b = "10") then
                    DOB_clsn(DOBW_1 downto 0) := DOB_clsn(DOBW_1 downto 0) xor DOB_clsn_sav(DOBW_1 downto 0);
                    if(DOPBW_1 /= -1) then
                       DOPB_clsn(DOPBW_1 downto 0) := DOPB_clsn(DOPBW_1 downto 0) xor DOPB_clsn_sav(DOPBW_1 downto 0);
                    end if;
                 end if;

                 if(wr_mode_a = "10") then
                    DOA_clsn(DOAW_1 downto 0) := DOA_clsn(DOAW_1 downto 0) xor DOA_clsn_sav(DOAW_1 downto 0);
                    if(DOPAW_1 /= -1) then
                       DOPA_clsn(DOPAW_1 downto 0) := DOPA_clsn(DOPAW_1 downto 0) xor DOPA_clsn_sav(DOPAW_1 downto 0);
                    end if;
                 end if;


              elsif(SimCollisionCheck_var = 3) then
                 --- Message 
                 Memory_Collision_Msg_ramb16
                 (  collision_type => collision_msg,
                   EntityName => "RAMB16BWER",
                   InstanceName => RAMB16BWER'path_name,
                   address_1 => msg_addr1,
                   address_2 => msg_addr2
                 );


                 DOB_clsn_read_index := SLV_TO_INT(tmp_zero_read_b(4 downto 0));
                 DOA_clsn_read_index := SLV_TO_INT(tmp_zero_read_a(4 downto 0));

                 DOB_clsn(DOBW_1 downto 0) := clsn_xbufs.DO1_clsn((DOB_clsn_read_index+DOBW_1) downto DOB_clsn_read_index);
                 DOA_clsn(DOAW_1 downto 0) := clsn_xbufs.DO2_clsn((DOA_clsn_read_index+DOAW_1) downto DOA_clsn_read_index);

                 if(DOPBW_1 /= -1) then
                    DOPB_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 0));
                    DOPB_clsn(DOPBW_1 downto 0) := clsn_xbufs.DOP1_clsn((DOPB_clsn_read_index+DOPBW_1) downto DOPB_clsn_read_index);
                 end if;

                 if(DOPAW_1 /= -1) then
                    DOPA_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 0));
                    DOPA_clsn(DOPAW_1 downto 0) := clsn_xbufs.DOP2_clsn((DOPA_clsn_read_index+DOPAW_1) downto DOPA_clsn_read_index);
                 end if;

                 if(wr_mode_b = "10") then
                    DOB_clsn(DOBW_1 downto 0) := DOB_clsn(DOBW_1 downto 0) xor DOB_clsn_sav(DOBW_1 downto 0);
                    if(DOPBW_1 /= -1) then
                       DOPB_clsn(DOPBW_1 downto 0) := DOPB_clsn(DOPBW_1 downto 0) xor DOPB_clsn_sav(DOPBW_1 downto 0);
                    end if;
                 end if;

                 if(wr_mode_a = "10") then
                    DOA_clsn(DOAW_1 downto 0) := DOA_clsn(DOAW_1 downto 0) xor DOA_clsn_sav(DOAW_1 downto 0);
                    if(DOPAW_1 /= -1) then
                       DOPA_clsn(DOPAW_1 downto 0) := DOPA_clsn(DOPAW_1 downto 0) xor DOPA_clsn_sav(DOPAW_1 downto 0);
                    end if;
                 end if;

              end if;

           end if;

           DOB_clsn_zero  := DOB_clsn;
           DOPB_clsn_zero := DOPB_clsn;
           if(RSTA_dly_sampled = '0') then
             DOA_clsn_zero  := DOA_clsn;
             DOPA_clsn_zero := DOPA_clsn;
           end if;

        end if;

----------------  END COLLISION B ------------------------------
            if (wr_mode_b = "00") then

               case DIBW is
               ---------
               when 1|2|4|8 =>
               ---------
                  tmp_we(1 downto 0) := addrb_dly_sampled( 4 downto 3);
                  web_index := SLV_TO_INT(tmp_we);
                  if(web_dly_sampled(web_index) = '1') then
                     if(DOBW > DIBW) then
                        DOB_zd_buf(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto  ADDRESS_READ_B);
                        DOB_zd_buf(((DOB_INDEX *DIBW) + DIBW_1) downto (DOB_INDEX *DIBW)) := DIB_dly(DIBW_1 downto 0);
                        DOB_zd(DOBW_1 downto 0) := DOB_zd_buf(DOBW_1 downto 0);
                              
                        if(DOPBW_1 /= -1) then
                          DOPB_zd_buf(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto  (16384 + ADDRESS_PARITY_READ_B));
                          DOPB_zd_buf(((DOPB_INDEX *DIPBW) + DIPBW_1) downto (DOPB_INDEX *DIPBW)) := DIPB_dly(DIPBW_1 downto 0);
                          DOPB_zd(DOPBW_1 downto 0) := DOPB_zd_buf(DOPBW_1 downto 0);
                        end if;
                     elsif(DOBW <= DIBW) then
--FP                        DOB_zd(DOBW_1 downto 0)   := DIB_dly(DOBW_1 downto 0);
                        DOB_zd(DOBW_1 downto 0)   := DIB_dly((((DOB_INDEX)*DOBW)+ DOBW_1) downto ((DOB_INDEX)*DOBW));
                        if(DOPBW_1 /= -1) then
                           DOPB_zd(DOPBW_1 downto 0)   := DIPB_dly(DOPBW_1 downto 0);
                        end if;
                     end if;
                  elsif(web_dly_sampled(web_index) = '0') then
                     DOB_zd(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto (ADDRESS_READ_B));
                     if(DOPBW_1 /= -1) then
                        DOPB_zd(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto (16384 + ADDRESS_PARITY_READ_B));
                     end if;
                  end if;
                     
               ---------
               when 16 =>
               ---------
                  if(DOBW > DIBW) then
                     DOB_zd_buf(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto  ADDRESS_READ_B);
                     DOPB_zd_buf(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto  (16384 + ADDRESS_PARITY_READ_B));
-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's  or all 1's

                     xout_we_seg1(1) := addrb_dly_sampled(4);
                     xout_we_seg1(0) := '0';
                     xout_we_seg2(1) := addrb_dly_sampled(4);
                     xout_we_seg2(0) := '1';

                     if(web_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= web_dly_sampled(SLV_TO_INT(xout_we_seg2))) then
                        DOB_zd_buf(DOBW_1 downto 0) := (others => 'X');
                        DOPB_zd_buf(DOPBW_1 downto 0) := (others => 'X');
                     else
                        tmp_we(1) := addrb_dly_sampled(4);
                        tmp_we(0) := '0';
                        web_index := SLV_TO_INT(tmp_we);
                        if(web_dly_sampled(web_index) = '1') then
                           DOB_zd_buf(((DOB_INDEX *DIBW) + (DIBW/2 - 1)) downto (DOB_INDEX *DIBW)) := DIB_dly((DIBW/2 - 1) downto 0);
                           DOPB_zd_buf(((DOPB_INDEX *DIPBW) + (DIPBW/2 - 1)) downto (DOPB_INDEX *DIPBW)) := DIPB_dly((DIPBW/2 - 1) downto 0);
                        end if;

                        tmp_we(1) := addrb_dly_sampled(4);
                        tmp_we(0) := '1';
                        web_index := SLV_TO_INT(tmp_we);
                        if(web_dly_sampled(web_index) = '1') then
                          DOB_zd_buf(((DOB_INDEX *DIBW) + DIBW_1) downto ((DOB_INDEX *DIBW) + DIBW/2 )) := DIB_dly(DIBW_1 downto DIBW/2);
                          DOPB_zd_buf(((DOPB_INDEX *DIPBW) + DIPBW_1) downto ((DOPB_INDEX *DIPBW) + DIPBW/2 )) := DIPB_dly(DIPBW_1 downto DIPBW/2);
                        end if;

                     end if;

                     DOB_zd(DOBW_1 downto 0)   := DOB_zd_buf(DOBW_1 downto 0);
                     DOPB_zd(DOPBW_1 downto 0) := DOPB_zd_buf(DOPBW_1 downto 0);

                  end if;

-------------------
                  if(DOBW <= DIBW) then
                     DOB_zd_buf(DIBW_1 downto 0) := MEM((ADDRESS_WRITE_B + DIBW_1) downto  ADDRESS_WRITE_B);
                     if(DOPBW_1 /= -1) then
                        DOPB_zd_buf(DIPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto  (16384 + ADDRESS_PARITY_WRITE_B));
                     end if;
-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's  or all 1's
                          
                     xout_we_seg1(1) := addrb_dly_sampled(4);
                     xout_we_seg1(0) := '0';
                     xout_we_seg2(1) := addrb_dly_sampled(4);
                     xout_we_seg2(0) := '1';

                     tmp_we(1) := addrb_dly_sampled(4);
                     tmp_we(0) := '0';
                     web_index := SLV_TO_INT(tmp_we);
                     if(web_dly_sampled(web_index) = '1') then
                        DOB_zd_buf((DIBW/2 - 1) downto 0)   := DIB_dly((DIBW/2 -1 ) downto 0);
                        if(DOPBW_1 /= -1) then
                           DOPB_zd_buf((DIPBW/2 - 1) downto 0)   := DIPB_dly((DIPBW/2 -1 ) downto 0);
                        end if;
                     elsif(web_dly_sampled(web_index) = '0') then
                        if(web_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= web_dly_sampled(SLV_TO_INT(xout_we_seg2))) then
                           DOB_zd_buf((DIBW/2 - 1) downto 0)   := (others => 'X');
                           if(DOPBW_1 /= -1) then
                              DOPB_zd_buf((DIPBW/2 - 1) downto 0)   := (others => 'X');
                           end if;
                        end if;
                     end if;

                     tmp_we(1) := addrb_dly_sampled(4);
                     tmp_we(0) := '1';
                     web_index := SLV_TO_INT(tmp_we);
                     if(web_dly_sampled(web_index) = '1') then
                        DOB_zd_buf(DIBW_1 downto DIBW/2 )   := DIB_dly(DIBW_1 downto DIBW/2);
                        if(DOPBW_1 /= -1) then
                           DOPB_zd_buf(DIPBW_1 downto DIPBW/2 )   := DIPB_dly(DIPBW_1 downto DIPBW/2);
                        end if;
                     elsif(web_dly_sampled(web_index) = '0') then
                        if(web_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= web_dly_sampled(SLV_TO_INT(xout_we_seg2))) then
                           DOB_zd_buf(DIBW_1 downto DIBW/2 )   := (others => 'X');
                           if(DOPBW_1 /= -1) then
                              DOPB_zd_buf(DIPBW_1 downto DIPBW/2 )   := (others => 'X');
                           end if;
                        end if;
                     end if;

-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's  or all 1's
                     if((web_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= web_dly_sampled(SLV_TO_INT(xout_we_seg2))) and (DOBW /= DIBW)) then
                        DOB_zd_buf(DIBW_1 downto 0) := (others => 'X');
                        DOPB_zd_buf(DIPBW_1 downto 0) := (others => 'X');
                     end if;

                     DOB_zd(DOBW_1 downto 0)   := DOB_zd_buf(((DOB_INDEX * DOBW) + DOBW_1) downto (DOB_INDEX * DOBW));
                     if(DOPBW_1 /= -1) then
                        DOPB_zd(DOPBW_1 downto 0) :=  DOPB_zd_buf(((DOPB_INDEX * DOPBW) + DOPBW_1) downto (DOPB_INDEX * DOPBW));
                     end if;

                  end if;

               ---------
               when 32 =>
               ---------
                  for i in 0 to 3 loop
                     if (web_dly_sampled(i) = '1') then
                        DOB_zd_buf(((DIBW/4)*(i+1) - 1) downto (DIBW/4)*i)   := DIB_dly(((DIBW/4)*(i+1) - 1) downto (DIBW/4)*i);
                        if(DOPBW_1 /= -1) then
                           DOPB_zd_buf(((DIPBW/4)*(i+1) - 1) downto (DIPBW/4)*i) := DIPB_dly(((DIPBW/4)*(i+1) - 1) downto (DIPBW/4)*i);
                        end if;
                     elsif (web_dly_sampled(i) = '0') then
-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's  or all 1's
                        DOB_zd_buf(((DIBW/4)*(i+1) - 1) downto (DIBW/4)*i)   := (others => 'X');
                        if(DOPBW_1 /= -1) then
                           DOPB_zd_buf(((DIPBW/4)*(i+1) - 1) downto (DIPBW/4)*i) := (others => 'X');
                        end if;
                     end if;
                  end loop;
-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's  or all 1's
                  if((web_dly_sampled(0) = '0') and (web_dly_sampled(1) = '0') and (web_dly_sampled(2) = '0') and  (web_dly_sampled(3) = '0')) then
                     DOB_zd_buf(DIBW_1 downto 0) := MEM((ADDRESS_WRITE_B + DIBW_1) downto  ADDRESS_WRITE_B);
                     if(DOPBW_1 /= -1) then
                        DOPB_zd_buf(DIPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto  (16384 + ADDRESS_PARITY_WRITE_B));
                     end if;
                  elsif(not((web_dly_sampled(0) = '1') and (web_dly_sampled(1) = '1') and (web_dly_sampled(2) = '1') and  (web_dly_sampled(3) = '1'))) then
                      if(DOBW /= DIBW) then
                         DOB_zd_buf(DIBW_1 downto 0) := (others => 'X');
                         if(DOPBW_1 /= -1) then
                            DOPB_zd_buf(DIPBW_1 downto 0) := (others => 'X');
                         end if;
                      end if;
                  end if;

                  DOB_zd(DOBW_1 downto 0)   := DOB_zd_buf(((DOB_INDEX * DOBW) + DOBW_1) downto (DOB_INDEX * DOBW));
                  if(DOPBW_1 /= -1) then
                     DOPB_zd(DOPBW_1 downto 0) :=  DOPB_zd_buf(((DOPB_INDEX * DOPBW) + DOPBW_1) downto (DOPB_INDEX * DOPBW));
                  end if;

                  when others =>
                     null;
               end case;

            elsif(wr_mode_b = "01") then
              DOB_zd(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto (ADDRESS_READ_B));
              if(DOPBW_1 /= -1) then
                  DOPB_zd(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto (16384 + ADDRESS_PARITY_READ_B));
              end if;
            elsif(wr_mode_b = "10") then
              case DIBW is
                 when 1|2|4|8 =>
                    tmp_we(1 downto 0) := addrb_dly_sampled( 4 downto 3);
                    web_index := SLV_TO_INT(tmp_we);
                    if (web_dly_sampled(web_index) = '0') then
                       DOB_zd(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto (ADDRESS_READ_B));
                       if(DOPBW_1 /= -1) then
                           DOPB_zd(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto (16384 + ADDRESS_PARITY_READ_B));
                       end if;
                    end if;
                 ----------
                 when 16|32 =>
                 ----------
                    if ((web_dly_sampled(0) = '0') and (web_dly_sampled(1) = '0') and (web_dly_sampled(2) = '0') and (web_dly_sampled(3) = '0'))then
                       DOB_zd(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto (ADDRESS_READ_B));
                       if(DOPBW_1 /= -1) then
                           DOPB_zd(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto (16384 + ADDRESS_PARITY_READ_B));
                       end if;
                    end if;
                 ----------
                 when others =>
                 ----------
                    null;
               end case;
          end if;
          end if;
            end if; -- /* end enb_dly_sampled = '1' */
      end if;

------------------------------------------------------------------------                       
------------ Port A  -- Memory Update ----------------------------------
------------------------------------------------------------------------                       

    if((GSR_CLKA_dly = '0') and rising_edge(CLKA_dly)) then
        if (ena_dly_sampled = '1') then
                case DIAW is
                  --------------
                  when 1|2|4|8 =>
                  --------------
                      tmp_we(1 downto 0) := addra_dly_sampled( 4 downto 3);
                      wea_index := SLV_TO_INT(tmp_we);
                      if (wea_dly_sampled(wea_index) = '1') then
                         if (VALID_ADDRA) then
                            MEM((ADDRESS_WRITE_A + DIAW_1) downto (ADDRESS_WRITE_A)) := DIA_dly(DIAW_1 downto 0);
                            if(DIPAW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto (16384 + ADDRESS_PARITY_WRITE_A)) := DIPA_dly(DIPAW_1 downto 0);
                            end if;
                         else
                          DOA_zd(DOAW_1 downto 0) := (others => 'X');
                          if(DOPAW_1 /= -1) then
                             DOPA_zd(DOPAW_1 downto 0) := (others => 'X');
                          end if;
                         end if; -- /* VAILD ADDRA */
                      end if; -- /*  wea_dly_sampled = '1' */ 

                  ---------
                  when 16 =>
                  ---------
                      tmp_we(1) := addra_dly_sampled(4);
                      tmp_we(0) := '0';
                      wea_index := SLV_TO_INT(tmp_we);
                      if (wea_dly_sampled(wea_index) = '1') then
                         if (VALID_ADDRA) then
                            MEM((ADDRESS_WRITE_A + DIAW/2 -1) downto (ADDRESS_WRITE_A)) := DIA_dly((DIAW/2 - 1) downto 0);
                            if(DIPAW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW/2 - 1) downto (16384 + ADDRESS_PARITY_WRITE_A)) := DIPA_dly((DIPAW/2 -1) downto 0);
                            end if;
                         end if; -- /* VAILD ADDRA */
                      end if; -- /*  wea_dly_sampled = '1' */ 

                      tmp_we(0) := '1';
                      wea_index := SLV_TO_INT(tmp_we);
                      if (wea_dly_sampled(wea_index) = '1') then
                         if (VALID_ADDRA) then
                            MEM((ADDRESS_WRITE_A + DIAW_1) downto (ADDRESS_WRITE_A + DIAW/2)) := DIA_dly(DIAW_1 downto DIAW/2);
                            if(DIPAW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto (16384 + ADDRESS_PARITY_WRITE_A + DIPAW/2)) := DIPA_dly(DIPAW_1 downto DIPAW/2);
                            end if;
                         end if; -- /* VAILD ADDRA */
                      end if; -- /*  wea_dly_sampled = '1' */ 

                  ---------
                  when 32 =>
                  ---------
                      wea_index := 0;
                      if (wea_dly_sampled(wea_index) = '1') then
                         if (VALID_ADDRA) then
                            MEM((ADDRESS_WRITE_A + (DIAW/4)*1 -1) downto (ADDRESS_WRITE_A)) := DIA_dly((((DIAW/4)*1) - 1) downto 0);
                            if(DIPAW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*1 - 1) downto (16384 + ADDRESS_PARITY_WRITE_A)) := DIPA_dly(((DIPAW/4)*1 -1) downto 0);
                            end if;
                         end if; -- /* VAILD ADDRA */
                      end if; -- /*  wea_dly_sampled = '1' */ 

                      wea_index := 1;
                      if (wea_dly_sampled(wea_index) = '1') then
                         if (VALID_ADDRA) then
                            MEM((ADDRESS_WRITE_A + (DIAW/4)*2 -1) downto (ADDRESS_WRITE_A + (DIAW/4)*1)) := DIA_dly((((DIAW/4)*2) - 1) downto (DIAW/4)*1);
                            if(DIPAW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*2 - 1) downto (16384 + ADDRESS_PARITY_WRITE_A  + (DIPAW/4)*1)) := DIPA_dly(((DIPAW/4)*2 -1) downto ((DIPAW/4)*1));
                            end if;
                         end if; -- /* VAILD ADDRA */
                      end if; -- /*  wea_dly_sampled = '1' */ 

                      wea_index := 2;
                      if (wea_dly_sampled(wea_index) = '1') then
                         if (VALID_ADDRA) then
                            MEM((ADDRESS_WRITE_A + (DIAW/4)*3 -1) downto (ADDRESS_WRITE_A + (DIAW/4)*2)) := DIA_dly((((DIAW/4)*3) - 1) downto (DIAW/4)*2);
                            if(DIPAW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*3 - 1) downto (16384 + ADDRESS_PARITY_WRITE_A  + (DIPAW/4)*2)) := DIPA_dly(((DIPAW/4)*3 -1) downto ((DIPAW/4)*2));
                            end if;
                         end if; -- /* VAILD ADDRA */
                      end if; -- /*  wea_dly_sampled = '1' */ 

                      wea_index := 3;
                      if (wea_dly_sampled(wea_index) = '1') then
                         if (VALID_ADDRA) then
                            MEM((ADDRESS_WRITE_A + (DIAW/4)*4 -1) downto (ADDRESS_WRITE_A + (DIAW/4)*3)) := DIA_dly((((DIAW/4)*4) - 1) downto (DIAW/4)*3);
                            if(DIPAW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*4 - 1) downto (16384 + ADDRESS_PARITY_WRITE_A  + (DIPAW/4)*3)) := DIPA_dly(((DIPAW/4)*4 -1) downto ((DIPAW/4)*3));
                            end if;
                         end if; -- /* VAILD ADDRA */
                      end if; -- /*  wea_dly_sampled = '1' */ 
                  when others =>
                     null;
                end case;

-----------------------  Start COLLISION MEMORY UPDATE A ------------------------------

        if(SimCollisionCheck_var /= 0) then
           if(clsn_type.write_write) then
              tmp_membuf := (others => '0');
              DOA_clsn_write_index := SLV_TO_INT(tmp_zero_write_a(4 downto 0));
              tmp_membuf(DIAW_1 downto 0) := MEM((ADDRESS_WRITE_A + DIAW_1) downto (ADDRESS_WRITE_A));
              MEM((ADDRESS_WRITE_A + DIAW_1) downto (ADDRESS_WRITE_A)) := tmp_membuf(DIAW_1 downto 0) xor clsn_xbufs.MEM1_clsn((DOA_clsn_write_index+DIAW_1) downto DOA_clsn_write_index);

             if((DIPAW_1 /= -1) and (DIPBW_1 /= -1)) then
                tmp_membuf := (others => '0');
                DOPA_clsn_write_index := SLV_TO_INT(tmp_zero_parity_write_a(1 downto 0));
                tmp_membuf(DIPAW_1 downto 0) :=  MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto (16384 + ADDRESS_PARITY_WRITE_A));
                MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto (16384 + ADDRESS_PARITY_WRITE_A)) := tmp_membuf(DIPAW_1 downto 0) xor clsn_xbufs.MEMP1_clsn((DOPA_clsn_write_index + DIPAW_1) downto DOPA_clsn_write_index);
              end if;
           end if;
        end if;
                
-----------------------  END COLLISION MEMORY UPDATE A   ------------------------------
                 
            end if; -- /* end ena_dly_sampled = '1' */
      end if;
------------------------------------------------------------------------                       
------------ Port B  -- Memory Update ----------------------------------
------------------------------------------------------------------------                       

    if((GSR_CLKB_dly = '0') and rising_edge(CLKB_dly)) then
        if (enb_dly_sampled = '1') then
                case DIBW is
                  --------------
                  when 1|2|4|8 =>
                  --------------
                      tmp_we(1 downto 0) := addrb_dly_sampled( 4 downto 3);
                      web_index := SLV_TO_INT(tmp_we);
                      if (web_dly_sampled(web_index) = '1') then
                         if (VALID_ADDRB) then
                            MEM((ADDRESS_WRITE_B + DIBW_1) downto (ADDRESS_WRITE_B)) := DIB_dly(DIBW_1 downto 0);
                            if(DIPBW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto (16384 + ADDRESS_PARITY_WRITE_B)) := DIPB_dly(DIPBW_1 downto 0);
                            end if;
                         else
                          DOB_zd(DOBW_1 downto 0) := (others => 'X');
                          if(DOPBW_1 /= -1) then
                             DOPB_zd(DOPBW_1 downto 0) := (others => 'X');
                          end if;
                         end if; -- /* VAILD ADDRB */
                      end if; -- /*  web_dly_sampled = '1' */ 

                  ---------
                  when 16 =>
                  ---------
                      tmp_we(1) := addrb_dly_sampled(4);
                      tmp_we(0) := '0';
                      web_index := SLV_TO_INT(tmp_we);
                      if (web_dly_sampled(web_index) = '1') then
                         if (VALID_ADDRB) then
                            MEM((ADDRESS_WRITE_B + DIBW/2 -1) downto (ADDRESS_WRITE_B)) := DIB_dly((DIBW/2 - 1) downto 0);
                            if(DIPBW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW/2 - 1) downto (16384 + ADDRESS_PARITY_WRITE_B)) := DIPB_dly((DIPBW/2 -1) downto 0);
                            end if;
                         end if; -- /* VAILD ADDRB */
                      end if; -- /*  web_dly_sampled = '1' */ 

                      tmp_we(0) := '1';
                      web_index := SLV_TO_INT(tmp_we);
                      if (web_dly_sampled(web_index) = '1') then
                         if (VALID_ADDRB) then
                            MEM((ADDRESS_WRITE_B + DIBW_1) downto (ADDRESS_WRITE_B + DIBW/2)) := DIB_dly(DIBW_1 downto DIBW/2);
                            if(DIPBW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto (16384 + ADDRESS_PARITY_WRITE_B + DIPBW/2)) := DIPB_dly(DIPBW_1 downto DIPBW/2);
                            end if;
                         end if; -- /* VAILD ADDRB */
                      end if; -- /*  web_dly_sampled = '1' */ 

                  ---------
                  when 32 =>
                  ---------
                      web_index := 0;
                      if (web_dly_sampled(web_index) = '1') then
                         if (VALID_ADDRB) then
                            MEM((ADDRESS_WRITE_B + (DIBW/4)*1 -1) downto (ADDRESS_WRITE_B)) := DIB_dly((((DIBW/4)*1) - 1) downto 0);
                            if(DIPBW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*1 - 1) downto (16384 + ADDRESS_PARITY_WRITE_B)) := DIPB_dly(((DIPBW/4)*1 -1) downto 0);
                            end if;
                         end if; -- /* VAILD ADDRB */
                      end if; -- /*  web_dly_sampled = '1' */ 

                      web_index := 1;
                      if (web_dly_sampled(web_index) = '1') then
                         if (VALID_ADDRB) then
                            MEM((ADDRESS_WRITE_B + (DIBW/4)*2 -1) downto (ADDRESS_WRITE_B + (DIBW/4)*1)) := DIB_dly((((DIBW/4)*2) - 1) downto (DIBW/4)*1);
                            if(DIPBW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*2 - 1) downto (16384 + ADDRESS_PARITY_WRITE_B  + (DIPBW/4)*1)) := DIPB_dly(((DIPBW/4)*2 -1) downto ((DIPBW/4)*1));
                            end if;
                         end if; -- /* VAILD ADDRB */
                      end if; -- /*  web_dly_sampled = '1' */ 

                      web_index := 2;
                      if (web_dly_sampled(web_index) = '1') then
                         if (VALID_ADDRB) then
                            MEM((ADDRESS_WRITE_B + (DIBW/4)*3 -1) downto (ADDRESS_WRITE_B + (DIBW/4)*2)) := DIB_dly((((DIBW/4)*3) - 1) downto (DIBW/4)*2);
                            if(DIPBW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*3 - 1) downto (16384 + ADDRESS_PARITY_WRITE_B  + (DIPBW/4)*2)) := DIPB_dly(((DIPBW/4)*3 -1) downto ((DIPBW/4)*2));
                            end if;
                         end if; -- /* VAILD ADDRB */
                      end if; -- /*  web_dly_sampled = '1' */ 

                      web_index := 3;
                      if (web_dly_sampled(web_index) = '1') then
                         if (VALID_ADDRB) then
                            MEM((ADDRESS_WRITE_B + (DIBW/4)*4 -1) downto (ADDRESS_WRITE_B + (DIBW/4)*3)) := DIB_dly((((DIBW/4)*4) - 1) downto (DIBW/4)*3);
                            if(DIPBW_1 /= -1) then
                               MEM((16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*4 - 1) downto (16384 + ADDRESS_PARITY_WRITE_B  + (DIPBW/4)*3)) := DIPB_dly(((DIPBW/4)*4 -1) downto ((DIPBW/4)*3));
                            end if;
                         end if; -- /* VAILD ADDRB */
                      end if; -- /*  web_dly_sampled = '1' */ 
                  when others =>
                     null;
                end case;
                 
-----------------------  Start COLLISION MEMORY UPDATE B ------------------------------

        if(SimCollisionCheck_var /= 0) then
           if(clsn_type.write_write) then
              tmp_membuf := (others => '0');
              DOB_clsn_write_index := SLV_TO_INT(tmp_zero_write_b(4 downto 0));
              tmp_membuf(DIBW_1 downto 0) := MEM((ADDRESS_WRITE_B + DIBW_1) downto (ADDRESS_WRITE_B));
              MEM((ADDRESS_WRITE_B + DIBW_1) downto (ADDRESS_WRITE_B)) := tmp_membuf(DIBW_1 downto 0) xor clsn_xbufs.MEM1_clsn((DOB_clsn_write_index+DIBW_1) downto DOB_clsn_write_index);

             if((DIPBW_1 /= -1) and (DIPAW_1 /= -1)) then
                tmp_membuf := (others => '0');
                DOPB_clsn_write_index := SLV_TO_INT(tmp_zero_parity_write_b(1 downto 0));
                tmp_membuf(DIPBW_1 downto 0) :=  MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto (16384 + ADDRESS_PARITY_WRITE_B));
                MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto (16384 + ADDRESS_PARITY_WRITE_B)) := tmp_membuf(DIPBW_1 downto 0) xor clsn_xbufs.MEMP1_clsn((DOPB_clsn_write_index + DIPBW_1) downto DOPB_clsn_write_index);
              end if;
           end if;
        end if;
                
-----------------------  END COLLISION MEMORY UPDATE B   ------------------------------

            end if; -- /* end enb_dly_sampled = '1' */
      end if;
--=======================================================================================
----- Port A

    DOA_viol(0)  <= ViolationA xor DOA_zd(0) xor DOA_clsn_zero(0);
    DOA_viol(1)  <= ViolationA xor DOA_zd(1) xor DOA_clsn_zero(1);
    DOA_viol(2)  <= ViolationA xor DOA_zd(2) xor DOA_clsn_zero(2);
    DOA_viol(3)  <= ViolationA xor DOA_zd(3) xor DOA_clsn_zero(3);
    DOA_viol(4)  <= ViolationA xor DOA_zd(4) xor DOA_clsn_zero(4);
    DOA_viol(5)  <= ViolationA xor DOA_zd(5) xor DOA_clsn_zero(5);
    DOA_viol(6)  <= ViolationA xor DOA_zd(6) xor DOA_clsn_zero(6);
    DOA_viol(7)  <= ViolationA xor DOA_zd(7) xor DOA_clsn_zero(7);
    DOA_viol(8)  <= ViolationA xor DOA_zd(8) xor DOA_clsn_zero(8);
    DOA_viol(9)  <= ViolationA xor DOA_zd(9) xor DOA_clsn_zero(9);
    DOA_viol(10) <= ViolationA xor DOA_zd(10) xor DOA_clsn_zero(10);
    DOA_viol(11) <= ViolationA xor DOA_zd(11) xor DOA_clsn_zero(11);
    DOA_viol(12) <= ViolationA xor DOA_zd(12) xor DOA_clsn_zero(12);
    DOA_viol(13) <= ViolationA xor DOA_zd(13) xor DOA_clsn_zero(13);
    DOA_viol(14) <= ViolationA xor DOA_zd(14) xor DOA_clsn_zero(14);
    DOA_viol(15) <= ViolationA xor DOA_zd(15) xor DOA_clsn_zero(15);
    DOA_viol(16) <= ViolationA xor DOA_zd(16) xor DOA_clsn_zero(16);
    DOA_viol(17) <= ViolationA xor DOA_zd(17) xor DOA_clsn_zero(17);
    DOA_viol(18) <= ViolationA xor DOA_zd(18) xor DOA_clsn_zero(18);
    DOA_viol(19) <= ViolationA xor DOA_zd(19) xor DOA_clsn_zero(19);
    DOA_viol(20) <= ViolationA xor DOA_zd(20) xor DOA_clsn_zero(20);
    DOA_viol(21) <= ViolationA xor DOA_zd(21) xor DOA_clsn_zero(21);
    DOA_viol(22) <= ViolationA xor DOA_zd(22) xor DOA_clsn_zero(22);
    DOA_viol(23) <= ViolationA xor DOA_zd(23) xor DOA_clsn_zero(23);
    DOA_viol(24) <= ViolationA xor DOA_zd(24) xor DOA_clsn_zero(24);
    DOA_viol(25) <= ViolationA xor DOA_zd(25) xor DOA_clsn_zero(25);
    DOA_viol(26) <= ViolationA xor DOA_zd(26) xor DOA_clsn_zero(26);
    DOA_viol(27) <= ViolationA xor DOA_zd(27) xor DOA_clsn_zero(27);
    DOA_viol(28) <= ViolationA xor DOA_zd(28) xor DOA_clsn_zero(28);
    DOA_viol(29) <= ViolationA xor DOA_zd(29) xor DOA_clsn_zero(29);
    DOA_viol(30) <= ViolationA xor DOA_zd(30) xor DOA_clsn_zero(30);
    DOA_viol(31) <= ViolationA xor DOA_zd(31) xor DOA_clsn_zero(31);
    DOPA_viol(0) <= ViolationA xor DOPA_zd(0) xor DOPA_clsn_zero(0);
    DOPA_viol(1) <= ViolationA xor DOPA_zd(1) xor DOPA_clsn_zero(1);
    DOPA_viol(2) <= ViolationA xor DOPA_zd(2) xor DOPA_clsn_zero(2);
    DOPA_viol(3) <= ViolationA xor DOPA_zd(3) xor DOPA_clsn_zero(3);

----- Port B

    DOB_viol(0)  <= ViolationB xor DOB_zd(0) xor DOB_clsn_zero(0);
    DOB_viol(1)  <= ViolationB xor DOB_zd(1) xor DOB_clsn_zero(1);
    DOB_viol(2)  <= ViolationB xor DOB_zd(2) xor DOB_clsn_zero(2);
    DOB_viol(3)  <= ViolationB xor DOB_zd(3) xor DOB_clsn_zero(3);
    DOB_viol(4)  <= ViolationB xor DOB_zd(4) xor DOB_clsn_zero(4);
    DOB_viol(5)  <= ViolationB xor DOB_zd(5) xor DOB_clsn_zero(5);
    DOB_viol(6)  <= ViolationB xor DOB_zd(6) xor DOB_clsn_zero(6);
    DOB_viol(7)  <= ViolationB xor DOB_zd(7) xor DOB_clsn_zero(7);
    DOB_viol(8)  <= ViolationB xor DOB_zd(8) xor DOB_clsn_zero(8);
    DOB_viol(9)  <= ViolationB xor DOB_zd(9) xor DOB_clsn_zero(9);
    DOB_viol(10) <= ViolationB xor DOB_zd(10) xor DOB_clsn_zero(10);
    DOB_viol(11) <= ViolationB xor DOB_zd(11) xor DOB_clsn_zero(11);
    DOB_viol(12) <= ViolationB xor DOB_zd(12) xor DOB_clsn_zero(12);
    DOB_viol(13) <= ViolationB xor DOB_zd(13) xor DOB_clsn_zero(13);
    DOB_viol(14) <= ViolationB xor DOB_zd(14) xor DOB_clsn_zero(14);
    DOB_viol(15) <= ViolationB xor DOB_zd(15) xor DOB_clsn_zero(15);
    DOB_viol(16) <= ViolationB xor DOB_zd(16) xor DOB_clsn_zero(16);
    DOB_viol(17) <= ViolationB xor DOB_zd(17) xor DOB_clsn_zero(17);
    DOB_viol(18) <= ViolationB xor DOB_zd(18) xor DOB_clsn_zero(18);
    DOB_viol(19) <= ViolationB xor DOB_zd(19) xor DOB_clsn_zero(19);
    DOB_viol(20) <= ViolationB xor DOB_zd(20) xor DOB_clsn_zero(20);
    DOB_viol(21) <= ViolationB xor DOB_zd(21) xor DOB_clsn_zero(21);
    DOB_viol(22) <= ViolationB xor DOB_zd(22) xor DOB_clsn_zero(22);
    DOB_viol(23) <= ViolationB xor DOB_zd(23) xor DOB_clsn_zero(23);
    DOB_viol(24) <= ViolationB xor DOB_zd(24) xor DOB_clsn_zero(24);
    DOB_viol(25) <= ViolationB xor DOB_zd(25) xor DOB_clsn_zero(25);
    DOB_viol(26) <= ViolationB xor DOB_zd(26) xor DOB_clsn_zero(26);
    DOB_viol(27) <= ViolationB xor DOB_zd(27) xor DOB_clsn_zero(27);
    DOB_viol(28) <= ViolationB xor DOB_zd(28) xor DOB_clsn_zero(28);
    DOB_viol(29) <= ViolationB xor DOB_zd(29) xor DOB_clsn_zero(29);
    DOB_viol(30) <= ViolationB xor DOB_zd(30) xor DOB_clsn_zero(30);
    DOB_viol(31) <= ViolationB xor DOB_zd(31) xor DOB_clsn_zero(31);
    DOPB_viol(0) <= ViolationB xor DOPB_zd(0) xor DOPB_clsn_zero(0);
    DOPB_viol(1) <= ViolationB xor DOPB_zd(1) xor DOPB_clsn_zero(1);
    DOPB_viol(2) <= ViolationB xor DOPB_zd(2) xor DOPB_clsn_zero(2);
    DOPB_viol(3) <= ViolationB xor DOPB_zd(3) xor DOPB_clsn_zero(3);

    wait on ADDRA_dly, ADDRB_dly, CLKA_dly, CLKB_dly, DIA_dly, DIB_dly, DIPA_dly, DIPB_dly, ENA_dly, ENB_dly, GSR_ipd, GSR_CLKA_dly, GSR_CLKB_dly, REGCEA_dly, REGCEB_dly, RSTA_dly, RSTB_dly, WEA_dly, WEB_dly;
  end process VITALBehavior;

----------------------------------------------------------------------------
------------------- Output Registers -- Port A -----------------------------
----------------------------------------------------------------------------

   prcs_regA:process (INIT_DONE, CLKA_dly, GSR_CLKA_dly, RSTA_dly)
   variable ssra_reg_var : std_ulogic := '0';
   variable FIRST_TIME : boolean := true;
   begin

-- CR 430517 - added 1 line though it may not be necessary
       ssra_reg_var := '0';

       if(FIRST_TIME and INIT_DONE) then
           DOA_regist(DOAW_1 downto 0) <= INI_A_sig(DOAW_1 downto 0);
           if(DOPAW_1 /= -1) then
             DOPA_regist(DOPAW_1 downto 0) <= INI_A_sig((DOPAW_1 + DOAW) downto DOAW);
           end if;
           FIRST_TIME := false;
       elsif(DOA_REG = 1) then
           if(GSR_CLKA_dly = '1') then
              DOA_regist(DOAW_1 downto 0) <= INI_A_sig(DOAW_1 downto 0);
              if(DOPAW_1 /= -1) then
                DOPA_regist(DOPAW_1 downto 0) <= INI_A_sig((DOPAW_1 + DOAW) downto DOAW);
              end if;
              ssra_reg_var := '0';
-- CR 426962
--           elsif((GSR_CLKA_dly = '0') and (ENA_dly = '1'))then
           elsif (GSR_CLKA_dly = '0') then
              if(ENA_dly = '1') then
                 ssra_reg_var := RSTA_dly;
              end if;
              case rst_async_flag is
                  when '1' =>
                  -----------// async reset
-- CR 427370 fix
                       if((RSTA_dly = '1') and (ENA_dly = '1'))then
                          DOA_regist(DOAW_1 downto 0) <=  SRVA_A_sig(DOAW_1 downto 0);
                          if(DOPAW_1 /= -1) then
                             DOPA_regist(DOPAW_1 downto 0) <= SRVA_A_sig((DOPAW_1 + DOAW) downto DOAW);
                          end if;
--                       elsif ((RSTA_dly = '0') and (REGCEA_dly = '1')) then
                       elsif ((ssra_reg_var = '0') and (REGCEA_dly = '1')) then
                          if(rising_edge(CLKA_dly)) then
                             DOA_regist <= DOA_viol;
                             DOPA_regist <= DOPA_viol;
                          end if;
                       end if;
                  
                  when '0' =>
                       if(rising_edge(CLKA_dly)) then
--                          if(RSTA_dly = '1') then
                          if(ssra_reg_var = '1') then
                             DOA_regist(DOAW_1 downto 0) <=  SRVA_A_sig(DOAW_1 downto 0);
                             if(DOPAW_1 /= -1) then
                                DOPA_regist(DOPAW_1 downto 0) <= SRVA_A_sig((DOPAW_1 + DOAW) downto DOAW);
                             end if;
--                          elsif ((RSTA_dly = '0') and (REGCEA_dly = '1')) then
                          elsif ((ssra_reg_var = '0') and (REGCEA_dly = '1')) then
                             DOA_regist <= DOA_viol;
                             DOPA_regist <= DOPA_viol;
                          end if;
                       end if;
                  when others => null;
              end case;

           end if;
       end if;
   end process prcs_regA;
-----------------------------------------------------------------------------------
   prcs_PipeLineA:process (INIT_DONE, DOA_viol, DOPA_viol, DOA_regist, DOPA_regist)
   variable FIRST_TIME : boolean := true;
   begin
    if(FIRST_TIME) then
      if(INIT_DONE) then
        DOA_mux(DOAW_1 downto 0) <= INI_A_sig(DOAW_1 downto 0);
        if(DOPAW_1 /= -1) then
           DOPA_mux(DOPAW_1 downto 0) <= INI_A_sig((DOPAW_1 + DOAW) downto DOAW);
        end if;
        FIRST_TIME := false;
      end if;
    else
     case DOA_REG is
       when 0 =>
            DOA_mux  <= DOA_viol;
            DOPA_mux <= DOPA_viol;

       when 1 =>
            DOA_mux  <= DOA_regist;
            DOPA_mux <= DOPA_regist;
       when others =>
            assert false
            report "Attribute Syntax Error : The allowed values for DOA_REG are 0 or 1"
            severity Failure;
     end case;
    end if;
   end process prcs_PipeLineA;

----------------------------------------------------------------------------
------------------- Output Registers -- Port B -----------------------------
----------------------------------------------------------------------------

   prcs_regB:process (INIT_DONE, CLKB_dly, GSR_CLKB_dly, RSTB_dly)
   variable ssrb_reg_var : std_ulogic := '0';
   variable FIRST_TIME : boolean := true;
   begin

-- CR 430517 - added 1 line though it may not be necessary
       ssrb_reg_var := '0';

       if(FIRST_TIME and INIT_DONE) then
           DOB_regist(DOBW_1 downto 0) <= INI_B_sig(DOBW_1 downto 0);
           if(DOPBW_1 /= -1) then
             DOPB_regist(DOPBW_1 downto 0) <= INI_B_sig((DOPBW_1 + DOBW) downto DOBW);
           end if;
           FIRST_TIME := false;
       elsif(DOB_REG = 1) then
           if(GSR_CLKB_dly = '1') then
              DOB_regist(DOBW_1 downto 0) <= INI_B_sig(DOBW_1 downto 0);
              if(DOPBW_1 /= -1) then
                DOPB_regist(DOPBW_1 downto 0) <= INI_B_sig((DOPBW_1 + DOBW) downto DOBW);
              end if;
              ssrb_reg_var := '0';
-- CR 426962
--           elsif((GSR_CLKB_dly = '0') and (ENB_dly = '1'))then
           elsif(GSR_CLKB_dly = '0') then
              if(ENB_dly = '1') then
                 ssrb_reg_var := RSTB_dly;
              end if;
              case rst_async_flag is
                  when '1' =>
                  -----------// async reset
-- CR 427370 fix
                       if((RSTB_dly = '1') and (ENB_dly = '1')) then
                          DOB_regist(DOBW_1 downto 0) <=  SRVA_B_sig(DOBW_1 downto 0);
                          if(DOPBW_1 /= -1) then
                             DOPB_regist(DOPBW_1 downto 0) <= SRVA_B_sig((DOPBW_1 + DOBW) downto DOBW);
                          end if;
--                       elsif ((RSTB_dly = '0') and (REGCEB_dly = '1')) then
                       elsif ((ssrb_reg_var = '0') and (REGCEB_dly = '1')) then
                          if(rising_edge(CLKB_dly)) then
                             DOB_regist <= DOB_viol;
                             DOPB_regist <= DOPB_viol;
                          end if;
                       end if;
                  
                  when '0' =>
                       if(rising_edge(CLKB_dly)) then
--                          if(RSTB_dly = '1') then
                          if(ssrb_reg_var = '1') then
                             DOB_regist(DOBW_1 downto 0) <=  SRVA_B_sig(DOBW_1 downto 0);
                             if(DOPBW_1 /= -1) then
                                DOPB_regist(DOPBW_1 downto 0) <= SRVA_B_sig((DOPBW_1 + DOBW) downto DOBW);
                             end if;
--                          elsif ((RSTB_dly = '0') and (REGCEB_dly = '1')) then
                          elsif ((ssrb_reg_var = '0') and (REGCEB_dly = '1')) then
                             DOB_regist <= DOB_viol;
                             DOPB_regist <= DOPB_viol;
                          end if;
                       end if;
                  when others => null;
              end case;

           end if;
       end if;
   end process prcs_regB;

----------------------------------------------------------------------------
   prcs_PipeLineB:process (INIT_DONE, DOB_viol, DOPB_viol, DOB_regist, DOPB_regist)
   variable FIRST_TIME : boolean := true;
   begin
    if(FIRST_TIME) then
      if(INIT_DONE) then
        DOB_mux(DOBW_1 downto 0) <= INI_B_sig(DOBW_1 downto 0);
        if(DOPBW_1 /= -1) then
           DOPB_mux(DOPBW_1 downto 0) <= INI_B_sig((DOPBW_1 + DOBW) downto DOBW);
        end if;
        FIRST_TIME := false;
      end if;
    else
     case DOB_REG is
       when 0 =>
            DOB_mux  <= DOB_viol;
            DOPB_mux <= DOPB_viol;

       when 1 =>
            DOB_mux  <= DOB_regist;
            DOPB_mux <= DOPB_regist;
       when others =>
            assert false
            report "Attribute Syntax Error : The allowed values for DOB_REG are 0 or 1"
            severity Failure;
     end case;
    end if;
   end process prcs_PipeLineB;

----- ###############################################################################

   prcs_output:process (DOA_mux, DOPA_mux, DOB_mux, DOPB_mux)
   begin
       DOA    <= DOA_mux after SYNC_PATH_DELAY;
       DOPA   <= DOPA_mux after SYNC_PATH_DELAY;
       DOB    <= DOB_mux after SYNC_PATH_DELAY;
       DOPB   <= DOPB_mux after SYNC_PATH_DELAY;
   end process prcs_output;

end RAMB16BWER_V;

