-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: cpu_embedded using cpu_core and rom
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

use work.sdram_config.all;
use work.sdram_types.all;

entity tb_ctrl_ddr_wb64 is
end;

architecture struct of tb_ctrl_ddr_wb64 is

	constant CLK_PERIOD		: time := 10 ns;
	constant TPD_BOARD_SIM	: time := 1 ns;
	constant SDCLK_PERIOD	: time := 10 ns;

	signal sdclk			: std_logic := '1';  
	signal sdclk_fb			: std_logic;  
	signal part_clk_p		: std_logic;  
	signal part_clk_n		: std_logic;  
	signal part_cke			: std_logic;  
	signal part_cs_n		: std_logic;  
	signal part_we_n		: std_logic;  
	signal part_ras_n		: std_logic;  
	signal part_cas_n		: std_logic;  
	signal part_ba			: unsigned(PART_BANK_WIDTH-1 downto 0) := (others => '0');
	signal part_dm			: unsigned(PART_DM_WIDTH-1 downto 0) := (others => '0');
	signal part_dqs			: unsigned(PART_DQS_WIDTH-1 downto 0) := (others => '0');
	signal part_addr		: unsigned(PART_ADDR_WIDTH-1 downto 0) := (others => '0');
	signal part_data		: unsigned(PART_DATA_WIDTH-1 downto 0) := (others => '0');

	signal CLK_O			: std_logic := '1';
	signal RST_O			: std_logic := '1';
	signal CYC_O			: std_logic := '0';
	signal STB_O			: std_logic := '0';
	signal WE_O				: std_logic := '0';
	signal SEL_O			: unsigned(BUS_DM_WIDTH-1 downto 0);
	signal ACK_I			: std_logic;
	signal MRDY_O			: std_logic := '1';
	signal SRDY_I			: std_logic;
	signal ADDR_O			: unsigned(31 downto 0) := (others => '-');
	signal DAT_I			: unsigned(BUS_DATA_WIDTH-1 downto 0);
	signal DAT_O			: unsigned(BUS_DATA_WIDTH-1 downto 0);

	signal dout_rst			: std_logic := '0';
	signal dout_reg			: unsigned(31 downto 0);
	signal dout_cnt			: natural range 0 to 255;

	signal sddat			: unsigned(31 downto 0) := (others => '-');
	signal sdsel			: unsigned(3 downto 0) := (others => '1');

	type sd_cmd_t is (nop, lmr, ar, pre, act, write, read, bst);
	signal sd_cmd : sd_cmd_t;
	
begin 
   
	process(part_cs_n, part_ras_n, part_cas_n, part_we_n)
	variable cmd : unsigned (2 downto 0);

	begin
		cmd := part_ras_n & part_cas_n & part_we_n;
		sd_cmd <= nop;
		if part_cs_n = '0' then
			case cmd is
				when "000" =>
					sd_cmd <= lmr;
				when "001" =>
					sd_cmd <= ar;
				when "010" =>
					sd_cmd <= pre;
				when "011" =>
					sd_cmd <= act;
				when "100" =>
					sd_cmd <= write;
				when "101" =>
					sd_cmd <= read;
				when "110" =>
					sd_cmd <= bst;
				when "111" =>
					sd_cmd <= nop;
				
				when others =>
					sd_cmd <= nop;

			end case;
		end if;
	end process;
	
	sdclk_fb	<= part_clk_p after TPD_BOARD_SIM;

	DAT_O	<= X"DEADBEEF" & sddat;
	SEL_O	<= "0000" & sdsel;
	
	-- DDR SDRAM Controller Core
	uut : entity work.ctrl_ddr_wb64
	GENERIC MAP
	(
		F_SYSCLK	 	=> 100.000,
		F_SDRCLK	 	=> 100.000,
		FIFO_DEPTH		=> 4,
		TPD_BOARD_SIM	=> TPD_BOARD_SIM
	)
	PORT MAP
	(
		RST_I				=> RST_O,
		CLK_I				=> CLK_O,
		SDRAM_CLK_I			=> sdclk,
		SDRAM_CLK_FB_I		=> sdclk_fb,
		
		CYC_I				=> CYC_O,
		STB_I				=> STB_O,
		SEL_I				=> SEL_O,
		WE_I				=> WE_O,
		ACK_O				=> ACK_I,
		SRDY_O				=> SRDY_I,
		MRDY_I				=> MRDY_O,
		ADDR_I				=> ADDR_O,
		DAT_I				=> DAT_O,
		DAT_O				=> DAT_I,

		-- SDRAM signals
		sd_clk_p			=> part_clk_p,
		sd_clk_n			=> part_clk_n,
		sd_cke				=> part_cke,
		sd_cs_n				=> part_cs_n,
		sd_cas_n			=> part_cas_n,
		sd_ras_n			=> part_ras_n,
		sd_we_n				=> part_we_n,
		sd_addr				=> part_addr,
		sd_ba				=> part_ba,
		sd_dm				=> part_dm,
		sd_dqs				=> part_dqs,
		sd_data				=> part_data
		
	);
   
   -- MICRON DDR SDRAM Simulation Model
i_mt46v16m16_0 : entity work.mt46v16m16 
      port map
      (
         unsigned(dq)	=> std_logic_vector(part_data(15 downto 0)),
         unsigned(dqs)	=> std_logic_vector(part_dqs(1 downto 0)),
         addr  => std_logic_vector(part_addr),
         ba    => std_logic_vector(part_ba),
         clk   => part_clk_p,
         clk_n => part_clk_n,
         cke   => part_cke,
         cs_n  => part_cs_n,
         ras_n => part_ras_n,
         cas_n => part_cas_n,
         we_n  => part_we_n,
         dm    => std_logic_vector(part_dm(1 downto 0))
	);

   -- MICRON DDR SDRAM Simulation Model
i_mt46v16m16_1 : entity work.mt46v16m16 
      port map
      (
         unsigned(dq)	=> std_logic_vector(part_data(31 downto 16)),
         unsigned(dqs)	=> std_logic_vector(part_dqs(3 downto 2)),
         addr  => std_logic_vector(part_addr),
         ba    => std_logic_vector(part_ba),
         clk   => part_clk_p,
         clk_n => part_clk_n,
         cke   => part_cke,
         cs_n  => part_cs_n,
         ras_n => part_ras_n,
         cas_n => part_cas_n,
         we_n  => part_we_n,
         dm    => std_logic_vector(part_dm(3 downto 2))
	);

CLK_GEN: process
	begin
		wait for CLK_PERIOD/2;
		CLK_O <= not CLK_O;
	end process;

SDCLK_GEN: process
	begin
		wait for SDCLK_PERIOD/2;
		sdclk <= not sdclk;
	end process;

read_register:
	process(CLK_O)
	begin
		if rising_edge(CLK_O) then
			if dout_rst = '1' then
				dout_cnt <= 0;
			elsif ACK_I = '1' and WE_O = '0' then
				dout_reg	<= DAT_I(31 downto 0);
				dout_cnt 	<= dout_cnt + 1;
			end if;
		end if;
	end process;
		
------------------------------------------------------------------------------------------

STIMULUS: process

	begin

		wait for 3*CLK_PERIOD;
		RST_O <= '0';
		
		wait until RST_O = '0';
		-- 8 single cycles
		CYC_O	<= '1';
		STB_O	<= '1';
		WE_O	<= '1';
		sddat	<= X"1234_0000";
		ADDR_O	<= X"0000_0000";
		
		for i in 0 to 8192 loop
			wait until rising_edge(CLK_O) and SRDY_I = '1';
			sddat	<= sddat + 1;
			ADDR_O	<= ADDR_O + 4;
		end loop;
	
		STB_O	<= '0';
		wait until rising_edge(CLK_O);
		CYC_O	<= '0';

		------------------------------------------------------------
		wait for 3*CLK_PERIOD;
		------------------------------------------------------------

		-- 8-word burst cycle
		dout_rst	<= '1';
		wait until rising_edge(CLK_O);
		dout_rst	<= '0';
		CYC_O	<= '1';
		STB_O	<= '1';
		WE_O	<= '0';
		ADDR_O	<= X"0000_0000";

		for i in 0 to 31 loop
			wait until rising_edge(CLK_O) and SRDY_I = '1';
			ADDR_O	<= ADDR_O + 4;
		end loop;
		
		STB_O	<= '0';
		wait until rising_edge(CLK_O) and dout_cnt = 31;
		CYC_O	<= '0';

		------------------------------------------------------------
		wait for 3*CLK_PERIOD;
		------------------------------------------------------------

		wait until rising_edge(CLK_O);
		-- 1-word burst cycle
		CYC_O	<= '1';
		STB_O	<= '1';
		WE_O	<= '1';
		sdsel	<= "0011";
		ADDR_O	<= X"0000_0080";
		sddat	<= X"DEADBEEF";
		wait until rising_edge(CLK_O) and SRDY_I = '1';
		STB_O	<= '0';
		wait until rising_edge(CLK_O);
		CYC_O	<= '0';

		------------------------------------------------------------
		wait for 3*CLK_PERIOD;
		------------------------------------------------------------

		wait until rising_edge(CLK_O);
		-- 1-word burst cycle
		CYC_O	<= '1';
		STB_O	<= '1';
		WE_O	<= '0';
		ADDR_O	<= X"0000_0080";
		wait until rising_edge(CLK_O) and SRDY_I = '1';
		STB_O	<= '0';
		wait until rising_edge(CLK_O) and ACK_I = '1';
		CYC_O	<= '0';

		------------------------------------------------------------
		wait for 3*CLK_PERIOD;
		------------------------------------------------------------

		-- 8-word burst cycle
		dout_rst	<= '1';
		wait until rising_edge(CLK_O);
		dout_rst	<= '0';

		CYC_O	<= '1';
		STB_O	<= '1';
		WE_O	<= '0';
		ADDR_O	<= X"0000_0000";

		for i in 0 to 31 loop
			wait until rising_edge(CLK_O) and SRDY_I = '1';
			ADDR_O	<= ADDR_O + 4;
		end loop;
		
		STB_O	<= '0';
		wait until rising_edge(CLK_O) and dout_cnt = 31;
		CYC_O	<= '0';

		------------------------------------------------------------
		wait for 10*CLK_PERIOD;
		------------------------------------------------------------

		for k in 0 to 3 loop
			------------------------------------------------------------
--			wait for 3*CLK_PERIOD;
			------------------------------------------------------------

			-- 8-word burst cycle
			dout_rst	<= '1';
			wait until rising_edge(CLK_O);
			dout_rst	<= '0';

			CYC_O	<= '1';
			STB_O	<= '1';
			WE_O	<= '0';
			ADDR_O	<= X"0000_0000";

			for i in 0 to 7 loop
				wait until rising_edge(CLK_O) and SRDY_I = '1';
				ADDR_O	<= ADDR_O + 4;
			end loop;

			STB_O	<= '0';
			wait until rising_edge(CLK_O) and dout_cnt = 7;
			CYC_O	<= '0';

			------------------------------------------------------------
--			wait for 3*CLK_PERIOD;
			------------------------------------------------------------

			-- 8-word burst cycle
			dout_rst	<= '1';
			wait until rising_edge(CLK_O);
			dout_rst	<= '0';

			CYC_O	<= '1';
			STB_O	<= '1';
			WE_O	<= '0';
			ADDR_O	<= X"0000_0400";

			for i in 0 to 7 loop
				wait until rising_edge(CLK_O) and SRDY_I = '1';
				ADDR_O	<= ADDR_O + 4;
			end loop;

			STB_O	<= '0';
			wait until rising_edge(CLK_O) and dout_cnt = 7;
			CYC_O	<= '0';

			------------------------------------------------------------
--			wait for 3*CLK_PERIOD;
			------------------------------------------------------------

			-- 8-word burst cycle
			dout_rst	<= '1';
			wait until rising_edge(CLK_O);
			dout_rst	<= '0';

			CYC_O	<= '1';
			STB_O	<= '1';
			WE_O	<= '0';
			ADDR_O	<= X"0000_0800";

			for i in 0 to 7 loop
				wait until rising_edge(CLK_O) and SRDY_I = '1';
				ADDR_O	<= ADDR_O + 4;
			end loop;

			STB_O	<= '0';
			wait until rising_edge(CLK_O) and dout_cnt = 7;
			CYC_O	<= '0';

			------------------------------------------------------------
--			wait for 3*CLK_PERIOD;
			------------------------------------------------------------

			-- 8-word burst cycle
			dout_rst	<= '1';
			wait until rising_edge(CLK_O);
			dout_rst	<= '0';

			CYC_O	<= '1';
			STB_O	<= '1';
			WE_O	<= '0';
			ADDR_O	<= X"0000_0C00";

			for i in 0 to 7 loop
				wait until rising_edge(CLK_O) and SRDY_I = '1';
				ADDR_O	<= ADDR_O + 4;
			end loop;

			STB_O	<= '0';
			wait until rising_edge(CLK_O) and dout_cnt = 7;
			CYC_O	<= '0';
		
		end loop;

		------------------------------------------------------------
		wait for 10*CLK_PERIOD;
		------------------------------------------------------------
		
		for k in 0 to 3 loop

			-- 8-word burst cycle
			dout_rst	<= '1';
			wait until rising_edge(CLK_O);
			dout_rst	<= '0';

			CYC_O	<= '1';
			STB_O	<= '1';
			WE_O	<= '0';
			ADDR_O	<= X"0000_1000";

			for i in 0 to 7 loop
				wait until rising_edge(CLK_O) and SRDY_I = '1';
				ADDR_O	<= ADDR_O + 4;
			end loop;

			STB_O	<= '0';
			wait until rising_edge(CLK_O) and dout_cnt = 7;
			CYC_O	<= '0';

			------------------------------------------------------------
--			wait for 3*CLK_PERIOD;
			------------------------------------------------------------

			-- 8-word burst cycle
			dout_rst	<= '1';
			wait until rising_edge(CLK_O);
			dout_rst	<= '0';

			CYC_O	<= '1';
			STB_O	<= '1';
			WE_O	<= '0';
			ADDR_O	<= X"0000_1400";

			for i in 0 to 7 loop
				wait until rising_edge(CLK_O) and SRDY_I = '1';
				ADDR_O	<= ADDR_O + 4;
			end loop;

			STB_O	<= '0';
			wait until rising_edge(CLK_O) and dout_cnt = 7;
			CYC_O	<= '0';

			------------------------------------------------------------
--			wait for 3*CLK_PERIOD;
			------------------------------------------------------------

			-- 8-word burst cycle
			dout_rst	<= '1';
			wait until rising_edge(CLK_O);
			dout_rst	<= '0';

			CYC_O	<= '1';
			STB_O	<= '1';
			WE_O	<= '0';
			ADDR_O	<= X"0000_1800";

			for i in 0 to 7 loop
				wait until rising_edge(CLK_O) and SRDY_I = '1';
				ADDR_O	<= ADDR_O + 4;
			end loop;

			STB_O	<= '0';
			wait until rising_edge(CLK_O) and dout_cnt = 7;
			CYC_O	<= '0';

			------------------------------------------------------------
--			wait for 3*CLK_PERIOD;
			------------------------------------------------------------

			-- 8-word burst cycle
			dout_rst	<= '1';
			wait until rising_edge(CLK_O);
			dout_rst	<= '0';

			CYC_O	<= '1';
			STB_O	<= '1';
			WE_O	<= '0';
			ADDR_O	<= X"0000_1C00";

			for i in 0 to 7 loop
				wait until rising_edge(CLK_O) and SRDY_I = '1';
				ADDR_O	<= ADDR_O + 4;
			end loop;

			STB_O	<= '0';
			wait until rising_edge(CLK_O) and dout_cnt = 7;
			CYC_O	<= '0';
		
		end loop;

		------------------------------------------------------------
		wait for 10*CLK_PERIOD;
		------------------------------------------------------------

		for k in 0 to 3 loop
			------------------------------------------------------------
--			wait for 3*CLK_PERIOD;
			------------------------------------------------------------

			-- 8-word burst cycle
			dout_rst	<= '1';
			wait until rising_edge(CLK_O);
			dout_rst	<= '0';

			CYC_O	<= '1';
			STB_O	<= '1';
			WE_O	<= '1';
			sdsel	<= "1111";
			sddat	<= X"1111_0000";
			ADDR_O	<= X"0000_0000";

			for i in 0 to 7 loop
				wait until rising_edge(CLK_O) and SRDY_I = '1';
				sddat	<= sddat + 1;
				ADDR_O	<= ADDR_O + 4;
			end loop;

			STB_O	<= '0';
			wait until rising_edge(CLK_O);
			CYC_O	<= '0';

			------------------------------------------------------------
--			wait for 3*CLK_PERIOD;
			------------------------------------------------------------

			-- 8-word burst cycle
			dout_rst	<= '1';
			wait until rising_edge(CLK_O);
			dout_rst	<= '0';

			CYC_O	<= '1';
			STB_O	<= '1';
			WE_O	<= '1';
			sdsel	<= "1111";
			sddat	<= X"2222_0000";
			ADDR_O	<= X"0000_0400";

			for i in 0 to 7 loop
				wait until rising_edge(CLK_O) and SRDY_I = '1';
				sddat	<= sddat + 1;
				ADDR_O	<= ADDR_O + 4;
			end loop;

			STB_O	<= '0';
			wait until rising_edge(CLK_O);
			CYC_O	<= '0';

			------------------------------------------------------------
--			wait for 3*CLK_PERIOD;
			------------------------------------------------------------

			-- 8-word burst cycle
			dout_rst	<= '1';
			wait until rising_edge(CLK_O);
			dout_rst	<= '0';

			CYC_O	<= '1';
			STB_O	<= '1';
			WE_O	<= '1';
			sdsel	<= "1111";
			sddat	<= X"3333_0000";
			ADDR_O	<= X"0000_0800";

			for i in 0 to 7 loop
				wait until rising_edge(CLK_O) and SRDY_I = '1';
				sddat	<= sddat + 1;
				ADDR_O	<= ADDR_O + 4;
			end loop;

			STB_O	<= '0';
			wait until rising_edge(CLK_O);
			CYC_O	<= '0';

			------------------------------------------------------------
--			wait for 3*CLK_PERIOD;
			------------------------------------------------------------

			-- 8-word burst cycle
			dout_rst	<= '1';
			wait until rising_edge(CLK_O);
			dout_rst	<= '0';

			CYC_O	<= '1';
			STB_O	<= '1';
			WE_O	<= '1';
			sdsel	<= "1111";
			sddat	<= X"4444_0000";
			ADDR_O	<= X"0000_0C00";

			for i in 0 to 7 loop
				wait until rising_edge(CLK_O) and SRDY_I = '1';
				sddat	<= sddat + 1;
				ADDR_O	<= ADDR_O + 4;
			end loop;

			STB_O	<= '0';
			wait until rising_edge(CLK_O);
			CYC_O	<= '0';
		
		end loop;

		------------------------------------------------------------
		wait for 10*CLK_PERIOD;
		------------------------------------------------------------
		
		for k in 0 to 3 loop

			-- 8-word burst cycle
			dout_rst	<= '1';
			wait until rising_edge(CLK_O);
			dout_rst	<= '0';

			CYC_O	<= '1';
			STB_O	<= '1';
			WE_O	<= '1';
			sdsel	<= "1111";
			sddat	<= X"1111_0000";
			ADDR_O	<= X"0000_1000";

			for i in 0 to 7 loop
				wait until rising_edge(CLK_O) and SRDY_I = '1';
				sddat	<= sddat + 1;
				ADDR_O	<= ADDR_O + 4;
			end loop;

			STB_O	<= '0';
			wait until rising_edge(CLK_O);
			CYC_O	<= '0';

			------------------------------------------------------------
--			wait for 3*CLK_PERIOD;
			------------------------------------------------------------

			-- 8-word burst cycle
			dout_rst	<= '1';
			wait until rising_edge(CLK_O);
			dout_rst	<= '0';

			CYC_O	<= '1';
			STB_O	<= '1';
			WE_O	<= '1';
			sdsel	<= "1111";
			sddat	<= X"2222_0000";
			ADDR_O	<= X"0000_1400";

			for i in 0 to 7 loop
				wait until rising_edge(CLK_O) and SRDY_I = '1';
				sddat	<= sddat + 1;
				ADDR_O	<= ADDR_O + 4;
			end loop;

			STB_O	<= '0';
			wait until rising_edge(CLK_O);
			CYC_O	<= '0';

			------------------------------------------------------------
--			wait for 3*CLK_PERIOD;
			------------------------------------------------------------

			-- 8-word burst cycle
			dout_rst	<= '1';
			wait until rising_edge(CLK_O);
			dout_rst	<= '0';

			CYC_O	<= '1';
			STB_O	<= '1';
			WE_O	<= '1';
			sdsel	<= "1111";
			sddat	<= X"3333_0000";
			ADDR_O	<= X"0000_1800";

			for i in 0 to 7 loop
				wait until rising_edge(CLK_O) and SRDY_I = '1';
				sddat	<= sddat + 1;
				ADDR_O	<= ADDR_O + 4;
			end loop;

			STB_O	<= '0';
			wait until rising_edge(CLK_O);
			CYC_O	<= '0';

			------------------------------------------------------------
--			wait for 3*CLK_PERIOD;
			------------------------------------------------------------

			-- 8-word burst cycle
			dout_rst	<= '1';
			wait until rising_edge(CLK_O);
			dout_rst	<= '0';

			CYC_O	<= '1';
			STB_O	<= '1';
			WE_O	<= '1';
			sdsel	<= "1111";
			sddat	<= X"4444_0000";
			ADDR_O	<= X"0000_1C00";

			for i in 0 to 7 loop
				wait until rising_edge(CLK_O) and SRDY_I = '1';
				sddat	<= sddat + 1;
				ADDR_O	<= ADDR_O + 4;
			end loop;

			STB_O	<= '0';
			wait until rising_edge(CLK_O);
			CYC_O	<= '0';
		
		end loop;

		------------------------------------------------------------
		wait for 10*CLK_PERIOD;
		------------------------------------------------------------
		
		for k in 0 to 3 loop

			-- 8-word burst cycle
			dout_rst	<= '1';
			wait until rising_edge(CLK_O);
			dout_rst	<= '0';

			CYC_O	<= '1';
			STB_O	<= '1';
			WE_O	<= '0';
			ADDR_O	<= X"0000_1000";

			for i in 0 to 7 loop
				wait until rising_edge(CLK_O) and SRDY_I = '1';
				ADDR_O	<= ADDR_O + 4;
			end loop;

			STB_O	<= '0';
			wait until rising_edge(CLK_O) and dout_cnt = 7;
			CYC_O	<= '0';

			------------------------------------------------------------
--			wait for 3*CLK_PERIOD;
			------------------------------------------------------------

			-- 8-word burst cycle
			dout_rst	<= '1';
			wait until rising_edge(CLK_O);
			dout_rst	<= '0';

			CYC_O	<= '1';
			STB_O	<= '1';
			WE_O	<= '0';
			ADDR_O	<= X"0000_1400";

			for i in 0 to 7 loop
				wait until rising_edge(CLK_O) and SRDY_I = '1';
				ADDR_O	<= ADDR_O + 4;
			end loop;

			STB_O	<= '0';
			wait until rising_edge(CLK_O) and dout_cnt = 7;
			CYC_O	<= '0';

			------------------------------------------------------------
--			wait for 3*CLK_PERIOD;
			------------------------------------------------------------

			-- 8-word burst cycle
			dout_rst	<= '1';
			wait until rising_edge(CLK_O);
			dout_rst	<= '0';

			CYC_O	<= '1';
			STB_O	<= '1';
			WE_O	<= '0';
			ADDR_O	<= X"0000_1800";

			for i in 0 to 7 loop
				wait until rising_edge(CLK_O) and SRDY_I = '1';
				ADDR_O	<= ADDR_O + 4;
			end loop;

			STB_O	<= '0';
			wait until rising_edge(CLK_O) and dout_cnt = 7;
			CYC_O	<= '0';

			------------------------------------------------------------
--			wait for 3*CLK_PERIOD;
			------------------------------------------------------------

			-- 8-word burst cycle
			dout_rst	<= '1';
			wait until rising_edge(CLK_O);
			dout_rst	<= '0';

			CYC_O	<= '1';
			STB_O	<= '1';
			WE_O	<= '0';
			ADDR_O	<= X"0000_1C00";

			for i in 0 to 7 loop
				wait until rising_edge(CLK_O) and SRDY_I = '1';
				ADDR_O	<= ADDR_O + 4;
			end loop;

			STB_O	<= '0';
			wait until rising_edge(CLK_O) and dout_cnt = 7;
			CYC_O	<= '0';
		
		end loop;

		wait; 
	
	end process;
	
end architecture struct;
