-- Xilinx Vhdl netlist produced by netgen application (version G.30)
-- Command       : -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim eval2clk.nga eval2clk_timesim.vhd 
-- Input file    : eval2clk.nga
-- Output file   : eval2clk_timesim.vhd
-- Design name   : eval2clk.nga
-- # of Entities : 1
-- Xilinx        : D:/Xilinx
-- Device        : XC95288XL-6-TQ144 (Speed File: Version 3.0)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity eval2clk is
  port (
    RES : in STD_LOGIC := 'X'; 
    CLK : in STD_LOGIC := 'X'; 
    dummy_out : out STD_LOGIC; 
    SCLK : out STD_LOGIC 
  );
end eval2clk;

architecture Structure of eval2clk is
  signal SCLK_OBUF : STD_LOGIC; 
  signal FSRIO_1 : STD_LOGIC; 
  signal FCLKIO_0 : STD_LOGIC; 
  signal dummy_out_OBUF_Q : STD_LOGIC; 
  signal SCLK_OBUF_BUF0 : STD_LOGIC; 
  signal dummy_out_OBUF_Q_0 : STD_LOGIC; 
  signal dummy_out_OBUF_D : STD_LOGIC; 
  signal dummy_out_OBUF_tsimcreated_xor_Q : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal dummy_out_OBUF_tsimcreated_prld_Q : STD_LOGIC; 
  signal dummy_out_OBUF_CLKF : STD_LOGIC; 
  signal Gnd : STD_LOGIC; 
  signal dummy_out_OBUF_CE : STD_LOGIC; 
  signal dummy_out_OBUF_D1 : STD_LOGIC; 
  signal dummy_out_OBUF_D2 : STD_LOGIC; 
  signal SCLK1 : STD_LOGIC; 
  signal SCLK1_Q : STD_LOGIC; 
  signal SCLK1_D : STD_LOGIC; 
  signal SCLK1_tsimcreated_xor_Q : STD_LOGIC; 
  signal SCLK1_tsimcreated_prld_Q : STD_LOGIC; 
  signal SCLK1_CE : STD_LOGIC; 
  signal SCLK1_D1 : STD_LOGIC; 
  signal SCLK1_D2 : STD_LOGIC; 
  signal count_0_Q : STD_LOGIC; 
  signal count_0_D : STD_LOGIC; 
  signal count_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal count_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal Vcc : STD_LOGIC; 
  signal count_0_D1 : STD_LOGIC; 
  signal count_0_D2 : STD_LOGIC; 
  signal count_4_Q : STD_LOGIC; 
  signal count_4_D : STD_LOGIC; 
  signal count_4_tsimcreated_xor_Q : STD_LOGIC; 
  signal count_4_tsimcreated_prld_Q : STD_LOGIC; 
  signal count_4_D1 : STD_LOGIC; 
  signal count_4_D2 : STD_LOGIC; 
  signal count_4_D2_PT_0 : STD_LOGIC; 
  signal count_4_D2_PT_1 : STD_LOGIC; 
  signal scount_0_Q : STD_LOGIC; 
  signal scount_0_D : STD_LOGIC; 
  signal scount_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal scount_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal scount_0_CLKF : STD_LOGIC; 
  signal scount_0_D1 : STD_LOGIC; 
  signal scount_0_D2 : STD_LOGIC; 
  signal scount_4_Q : STD_LOGIC; 
  signal scount_4_D : STD_LOGIC; 
  signal scount_4_tsimcreated_xor_Q : STD_LOGIC; 
  signal scount_4_tsimcreated_prld_Q : STD_LOGIC; 
  signal scount_4_CLKF : STD_LOGIC; 
  signal scount_4_D1 : STD_LOGIC; 
  signal scount_4_D2 : STD_LOGIC; 
  signal scount_4_D2_PT_0 : STD_LOGIC; 
  signal scount_4_D2_PT_1 : STD_LOGIC; 
  signal count_1_Q : STD_LOGIC; 
  signal count_1_D : STD_LOGIC; 
  signal count_1_tsimcreated_xor_Q : STD_LOGIC; 
  signal count_1_tsimcreated_prld_Q : STD_LOGIC; 
  signal count_1_D1 : STD_LOGIC; 
  signal count_1_D2 : STD_LOGIC; 
  signal count_1_D2_PT_0 : STD_LOGIC; 
  signal count_1_D2_PT_1 : STD_LOGIC; 
  signal count_2_Q : STD_LOGIC; 
  signal count_2_D : STD_LOGIC; 
  signal count_2_tsimcreated_xor_Q : STD_LOGIC; 
  signal count_2_D1 : STD_LOGIC; 
  signal count_2_D2 : STD_LOGIC; 
  signal count_3_Q : STD_LOGIC; 
  signal count_3_D : STD_LOGIC; 
  signal count_3_tsimcreated_xor_Q : STD_LOGIC; 
  signal count_3_tsimcreated_prld_Q : STD_LOGIC; 
  signal count_3_D1 : STD_LOGIC; 
  signal count_3_D2 : STD_LOGIC; 
  signal count_3_D2_PT_0 : STD_LOGIC; 
  signal count_3_D2_PT_1 : STD_LOGIC; 
  signal count_3_D2_PT_2 : STD_LOGIC; 
  signal scount_1_Q : STD_LOGIC; 
  signal scount_1_D : STD_LOGIC; 
  signal scount_1_tsimcreated_xor_Q : STD_LOGIC; 
  signal scount_1_CLKF : STD_LOGIC; 
  signal scount_1_D1 : STD_LOGIC; 
  signal scount_1_D2 : STD_LOGIC; 
  signal scount_2_Q : STD_LOGIC; 
  signal scount_2_D : STD_LOGIC; 
  signal scount_2_tsimcreated_xor_Q : STD_LOGIC; 
  signal scount_2_tsimcreated_prld_Q : STD_LOGIC; 
  signal scount_2_CLKF : STD_LOGIC; 
  signal scount_2_D1 : STD_LOGIC; 
  signal scount_2_D2 : STD_LOGIC; 
  signal scount_2_D2_PT_0 : STD_LOGIC; 
  signal scount_2_D2_PT_1 : STD_LOGIC; 
  signal scount_2_D2_PT_2 : STD_LOGIC; 
  signal scount_3_Q : STD_LOGIC; 
  signal scount_3_D : STD_LOGIC; 
  signal scount_3_tsimcreated_xor_Q : STD_LOGIC; 
  signal scount_3_tsimcreated_prld_Q : STD_LOGIC; 
  signal scount_3_CLKF : STD_LOGIC; 
  signal scount_3_D1 : STD_LOGIC; 
  signal scount_3_D2 : STD_LOGIC; 
  signal scount_3_D2_PT_0 : STD_LOGIC; 
  signal scount_3_D2_PT_1 : STD_LOGIC; 
  signal scount_3_D2_PT_2 : STD_LOGIC; 
  signal count_5_Q : STD_LOGIC; 
  signal count_5_D : STD_LOGIC; 
  signal count_5_tsimcreated_xor_Q : STD_LOGIC; 
  signal count_5_tsimcreated_prld_Q : STD_LOGIC; 
  signal count_5_D1 : STD_LOGIC; 
  signal count_5_D2 : STD_LOGIC; 
  signal scount_5_Q : STD_LOGIC; 
  signal scount_5_D : STD_LOGIC; 
  signal scount_5_tsimcreated_xor_Q : STD_LOGIC; 
  signal scount_5_tsimcreated_prld_Q : STD_LOGIC; 
  signal scount_5_CLKF : STD_LOGIC; 
  signal scount_5_D1 : STD_LOGIC; 
  signal scount_5_D2 : STD_LOGIC; 
  signal SCLK_OBUF_BUF0_Q : STD_LOGIC; 
  signal SCLK_OBUF_BUF0_D : STD_LOGIC; 
  signal SCLK_OBUF_BUF0_D1 : STD_LOGIC; 
  signal SCLK_OBUF_BUF0_D2 : STD_LOGIC; 
  signal NlwInverterSignal_dummy_out_OBUF_CE_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dummy_out_OBUF_CE_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_dummy_out_OBUF_CE_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_dummy_out_OBUF_CE_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_dummy_out_OBUF_CE_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_dummy_out_OBUF_CE_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SCLK1_CE_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SCLK1_CE_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SCLK1_CE_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SCLK1_CE_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SCLK1_CE_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_SCLK1_CE_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_scount_0_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_scount_0_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_scount_0_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_scount_0_D2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_scount_0_D2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_scount_0_D2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_scount_0_D2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_scount_4_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_scount_4_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_scount_4_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_scount_4_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_scount_4_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_scount_4_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_scount_4_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_scount_4_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_scount_1_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_scount_2_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_scount_2_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_scount_2_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_scount_2_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_scount_2_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_scount_3_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_scount_3_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_scount_3_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_scount_3_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_scount_3_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_scount_3_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_scount_3_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_scount_3_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_scount_3_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_D2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_D2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_D2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_scount_5_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_scount_5_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_scount_5_D2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_scount_5_D2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_scount_5_D2_IN4 : STD_LOGIC; 
  signal scount : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal count : STD_LOGIC_VECTOR ( 5 downto 0 ); 
begin
  SCLK_OBUF_1 : X_BUF
    port map (
      I => RES,
      O => SCLK_OBUF
    );
  FSRIO_1_2 : X_BUF
    port map (
      I => RES,
      O => FSRIO_1
    );
  FCLKIO_0_3 : X_BUF
    port map (
      I => CLK,
      O => FCLKIO_0
    );
  dummy_out_4 : X_BUF
    port map (
      I => dummy_out_OBUF_Q,
      O => dummy_out
    );
  SCLK_5 : X_BUF
    port map (
      I => SCLK_OBUF_BUF0,
      O => SCLK
    );
  dummy_out_OBUF_Q_6 : X_BUF
    port map (
      I => dummy_out_OBUF_Q_0,
      O => dummy_out_OBUF_Q
    );
  dummy_out_OBUF_tsimcreated_xor_Q_7 : X_XOR2
    port map (
      I0 => dummy_out_OBUF_D,
      I1 => dummy_out_OBUF_Q_0,
      O => dummy_out_OBUF_tsimcreated_xor_Q
    );
  dummy_out_OBUF_tsimcreated_prld_Q_8 : X_OR2
    port map (
      I0 => FSRIO_1,
      I1 => PRLD,
      O => dummy_out_OBUF_tsimcreated_prld_Q
    );
  dummy_out_OBUF_REG : X_FF
    port map (
      I => dummy_out_OBUF_tsimcreated_xor_Q,
      CE => dummy_out_OBUF_CE,
      CLK => dummy_out_OBUF_CLKF,
      SET => dummy_out_OBUF_tsimcreated_prld_Q,
      RST => Gnd,
      O => dummy_out_OBUF_Q_0
    );
  Gnd_9 : X_ZERO
    port map (
      O => Gnd
    );
  dummy_out_OBUF_D_10 : X_XOR2
    port map (
      I0 => dummy_out_OBUF_D1,
      I1 => dummy_out_OBUF_D2,
      O => dummy_out_OBUF_D
    );
  dummy_out_OBUF_D1_11 : X_ZERO
    port map (
      O => dummy_out_OBUF_D1
    );
  dummy_out_OBUF_D2_12 : X_ONE
    port map (
      O => dummy_out_OBUF_D2
    );
  dummy_out_OBUF_CLKF_13 : X_AND2
    port map (
      I0 => SCLK1,
      I1 => SCLK1,
      O => dummy_out_OBUF_CLKF
    );
  dummy_out_OBUF_CE_14 : X_AND6
    port map (
      I0 => NlwInverterSignal_dummy_out_OBUF_CE_IN0,
      I1 => NlwInverterSignal_dummy_out_OBUF_CE_IN1,
      I2 => NlwInverterSignal_dummy_out_OBUF_CE_IN2,
      I3 => NlwInverterSignal_dummy_out_OBUF_CE_IN3,
      I4 => NlwInverterSignal_dummy_out_OBUF_CE_IN4,
      I5 => NlwInverterSignal_dummy_out_OBUF_CE_IN5,
      O => dummy_out_OBUF_CE
    );
  SCLK1_15 : X_BUF
    port map (
      I => SCLK1_Q,
      O => SCLK1
    );
  SCLK1_tsimcreated_xor_Q_16 : X_XOR2
    port map (
      I0 => SCLK1_D,
      I1 => SCLK1_Q,
      O => SCLK1_tsimcreated_xor_Q
    );
  SCLK1_tsimcreated_prld_Q_17 : X_OR2
    port map (
      I0 => FSRIO_1,
      I1 => PRLD,
      O => SCLK1_tsimcreated_prld_Q
    );
  SCLK1_REG : X_FF
    port map (
      I => SCLK1_tsimcreated_xor_Q,
      CE => SCLK1_CE,
      CLK => FCLKIO_0,
      SET => SCLK1_tsimcreated_prld_Q,
      RST => Gnd,
      O => SCLK1_Q
    );
  SCLK1_D_18 : X_XOR2
    port map (
      I0 => SCLK1_D1,
      I1 => SCLK1_D2,
      O => SCLK1_D
    );
  SCLK1_D1_19 : X_ZERO
    port map (
      O => SCLK1_D1
    );
  SCLK1_D2_20 : X_ONE
    port map (
      O => SCLK1_D2
    );
  SCLK1_CE_21 : X_AND6
    port map (
      I0 => NlwInverterSignal_SCLK1_CE_IN0,
      I1 => NlwInverterSignal_SCLK1_CE_IN1,
      I2 => NlwInverterSignal_SCLK1_CE_IN2,
      I3 => NlwInverterSignal_SCLK1_CE_IN3,
      I4 => NlwInverterSignal_SCLK1_CE_IN4,
      I5 => NlwInverterSignal_SCLK1_CE_IN5,
      O => SCLK1_CE
    );
  count_0_Q_22 : X_BUF
    port map (
      I => count_0_Q,
      O => count(0)
    );
  count_0_tsimcreated_xor_Q_23 : X_XOR2
    port map (
      I0 => count_0_D,
      I1 => count_0_Q,
      O => count_0_tsimcreated_xor_Q
    );
  count_0_tsimcreated_prld_Q_24 : X_OR2
    port map (
      I0 => FSRIO_1,
      I1 => PRLD,
      O => count_0_tsimcreated_prld_Q
    );
  count_0_REG : X_FF
    port map (
      I => count_0_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => count_0_tsimcreated_prld_Q,
      O => count_0_Q
    );
  Vcc_25 : X_ONE
    port map (
      O => Vcc
    );
  count_0_D_26 : X_XOR2
    port map (
      I0 => NlwInverterSignal_count_0_D_IN0,
      I1 => count_0_D2,
      O => count_0_D
    );
  count_0_D1_27 : X_ZERO
    port map (
      O => count_0_D1
    );
  count_0_D2_28 : X_AND6
    port map (
      I0 => NlwInverterSignal_count_0_D2_IN0,
      I1 => NlwInverterSignal_count_0_D2_IN1,
      I2 => NlwInverterSignal_count_0_D2_IN2,
      I3 => NlwInverterSignal_count_0_D2_IN3,
      I4 => NlwInverterSignal_count_0_D2_IN4,
      I5 => NlwInverterSignal_count_0_D2_IN5,
      O => count_0_D2
    );
  count_4_Q_29 : X_BUF
    port map (
      I => count_4_Q,
      O => count(4)
    );
  count_4_tsimcreated_xor_Q_30 : X_XOR2
    port map (
      I0 => count_4_D,
      I1 => count_4_Q,
      O => count_4_tsimcreated_xor_Q
    );
  count_4_tsimcreated_prld_Q_31 : X_OR2
    port map (
      I0 => FSRIO_1,
      I1 => PRLD,
      O => count_4_tsimcreated_prld_Q
    );
  count_4_REG : X_FF
    port map (
      I => count_4_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => count_4_tsimcreated_prld_Q,
      O => count_4_Q
    );
  count_4_D_32 : X_XOR2
    port map (
      I0 => count_4_D1,
      I1 => count_4_D2,
      O => count_4_D
    );
  count_4_D1_33 : X_ZERO
    port map (
      O => count_4_D1
    );
  count_4_D2_PT_0_34 : X_AND5
    port map (
      I0 => NlwInverterSignal_count_4_D2_PT_0_IN0,
      I1 => count(4),
      I2 => NlwInverterSignal_count_4_D2_PT_0_IN2,
      I3 => NlwInverterSignal_count_4_D2_PT_0_IN3,
      I4 => NlwInverterSignal_count_4_D2_PT_0_IN4,
      O => count_4_D2_PT_0
    );
  count_4_D2_PT_1_35 : X_AND5
    port map (
      I0 => NlwInverterSignal_count_4_D2_PT_1_IN0,
      I1 => NlwInverterSignal_count_4_D2_PT_1_IN1,
      I2 => NlwInverterSignal_count_4_D2_PT_1_IN2,
      I3 => NlwInverterSignal_count_4_D2_PT_1_IN3,
      I4 => count(5),
      O => count_4_D2_PT_1
    );
  count_4_D2_36 : X_OR2
    port map (
      I0 => count_4_D2_PT_0,
      I1 => count_4_D2_PT_1,
      O => count_4_D2
    );
  scount_0_Q_37 : X_BUF
    port map (
      I => scount_0_Q,
      O => scount(0)
    );
  scount_0_tsimcreated_xor_Q_38 : X_XOR2
    port map (
      I0 => scount_0_D,
      I1 => scount_0_Q,
      O => scount_0_tsimcreated_xor_Q
    );
  scount_0_tsimcreated_prld_Q_39 : X_OR2
    port map (
      I0 => FSRIO_1,
      I1 => PRLD,
      O => scount_0_tsimcreated_prld_Q
    );
  scount_0_REG : X_FF
    port map (
      I => scount_0_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => scount_0_CLKF,
      SET => Gnd,
      RST => scount_0_tsimcreated_prld_Q,
      O => scount_0_Q
    );
  scount_0_D_40 : X_XOR2
    port map (
      I0 => NlwInverterSignal_scount_0_D_IN0,
      I1 => scount_0_D2,
      O => scount_0_D
    );
  scount_0_D1_41 : X_ZERO
    port map (
      O => scount_0_D1
    );
  scount_0_D2_42 : X_AND6
    port map (
      I0 => NlwInverterSignal_scount_0_D2_IN0,
      I1 => NlwInverterSignal_scount_0_D2_IN1,
      I2 => NlwInverterSignal_scount_0_D2_IN2,
      I3 => NlwInverterSignal_scount_0_D2_IN3,
      I4 => NlwInverterSignal_scount_0_D2_IN4,
      I5 => NlwInverterSignal_scount_0_D2_IN5,
      O => scount_0_D2
    );
  scount_0_CLKF_43 : X_AND2
    port map (
      I0 => SCLK1,
      I1 => SCLK1,
      O => scount_0_CLKF
    );
  scount_4_Q_44 : X_BUF
    port map (
      I => scount_4_Q,
      O => scount(4)
    );
  scount_4_tsimcreated_xor_Q_45 : X_XOR2
    port map (
      I0 => scount_4_D,
      I1 => scount_4_Q,
      O => scount_4_tsimcreated_xor_Q
    );
  scount_4_tsimcreated_prld_Q_46 : X_OR2
    port map (
      I0 => FSRIO_1,
      I1 => PRLD,
      O => scount_4_tsimcreated_prld_Q
    );
  scount_4_REG : X_FF
    port map (
      I => scount_4_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => scount_4_CLKF,
      SET => Gnd,
      RST => scount_4_tsimcreated_prld_Q,
      O => scount_4_Q
    );
  scount_4_D_47 : X_XOR2
    port map (
      I0 => scount_4_D1,
      I1 => scount_4_D2,
      O => scount_4_D
    );
  scount_4_D1_48 : X_ZERO
    port map (
      O => scount_4_D1
    );
  scount_4_D2_PT_0_49 : X_AND5
    port map (
      I0 => NlwInverterSignal_scount_4_D2_PT_0_IN0,
      I1 => scount(4),
      I2 => NlwInverterSignal_scount_4_D2_PT_0_IN2,
      I3 => NlwInverterSignal_scount_4_D2_PT_0_IN3,
      I4 => NlwInverterSignal_scount_4_D2_PT_0_IN4,
      O => scount_4_D2_PT_0
    );
  scount_4_D2_PT_1_50 : X_AND5
    port map (
      I0 => NlwInverterSignal_scount_4_D2_PT_1_IN0,
      I1 => NlwInverterSignal_scount_4_D2_PT_1_IN1,
      I2 => NlwInverterSignal_scount_4_D2_PT_1_IN2,
      I3 => NlwInverterSignal_scount_4_D2_PT_1_IN3,
      I4 => scount(5),
      O => scount_4_D2_PT_1
    );
  scount_4_D2_51 : X_OR2
    port map (
      I0 => scount_4_D2_PT_0,
      I1 => scount_4_D2_PT_1,
      O => scount_4_D2
    );
  scount_4_CLKF_52 : X_AND2
    port map (
      I0 => SCLK1,
      I1 => SCLK1,
      O => scount_4_CLKF
    );
  count_1_Q_53 : X_BUF
    port map (
      I => count_1_Q,
      O => count(1)
    );
  count_1_tsimcreated_xor_Q_54 : X_XOR2
    port map (
      I0 => count_1_D,
      I1 => count_1_Q,
      O => count_1_tsimcreated_xor_Q
    );
  count_1_tsimcreated_prld_Q_55 : X_OR2
    port map (
      I0 => FSRIO_1,
      I1 => PRLD,
      O => count_1_tsimcreated_prld_Q
    );
  count_1_REG : X_FF
    port map (
      I => count_1_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => count_1_tsimcreated_prld_Q,
      O => count_1_Q
    );
  count_1_D_56 : X_XOR2
    port map (
      I0 => NlwInverterSignal_count_1_D_IN0,
      I1 => count_1_D2,
      O => count_1_D
    );
  count_1_D1_57 : X_ZERO
    port map (
      O => count_1_D1
    );
  count_1_D2_PT_0_58 : X_AND2
    port map (
      I0 => count(0),
      I1 => count(0),
      O => count_1_D2_PT_0
    );
  count_1_D2_PT_1_59 : X_AND5
    port map (
      I0 => NlwInverterSignal_count_1_D2_PT_1_IN0,
      I1 => NlwInverterSignal_count_1_D2_PT_1_IN1,
      I2 => NlwInverterSignal_count_1_D2_PT_1_IN2,
      I3 => NlwInverterSignal_count_1_D2_PT_1_IN3,
      I4 => NlwInverterSignal_count_1_D2_PT_1_IN4,
      O => count_1_D2_PT_1
    );
  count_1_D2_60 : X_OR2
    port map (
      I0 => count_1_D2_PT_0,
      I1 => count_1_D2_PT_1,
      O => count_1_D2
    );
  count_2_Q_61 : X_BUF
    port map (
      I => count_2_Q,
      O => count(2)
    );
  count_2_tsimcreated_xor_Q_62 : X_XOR2
    port map (
      I0 => count_2_D,
      I1 => count_2_Q,
      O => count_2_tsimcreated_xor_Q
    );
  count_2_REG : X_FF
    port map (
      I => count_2_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => FSRIO_1,
      RST => PRLD,
      O => count_2_Q
    );
  count_2_D_63 : X_XOR2
    port map (
      I0 => count_2_D1,
      I1 => count_2_D2,
      O => count_2_D
    );
  count_2_D1_64 : X_ZERO
    port map (
      O => count_2_D1
    );
  count_2_D2_65 : X_AND2
    port map (
      I0 => NlwInverterSignal_count_2_D2_IN0,
      I1 => NlwInverterSignal_count_2_D2_IN1,
      O => count_2_D2
    );
  count_3_Q_66 : X_BUF
    port map (
      I => count_3_Q,
      O => count(3)
    );
  count_3_tsimcreated_xor_Q_67 : X_XOR2
    port map (
      I0 => count_3_D,
      I1 => count_3_Q,
      O => count_3_tsimcreated_xor_Q
    );
  count_3_tsimcreated_prld_Q_68 : X_OR2
    port map (
      I0 => FSRIO_1,
      I1 => PRLD,
      O => count_3_tsimcreated_prld_Q
    );
  count_3_REG : X_FF
    port map (
      I => count_3_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => count_3_tsimcreated_prld_Q,
      O => count_3_Q
    );
  count_3_D_69 : X_XOR2
    port map (
      I0 => count_3_D1,
      I1 => count_3_D2,
      O => count_3_D
    );
  count_3_D1_70 : X_ZERO
    port map (
      O => count_3_D1
    );
  count_3_D2_PT_0_71 : X_AND4
    port map (
      I0 => NlwInverterSignal_count_3_D2_PT_0_IN0,
      I1 => count(4),
      I2 => NlwInverterSignal_count_3_D2_PT_0_IN2,
      I3 => NlwInverterSignal_count_3_D2_PT_0_IN3,
      O => count_3_D2_PT_0
    );
  count_3_D2_PT_1_72 : X_AND4
    port map (
      I0 => NlwInverterSignal_count_3_D2_PT_1_IN0,
      I1 => NlwInverterSignal_count_3_D2_PT_1_IN1,
      I2 => NlwInverterSignal_count_3_D2_PT_1_IN2,
      I3 => count(3),
      O => count_3_D2_PT_1
    );
  count_3_D2_PT_2_73 : X_AND4
    port map (
      I0 => NlwInverterSignal_count_3_D2_PT_2_IN0,
      I1 => NlwInverterSignal_count_3_D2_PT_2_IN1,
      I2 => NlwInverterSignal_count_3_D2_PT_2_IN2,
      I3 => count(5),
      O => count_3_D2_PT_2
    );
  count_3_D2_74 : X_OR3
    port map (
      I0 => count_3_D2_PT_0,
      I1 => count_3_D2_PT_1,
      I2 => count_3_D2_PT_2,
      O => count_3_D2
    );
  scount_1_Q_75 : X_BUF
    port map (
      I => scount_1_Q,
      O => scount(1)
    );
  scount_1_tsimcreated_xor_Q_76 : X_XOR2
    port map (
      I0 => scount_1_D,
      I1 => scount_1_Q,
      O => scount_1_tsimcreated_xor_Q
    );
  scount_1_REG : X_FF
    port map (
      I => scount_1_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => scount_1_CLKF,
      SET => FSRIO_1,
      RST => PRLD,
      O => scount_1_Q
    );
  scount_1_D_77 : X_XOR2
    port map (
      I0 => NlwInverterSignal_scount_1_D_IN0,
      I1 => scount_1_D2,
      O => scount_1_D
    );
  scount_1_D1_78 : X_ZERO
    port map (
      O => scount_1_D1
    );
  scount_1_D2_79 : X_AND2
    port map (
      I0 => scount(0),
      I1 => scount(0),
      O => scount_1_D2
    );
  scount_1_CLKF_80 : X_AND2
    port map (
      I0 => SCLK1,
      I1 => SCLK1,
      O => scount_1_CLKF
    );
  scount_2_Q_81 : X_BUF
    port map (
      I => scount_2_Q,
      O => scount(2)
    );
  scount_2_tsimcreated_xor_Q_82 : X_XOR2
    port map (
      I0 => scount_2_D,
      I1 => scount_2_Q,
      O => scount_2_tsimcreated_xor_Q
    );
  scount_2_tsimcreated_prld_Q_83 : X_OR2
    port map (
      I0 => FSRIO_1,
      I1 => PRLD,
      O => scount_2_tsimcreated_prld_Q
    );
  scount_2_REG : X_FF
    port map (
      I => scount_2_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => scount_2_CLKF,
      SET => Gnd,
      RST => scount_2_tsimcreated_prld_Q,
      O => scount_2_Q
    );
  scount_2_D_84 : X_XOR2
    port map (
      I0 => NlwInverterSignal_scount_2_D_IN0,
      I1 => scount_2_D2,
      O => scount_2_D
    );
  scount_2_D1_85 : X_ZERO
    port map (
      O => scount_2_D1
    );
  scount_2_D2_PT_0_86 : X_AND2
    port map (
      I0 => scount(0),
      I1 => scount(0),
      O => scount_2_D2_PT_0
    );
  scount_2_D2_PT_1_87 : X_AND2
    port map (
      I0 => scount(1),
      I1 => scount(1),
      O => scount_2_D2_PT_1
    );
  scount_2_D2_PT_2_88 : X_AND4
    port map (
      I0 => NlwInverterSignal_scount_2_D2_PT_2_IN0,
      I1 => NlwInverterSignal_scount_2_D2_PT_2_IN1,
      I2 => NlwInverterSignal_scount_2_D2_PT_2_IN2,
      I3 => NlwInverterSignal_scount_2_D2_PT_2_IN3,
      O => scount_2_D2_PT_2
    );
  scount_2_D2_89 : X_OR3
    port map (
      I0 => scount_2_D2_PT_0,
      I1 => scount_2_D2_PT_1,
      I2 => scount_2_D2_PT_2,
      O => scount_2_D2
    );
  scount_2_CLKF_90 : X_AND2
    port map (
      I0 => SCLK1,
      I1 => SCLK1,
      O => scount_2_CLKF
    );
  scount_3_Q_91 : X_BUF
    port map (
      I => scount_3_Q,
      O => scount(3)
    );
  scount_3_tsimcreated_xor_Q_92 : X_XOR2
    port map (
      I0 => scount_3_D,
      I1 => scount_3_Q,
      O => scount_3_tsimcreated_xor_Q
    );
  scount_3_tsimcreated_prld_Q_93 : X_OR2
    port map (
      I0 => FSRIO_1,
      I1 => PRLD,
      O => scount_3_tsimcreated_prld_Q
    );
  scount_3_REG : X_FF
    port map (
      I => scount_3_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => scount_3_CLKF,
      SET => Gnd,
      RST => scount_3_tsimcreated_prld_Q,
      O => scount_3_Q
    );
  scount_3_D_94 : X_XOR2
    port map (
      I0 => scount_3_D1,
      I1 => scount_3_D2,
      O => scount_3_D
    );
  scount_3_D1_95 : X_ZERO
    port map (
      O => scount_3_D1
    );
  scount_3_D2_PT_0_96 : X_AND4
    port map (
      I0 => NlwInverterSignal_scount_3_D2_PT_0_IN0,
      I1 => scount(4),
      I2 => NlwInverterSignal_scount_3_D2_PT_0_IN2,
      I3 => NlwInverterSignal_scount_3_D2_PT_0_IN3,
      O => scount_3_D2_PT_0
    );
  scount_3_D2_PT_1_97 : X_AND4
    port map (
      I0 => NlwInverterSignal_scount_3_D2_PT_1_IN0,
      I1 => NlwInverterSignal_scount_3_D2_PT_1_IN1,
      I2 => NlwInverterSignal_scount_3_D2_PT_1_IN2,
      I3 => scount(3),
      O => scount_3_D2_PT_1
    );
  scount_3_D2_PT_2_98 : X_AND4
    port map (
      I0 => NlwInverterSignal_scount_3_D2_PT_2_IN0,
      I1 => NlwInverterSignal_scount_3_D2_PT_2_IN1,
      I2 => NlwInverterSignal_scount_3_D2_PT_2_IN2,
      I3 => scount(5),
      O => scount_3_D2_PT_2
    );
  scount_3_D2_99 : X_OR3
    port map (
      I0 => scount_3_D2_PT_0,
      I1 => scount_3_D2_PT_1,
      I2 => scount_3_D2_PT_2,
      O => scount_3_D2
    );
  scount_3_CLKF_100 : X_AND2
    port map (
      I0 => SCLK1,
      I1 => SCLK1,
      O => scount_3_CLKF
    );
  count_5_Q_101 : X_BUF
    port map (
      I => count_5_Q,
      O => count(5)
    );
  count_5_tsimcreated_xor_Q_102 : X_XOR2
    port map (
      I0 => count_5_D,
      I1 => count_5_Q,
      O => count_5_tsimcreated_xor_Q
    );
  count_5_tsimcreated_prld_Q_103 : X_OR2
    port map (
      I0 => FSRIO_1,
      I1 => PRLD,
      O => count_5_tsimcreated_prld_Q
    );
  count_5_REG : X_FF
    port map (
      I => count_5_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => count_5_tsimcreated_prld_Q,
      O => count_5_Q
    );
  count_5_D_104 : X_XOR2
    port map (
      I0 => count_5_D1,
      I1 => count_5_D2,
      O => count_5_D
    );
  count_5_D1_105 : X_ZERO
    port map (
      O => count_5_D1
    );
  count_5_D2_106 : X_AND6
    port map (
      I0 => NlwInverterSignal_count_5_D2_IN0,
      I1 => NlwInverterSignal_count_5_D2_IN1,
      I2 => NlwInverterSignal_count_5_D2_IN2,
      I3 => NlwInverterSignal_count_5_D2_IN3,
      I4 => NlwInverterSignal_count_5_D2_IN4,
      I5 => count(5),
      O => count_5_D2
    );
  scount_5_Q_107 : X_BUF
    port map (
      I => scount_5_Q,
      O => scount(5)
    );
  scount_5_tsimcreated_xor_Q_108 : X_XOR2
    port map (
      I0 => scount_5_D,
      I1 => scount_5_Q,
      O => scount_5_tsimcreated_xor_Q
    );
  scount_5_tsimcreated_prld_Q_109 : X_OR2
    port map (
      I0 => FSRIO_1,
      I1 => PRLD,
      O => scount_5_tsimcreated_prld_Q
    );
  scount_5_REG : X_FF
    port map (
      I => scount_5_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => scount_5_CLKF,
      SET => Gnd,
      RST => scount_5_tsimcreated_prld_Q,
      O => scount_5_Q
    );
  scount_5_D_110 : X_XOR2
    port map (
      I0 => scount_5_D1,
      I1 => scount_5_D2,
      O => scount_5_D
    );
  scount_5_D1_111 : X_ZERO
    port map (
      O => scount_5_D1
    );
  scount_5_D2_112 : X_AND6
    port map (
      I0 => NlwInverterSignal_scount_5_D2_IN0,
      I1 => NlwInverterSignal_scount_5_D2_IN1,
      I2 => NlwInverterSignal_scount_5_D2_IN2,
      I3 => NlwInverterSignal_scount_5_D2_IN3,
      I4 => NlwInverterSignal_scount_5_D2_IN4,
      I5 => scount(5),
      O => scount_5_D2
    );
  scount_5_CLKF_113 : X_AND2
    port map (
      I0 => SCLK1,
      I1 => SCLK1,
      O => scount_5_CLKF
    );
  SCLK_OBUF_BUF0_114 : X_BUF
    port map (
      I => SCLK_OBUF_BUF0_Q,
      O => SCLK_OBUF_BUF0
    );
  SCLK_OBUF_BUF0_Q_115 : X_BUF
    port map (
      I => SCLK_OBUF_BUF0_D,
      O => SCLK_OBUF_BUF0_Q
    );
  SCLK_OBUF_BUF0_D_116 : X_XOR2
    port map (
      I0 => SCLK_OBUF_BUF0_D1,
      I1 => SCLK_OBUF_BUF0_D2,
      O => SCLK_OBUF_BUF0_D
    );
  SCLK_OBUF_BUF0_D1_117 : X_ZERO
    port map (
      O => SCLK_OBUF_BUF0_D1
    );
  SCLK_OBUF_BUF0_D2_118 : X_AND2
    port map (
      I0 => SCLK_OBUF,
      I1 => SCLK_OBUF,
      O => SCLK_OBUF_BUF0_D2
    );
  NlwInverterBlock_dummy_out_OBUF_CE_IN0 : X_INV
    port map (
      I => scount(0),
      O => NlwInverterSignal_dummy_out_OBUF_CE_IN0
    );
  NlwInverterBlock_dummy_out_OBUF_CE_IN1 : X_INV
    port map (
      I => scount(4),
      O => NlwInverterSignal_dummy_out_OBUF_CE_IN1
    );
  NlwInverterBlock_dummy_out_OBUF_CE_IN2 : X_INV
    port map (
      I => scount(1),
      O => NlwInverterSignal_dummy_out_OBUF_CE_IN2
    );
  NlwInverterBlock_dummy_out_OBUF_CE_IN3 : X_INV
    port map (
      I => scount(2),
      O => NlwInverterSignal_dummy_out_OBUF_CE_IN3
    );
  NlwInverterBlock_dummy_out_OBUF_CE_IN4 : X_INV
    port map (
      I => scount(3),
      O => NlwInverterSignal_dummy_out_OBUF_CE_IN4
    );
  NlwInverterBlock_dummy_out_OBUF_CE_IN5 : X_INV
    port map (
      I => scount(5),
      O => NlwInverterSignal_dummy_out_OBUF_CE_IN5
    );
  NlwInverterBlock_SCLK1_CE_IN0 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_SCLK1_CE_IN0
    );
  NlwInverterBlock_SCLK1_CE_IN1 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_SCLK1_CE_IN1
    );
  NlwInverterBlock_SCLK1_CE_IN2 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_SCLK1_CE_IN2
    );
  NlwInverterBlock_SCLK1_CE_IN3 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_SCLK1_CE_IN3
    );
  NlwInverterBlock_SCLK1_CE_IN4 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_SCLK1_CE_IN4
    );
  NlwInverterBlock_SCLK1_CE_IN5 : X_INV
    port map (
      I => count(5),
      O => NlwInverterSignal_SCLK1_CE_IN5
    );
  NlwInverterBlock_count_0_D_IN0 : X_INV
    port map (
      I => count_0_D1,
      O => NlwInverterSignal_count_0_D_IN0
    );
  NlwInverterBlock_count_0_D2_IN0 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_count_0_D2_IN0
    );
  NlwInverterBlock_count_0_D2_IN1 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_count_0_D2_IN1
    );
  NlwInverterBlock_count_0_D2_IN2 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_0_D2_IN2
    );
  NlwInverterBlock_count_0_D2_IN3 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_0_D2_IN3
    );
  NlwInverterBlock_count_0_D2_IN4 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_count_0_D2_IN4
    );
  NlwInverterBlock_count_0_D2_IN5 : X_INV
    port map (
      I => count(5),
      O => NlwInverterSignal_count_0_D2_IN5
    );
  NlwInverterBlock_count_4_D2_PT_0_IN0 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_count_4_D2_PT_0_IN0
    );
  NlwInverterBlock_count_4_D2_PT_0_IN2 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_4_D2_PT_0_IN2
    );
  NlwInverterBlock_count_4_D2_PT_0_IN3 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_4_D2_PT_0_IN3
    );
  NlwInverterBlock_count_4_D2_PT_0_IN4 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_count_4_D2_PT_0_IN4
    );
  NlwInverterBlock_count_4_D2_PT_1_IN0 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_count_4_D2_PT_1_IN0
    );
  NlwInverterBlock_count_4_D2_PT_1_IN1 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_4_D2_PT_1_IN1
    );
  NlwInverterBlock_count_4_D2_PT_1_IN2 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_4_D2_PT_1_IN2
    );
  NlwInverterBlock_count_4_D2_PT_1_IN3 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_count_4_D2_PT_1_IN3
    );
  NlwInverterBlock_scount_0_D_IN0 : X_INV
    port map (
      I => scount_0_D1,
      O => NlwInverterSignal_scount_0_D_IN0
    );
  NlwInverterBlock_scount_0_D2_IN0 : X_INV
    port map (
      I => scount(0),
      O => NlwInverterSignal_scount_0_D2_IN0
    );
  NlwInverterBlock_scount_0_D2_IN1 : X_INV
    port map (
      I => scount(4),
      O => NlwInverterSignal_scount_0_D2_IN1
    );
  NlwInverterBlock_scount_0_D2_IN2 : X_INV
    port map (
      I => scount(1),
      O => NlwInverterSignal_scount_0_D2_IN2
    );
  NlwInverterBlock_scount_0_D2_IN3 : X_INV
    port map (
      I => scount(2),
      O => NlwInverterSignal_scount_0_D2_IN3
    );
  NlwInverterBlock_scount_0_D2_IN4 : X_INV
    port map (
      I => scount(3),
      O => NlwInverterSignal_scount_0_D2_IN4
    );
  NlwInverterBlock_scount_0_D2_IN5 : X_INV
    port map (
      I => scount(5),
      O => NlwInverterSignal_scount_0_D2_IN5
    );
  NlwInverterBlock_scount_4_D2_PT_0_IN0 : X_INV
    port map (
      I => scount(0),
      O => NlwInverterSignal_scount_4_D2_PT_0_IN0
    );
  NlwInverterBlock_scount_4_D2_PT_0_IN2 : X_INV
    port map (
      I => scount(1),
      O => NlwInverterSignal_scount_4_D2_PT_0_IN2
    );
  NlwInverterBlock_scount_4_D2_PT_0_IN3 : X_INV
    port map (
      I => scount(2),
      O => NlwInverterSignal_scount_4_D2_PT_0_IN3
    );
  NlwInverterBlock_scount_4_D2_PT_0_IN4 : X_INV
    port map (
      I => scount(3),
      O => NlwInverterSignal_scount_4_D2_PT_0_IN4
    );
  NlwInverterBlock_scount_4_D2_PT_1_IN0 : X_INV
    port map (
      I => scount(0),
      O => NlwInverterSignal_scount_4_D2_PT_1_IN0
    );
  NlwInverterBlock_scount_4_D2_PT_1_IN1 : X_INV
    port map (
      I => scount(1),
      O => NlwInverterSignal_scount_4_D2_PT_1_IN1
    );
  NlwInverterBlock_scount_4_D2_PT_1_IN2 : X_INV
    port map (
      I => scount(2),
      O => NlwInverterSignal_scount_4_D2_PT_1_IN2
    );
  NlwInverterBlock_scount_4_D2_PT_1_IN3 : X_INV
    port map (
      I => scount(3),
      O => NlwInverterSignal_scount_4_D2_PT_1_IN3
    );
  NlwInverterBlock_count_1_D_IN0 : X_INV
    port map (
      I => count_1_D1,
      O => NlwInverterSignal_count_1_D_IN0
    );
  NlwInverterBlock_count_1_D2_PT_1_IN0 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_count_1_D2_PT_1_IN0
    );
  NlwInverterBlock_count_1_D2_PT_1_IN1 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_1_D2_PT_1_IN1
    );
  NlwInverterBlock_count_1_D2_PT_1_IN2 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_1_D2_PT_1_IN2
    );
  NlwInverterBlock_count_1_D2_PT_1_IN3 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_count_1_D2_PT_1_IN3
    );
  NlwInverterBlock_count_1_D2_PT_1_IN4 : X_INV
    port map (
      I => count(5),
      O => NlwInverterSignal_count_1_D2_PT_1_IN4
    );
  NlwInverterBlock_count_2_D2_IN0 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_count_2_D2_IN0
    );
  NlwInverterBlock_count_2_D2_IN1 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_2_D2_IN1
    );
  NlwInverterBlock_count_3_D2_PT_0_IN0 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_count_3_D2_PT_0_IN0
    );
  NlwInverterBlock_count_3_D2_PT_0_IN2 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_3_D2_PT_0_IN2
    );
  NlwInverterBlock_count_3_D2_PT_0_IN3 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_3_D2_PT_0_IN3
    );
  NlwInverterBlock_count_3_D2_PT_1_IN0 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_count_3_D2_PT_1_IN0
    );
  NlwInverterBlock_count_3_D2_PT_1_IN1 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_3_D2_PT_1_IN1
    );
  NlwInverterBlock_count_3_D2_PT_1_IN2 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_3_D2_PT_1_IN2
    );
  NlwInverterBlock_count_3_D2_PT_2_IN0 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_count_3_D2_PT_2_IN0
    );
  NlwInverterBlock_count_3_D2_PT_2_IN1 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_3_D2_PT_2_IN1
    );
  NlwInverterBlock_count_3_D2_PT_2_IN2 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_3_D2_PT_2_IN2
    );
  NlwInverterBlock_scount_1_D_IN0 : X_INV
    port map (
      I => scount_1_D1,
      O => NlwInverterSignal_scount_1_D_IN0
    );
  NlwInverterBlock_scount_2_D_IN0 : X_INV
    port map (
      I => scount_2_D1,
      O => NlwInverterSignal_scount_2_D_IN0
    );
  NlwInverterBlock_scount_2_D2_PT_2_IN0 : X_INV
    port map (
      I => scount(4),
      O => NlwInverterSignal_scount_2_D2_PT_2_IN0
    );
  NlwInverterBlock_scount_2_D2_PT_2_IN1 : X_INV
    port map (
      I => scount(2),
      O => NlwInverterSignal_scount_2_D2_PT_2_IN1
    );
  NlwInverterBlock_scount_2_D2_PT_2_IN2 : X_INV
    port map (
      I => scount(3),
      O => NlwInverterSignal_scount_2_D2_PT_2_IN2
    );
  NlwInverterBlock_scount_2_D2_PT_2_IN3 : X_INV
    port map (
      I => scount(5),
      O => NlwInverterSignal_scount_2_D2_PT_2_IN3
    );
  NlwInverterBlock_scount_3_D2_PT_0_IN0 : X_INV
    port map (
      I => scount(0),
      O => NlwInverterSignal_scount_3_D2_PT_0_IN0
    );
  NlwInverterBlock_scount_3_D2_PT_0_IN2 : X_INV
    port map (
      I => scount(1),
      O => NlwInverterSignal_scount_3_D2_PT_0_IN2
    );
  NlwInverterBlock_scount_3_D2_PT_0_IN3 : X_INV
    port map (
      I => scount(2),
      O => NlwInverterSignal_scount_3_D2_PT_0_IN3
    );
  NlwInverterBlock_scount_3_D2_PT_1_IN0 : X_INV
    port map (
      I => scount(0),
      O => NlwInverterSignal_scount_3_D2_PT_1_IN0
    );
  NlwInverterBlock_scount_3_D2_PT_1_IN1 : X_INV
    port map (
      I => scount(1),
      O => NlwInverterSignal_scount_3_D2_PT_1_IN1
    );
  NlwInverterBlock_scount_3_D2_PT_1_IN2 : X_INV
    port map (
      I => scount(2),
      O => NlwInverterSignal_scount_3_D2_PT_1_IN2
    );
  NlwInverterBlock_scount_3_D2_PT_2_IN0 : X_INV
    port map (
      I => scount(0),
      O => NlwInverterSignal_scount_3_D2_PT_2_IN0
    );
  NlwInverterBlock_scount_3_D2_PT_2_IN1 : X_INV
    port map (
      I => scount(1),
      O => NlwInverterSignal_scount_3_D2_PT_2_IN1
    );
  NlwInverterBlock_scount_3_D2_PT_2_IN2 : X_INV
    port map (
      I => scount(2),
      O => NlwInverterSignal_scount_3_D2_PT_2_IN2
    );
  NlwInverterBlock_count_5_D2_IN0 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_count_5_D2_IN0
    );
  NlwInverterBlock_count_5_D2_IN1 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_count_5_D2_IN1
    );
  NlwInverterBlock_count_5_D2_IN2 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_5_D2_IN2
    );
  NlwInverterBlock_count_5_D2_IN3 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_5_D2_IN3
    );
  NlwInverterBlock_count_5_D2_IN4 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_count_5_D2_IN4
    );
  NlwInverterBlock_scount_5_D2_IN0 : X_INV
    port map (
      I => scount(0),
      O => NlwInverterSignal_scount_5_D2_IN0
    );
  NlwInverterBlock_scount_5_D2_IN1 : X_INV
    port map (
      I => scount(4),
      O => NlwInverterSignal_scount_5_D2_IN1
    );
  NlwInverterBlock_scount_5_D2_IN2 : X_INV
    port map (
      I => scount(1),
      O => NlwInverterSignal_scount_5_D2_IN2
    );
  NlwInverterBlock_scount_5_D2_IN3 : X_INV
    port map (
      I => scount(2),
      O => NlwInverterSignal_scount_5_D2_IN3
    );
  NlwInverterBlock_scount_5_D2_IN4 : X_INV
    port map (
      I => scount(3),
      O => NlwInverterSignal_scount_5_D2_IN4
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => PRLD);

end Structure;

