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-- Company: 
-- Engineer:
--
-- Create Date:   17:16:42 13.05.2007
-- Design Name:   tb_mix_cpx
-- Module Name:   tb_mix_cpx.vhd
-- Project Name:  mix_cpx
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
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LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; --  Imports the standard textio package.

library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;

library work;
use work.PCK_FIO.all;
use work.fixed_util_pkg.all;

ENTITY tb_cic_c_pipe IS
	Generic
	(
		max_width		: integer := 32;
		max_width_frac	: integer := 20
	);
END tb_cic_c_pipe;

ARCHITECTURE behavior OF tb_cic_c_pipe IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT cic_c_pipe
	GENERIC
	(
		max_diff_delay	: integer;
		max_width		: integer;
		max_width_frac	: integer
	);
	PORT
	(
		clk			: in std_logic;
		rst			: in std_logic;
		vld_in		: in std_logic;
		diff_delay	: in natural range 1 to max_diff_delay;
		din			: in sfixed;
		dout		: out sfixed;
		vld_out 	: out std_logic
	);
	END COMPONENT;

	--Constants
	constant PERIOD : time := 10 ns;
	

	--Inputs
	SIGNAL clk			: std_logic := '0';
	SIGNAL srst			: std_logic := '1';
	SIGNAL vld_in		: std_logic := '0';
	SIGNAL din			: sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
	SIGNAL diff_delay	: natural := 1;
	
	--Outputs
	SIGNAL dout			: sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
	SIGNAL vld_out		: std_logic;
	
	SIGNAL fileout_enable   : std_logic := '0';

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: cic_c_pipe 
	GENERIC MAP
	(
		max_diff_delay	=> 2,
		max_width		=> max_width,
		max_width_frac	=> max_width_frac
	)
	PORT MAP
	(
		clk				=> clk,
		rst				=> srst,
		vld_in			=> vld_in,
		diff_delay		=> diff_delay,
		din				=> din,
		dout			=> dout,
		vld_out			=> vld_out
	);


 	tb_clk : PROCESS
	BEGIN
		clk <= not clk;
		wait for PERIOD/2;
	END PROCESS;

	tb : PROCESS

	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 4*PERIOD;
		srst <= '0';
		------------------------------------------
		wait for 2*PERIOD;
		wait until rising_edge(clk);
		din		<= to_sfixed(0.0, din);
		vld_in	<= '1';

		wait for 9*PERIOD;
		wait until rising_edge(clk);

		din		<= to_sfixed(0.5, din);

		wait for 9*PERIOD;
		wait until rising_edge(clk);

		din		<= to_sfixed(0.0, din);

		wait for 9*PERIOD;
		wait until rising_edge(clk);
		vld_in	<= '0';

		wait for 20*PERIOD;

		assert false report "Test finished" severity error;
		wait; 
	END PROCESS;
	
END;
