-- ============================================================================
--
-- Design unit      :   ecb_mode_iface (interfaces of ECB-mode en-/decryption
--                      modules)
--
-- File Name        :   ecb_mode_iface.vhd
--
-- Purpose          :   The package collects type declarations for all non-
--                      trivial interfaces of used entities. Record types
--                      are used extensively to group related signals (e.g.
--                      data / control & status, physical attachment etc.).
--
--
-- Depends on       :
--
--  - Package(s)    :   aes_definitions, tech_iface, engine_iface
--
--  - Module(s)     :   -
--
--
-- Dev. Platform    :   Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
--
--  - Simulator(s)  :   Modelsim XE III 6.0d
--
--  - Synthesis     :   Xilinx XST
--
--  - Place & Route :   Xilinx PAR
--
--
-- Errors           :   None known
--
--
-- Limitations      :   None known
--
--
-- Notes            :   Version for implementation using 32-bit datapath
--
--
-- Author(s)        :   A. Freund (af) <a.freund@dsi-it.de>
--                      Digitale Signalverabeitung & Informationstechnik GmbH,
--                      Bremen, Germany
--
--
-- ============================================================================
--
-- Revision List:
-- Version      Author(s)       Date        Changes
--
-- v0.00        af              2006-11-15  initial version
--
-- see SVN logs
--
-- ============================================================================
--
-- Naming conventions:
--
--  - coding style: record-signals for related purposes (Gaisler-style)
--  - active-low signals are indicated by appending "_n"
--  - constants are in UPPERCASE
--  - name parts are separated by "_"
--
-- ============================================================================


library ieee;
use ieee.std_logic_1164.all;


use work.aes_definitions.all;
use work.tech_iface.all;
use work.engine_iface.all;


package ecb_mode_iface is


--
-- ECB-mode encryption interface definition
--


	-- data/control input signals
	type ecb_mode_encryption_in_type is record
		start	:	std_logic;			-- start encryption
		plain	:	part_data_t;		-- data to be encrypted (plaintext)
		key_id	:	key_id_t;			-- key id to use
	end record;

	-- data/status outputs signals
	type ecb_mode_encryption_out_type is record
		cipher	:	part_data_t;		-- encrypted data (ciphertext)
		busy 	:	std_logic;			-- busy, encrypion in progress
		valid	:	std_logic;			-- ciphertext is valid (encryption finished)
	end record;


--
-- ECB-mode decryption interface definition
--


	-- data/control input signals
	type ecb_mode_decryption_in_type is record
		start	:	std_logic;			-- start decryption
		cipher	:	part_data_t;		-- data to be decrypted (ciphertext)
		key_id	:	key_id_t;			-- key id to use
	end record;

	-- data/status outputs signals
	type ecb_mode_decryption_out_type is record
		plain	:	part_data_t;		-- decrypted data (plaintext)
		busy 	:	std_logic;			-- busy, decrypion in progress
		valid	:	std_logic;			-- plaintext is valid (decryption finished)
	end record;


--
--
-- Component declarations
--
--


	-- AES ECB-mode encryption
	component ecb_mode_encryption is
		port (
			rst		: 	in	std_logic;						-- reset
			clk		:	in	std_logic;						-- clock
			mode_i	:	in	ecb_mode_encryption_in_type;	-- see package ecb_mode_iface
			mode_o	:	out	ecb_mode_encryption_out_type;	-- see package ecb_mode_iface
			enc_i	:	in	encryption_engine_out_type;		-- see package engine_iface
			enc_o	:	out	encryption_engine_in_type		-- see package engine_iface
		);
	end component;



	-- AES ECB-mode decryption
	component ecb_mode_decryption is
		port (
			rst		: 	in	std_logic;						-- reset
			clk		:	in	std_logic;						-- clock
			mode_i	:	in	ecb_mode_decryption_in_type;	-- see package ecb_mode_iface
			mode_o	:	out	ecb_mode_decryption_out_type;	-- see package ecb_mode_iface
			dec_i	:	in	decryption_engine_out_type;		-- see package engine_iface
			dec_o	:	out	decryption_engine_in_type		-- see package engine_iface
		);
	end component;


end ecb_mode_iface;
