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-- Company: 
-- Engineer:
--
-- Create Date:   17:16:42 13.05.2007
-- Design Name:   tb_mix_cpx
-- Module Name:   tb_mix_cpx.vhd
-- Project Name:  mix_cpx
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
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LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; --  Imports the standard textio package.

library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;

library work;
use work.fixed_util_pkg.all;

entity syn_cic_i_pipe is
Generic
(
	max_width		: integer := 32;
	max_width_frac	: integer := 20
);
Port
(
	clk			: in std_logic;
	rst			: in std_logic;
	vld_in		: in std_logic;
	din			: in signed(max_width-1 downto 0);
	dout		: out signed(max_width-1 downto 0);
	vld_out 	: out std_logic
);
end syn_cic_i_pipe;

ARCHITECTURE behavior OF syn_cic_i_pipe IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT cic_i_pipe
	GENERIC
	(
		max_width		: integer;
		max_width_frac	: integer
	);
	PORT
	(
		clk			: in std_logic;
		rst			: in std_logic;
		vld_in		: in std_logic;
		din			: in sfixed;
		dout		: out sfixed;
		vld_out 	: out std_logic
	);
	END COMPONENT;

	--Inputs
	SIGNAL sdin			: sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
	
	--Outputs
	SIGNAL sdout		: sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
	
BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: cic_i_pipe 
	GENERIC MAP
	(
		max_width		=> max_width,
		max_width_frac	=> max_width_frac
	)
	PORT MAP
	(
		clk				=> clk,
		rst				=> rst,
		vld_in			=> vld_in,
		din				=> sdin,
		dout			=> sdout,
		vld_out			=> vld_out
	);

	sdin	<= to_sfixed(din, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
	dout	<= signed(sdout);

END;
