
-- VHDL Test Bench Created from source file vconfig.vhd -- 20:20:01 05/01/2004
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY vconfig_tb IS
END vconfig_tb;

ARCHITECTURE behavior OF vconfig_tb IS 

	COMPONENT vconfig
	PORT(
		RES : IN std_logic;
		nINIT_B : IN std_logic;
		CLK : IN std_logic;
		DONE : IN std_logic;
		CCLK : OUT std_logic;      
		CCLK_PRESCALER : IN std_logic_vector(5 downto 0);
      LOAD_PRESCALER : in std_logic;
		DIN : IN std_logic_vector(31 downto 0);
		DOUT : OUT std_logic;
 	   BUF_IS_EMPTY : inout std_logic;
		LOAD_SREG : IN std_logic    
		);
	END COMPONENT;

	SIGNAL RES :  std_logic := '1';
	SIGNAL nINIT_B :  std_logic := '0';
	SIGNAL CLK :  std_logic := '0';
	SIGNAL DONE :  std_logic := '1';
	SIGNAL CCLK :  std_logic;
	SIGNAL CCLK_PRESCALER :  std_logic_vector(5 downto 0);
	SIGNAL LOAD_PRESCALER :  std_logic := '0';
	SIGNAL DOUT :  std_logic;
	SIGNAL DIN :  std_logic_vector(31 downto 0);
	SIGNAL LOAD_SREG :  std_logic := '0';
	SIGNAL BUF_IS_EMPTY : std_logic;

	constant ClockPeriod : Time := 16.667 ns;
	constant CFG_PRESCALE: integer range 0 to 63 := 2;

BEGIN

	uut: vconfig PORT MAP(
		RES => RES,
		nINIT_B => nINIT_B,
		CLK => CLK,
		DONE => DONE,
		CCLK => CCLK,
		CCLK_PRESCALER => CCLK_PRESCALER,
		LOAD_PRESCALER => LOAD_PRESCALER,
		DOUT => DOUT,
		DIN => DIN,
		BUF_IS_EMPTY => BUF_IS_EMPTY,
		LOAD_SREG => LOAD_SREG
	);

	busclock: process
	begin
		CLK <= '1';
		loop
			wait for (ClockPeriod / 2);
			CLK <= not CLK;
		end loop;  
	end process;

-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN

	   wait for 5*ClockPeriod;
		RES <= '0';

	   wait for 5*ClockPeriod;
		CCLK_PRESCALER <= CONV_STD_LOGIC_VECTOR(CFG_PRESCALE,6);

	   wait for 1.5*ClockPeriod;
		LOAD_PRESCALER <= '1';

	   wait for 1*ClockPeriod;
		LOAD_PRESCALER <= '0';

	   wait for 1*ClockPeriod;
		DIN <= X"BAA34569";

	   wait for 1.5*ClockPeriod;
      LOAD_SREG <= '1';		

	   wait for 1.0*ClockPeriod;
      LOAD_SREG <= '0';		
	   
	   wait for 5*ClockPeriod;
		DONE <= '0';

	   wait for 2*ClockPeriod;
		nINIT_B <= '1';

	   wait for 30.0*real(CFG_PRESCALE)*ClockPeriod*2;

		DIN <= X"8654F41B";

	   wait for 1.5*ClockPeriod;
      LOAD_SREG <= '1';		

	   wait for 2.0*ClockPeriod;
      LOAD_SREG <= '0';		

	   wait for 29.0*real(CFG_PRESCALE)*ClockPeriod*2;
		DONE <= '1';

	   wait for 10.0*ClockPeriod;
		nINIT_B <= '0';

      wait; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;
