--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    11:25:45 10/15/05
-- Design Name:    
-- Module Name:    vga_ctrl_core - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library work;
use work.utils_pkg.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
Library UNISIM;
use UNISIM.vcomponents.all;

entity clkgen is
	Generic
	(
		clk_in_freq			: real	:= 100.0;
		clk_out_freq		: real	:= 100.0
	);
	Port
	(
		rst			: in std_logic;
		clk_in		: in std_logic;
		clk_out		: out std_logic;
		locked		: out std_logic
	);
end clkgen;

architecture tech of clkgen is

	signal dcm_clk0               : std_logic;
	signal dcm_clk_fb             : std_logic;
	signal clk_out0	              : std_logic;

	begin
	
	-- Compnent instantiation
	DCM_VGA_CLK_inst : DCM_BASE
	generic map (
		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
						   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
		CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, clk_out_freq),   -- Can be any interger from 1 to 32
		CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, clk_out_freq), -- Can be any integer from 2 to 32
		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
		CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
		CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
		DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
											 --   an integer from 0 to 15
		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
		PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
		STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
	port map
	(
		CLK0 => dcm_clk0,         -- 0 degree DCM CLK ouptput
		CLK180 => open,     -- 180 degree DCM CLK output
		CLK270 => open,     -- 270 degree DCM CLK output
		CLK2X => open,       -- 2X DCM CLK output
		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
		CLK90 => open,       -- 90 degree DCM CLK output
		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
		CLKFX => clk_out0,       -- DCM CLK synthesis out (M/D)
		CLKFX180 => open, -- 180 degree CLK synthesis out
		LOCKED => locked,     -- DCM LOCK status output
		CLKFB => dcm_clk_fb,       -- DCM clock feedback
		CLKIN => clk_in,       -- Clock input (from IBUFG, BUFG or DCM)
		RST => rst            -- DCM asynchronous reset input
	);

	BUFG_dcm_clk_fb : BUFG
	port map
	(
		O => dcm_clk_fb,     -- Clock buffer output
		I => dcm_clk0        -- Clock buffer input
	);

	BUFG_clk_out : BUFG
	port map
	(
		O => clk_out,     -- Clock buffer output
		I => clk_out0     -- Clock buffer input
	);

end tech;
