--------------------------------------------------------------------------------------------------
-- COMMAND FORMAT                                                                               --
--                                                                                              --
-- write(column address(integer), bank(bit_vector), first data(integer), dqm(bit), cke(bit));   --
-- read(column address(integer), bank(bit_vector), dqm(bit), cke(bit));                         --
-- active(row address(integer), bank(bit_vector), data bus (integer), dqm(bit), cke(bit));      --
-- precharge(bank(bit_vector), address (integer), data bus(integer), dqm(bit), cke(bit));       --
-- nop(data bus(integer), dqm(bit), cke(bit));                                                  --
-- burst_term(data bus(integer), dqm(bit), cke(bit));                                           --
-- load_array('1');                                                                             --
-- load_mode_reg(register(integer), cke(bit));                                                  --
-- next_cycle(clk);  This is used after every command(incl. nop) to clock                       --
--                   at the correct clock frequency entered in the clock                        --
--                   period constant below                                                      --
-- unload_array(row_start(integer), row_end(integer), bank(bit_vector))                         --
-- load_mode_reg(op_code(integer))                                                              --
--                                                                                              --
--------------------------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;
USE work.generate_vectors.all;

ENTITY vector_generate IS
END vector_generate;

ARCHITECTURE vector_generate OF vector_generate IS

   SIGNAL   stim_done  : BOOLEAN := FALSE;
   SIGNAL   clk        : BIT     := '0';
   CONSTANT clk_start  : time    := 15 ns;
   CONSTANT clk_period : time    := 10 ns;
   CONSTANT Z          : INTEGER := -100;
  
BEGIN

PROCESS

BEGIN

WAIT UNTIL clk = '1' AND clk'EVENT;
   
--------------------ENTER COMMANDS BELOW THIS LINE----------------------------- 
--******************DO NOT USE -100 FOR A DQ VALUE*************************----
--*******************Z WILL PLACE HI-Z ON THE BUS**************************----
--*******USE next_cycle(clk) FOR ADVANCING TO NEXT CLOCK CYCLE*************----

nop(Z, '0', '1');  --Always begin with one nop when using Micron's testbench

next_cycle(clk);
load_array;

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
precharge("00", 1024, Z, '0', '1');

FOR i IN 1 to 2 LOOP
    next_cycle(clk);
    nop(Z, '0', '1');
END LOOP;

next_cycle(clk);
auto_refresh;

FOR i IN 1 TO 8 LOOP
    next_cycle(clk);
    nop(Z, '0', '1');
END LOOP;

next_cycle(clk);
auto_refresh;

FOR i IN 1 TO 8 LOOP
    next_cycle(clk);
    nop(Z, '0', '1');
END LOOP;

next_cycle(clk);
load_mode_reg(49, '1');    -- 19 / 35 / 51 -> lat=3,bl=8,mode=seq

next_cycle(clk);
nop(Z, '0', '1');

-- Write Section

next_cycle(clk);
active(0, "00", Z, '0', '1');      -- Activate     Bank 0

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);                    
--write(0, "00", 10, '0', '1');       -- Write        Bank 0
write(1024, "00", 10, '0', '1');    -- Write        Bank 0        Auto Precharge

next_cycle(clk);
nop(11, '0', '1');

next_cycle(clk);
active(0, "01", 12, '0', '1');    -- Activate     Bank 1

next_cycle(clk);
nop(13, '0', '1');

next_cycle(clk);
nop(14, '0', '1');

next_cycle(clk);
nop(15, '0', '1');

next_cycle(clk);
nop(16, '0', '1');

next_cycle(clk);
nop(17, '0', '1');

next_cycle(clk);   
--write(0, "01", 20, '0', '1');     -- Write        Bank 1
write(1024, "01", 20, '0', '1');     -- Write        Bank 1        Auto Precharge

next_cycle(clk);
--precharge("00", 0, 21, '0', '1'); -- Precharge    Bank 0
nop(21, '0', '1');

next_cycle(clk);
active(0, "10", 22, '0', '1');    -- Activate     Bank 2

next_cycle(clk);
nop(23, '0', '1');

next_cycle(clk);
nop(24, '0', '1');

next_cycle(clk);
nop(25, '0', '1');

next_cycle(clk);
nop(26, '0', '1');

next_cycle(clk);
nop(27, '0', '1');

next_cycle(clk);   
--write(0, "10", 30, '0', '1');     -- Write        Bank 2
write(1024, "10", 30, '0', '1');     -- Write        Bank 2        Auto Precharge

next_cycle(clk);
--precharge("01", 0, 31, '0', '1'); -- Precharge    Bank 1
nop(31, '0', '1');

next_cycle(clk);
active(0, "11", 32, '0', '1');    -- Activate     Bank 3

next_cycle(clk);
nop(33, '0', '1');

next_cycle(clk);
nop(34, '0', '1');

next_cycle(clk);
nop(35, '0', '1');

next_cycle(clk);
nop(36, '0', '1');

next_cycle(clk);
nop(37, '0', '1');

next_cycle(clk);   
--write(0, "11", 40, '0', '1');     -- Write        Bank 3
write(1024, "11", 40, '0', '1');     -- Write        Bank 3        Auto Precharge

next_cycle(clk);
--precharge("10", 0, 41, '0', '1'); -- Precharge    Bank 2
nop(41, '0', '1');

next_cycle(clk);
active(0, "00", 42, '0', '1');    -- Activate     Bank 0

next_cycle(clk);
nop(43, '0', '1');

next_cycle(clk);
nop(44, '0', '1');

next_cycle(clk);
nop(45, '0', '1');

next_cycle(clk);
nop(46, '0', '1');

next_cycle(clk);
nop(47, '0', '1');

-- Read Section

next_cycle(clk);
--read(0, "00", '0', '1');           -- Read         Bank 0
read(1024, "00", '0', '1');           -- Read         Bank 0        Auto Precharge

next_cycle(clk);
--precharge("11", 0, Z, '0', '1');   -- Precharge    Bank 3
nop(Z, '0', '1'); 

next_cycle(clk);
active(0, "01", Z, '0', '1');      -- Activate     Bank 1

next_cycle(clk);
nop(Z, '0', '1'); 

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
--read(0, "01", '0', '1');           -- Read         Bank 1
read(1024, "01", '0', '1');           -- Read         Bank 1        Auto Precharge

next_cycle(clk);
--precharge("00", 0, Z, '0', '1');   -- Precharge    Bank 0
nop(Z, '0', '1'); 

next_cycle(clk);
active(0, "10", Z, '0', '1');      -- Activate     Bank 2

next_cycle(clk);
nop(Z, '0', '1'); 

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
--read(0, "10", '0', '1');           -- Read         Bank 2
read(1024, "10", '0', '1');           -- Read         Bank 2        Auto Precharge

next_cycle(clk);
--precharge("01", 0, Z, '0', '1');   -- Precharge    Bank 1
nop(Z, '0', '1'); 

next_cycle(clk);
active(0, "11", Z, '0', '1');      -- Activate     Bank 3

next_cycle(clk);
nop(Z, '0', '1'); 

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
--read(0, "11", '0', '1');           -- Read         Bank 3
read(1024, "11", '0', '1');           -- Read         Bank 3        Auto Precharge

next_cycle(clk);
--precharge("10", 0, Z, '0', '1');   -- Precharge    Bank 2
nop(Z, '0', '1'); 

next_cycle(clk);
nop(Z, '0', '1'); 

next_cycle(clk);
nop(Z, '0', '1'); 

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
--precharge("11", 0, Z, '0', '1');   -- Precharge    Bank 3
nop(Z, '0', '1'); 

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
nop(Z, '0', '1');

next_cycle(clk);
unload_array(0, 1, "00");           -- Unload From Row 0-1, Bank 00

next_cycle(clk);
unload_array(0, 1, "01");           -- Unload From Row 0-1, Bank 10

next_cycle(clk);
unload_array(0, 1, "10");           -- Unload From Row 0-1, Bank 01

next_cycle(clk);
unload_array(0, 1, "11");           -- Unload From Row 0-1, Bank 11

next_cycle(clk);
nop(Z, '0', '1'); 

stim_done <= TRUE;  --always include this line at the end of your stimulus   

-------------------------------------------------------------------------------
--*************************************************************************----
END PROCESS;


clock:
  PROCESS
    VARIABLE done_time : time;
    VARIABLE cycle_var : integer := 0;
  BEGIN
    cycle <= 0;
    clk <= '0';
    WAIT for clk_start;
    WHILE not stim_done loop
         clk <= '1';
         cycle <= cycle_var;
      WAIT for clk_period/2;
         cycle_var := cycle_var + 1;
         clk <= '0';
      WAIT for clk_period/2;
    END LOOP;    
    
    ASSERT (FALSE) 
       REPORT "Test Vectors Generated" 
       SEVERITY note;
       
    WAIT;
  END PROCESS;
  

END;
