
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   12:39:41 06/16/2007
-- Design Name:   ac97_test
-- Module Name:   W:/vhdl/projects/ac97_Controller/src/tb_ac97_test.vhd
-- Project Name:  eval_ac
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ac97_test
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY tb_ac97_test IS
END tb_ac97_test;

ARCHITECTURE behavior OF tb_ac97_test IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT ac97_test
	PORT(
		sys_rst_n_in : IN std_logic;
		sys_clk_in : IN std_logic;
		ac97_bit_clk : IN std_logic;
		ac97_sdata_in : IN std_logic;          
		ac97_reset_n : OUT std_logic;
		ac97_sdata_out : OUT std_logic;
		ac97_sync : OUT std_logic;
		sys_lcd_d		: inout std_logic_vector(3 downto 0);
		sys_lcd_e		: out std_logic;
		sys_lcd_rs		: out std_logic;
		sys_lcd_rw		: out std_logic;
		sys_rx			: in std_logic;
		sys_tx			: out std_logic;
		sys_btn			: in STD_LOGIC_VECTOR(4 downto 0);
		sys_dip			: in STD_LOGIC_VECTOR(7 downto 0);
		sys_led : OUT std_logic_vector(8 downto 0)
		);
	END COMPONENT;

	CONSTANT CLK_PERIOD : time := 10 ns;
--	CONSTANT BIT_CLK_PERIOD : time := 100 ns;
	CONSTANT BIT_CLK_PERIOD : time := 81.38020833333333 ns;

	--Inputs
	SIGNAL sys_rst_n_in :  std_logic := '0';
	SIGNAL sys_clk_in :  std_logic := '0';
	SIGNAL ac97_bit_clk :  std_logic := '1';
	SIGNAL ac97_sdata_in :  std_logic := '0';
	SIGNAL sys_rx :  std_logic := '0';
	SIGNAL sys_btn	: STD_LOGIC_VECTOR(4 downto 0) := (others => '0');
	SIGNAL sys_dip	: STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
	SIGNAL sys_lcd_d :  std_logic_vector(3 downto 0) := (others => 'Z');

	--Outputs
	SIGNAL ac97_reset_n :  std_logic;
	SIGNAL ac97_sdata_out :  std_logic;
	SIGNAL ac97_sync :  std_logic;
	SIGNAL sys_tx :  std_logic;
	SIGNAL sys_lcd_e :  std_logic;
	SIGNAL sys_lcd_rs :  std_logic;
	SIGNAL sys_lcd_rw :  std_logic;
	SIGNAL sys_led :  std_logic_vector(8 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: ac97_test PORT MAP(
		sys_rst_n_in => sys_rst_n_in,
		sys_clk_in => sys_clk_in,
		ac97_bit_clk => ac97_bit_clk,
		ac97_sdata_in => ac97_sdata_in,
		ac97_reset_n => ac97_reset_n,
		ac97_sdata_out => ac97_sdata_out,
		ac97_sync => ac97_sync,
		sys_btn => sys_btn,
		sys_dip => sys_dip,
		sys_rx => sys_rx,
		sys_tx => sys_tx,
		sys_lcd_d => sys_lcd_d,
		sys_lcd_e => sys_lcd_e,
		sys_lcd_rs => sys_lcd_rs,
		sys_lcd_rw => sys_lcd_rw,
		sys_led => sys_led
	);

	clk_gen : PROCESS
	begin
	wait for CLK_PERIOD/2;
	sys_clk_in <= not sys_clk_in;
	end process;

	bit_clk_gen : PROCESS
	begin
	if (ac97_reset_n = '0') then
		ac97_bit_clk <= '0';
		wait until ac97_reset_n = '1';
		wait for 373.56 ns;
	end if;	
	wait for BIT_CLK_PERIOD/2;
	ac97_bit_clk <= not ac97_bit_clk;
		
	end process;

	tb : PROCESS
	BEGIN

		wait for 8 * CLK_PERIOD;
		sys_rst_n_in <= '1';

		wait for 1234 * BIT_CLK_PERIOD;
		
		
		for i in 0 to 1000 loop
			wait until rising_edge(ac97_bit_clk) and ac97_sync = '1';
			ac97_sdata_in <= '1';
			wait until rising_edge(ac97_bit_clk);
			ac97_sdata_in <= '1';

		end loop;
		
		wait; -- will wait forever
	END PROCESS;

END;
