-- ============================================================================
--
-- Design unit		:	ecb_core_iface (interfaces of ECB-mode en-/decryption
--						cores)
--
-- File Name		:	ecb_core_iface.vhd
--
-- Purpose			:	The package collects type declarations for all non-
--						trivial interfaces of used entities. Record types
--						are used extensively to group related signals (e.g.
--						data / control & status, physical attachment etc.).
--
--
-- Depends on 		:
--
--	- Package(s)	:	tech_iface, key_schedule_iface, engine_iface,
--						ecb_mode_iface
--
--	- Module(s)		:	-
--
--
-- Dev. Platform	:	Xilinx ISE 8.1i SP3 / Win32 (W2k SP4)
--
--	- Simulator(s)	:	Modelsim XE III 6.0d
--
--	- Synthesis		:	Xilinx XST
--
--	- Place & Route	:	Xilinx PAR
--
--
-- Errors			:	None known
--
--
-- Limitations		:	None known
--
--
-- Notes			:	-
--
--
-- Author(s)		:	A. Freund (af) <a.freund@dsi-it.de>
--						Digitale Signalverabeitung & Informationstechnik GmbH,
--						Bremen, Germany
--
--
-- ============================================================================
--
-- Revision List:
-- Version		Author(s)		Date		Changes
--
-- v0.00		af				2006-11-15	initial version
--
-- see SVN logs
--
-- ============================================================================
--
-- Naming conventions:
--
--	- coding style: record-signals for related purposes (Gaisler-style)
-- 	- active-low signals are indicated by appending "_n"
--	- constants are in UPPERCASE
--	- name parts are separated by "_"
--
-- ============================================================================


library ieee;
use ieee.std_logic_1164.all;


use work.tech_iface.all;
use work.key_schedule_iface.all;
use work.engine_iface.all;
use work.ecb_mode_iface.all;


package ecb_core_iface is


-- no new interfaces are needed yet



--
--
-- Component declarations
--
--


	-- AES-ECB-128 encryption core
	component ecb_128_encryption_core is
		port (
			rst		:	in	std_logic;						-- reset
			clk		:	in	std_logic;						-- clock
			mode_i	:	in	ecb_mode_encryption_in_type;	-- see package ecb_mode_iface
			mode_o	:	out	ecb_mode_encryption_out_type;	-- see package ecb_mode_iface
			key_i	:	in	key_schedule_128_in_type;		-- see package key_schedule_iface
			key_o	:	out	key_schedule_128_out_type;		-- see package key_schedule_iface
			sbld_i	:	in	sbox_stage_load_in_type			-- see package tech_iface
		);
	end component;


	-- AES-ECB-128 decryption core
	component ecb_128_decryption_core is
		port (
			rst		:	in	std_logic;						-- reset
			clk		:	in	std_logic;						-- clock
			mode_i	:	in	ecb_mode_decryption_in_type;	-- see package ecb_mode_iface
			mode_o	:	out	ecb_mode_decryption_out_type;	-- see package ecb_mode_iface
			key_i	:	in	key_schedule_128_in_type;		-- see package key_schedule_iface
			key_o	:	out	key_schedule_128_out_type;		-- see package key_schedule_iface
			sbld_i	:	in	sbox_stage_load_in_type			-- see package tech_iface
		);
	end component;


	-- AES-ECB-256 encryption core
	component ecb_256_encryption_core is
		port (
			rst		:	in	std_logic;						-- reset
			clk		:	in	std_logic;						-- clock
			mode_i	:	in	ecb_mode_encryption_in_type;	-- see package ecb_mode_iface
			mode_o	:	out	ecb_mode_encryption_out_type;	-- see package ecb_mode_iface
			key_i	:	in	key_schedule_256_in_type;		-- see package key_schedule_iface
			key_o	:	out	key_schedule_256_out_type;		-- see package key_schedule_iface
			sbld_i	:	in	sbox_stage_load_in_type			-- see package tech_iface
		);
	end component;


	-- AES-ECB-256 decryption core
	component ecb_256_decryption_core is
		port (
			rst		:	in	std_logic;						-- reset
			clk		:	in	std_logic;						-- clock
			mode_i	:	in	ecb_mode_decryption_in_type;	-- see package ecb_mode_iface
			mode_o	:	out	ecb_mode_decryption_out_type;	-- see package ecb_mode_iface
			key_i	:	in	key_schedule_256_in_type;		-- see package key_schedule_iface
			key_o	:	out	key_schedule_256_out_type;		-- see package key_schedule_iface
			sbld_i	:	in	sbox_stage_load_in_type			-- see package tech_iface
		);
	end component;


end ecb_core_iface;
