-------------------------------------------------------------------------
-- Project: SDRAM controller
-- This file: Type definitions
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------

library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

use work.sdram_config.all;

package sdram_types is

	-----------------------------------------------------------------------------------------
	-- Table of Timing Parameters as a function of operation

	-- Derived constants from sdram_config

	constant DDR_DQS_WIDTH  	: positive := DDR_DATA_WIDTH / 8; -- Number of data strobe lines
	constant DDR_DM_WIDTH   	: positive := DDR_DATA_WIDTH / 8; -- Number of Data Mask Lines
	constant SDR_DATA_WIDTH 	: positive := 2*DDR_DATA_WIDTH;  -- 
	constant SDR_DM_WIDTH		: positive := 2*DDR_DM_WIDTH;  -- 

	subtype user_cmd_t is unsigned(1 downto 0);
	constant UCMD_NOP			: user_cmd_t := "00";
	constant UCMD_READ			: user_cmd_t := "01";
	constant UCMD_WRITE			: user_cmd_t := "10";
	constant UCMD_LMR			: user_cmd_t := "11";

	subtype sdr_cmd_t is natural range 0 to 9;
	constant SD_DESELECT		: sdr_cmd_t := 0;
	constant SD_NOP				: sdr_cmd_t := 1;
	constant SD_LMR				: sdr_cmd_t := 2;
	constant SD_ACT				: sdr_cmd_t := 3;
	constant SD_READ			: sdr_cmd_t := 4;
	constant SD_WRITE			: sdr_cmd_t := 5;
	constant SD_PRE				: sdr_cmd_t := 6;
	constant SD_BST				: sdr_cmd_t := 7;
	constant SD_AR				: sdr_cmd_t := 8;
	constant SD_SR				: sdr_cmd_t := 9;
	
	type sdr_state_t is (PWR_DOWN, PRECHARGE, MODE, IDLE, ROW_ACT, WRITE, WRITE_A, READ, READ_A, BURST_STOP, SELF_REF, AUTO_REF, PRE_PWR_DOWN, ACT_PWR_DOWN);
	subtype user_addr_t is unsigned(DDR_BANK_WIDTH+DDR_ROW_ADDR_WIDTH+DDR_COL_ADDR_WIDTH-1 downto 0);
	subtype sdr_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
	subtype sdr_ba_t is unsigned(DDR_BANK_WIDTH-1 downto 0);
	subtype mode_word_t is unsigned(DDR_ADDR_WIDTH+DDR_BANK_WIDTH-1 downto 0);

	subtype bank_addr_t is unsigned(DDR_BANK_WIDTH-1 downto 0);
	subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
	subtype col_addr_t is unsigned(8 downto 0);
	
	subtype cycle_cnt_t is natural range 0 to 10;
	
	type phy_ctrl_t is
	record
		drive_en		: std_logic;
		re				: std_logic;
		we				: std_logic;
		utag_we			: std_logic;
	end record phy_ctrl_t;

	type sdr_cmd_lines_t is
	record
         cs_n    : std_logic;
         ras_n   : std_logic;
         cas_n   : std_logic;
         we_n    : std_logic;
	end record sdr_cmd_lines_t;

	type part_ctrl_t is
	record
		cmd		: sdr_cmd_lines_t;
		ba	 	: unsigned(DDR_BANK_WIDTH-1 downto 0);
		addr	: unsigned(DDR_ADDR_WIDTH-1 downto 0);
		cke		: std_logic;
	end record part_ctrl_t;
	
	type part_cmd_array_t is array (sdr_cmd_t) of sdr_cmd_lines_t;
	constant COMMAND : part_cmd_array_t :=
	--	 command                 cs_n     ras_qn      cas_qn      we_qn
	(	SD_DESELECT         =>   (   '1',      '1',        '1',        '1'),
		SD_NOP              =>   (   '0',      '1',        '1',        '1'),
		SD_LMR              =>   (   '0',      '0',        '0',        '0'),
		SD_ACT              =>   (   '0',      '0',        '1',        '1'),
		SD_READ             =>   (   '0',      '1',        '0',        '1'),
		SD_WRITE            =>   (   '0',      '1',        '0',        '0'),
		SD_PRE              =>   (   '0',      '0',        '1',        '0'),
		SD_BST              =>   (   '0',      '1',        '1',        '0'),
		SD_AR               =>   (   '0',      '0',        '0',        '1'),
		SD_SR               =>   (   '0',      '0',        '0',        '1')
	);

	type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t;
	constant TIMING : part_timing_array_t :=
	--	 command                 cycle_cnt
	(	SD_DESELECT         =>   (     0        ),
		SD_NOP              =>   (     0        ),
		SD_LMR              =>   (     TMRD-1   ),
		SD_ACT              =>   (     TRCD-1   ),
		SD_READ             =>   (     TCAS-1   ),
		SD_WRITE            =>   (     TWR-1    ),
		SD_PRE              =>   (     TRP-1    ),
		SD_BST              =>   (     0        ),
		SD_AR               =>   (     TRFC-1   ),
		SD_SR               =>   (     TRFC-1   )
	);

	type init_seq_t is 
	record
		cmd			: sdr_cmd_t;
		mode_word	: mode_word_t;
		wait_cycle	: natural;
	end record init_seq_t;	
	
end sdram_types;
