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-- Company: 
-- Engineer:
--
-- Create Date:   17:16:42 13.05.2007
-- Design Name:   tb_nco
-- Module Name:   tb_nco.vhd
-- Project Name:  nco
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; --  Imports the standard textio package.

library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;

library work;
use work.fixed_util_pkg.all;
use work.filter_pkg.all;
use work.fir_pkg.all;

ENTITY syn_fir_lowpass IS
	Generic
	(
		ntaps_per_stage		: integer := 32;
		nstages				: integer := 2;
		nbits_in			: integer := 16;
		nbits_in_frac		: integer := 14;
		nbits_stages		: integer := 32;
		nbits_stages_frac	: integer := 30;
		nbits_out			: integer := 32;
		nbits_out_frac		: integer := 30;
		fir_npipe_regs		: integer := 7
	);
	PORT(
		rst			: in  std_logic;
		clk			: in  std_logic;
		h_addr		: in natural range 0 to nstages*ntaps_per_stage-1;
		h_we		: in std_logic;
		h_din		: in signed(nbits_stages-1 downto 0);
		start_i		: in  std_logic;
		ready_i		: out std_logic;
		x_valid_i	: in  std_logic;
		x_din_i		: in  signed(nbits_in-1 downto 0);
		y_valid_i	: out std_logic;
		y_dout_i	: out signed(nbits_out-1 downto 0);
		start_q		: in  std_logic;
		ready_q		: out std_logic;
		x_valid_q	: in  std_logic;
		x_din_q		: in  signed(nbits_in-1 downto 0);
		y_valid_q	: out std_logic;
		y_dout_q	: out signed(nbits_out-1 downto 0)
	);
END syn_fir_lowpass;

ARCHITECTURE behavior OF syn_fir_lowpass IS 

	-- Lowpass parameter

	--Outputs
	SIGNAL h_i, h_q  : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
	SIGNAL x_i, x_q  : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
	SIGNAL y_i, y_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));

	SIGNAL h_in			: sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	inst_fir_semi_parallel_i : entity work.fir_semi_parallel
	GENERIC MAP
	(
		ntaps_per_stage		=> ntaps_per_stage,
		nstages				=> nstages,
		pipe_latency		=> fir_npipe_regs,
		nbits_in			=> nbits_in,
		nbits_in_frac		=> nbits_in_frac,
		nbits_stages		=> nbits_stages,
		nbits_stages_frac	=> nbits_stages_frac,
		nbits_out			=> nbits_out,
		nbits_out_frac		=> nbits_out_frac
	)
	PORT MAP
	(
		rst			=> rst,
		clk			=> clk,
		h_addr		=> h_addr,
		h_we		=> h_we,
		h_in		=> h_in,
		din_vld		=> x_valid_i,
		din			=> x_i,
		dout_vld	=> y_valid_i,
		start		=> start_i,
		rdy			=> ready_i,
		dout		=> y_i
	);

	inst_fir_semi_parallel_q : entity work.fir_semi_parallel
	GENERIC MAP
	(
		ntaps_per_stage		=> ntaps_per_stage,
		nstages				=> nstages,
		pipe_latency		=> fir_npipe_regs,
		nbits_in			=> nbits_in,
		nbits_in_frac		=> nbits_in_frac,
		nbits_stages		=> nbits_stages,
		nbits_stages_frac	=> nbits_stages_frac,
		nbits_out			=> nbits_out,
		nbits_out_frac		=> nbits_out_frac
	)
	PORT MAP
	(
		rst			=> rst,
		clk			=> clk,
		h_addr		=> h_addr,
		h_we		=> h_we,
		h_in		=> h_in,
		din_vld		=> x_valid_q,
		din			=> x_q,
		dout_vld	=> y_valid_q,
		start		=> start_q,
		rdy			=> ready_q,
		dout		=> y_q
	);

	h_in <= sfixed(h_din);
	
	x_i <= sfixed(x_din_i);
	y_dout_i <= signed(y_i);

	x_q <= sfixed(x_din_q);
	y_dout_q <= signed(y_q);
	
END;
