--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   17:16:42 13.05.2007
-- Design Name:   tb_mix_cpx
-- Module Name:   tb_mix_cpx.vhd
-- Project Name:  mix_cpx
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; --  Imports the standard textio package.

library work;
use work.fixed_pkg.all;
use work.mix_pkg.all;

ENTITY tb_syn_mix_cpx IS
	Generic (
		nbits_in		: integer := 12;
		nbits_in_frac	: integer := 12;
		nbits_out		: integer := 12;
		nbits_out_frac	: integer := 12;
		has_in_reg		: boolean := true;
		has_pipe_reg	: boolean := true;
		has_out_reg		: boolean := true;
		rounding		: boolean := true;
		saturating		: boolean := true
	        );
END tb_syn_mix_cpx;

ARCHITECTURE behavior OF tb_syn_mix_cpx IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT syn_mix_cpx
	GENERIC
	(
		nbits_in		: integer;
		nbits_in_frac	: integer;
		nbits_out		: integer;
		nbits_out_frac	: integer;
		has_in_reg		: boolean;
		has_pipe_reg	: boolean;
		has_out_reg		: boolean;
		rounding		: boolean;
		saturating		: boolean
	);
	PORT
	(
		sys_rst			: in std_logic;
		sys_clk			: in std_logic;
		sys_in_valid	: in std_logic;
		sys_x_re_in		: in signed;
		sys_x_im_in		: in signed;
		sys_y_re_in		: in signed;
		sys_y_im_in		: in signed;
		sys_out_valid	: out std_logic;
		sys_z_re_out	: out signed;
		sys_z_im_out	: out signed
	);
	END COMPONENT;

	--Constants
	constant PERIOD : time := 10 ns;
	

	--Inputs
	SIGNAL clk         : std_logic := '0';
	SIGNAL srst        : std_logic := '1';
	SIGNAL in_valid    : std_logic := '0';
	SIGNAL x_re_in     : signed(nbits_in-1 downto 0);
	SIGNAL x_im_in     : signed(nbits_in-1 downto 0);
	SIGNAL y_re_in     : signed(nbits_in-1 downto 0);
	SIGNAL y_im_in     : signed(nbits_in-1 downto 0);

	--Outputs
	SIGNAL z_re_out    : signed(nbits_out-1 downto 0);
	SIGNAL z_im_out    : signed(nbits_out-1 downto 0);
	SIGNAL out_valid   : std_logic;
	
	SIGNAL x_re    : real := 0.0;
	SIGNAL x_im    : real := 0.0;
	SIGNAL y_re    : real := 0.0;
	SIGNAL y_im    : real := 0.0;
	SIGNAL z_re    : real := 0.0;
	SIGNAL z_im    : real := 0.0;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: syn_mix_cpx 
	GENERIC MAP
	(
		nbits_in		=> nbits_in,
		nbits_in_frac	=> nbits_in_frac,
		nbits_out		=> nbits_out,
		nbits_out_frac	=> nbits_out_frac,
		has_in_reg		=> has_in_reg,
		has_pipe_reg	=> has_pipe_reg,
		has_out_reg		=> has_out_reg,
		rounding		=> rounding,
		saturating		=> saturating
	)
	PORT MAP
	(
		sys_rst			=> srst,
		sys_clk			=> clk,
		sys_in_valid	=> in_valid,
		sys_x_re_in		=> x_re_in,
		sys_x_im_in		=> x_im_in,
		sys_y_re_in		=> y_re_in,
		sys_y_im_in		=> y_im_in,
		sys_out_valid	=> out_valid,
		sys_z_re_out	=> z_re_out,
		sys_z_im_out	=> z_im_out
	);

 	tb_clk : PROCESS
	BEGIN
		clk <= not clk;
		wait for PERIOD/2;
	END PROCESS;

	tb : PROCESS

	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 4*PERIOD;
		srst <= '0';
		------------------------------------------
		wait for 2*PERIOD;
		wait until rising_edge(clk);
		x_re_in <= signed(to_sfixed(0.5, sproto(nbits_in, nbits_in_frac)));
		x_im_in <= signed(to_sfixed(0.5, sproto(nbits_in, nbits_in_frac)));
		y_re_in <= signed(to_sfixed(0.5, sproto(nbits_in, nbits_in_frac)));
		y_im_in <= signed(to_sfixed(0.5, sproto(nbits_in, nbits_in_frac)));
		in_valid <= '1';
		------------------------------------------
		wait until rising_edge(clk);
		x_re_in <= signed(to_sfixed(0.125, sproto(nbits_in, nbits_in_frac)));
		x_im_in <= signed(to_sfixed(0.25, sproto(nbits_in, nbits_in_frac)));
		y_re_in <= signed(to_sfixed(0.25, sproto(nbits_in, nbits_in_frac)));
		y_im_in <= signed(to_sfixed(0.125, sproto(nbits_in, nbits_in_frac)));
		in_valid <= '1';
		------------------------------------------
		wait until rising_edge(clk);
		x_re_in <= signed(to_sfixed(0.125, sproto(nbits_in, nbits_in_frac)));
		x_im_in <= signed(to_sfixed(-0.25, sproto(nbits_in, nbits_in_frac)));
		y_re_in <= signed(to_sfixed(0.25, sproto(nbits_in, nbits_in_frac)));
		y_im_in <= signed(to_sfixed(0.125, sproto(nbits_in, nbits_in_frac)));
		in_valid <= '1';
		------------------------------------------
		wait until rising_edge(clk);
		x_re_in <= signed(to_sfixed(0.125, sproto(nbits_in, nbits_in_frac)));
		x_im_in <= signed(to_sfixed(0.25, sproto(nbits_in, nbits_in_frac)));
		y_re_in <= signed(to_sfixed(0.25, sproto(nbits_in, nbits_in_frac)));
		y_im_in <= signed(to_sfixed(-0.125, sproto(nbits_in, nbits_in_frac)));
		in_valid <= '1';
		wait until rising_edge(clk);
		in_valid <= '0';

		wait for 20*PERIOD;

		assert false report "Test finished" severity error;
		wait; 
	END PROCESS;
	
	x_re <= to_real(sfixed(x_re_in));
	x_im <= to_real(sfixed(x_im_in));
	y_re <= to_real(sfixed(y_re_in));
	y_im <= to_real(sfixed(y_im_in));
	z_re <= to_real(sfixed(z_re_out));
	z_im <= to_real(sfixed(z_im_out));
	
END;
