-- Xilinx Vhdl netlist produced by netgen application (version G.30)
-- Command       : -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim vconfig.nga vconfig.vhd 
-- Input file    : vconfig.nga
-- Output file   : vconfig.vhd
-- Design name   : vconfig.nga
-- # of Entities : 1
-- Xilinx        : D:/Xilinx
-- Device        : XC95288XL-6-TQ144 (Speed File: Version 3.0)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity vconfig is
  port (
    nINIT_B : in STD_LOGIC := 'X'; 
    LOAD : in STD_LOGIC := 'X'; 
    RES : in STD_LOGIC := 'X'; 
    DONE : in STD_LOGIC := 'X'; 
    CLK : in STD_LOGIC := 'X'; 
    DOUT : out STD_LOGIC; 
    VCLK : out STD_LOGIC; 
    DIN : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    VCLK_PRESCALE : in STD_LOGIC_VECTOR ( 5 downto 0 ) 
  );
end vconfig;

architecture Structure of vconfig is
  signal FOEIO_1 : STD_LOGIC; 
  signal LOAD_IBUF : STD_LOGIC; 
  signal DIN_31_IBUF : STD_LOGIC; 
  signal RES_IBUF : STD_LOGIC; 
  signal DONE_IBUF : STD_LOGIC; 
  signal FCLKIO_0 : STD_LOGIC; 
  signal VCLK_PRESCALE_0_IBUF : STD_LOGIC; 
  signal VCLK_PRESCALE_4_IBUF : STD_LOGIC; 
  signal VCLK_PRESCALE_1_IBUF : STD_LOGIC; 
  signal VCLK_PRESCALE_2_IBUF : STD_LOGIC; 
  signal VCLK_PRESCALE_3_IBUF : STD_LOGIC; 
  signal DIN_0_IBUF : STD_LOGIC; 
  signal DIN_10_IBUF : STD_LOGIC; 
  signal DIN_11_IBUF : STD_LOGIC; 
  signal DIN_12_IBUF : STD_LOGIC; 
  signal DIN_13_IBUF : STD_LOGIC; 
  signal DIN_14_IBUF : STD_LOGIC; 
  signal DIN_15_IBUF : STD_LOGIC; 
  signal DIN_16_IBUF : STD_LOGIC; 
  signal DIN_17_IBUF : STD_LOGIC; 
  signal DIN_18_IBUF : STD_LOGIC; 
  signal DIN_19_IBUF : STD_LOGIC; 
  signal DIN_1_IBUF : STD_LOGIC; 
  signal DIN_20_IBUF : STD_LOGIC; 
  signal DIN_21_IBUF : STD_LOGIC; 
  signal DIN_22_IBUF : STD_LOGIC; 
  signal DIN_23_IBUF : STD_LOGIC; 
  signal DIN_24_IBUF : STD_LOGIC; 
  signal DIN_25_IBUF : STD_LOGIC; 
  signal DIN_26_IBUF : STD_LOGIC; 
  signal DIN_27_IBUF : STD_LOGIC; 
  signal DIN_28_IBUF : STD_LOGIC; 
  signal DIN_29_IBUF : STD_LOGIC; 
  signal DIN_2_IBUF : STD_LOGIC; 
  signal DIN_30_IBUF : STD_LOGIC; 
  signal DIN_3_IBUF : STD_LOGIC; 
  signal DIN_4_IBUF : STD_LOGIC; 
  signal DIN_5_IBUF : STD_LOGIC; 
  signal DIN_6_IBUF : STD_LOGIC; 
  signal DIN_7_IBUF : STD_LOGIC; 
  signal DIN_8_IBUF : STD_LOGIC; 
  signal DIN_9_IBUF : STD_LOGIC; 
  signal VCLK_PRESCALE_5_IBUF : STD_LOGIC; 
  signal REG_31_Q : STD_LOGIC; 
  signal REG_31_OE : STD_LOGIC; 
  signal VCLK_OBUF_Q : STD_LOGIC; 
  signal REG_31_Q_0 : STD_LOGIC; 
  signal REG_31_BUFOE_OUT : STD_LOGIC; 
  signal REG_31_D : STD_LOGIC; 
  signal REG_31_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_31_RSTF : STD_LOGIC; 
  signal REG_31_SETF : STD_LOGIC; 
  signal REG_31_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal REG_31_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_31_CLKF : STD_LOGIC; 
  signal Vcc : STD_LOGIC; 
  signal REG_31_D1 : STD_LOGIC; 
  signal REG_31_D2 : STD_LOGIC; 
  signal SHIFT_EN : STD_LOGIC; 
  signal SREG_IS_EMPTY : STD_LOGIC; 
  signal REG_31_D2_PT_0 : STD_LOGIC; 
  signal REG_31_D2_PT_1 : STD_LOGIC; 
  signal SCLK : STD_LOGIC; 
  signal SHIFT_EN_Q : STD_LOGIC; 
  signal SHIFT_EN_RSTF : STD_LOGIC; 
  signal SHIFT_EN_tsimcreated_prld_Q : STD_LOGIC; 
  signal SHIFT_EN_D : STD_LOGIC; 
  signal SHIFT_EN_CLKF : STD_LOGIC; 
  signal Gnd : STD_LOGIC; 
  signal SHIFT_EN_CE : STD_LOGIC; 
  signal SHIFT_EN_D1 : STD_LOGIC; 
  signal SHIFT_EN_D2 : STD_LOGIC; 
  signal count_0_Q : STD_LOGIC; 
  signal count_0_RSTF : STD_LOGIC; 
  signal count_0_SETF : STD_LOGIC; 
  signal count_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal count_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal count_0_D : STD_LOGIC; 
  signal count_0_D1 : STD_LOGIC; 
  signal count_0_D2 : STD_LOGIC; 
  signal count_0_D2_PT_0 : STD_LOGIC; 
  signal count_0_D2_PT_1 : STD_LOGIC; 
  signal count_0_D2_PT_2 : STD_LOGIC; 
  signal count_4_Q : STD_LOGIC; 
  signal count_4_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal count_4_EXP : STD_LOGIC; 
  signal count_4_D : STD_LOGIC; 
  signal count_4_tsimcreated_xor_Q : STD_LOGIC; 
  signal count_4_RSTF : STD_LOGIC; 
  signal count_4_SETF : STD_LOGIC; 
  signal count_4_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal count_4_tsimcreated_prld_Q : STD_LOGIC; 
  signal count_4_D1 : STD_LOGIC; 
  signal count_4_D2 : STD_LOGIC; 
  signal EXP19_EXP : STD_LOGIC; 
  signal count_4_D2_PT_0 : STD_LOGIC; 
  signal count_4_D2_PT_1 : STD_LOGIC; 
  signal count_4_D2_PT_2 : STD_LOGIC; 
  signal count_1_Q : STD_LOGIC; 
  signal count_1_RSTF : STD_LOGIC; 
  signal count_1_SETF : STD_LOGIC; 
  signal count_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal count_1_tsimcreated_prld_Q : STD_LOGIC; 
  signal count_1_D : STD_LOGIC; 
  signal count_1_D1 : STD_LOGIC; 
  signal count_1_D2 : STD_LOGIC; 
  signal count_5_EXP : STD_LOGIC; 
  signal count_1_D2_PT_0 : STD_LOGIC; 
  signal count_1_D2_PT_1 : STD_LOGIC; 
  signal count_1_D2_PT_2 : STD_LOGIC; 
  signal count_1_D2_PT_3 : STD_LOGIC; 
  signal count_2_Q : STD_LOGIC; 
  signal count_2_RSTF : STD_LOGIC; 
  signal count_2_SETF : STD_LOGIC; 
  signal count_2_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal count_2_tsimcreated_prld_Q : STD_LOGIC; 
  signal count_2_D : STD_LOGIC; 
  signal count_2_D1 : STD_LOGIC; 
  signal count_2_D2 : STD_LOGIC; 
  signal count_2_D2_PT_0 : STD_LOGIC; 
  signal count_3_EXP : STD_LOGIC; 
  signal count_2_D2_PT_1 : STD_LOGIC; 
  signal count_2_D2_PT_2 : STD_LOGIC; 
  signal count_2_D2_PT_3 : STD_LOGIC; 
  signal count_2_D2_PT_4 : STD_LOGIC; 
  signal count_3_Q : STD_LOGIC; 
  signal count_3_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal count_3_RSTF : STD_LOGIC; 
  signal count_3_SETF : STD_LOGIC; 
  signal count_3_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal count_3_tsimcreated_prld_Q : STD_LOGIC; 
  signal count_3_D : STD_LOGIC; 
  signal count_3_D1 : STD_LOGIC; 
  signal count_3_D2 : STD_LOGIC; 
  signal EXP20_EXP : STD_LOGIC; 
  signal count_3_D2_PT_0 : STD_LOGIC; 
  signal count_3_D2_PT_1 : STD_LOGIC; 
  signal count_3_D2_PT_2 : STD_LOGIC; 
  signal REG_0_Q : STD_LOGIC; 
  signal REG_0_D : STD_LOGIC; 
  signal REG_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_RSTF : STD_LOGIC; 
  signal REG_0_SETF : STD_LOGIC; 
  signal REG_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_CLKF : STD_LOGIC; 
  signal REG_0_D1 : STD_LOGIC; 
  signal REG_0_D2 : STD_LOGIC; 
  signal REG_10_Q : STD_LOGIC; 
  signal REG_10_D : STD_LOGIC; 
  signal REG_10_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_10_RSTF : STD_LOGIC; 
  signal REG_10_SETF : STD_LOGIC; 
  signal REG_10_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_10_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_10_CLKF : STD_LOGIC; 
  signal REG_10_D1 : STD_LOGIC; 
  signal REG_10_D2 : STD_LOGIC; 
  signal REG_10_D2_PT_0 : STD_LOGIC; 
  signal REG_10_D2_PT_1 : STD_LOGIC; 
  signal REG_11_Q : STD_LOGIC; 
  signal REG_11_D : STD_LOGIC; 
  signal REG_11_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_11_RSTF : STD_LOGIC; 
  signal REG_11_SETF : STD_LOGIC; 
  signal REG_11_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_11_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_11_CLKF : STD_LOGIC; 
  signal REG_11_D1 : STD_LOGIC; 
  signal REG_11_D2 : STD_LOGIC; 
  signal REG_11_D2_PT_0 : STD_LOGIC; 
  signal REG_11_D2_PT_1 : STD_LOGIC; 
  signal REG_12_Q : STD_LOGIC; 
  signal REG_12_D : STD_LOGIC; 
  signal REG_12_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_12_RSTF : STD_LOGIC; 
  signal REG_12_SETF : STD_LOGIC; 
  signal REG_12_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_12_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_12_CLKF : STD_LOGIC; 
  signal REG_12_D1 : STD_LOGIC; 
  signal REG_12_D2 : STD_LOGIC; 
  signal REG_12_D2_PT_0 : STD_LOGIC; 
  signal REG_12_D2_PT_1 : STD_LOGIC; 
  signal REG_13_Q : STD_LOGIC; 
  signal REG_13_D : STD_LOGIC; 
  signal REG_13_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_13_RSTF : STD_LOGIC; 
  signal REG_13_SETF : STD_LOGIC; 
  signal REG_13_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_13_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_13_CLKF : STD_LOGIC; 
  signal REG_13_D1 : STD_LOGIC; 
  signal REG_13_D2 : STD_LOGIC; 
  signal REG_13_D2_PT_0 : STD_LOGIC; 
  signal REG_13_D2_PT_1 : STD_LOGIC; 
  signal REG_14_Q : STD_LOGIC; 
  signal REG_14_D : STD_LOGIC; 
  signal REG_14_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_14_RSTF : STD_LOGIC; 
  signal REG_14_SETF : STD_LOGIC; 
  signal REG_14_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_14_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_14_CLKF : STD_LOGIC; 
  signal REG_14_D1 : STD_LOGIC; 
  signal REG_14_D2 : STD_LOGIC; 
  signal REG_14_D2_PT_0 : STD_LOGIC; 
  signal REG_14_D2_PT_1 : STD_LOGIC; 
  signal REG_15_Q : STD_LOGIC; 
  signal REG_15_D : STD_LOGIC; 
  signal REG_15_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_15_RSTF : STD_LOGIC; 
  signal REG_15_SETF : STD_LOGIC; 
  signal REG_15_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_15_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_15_CLKF : STD_LOGIC; 
  signal REG_15_D1 : STD_LOGIC; 
  signal REG_15_D2 : STD_LOGIC; 
  signal REG_15_D2_PT_0 : STD_LOGIC; 
  signal REG_15_D2_PT_1 : STD_LOGIC; 
  signal REG_16_Q : STD_LOGIC; 
  signal REG_16_D : STD_LOGIC; 
  signal REG_16_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_16_RSTF : STD_LOGIC; 
  signal REG_16_SETF : STD_LOGIC; 
  signal REG_16_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_16_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_16_CLKF : STD_LOGIC; 
  signal REG_16_D1 : STD_LOGIC; 
  signal REG_16_D2 : STD_LOGIC; 
  signal REG_16_D2_PT_0 : STD_LOGIC; 
  signal REG_16_D2_PT_1 : STD_LOGIC; 
  signal REG_17_Q : STD_LOGIC; 
  signal REG_17_D : STD_LOGIC; 
  signal REG_17_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_17_RSTF : STD_LOGIC; 
  signal REG_17_SETF : STD_LOGIC; 
  signal REG_17_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_17_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_17_CLKF : STD_LOGIC; 
  signal REG_17_D1 : STD_LOGIC; 
  signal REG_17_D2 : STD_LOGIC; 
  signal REG_17_D2_PT_0 : STD_LOGIC; 
  signal REG_17_D2_PT_1 : STD_LOGIC; 
  signal REG_18_Q : STD_LOGIC; 
  signal REG_18_D : STD_LOGIC; 
  signal REG_18_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_18_RSTF : STD_LOGIC; 
  signal REG_18_SETF : STD_LOGIC; 
  signal REG_18_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_18_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_18_CLKF : STD_LOGIC; 
  signal REG_18_D1 : STD_LOGIC; 
  signal REG_18_D2 : STD_LOGIC; 
  signal REG_18_D2_PT_0 : STD_LOGIC; 
  signal REG_18_D2_PT_1 : STD_LOGIC; 
  signal REG_19_Q : STD_LOGIC; 
  signal REG_19_D : STD_LOGIC; 
  signal REG_19_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_19_RSTF : STD_LOGIC; 
  signal REG_19_SETF : STD_LOGIC; 
  signal REG_19_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_19_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_19_CLKF : STD_LOGIC; 
  signal REG_19_D1 : STD_LOGIC; 
  signal REG_19_D2 : STD_LOGIC; 
  signal REG_19_D2_PT_0 : STD_LOGIC; 
  signal REG_19_D2_PT_1 : STD_LOGIC; 
  signal REG_1_Q : STD_LOGIC; 
  signal REG_1_D : STD_LOGIC; 
  signal REG_1_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_RSTF : STD_LOGIC; 
  signal REG_1_SETF : STD_LOGIC; 
  signal REG_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_CLKF : STD_LOGIC; 
  signal REG_1_D1 : STD_LOGIC; 
  signal REG_1_D2 : STD_LOGIC; 
  signal REG_1_D2_PT_0 : STD_LOGIC; 
  signal REG_1_D2_PT_1 : STD_LOGIC; 
  signal REG_20_Q : STD_LOGIC; 
  signal REG_20_D : STD_LOGIC; 
  signal REG_20_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_20_RSTF : STD_LOGIC; 
  signal REG_20_SETF : STD_LOGIC; 
  signal REG_20_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_20_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_20_CLKF : STD_LOGIC; 
  signal REG_20_D1 : STD_LOGIC; 
  signal REG_20_D2 : STD_LOGIC; 
  signal REG_20_D2_PT_0 : STD_LOGIC; 
  signal REG_20_D2_PT_1 : STD_LOGIC; 
  signal REG_21_Q : STD_LOGIC; 
  signal REG_21_D : STD_LOGIC; 
  signal REG_21_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_21_RSTF : STD_LOGIC; 
  signal REG_21_SETF : STD_LOGIC; 
  signal REG_21_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_21_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_21_CLKF : STD_LOGIC; 
  signal REG_21_D1 : STD_LOGIC; 
  signal REG_21_D2 : STD_LOGIC; 
  signal REG_21_D2_PT_0 : STD_LOGIC; 
  signal REG_21_D2_PT_1 : STD_LOGIC; 
  signal REG_22_Q : STD_LOGIC; 
  signal REG_22_D : STD_LOGIC; 
  signal REG_22_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_22_RSTF : STD_LOGIC; 
  signal REG_22_SETF : STD_LOGIC; 
  signal REG_22_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_22_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_22_CLKF : STD_LOGIC; 
  signal REG_22_D1 : STD_LOGIC; 
  signal REG_22_D2 : STD_LOGIC; 
  signal REG_22_D2_PT_0 : STD_LOGIC; 
  signal REG_22_D2_PT_1 : STD_LOGIC; 
  signal REG_23_Q : STD_LOGIC; 
  signal REG_23_D : STD_LOGIC; 
  signal REG_23_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_23_RSTF : STD_LOGIC; 
  signal REG_23_SETF : STD_LOGIC; 
  signal REG_23_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_23_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_23_CLKF : STD_LOGIC; 
  signal REG_23_D1 : STD_LOGIC; 
  signal REG_23_D2 : STD_LOGIC; 
  signal REG_23_D2_PT_0 : STD_LOGIC; 
  signal REG_23_D2_PT_1 : STD_LOGIC; 
  signal REG_24_Q : STD_LOGIC; 
  signal REG_24_D : STD_LOGIC; 
  signal REG_24_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_24_RSTF : STD_LOGIC; 
  signal REG_24_SETF : STD_LOGIC; 
  signal REG_24_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_24_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_24_CLKF : STD_LOGIC; 
  signal REG_24_D1 : STD_LOGIC; 
  signal REG_24_D2 : STD_LOGIC; 
  signal REG_24_D2_PT_0 : STD_LOGIC; 
  signal REG_24_D2_PT_1 : STD_LOGIC; 
  signal REG_25_Q : STD_LOGIC; 
  signal REG_25_D : STD_LOGIC; 
  signal REG_25_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_25_RSTF : STD_LOGIC; 
  signal REG_25_SETF : STD_LOGIC; 
  signal REG_25_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_25_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_25_CLKF : STD_LOGIC; 
  signal REG_25_D1 : STD_LOGIC; 
  signal REG_25_D2 : STD_LOGIC; 
  signal REG_25_D2_PT_0 : STD_LOGIC; 
  signal REG_25_D2_PT_1 : STD_LOGIC; 
  signal REG_26_Q : STD_LOGIC; 
  signal REG_26_D : STD_LOGIC; 
  signal REG_26_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_26_RSTF : STD_LOGIC; 
  signal REG_26_SETF : STD_LOGIC; 
  signal REG_26_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_26_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_26_CLKF : STD_LOGIC; 
  signal REG_26_D1 : STD_LOGIC; 
  signal REG_26_D2 : STD_LOGIC; 
  signal REG_26_D2_PT_0 : STD_LOGIC; 
  signal REG_26_D2_PT_1 : STD_LOGIC; 
  signal REG_27_Q : STD_LOGIC; 
  signal REG_27_D : STD_LOGIC; 
  signal REG_27_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_27_RSTF : STD_LOGIC; 
  signal REG_27_SETF : STD_LOGIC; 
  signal REG_27_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_27_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_27_CLKF : STD_LOGIC; 
  signal REG_27_D1 : STD_LOGIC; 
  signal REG_27_D2 : STD_LOGIC; 
  signal REG_27_D2_PT_0 : STD_LOGIC; 
  signal REG_27_D2_PT_1 : STD_LOGIC; 
  signal REG_28_Q : STD_LOGIC; 
  signal REG_28_D : STD_LOGIC; 
  signal REG_28_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_28_RSTF : STD_LOGIC; 
  signal REG_28_SETF : STD_LOGIC; 
  signal REG_28_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_28_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_28_CLKF : STD_LOGIC; 
  signal REG_28_D1 : STD_LOGIC; 
  signal REG_28_D2 : STD_LOGIC; 
  signal REG_28_D2_PT_0 : STD_LOGIC; 
  signal REG_28_D2_PT_1 : STD_LOGIC; 
  signal REG_29_Q : STD_LOGIC; 
  signal REG_29_D : STD_LOGIC; 
  signal REG_29_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_29_RSTF : STD_LOGIC; 
  signal REG_29_SETF : STD_LOGIC; 
  signal REG_29_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_29_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_29_CLKF : STD_LOGIC; 
  signal REG_29_D1 : STD_LOGIC; 
  signal REG_29_D2 : STD_LOGIC; 
  signal REG_29_D2_PT_0 : STD_LOGIC; 
  signal REG_29_D2_PT_1 : STD_LOGIC; 
  signal REG_2_Q : STD_LOGIC; 
  signal REG_2_D : STD_LOGIC; 
  signal REG_2_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_2_RSTF : STD_LOGIC; 
  signal REG_2_SETF : STD_LOGIC; 
  signal REG_2_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_2_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_2_CLKF : STD_LOGIC; 
  signal REG_2_D1 : STD_LOGIC; 
  signal REG_2_D2 : STD_LOGIC; 
  signal REG_2_D2_PT_0 : STD_LOGIC; 
  signal REG_2_D2_PT_1 : STD_LOGIC; 
  signal REG_30_Q : STD_LOGIC; 
  signal REG_30_D : STD_LOGIC; 
  signal REG_30_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_30_RSTF : STD_LOGIC; 
  signal REG_30_SETF : STD_LOGIC; 
  signal REG_30_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_30_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_30_CLKF : STD_LOGIC; 
  signal REG_30_D1 : STD_LOGIC; 
  signal REG_30_D2 : STD_LOGIC; 
  signal REG_30_D2_PT_0 : STD_LOGIC; 
  signal REG_30_D2_PT_1 : STD_LOGIC; 
  signal REG_3_Q : STD_LOGIC; 
  signal REG_3_D : STD_LOGIC; 
  signal REG_3_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_3_RSTF : STD_LOGIC; 
  signal REG_3_SETF : STD_LOGIC; 
  signal REG_3_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_3_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_3_CLKF : STD_LOGIC; 
  signal REG_3_D1 : STD_LOGIC; 
  signal REG_3_D2 : STD_LOGIC; 
  signal REG_3_D2_PT_0 : STD_LOGIC; 
  signal REG_3_D2_PT_1 : STD_LOGIC; 
  signal REG_4_Q : STD_LOGIC; 
  signal REG_4_D : STD_LOGIC; 
  signal REG_4_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_4_RSTF : STD_LOGIC; 
  signal REG_4_SETF : STD_LOGIC; 
  signal REG_4_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_4_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_4_CLKF : STD_LOGIC; 
  signal REG_4_D1 : STD_LOGIC; 
  signal REG_4_D2 : STD_LOGIC; 
  signal REG_4_D2_PT_0 : STD_LOGIC; 
  signal REG_4_D2_PT_1 : STD_LOGIC; 
  signal REG_5_Q : STD_LOGIC; 
  signal REG_5_D : STD_LOGIC; 
  signal REG_5_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_5_RSTF : STD_LOGIC; 
  signal REG_5_SETF : STD_LOGIC; 
  signal REG_5_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_5_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_5_CLKF : STD_LOGIC; 
  signal REG_5_D1 : STD_LOGIC; 
  signal REG_5_D2 : STD_LOGIC; 
  signal REG_5_D2_PT_0 : STD_LOGIC; 
  signal REG_5_D2_PT_1 : STD_LOGIC; 
  signal REG_6_Q : STD_LOGIC; 
  signal REG_6_D : STD_LOGIC; 
  signal REG_6_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_6_RSTF : STD_LOGIC; 
  signal REG_6_SETF : STD_LOGIC; 
  signal REG_6_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_6_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_6_CLKF : STD_LOGIC; 
  signal REG_6_D1 : STD_LOGIC; 
  signal REG_6_D2 : STD_LOGIC; 
  signal REG_6_D2_PT_0 : STD_LOGIC; 
  signal REG_6_D2_PT_1 : STD_LOGIC; 
  signal REG_7_Q : STD_LOGIC; 
  signal REG_7_D : STD_LOGIC; 
  signal REG_7_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_7_RSTF : STD_LOGIC; 
  signal REG_7_SETF : STD_LOGIC; 
  signal REG_7_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_7_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_7_CLKF : STD_LOGIC; 
  signal REG_7_D1 : STD_LOGIC; 
  signal REG_7_D2 : STD_LOGIC; 
  signal REG_7_D2_PT_0 : STD_LOGIC; 
  signal REG_7_D2_PT_1 : STD_LOGIC; 
  signal REG_8_Q : STD_LOGIC; 
  signal REG_8_D : STD_LOGIC; 
  signal REG_8_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_8_RSTF : STD_LOGIC; 
  signal REG_8_SETF : STD_LOGIC; 
  signal REG_8_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_8_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_8_CLKF : STD_LOGIC; 
  signal REG_8_D1 : STD_LOGIC; 
  signal REG_8_D2 : STD_LOGIC; 
  signal REG_8_D2_PT_0 : STD_LOGIC; 
  signal REG_8_D2_PT_1 : STD_LOGIC; 
  signal REG_9_Q : STD_LOGIC; 
  signal REG_9_D : STD_LOGIC; 
  signal REG_9_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_9_RSTF : STD_LOGIC; 
  signal REG_9_SETF : STD_LOGIC; 
  signal REG_9_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_9_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_9_CLKF : STD_LOGIC; 
  signal REG_9_D1 : STD_LOGIC; 
  signal REG_9_D2 : STD_LOGIC; 
  signal REG_9_D2_PT_0 : STD_LOGIC; 
  signal REG_9_D2_PT_1 : STD_LOGIC; 
  signal count_5_Q : STD_LOGIC; 
  signal count_5_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal count_5_D : STD_LOGIC; 
  signal count_5_tsimcreated_xor_Q : STD_LOGIC; 
  signal count_5_RSTF : STD_LOGIC; 
  signal count_5_SETF : STD_LOGIC; 
  signal count_5_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal count_5_tsimcreated_prld_Q : STD_LOGIC; 
  signal count_5_D1 : STD_LOGIC; 
  signal count_5_D2 : STD_LOGIC; 
  signal EXP18_EXP : STD_LOGIC; 
  signal count_5_D2_PT_0 : STD_LOGIC; 
  signal count_5_D2_PT_1 : STD_LOGIC; 
  signal count_5_D2_PT_2 : STD_LOGIC; 
  signal SREG_IS_EMPTY_Q : STD_LOGIC; 
  signal SREG_IS_EMPTY_RSTF : STD_LOGIC; 
  signal SREG_IS_EMPTY_SETF : STD_LOGIC; 
  signal SREG_IS_EMPTY_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal SREG_IS_EMPTY_tsimcreated_prld_Q : STD_LOGIC; 
  signal SREG_IS_EMPTY_D : STD_LOGIC; 
  signal SREG_IS_EMPTY_CLKF : STD_LOGIC; 
  signal SREG_IS_EMPTY_D1 : STD_LOGIC; 
  signal SREG_IS_EMPTY_D2 : STD_LOGIC; 
  signal SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_UIM : STD_LOGIC; 
  signal SHIFT_CNT_0_Q : STD_LOGIC; 
  signal SHIFT_CNT_0_RSTF : STD_LOGIC; 
  signal SHIFT_CNT_0_SETF : STD_LOGIC; 
  signal SHIFT_CNT_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal SHIFT_CNT_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal SHIFT_CNT_0_D : STD_LOGIC; 
  signal SHIFT_CNT_0_CLKF : STD_LOGIC; 
  signal SHIFT_CNT_0_D1 : STD_LOGIC; 
  signal SHIFT_CNT_0_D2 : STD_LOGIC; 
  signal SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_UIM : STD_LOGIC; 
  signal SHIFT_CNT_1_Q : STD_LOGIC; 
  signal SHIFT_CNT_1_RSTF : STD_LOGIC; 
  signal SHIFT_CNT_1_SETF : STD_LOGIC; 
  signal SHIFT_CNT_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal SHIFT_CNT_1_tsimcreated_prld_Q : STD_LOGIC; 
  signal SHIFT_CNT_1_D : STD_LOGIC; 
  signal SHIFT_CNT_1_CLKF : STD_LOGIC; 
  signal SHIFT_CNT_1_D1 : STD_LOGIC; 
  signal SHIFT_CNT_1_D2 : STD_LOGIC; 
  signal SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_UIM : STD_LOGIC; 
  signal Msub_n0025_n00002_Msub_n0025_n00002_D2_UIM : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_18_INV_124_UIM : STD_LOGIC; 
  signal SHIFT_CNT_2_Q : STD_LOGIC; 
  signal SHIFT_CNT_2_RSTF : STD_LOGIC; 
  signal SHIFT_CNT_2_SETF : STD_LOGIC; 
  signal SHIFT_CNT_2_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal SHIFT_CNT_2_tsimcreated_prld_Q : STD_LOGIC; 
  signal SHIFT_CNT_2_D : STD_LOGIC; 
  signal SHIFT_CNT_2_CLKF : STD_LOGIC; 
  signal SHIFT_CNT_2_D1 : STD_LOGIC; 
  signal SHIFT_CNT_2_D2 : STD_LOGIC; 
  signal SHIFT_CNT_2_SHIFT_CNT_2_RSTF_UIM : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_23_INV_125_UIM : STD_LOGIC; 
  signal SHIFT_CNT_3_Q : STD_LOGIC; 
  signal SHIFT_CNT_3_RSTF : STD_LOGIC; 
  signal SHIFT_CNT_3_SETF : STD_LOGIC; 
  signal SHIFT_CNT_3_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal SHIFT_CNT_3_tsimcreated_prld_Q : STD_LOGIC; 
  signal SHIFT_CNT_3_D : STD_LOGIC; 
  signal SHIFT_CNT_3_CLKF : STD_LOGIC; 
  signal SHIFT_CNT_3_D1 : STD_LOGIC; 
  signal SHIFT_CNT_3_D2 : STD_LOGIC; 
  signal SHIFT_CNT_3_SHIFT_CNT_3_RSTF_UIM : STD_LOGIC; 
  signal Msub_n0025_n00022_Msub_n0025_n00022_D2_UIM : STD_LOGIC; 
  signal Q_OpTx_FX_DC_20_UIM : STD_LOGIC; 
  signal SHIFT_CNT_4_Q : STD_LOGIC; 
  signal SHIFT_CNT_4_RSTF : STD_LOGIC; 
  signal SHIFT_CNT_4_SETF : STD_LOGIC; 
  signal SHIFT_CNT_4_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal SHIFT_CNT_4_tsimcreated_prld_Q : STD_LOGIC; 
  signal SHIFT_CNT_4_D : STD_LOGIC; 
  signal SHIFT_CNT_4_CLKF : STD_LOGIC; 
  signal SHIFT_CNT_4_D1 : STD_LOGIC; 
  signal SHIFT_CNT_4_D2 : STD_LOGIC; 
  signal SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_UIM : STD_LOGIC; 
  signal Q_OpTx_FX_DC_21_UIM : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_SC_22_INV_126_UIM : STD_LOGIC; 
  signal VCLK_OBUF_Q_1 : STD_LOGIC; 
  signal VCLK_OBUF_D : STD_LOGIC; 
  signal VCLK_OBUF_tsimcreated_xor_Q : STD_LOGIC; 
  signal VCLK_OBUF_RSTF : STD_LOGIC; 
  signal VCLK_OBUF_CE : STD_LOGIC; 
  signal VCLK_OBUF_D1 : STD_LOGIC; 
  signal VCLK_OBUF_D2 : STD_LOGIC; 
  signal SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_Q : STD_LOGIC; 
  signal SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D : STD_LOGIC; 
  signal SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D1 : STD_LOGIC; 
  signal SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2 : STD_LOGIC; 
  signal SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_0 : STD_LOGIC; 
  signal SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1 : STD_LOGIC; 
  signal SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_Q : STD_LOGIC; 
  signal SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D : STD_LOGIC; 
  signal SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D1 : STD_LOGIC; 
  signal SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2 : STD_LOGIC; 
  signal SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0 : STD_LOGIC; 
  signal SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1 : STD_LOGIC; 
  signal SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2 : STD_LOGIC; 
  signal SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3 : STD_LOGIC; 
  signal SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_Q : STD_LOGIC; 
  signal SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D : STD_LOGIC; 
  signal SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D1 : STD_LOGIC; 
  signal SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2 : STD_LOGIC; 
  signal SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0 : STD_LOGIC; 
  signal SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1 : STD_LOGIC; 
  signal SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2 : STD_LOGIC; 
  signal SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3 : STD_LOGIC; 
  signal SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4 : STD_LOGIC; 
  signal Msub_n0025_n00002_Msub_n0025_n00002_D2_Q : STD_LOGIC; 
  signal Msub_n0025_n00002_Msub_n0025_n00002_D2_D : STD_LOGIC; 
  signal Msub_n0025_n00002_Msub_n0025_n00002_D2_D1 : STD_LOGIC; 
  signal Msub_n0025_n00002_Msub_n0025_n00002_D2_D2 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_18_INV_124_Q : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_18_INV_124_D : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_18_INV_124_D1 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_18_INV_124_D2 : STD_LOGIC; 
  signal SHIFT_CNT_2_SHIFT_CNT_2_RSTF_Q : STD_LOGIC; 
  signal SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D : STD_LOGIC; 
  signal SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D1 : STD_LOGIC; 
  signal SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2 : STD_LOGIC; 
  signal SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0 : STD_LOGIC; 
  signal SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1 : STD_LOGIC; 
  signal SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_23_INV_125_Q : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_23_INV_125_D : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_23_INV_125_D1 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_23_INV_125_D2 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2 : STD_LOGIC; 
  signal SHIFT_CNT_3_SHIFT_CNT_3_RSTF_Q : STD_LOGIC; 
  signal SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D : STD_LOGIC; 
  signal SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D1 : STD_LOGIC; 
  signal SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2 : STD_LOGIC; 
  signal SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0 : STD_LOGIC; 
  signal SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1 : STD_LOGIC; 
  signal SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2 : STD_LOGIC; 
  signal SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3 : STD_LOGIC; 
  signal Msub_n0025_n00022_Msub_n0025_n00022_D2_Q : STD_LOGIC; 
  signal Msub_n0025_n00022_Msub_n0025_n00022_D2_D : STD_LOGIC; 
  signal Msub_n0025_n00022_Msub_n0025_n00022_D2_D1 : STD_LOGIC; 
  signal Msub_n0025_n00022_Msub_n0025_n00022_D2_D2 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_20_Q : STD_LOGIC; 
  signal Q_OpTx_FX_DC_20_D : STD_LOGIC; 
  signal Q_OpTx_FX_DC_20_D1 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_20_D2 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_20_D2_PT_0 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_20_D2_PT_1 : STD_LOGIC; 
  signal SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_Q : STD_LOGIC; 
  signal SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D : STD_LOGIC; 
  signal SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D1 : STD_LOGIC; 
  signal SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2 : STD_LOGIC; 
  signal SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0 : STD_LOGIC; 
  signal SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1 : STD_LOGIC; 
  signal SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2 : STD_LOGIC; 
  signal SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_21_Q : STD_LOGIC; 
  signal Q_OpTx_FX_DC_21_D : STD_LOGIC; 
  signal Q_OpTx_FX_DC_21_D1 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_21_D2 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_21_D2_PT_0 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_21_D2_PT_1 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_SC_22_INV_126_Q : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_SC_22_INV_126_D : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_SC_22_INV_126_D1 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_SC_22_INV_126_D2 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_0 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_1 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3 : STD_LOGIC; 
  signal EXP18_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP18_EXP_PT_0 : STD_LOGIC; 
  signal EXP18_EXP_PT_1 : STD_LOGIC; 
  signal EXP19_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP19_EXP_PT_0 : STD_LOGIC; 
  signal EXP19_EXP_PT_1 : STD_LOGIC; 
  signal EXP19_EXP_PT_2 : STD_LOGIC; 
  signal EXP20_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP20_EXP_PT_0 : STD_LOGIC; 
  signal EXP20_EXP_PT_1 : STD_LOGIC; 
  signal EXP20_EXP_PT_2 : STD_LOGIC; 
  signal EXP20_EXP_PT_3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_31_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_31_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_31_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_31_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_31_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_31_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_31_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_31_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_31_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_31_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_31_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_31_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_CE_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_CE_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_D2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_10_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_10_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_10_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_10_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_10_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_10_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_10_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_10_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_10_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_10_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_10_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_10_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_11_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_11_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_11_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_11_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_11_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_11_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_11_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_11_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_11_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_11_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_11_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_11_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_12_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_12_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_12_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_12_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_12_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_12_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_12_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_12_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_12_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_12_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_12_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_12_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_13_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_13_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_13_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_13_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_13_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_13_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_13_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_13_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_13_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_13_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_13_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_13_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_14_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_14_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_14_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_14_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_14_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_14_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_14_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_14_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_14_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_14_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_14_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_14_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_15_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_15_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_15_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_15_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_15_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_15_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_15_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_15_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_15_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_15_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_15_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_15_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_16_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_16_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_16_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_16_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_16_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_16_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_16_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_16_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_16_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_16_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_16_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_16_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_17_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_17_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_17_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_17_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_17_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_17_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_17_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_17_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_17_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_17_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_17_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_17_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_18_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_18_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_18_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_18_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_18_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_18_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_18_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_18_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_18_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_18_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_18_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_18_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_19_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_19_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_19_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_19_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_19_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_19_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_19_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_19_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_19_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_19_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_19_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_19_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_20_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_20_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_20_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_20_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_20_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_20_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_20_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_20_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_20_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_20_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_20_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_20_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_21_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_21_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_21_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_21_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_21_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_21_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_21_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_21_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_21_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_21_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_21_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_21_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_22_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_22_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_22_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_22_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_22_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_22_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_22_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_22_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_22_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_22_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_22_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_22_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_23_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_23_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_23_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_23_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_23_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_23_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_23_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_23_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_23_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_23_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_23_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_23_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_24_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_24_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_24_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_24_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_24_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_24_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_24_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_24_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_24_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_24_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_24_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_24_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_25_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_25_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_25_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_25_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_25_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_25_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_25_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_25_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_25_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_25_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_25_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_25_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_26_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_26_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_26_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_26_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_26_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_26_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_26_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_26_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_26_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_26_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_26_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_26_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_27_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_27_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_27_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_27_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_27_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_27_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_27_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_27_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_27_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_27_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_27_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_27_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_28_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_28_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_28_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_28_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_28_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_28_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_28_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_28_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_28_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_28_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_28_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_28_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_29_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_29_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_29_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_29_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_29_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_29_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_29_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_29_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_29_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_29_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_29_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_29_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_2_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_2_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_2_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_2_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_2_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_2_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_2_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_2_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_2_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_2_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_2_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_2_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_30_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_30_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_30_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_30_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_30_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_30_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_30_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_30_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_30_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_30_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_30_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_30_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_3_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_3_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_3_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_3_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_3_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_3_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_3_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_3_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_3_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_3_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_3_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_3_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_4_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_4_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_4_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_4_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_4_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_4_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_4_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_4_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_4_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_4_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_4_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_4_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_5_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_5_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_5_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_5_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_5_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_5_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_5_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_5_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_5_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_5_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_5_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_5_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_6_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_6_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_6_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_6_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_6_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_6_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_6_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_6_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_6_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_6_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_6_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_6_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_7_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_7_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_7_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_7_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_7_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_7_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_7_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_7_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_7_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_7_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_7_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_7_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_8_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_8_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_8_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_8_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_8_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_8_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_8_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_8_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_8_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_8_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_8_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_8_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_9_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_9_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_9_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_9_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_9_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_9_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_9_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_9_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_9_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_9_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_9_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_9_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SREG_IS_EMPTY_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SREG_IS_EMPTY_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_SETF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_SETF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_RSTF_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_RSTF_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_SETF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_SETF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_RSTF_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_SETF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_VCLK_OBUF_CE_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_VCLK_OBUF_CE_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_VCLK_OBUF_CE_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_VCLK_OBUF_CE_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_VCLK_OBUF_CE_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_VCLK_OBUF_CE_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Msub_n0025_n00002_Msub_n0025_n00002_D2_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Msub_n0025_n00002_Msub_n0025_n00002_D2_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_FX_DC_20_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_FX_DC_20_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_FX_DC_20_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_FX_DC_20_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_FX_DC_20_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_FX_DC_21_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_FX_DC_21_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP20_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP20_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP20_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP20_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP20_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP20_EXP_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP20_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP20_EXP_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP20_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP20_EXP_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP20_EXP_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP20_EXP_PT_3_IN3 : STD_LOGIC; 
  signal REG : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal count : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal SHIFT_CNT : STD_LOGIC_VECTOR ( 4 downto 0 ); 
begin
  FOEIO_1_2 : X_BUF
    port map (
      I => nINIT_B,
      O => FOEIO_1
    );
  LOAD_IBUF_3 : X_BUF
    port map (
      I => LOAD,
      O => LOAD_IBUF
    );
  DIN_31_IBUF_4 : X_BUF
    port map (
      I => DIN(31),
      O => DIN_31_IBUF
    );
  RES_IBUF_5 : X_BUF
    port map (
      I => RES,
      O => RES_IBUF
    );
  DONE_IBUF_6 : X_BUF
    port map (
      I => DONE,
      O => DONE_IBUF
    );
  FCLKIO_0_7 : X_BUF
    port map (
      I => CLK,
      O => FCLKIO_0
    );
  VCLK_PRESCALE_0_IBUF_8 : X_BUF
    port map (
      I => VCLK_PRESCALE(0),
      O => VCLK_PRESCALE_0_IBUF
    );
  VCLK_PRESCALE_4_IBUF_9 : X_BUF
    port map (
      I => VCLK_PRESCALE(4),
      O => VCLK_PRESCALE_4_IBUF
    );
  VCLK_PRESCALE_1_IBUF_10 : X_BUF
    port map (
      I => VCLK_PRESCALE(1),
      O => VCLK_PRESCALE_1_IBUF
    );
  VCLK_PRESCALE_2_IBUF_11 : X_BUF
    port map (
      I => VCLK_PRESCALE(2),
      O => VCLK_PRESCALE_2_IBUF
    );
  VCLK_PRESCALE_3_IBUF_12 : X_BUF
    port map (
      I => VCLK_PRESCALE(3),
      O => VCLK_PRESCALE_3_IBUF
    );
  DIN_0_IBUF_13 : X_BUF
    port map (
      I => DIN(0),
      O => DIN_0_IBUF
    );
  DIN_10_IBUF_14 : X_BUF
    port map (
      I => DIN(10),
      O => DIN_10_IBUF
    );
  DIN_11_IBUF_15 : X_BUF
    port map (
      I => DIN(11),
      O => DIN_11_IBUF
    );
  DIN_12_IBUF_16 : X_BUF
    port map (
      I => DIN(12),
      O => DIN_12_IBUF
    );
  DIN_13_IBUF_17 : X_BUF
    port map (
      I => DIN(13),
      O => DIN_13_IBUF
    );
  DIN_14_IBUF_18 : X_BUF
    port map (
      I => DIN(14),
      O => DIN_14_IBUF
    );
  DIN_15_IBUF_19 : X_BUF
    port map (
      I => DIN(15),
      O => DIN_15_IBUF
    );
  DIN_16_IBUF_20 : X_BUF
    port map (
      I => DIN(16),
      O => DIN_16_IBUF
    );
  DIN_17_IBUF_21 : X_BUF
    port map (
      I => DIN(17),
      O => DIN_17_IBUF
    );
  DIN_18_IBUF_22 : X_BUF
    port map (
      I => DIN(18),
      O => DIN_18_IBUF
    );
  DIN_19_IBUF_23 : X_BUF
    port map (
      I => DIN(19),
      O => DIN_19_IBUF
    );
  DIN_1_IBUF_24 : X_BUF
    port map (
      I => DIN(1),
      O => DIN_1_IBUF
    );
  DIN_20_IBUF_25 : X_BUF
    port map (
      I => DIN(20),
      O => DIN_20_IBUF
    );
  DIN_21_IBUF_26 : X_BUF
    port map (
      I => DIN(21),
      O => DIN_21_IBUF
    );
  DIN_22_IBUF_27 : X_BUF
    port map (
      I => DIN(22),
      O => DIN_22_IBUF
    );
  DIN_23_IBUF_28 : X_BUF
    port map (
      I => DIN(23),
      O => DIN_23_IBUF
    );
  DIN_24_IBUF_29 : X_BUF
    port map (
      I => DIN(24),
      O => DIN_24_IBUF
    );
  DIN_25_IBUF_30 : X_BUF
    port map (
      I => DIN(25),
      O => DIN_25_IBUF
    );
  DIN_26_IBUF_31 : X_BUF
    port map (
      I => DIN(26),
      O => DIN_26_IBUF
    );
  DIN_27_IBUF_32 : X_BUF
    port map (
      I => DIN(27),
      O => DIN_27_IBUF
    );
  DIN_28_IBUF_33 : X_BUF
    port map (
      I => DIN(28),
      O => DIN_28_IBUF
    );
  DIN_29_IBUF_34 : X_BUF
    port map (
      I => DIN(29),
      O => DIN_29_IBUF
    );
  DIN_2_IBUF_35 : X_BUF
    port map (
      I => DIN(2),
      O => DIN_2_IBUF
    );
  DIN_30_IBUF_36 : X_BUF
    port map (
      I => DIN(30),
      O => DIN_30_IBUF
    );
  DIN_3_IBUF_37 : X_BUF
    port map (
      I => DIN(3),
      O => DIN_3_IBUF
    );
  DIN_4_IBUF_38 : X_BUF
    port map (
      I => DIN(4),
      O => DIN_4_IBUF
    );
  DIN_5_IBUF_39 : X_BUF
    port map (
      I => DIN(5),
      O => DIN_5_IBUF
    );
  DIN_6_IBUF_40 : X_BUF
    port map (
      I => DIN(6),
      O => DIN_6_IBUF
    );
  DIN_7_IBUF_41 : X_BUF
    port map (
      I => DIN(7),
      O => DIN_7_IBUF
    );
  DIN_8_IBUF_42 : X_BUF
    port map (
      I => DIN(8),
      O => DIN_8_IBUF
    );
  DIN_9_IBUF_43 : X_BUF
    port map (
      I => DIN(9),
      O => DIN_9_IBUF
    );
  VCLK_PRESCALE_5_IBUF_44 : X_BUF
    port map (
      I => VCLK_PRESCALE(5),
      O => VCLK_PRESCALE_5_IBUF
    );
  DOUT_45 : X_TRI
    port map (
      I => REG_31_Q,
      CTL => REG_31_OE,
      O => DOUT
    );
  VCLK_46 : X_BUF
    port map (
      I => VCLK_OBUF_Q,
      O => VCLK
    );
  REG_31_Q_47 : X_BUF
    port map (
      I => REG_31_Q_0,
      O => REG_31_Q
    );
  REG_31_Q_48 : X_BUF
    port map (
      I => REG_31_Q_0,
      O => REG(31)
    );
  REG_31_OE_49 : X_BUF
    port map (
      I => REG_31_BUFOE_OUT,
      O => REG_31_OE
    );
  REG_31_BUFOE_OUT_50 : X_BUF
    port map (
      I => FOEIO_1,
      O => REG_31_BUFOE_OUT
    );
  REG_31_tsimcreated_xor_Q_51 : X_XOR2
    port map (
      I0 => REG_31_D,
      I1 => REG_31_Q_0,
      O => REG_31_tsimcreated_xor_Q
    );
  REG_31_tsimcreated_set_and_noreset_Q_52 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_31_tsimcreated_set_and_noreset_IN0,
      I1 => REG_31_SETF,
      O => REG_31_tsimcreated_set_and_noreset_Q
    );
  REG_31_tsimcreated_prld_Q_53 : X_OR2
    port map (
      I0 => REG_31_RSTF,
      I1 => PRLD,
      O => REG_31_tsimcreated_prld_Q
    );
  REG_31_REG : X_FF
    port map (
      I => REG_31_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_31_CLKF,
      SET => REG_31_tsimcreated_set_and_noreset_Q,
      RST => REG_31_tsimcreated_prld_Q,
      O => REG_31_Q_0
    );
  Vcc_54 : X_ONE
    port map (
      O => Vcc
    );
  REG_31_D_55 : X_XOR2
    port map (
      I0 => REG_31_D1,
      I1 => REG_31_D2,
      O => REG_31_D
    );
  REG_31_D1_56 : X_ZERO
    port map (
      O => REG_31_D1
    );
  REG_31_D2_PT_0_57 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_31_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_31_D2_PT_0_IN1,
      I2 => REG(31),
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_REG_31_D2_PT_0_IN4,
      I5 => NlwInverterSignal_REG_31_D2_PT_0_IN5,
      O => REG_31_D2_PT_0
    );
  REG_31_D2_PT_1_58 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_31_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_31_D2_PT_1_IN1,
      I2 => NlwInverterSignal_REG_31_D2_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => REG(30),
      I5 => NlwInverterSignal_REG_31_D2_PT_1_IN5,
      O => REG_31_D2_PT_1
    );
  REG_31_D2_59 : X_OR2
    port map (
      I0 => REG_31_D2_PT_0,
      I1 => REG_31_D2_PT_1,
      O => REG_31_D2
    );
  REG_31_CLKF_60 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_31_CLKF_IN0,
      I1 => NlwInverterSignal_REG_31_CLKF_IN1,
      O => REG_31_CLKF
    );
  REG_31_SETF_61 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => DIN_31_IBUF,
      I2 => SREG_IS_EMPTY,
      O => REG_31_SETF
    );
  REG_31_RSTF_62 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => NlwInverterSignal_REG_31_RSTF_IN1,
      I2 => SREG_IS_EMPTY,
      O => REG_31_RSTF
    );
  SHIFT_EN_63 : X_BUF
    port map (
      I => SHIFT_EN_Q,
      O => SHIFT_EN
    );
  SHIFT_EN_tsimcreated_prld_Q_64 : X_OR2
    port map (
      I0 => SHIFT_EN_RSTF,
      I1 => PRLD,
      O => SHIFT_EN_tsimcreated_prld_Q
    );
  SHIFT_EN_REG : X_FF
    port map (
      I => SHIFT_EN_D,
      CE => SHIFT_EN_CE,
      CLK => SHIFT_EN_CLKF,
      SET => Gnd,
      RST => SHIFT_EN_tsimcreated_prld_Q,
      O => SHIFT_EN_Q
    );
  Gnd_65 : X_ZERO
    port map (
      O => Gnd
    );
  SHIFT_EN_D_66 : X_XOR2
    port map (
      I0 => SHIFT_EN_D1,
      I1 => SHIFT_EN_D2,
      O => SHIFT_EN_D
    );
  SHIFT_EN_D1_67 : X_ZERO
    port map (
      O => SHIFT_EN_D1
    );
  SHIFT_EN_D2_68 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_EN_D2_IN0,
      I1 => NlwInverterSignal_SHIFT_EN_D2_IN1,
      O => SHIFT_EN_D2
    );
  SHIFT_EN_CLKF_69 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_EN_CLKF_IN0,
      I1 => NlwInverterSignal_SHIFT_EN_CLKF_IN1,
      O => SHIFT_EN_CLKF
    );
  SHIFT_EN_RSTF_70 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => RES_IBUF,
      O => SHIFT_EN_RSTF
    );
  SHIFT_EN_CE_71 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_EN_CE_IN0,
      I1 => NlwInverterSignal_SHIFT_EN_CE_IN1,
      O => SHIFT_EN_CE
    );
  count_0_Q_72 : X_BUF
    port map (
      I => count_0_Q,
      O => count(0)
    );
  count_0_tsimcreated_set_and_noreset_Q_73 : X_AND2
    port map (
      I0 => NlwInverterSignal_count_0_tsimcreated_set_and_noreset_IN0,
      I1 => count_0_SETF,
      O => count_0_tsimcreated_set_and_noreset_Q
    );
  count_0_tsimcreated_prld_Q_74 : X_OR2
    port map (
      I0 => count_0_RSTF,
      I1 => PRLD,
      O => count_0_tsimcreated_prld_Q
    );
  count_0_REG : X_FF
    port map (
      I => count_0_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => count_0_tsimcreated_set_and_noreset_Q,
      RST => count_0_tsimcreated_prld_Q,
      O => count_0_Q
    );
  count_0_D_75 : X_XOR2
    port map (
      I0 => NlwInverterSignal_count_0_D_IN0,
      I1 => count_0_D2,
      O => count_0_D
    );
  count_0_D1_76 : X_ZERO
    port map (
      O => count_0_D1
    );
  count_0_D2_PT_0_77 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_0_D2_PT_0_IN1,
      O => count_0_D2_PT_0
    );
  count_0_D2_PT_1_78 : X_AND2
    port map (
      I0 => NlwInverterSignal_count_0_D2_PT_1_IN0,
      I1 => count(0),
      O => count_0_D2_PT_1
    );
  count_0_D2_PT_2_79 : X_AND6
    port map (
      I0 => NlwInverterSignal_count_0_D2_PT_2_IN0,
      I1 => NlwInverterSignal_count_0_D2_PT_2_IN1,
      I2 => NlwInverterSignal_count_0_D2_PT_2_IN2,
      I3 => NlwInverterSignal_count_0_D2_PT_2_IN3,
      I4 => NlwInverterSignal_count_0_D2_PT_2_IN4,
      I5 => NlwInverterSignal_count_0_D2_PT_2_IN5,
      O => count_0_D2_PT_2
    );
  count_0_D2_80 : X_OR3
    port map (
      I0 => count_0_D2_PT_0,
      I1 => count_0_D2_PT_1,
      I2 => count_0_D2_PT_2,
      O => count_0_D2
    );
  count_0_SETF_81 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => VCLK_PRESCALE_0_IBUF,
      O => count_0_SETF
    );
  count_0_RSTF_82 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_0_RSTF_IN1,
      O => count_0_RSTF
    );
  count_4_Q_83 : X_BUF
    port map (
      I => count_4_Q,
      O => count(4)
    );
  count_4_EXP_84 : X_BUF
    port map (
      I => count_4_EXP_tsimrenamed_net_Q,
      O => count_4_EXP
    );
  count_4_tsimcreated_xor_Q_85 : X_XOR2
    port map (
      I0 => count_4_D,
      I1 => count_4_Q,
      O => count_4_tsimcreated_xor_Q
    );
  count_4_tsimcreated_set_and_noreset_Q_86 : X_AND2
    port map (
      I0 => NlwInverterSignal_count_4_tsimcreated_set_and_noreset_IN0,
      I1 => count_4_SETF,
      O => count_4_tsimcreated_set_and_noreset_Q
    );
  count_4_tsimcreated_prld_Q_87 : X_OR2
    port map (
      I0 => count_4_RSTF,
      I1 => PRLD,
      O => count_4_tsimcreated_prld_Q
    );
  count_4_REG : X_FF
    port map (
      I => count_4_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => count_4_tsimcreated_set_and_noreset_Q,
      RST => count_4_tsimcreated_prld_Q,
      O => count_4_Q
    );
  count_4_D_88 : X_XOR2
    port map (
      I0 => count_4_D1,
      I1 => count_4_D2,
      O => count_4_D
    );
  count_4_D1_89 : X_ZERO
    port map (
      O => count_4_D1
    );
  count_4_D2_PT_0_90 : X_AND2
    port map (
      I0 => EXP19_EXP,
      I1 => EXP19_EXP,
      O => count_4_D2_PT_0
    );
  count_4_D2_PT_1_91 : X_AND6
    port map (
      I0 => NlwInverterSignal_count_4_D2_PT_1_IN0,
      I1 => NlwInverterSignal_count_4_D2_PT_1_IN1,
      I2 => NlwInverterSignal_count_4_D2_PT_1_IN2,
      I3 => NlwInverterSignal_count_4_D2_PT_1_IN3,
      I4 => NlwInverterSignal_count_4_D2_PT_1_IN4,
      I5 => count(5),
      O => count_4_D2_PT_1
    );
  count_4_D2_PT_2_92 : X_AND6
    port map (
      I0 => NlwInverterSignal_count_4_D2_PT_2_IN0,
      I1 => NlwInverterSignal_count_4_D2_PT_2_IN1,
      I2 => NlwInverterSignal_count_4_D2_PT_2_IN2,
      I3 => NlwInverterSignal_count_4_D2_PT_2_IN3,
      I4 => NlwInverterSignal_count_4_D2_PT_2_IN4,
      I5 => VCLK_PRESCALE_4_IBUF,
      O => count_4_D2_PT_2
    );
  count_4_D2_93 : X_OR3
    port map (
      I0 => count_4_D2_PT_0,
      I1 => count_4_D2_PT_1,
      I2 => count_4_D2_PT_2,
      O => count_4_D2
    );
  count_4_SETF_94 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => VCLK_PRESCALE_4_IBUF,
      O => count_4_SETF
    );
  count_4_RSTF_95 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_4_RSTF_IN1,
      O => count_4_RSTF
    );
  count_4_EXP_tsimrenamed_net_Q_96 : X_AND4
    port map (
      I0 => NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN0,
      I1 => NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN1,
      I2 => NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN2,
      I3 => count(2),
      O => count_4_EXP_tsimrenamed_net_Q
    );
  count_1_Q_97 : X_BUF
    port map (
      I => count_1_Q,
      O => count(1)
    );
  count_1_tsimcreated_set_and_noreset_Q_98 : X_AND2
    port map (
      I0 => NlwInverterSignal_count_1_tsimcreated_set_and_noreset_IN0,
      I1 => count_1_SETF,
      O => count_1_tsimcreated_set_and_noreset_Q
    );
  count_1_tsimcreated_prld_Q_99 : X_OR2
    port map (
      I0 => count_1_RSTF,
      I1 => PRLD,
      O => count_1_tsimcreated_prld_Q
    );
  count_1_REG : X_FF
    port map (
      I => count_1_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => count_1_tsimcreated_set_and_noreset_Q,
      RST => count_1_tsimcreated_prld_Q,
      O => count_1_Q
    );
  count_1_D_100 : X_XOR2
    port map (
      I0 => NlwInverterSignal_count_1_D_IN0,
      I1 => count_1_D2,
      O => count_1_D
    );
  count_1_D1_101 : X_ZERO
    port map (
      O => count_1_D1
    );
  count_1_D2_PT_0_102 : X_AND2
    port map (
      I0 => count_5_EXP,
      I1 => count_5_EXP,
      O => count_1_D2_PT_0
    );
  count_1_D2_PT_1_103 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_1_D2_PT_1_IN1,
      O => count_1_D2_PT_1
    );
  count_1_D2_PT_2_104 : X_AND3
    port map (
      I0 => NlwInverterSignal_count_1_D2_PT_2_IN0,
      I1 => count(0),
      I2 => NlwInverterSignal_count_1_D2_PT_2_IN2,
      O => count_1_D2_PT_2
    );
  count_1_D2_PT_3_105 : X_AND3
    port map (
      I0 => NlwInverterSignal_count_1_D2_PT_3_IN0,
      I1 => NlwInverterSignal_count_1_D2_PT_3_IN1,
      I2 => count(1),
      O => count_1_D2_PT_3
    );
  count_1_D2_106 : X_OR4
    port map (
      I0 => count_1_D2_PT_0,
      I1 => count_1_D2_PT_1,
      I2 => count_1_D2_PT_2,
      I3 => count_1_D2_PT_3,
      O => count_1_D2
    );
  count_1_SETF_107 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => VCLK_PRESCALE_1_IBUF,
      O => count_1_SETF
    );
  count_1_RSTF_108 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_1_RSTF_IN1,
      O => count_1_RSTF
    );
  count_2_Q_109 : X_BUF
    port map (
      I => count_2_Q,
      O => count(2)
    );
  count_2_tsimcreated_set_and_noreset_Q_110 : X_AND2
    port map (
      I0 => NlwInverterSignal_count_2_tsimcreated_set_and_noreset_IN0,
      I1 => count_2_SETF,
      O => count_2_tsimcreated_set_and_noreset_Q
    );
  count_2_tsimcreated_prld_Q_111 : X_OR2
    port map (
      I0 => count_2_RSTF,
      I1 => PRLD,
      O => count_2_tsimcreated_prld_Q
    );
  count_2_REG : X_FF
    port map (
      I => count_2_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => count_2_tsimcreated_set_and_noreset_Q,
      RST => count_2_tsimcreated_prld_Q,
      O => count_2_Q
    );
  count_2_D_112 : X_XOR2
    port map (
      I0 => NlwInverterSignal_count_2_D_IN0,
      I1 => count_2_D2,
      O => count_2_D
    );
  count_2_D1_113 : X_ZERO
    port map (
      O => count_2_D1
    );
  count_2_D2_PT_0_114 : X_AND2
    port map (
      I0 => count_4_EXP,
      I1 => count_4_EXP,
      O => count_2_D2_PT_0
    );
  count_2_D2_PT_1_115 : X_AND2
    port map (
      I0 => count_3_EXP,
      I1 => count_3_EXP,
      O => count_2_D2_PT_1
    );
  count_2_D2_PT_2_116 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_2_D2_PT_2_IN1,
      O => count_2_D2_PT_2
    );
  count_2_D2_PT_3_117 : X_AND3
    port map (
      I0 => NlwInverterSignal_count_2_D2_PT_3_IN0,
      I1 => count(0),
      I2 => NlwInverterSignal_count_2_D2_PT_3_IN2,
      O => count_2_D2_PT_3
    );
  count_2_D2_PT_4_118 : X_AND3
    port map (
      I0 => NlwInverterSignal_count_2_D2_PT_4_IN0,
      I1 => count(1),
      I2 => NlwInverterSignal_count_2_D2_PT_4_IN2,
      O => count_2_D2_PT_4
    );
  count_2_D2_119 : X_OR5
    port map (
      I0 => count_2_D2_PT_0,
      I1 => count_2_D2_PT_1,
      I2 => count_2_D2_PT_2,
      I3 => count_2_D2_PT_3,
      I4 => count_2_D2_PT_4,
      O => count_2_D2
    );
  count_2_SETF_120 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => VCLK_PRESCALE_2_IBUF,
      O => count_2_SETF
    );
  count_2_RSTF_121 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_2_RSTF_IN1,
      O => count_2_RSTF
    );
  count_3_Q_122 : X_BUF
    port map (
      I => count_3_Q,
      O => count(3)
    );
  count_3_EXP_123 : X_BUF
    port map (
      I => count_3_EXP_tsimrenamed_net_Q,
      O => count_3_EXP
    );
  count_3_tsimcreated_set_and_noreset_Q_124 : X_AND2
    port map (
      I0 => NlwInverterSignal_count_3_tsimcreated_set_and_noreset_IN0,
      I1 => count_3_SETF,
      O => count_3_tsimcreated_set_and_noreset_Q
    );
  count_3_tsimcreated_prld_Q_125 : X_OR2
    port map (
      I0 => count_3_RSTF,
      I1 => PRLD,
      O => count_3_tsimcreated_prld_Q
    );
  count_3_REG : X_FF
    port map (
      I => count_3_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => count_3_tsimcreated_set_and_noreset_Q,
      RST => count_3_tsimcreated_prld_Q,
      O => count_3_Q
    );
  count_3_D_126 : X_XOR2
    port map (
      I0 => NlwInverterSignal_count_3_D_IN0,
      I1 => count_3_D2,
      O => count_3_D
    );
  count_3_D1_127 : X_ZERO
    port map (
      O => count_3_D1
    );
  count_3_D2_PT_0_128 : X_AND2
    port map (
      I0 => EXP20_EXP,
      I1 => EXP20_EXP,
      O => count_3_D2_PT_0
    );
  count_3_D2_PT_1_129 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_3_D2_PT_1_IN1,
      O => count_3_D2_PT_1
    );
  count_3_D2_PT_2_130 : X_AND3
    port map (
      I0 => NlwInverterSignal_count_3_D2_PT_2_IN0,
      I1 => count(0),
      I2 => NlwInverterSignal_count_3_D2_PT_2_IN2,
      O => count_3_D2_PT_2
    );
  count_3_D2_131 : X_OR3
    port map (
      I0 => count_3_D2_PT_0,
      I1 => count_3_D2_PT_1,
      I2 => count_3_D2_PT_2,
      O => count_3_D2
    );
  count_3_SETF_132 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => VCLK_PRESCALE_3_IBUF,
      O => count_3_SETF
    );
  count_3_RSTF_133 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_3_RSTF_IN1,
      O => count_3_RSTF
    );
  count_3_EXP_tsimrenamed_net_Q_134 : X_AND5
    port map (
      I0 => NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN0,
      I1 => NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN1,
      I2 => NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN2,
      I3 => NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN3,
      I4 => NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN4,
      O => count_3_EXP_tsimrenamed_net_Q
    );
  REG_0_Q_135 : X_BUF
    port map (
      I => REG_0_Q,
      O => REG(0)
    );
  REG_0_tsimcreated_xor_Q_136 : X_XOR2
    port map (
      I0 => REG_0_D,
      I1 => REG_0_Q,
      O => REG_0_tsimcreated_xor_Q
    );
  REG_0_tsimcreated_set_and_noreset_Q_137 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_SETF,
      O => REG_0_tsimcreated_set_and_noreset_Q
    );
  REG_0_tsimcreated_prld_Q_138 : X_OR2
    port map (
      I0 => REG_0_RSTF,
      I1 => PRLD,
      O => REG_0_tsimcreated_prld_Q
    );
  REG_0_REG : X_FF
    port map (
      I => REG_0_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_CLKF,
      SET => REG_0_tsimcreated_set_and_noreset_Q,
      RST => REG_0_tsimcreated_prld_Q,
      O => REG_0_Q
    );
  REG_0_D_139 : X_XOR2
    port map (
      I0 => REG_0_D1,
      I1 => REG_0_D2,
      O => REG_0_D
    );
  REG_0_D1_140 : X_ZERO
    port map (
      O => REG_0_D1
    );
  REG_0_D2_141 : X_AND5
    port map (
      I0 => NlwInverterSignal_REG_0_D2_IN0,
      I1 => NlwInverterSignal_REG_0_D2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_D2_IN3,
      I4 => REG(0),
      O => REG_0_D2
    );
  REG_0_CLKF_142 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_CLKF_IN1,
      O => REG_0_CLKF
    );
  REG_0_SETF_143 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_0_IBUF,
      O => REG_0_SETF
    );
  REG_0_RSTF_144 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_0_RSTF_IN2,
      O => REG_0_RSTF
    );
  REG_10_Q_145 : X_BUF
    port map (
      I => REG_10_Q,
      O => REG(10)
    );
  REG_10_tsimcreated_xor_Q_146 : X_XOR2
    port map (
      I0 => REG_10_D,
      I1 => REG_10_Q,
      O => REG_10_tsimcreated_xor_Q
    );
  REG_10_tsimcreated_set_and_noreset_Q_147 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_10_tsimcreated_set_and_noreset_IN0,
      I1 => REG_10_SETF,
      O => REG_10_tsimcreated_set_and_noreset_Q
    );
  REG_10_tsimcreated_prld_Q_148 : X_OR2
    port map (
      I0 => REG_10_RSTF,
      I1 => PRLD,
      O => REG_10_tsimcreated_prld_Q
    );
  REG_10_REG : X_FF
    port map (
      I => REG_10_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_10_CLKF,
      SET => REG_10_tsimcreated_set_and_noreset_Q,
      RST => REG_10_tsimcreated_prld_Q,
      O => REG_10_Q
    );
  REG_10_D_149 : X_XOR2
    port map (
      I0 => REG_10_D1,
      I1 => REG_10_D2,
      O => REG_10_D
    );
  REG_10_D1_150 : X_ZERO
    port map (
      O => REG_10_D1
    );
  REG_10_D2_PT_0_151 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_10_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_10_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_10_D2_PT_0_IN3,
      I4 => REG(10),
      I5 => NlwInverterSignal_REG_10_D2_PT_0_IN5,
      O => REG_10_D2_PT_0
    );
  REG_10_D2_PT_1_152 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_10_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_10_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_10_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_10_D2_PT_1_IN4,
      I5 => REG(9),
      O => REG_10_D2_PT_1
    );
  REG_10_D2_153 : X_OR2
    port map (
      I0 => REG_10_D2_PT_0,
      I1 => REG_10_D2_PT_1,
      O => REG_10_D2
    );
  REG_10_CLKF_154 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_10_CLKF_IN0,
      I1 => NlwInverterSignal_REG_10_CLKF_IN1,
      O => REG_10_CLKF
    );
  REG_10_SETF_155 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_10_IBUF,
      O => REG_10_SETF
    );
  REG_10_RSTF_156 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_10_RSTF_IN2,
      O => REG_10_RSTF
    );
  REG_11_Q_157 : X_BUF
    port map (
      I => REG_11_Q,
      O => REG(11)
    );
  REG_11_tsimcreated_xor_Q_158 : X_XOR2
    port map (
      I0 => REG_11_D,
      I1 => REG_11_Q,
      O => REG_11_tsimcreated_xor_Q
    );
  REG_11_tsimcreated_set_and_noreset_Q_159 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_11_tsimcreated_set_and_noreset_IN0,
      I1 => REG_11_SETF,
      O => REG_11_tsimcreated_set_and_noreset_Q
    );
  REG_11_tsimcreated_prld_Q_160 : X_OR2
    port map (
      I0 => REG_11_RSTF,
      I1 => PRLD,
      O => REG_11_tsimcreated_prld_Q
    );
  REG_11_REG : X_FF
    port map (
      I => REG_11_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_11_CLKF,
      SET => REG_11_tsimcreated_set_and_noreset_Q,
      RST => REG_11_tsimcreated_prld_Q,
      O => REG_11_Q
    );
  REG_11_D_161 : X_XOR2
    port map (
      I0 => REG_11_D1,
      I1 => REG_11_D2,
      O => REG_11_D
    );
  REG_11_D1_162 : X_ZERO
    port map (
      O => REG_11_D1
    );
  REG_11_D2_PT_0_163 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_11_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_11_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_11_D2_PT_0_IN3,
      I4 => REG(10),
      I5 => NlwInverterSignal_REG_11_D2_PT_0_IN5,
      O => REG_11_D2_PT_0
    );
  REG_11_D2_PT_1_164 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_11_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_11_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_11_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_11_D2_PT_1_IN4,
      I5 => REG(11),
      O => REG_11_D2_PT_1
    );
  REG_11_D2_165 : X_OR2
    port map (
      I0 => REG_11_D2_PT_0,
      I1 => REG_11_D2_PT_1,
      O => REG_11_D2
    );
  REG_11_CLKF_166 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_11_CLKF_IN0,
      I1 => NlwInverterSignal_REG_11_CLKF_IN1,
      O => REG_11_CLKF
    );
  REG_11_SETF_167 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_11_IBUF,
      O => REG_11_SETF
    );
  REG_11_RSTF_168 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_11_RSTF_IN2,
      O => REG_11_RSTF
    );
  REG_12_Q_169 : X_BUF
    port map (
      I => REG_12_Q,
      O => REG(12)
    );
  REG_12_tsimcreated_xor_Q_170 : X_XOR2
    port map (
      I0 => REG_12_D,
      I1 => REG_12_Q,
      O => REG_12_tsimcreated_xor_Q
    );
  REG_12_tsimcreated_set_and_noreset_Q_171 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_12_tsimcreated_set_and_noreset_IN0,
      I1 => REG_12_SETF,
      O => REG_12_tsimcreated_set_and_noreset_Q
    );
  REG_12_tsimcreated_prld_Q_172 : X_OR2
    port map (
      I0 => REG_12_RSTF,
      I1 => PRLD,
      O => REG_12_tsimcreated_prld_Q
    );
  REG_12_REG : X_FF
    port map (
      I => REG_12_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_12_CLKF,
      SET => REG_12_tsimcreated_set_and_noreset_Q,
      RST => REG_12_tsimcreated_prld_Q,
      O => REG_12_Q
    );
  REG_12_D_173 : X_XOR2
    port map (
      I0 => REG_12_D1,
      I1 => REG_12_D2,
      O => REG_12_D
    );
  REG_12_D1_174 : X_ZERO
    port map (
      O => REG_12_D1
    );
  REG_12_D2_PT_0_175 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_12_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_12_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_12_D2_PT_0_IN3,
      I4 => REG(11),
      I5 => NlwInverterSignal_REG_12_D2_PT_0_IN5,
      O => REG_12_D2_PT_0
    );
  REG_12_D2_PT_1_176 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_12_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_12_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_12_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_12_D2_PT_1_IN4,
      I5 => REG(12),
      O => REG_12_D2_PT_1
    );
  REG_12_D2_177 : X_OR2
    port map (
      I0 => REG_12_D2_PT_0,
      I1 => REG_12_D2_PT_1,
      O => REG_12_D2
    );
  REG_12_CLKF_178 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_12_CLKF_IN0,
      I1 => NlwInverterSignal_REG_12_CLKF_IN1,
      O => REG_12_CLKF
    );
  REG_12_SETF_179 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_12_IBUF,
      O => REG_12_SETF
    );
  REG_12_RSTF_180 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_12_RSTF_IN2,
      O => REG_12_RSTF
    );
  REG_13_Q_181 : X_BUF
    port map (
      I => REG_13_Q,
      O => REG(13)
    );
  REG_13_tsimcreated_xor_Q_182 : X_XOR2
    port map (
      I0 => REG_13_D,
      I1 => REG_13_Q,
      O => REG_13_tsimcreated_xor_Q
    );
  REG_13_tsimcreated_set_and_noreset_Q_183 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_13_tsimcreated_set_and_noreset_IN0,
      I1 => REG_13_SETF,
      O => REG_13_tsimcreated_set_and_noreset_Q
    );
  REG_13_tsimcreated_prld_Q_184 : X_OR2
    port map (
      I0 => REG_13_RSTF,
      I1 => PRLD,
      O => REG_13_tsimcreated_prld_Q
    );
  REG_13_REG : X_FF
    port map (
      I => REG_13_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_13_CLKF,
      SET => REG_13_tsimcreated_set_and_noreset_Q,
      RST => REG_13_tsimcreated_prld_Q,
      O => REG_13_Q
    );
  REG_13_D_185 : X_XOR2
    port map (
      I0 => REG_13_D1,
      I1 => REG_13_D2,
      O => REG_13_D
    );
  REG_13_D1_186 : X_ZERO
    port map (
      O => REG_13_D1
    );
  REG_13_D2_PT_0_187 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_13_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_13_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_13_D2_PT_0_IN3,
      I4 => REG(12),
      I5 => NlwInverterSignal_REG_13_D2_PT_0_IN5,
      O => REG_13_D2_PT_0
    );
  REG_13_D2_PT_1_188 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_13_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_13_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_13_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_13_D2_PT_1_IN4,
      I5 => REG(13),
      O => REG_13_D2_PT_1
    );
  REG_13_D2_189 : X_OR2
    port map (
      I0 => REG_13_D2_PT_0,
      I1 => REG_13_D2_PT_1,
      O => REG_13_D2
    );
  REG_13_CLKF_190 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_13_CLKF_IN0,
      I1 => NlwInverterSignal_REG_13_CLKF_IN1,
      O => REG_13_CLKF
    );
  REG_13_SETF_191 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_13_IBUF,
      O => REG_13_SETF
    );
  REG_13_RSTF_192 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_13_RSTF_IN2,
      O => REG_13_RSTF
    );
  REG_14_Q_193 : X_BUF
    port map (
      I => REG_14_Q,
      O => REG(14)
    );
  REG_14_tsimcreated_xor_Q_194 : X_XOR2
    port map (
      I0 => REG_14_D,
      I1 => REG_14_Q,
      O => REG_14_tsimcreated_xor_Q
    );
  REG_14_tsimcreated_set_and_noreset_Q_195 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_14_tsimcreated_set_and_noreset_IN0,
      I1 => REG_14_SETF,
      O => REG_14_tsimcreated_set_and_noreset_Q
    );
  REG_14_tsimcreated_prld_Q_196 : X_OR2
    port map (
      I0 => REG_14_RSTF,
      I1 => PRLD,
      O => REG_14_tsimcreated_prld_Q
    );
  REG_14_REG : X_FF
    port map (
      I => REG_14_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_14_CLKF,
      SET => REG_14_tsimcreated_set_and_noreset_Q,
      RST => REG_14_tsimcreated_prld_Q,
      O => REG_14_Q
    );
  REG_14_D_197 : X_XOR2
    port map (
      I0 => REG_14_D1,
      I1 => REG_14_D2,
      O => REG_14_D
    );
  REG_14_D1_198 : X_ZERO
    port map (
      O => REG_14_D1
    );
  REG_14_D2_PT_0_199 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_14_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_14_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_14_D2_PT_0_IN3,
      I4 => REG(13),
      I5 => NlwInverterSignal_REG_14_D2_PT_0_IN5,
      O => REG_14_D2_PT_0
    );
  REG_14_D2_PT_1_200 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_14_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_14_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_14_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_14_D2_PT_1_IN4,
      I5 => REG(14),
      O => REG_14_D2_PT_1
    );
  REG_14_D2_201 : X_OR2
    port map (
      I0 => REG_14_D2_PT_0,
      I1 => REG_14_D2_PT_1,
      O => REG_14_D2
    );
  REG_14_CLKF_202 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_14_CLKF_IN0,
      I1 => NlwInverterSignal_REG_14_CLKF_IN1,
      O => REG_14_CLKF
    );
  REG_14_SETF_203 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_14_IBUF,
      O => REG_14_SETF
    );
  REG_14_RSTF_204 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_14_RSTF_IN2,
      O => REG_14_RSTF
    );
  REG_15_Q_205 : X_BUF
    port map (
      I => REG_15_Q,
      O => REG(15)
    );
  REG_15_tsimcreated_xor_Q_206 : X_XOR2
    port map (
      I0 => REG_15_D,
      I1 => REG_15_Q,
      O => REG_15_tsimcreated_xor_Q
    );
  REG_15_tsimcreated_set_and_noreset_Q_207 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_15_tsimcreated_set_and_noreset_IN0,
      I1 => REG_15_SETF,
      O => REG_15_tsimcreated_set_and_noreset_Q
    );
  REG_15_tsimcreated_prld_Q_208 : X_OR2
    port map (
      I0 => REG_15_RSTF,
      I1 => PRLD,
      O => REG_15_tsimcreated_prld_Q
    );
  REG_15_REG : X_FF
    port map (
      I => REG_15_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_15_CLKF,
      SET => REG_15_tsimcreated_set_and_noreset_Q,
      RST => REG_15_tsimcreated_prld_Q,
      O => REG_15_Q
    );
  REG_15_D_209 : X_XOR2
    port map (
      I0 => REG_15_D1,
      I1 => REG_15_D2,
      O => REG_15_D
    );
  REG_15_D1_210 : X_ZERO
    port map (
      O => REG_15_D1
    );
  REG_15_D2_PT_0_211 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_15_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_15_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_15_D2_PT_0_IN3,
      I4 => REG(14),
      I5 => NlwInverterSignal_REG_15_D2_PT_0_IN5,
      O => REG_15_D2_PT_0
    );
  REG_15_D2_PT_1_212 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_15_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_15_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_15_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_15_D2_PT_1_IN4,
      I5 => REG(15),
      O => REG_15_D2_PT_1
    );
  REG_15_D2_213 : X_OR2
    port map (
      I0 => REG_15_D2_PT_0,
      I1 => REG_15_D2_PT_1,
      O => REG_15_D2
    );
  REG_15_CLKF_214 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_15_CLKF_IN0,
      I1 => NlwInverterSignal_REG_15_CLKF_IN1,
      O => REG_15_CLKF
    );
  REG_15_SETF_215 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_15_IBUF,
      O => REG_15_SETF
    );
  REG_15_RSTF_216 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_15_RSTF_IN2,
      O => REG_15_RSTF
    );
  REG_16_Q_217 : X_BUF
    port map (
      I => REG_16_Q,
      O => REG(16)
    );
  REG_16_tsimcreated_xor_Q_218 : X_XOR2
    port map (
      I0 => REG_16_D,
      I1 => REG_16_Q,
      O => REG_16_tsimcreated_xor_Q
    );
  REG_16_tsimcreated_set_and_noreset_Q_219 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_16_tsimcreated_set_and_noreset_IN0,
      I1 => REG_16_SETF,
      O => REG_16_tsimcreated_set_and_noreset_Q
    );
  REG_16_tsimcreated_prld_Q_220 : X_OR2
    port map (
      I0 => REG_16_RSTF,
      I1 => PRLD,
      O => REG_16_tsimcreated_prld_Q
    );
  REG_16_REG : X_FF
    port map (
      I => REG_16_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_16_CLKF,
      SET => REG_16_tsimcreated_set_and_noreset_Q,
      RST => REG_16_tsimcreated_prld_Q,
      O => REG_16_Q
    );
  REG_16_D_221 : X_XOR2
    port map (
      I0 => REG_16_D1,
      I1 => REG_16_D2,
      O => REG_16_D
    );
  REG_16_D1_222 : X_ZERO
    port map (
      O => REG_16_D1
    );
  REG_16_D2_PT_0_223 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_16_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_16_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_16_D2_PT_0_IN3,
      I4 => REG(15),
      I5 => NlwInverterSignal_REG_16_D2_PT_0_IN5,
      O => REG_16_D2_PT_0
    );
  REG_16_D2_PT_1_224 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_16_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_16_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_16_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_16_D2_PT_1_IN4,
      I5 => REG(16),
      O => REG_16_D2_PT_1
    );
  REG_16_D2_225 : X_OR2
    port map (
      I0 => REG_16_D2_PT_0,
      I1 => REG_16_D2_PT_1,
      O => REG_16_D2
    );
  REG_16_CLKF_226 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_16_CLKF_IN0,
      I1 => NlwInverterSignal_REG_16_CLKF_IN1,
      O => REG_16_CLKF
    );
  REG_16_SETF_227 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_16_IBUF,
      O => REG_16_SETF
    );
  REG_16_RSTF_228 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_16_RSTF_IN2,
      O => REG_16_RSTF
    );
  REG_17_Q_229 : X_BUF
    port map (
      I => REG_17_Q,
      O => REG(17)
    );
  REG_17_tsimcreated_xor_Q_230 : X_XOR2
    port map (
      I0 => REG_17_D,
      I1 => REG_17_Q,
      O => REG_17_tsimcreated_xor_Q
    );
  REG_17_tsimcreated_set_and_noreset_Q_231 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_17_tsimcreated_set_and_noreset_IN0,
      I1 => REG_17_SETF,
      O => REG_17_tsimcreated_set_and_noreset_Q
    );
  REG_17_tsimcreated_prld_Q_232 : X_OR2
    port map (
      I0 => REG_17_RSTF,
      I1 => PRLD,
      O => REG_17_tsimcreated_prld_Q
    );
  REG_17_REG : X_FF
    port map (
      I => REG_17_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_17_CLKF,
      SET => REG_17_tsimcreated_set_and_noreset_Q,
      RST => REG_17_tsimcreated_prld_Q,
      O => REG_17_Q
    );
  REG_17_D_233 : X_XOR2
    port map (
      I0 => REG_17_D1,
      I1 => REG_17_D2,
      O => REG_17_D
    );
  REG_17_D1_234 : X_ZERO
    port map (
      O => REG_17_D1
    );
  REG_17_D2_PT_0_235 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_17_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_17_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_17_D2_PT_0_IN3,
      I4 => REG(16),
      I5 => NlwInverterSignal_REG_17_D2_PT_0_IN5,
      O => REG_17_D2_PT_0
    );
  REG_17_D2_PT_1_236 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_17_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_17_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_17_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_17_D2_PT_1_IN4,
      I5 => REG(17),
      O => REG_17_D2_PT_1
    );
  REG_17_D2_237 : X_OR2
    port map (
      I0 => REG_17_D2_PT_0,
      I1 => REG_17_D2_PT_1,
      O => REG_17_D2
    );
  REG_17_CLKF_238 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_17_CLKF_IN0,
      I1 => NlwInverterSignal_REG_17_CLKF_IN1,
      O => REG_17_CLKF
    );
  REG_17_SETF_239 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_17_IBUF,
      O => REG_17_SETF
    );
  REG_17_RSTF_240 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_17_RSTF_IN2,
      O => REG_17_RSTF
    );
  REG_18_Q_241 : X_BUF
    port map (
      I => REG_18_Q,
      O => REG(18)
    );
  REG_18_tsimcreated_xor_Q_242 : X_XOR2
    port map (
      I0 => REG_18_D,
      I1 => REG_18_Q,
      O => REG_18_tsimcreated_xor_Q
    );
  REG_18_tsimcreated_set_and_noreset_Q_243 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_18_tsimcreated_set_and_noreset_IN0,
      I1 => REG_18_SETF,
      O => REG_18_tsimcreated_set_and_noreset_Q
    );
  REG_18_tsimcreated_prld_Q_244 : X_OR2
    port map (
      I0 => REG_18_RSTF,
      I1 => PRLD,
      O => REG_18_tsimcreated_prld_Q
    );
  REG_18_REG : X_FF
    port map (
      I => REG_18_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_18_CLKF,
      SET => REG_18_tsimcreated_set_and_noreset_Q,
      RST => REG_18_tsimcreated_prld_Q,
      O => REG_18_Q
    );
  REG_18_D_245 : X_XOR2
    port map (
      I0 => REG_18_D1,
      I1 => REG_18_D2,
      O => REG_18_D
    );
  REG_18_D1_246 : X_ZERO
    port map (
      O => REG_18_D1
    );
  REG_18_D2_PT_0_247 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_18_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_18_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_18_D2_PT_0_IN3,
      I4 => REG(17),
      I5 => NlwInverterSignal_REG_18_D2_PT_0_IN5,
      O => REG_18_D2_PT_0
    );
  REG_18_D2_PT_1_248 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_18_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_18_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_18_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_18_D2_PT_1_IN4,
      I5 => REG(18),
      O => REG_18_D2_PT_1
    );
  REG_18_D2_249 : X_OR2
    port map (
      I0 => REG_18_D2_PT_0,
      I1 => REG_18_D2_PT_1,
      O => REG_18_D2
    );
  REG_18_CLKF_250 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_18_CLKF_IN0,
      I1 => NlwInverterSignal_REG_18_CLKF_IN1,
      O => REG_18_CLKF
    );
  REG_18_SETF_251 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_18_IBUF,
      O => REG_18_SETF
    );
  REG_18_RSTF_252 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_18_RSTF_IN2,
      O => REG_18_RSTF
    );
  REG_19_Q_253 : X_BUF
    port map (
      I => REG_19_Q,
      O => REG(19)
    );
  REG_19_tsimcreated_xor_Q_254 : X_XOR2
    port map (
      I0 => REG_19_D,
      I1 => REG_19_Q,
      O => REG_19_tsimcreated_xor_Q
    );
  REG_19_tsimcreated_set_and_noreset_Q_255 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_19_tsimcreated_set_and_noreset_IN0,
      I1 => REG_19_SETF,
      O => REG_19_tsimcreated_set_and_noreset_Q
    );
  REG_19_tsimcreated_prld_Q_256 : X_OR2
    port map (
      I0 => REG_19_RSTF,
      I1 => PRLD,
      O => REG_19_tsimcreated_prld_Q
    );
  REG_19_REG : X_FF
    port map (
      I => REG_19_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_19_CLKF,
      SET => REG_19_tsimcreated_set_and_noreset_Q,
      RST => REG_19_tsimcreated_prld_Q,
      O => REG_19_Q
    );
  REG_19_D_257 : X_XOR2
    port map (
      I0 => REG_19_D1,
      I1 => REG_19_D2,
      O => REG_19_D
    );
  REG_19_D1_258 : X_ZERO
    port map (
      O => REG_19_D1
    );
  REG_19_D2_PT_0_259 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_19_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_19_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_19_D2_PT_0_IN3,
      I4 => REG(18),
      I5 => NlwInverterSignal_REG_19_D2_PT_0_IN5,
      O => REG_19_D2_PT_0
    );
  REG_19_D2_PT_1_260 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_19_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_19_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_19_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_19_D2_PT_1_IN4,
      I5 => REG(19),
      O => REG_19_D2_PT_1
    );
  REG_19_D2_261 : X_OR2
    port map (
      I0 => REG_19_D2_PT_0,
      I1 => REG_19_D2_PT_1,
      O => REG_19_D2
    );
  REG_19_CLKF_262 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_19_CLKF_IN0,
      I1 => NlwInverterSignal_REG_19_CLKF_IN1,
      O => REG_19_CLKF
    );
  REG_19_SETF_263 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_19_IBUF,
      O => REG_19_SETF
    );
  REG_19_RSTF_264 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_19_RSTF_IN2,
      O => REG_19_RSTF
    );
  REG_1_Q_265 : X_BUF
    port map (
      I => REG_1_Q,
      O => REG(1)
    );
  REG_1_tsimcreated_xor_Q_266 : X_XOR2
    port map (
      I0 => REG_1_D,
      I1 => REG_1_Q,
      O => REG_1_tsimcreated_xor_Q
    );
  REG_1_tsimcreated_set_and_noreset_Q_267 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_SETF,
      O => REG_1_tsimcreated_set_and_noreset_Q
    );
  REG_1_tsimcreated_prld_Q_268 : X_OR2
    port map (
      I0 => REG_1_RSTF,
      I1 => PRLD,
      O => REG_1_tsimcreated_prld_Q
    );
  REG_1_REG : X_FF
    port map (
      I => REG_1_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_CLKF,
      SET => REG_1_tsimcreated_set_and_noreset_Q,
      RST => REG_1_tsimcreated_prld_Q,
      O => REG_1_Q
    );
  REG_1_D_269 : X_XOR2
    port map (
      I0 => REG_1_D1,
      I1 => REG_1_D2,
      O => REG_1_D
    );
  REG_1_D1_270 : X_ZERO
    port map (
      O => REG_1_D1
    );
  REG_1_D2_PT_0_271 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_1_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_1_D2_PT_0_IN3,
      I4 => REG(0),
      I5 => NlwInverterSignal_REG_1_D2_PT_0_IN5,
      O => REG_1_D2_PT_0
    );
  REG_1_D2_PT_1_272 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_1_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_1_D2_PT_1_IN4,
      I5 => REG(1),
      O => REG_1_D2_PT_1
    );
  REG_1_D2_273 : X_OR2
    port map (
      I0 => REG_1_D2_PT_0,
      I1 => REG_1_D2_PT_1,
      O => REG_1_D2
    );
  REG_1_CLKF_274 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_CLKF_IN1,
      O => REG_1_CLKF
    );
  REG_1_SETF_275 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_1_IBUF,
      O => REG_1_SETF
    );
  REG_1_RSTF_276 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_1_RSTF_IN2,
      O => REG_1_RSTF
    );
  REG_20_Q_277 : X_BUF
    port map (
      I => REG_20_Q,
      O => REG(20)
    );
  REG_20_tsimcreated_xor_Q_278 : X_XOR2
    port map (
      I0 => REG_20_D,
      I1 => REG_20_Q,
      O => REG_20_tsimcreated_xor_Q
    );
  REG_20_tsimcreated_set_and_noreset_Q_279 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_20_tsimcreated_set_and_noreset_IN0,
      I1 => REG_20_SETF,
      O => REG_20_tsimcreated_set_and_noreset_Q
    );
  REG_20_tsimcreated_prld_Q_280 : X_OR2
    port map (
      I0 => REG_20_RSTF,
      I1 => PRLD,
      O => REG_20_tsimcreated_prld_Q
    );
  REG_20_REG : X_FF
    port map (
      I => REG_20_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_20_CLKF,
      SET => REG_20_tsimcreated_set_and_noreset_Q,
      RST => REG_20_tsimcreated_prld_Q,
      O => REG_20_Q
    );
  REG_20_D_281 : X_XOR2
    port map (
      I0 => REG_20_D1,
      I1 => REG_20_D2,
      O => REG_20_D
    );
  REG_20_D1_282 : X_ZERO
    port map (
      O => REG_20_D1
    );
  REG_20_D2_PT_0_283 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_20_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_20_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_20_D2_PT_0_IN3,
      I4 => REG(19),
      I5 => NlwInverterSignal_REG_20_D2_PT_0_IN5,
      O => REG_20_D2_PT_0
    );
  REG_20_D2_PT_1_284 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_20_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_20_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_20_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_20_D2_PT_1_IN4,
      I5 => REG(20),
      O => REG_20_D2_PT_1
    );
  REG_20_D2_285 : X_OR2
    port map (
      I0 => REG_20_D2_PT_0,
      I1 => REG_20_D2_PT_1,
      O => REG_20_D2
    );
  REG_20_CLKF_286 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_20_CLKF_IN0,
      I1 => NlwInverterSignal_REG_20_CLKF_IN1,
      O => REG_20_CLKF
    );
  REG_20_SETF_287 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_20_IBUF,
      O => REG_20_SETF
    );
  REG_20_RSTF_288 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_20_RSTF_IN2,
      O => REG_20_RSTF
    );
  REG_21_Q_289 : X_BUF
    port map (
      I => REG_21_Q,
      O => REG(21)
    );
  REG_21_tsimcreated_xor_Q_290 : X_XOR2
    port map (
      I0 => REG_21_D,
      I1 => REG_21_Q,
      O => REG_21_tsimcreated_xor_Q
    );
  REG_21_tsimcreated_set_and_noreset_Q_291 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_21_tsimcreated_set_and_noreset_IN0,
      I1 => REG_21_SETF,
      O => REG_21_tsimcreated_set_and_noreset_Q
    );
  REG_21_tsimcreated_prld_Q_292 : X_OR2
    port map (
      I0 => REG_21_RSTF,
      I1 => PRLD,
      O => REG_21_tsimcreated_prld_Q
    );
  REG_21_REG : X_FF
    port map (
      I => REG_21_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_21_CLKF,
      SET => REG_21_tsimcreated_set_and_noreset_Q,
      RST => REG_21_tsimcreated_prld_Q,
      O => REG_21_Q
    );
  REG_21_D_293 : X_XOR2
    port map (
      I0 => REG_21_D1,
      I1 => REG_21_D2,
      O => REG_21_D
    );
  REG_21_D1_294 : X_ZERO
    port map (
      O => REG_21_D1
    );
  REG_21_D2_PT_0_295 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_21_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_21_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_21_D2_PT_0_IN3,
      I4 => REG(20),
      I5 => NlwInverterSignal_REG_21_D2_PT_0_IN5,
      O => REG_21_D2_PT_0
    );
  REG_21_D2_PT_1_296 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_21_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_21_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_21_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_21_D2_PT_1_IN4,
      I5 => REG(21),
      O => REG_21_D2_PT_1
    );
  REG_21_D2_297 : X_OR2
    port map (
      I0 => REG_21_D2_PT_0,
      I1 => REG_21_D2_PT_1,
      O => REG_21_D2
    );
  REG_21_CLKF_298 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_21_CLKF_IN0,
      I1 => NlwInverterSignal_REG_21_CLKF_IN1,
      O => REG_21_CLKF
    );
  REG_21_SETF_299 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_21_IBUF,
      O => REG_21_SETF
    );
  REG_21_RSTF_300 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_21_RSTF_IN2,
      O => REG_21_RSTF
    );
  REG_22_Q_301 : X_BUF
    port map (
      I => REG_22_Q,
      O => REG(22)
    );
  REG_22_tsimcreated_xor_Q_302 : X_XOR2
    port map (
      I0 => REG_22_D,
      I1 => REG_22_Q,
      O => REG_22_tsimcreated_xor_Q
    );
  REG_22_tsimcreated_set_and_noreset_Q_303 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_22_tsimcreated_set_and_noreset_IN0,
      I1 => REG_22_SETF,
      O => REG_22_tsimcreated_set_and_noreset_Q
    );
  REG_22_tsimcreated_prld_Q_304 : X_OR2
    port map (
      I0 => REG_22_RSTF,
      I1 => PRLD,
      O => REG_22_tsimcreated_prld_Q
    );
  REG_22_REG : X_FF
    port map (
      I => REG_22_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_22_CLKF,
      SET => REG_22_tsimcreated_set_and_noreset_Q,
      RST => REG_22_tsimcreated_prld_Q,
      O => REG_22_Q
    );
  REG_22_D_305 : X_XOR2
    port map (
      I0 => REG_22_D1,
      I1 => REG_22_D2,
      O => REG_22_D
    );
  REG_22_D1_306 : X_ZERO
    port map (
      O => REG_22_D1
    );
  REG_22_D2_PT_0_307 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_22_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_22_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_22_D2_PT_0_IN3,
      I4 => REG(21),
      I5 => NlwInverterSignal_REG_22_D2_PT_0_IN5,
      O => REG_22_D2_PT_0
    );
  REG_22_D2_PT_1_308 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_22_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_22_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_22_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_22_D2_PT_1_IN4,
      I5 => REG(22),
      O => REG_22_D2_PT_1
    );
  REG_22_D2_309 : X_OR2
    port map (
      I0 => REG_22_D2_PT_0,
      I1 => REG_22_D2_PT_1,
      O => REG_22_D2
    );
  REG_22_CLKF_310 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_22_CLKF_IN0,
      I1 => NlwInverterSignal_REG_22_CLKF_IN1,
      O => REG_22_CLKF
    );
  REG_22_SETF_311 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_22_IBUF,
      O => REG_22_SETF
    );
  REG_22_RSTF_312 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_22_RSTF_IN2,
      O => REG_22_RSTF
    );
  REG_23_Q_313 : X_BUF
    port map (
      I => REG_23_Q,
      O => REG(23)
    );
  REG_23_tsimcreated_xor_Q_314 : X_XOR2
    port map (
      I0 => REG_23_D,
      I1 => REG_23_Q,
      O => REG_23_tsimcreated_xor_Q
    );
  REG_23_tsimcreated_set_and_noreset_Q_315 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_23_tsimcreated_set_and_noreset_IN0,
      I1 => REG_23_SETF,
      O => REG_23_tsimcreated_set_and_noreset_Q
    );
  REG_23_tsimcreated_prld_Q_316 : X_OR2
    port map (
      I0 => REG_23_RSTF,
      I1 => PRLD,
      O => REG_23_tsimcreated_prld_Q
    );
  REG_23_REG : X_FF
    port map (
      I => REG_23_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_23_CLKF,
      SET => REG_23_tsimcreated_set_and_noreset_Q,
      RST => REG_23_tsimcreated_prld_Q,
      O => REG_23_Q
    );
  REG_23_D_317 : X_XOR2
    port map (
      I0 => REG_23_D1,
      I1 => REG_23_D2,
      O => REG_23_D
    );
  REG_23_D1_318 : X_ZERO
    port map (
      O => REG_23_D1
    );
  REG_23_D2_PT_0_319 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_23_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_23_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_23_D2_PT_0_IN3,
      I4 => REG(22),
      I5 => NlwInverterSignal_REG_23_D2_PT_0_IN5,
      O => REG_23_D2_PT_0
    );
  REG_23_D2_PT_1_320 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_23_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_23_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_23_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_23_D2_PT_1_IN4,
      I5 => REG(23),
      O => REG_23_D2_PT_1
    );
  REG_23_D2_321 : X_OR2
    port map (
      I0 => REG_23_D2_PT_0,
      I1 => REG_23_D2_PT_1,
      O => REG_23_D2
    );
  REG_23_CLKF_322 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_23_CLKF_IN0,
      I1 => NlwInverterSignal_REG_23_CLKF_IN1,
      O => REG_23_CLKF
    );
  REG_23_SETF_323 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_23_IBUF,
      O => REG_23_SETF
    );
  REG_23_RSTF_324 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_23_RSTF_IN2,
      O => REG_23_RSTF
    );
  REG_24_Q_325 : X_BUF
    port map (
      I => REG_24_Q,
      O => REG(24)
    );
  REG_24_tsimcreated_xor_Q_326 : X_XOR2
    port map (
      I0 => REG_24_D,
      I1 => REG_24_Q,
      O => REG_24_tsimcreated_xor_Q
    );
  REG_24_tsimcreated_set_and_noreset_Q_327 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_24_tsimcreated_set_and_noreset_IN0,
      I1 => REG_24_SETF,
      O => REG_24_tsimcreated_set_and_noreset_Q
    );
  REG_24_tsimcreated_prld_Q_328 : X_OR2
    port map (
      I0 => REG_24_RSTF,
      I1 => PRLD,
      O => REG_24_tsimcreated_prld_Q
    );
  REG_24_REG : X_FF
    port map (
      I => REG_24_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_24_CLKF,
      SET => REG_24_tsimcreated_set_and_noreset_Q,
      RST => REG_24_tsimcreated_prld_Q,
      O => REG_24_Q
    );
  REG_24_D_329 : X_XOR2
    port map (
      I0 => REG_24_D1,
      I1 => REG_24_D2,
      O => REG_24_D
    );
  REG_24_D1_330 : X_ZERO
    port map (
      O => REG_24_D1
    );
  REG_24_D2_PT_0_331 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_24_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_24_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_24_D2_PT_0_IN3,
      I4 => REG(23),
      I5 => NlwInverterSignal_REG_24_D2_PT_0_IN5,
      O => REG_24_D2_PT_0
    );
  REG_24_D2_PT_1_332 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_24_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_24_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_24_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_24_D2_PT_1_IN4,
      I5 => REG(24),
      O => REG_24_D2_PT_1
    );
  REG_24_D2_333 : X_OR2
    port map (
      I0 => REG_24_D2_PT_0,
      I1 => REG_24_D2_PT_1,
      O => REG_24_D2
    );
  REG_24_CLKF_334 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_24_CLKF_IN0,
      I1 => NlwInverterSignal_REG_24_CLKF_IN1,
      O => REG_24_CLKF
    );
  REG_24_SETF_335 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_24_IBUF,
      O => REG_24_SETF
    );
  REG_24_RSTF_336 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_24_RSTF_IN2,
      O => REG_24_RSTF
    );
  REG_25_Q_337 : X_BUF
    port map (
      I => REG_25_Q,
      O => REG(25)
    );
  REG_25_tsimcreated_xor_Q_338 : X_XOR2
    port map (
      I0 => REG_25_D,
      I1 => REG_25_Q,
      O => REG_25_tsimcreated_xor_Q
    );
  REG_25_tsimcreated_set_and_noreset_Q_339 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_25_tsimcreated_set_and_noreset_IN0,
      I1 => REG_25_SETF,
      O => REG_25_tsimcreated_set_and_noreset_Q
    );
  REG_25_tsimcreated_prld_Q_340 : X_OR2
    port map (
      I0 => REG_25_RSTF,
      I1 => PRLD,
      O => REG_25_tsimcreated_prld_Q
    );
  REG_25_REG : X_FF
    port map (
      I => REG_25_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_25_CLKF,
      SET => REG_25_tsimcreated_set_and_noreset_Q,
      RST => REG_25_tsimcreated_prld_Q,
      O => REG_25_Q
    );
  REG_25_D_341 : X_XOR2
    port map (
      I0 => REG_25_D1,
      I1 => REG_25_D2,
      O => REG_25_D
    );
  REG_25_D1_342 : X_ZERO
    port map (
      O => REG_25_D1
    );
  REG_25_D2_PT_0_343 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_25_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_25_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_25_D2_PT_0_IN3,
      I4 => REG(24),
      I5 => NlwInverterSignal_REG_25_D2_PT_0_IN5,
      O => REG_25_D2_PT_0
    );
  REG_25_D2_PT_1_344 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_25_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_25_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_25_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_25_D2_PT_1_IN4,
      I5 => REG(25),
      O => REG_25_D2_PT_1
    );
  REG_25_D2_345 : X_OR2
    port map (
      I0 => REG_25_D2_PT_0,
      I1 => REG_25_D2_PT_1,
      O => REG_25_D2
    );
  REG_25_CLKF_346 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_25_CLKF_IN0,
      I1 => NlwInverterSignal_REG_25_CLKF_IN1,
      O => REG_25_CLKF
    );
  REG_25_SETF_347 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_25_IBUF,
      O => REG_25_SETF
    );
  REG_25_RSTF_348 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_25_RSTF_IN2,
      O => REG_25_RSTF
    );
  REG_26_Q_349 : X_BUF
    port map (
      I => REG_26_Q,
      O => REG(26)
    );
  REG_26_tsimcreated_xor_Q_350 : X_XOR2
    port map (
      I0 => REG_26_D,
      I1 => REG_26_Q,
      O => REG_26_tsimcreated_xor_Q
    );
  REG_26_tsimcreated_set_and_noreset_Q_351 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_26_tsimcreated_set_and_noreset_IN0,
      I1 => REG_26_SETF,
      O => REG_26_tsimcreated_set_and_noreset_Q
    );
  REG_26_tsimcreated_prld_Q_352 : X_OR2
    port map (
      I0 => REG_26_RSTF,
      I1 => PRLD,
      O => REG_26_tsimcreated_prld_Q
    );
  REG_26_REG : X_FF
    port map (
      I => REG_26_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_26_CLKF,
      SET => REG_26_tsimcreated_set_and_noreset_Q,
      RST => REG_26_tsimcreated_prld_Q,
      O => REG_26_Q
    );
  REG_26_D_353 : X_XOR2
    port map (
      I0 => REG_26_D1,
      I1 => REG_26_D2,
      O => REG_26_D
    );
  REG_26_D1_354 : X_ZERO
    port map (
      O => REG_26_D1
    );
  REG_26_D2_PT_0_355 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_26_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_26_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_26_D2_PT_0_IN3,
      I4 => REG(25),
      I5 => NlwInverterSignal_REG_26_D2_PT_0_IN5,
      O => REG_26_D2_PT_0
    );
  REG_26_D2_PT_1_356 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_26_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_26_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_26_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_26_D2_PT_1_IN4,
      I5 => REG(26),
      O => REG_26_D2_PT_1
    );
  REG_26_D2_357 : X_OR2
    port map (
      I0 => REG_26_D2_PT_0,
      I1 => REG_26_D2_PT_1,
      O => REG_26_D2
    );
  REG_26_CLKF_358 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_26_CLKF_IN0,
      I1 => NlwInverterSignal_REG_26_CLKF_IN1,
      O => REG_26_CLKF
    );
  REG_26_SETF_359 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_26_IBUF,
      O => REG_26_SETF
    );
  REG_26_RSTF_360 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_26_RSTF_IN2,
      O => REG_26_RSTF
    );
  REG_27_Q_361 : X_BUF
    port map (
      I => REG_27_Q,
      O => REG(27)
    );
  REG_27_tsimcreated_xor_Q_362 : X_XOR2
    port map (
      I0 => REG_27_D,
      I1 => REG_27_Q,
      O => REG_27_tsimcreated_xor_Q
    );
  REG_27_tsimcreated_set_and_noreset_Q_363 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_27_tsimcreated_set_and_noreset_IN0,
      I1 => REG_27_SETF,
      O => REG_27_tsimcreated_set_and_noreset_Q
    );
  REG_27_tsimcreated_prld_Q_364 : X_OR2
    port map (
      I0 => REG_27_RSTF,
      I1 => PRLD,
      O => REG_27_tsimcreated_prld_Q
    );
  REG_27_REG : X_FF
    port map (
      I => REG_27_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_27_CLKF,
      SET => REG_27_tsimcreated_set_and_noreset_Q,
      RST => REG_27_tsimcreated_prld_Q,
      O => REG_27_Q
    );
  REG_27_D_365 : X_XOR2
    port map (
      I0 => REG_27_D1,
      I1 => REG_27_D2,
      O => REG_27_D
    );
  REG_27_D1_366 : X_ZERO
    port map (
      O => REG_27_D1
    );
  REG_27_D2_PT_0_367 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_27_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_27_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_27_D2_PT_0_IN3,
      I4 => REG(26),
      I5 => NlwInverterSignal_REG_27_D2_PT_0_IN5,
      O => REG_27_D2_PT_0
    );
  REG_27_D2_PT_1_368 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_27_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_27_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_27_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_27_D2_PT_1_IN4,
      I5 => REG(27),
      O => REG_27_D2_PT_1
    );
  REG_27_D2_369 : X_OR2
    port map (
      I0 => REG_27_D2_PT_0,
      I1 => REG_27_D2_PT_1,
      O => REG_27_D2
    );
  REG_27_CLKF_370 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_27_CLKF_IN0,
      I1 => NlwInverterSignal_REG_27_CLKF_IN1,
      O => REG_27_CLKF
    );
  REG_27_SETF_371 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_27_IBUF,
      O => REG_27_SETF
    );
  REG_27_RSTF_372 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_27_RSTF_IN2,
      O => REG_27_RSTF
    );
  REG_28_Q_373 : X_BUF
    port map (
      I => REG_28_Q,
      O => REG(28)
    );
  REG_28_tsimcreated_xor_Q_374 : X_XOR2
    port map (
      I0 => REG_28_D,
      I1 => REG_28_Q,
      O => REG_28_tsimcreated_xor_Q
    );
  REG_28_tsimcreated_set_and_noreset_Q_375 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_28_tsimcreated_set_and_noreset_IN0,
      I1 => REG_28_SETF,
      O => REG_28_tsimcreated_set_and_noreset_Q
    );
  REG_28_tsimcreated_prld_Q_376 : X_OR2
    port map (
      I0 => REG_28_RSTF,
      I1 => PRLD,
      O => REG_28_tsimcreated_prld_Q
    );
  REG_28_REG : X_FF
    port map (
      I => REG_28_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_28_CLKF,
      SET => REG_28_tsimcreated_set_and_noreset_Q,
      RST => REG_28_tsimcreated_prld_Q,
      O => REG_28_Q
    );
  REG_28_D_377 : X_XOR2
    port map (
      I0 => REG_28_D1,
      I1 => REG_28_D2,
      O => REG_28_D
    );
  REG_28_D1_378 : X_ZERO
    port map (
      O => REG_28_D1
    );
  REG_28_D2_PT_0_379 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_28_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_28_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_28_D2_PT_0_IN3,
      I4 => REG(27),
      I5 => NlwInverterSignal_REG_28_D2_PT_0_IN5,
      O => REG_28_D2_PT_0
    );
  REG_28_D2_PT_1_380 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_28_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_28_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_28_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_28_D2_PT_1_IN4,
      I5 => REG(28),
      O => REG_28_D2_PT_1
    );
  REG_28_D2_381 : X_OR2
    port map (
      I0 => REG_28_D2_PT_0,
      I1 => REG_28_D2_PT_1,
      O => REG_28_D2
    );
  REG_28_CLKF_382 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_28_CLKF_IN0,
      I1 => NlwInverterSignal_REG_28_CLKF_IN1,
      O => REG_28_CLKF
    );
  REG_28_SETF_383 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_28_IBUF,
      O => REG_28_SETF
    );
  REG_28_RSTF_384 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_28_RSTF_IN2,
      O => REG_28_RSTF
    );
  REG_29_Q_385 : X_BUF
    port map (
      I => REG_29_Q,
      O => REG(29)
    );
  REG_29_tsimcreated_xor_Q_386 : X_XOR2
    port map (
      I0 => REG_29_D,
      I1 => REG_29_Q,
      O => REG_29_tsimcreated_xor_Q
    );
  REG_29_tsimcreated_set_and_noreset_Q_387 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_29_tsimcreated_set_and_noreset_IN0,
      I1 => REG_29_SETF,
      O => REG_29_tsimcreated_set_and_noreset_Q
    );
  REG_29_tsimcreated_prld_Q_388 : X_OR2
    port map (
      I0 => REG_29_RSTF,
      I1 => PRLD,
      O => REG_29_tsimcreated_prld_Q
    );
  REG_29_REG : X_FF
    port map (
      I => REG_29_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_29_CLKF,
      SET => REG_29_tsimcreated_set_and_noreset_Q,
      RST => REG_29_tsimcreated_prld_Q,
      O => REG_29_Q
    );
  REG_29_D_389 : X_XOR2
    port map (
      I0 => REG_29_D1,
      I1 => REG_29_D2,
      O => REG_29_D
    );
  REG_29_D1_390 : X_ZERO
    port map (
      O => REG_29_D1
    );
  REG_29_D2_PT_0_391 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_29_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_29_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_29_D2_PT_0_IN3,
      I4 => REG(28),
      I5 => NlwInverterSignal_REG_29_D2_PT_0_IN5,
      O => REG_29_D2_PT_0
    );
  REG_29_D2_PT_1_392 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_29_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_29_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_29_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_29_D2_PT_1_IN4,
      I5 => REG(29),
      O => REG_29_D2_PT_1
    );
  REG_29_D2_393 : X_OR2
    port map (
      I0 => REG_29_D2_PT_0,
      I1 => REG_29_D2_PT_1,
      O => REG_29_D2
    );
  REG_29_CLKF_394 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_29_CLKF_IN0,
      I1 => NlwInverterSignal_REG_29_CLKF_IN1,
      O => REG_29_CLKF
    );
  REG_29_SETF_395 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_29_IBUF,
      O => REG_29_SETF
    );
  REG_29_RSTF_396 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_29_RSTF_IN2,
      O => REG_29_RSTF
    );
  REG_2_Q_397 : X_BUF
    port map (
      I => REG_2_Q,
      O => REG(2)
    );
  REG_2_tsimcreated_xor_Q_398 : X_XOR2
    port map (
      I0 => REG_2_D,
      I1 => REG_2_Q,
      O => REG_2_tsimcreated_xor_Q
    );
  REG_2_tsimcreated_set_and_noreset_Q_399 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_2_tsimcreated_set_and_noreset_IN0,
      I1 => REG_2_SETF,
      O => REG_2_tsimcreated_set_and_noreset_Q
    );
  REG_2_tsimcreated_prld_Q_400 : X_OR2
    port map (
      I0 => REG_2_RSTF,
      I1 => PRLD,
      O => REG_2_tsimcreated_prld_Q
    );
  REG_2_REG : X_FF
    port map (
      I => REG_2_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_2_CLKF,
      SET => REG_2_tsimcreated_set_and_noreset_Q,
      RST => REG_2_tsimcreated_prld_Q,
      O => REG_2_Q
    );
  REG_2_D_401 : X_XOR2
    port map (
      I0 => REG_2_D1,
      I1 => REG_2_D2,
      O => REG_2_D
    );
  REG_2_D1_402 : X_ZERO
    port map (
      O => REG_2_D1
    );
  REG_2_D2_PT_0_403 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_2_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_2_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_2_D2_PT_0_IN3,
      I4 => REG(1),
      I5 => NlwInverterSignal_REG_2_D2_PT_0_IN5,
      O => REG_2_D2_PT_0
    );
  REG_2_D2_PT_1_404 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_2_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_2_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_2_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_2_D2_PT_1_IN4,
      I5 => REG(2),
      O => REG_2_D2_PT_1
    );
  REG_2_D2_405 : X_OR2
    port map (
      I0 => REG_2_D2_PT_0,
      I1 => REG_2_D2_PT_1,
      O => REG_2_D2
    );
  REG_2_CLKF_406 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_2_CLKF_IN0,
      I1 => NlwInverterSignal_REG_2_CLKF_IN1,
      O => REG_2_CLKF
    );
  REG_2_SETF_407 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_2_IBUF,
      O => REG_2_SETF
    );
  REG_2_RSTF_408 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_2_RSTF_IN2,
      O => REG_2_RSTF
    );
  REG_30_Q_409 : X_BUF
    port map (
      I => REG_30_Q,
      O => REG(30)
    );
  REG_30_tsimcreated_xor_Q_410 : X_XOR2
    port map (
      I0 => REG_30_D,
      I1 => REG_30_Q,
      O => REG_30_tsimcreated_xor_Q
    );
  REG_30_tsimcreated_set_and_noreset_Q_411 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_30_tsimcreated_set_and_noreset_IN0,
      I1 => REG_30_SETF,
      O => REG_30_tsimcreated_set_and_noreset_Q
    );
  REG_30_tsimcreated_prld_Q_412 : X_OR2
    port map (
      I0 => REG_30_RSTF,
      I1 => PRLD,
      O => REG_30_tsimcreated_prld_Q
    );
  REG_30_REG : X_FF
    port map (
      I => REG_30_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_30_CLKF,
      SET => REG_30_tsimcreated_set_and_noreset_Q,
      RST => REG_30_tsimcreated_prld_Q,
      O => REG_30_Q
    );
  REG_30_D_413 : X_XOR2
    port map (
      I0 => REG_30_D1,
      I1 => REG_30_D2,
      O => REG_30_D
    );
  REG_30_D1_414 : X_ZERO
    port map (
      O => REG_30_D1
    );
  REG_30_D2_PT_0_415 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_30_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_30_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => REG(30),
      I4 => NlwInverterSignal_REG_30_D2_PT_0_IN4,
      I5 => NlwInverterSignal_REG_30_D2_PT_0_IN5,
      O => REG_30_D2_PT_0
    );
  REG_30_D2_PT_1_416 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_30_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_30_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_30_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_30_D2_PT_1_IN4,
      I5 => REG(29),
      O => REG_30_D2_PT_1
    );
  REG_30_D2_417 : X_OR2
    port map (
      I0 => REG_30_D2_PT_0,
      I1 => REG_30_D2_PT_1,
      O => REG_30_D2
    );
  REG_30_CLKF_418 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_30_CLKF_IN0,
      I1 => NlwInverterSignal_REG_30_CLKF_IN1,
      O => REG_30_CLKF
    );
  REG_30_SETF_419 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_30_IBUF,
      O => REG_30_SETF
    );
  REG_30_RSTF_420 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_30_RSTF_IN2,
      O => REG_30_RSTF
    );
  REG_3_Q_421 : X_BUF
    port map (
      I => REG_3_Q,
      O => REG(3)
    );
  REG_3_tsimcreated_xor_Q_422 : X_XOR2
    port map (
      I0 => REG_3_D,
      I1 => REG_3_Q,
      O => REG_3_tsimcreated_xor_Q
    );
  REG_3_tsimcreated_set_and_noreset_Q_423 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_3_tsimcreated_set_and_noreset_IN0,
      I1 => REG_3_SETF,
      O => REG_3_tsimcreated_set_and_noreset_Q
    );
  REG_3_tsimcreated_prld_Q_424 : X_OR2
    port map (
      I0 => REG_3_RSTF,
      I1 => PRLD,
      O => REG_3_tsimcreated_prld_Q
    );
  REG_3_REG : X_FF
    port map (
      I => REG_3_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_3_CLKF,
      SET => REG_3_tsimcreated_set_and_noreset_Q,
      RST => REG_3_tsimcreated_prld_Q,
      O => REG_3_Q
    );
  REG_3_D_425 : X_XOR2
    port map (
      I0 => REG_3_D1,
      I1 => REG_3_D2,
      O => REG_3_D
    );
  REG_3_D1_426 : X_ZERO
    port map (
      O => REG_3_D1
    );
  REG_3_D2_PT_0_427 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_3_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_3_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_3_D2_PT_0_IN3,
      I4 => REG(2),
      I5 => NlwInverterSignal_REG_3_D2_PT_0_IN5,
      O => REG_3_D2_PT_0
    );
  REG_3_D2_PT_1_428 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_3_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_3_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_3_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_3_D2_PT_1_IN4,
      I5 => REG(3),
      O => REG_3_D2_PT_1
    );
  REG_3_D2_429 : X_OR2
    port map (
      I0 => REG_3_D2_PT_0,
      I1 => REG_3_D2_PT_1,
      O => REG_3_D2
    );
  REG_3_CLKF_430 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_3_CLKF_IN0,
      I1 => NlwInverterSignal_REG_3_CLKF_IN1,
      O => REG_3_CLKF
    );
  REG_3_SETF_431 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_3_IBUF,
      O => REG_3_SETF
    );
  REG_3_RSTF_432 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_3_RSTF_IN2,
      O => REG_3_RSTF
    );
  REG_4_Q_433 : X_BUF
    port map (
      I => REG_4_Q,
      O => REG(4)
    );
  REG_4_tsimcreated_xor_Q_434 : X_XOR2
    port map (
      I0 => REG_4_D,
      I1 => REG_4_Q,
      O => REG_4_tsimcreated_xor_Q
    );
  REG_4_tsimcreated_set_and_noreset_Q_435 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_4_tsimcreated_set_and_noreset_IN0,
      I1 => REG_4_SETF,
      O => REG_4_tsimcreated_set_and_noreset_Q
    );
  REG_4_tsimcreated_prld_Q_436 : X_OR2
    port map (
      I0 => REG_4_RSTF,
      I1 => PRLD,
      O => REG_4_tsimcreated_prld_Q
    );
  REG_4_REG : X_FF
    port map (
      I => REG_4_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_4_CLKF,
      SET => REG_4_tsimcreated_set_and_noreset_Q,
      RST => REG_4_tsimcreated_prld_Q,
      O => REG_4_Q
    );
  REG_4_D_437 : X_XOR2
    port map (
      I0 => REG_4_D1,
      I1 => REG_4_D2,
      O => REG_4_D
    );
  REG_4_D1_438 : X_ZERO
    port map (
      O => REG_4_D1
    );
  REG_4_D2_PT_0_439 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_4_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_4_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_4_D2_PT_0_IN3,
      I4 => REG(3),
      I5 => NlwInverterSignal_REG_4_D2_PT_0_IN5,
      O => REG_4_D2_PT_0
    );
  REG_4_D2_PT_1_440 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_4_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_4_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_4_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_4_D2_PT_1_IN4,
      I5 => REG(4),
      O => REG_4_D2_PT_1
    );
  REG_4_D2_441 : X_OR2
    port map (
      I0 => REG_4_D2_PT_0,
      I1 => REG_4_D2_PT_1,
      O => REG_4_D2
    );
  REG_4_CLKF_442 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_4_CLKF_IN0,
      I1 => NlwInverterSignal_REG_4_CLKF_IN1,
      O => REG_4_CLKF
    );
  REG_4_SETF_443 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_4_IBUF,
      O => REG_4_SETF
    );
  REG_4_RSTF_444 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_4_RSTF_IN2,
      O => REG_4_RSTF
    );
  REG_5_Q_445 : X_BUF
    port map (
      I => REG_5_Q,
      O => REG(5)
    );
  REG_5_tsimcreated_xor_Q_446 : X_XOR2
    port map (
      I0 => REG_5_D,
      I1 => REG_5_Q,
      O => REG_5_tsimcreated_xor_Q
    );
  REG_5_tsimcreated_set_and_noreset_Q_447 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_5_tsimcreated_set_and_noreset_IN0,
      I1 => REG_5_SETF,
      O => REG_5_tsimcreated_set_and_noreset_Q
    );
  REG_5_tsimcreated_prld_Q_448 : X_OR2
    port map (
      I0 => REG_5_RSTF,
      I1 => PRLD,
      O => REG_5_tsimcreated_prld_Q
    );
  REG_5_REG : X_FF
    port map (
      I => REG_5_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_5_CLKF,
      SET => REG_5_tsimcreated_set_and_noreset_Q,
      RST => REG_5_tsimcreated_prld_Q,
      O => REG_5_Q
    );
  REG_5_D_449 : X_XOR2
    port map (
      I0 => REG_5_D1,
      I1 => REG_5_D2,
      O => REG_5_D
    );
  REG_5_D1_450 : X_ZERO
    port map (
      O => REG_5_D1
    );
  REG_5_D2_PT_0_451 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_5_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_5_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_5_D2_PT_0_IN3,
      I4 => REG(4),
      I5 => NlwInverterSignal_REG_5_D2_PT_0_IN5,
      O => REG_5_D2_PT_0
    );
  REG_5_D2_PT_1_452 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_5_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_5_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_5_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_5_D2_PT_1_IN4,
      I5 => REG(5),
      O => REG_5_D2_PT_1
    );
  REG_5_D2_453 : X_OR2
    port map (
      I0 => REG_5_D2_PT_0,
      I1 => REG_5_D2_PT_1,
      O => REG_5_D2
    );
  REG_5_CLKF_454 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_5_CLKF_IN0,
      I1 => NlwInverterSignal_REG_5_CLKF_IN1,
      O => REG_5_CLKF
    );
  REG_5_SETF_455 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_5_IBUF,
      O => REG_5_SETF
    );
  REG_5_RSTF_456 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_5_RSTF_IN2,
      O => REG_5_RSTF
    );
  REG_6_Q_457 : X_BUF
    port map (
      I => REG_6_Q,
      O => REG(6)
    );
  REG_6_tsimcreated_xor_Q_458 : X_XOR2
    port map (
      I0 => REG_6_D,
      I1 => REG_6_Q,
      O => REG_6_tsimcreated_xor_Q
    );
  REG_6_tsimcreated_set_and_noreset_Q_459 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_6_tsimcreated_set_and_noreset_IN0,
      I1 => REG_6_SETF,
      O => REG_6_tsimcreated_set_and_noreset_Q
    );
  REG_6_tsimcreated_prld_Q_460 : X_OR2
    port map (
      I0 => REG_6_RSTF,
      I1 => PRLD,
      O => REG_6_tsimcreated_prld_Q
    );
  REG_6_REG : X_FF
    port map (
      I => REG_6_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_6_CLKF,
      SET => REG_6_tsimcreated_set_and_noreset_Q,
      RST => REG_6_tsimcreated_prld_Q,
      O => REG_6_Q
    );
  REG_6_D_461 : X_XOR2
    port map (
      I0 => REG_6_D1,
      I1 => REG_6_D2,
      O => REG_6_D
    );
  REG_6_D1_462 : X_ZERO
    port map (
      O => REG_6_D1
    );
  REG_6_D2_PT_0_463 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_6_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_6_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_6_D2_PT_0_IN3,
      I4 => REG(5),
      I5 => NlwInverterSignal_REG_6_D2_PT_0_IN5,
      O => REG_6_D2_PT_0
    );
  REG_6_D2_PT_1_464 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_6_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_6_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_6_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_6_D2_PT_1_IN4,
      I5 => REG(6),
      O => REG_6_D2_PT_1
    );
  REG_6_D2_465 : X_OR2
    port map (
      I0 => REG_6_D2_PT_0,
      I1 => REG_6_D2_PT_1,
      O => REG_6_D2
    );
  REG_6_CLKF_466 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_6_CLKF_IN0,
      I1 => NlwInverterSignal_REG_6_CLKF_IN1,
      O => REG_6_CLKF
    );
  REG_6_SETF_467 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_6_IBUF,
      O => REG_6_SETF
    );
  REG_6_RSTF_468 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_6_RSTF_IN2,
      O => REG_6_RSTF
    );
  REG_7_Q_469 : X_BUF
    port map (
      I => REG_7_Q,
      O => REG(7)
    );
  REG_7_tsimcreated_xor_Q_470 : X_XOR2
    port map (
      I0 => REG_7_D,
      I1 => REG_7_Q,
      O => REG_7_tsimcreated_xor_Q
    );
  REG_7_tsimcreated_set_and_noreset_Q_471 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_7_tsimcreated_set_and_noreset_IN0,
      I1 => REG_7_SETF,
      O => REG_7_tsimcreated_set_and_noreset_Q
    );
  REG_7_tsimcreated_prld_Q_472 : X_OR2
    port map (
      I0 => REG_7_RSTF,
      I1 => PRLD,
      O => REG_7_tsimcreated_prld_Q
    );
  REG_7_REG : X_FF
    port map (
      I => REG_7_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_7_CLKF,
      SET => REG_7_tsimcreated_set_and_noreset_Q,
      RST => REG_7_tsimcreated_prld_Q,
      O => REG_7_Q
    );
  REG_7_D_473 : X_XOR2
    port map (
      I0 => REG_7_D1,
      I1 => REG_7_D2,
      O => REG_7_D
    );
  REG_7_D1_474 : X_ZERO
    port map (
      O => REG_7_D1
    );
  REG_7_D2_PT_0_475 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_7_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_7_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_7_D2_PT_0_IN3,
      I4 => REG(6),
      I5 => NlwInverterSignal_REG_7_D2_PT_0_IN5,
      O => REG_7_D2_PT_0
    );
  REG_7_D2_PT_1_476 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_7_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_7_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_7_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_7_D2_PT_1_IN4,
      I5 => REG(7),
      O => REG_7_D2_PT_1
    );
  REG_7_D2_477 : X_OR2
    port map (
      I0 => REG_7_D2_PT_0,
      I1 => REG_7_D2_PT_1,
      O => REG_7_D2
    );
  REG_7_CLKF_478 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_7_CLKF_IN0,
      I1 => NlwInverterSignal_REG_7_CLKF_IN1,
      O => REG_7_CLKF
    );
  REG_7_SETF_479 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_7_IBUF,
      O => REG_7_SETF
    );
  REG_7_RSTF_480 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_7_RSTF_IN2,
      O => REG_7_RSTF
    );
  REG_8_Q_481 : X_BUF
    port map (
      I => REG_8_Q,
      O => REG(8)
    );
  REG_8_tsimcreated_xor_Q_482 : X_XOR2
    port map (
      I0 => REG_8_D,
      I1 => REG_8_Q,
      O => REG_8_tsimcreated_xor_Q
    );
  REG_8_tsimcreated_set_and_noreset_Q_483 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_8_tsimcreated_set_and_noreset_IN0,
      I1 => REG_8_SETF,
      O => REG_8_tsimcreated_set_and_noreset_Q
    );
  REG_8_tsimcreated_prld_Q_484 : X_OR2
    port map (
      I0 => REG_8_RSTF,
      I1 => PRLD,
      O => REG_8_tsimcreated_prld_Q
    );
  REG_8_REG : X_FF
    port map (
      I => REG_8_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_8_CLKF,
      SET => REG_8_tsimcreated_set_and_noreset_Q,
      RST => REG_8_tsimcreated_prld_Q,
      O => REG_8_Q
    );
  REG_8_D_485 : X_XOR2
    port map (
      I0 => REG_8_D1,
      I1 => REG_8_D2,
      O => REG_8_D
    );
  REG_8_D1_486 : X_ZERO
    port map (
      O => REG_8_D1
    );
  REG_8_D2_PT_0_487 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_8_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_8_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_8_D2_PT_0_IN3,
      I4 => REG(7),
      I5 => NlwInverterSignal_REG_8_D2_PT_0_IN5,
      O => REG_8_D2_PT_0
    );
  REG_8_D2_PT_1_488 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_8_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_8_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_8_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_8_D2_PT_1_IN4,
      I5 => REG(8),
      O => REG_8_D2_PT_1
    );
  REG_8_D2_489 : X_OR2
    port map (
      I0 => REG_8_D2_PT_0,
      I1 => REG_8_D2_PT_1,
      O => REG_8_D2
    );
  REG_8_CLKF_490 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_8_CLKF_IN0,
      I1 => NlwInverterSignal_REG_8_CLKF_IN1,
      O => REG_8_CLKF
    );
  REG_8_SETF_491 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_8_IBUF,
      O => REG_8_SETF
    );
  REG_8_RSTF_492 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_8_RSTF_IN2,
      O => REG_8_RSTF
    );
  REG_9_Q_493 : X_BUF
    port map (
      I => REG_9_Q,
      O => REG(9)
    );
  REG_9_tsimcreated_xor_Q_494 : X_XOR2
    port map (
      I0 => REG_9_D,
      I1 => REG_9_Q,
      O => REG_9_tsimcreated_xor_Q
    );
  REG_9_tsimcreated_set_and_noreset_Q_495 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_9_tsimcreated_set_and_noreset_IN0,
      I1 => REG_9_SETF,
      O => REG_9_tsimcreated_set_and_noreset_Q
    );
  REG_9_tsimcreated_prld_Q_496 : X_OR2
    port map (
      I0 => REG_9_RSTF,
      I1 => PRLD,
      O => REG_9_tsimcreated_prld_Q
    );
  REG_9_REG : X_FF
    port map (
      I => REG_9_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_9_CLKF,
      SET => REG_9_tsimcreated_set_and_noreset_Q,
      RST => REG_9_tsimcreated_prld_Q,
      O => REG_9_Q
    );
  REG_9_D_497 : X_XOR2
    port map (
      I0 => REG_9_D1,
      I1 => REG_9_D2,
      O => REG_9_D
    );
  REG_9_D1_498 : X_ZERO
    port map (
      O => REG_9_D1
    );
  REG_9_D2_PT_0_499 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_9_D2_PT_0_IN0,
      I1 => NlwInverterSignal_REG_9_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_9_D2_PT_0_IN3,
      I4 => REG(9),
      I5 => NlwInverterSignal_REG_9_D2_PT_0_IN5,
      O => REG_9_D2_PT_0
    );
  REG_9_D2_PT_1_500 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_9_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_9_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_9_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_9_D2_PT_1_IN4,
      I5 => REG(8),
      O => REG_9_D2_PT_1
    );
  REG_9_D2_501 : X_OR2
    port map (
      I0 => REG_9_D2_PT_0,
      I1 => REG_9_D2_PT_1,
      O => REG_9_D2
    );
  REG_9_CLKF_502 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_9_CLKF_IN0,
      I1 => NlwInverterSignal_REG_9_CLKF_IN1,
      O => REG_9_CLKF
    );
  REG_9_SETF_503 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => DIN_9_IBUF,
      O => REG_9_SETF
    );
  REG_9_RSTF_504 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => SREG_IS_EMPTY,
      I2 => NlwInverterSignal_REG_9_RSTF_IN2,
      O => REG_9_RSTF
    );
  count_5_Q_505 : X_BUF
    port map (
      I => count_5_Q,
      O => count(5)
    );
  count_5_EXP_506 : X_BUF
    port map (
      I => count_5_EXP_tsimrenamed_net_Q,
      O => count_5_EXP
    );
  count_5_tsimcreated_xor_Q_507 : X_XOR2
    port map (
      I0 => count_5_D,
      I1 => count_5_Q,
      O => count_5_tsimcreated_xor_Q
    );
  count_5_tsimcreated_set_and_noreset_Q_508 : X_AND2
    port map (
      I0 => NlwInverterSignal_count_5_tsimcreated_set_and_noreset_IN0,
      I1 => count_5_SETF,
      O => count_5_tsimcreated_set_and_noreset_Q
    );
  count_5_tsimcreated_prld_Q_509 : X_OR2
    port map (
      I0 => count_5_RSTF,
      I1 => PRLD,
      O => count_5_tsimcreated_prld_Q
    );
  count_5_REG : X_FF
    port map (
      I => count_5_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => count_5_tsimcreated_set_and_noreset_Q,
      RST => count_5_tsimcreated_prld_Q,
      O => count_5_Q
    );
  count_5_D_510 : X_XOR2
    port map (
      I0 => count_5_D1,
      I1 => count_5_D2,
      O => count_5_D
    );
  count_5_D1_511 : X_ZERO
    port map (
      O => count_5_D1
    );
  count_5_D2_PT_0_512 : X_AND2
    port map (
      I0 => EXP18_EXP,
      I1 => EXP18_EXP,
      O => count_5_D2_PT_0
    );
  count_5_D2_PT_1_513 : X_AND3
    port map (
      I0 => RES_IBUF,
      I1 => count(5),
      I2 => NlwInverterSignal_count_5_D2_PT_1_IN2,
      O => count_5_D2_PT_1
    );
  count_5_D2_PT_2_514 : X_AND3
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_5_D2_PT_2_IN1,
      I2 => VCLK_PRESCALE_5_IBUF,
      O => count_5_D2_PT_2
    );
  count_5_D2_515 : X_OR3
    port map (
      I0 => count_5_D2_PT_0,
      I1 => count_5_D2_PT_1,
      I2 => count_5_D2_PT_2,
      O => count_5_D2
    );
  count_5_SETF_516 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => VCLK_PRESCALE_5_IBUF,
      O => count_5_SETF
    );
  count_5_RSTF_517 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_5_RSTF_IN1,
      O => count_5_RSTF
    );
  count_5_EXP_tsimrenamed_net_Q_518 : X_AND6
    port map (
      I0 => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN0,
      I1 => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN1,
      I2 => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN2,
      I3 => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN3,
      I4 => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN4,
      I5 => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN5,
      O => count_5_EXP_tsimrenamed_net_Q
    );
  SREG_IS_EMPTY_519 : X_BUF
    port map (
      I => SREG_IS_EMPTY_Q,
      O => SREG_IS_EMPTY
    );
  SREG_IS_EMPTY_tsimcreated_set_and_noreset_Q_520 : X_AND2
    port map (
      I0 => NlwInverterSignal_SREG_IS_EMPTY_tsimcreated_set_and_noreset_IN0,
      I1 => SREG_IS_EMPTY_SETF,
      O => SREG_IS_EMPTY_tsimcreated_set_and_noreset_Q
    );
  SREG_IS_EMPTY_tsimcreated_prld_Q_521 : X_OR2
    port map (
      I0 => SREG_IS_EMPTY_RSTF,
      I1 => PRLD,
      O => SREG_IS_EMPTY_tsimcreated_prld_Q
    );
  SREG_IS_EMPTY_REG : X_FF
    port map (
      I => SREG_IS_EMPTY_D,
      CE => Vcc,
      CLK => SREG_IS_EMPTY_CLKF,
      SET => SREG_IS_EMPTY_tsimcreated_set_and_noreset_Q,
      RST => SREG_IS_EMPTY_tsimcreated_prld_Q,
      O => SREG_IS_EMPTY_Q
    );
  SREG_IS_EMPTY_D_522 : X_XOR2
    port map (
      I0 => SREG_IS_EMPTY_D1,
      I1 => SREG_IS_EMPTY_D2,
      O => SREG_IS_EMPTY_D
    );
  SREG_IS_EMPTY_D1_523 : X_ZERO
    port map (
      O => SREG_IS_EMPTY_D1
    );
  SREG_IS_EMPTY_D2_524 : X_ZERO
    port map (
      O => SREG_IS_EMPTY_D2
    );
  SREG_IS_EMPTY_CLKF_525 : X_ZERO
    port map (
      O => SREG_IS_EMPTY_CLKF
    );
  SREG_IS_EMPTY_SETF_526 : X_AND2
    port map (
      I0 => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_UIM,
      I1 => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_UIM,
      O => SREG_IS_EMPTY_SETF
    );
  SREG_IS_EMPTY_RSTF_527 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => NlwInverterSignal_SREG_IS_EMPTY_RSTF_IN1,
      I2 => SREG_IS_EMPTY,
      O => SREG_IS_EMPTY_RSTF
    );
  SHIFT_CNT_0_Q_528 : X_BUF
    port map (
      I => SHIFT_CNT_0_Q,
      O => SHIFT_CNT(0)
    );
  SHIFT_CNT_0_tsimcreated_set_and_noreset_Q_529 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_0_tsimcreated_set_and_noreset_IN0,
      I1 => SHIFT_CNT_0_SETF,
      O => SHIFT_CNT_0_tsimcreated_set_and_noreset_Q
    );
  SHIFT_CNT_0_tsimcreated_prld_Q_530 : X_OR2
    port map (
      I0 => SHIFT_CNT_0_RSTF,
      I1 => PRLD,
      O => SHIFT_CNT_0_tsimcreated_prld_Q
    );
  SHIFT_CNT_0_REG : X_FF
    port map (
      I => SHIFT_CNT_0_D,
      CE => Vcc,
      CLK => SHIFT_CNT_0_CLKF,
      SET => SHIFT_CNT_0_tsimcreated_set_and_noreset_Q,
      RST => SHIFT_CNT_0_tsimcreated_prld_Q,
      O => SHIFT_CNT_0_Q
    );
  SHIFT_CNT_0_D_531 : X_XOR2
    port map (
      I0 => SHIFT_CNT_0_D1,
      I1 => SHIFT_CNT_0_D2,
      O => SHIFT_CNT_0_D
    );
  SHIFT_CNT_0_D1_532 : X_ZERO
    port map (
      O => SHIFT_CNT_0_D1
    );
  SHIFT_CNT_0_D2_533 : X_ZERO
    port map (
      O => SHIFT_CNT_0_D2
    );
  SHIFT_CNT_0_CLKF_534 : X_ZERO
    port map (
      O => SHIFT_CNT_0_CLKF
    );
  SHIFT_CNT_0_SETF_535 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_0_SETF_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_0_SETF_IN1,
      O => SHIFT_CNT_0_SETF
    );
  SHIFT_CNT_0_RSTF_536 : X_AND4
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_0_RSTF_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_0_RSTF_IN1,
      I2 => SHIFT_EN,
      I3 => SHIFT_CNT(0),
      O => SHIFT_CNT_0_RSTF
    );
  SHIFT_CNT_1_Q_537 : X_BUF
    port map (
      I => SHIFT_CNT_1_Q,
      O => SHIFT_CNT(1)
    );
  SHIFT_CNT_1_tsimcreated_set_and_noreset_Q_538 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_1_tsimcreated_set_and_noreset_IN0,
      I1 => SHIFT_CNT_1_SETF,
      O => SHIFT_CNT_1_tsimcreated_set_and_noreset_Q
    );
  SHIFT_CNT_1_tsimcreated_prld_Q_539 : X_OR2
    port map (
      I0 => SHIFT_CNT_1_RSTF,
      I1 => PRLD,
      O => SHIFT_CNT_1_tsimcreated_prld_Q
    );
  SHIFT_CNT_1_REG : X_FF
    port map (
      I => SHIFT_CNT_1_D,
      CE => Vcc,
      CLK => SHIFT_CNT_1_CLKF,
      SET => SHIFT_CNT_1_tsimcreated_set_and_noreset_Q,
      RST => SHIFT_CNT_1_tsimcreated_prld_Q,
      O => SHIFT_CNT_1_Q
    );
  SHIFT_CNT_1_D_540 : X_XOR2
    port map (
      I0 => SHIFT_CNT_1_D1,
      I1 => SHIFT_CNT_1_D2,
      O => SHIFT_CNT_1_D
    );
  SHIFT_CNT_1_D1_541 : X_ZERO
    port map (
      O => SHIFT_CNT_1_D1
    );
  SHIFT_CNT_1_D2_542 : X_ZERO
    port map (
      O => SHIFT_CNT_1_D2
    );
  SHIFT_CNT_1_CLKF_543 : X_ZERO
    port map (
      O => SHIFT_CNT_1_CLKF
    );
  SHIFT_CNT_1_SETF_544 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_1_SETF_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_1_SETF_IN1,
      O => SHIFT_CNT_1_SETF
    );
  SHIFT_CNT_1_RSTF_545 : X_AND5
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_1_RSTF_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_1_RSTF_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_SHIFT_CNT_1_RSTF_IN3,
      I4 => NlwInverterSignal_SHIFT_CNT_1_RSTF_IN4,
      O => SHIFT_CNT_1_RSTF
    );
  SHIFT_CNT_2_Q_546 : X_BUF
    port map (
      I => SHIFT_CNT_2_Q,
      O => SHIFT_CNT(2)
    );
  SHIFT_CNT_2_tsimcreated_set_and_noreset_Q_547 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_2_tsimcreated_set_and_noreset_IN0,
      I1 => SHIFT_CNT_2_SETF,
      O => SHIFT_CNT_2_tsimcreated_set_and_noreset_Q
    );
  SHIFT_CNT_2_tsimcreated_prld_Q_548 : X_OR2
    port map (
      I0 => SHIFT_CNT_2_RSTF,
      I1 => PRLD,
      O => SHIFT_CNT_2_tsimcreated_prld_Q
    );
  SHIFT_CNT_2_REG : X_FF
    port map (
      I => SHIFT_CNT_2_D,
      CE => Vcc,
      CLK => SHIFT_CNT_2_CLKF,
      SET => SHIFT_CNT_2_tsimcreated_set_and_noreset_Q,
      RST => SHIFT_CNT_2_tsimcreated_prld_Q,
      O => SHIFT_CNT_2_Q
    );
  SHIFT_CNT_2_D_549 : X_XOR2
    port map (
      I0 => SHIFT_CNT_2_D1,
      I1 => SHIFT_CNT_2_D2,
      O => SHIFT_CNT_2_D
    );
  SHIFT_CNT_2_D1_550 : X_ZERO
    port map (
      O => SHIFT_CNT_2_D1
    );
  SHIFT_CNT_2_D2_551 : X_ZERO
    port map (
      O => SHIFT_CNT_2_D2
    );
  SHIFT_CNT_2_CLKF_552 : X_ZERO
    port map (
      O => SHIFT_CNT_2_CLKF
    );
  SHIFT_CNT_2_SETF_553 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_2_SETF_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_2_SETF_IN1,
      O => SHIFT_CNT_2_SETF
    );
  SHIFT_CNT_2_RSTF_554 : X_AND2
    port map (
      I0 => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_UIM,
      I1 => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_UIM,
      O => SHIFT_CNT_2_RSTF
    );
  SHIFT_CNT_3_Q_555 : X_BUF
    port map (
      I => SHIFT_CNT_3_Q,
      O => SHIFT_CNT(3)
    );
  SHIFT_CNT_3_tsimcreated_set_and_noreset_Q_556 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_3_tsimcreated_set_and_noreset_IN0,
      I1 => SHIFT_CNT_3_SETF,
      O => SHIFT_CNT_3_tsimcreated_set_and_noreset_Q
    );
  SHIFT_CNT_3_tsimcreated_prld_Q_557 : X_OR2
    port map (
      I0 => SHIFT_CNT_3_RSTF,
      I1 => PRLD,
      O => SHIFT_CNT_3_tsimcreated_prld_Q
    );
  SHIFT_CNT_3_REG : X_FF
    port map (
      I => SHIFT_CNT_3_D,
      CE => Vcc,
      CLK => SHIFT_CNT_3_CLKF,
      SET => SHIFT_CNT_3_tsimcreated_set_and_noreset_Q,
      RST => SHIFT_CNT_3_tsimcreated_prld_Q,
      O => SHIFT_CNT_3_Q
    );
  SHIFT_CNT_3_D_558 : X_XOR2
    port map (
      I0 => SHIFT_CNT_3_D1,
      I1 => SHIFT_CNT_3_D2,
      O => SHIFT_CNT_3_D
    );
  SHIFT_CNT_3_D1_559 : X_ZERO
    port map (
      O => SHIFT_CNT_3_D1
    );
  SHIFT_CNT_3_D2_560 : X_ZERO
    port map (
      O => SHIFT_CNT_3_D2
    );
  SHIFT_CNT_3_CLKF_561 : X_ZERO
    port map (
      O => SHIFT_CNT_3_CLKF
    );
  SHIFT_CNT_3_SETF_562 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_3_SETF_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_3_SETF_IN1,
      O => SHIFT_CNT_3_SETF
    );
  SHIFT_CNT_3_RSTF_563 : X_AND5
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_3_RSTF_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_3_RSTF_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_SHIFT_CNT_3_RSTF_IN3,
      I4 => Q_OpTx_FX_DC_20_UIM,
      O => SHIFT_CNT_3_RSTF
    );
  SHIFT_CNT_4_Q_564 : X_BUF
    port map (
      I => SHIFT_CNT_4_Q,
      O => SHIFT_CNT(4)
    );
  SHIFT_CNT_4_tsimcreated_set_and_noreset_Q_565 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_4_tsimcreated_set_and_noreset_IN0,
      I1 => SHIFT_CNT_4_SETF,
      O => SHIFT_CNT_4_tsimcreated_set_and_noreset_Q
    );
  SHIFT_CNT_4_tsimcreated_prld_Q_566 : X_OR2
    port map (
      I0 => SHIFT_CNT_4_RSTF,
      I1 => PRLD,
      O => SHIFT_CNT_4_tsimcreated_prld_Q
    );
  SHIFT_CNT_4_REG : X_FF
    port map (
      I => SHIFT_CNT_4_D,
      CE => Vcc,
      CLK => SHIFT_CNT_4_CLKF,
      SET => SHIFT_CNT_4_tsimcreated_set_and_noreset_Q,
      RST => SHIFT_CNT_4_tsimcreated_prld_Q,
      O => SHIFT_CNT_4_Q
    );
  SHIFT_CNT_4_D_567 : X_XOR2
    port map (
      I0 => SHIFT_CNT_4_D1,
      I1 => SHIFT_CNT_4_D2,
      O => SHIFT_CNT_4_D
    );
  SHIFT_CNT_4_D1_568 : X_ZERO
    port map (
      O => SHIFT_CNT_4_D1
    );
  SHIFT_CNT_4_D2_569 : X_ZERO
    port map (
      O => SHIFT_CNT_4_D2
    );
  SHIFT_CNT_4_CLKF_570 : X_ZERO
    port map (
      O => SHIFT_CNT_4_CLKF
    );
  SHIFT_CNT_4_SETF_571 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_4_SETF_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_4_SETF_IN1,
      O => SHIFT_CNT_4_SETF
    );
  SHIFT_CNT_4_RSTF_572 : X_AND2
    port map (
      I0 => Q_OpTx_FX_DC_21_UIM,
      I1 => NlwInverterSignal_SHIFT_CNT_4_RSTF_IN1,
      O => SHIFT_CNT_4_RSTF
    );
  VCLK_OBUF_Q_573 : X_BUF
    port map (
      I => VCLK_OBUF_Q_1,
      O => VCLK_OBUF_Q
    );
  SCLK_574 : X_BUF
    port map (
      I => VCLK_OBUF_Q_1,
      O => SCLK
    );
  VCLK_OBUF_tsimcreated_xor_Q_575 : X_XOR2
    port map (
      I0 => VCLK_OBUF_D,
      I1 => VCLK_OBUF_Q_1,
      O => VCLK_OBUF_tsimcreated_xor_Q
    );
  VCLK_OBUF_REG : X_FF
    port map (
      I => VCLK_OBUF_tsimcreated_xor_Q,
      CE => VCLK_OBUF_CE,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => VCLK_OBUF_RSTF,
      O => VCLK_OBUF_Q_1
    );
  VCLK_OBUF_D_576 : X_XOR2
    port map (
      I0 => VCLK_OBUF_D1,
      I1 => VCLK_OBUF_D2,
      O => VCLK_OBUF_D
    );
  VCLK_OBUF_D1_577 : X_ZERO
    port map (
      O => VCLK_OBUF_D1
    );
  VCLK_OBUF_D2_578 : X_ONE
    port map (
      O => VCLK_OBUF_D2
    );
  VCLK_OBUF_RSTF_579 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => RES_IBUF,
      O => VCLK_OBUF_RSTF
    );
  VCLK_OBUF_CE_580 : X_AND6
    port map (
      I0 => NlwInverterSignal_VCLK_OBUF_CE_IN0,
      I1 => NlwInverterSignal_VCLK_OBUF_CE_IN1,
      I2 => NlwInverterSignal_VCLK_OBUF_CE_IN2,
      I3 => NlwInverterSignal_VCLK_OBUF_CE_IN3,
      I4 => NlwInverterSignal_VCLK_OBUF_CE_IN4,
      I5 => NlwInverterSignal_VCLK_OBUF_CE_IN5,
      O => VCLK_OBUF_CE
    );
  SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_UIM_581 : X_BUF
    port map (
      I => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_Q,
      O => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_UIM
    );
  SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_Q_582 : X_BUF
    port map (
      I => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D,
      O => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_Q
    );
  SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D_583 : X_XOR2
    port map (
      I0 => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D1,
      I1 => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2,
      O => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D
    );
  SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D1_584 : X_ZERO
    port map (
      O => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D1
    );
  SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_0_585 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => RES_IBUF,
      O => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_0
    );
  SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_586 : X_AND7
    port map (
      I0 => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN0,
      I1 => SHIFT_EN,
      I2 => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN2,
      I3 => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN3,
      I4 => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN4,
      I5 => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN5,
      I6 => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN6,
      O => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1
    );
  SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_587 : X_OR2
    port map (
      I0 => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_0,
      I1 => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1,
      O => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2
    );
  SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_UIM_588 : X_BUF
    port map (
      I => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_Q,
      O => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_UIM
    );
  SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_Q_589 : X_BUF
    port map (
      I => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D,
      O => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_Q
    );
  SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D_590 : X_XOR2
    port map (
      I0 => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D1,
      I1 => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2,
      O => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D
    );
  SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D1_591 : X_ZERO
    port map (
      O => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D1
    );
  SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0_592 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0_IN1,
      I2 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0_IN2,
      O => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0
    );
  SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_593 : X_AND3
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN1,
      I2 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN2,
      O => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1
    );
  SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2_594 : X_AND3
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2_IN1,
      I2 => SHIFT_CNT(0),
      O => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2
    );
  SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_595 : X_AND6
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN1,
      I2 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN2,
      I3 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN3,
      I4 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN4,
      I5 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN5,
      O => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3
    );
  SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_596 : X_OR4
    port map (
      I0 => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0,
      I1 => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1,
      I2 => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2,
      I3 => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3,
      O => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2
    );
  SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_UIM_597 : X_BUF
    port map (
      I => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_Q,
      O => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_UIM
    );
  SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_Q_598 : X_BUF
    port map (
      I => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D,
      O => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_Q
    );
  SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D_599 : X_XOR2
    port map (
      I0 => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D1,
      I1 => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2,
      O => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D
    );
  SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D1_600 : X_ZERO
    port map (
      O => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D1
    );
  SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0_601 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0_IN1,
      I2 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0_IN2,
      O => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0
    );
  SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_602 : X_AND3
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN1,
      I2 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN2,
      O => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1
    );
  SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_603 : X_AND4
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN1,
      I2 => SHIFT_CNT(0),
      I3 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN3,
      O => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2
    );
  SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_604 : X_AND4
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN1,
      I2 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN2,
      I3 => SHIFT_CNT(1),
      O => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3
    );
  SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_605 : X_AND6
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN1,
      I2 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN2,
      I3 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN3,
      I4 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN4,
      I5 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN5,
      O => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4
    );
  SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_606 : X_OR5
    port map (
      I0 => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0,
      I1 => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1,
      I2 => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2,
      I3 => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3,
      I4 => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4,
      O => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2
    );
  Msub_n0025_n00002_Msub_n0025_n00002_D2_UIM_607 : X_BUF
    port map (
      I => Msub_n0025_n00002_Msub_n0025_n00002_D2_Q,
      O => Msub_n0025_n00002_Msub_n0025_n00002_D2_UIM
    );
  Msub_n0025_n00002_Msub_n0025_n00002_D2_Q_608 : X_BUF
    port map (
      I => Msub_n0025_n00002_Msub_n0025_n00002_D2_D,
      O => Msub_n0025_n00002_Msub_n0025_n00002_D2_Q
    );
  Msub_n0025_n00002_Msub_n0025_n00002_D2_D_609 : X_XOR2
    port map (
      I0 => Msub_n0025_n00002_Msub_n0025_n00002_D2_D1,
      I1 => Msub_n0025_n00002_Msub_n0025_n00002_D2_D2,
      O => Msub_n0025_n00002_Msub_n0025_n00002_D2_D
    );
  Msub_n0025_n00002_Msub_n0025_n00002_D2_D1_610 : X_ZERO
    port map (
      O => Msub_n0025_n00002_Msub_n0025_n00002_D2_D1
    );
  Msub_n0025_n00002_Msub_n0025_n00002_D2_D2_611 : X_AND2
    port map (
      I0 => NlwInverterSignal_Msub_n0025_n00002_Msub_n0025_n00002_D2_D2_IN0,
      I1 => NlwInverterSignal_Msub_n0025_n00002_Msub_n0025_n00002_D2_D2_IN1,
      O => Msub_n0025_n00002_Msub_n0025_n00002_D2_D2
    );
  Q_OpTx_OpTx_FX_DC_18_INV_124_UIM_612 : X_BUF
    port map (
      I => Q_OpTx_OpTx_FX_DC_18_INV_124_Q,
      O => Q_OpTx_OpTx_FX_DC_18_INV_124_UIM
    );
  Q_OpTx_OpTx_FX_DC_18_INV_124_Q_613 : X_BUF
    port map (
      I => Q_OpTx_OpTx_FX_DC_18_INV_124_D,
      O => Q_OpTx_OpTx_FX_DC_18_INV_124_Q
    );
  Q_OpTx_OpTx_FX_DC_18_INV_124_D_614 : X_XOR2
    port map (
      I0 => Q_OpTx_OpTx_FX_DC_18_INV_124_D1,
      I1 => Q_OpTx_OpTx_FX_DC_18_INV_124_D2,
      O => Q_OpTx_OpTx_FX_DC_18_INV_124_D
    );
  Q_OpTx_OpTx_FX_DC_18_INV_124_D1_615 : X_ZERO
    port map (
      O => Q_OpTx_OpTx_FX_DC_18_INV_124_D1
    );
  Q_OpTx_OpTx_FX_DC_18_INV_124_D2_616 : X_AND2
    port map (
      I0 => SHIFT_CNT(0),
      I1 => SHIFT_CNT(1),
      O => Q_OpTx_OpTx_FX_DC_18_INV_124_D2
    );
  SHIFT_CNT_2_SHIFT_CNT_2_RSTF_UIM_617 : X_BUF
    port map (
      I => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_Q,
      O => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_UIM
    );
  SHIFT_CNT_2_SHIFT_CNT_2_RSTF_Q_618 : X_BUF
    port map (
      I => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D,
      O => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_Q
    );
  SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D_619 : X_XOR2
    port map (
      I0 => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D1,
      I1 => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2,
      O => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D
    );
  SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D1_620 : X_ZERO
    port map (
      O => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D1
    );
  SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_621 : X_AND5
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => SHIFT_CNT(0),
      I4 => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN4,
      O => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0
    );
  SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_622 : X_AND5
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => SHIFT_CNT(1),
      I4 => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN4,
      O => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1
    );
  SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_623 : X_AND6
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN3,
      I4 => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN4,
      I5 => SHIFT_CNT(2),
      O => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2
    );
  SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_624 : X_OR3
    port map (
      I0 => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0,
      I1 => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1,
      I2 => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2,
      O => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2
    );
  Q_OpTx_OpTx_FX_DC_23_INV_125_UIM_625 : X_BUF
    port map (
      I => Q_OpTx_OpTx_FX_DC_23_INV_125_Q,
      O => Q_OpTx_OpTx_FX_DC_23_INV_125_UIM
    );
  Q_OpTx_OpTx_FX_DC_23_INV_125_Q_626 : X_BUF
    port map (
      I => Q_OpTx_OpTx_FX_DC_23_INV_125_D,
      O => Q_OpTx_OpTx_FX_DC_23_INV_125_Q
    );
  Q_OpTx_OpTx_FX_DC_23_INV_125_D_627 : X_XOR2
    port map (
      I0 => Q_OpTx_OpTx_FX_DC_23_INV_125_D1,
      I1 => Q_OpTx_OpTx_FX_DC_23_INV_125_D2,
      O => Q_OpTx_OpTx_FX_DC_23_INV_125_D
    );
  Q_OpTx_OpTx_FX_DC_23_INV_125_D1_628 : X_ZERO
    port map (
      O => Q_OpTx_OpTx_FX_DC_23_INV_125_D1
    );
  Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0_629 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0_IN1,
      I2 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0_IN2,
      O => Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0
    );
  Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_630 : X_AND3
    port map (
      I0 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN0,
      I1 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN1,
      I2 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN2,
      O => Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1
    );
  Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_631 : X_AND7
    port map (
      I0 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN0,
      I1 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN1,
      I2 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN2,
      I3 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN3,
      I4 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN4,
      I5 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN5,
      I6 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN6,
      O => Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2
    );
  Q_OpTx_OpTx_FX_DC_23_INV_125_D2_632 : X_OR3
    port map (
      I0 => Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0,
      I1 => Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1,
      I2 => Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2,
      O => Q_OpTx_OpTx_FX_DC_23_INV_125_D2
    );
  SHIFT_CNT_3_SHIFT_CNT_3_RSTF_UIM_633 : X_BUF
    port map (
      I => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_Q,
      O => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_UIM
    );
  SHIFT_CNT_3_SHIFT_CNT_3_RSTF_Q_634 : X_BUF
    port map (
      I => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D,
      O => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_Q
    );
  SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D_635 : X_XOR2
    port map (
      I0 => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D1,
      I1 => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2,
      O => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D
    );
  SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D1_636 : X_ZERO
    port map (
      O => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D1
    );
  SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_637 : X_AND5
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => SHIFT_CNT(0),
      I4 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN4,
      O => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0
    );
  SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_638 : X_AND5
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => SHIFT_CNT(1),
      I4 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN4,
      O => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1
    );
  SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_639 : X_AND5
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => SHIFT_CNT(2),
      I4 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN4,
      O => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2
    );
  SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_640 : X_AND7
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN3,
      I4 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN4,
      I5 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN5,
      I6 => SHIFT_CNT(3),
      O => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3
    );
  SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_641 : X_OR4
    port map (
      I0 => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0,
      I1 => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1,
      I2 => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2,
      I3 => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3,
      O => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2
    );
  Msub_n0025_n00022_Msub_n0025_n00022_D2_UIM_642 : X_BUF
    port map (
      I => Msub_n0025_n00022_Msub_n0025_n00022_D2_Q,
      O => Msub_n0025_n00022_Msub_n0025_n00022_D2_UIM
    );
  Msub_n0025_n00022_Msub_n0025_n00022_D2_Q_643 : X_BUF
    port map (
      I => Msub_n0025_n00022_Msub_n0025_n00022_D2_D,
      O => Msub_n0025_n00022_Msub_n0025_n00022_D2_Q
    );
  Msub_n0025_n00022_Msub_n0025_n00022_D2_D_644 : X_XOR2
    port map (
      I0 => Msub_n0025_n00022_Msub_n0025_n00022_D2_D1,
      I1 => Msub_n0025_n00022_Msub_n0025_n00022_D2_D2,
      O => Msub_n0025_n00022_Msub_n0025_n00022_D2_D
    );
  Msub_n0025_n00022_Msub_n0025_n00022_D2_D1_645 : X_ZERO
    port map (
      O => Msub_n0025_n00022_Msub_n0025_n00022_D2_D1
    );
  Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_646 : X_AND4
    port map (
      I0 => NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN0,
      I1 => NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN1,
      I2 => NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN2,
      I3 => NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN3,
      O => Msub_n0025_n00022_Msub_n0025_n00022_D2_D2
    );
  Q_OpTx_FX_DC_20_UIM_647 : X_BUF
    port map (
      I => Q_OpTx_FX_DC_20_Q,
      O => Q_OpTx_FX_DC_20_UIM
    );
  Q_OpTx_FX_DC_20_Q_648 : X_BUF
    port map (
      I => Q_OpTx_FX_DC_20_D,
      O => Q_OpTx_FX_DC_20_Q
    );
  Q_OpTx_FX_DC_20_D_649 : X_XOR2
    port map (
      I0 => Q_OpTx_FX_DC_20_D1,
      I1 => Q_OpTx_FX_DC_20_D2,
      O => Q_OpTx_FX_DC_20_D
    );
  Q_OpTx_FX_DC_20_D1_650 : X_ZERO
    port map (
      O => Q_OpTx_FX_DC_20_D1
    );
  Q_OpTx_FX_DC_20_D2_PT_0_651 : X_AND2
    port map (
      I0 => NlwInverterSignal_OpTx_FX_DC_20_D2_PT_0_IN0,
      I1 => NlwInverterSignal_OpTx_FX_DC_20_D2_PT_0_IN1,
      O => Q_OpTx_FX_DC_20_D2_PT_0
    );
  Q_OpTx_FX_DC_20_D2_PT_1_652 : X_AND3
    port map (
      I0 => NlwInverterSignal_OpTx_FX_DC_20_D2_PT_1_IN0,
      I1 => NlwInverterSignal_OpTx_FX_DC_20_D2_PT_1_IN1,
      I2 => NlwInverterSignal_OpTx_FX_DC_20_D2_PT_1_IN2,
      O => Q_OpTx_FX_DC_20_D2_PT_1
    );
  Q_OpTx_FX_DC_20_D2_653 : X_OR2
    port map (
      I0 => Q_OpTx_FX_DC_20_D2_PT_0,
      I1 => Q_OpTx_FX_DC_20_D2_PT_1,
      O => Q_OpTx_FX_DC_20_D2
    );
  SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_UIM_654 : X_BUF
    port map (
      I => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_Q,
      O => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_UIM
    );
  SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_Q_655 : X_BUF
    port map (
      I => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D,
      O => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_Q
    );
  SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D_656 : X_XOR2
    port map (
      I0 => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D1,
      I1 => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2,
      O => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D
    );
  SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D1_657 : X_ZERO
    port map (
      O => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D1
    );
  SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0_658 : X_AND3
    port map (
      I0 => LOAD_IBUF,
      I1 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0_IN1,
      I2 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0_IN2,
      O => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0
    );
  SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_659 : X_AND3
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN1,
      I2 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN2,
      O => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1
    );
  SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_660 : X_AND3
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN1,
      I2 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN2,
      O => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2
    );
  SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_661 : X_AND6
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN1,
      I2 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN2,
      I3 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN3,
      I4 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN4,
      I5 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN5,
      O => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3
    );
  SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_662 : X_OR4
    port map (
      I0 => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0,
      I1 => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1,
      I2 => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2,
      I3 => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3,
      O => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2
    );
  Q_OpTx_FX_DC_21_UIM_663 : X_BUF
    port map (
      I => Q_OpTx_FX_DC_21_Q,
      O => Q_OpTx_FX_DC_21_UIM
    );
  Q_OpTx_FX_DC_21_Q_664 : X_BUF
    port map (
      I => Q_OpTx_FX_DC_21_D,
      O => Q_OpTx_FX_DC_21_Q
    );
  Q_OpTx_FX_DC_21_D_665 : X_XOR2
    port map (
      I0 => Q_OpTx_FX_DC_21_D1,
      I1 => Q_OpTx_FX_DC_21_D2,
      O => Q_OpTx_FX_DC_21_D
    );
  Q_OpTx_FX_DC_21_D1_666 : X_ZERO
    port map (
      O => Q_OpTx_FX_DC_21_D1
    );
  Q_OpTx_FX_DC_21_D2_PT_0_667 : X_AND2
    port map (
      I0 => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_0_IN0,
      I1 => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_0_IN1,
      O => Q_OpTx_FX_DC_21_D2_PT_0
    );
  Q_OpTx_FX_DC_21_D2_PT_1_668 : X_AND4
    port map (
      I0 => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN0,
      I1 => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN1,
      I2 => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN2,
      I3 => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN3,
      O => Q_OpTx_FX_DC_21_D2_PT_1
    );
  Q_OpTx_FX_DC_21_D2_669 : X_OR2
    port map (
      I0 => Q_OpTx_FX_DC_21_D2_PT_0,
      I1 => Q_OpTx_FX_DC_21_D2_PT_1,
      O => Q_OpTx_FX_DC_21_D2
    );
  Q_OpTx_OpTx_FX_SC_22_INV_126_UIM_670 : X_BUF
    port map (
      I => Q_OpTx_OpTx_FX_SC_22_INV_126_Q,
      O => Q_OpTx_OpTx_FX_SC_22_INV_126_UIM
    );
  Q_OpTx_OpTx_FX_SC_22_INV_126_Q_671 : X_BUF
    port map (
      I => Q_OpTx_OpTx_FX_SC_22_INV_126_D,
      O => Q_OpTx_OpTx_FX_SC_22_INV_126_Q
    );
  Q_OpTx_OpTx_FX_SC_22_INV_126_D_672 : X_XOR2
    port map (
      I0 => Q_OpTx_OpTx_FX_SC_22_INV_126_D1,
      I1 => Q_OpTx_OpTx_FX_SC_22_INV_126_D2,
      O => Q_OpTx_OpTx_FX_SC_22_INV_126_D
    );
  Q_OpTx_OpTx_FX_SC_22_INV_126_D1_673 : X_ZERO
    port map (
      O => Q_OpTx_OpTx_FX_SC_22_INV_126_D1
    );
  Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_0_674 : X_AND2
    port map (
      I0 => LOAD_IBUF,
      I1 => LOAD_IBUF,
      O => Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_0
    );
  Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_1_675 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => RES_IBUF,
      O => Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_1
    );
  Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2_676 : X_AND2
    port map (
      I0 => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2_IN0,
      I1 => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2_IN1,
      O => Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2
    );
  Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_677 : X_AND5
    port map (
      I0 => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN0,
      I1 => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN1,
      I2 => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN2,
      I3 => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN3,
      I4 => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN4,
      O => Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3
    );
  Q_OpTx_OpTx_FX_SC_22_INV_126_D2_678 : X_OR4
    port map (
      I0 => Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_0,
      I1 => Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_1,
      I2 => Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2,
      I3 => Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3,
      O => Q_OpTx_OpTx_FX_SC_22_INV_126_D2
    );
  EXP18_EXP_679 : X_BUF
    port map (
      I => EXP18_EXP_tsimrenamed_net_Q,
      O => EXP18_EXP
    );
  EXP18_EXP_PT_0_680 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP18_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP18_EXP_PT_0_IN1,
      I2 => NlwInverterSignal_EXP18_EXP_PT_0_IN2,
      I3 => NlwInverterSignal_EXP18_EXP_PT_0_IN3,
      I4 => NlwInverterSignal_EXP18_EXP_PT_0_IN4,
      I5 => NlwInverterSignal_EXP18_EXP_PT_0_IN5,
      I6 => count(5),
      O => EXP18_EXP_PT_0
    );
  EXP18_EXP_PT_1_681 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP18_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_EXP18_EXP_PT_1_IN1,
      I2 => NlwInverterSignal_EXP18_EXP_PT_1_IN2,
      I3 => NlwInverterSignal_EXP18_EXP_PT_1_IN3,
      I4 => NlwInverterSignal_EXP18_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_EXP18_EXP_PT_1_IN5,
      I6 => VCLK_PRESCALE_5_IBUF,
      O => EXP18_EXP_PT_1
    );
  EXP18_EXP_tsimrenamed_net_Q_682 : X_OR2
    port map (
      I0 => EXP18_EXP_PT_0,
      I1 => EXP18_EXP_PT_1,
      O => EXP18_EXP_tsimrenamed_net_Q
    );
  EXP19_EXP_683 : X_BUF
    port map (
      I => EXP19_EXP_tsimrenamed_net_Q,
      O => EXP19_EXP
    );
  EXP19_EXP_PT_0_684 : X_AND3
    port map (
      I0 => RES_IBUF,
      I1 => count(4),
      I2 => NlwInverterSignal_EXP19_EXP_PT_0_IN2,
      O => EXP19_EXP_PT_0
    );
  EXP19_EXP_PT_1_685 : X_AND3
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_EXP19_EXP_PT_1_IN1,
      I2 => VCLK_PRESCALE_4_IBUF,
      O => EXP19_EXP_PT_1
    );
  EXP19_EXP_PT_2_686 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP19_EXP_PT_2_IN0,
      I1 => NlwInverterSignal_EXP19_EXP_PT_2_IN1,
      I2 => count(4),
      I3 => NlwInverterSignal_EXP19_EXP_PT_2_IN3,
      I4 => NlwInverterSignal_EXP19_EXP_PT_2_IN4,
      I5 => NlwInverterSignal_EXP19_EXP_PT_2_IN5,
      O => EXP19_EXP_PT_2
    );
  EXP19_EXP_tsimrenamed_net_Q_687 : X_OR3
    port map (
      I0 => EXP19_EXP_PT_0,
      I1 => EXP19_EXP_PT_1,
      I2 => EXP19_EXP_PT_2,
      O => EXP19_EXP_tsimrenamed_net_Q
    );
  EXP20_EXP_688 : X_BUF
    port map (
      I => EXP20_EXP_tsimrenamed_net_Q,
      O => EXP20_EXP
    );
  EXP20_EXP_PT_0_689 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP20_EXP_PT_0_IN0,
      I1 => count(1),
      I2 => NlwInverterSignal_EXP20_EXP_PT_0_IN2,
      O => EXP20_EXP_PT_0
    );
  EXP20_EXP_PT_1_690 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP20_EXP_PT_1_IN0,
      I1 => count(2),
      I2 => NlwInverterSignal_EXP20_EXP_PT_1_IN2,
      O => EXP20_EXP_PT_1
    );
  EXP20_EXP_PT_2_691 : X_AND4
    port map (
      I0 => NlwInverterSignal_EXP20_EXP_PT_2_IN0,
      I1 => NlwInverterSignal_EXP20_EXP_PT_2_IN1,
      I2 => NlwInverterSignal_EXP20_EXP_PT_2_IN2,
      I3 => NlwInverterSignal_EXP20_EXP_PT_2_IN3,
      O => EXP20_EXP_PT_2
    );
  EXP20_EXP_PT_3_692 : X_AND5
    port map (
      I0 => NlwInverterSignal_EXP20_EXP_PT_3_IN0,
      I1 => NlwInverterSignal_EXP20_EXP_PT_3_IN1,
      I2 => NlwInverterSignal_EXP20_EXP_PT_3_IN2,
      I3 => NlwInverterSignal_EXP20_EXP_PT_3_IN3,
      I4 => count(3),
      O => EXP20_EXP_PT_3
    );
  EXP20_EXP_tsimrenamed_net_Q_693 : X_OR4
    port map (
      I0 => EXP20_EXP_PT_0,
      I1 => EXP20_EXP_PT_1,
      I2 => EXP20_EXP_PT_2,
      I3 => EXP20_EXP_PT_3,
      O => EXP20_EXP_tsimrenamed_net_Q
    );
  NlwInverterBlock_REG_31_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_31_RSTF,
      O => NlwInverterSignal_REG_31_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_31_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_31_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_31_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_31_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_31_D2_PT_0_IN4 : X_INV
    port map (
      I => REG(30),
      O => NlwInverterSignal_REG_31_D2_PT_0_IN4
    );
  NlwInverterBlock_REG_31_D2_PT_0_IN5 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_31_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_31_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_31_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_31_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_31_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_31_D2_PT_1_IN2 : X_INV
    port map (
      I => REG(31),
      O => NlwInverterSignal_REG_31_D2_PT_1_IN2
    );
  NlwInverterBlock_REG_31_D2_PT_1_IN5 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_31_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_31_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_31_CLKF_IN0
    );
  NlwInverterBlock_REG_31_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_31_CLKF_IN1
    );
  NlwInverterBlock_REG_31_RSTF_IN1 : X_INV
    port map (
      I => DIN_31_IBUF,
      O => NlwInverterSignal_REG_31_RSTF_IN1
    );
  NlwInverterBlock_SHIFT_EN_D2_IN0 : X_INV
    port map (
      I => DONE_IBUF,
      O => NlwInverterSignal_SHIFT_EN_D2_IN0
    );
  NlwInverterBlock_SHIFT_EN_D2_IN1 : X_INV
    port map (
      I => DONE_IBUF,
      O => NlwInverterSignal_SHIFT_EN_D2_IN1
    );
  NlwInverterBlock_SHIFT_EN_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_SHIFT_EN_CLKF_IN0
    );
  NlwInverterBlock_SHIFT_EN_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_SHIFT_EN_CLKF_IN1
    );
  NlwInverterBlock_SHIFT_EN_CE_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_EN_CE_IN0
    );
  NlwInverterBlock_SHIFT_EN_CE_IN1 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_EN_CE_IN1
    );
  NlwInverterBlock_count_0_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => count_0_RSTF,
      O => NlwInverterSignal_count_0_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_count_0_D_IN0 : X_INV
    port map (
      I => count_0_D1,
      O => NlwInverterSignal_count_0_D_IN0
    );
  NlwInverterBlock_count_0_D2_PT_0_IN1 : X_INV
    port map (
      I => VCLK_PRESCALE_0_IBUF,
      O => NlwInverterSignal_count_0_D2_PT_0_IN1
    );
  NlwInverterBlock_count_0_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_count_0_D2_PT_1_IN0
    );
  NlwInverterBlock_count_0_D2_PT_2_IN0 : X_INV
    port map (
      I => VCLK_PRESCALE_0_IBUF,
      O => NlwInverterSignal_count_0_D2_PT_2_IN0
    );
  NlwInverterBlock_count_0_D2_PT_2_IN1 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_count_0_D2_PT_2_IN1
    );
  NlwInverterBlock_count_0_D2_PT_2_IN2 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_0_D2_PT_2_IN2
    );
  NlwInverterBlock_count_0_D2_PT_2_IN3 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_0_D2_PT_2_IN3
    );
  NlwInverterBlock_count_0_D2_PT_2_IN4 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_count_0_D2_PT_2_IN4
    );
  NlwInverterBlock_count_0_D2_PT_2_IN5 : X_INV
    port map (
      I => count(5),
      O => NlwInverterSignal_count_0_D2_PT_2_IN5
    );
  NlwInverterBlock_count_0_RSTF_IN1 : X_INV
    port map (
      I => VCLK_PRESCALE_0_IBUF,
      O => NlwInverterSignal_count_0_RSTF_IN1
    );
  NlwInverterBlock_count_4_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => count_4_RSTF,
      O => NlwInverterSignal_count_4_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_count_4_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_count_4_D2_PT_1_IN0
    );
  NlwInverterBlock_count_4_D2_PT_1_IN1 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_count_4_D2_PT_1_IN1
    );
  NlwInverterBlock_count_4_D2_PT_1_IN2 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_4_D2_PT_1_IN2
    );
  NlwInverterBlock_count_4_D2_PT_1_IN3 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_4_D2_PT_1_IN3
    );
  NlwInverterBlock_count_4_D2_PT_1_IN4 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_count_4_D2_PT_1_IN4
    );
  NlwInverterBlock_count_4_D2_PT_2_IN0 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_count_4_D2_PT_2_IN0
    );
  NlwInverterBlock_count_4_D2_PT_2_IN1 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_count_4_D2_PT_2_IN1
    );
  NlwInverterBlock_count_4_D2_PT_2_IN2 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_4_D2_PT_2_IN2
    );
  NlwInverterBlock_count_4_D2_PT_2_IN3 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_4_D2_PT_2_IN3
    );
  NlwInverterBlock_count_4_D2_PT_2_IN4 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_count_4_D2_PT_2_IN4
    );
  NlwInverterBlock_count_4_RSTF_IN1 : X_INV
    port map (
      I => VCLK_PRESCALE_4_IBUF,
      O => NlwInverterSignal_count_4_RSTF_IN1
    );
  NlwInverterBlock_count_4_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_count_4_EXP_tsimrenamed_net_IN1 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN1
    );
  NlwInverterBlock_count_4_EXP_tsimrenamed_net_IN2 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN2
    );
  NlwInverterBlock_count_1_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => count_1_RSTF,
      O => NlwInverterSignal_count_1_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_count_1_D_IN0 : X_INV
    port map (
      I => count_1_D1,
      O => NlwInverterSignal_count_1_D_IN0
    );
  NlwInverterBlock_count_1_D2_PT_1_IN1 : X_INV
    port map (
      I => VCLK_PRESCALE_1_IBUF,
      O => NlwInverterSignal_count_1_D2_PT_1_IN1
    );
  NlwInverterBlock_count_1_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_count_1_D2_PT_2_IN0
    );
  NlwInverterBlock_count_1_D2_PT_2_IN2 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_1_D2_PT_2_IN2
    );
  NlwInverterBlock_count_1_D2_PT_3_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_count_1_D2_PT_3_IN0
    );
  NlwInverterBlock_count_1_D2_PT_3_IN1 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_count_1_D2_PT_3_IN1
    );
  NlwInverterBlock_count_1_RSTF_IN1 : X_INV
    port map (
      I => VCLK_PRESCALE_1_IBUF,
      O => NlwInverterSignal_count_1_RSTF_IN1
    );
  NlwInverterBlock_count_2_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => count_2_RSTF,
      O => NlwInverterSignal_count_2_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_count_2_D_IN0 : X_INV
    port map (
      I => count_2_D1,
      O => NlwInverterSignal_count_2_D_IN0
    );
  NlwInverterBlock_count_2_D2_PT_2_IN1 : X_INV
    port map (
      I => VCLK_PRESCALE_2_IBUF,
      O => NlwInverterSignal_count_2_D2_PT_2_IN1
    );
  NlwInverterBlock_count_2_D2_PT_3_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_count_2_D2_PT_3_IN0
    );
  NlwInverterBlock_count_2_D2_PT_3_IN2 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_2_D2_PT_3_IN2
    );
  NlwInverterBlock_count_2_D2_PT_4_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_count_2_D2_PT_4_IN0
    );
  NlwInverterBlock_count_2_D2_PT_4_IN2 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_2_D2_PT_4_IN2
    );
  NlwInverterBlock_count_2_RSTF_IN1 : X_INV
    port map (
      I => VCLK_PRESCALE_2_IBUF,
      O => NlwInverterSignal_count_2_RSTF_IN1
    );
  NlwInverterBlock_count_3_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => count_3_RSTF,
      O => NlwInverterSignal_count_3_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_count_3_D_IN0 : X_INV
    port map (
      I => count_3_D1,
      O => NlwInverterSignal_count_3_D_IN0
    );
  NlwInverterBlock_count_3_D2_PT_1_IN1 : X_INV
    port map (
      I => VCLK_PRESCALE_3_IBUF,
      O => NlwInverterSignal_count_3_D2_PT_1_IN1
    );
  NlwInverterBlock_count_3_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_count_3_D2_PT_2_IN0
    );
  NlwInverterBlock_count_3_D2_PT_2_IN2 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_count_3_D2_PT_2_IN2
    );
  NlwInverterBlock_count_3_RSTF_IN1 : X_INV
    port map (
      I => VCLK_PRESCALE_3_IBUF,
      O => NlwInverterSignal_count_3_RSTF_IN1
    );
  NlwInverterBlock_count_3_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_count_3_EXP_tsimrenamed_net_IN1 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN1
    );
  NlwInverterBlock_count_3_EXP_tsimrenamed_net_IN2 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN2
    );
  NlwInverterBlock_count_3_EXP_tsimrenamed_net_IN3 : X_INV
    port map (
      I => count(5),
      O => NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN3
    );
  NlwInverterBlock_count_3_EXP_tsimrenamed_net_IN4 : X_INV
    port map (
      I => VCLK_PRESCALE_2_IBUF,
      O => NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN4
    );
  NlwInverterBlock_REG_0_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_RSTF,
      O => NlwInverterSignal_REG_0_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_D2_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_0_D2_IN0
    );
  NlwInverterBlock_REG_0_D2_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_D2_IN1
    );
  NlwInverterBlock_REG_0_D2_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_0_D2_IN3
    );
  NlwInverterBlock_REG_0_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_CLKF_IN0
    );
  NlwInverterBlock_REG_0_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_CLKF_IN1
    );
  NlwInverterBlock_REG_0_RSTF_IN2 : X_INV
    port map (
      I => DIN_0_IBUF,
      O => NlwInverterSignal_REG_0_RSTF_IN2
    );
  NlwInverterBlock_REG_10_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_10_RSTF,
      O => NlwInverterSignal_REG_10_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_10_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_10_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_10_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_10_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_10_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_10_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_10_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(9),
      O => NlwInverterSignal_REG_10_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_10_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_10_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_10_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_10_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_10_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_10_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_10_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(10),
      O => NlwInverterSignal_REG_10_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_10_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_10_CLKF_IN0
    );
  NlwInverterBlock_REG_10_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_10_CLKF_IN1
    );
  NlwInverterBlock_REG_10_RSTF_IN2 : X_INV
    port map (
      I => DIN_10_IBUF,
      O => NlwInverterSignal_REG_10_RSTF_IN2
    );
  NlwInverterBlock_REG_11_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_11_RSTF,
      O => NlwInverterSignal_REG_11_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_11_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_11_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_11_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_11_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_11_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_11_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_11_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(11),
      O => NlwInverterSignal_REG_11_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_11_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_11_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_11_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_11_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_11_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_11_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_11_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(10),
      O => NlwInverterSignal_REG_11_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_11_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_11_CLKF_IN0
    );
  NlwInverterBlock_REG_11_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_11_CLKF_IN1
    );
  NlwInverterBlock_REG_11_RSTF_IN2 : X_INV
    port map (
      I => DIN_11_IBUF,
      O => NlwInverterSignal_REG_11_RSTF_IN2
    );
  NlwInverterBlock_REG_12_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_12_RSTF,
      O => NlwInverterSignal_REG_12_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_12_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_12_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_12_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_12_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_12_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_12_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_12_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(12),
      O => NlwInverterSignal_REG_12_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_12_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_12_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_12_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_12_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_12_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_12_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_12_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(11),
      O => NlwInverterSignal_REG_12_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_12_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_12_CLKF_IN0
    );
  NlwInverterBlock_REG_12_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_12_CLKF_IN1
    );
  NlwInverterBlock_REG_12_RSTF_IN2 : X_INV
    port map (
      I => DIN_12_IBUF,
      O => NlwInverterSignal_REG_12_RSTF_IN2
    );
  NlwInverterBlock_REG_13_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_13_RSTF,
      O => NlwInverterSignal_REG_13_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_13_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_13_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_13_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_13_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_13_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_13_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_13_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(13),
      O => NlwInverterSignal_REG_13_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_13_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_13_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_13_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_13_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_13_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_13_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_13_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(12),
      O => NlwInverterSignal_REG_13_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_13_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_13_CLKF_IN0
    );
  NlwInverterBlock_REG_13_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_13_CLKF_IN1
    );
  NlwInverterBlock_REG_13_RSTF_IN2 : X_INV
    port map (
      I => DIN_13_IBUF,
      O => NlwInverterSignal_REG_13_RSTF_IN2
    );
  NlwInverterBlock_REG_14_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_14_RSTF,
      O => NlwInverterSignal_REG_14_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_14_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_14_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_14_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_14_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_14_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_14_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_14_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(14),
      O => NlwInverterSignal_REG_14_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_14_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_14_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_14_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_14_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_14_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_14_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_14_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(13),
      O => NlwInverterSignal_REG_14_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_14_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_14_CLKF_IN0
    );
  NlwInverterBlock_REG_14_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_14_CLKF_IN1
    );
  NlwInverterBlock_REG_14_RSTF_IN2 : X_INV
    port map (
      I => DIN_14_IBUF,
      O => NlwInverterSignal_REG_14_RSTF_IN2
    );
  NlwInverterBlock_REG_15_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_15_RSTF,
      O => NlwInverterSignal_REG_15_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_15_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_15_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_15_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_15_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_15_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_15_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_15_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(15),
      O => NlwInverterSignal_REG_15_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_15_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_15_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_15_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_15_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_15_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_15_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_15_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(14),
      O => NlwInverterSignal_REG_15_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_15_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_15_CLKF_IN0
    );
  NlwInverterBlock_REG_15_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_15_CLKF_IN1
    );
  NlwInverterBlock_REG_15_RSTF_IN2 : X_INV
    port map (
      I => DIN_15_IBUF,
      O => NlwInverterSignal_REG_15_RSTF_IN2
    );
  NlwInverterBlock_REG_16_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_16_RSTF,
      O => NlwInverterSignal_REG_16_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_16_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_16_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_16_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_16_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_16_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_16_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_16_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(16),
      O => NlwInverterSignal_REG_16_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_16_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_16_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_16_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_16_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_16_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_16_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_16_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(15),
      O => NlwInverterSignal_REG_16_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_16_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_16_CLKF_IN0
    );
  NlwInverterBlock_REG_16_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_16_CLKF_IN1
    );
  NlwInverterBlock_REG_16_RSTF_IN2 : X_INV
    port map (
      I => DIN_16_IBUF,
      O => NlwInverterSignal_REG_16_RSTF_IN2
    );
  NlwInverterBlock_REG_17_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_17_RSTF,
      O => NlwInverterSignal_REG_17_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_17_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_17_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_17_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_17_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_17_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_17_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_17_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(17),
      O => NlwInverterSignal_REG_17_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_17_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_17_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_17_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_17_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_17_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_17_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_17_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(16),
      O => NlwInverterSignal_REG_17_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_17_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_17_CLKF_IN0
    );
  NlwInverterBlock_REG_17_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_17_CLKF_IN1
    );
  NlwInverterBlock_REG_17_RSTF_IN2 : X_INV
    port map (
      I => DIN_17_IBUF,
      O => NlwInverterSignal_REG_17_RSTF_IN2
    );
  NlwInverterBlock_REG_18_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_18_RSTF,
      O => NlwInverterSignal_REG_18_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_18_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_18_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_18_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_18_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_18_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_18_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_18_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(18),
      O => NlwInverterSignal_REG_18_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_18_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_18_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_18_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_18_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_18_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_18_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_18_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(17),
      O => NlwInverterSignal_REG_18_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_18_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_18_CLKF_IN0
    );
  NlwInverterBlock_REG_18_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_18_CLKF_IN1
    );
  NlwInverterBlock_REG_18_RSTF_IN2 : X_INV
    port map (
      I => DIN_18_IBUF,
      O => NlwInverterSignal_REG_18_RSTF_IN2
    );
  NlwInverterBlock_REG_19_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_19_RSTF,
      O => NlwInverterSignal_REG_19_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_19_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_19_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_19_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_19_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_19_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_19_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_19_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(19),
      O => NlwInverterSignal_REG_19_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_19_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_19_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_19_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_19_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_19_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_19_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_19_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(18),
      O => NlwInverterSignal_REG_19_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_19_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_19_CLKF_IN0
    );
  NlwInverterBlock_REG_19_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_19_CLKF_IN1
    );
  NlwInverterBlock_REG_19_RSTF_IN2 : X_INV
    port map (
      I => DIN_19_IBUF,
      O => NlwInverterSignal_REG_19_RSTF_IN2
    );
  NlwInverterBlock_REG_1_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_RSTF,
      O => NlwInverterSignal_REG_1_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_1_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_1_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_1_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_1_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_1_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(1),
      O => NlwInverterSignal_REG_1_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_1_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_1_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_1_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_1_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(0),
      O => NlwInverterSignal_REG_1_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_1_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_CLKF_IN0
    );
  NlwInverterBlock_REG_1_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_CLKF_IN1
    );
  NlwInverterBlock_REG_1_RSTF_IN2 : X_INV
    port map (
      I => DIN_1_IBUF,
      O => NlwInverterSignal_REG_1_RSTF_IN2
    );
  NlwInverterBlock_REG_20_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_20_RSTF,
      O => NlwInverterSignal_REG_20_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_20_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_20_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_20_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_20_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_20_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_20_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_20_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(20),
      O => NlwInverterSignal_REG_20_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_20_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_20_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_20_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_20_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_20_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_20_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_20_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(19),
      O => NlwInverterSignal_REG_20_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_20_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_20_CLKF_IN0
    );
  NlwInverterBlock_REG_20_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_20_CLKF_IN1
    );
  NlwInverterBlock_REG_20_RSTF_IN2 : X_INV
    port map (
      I => DIN_20_IBUF,
      O => NlwInverterSignal_REG_20_RSTF_IN2
    );
  NlwInverterBlock_REG_21_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_21_RSTF,
      O => NlwInverterSignal_REG_21_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_21_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_21_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_21_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_21_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_21_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_21_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_21_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(21),
      O => NlwInverterSignal_REG_21_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_21_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_21_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_21_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_21_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_21_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_21_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_21_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(20),
      O => NlwInverterSignal_REG_21_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_21_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_21_CLKF_IN0
    );
  NlwInverterBlock_REG_21_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_21_CLKF_IN1
    );
  NlwInverterBlock_REG_21_RSTF_IN2 : X_INV
    port map (
      I => DIN_21_IBUF,
      O => NlwInverterSignal_REG_21_RSTF_IN2
    );
  NlwInverterBlock_REG_22_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_22_RSTF,
      O => NlwInverterSignal_REG_22_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_22_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_22_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_22_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_22_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_22_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_22_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_22_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(22),
      O => NlwInverterSignal_REG_22_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_22_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_22_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_22_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_22_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_22_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_22_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_22_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(21),
      O => NlwInverterSignal_REG_22_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_22_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_22_CLKF_IN0
    );
  NlwInverterBlock_REG_22_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_22_CLKF_IN1
    );
  NlwInverterBlock_REG_22_RSTF_IN2 : X_INV
    port map (
      I => DIN_22_IBUF,
      O => NlwInverterSignal_REG_22_RSTF_IN2
    );
  NlwInverterBlock_REG_23_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_23_RSTF,
      O => NlwInverterSignal_REG_23_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_23_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_23_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_23_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_23_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_23_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_23_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_23_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(23),
      O => NlwInverterSignal_REG_23_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_23_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_23_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_23_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_23_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_23_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_23_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_23_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(22),
      O => NlwInverterSignal_REG_23_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_23_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_23_CLKF_IN0
    );
  NlwInverterBlock_REG_23_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_23_CLKF_IN1
    );
  NlwInverterBlock_REG_23_RSTF_IN2 : X_INV
    port map (
      I => DIN_23_IBUF,
      O => NlwInverterSignal_REG_23_RSTF_IN2
    );
  NlwInverterBlock_REG_24_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_24_RSTF,
      O => NlwInverterSignal_REG_24_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_24_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_24_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_24_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_24_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_24_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_24_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_24_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(24),
      O => NlwInverterSignal_REG_24_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_24_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_24_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_24_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_24_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_24_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_24_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_24_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(23),
      O => NlwInverterSignal_REG_24_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_24_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_24_CLKF_IN0
    );
  NlwInverterBlock_REG_24_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_24_CLKF_IN1
    );
  NlwInverterBlock_REG_24_RSTF_IN2 : X_INV
    port map (
      I => DIN_24_IBUF,
      O => NlwInverterSignal_REG_24_RSTF_IN2
    );
  NlwInverterBlock_REG_25_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_25_RSTF,
      O => NlwInverterSignal_REG_25_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_25_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_25_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_25_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_25_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_25_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_25_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_25_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(25),
      O => NlwInverterSignal_REG_25_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_25_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_25_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_25_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_25_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_25_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_25_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_25_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(24),
      O => NlwInverterSignal_REG_25_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_25_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_25_CLKF_IN0
    );
  NlwInverterBlock_REG_25_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_25_CLKF_IN1
    );
  NlwInverterBlock_REG_25_RSTF_IN2 : X_INV
    port map (
      I => DIN_25_IBUF,
      O => NlwInverterSignal_REG_25_RSTF_IN2
    );
  NlwInverterBlock_REG_26_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_26_RSTF,
      O => NlwInverterSignal_REG_26_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_26_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_26_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_26_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_26_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_26_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_26_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_26_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(26),
      O => NlwInverterSignal_REG_26_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_26_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_26_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_26_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_26_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_26_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_26_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_26_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(25),
      O => NlwInverterSignal_REG_26_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_26_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_26_CLKF_IN0
    );
  NlwInverterBlock_REG_26_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_26_CLKF_IN1
    );
  NlwInverterBlock_REG_26_RSTF_IN2 : X_INV
    port map (
      I => DIN_26_IBUF,
      O => NlwInverterSignal_REG_26_RSTF_IN2
    );
  NlwInverterBlock_REG_27_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_27_RSTF,
      O => NlwInverterSignal_REG_27_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_27_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_27_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_27_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_27_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_27_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_27_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_27_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(27),
      O => NlwInverterSignal_REG_27_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_27_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_27_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_27_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_27_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_27_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_27_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_27_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(26),
      O => NlwInverterSignal_REG_27_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_27_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_27_CLKF_IN0
    );
  NlwInverterBlock_REG_27_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_27_CLKF_IN1
    );
  NlwInverterBlock_REG_27_RSTF_IN2 : X_INV
    port map (
      I => DIN_27_IBUF,
      O => NlwInverterSignal_REG_27_RSTF_IN2
    );
  NlwInverterBlock_REG_28_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_28_RSTF,
      O => NlwInverterSignal_REG_28_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_28_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_28_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_28_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_28_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_28_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_28_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_28_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(28),
      O => NlwInverterSignal_REG_28_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_28_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_28_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_28_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_28_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_28_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_28_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_28_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(27),
      O => NlwInverterSignal_REG_28_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_28_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_28_CLKF_IN0
    );
  NlwInverterBlock_REG_28_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_28_CLKF_IN1
    );
  NlwInverterBlock_REG_28_RSTF_IN2 : X_INV
    port map (
      I => DIN_28_IBUF,
      O => NlwInverterSignal_REG_28_RSTF_IN2
    );
  NlwInverterBlock_REG_29_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_29_RSTF,
      O => NlwInverterSignal_REG_29_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_29_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_29_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_29_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_29_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_29_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_29_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_29_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(29),
      O => NlwInverterSignal_REG_29_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_29_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_29_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_29_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_29_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_29_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_29_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_29_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(28),
      O => NlwInverterSignal_REG_29_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_29_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_29_CLKF_IN0
    );
  NlwInverterBlock_REG_29_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_29_CLKF_IN1
    );
  NlwInverterBlock_REG_29_RSTF_IN2 : X_INV
    port map (
      I => DIN_29_IBUF,
      O => NlwInverterSignal_REG_29_RSTF_IN2
    );
  NlwInverterBlock_REG_2_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_2_RSTF,
      O => NlwInverterSignal_REG_2_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_2_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_2_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_2_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_2_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_2_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_2_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_2_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(2),
      O => NlwInverterSignal_REG_2_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_2_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_2_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_2_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_2_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_2_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_2_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_2_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(1),
      O => NlwInverterSignal_REG_2_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_2_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_2_CLKF_IN0
    );
  NlwInverterBlock_REG_2_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_2_CLKF_IN1
    );
  NlwInverterBlock_REG_2_RSTF_IN2 : X_INV
    port map (
      I => DIN_2_IBUF,
      O => NlwInverterSignal_REG_2_RSTF_IN2
    );
  NlwInverterBlock_REG_30_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_30_RSTF,
      O => NlwInverterSignal_REG_30_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_30_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_30_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_30_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_30_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_30_D2_PT_0_IN4 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_30_D2_PT_0_IN4
    );
  NlwInverterBlock_REG_30_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(29),
      O => NlwInverterSignal_REG_30_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_30_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_30_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_30_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_30_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_30_D2_PT_1_IN3 : X_INV
    port map (
      I => REG(30),
      O => NlwInverterSignal_REG_30_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_30_D2_PT_1_IN4 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_30_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_30_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_30_CLKF_IN0
    );
  NlwInverterBlock_REG_30_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_30_CLKF_IN1
    );
  NlwInverterBlock_REG_30_RSTF_IN2 : X_INV
    port map (
      I => DIN_30_IBUF,
      O => NlwInverterSignal_REG_30_RSTF_IN2
    );
  NlwInverterBlock_REG_3_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_3_RSTF,
      O => NlwInverterSignal_REG_3_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_3_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_3_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_3_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_3_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_3_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_3_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_3_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(3),
      O => NlwInverterSignal_REG_3_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_3_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_3_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_3_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_3_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_3_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_3_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_3_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(2),
      O => NlwInverterSignal_REG_3_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_3_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_3_CLKF_IN0
    );
  NlwInverterBlock_REG_3_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_3_CLKF_IN1
    );
  NlwInverterBlock_REG_3_RSTF_IN2 : X_INV
    port map (
      I => DIN_3_IBUF,
      O => NlwInverterSignal_REG_3_RSTF_IN2
    );
  NlwInverterBlock_REG_4_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_4_RSTF,
      O => NlwInverterSignal_REG_4_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_4_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_4_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_4_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_4_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_4_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_4_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_4_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(4),
      O => NlwInverterSignal_REG_4_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_4_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_4_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_4_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_4_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_4_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_4_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_4_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(3),
      O => NlwInverterSignal_REG_4_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_4_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_4_CLKF_IN0
    );
  NlwInverterBlock_REG_4_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_4_CLKF_IN1
    );
  NlwInverterBlock_REG_4_RSTF_IN2 : X_INV
    port map (
      I => DIN_4_IBUF,
      O => NlwInverterSignal_REG_4_RSTF_IN2
    );
  NlwInverterBlock_REG_5_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_5_RSTF,
      O => NlwInverterSignal_REG_5_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_5_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_5_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_5_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_5_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_5_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_5_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_5_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(5),
      O => NlwInverterSignal_REG_5_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_5_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_5_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_5_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_5_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_5_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_5_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_5_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(4),
      O => NlwInverterSignal_REG_5_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_5_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_5_CLKF_IN0
    );
  NlwInverterBlock_REG_5_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_5_CLKF_IN1
    );
  NlwInverterBlock_REG_5_RSTF_IN2 : X_INV
    port map (
      I => DIN_5_IBUF,
      O => NlwInverterSignal_REG_5_RSTF_IN2
    );
  NlwInverterBlock_REG_6_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_6_RSTF,
      O => NlwInverterSignal_REG_6_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_6_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_6_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_6_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_6_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_6_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_6_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_6_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(6),
      O => NlwInverterSignal_REG_6_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_6_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_6_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_6_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_6_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_6_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_6_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_6_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(5),
      O => NlwInverterSignal_REG_6_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_6_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_6_CLKF_IN0
    );
  NlwInverterBlock_REG_6_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_6_CLKF_IN1
    );
  NlwInverterBlock_REG_6_RSTF_IN2 : X_INV
    port map (
      I => DIN_6_IBUF,
      O => NlwInverterSignal_REG_6_RSTF_IN2
    );
  NlwInverterBlock_REG_7_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_7_RSTF,
      O => NlwInverterSignal_REG_7_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_7_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_7_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_7_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_7_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_7_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_7_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_7_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(7),
      O => NlwInverterSignal_REG_7_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_7_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_7_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_7_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_7_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_7_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_7_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_7_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(6),
      O => NlwInverterSignal_REG_7_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_7_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_7_CLKF_IN0
    );
  NlwInverterBlock_REG_7_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_7_CLKF_IN1
    );
  NlwInverterBlock_REG_7_RSTF_IN2 : X_INV
    port map (
      I => DIN_7_IBUF,
      O => NlwInverterSignal_REG_7_RSTF_IN2
    );
  NlwInverterBlock_REG_8_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_8_RSTF,
      O => NlwInverterSignal_REG_8_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_8_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_8_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_8_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_8_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_8_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_8_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_8_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(8),
      O => NlwInverterSignal_REG_8_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_8_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_8_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_8_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_8_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_8_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_8_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_8_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(7),
      O => NlwInverterSignal_REG_8_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_8_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_8_CLKF_IN0
    );
  NlwInverterBlock_REG_8_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_8_CLKF_IN1
    );
  NlwInverterBlock_REG_8_RSTF_IN2 : X_INV
    port map (
      I => DIN_8_IBUF,
      O => NlwInverterSignal_REG_8_RSTF_IN2
    );
  NlwInverterBlock_REG_9_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_9_RSTF,
      O => NlwInverterSignal_REG_9_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_9_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_9_D2_PT_0_IN0
    );
  NlwInverterBlock_REG_9_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_9_D2_PT_0_IN1
    );
  NlwInverterBlock_REG_9_D2_PT_0_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_9_D2_PT_0_IN3
    );
  NlwInverterBlock_REG_9_D2_PT_0_IN5 : X_INV
    port map (
      I => REG(8),
      O => NlwInverterSignal_REG_9_D2_PT_0_IN5
    );
  NlwInverterBlock_REG_9_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_REG_9_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_9_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_9_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_9_D2_PT_1_IN3 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_REG_9_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_9_D2_PT_1_IN4 : X_INV
    port map (
      I => REG(9),
      O => NlwInverterSignal_REG_9_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_9_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_9_CLKF_IN0
    );
  NlwInverterBlock_REG_9_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_9_CLKF_IN1
    );
  NlwInverterBlock_REG_9_RSTF_IN2 : X_INV
    port map (
      I => DIN_9_IBUF,
      O => NlwInverterSignal_REG_9_RSTF_IN2
    );
  NlwInverterBlock_count_5_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => count_5_RSTF,
      O => NlwInverterSignal_count_5_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_count_5_D2_PT_1_IN2 : X_INV
    port map (
      I => VCLK_PRESCALE_5_IBUF,
      O => NlwInverterSignal_count_5_D2_PT_1_IN2
    );
  NlwInverterBlock_count_5_D2_PT_2_IN1 : X_INV
    port map (
      I => count(5),
      O => NlwInverterSignal_count_5_D2_PT_2_IN1
    );
  NlwInverterBlock_count_5_RSTF_IN1 : X_INV
    port map (
      I => VCLK_PRESCALE_5_IBUF,
      O => NlwInverterSignal_count_5_RSTF_IN1
    );
  NlwInverterBlock_count_5_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_count_5_EXP_tsimrenamed_net_IN1 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN1
    );
  NlwInverterBlock_count_5_EXP_tsimrenamed_net_IN2 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN2
    );
  NlwInverterBlock_count_5_EXP_tsimrenamed_net_IN3 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN3
    );
  NlwInverterBlock_count_5_EXP_tsimrenamed_net_IN4 : X_INV
    port map (
      I => count(5),
      O => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN4
    );
  NlwInverterBlock_count_5_EXP_tsimrenamed_net_IN5 : X_INV
    port map (
      I => VCLK_PRESCALE_1_IBUF,
      O => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN5
    );
  NlwInverterBlock_SREG_IS_EMPTY_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => SREG_IS_EMPTY_RSTF,
      O => NlwInverterSignal_SREG_IS_EMPTY_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_SREG_IS_EMPTY_RSTF_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SREG_IS_EMPTY_RSTF_IN1
    );
  NlwInverterBlock_SHIFT_CNT_0_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => SHIFT_CNT_0_RSTF,
      O => NlwInverterSignal_SHIFT_CNT_0_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_SHIFT_CNT_0_SETF_IN0 : X_INV
    port map (
      I => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_UIM,
      O => NlwInverterSignal_SHIFT_CNT_0_SETF_IN0
    );
  NlwInverterBlock_SHIFT_CNT_0_SETF_IN1 : X_INV
    port map (
      I => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_UIM,
      O => NlwInverterSignal_SHIFT_CNT_0_SETF_IN1
    );
  NlwInverterBlock_SHIFT_CNT_0_RSTF_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_0_RSTF_IN0
    );
  NlwInverterBlock_SHIFT_CNT_0_RSTF_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_0_RSTF_IN1
    );
  NlwInverterBlock_SHIFT_CNT_1_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => SHIFT_CNT_1_RSTF,
      O => NlwInverterSignal_SHIFT_CNT_1_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_SHIFT_CNT_1_SETF_IN0 : X_INV
    port map (
      I => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_UIM,
      O => NlwInverterSignal_SHIFT_CNT_1_SETF_IN0
    );
  NlwInverterBlock_SHIFT_CNT_1_SETF_IN1 : X_INV
    port map (
      I => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_UIM,
      O => NlwInverterSignal_SHIFT_CNT_1_SETF_IN1
    );
  NlwInverterBlock_SHIFT_CNT_1_RSTF_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_1_RSTF_IN0
    );
  NlwInverterBlock_SHIFT_CNT_1_RSTF_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_1_RSTF_IN1
    );
  NlwInverterBlock_SHIFT_CNT_1_RSTF_IN3 : X_INV
    port map (
      I => Msub_n0025_n00002_Msub_n0025_n00002_D2_UIM,
      O => NlwInverterSignal_SHIFT_CNT_1_RSTF_IN3
    );
  NlwInverterBlock_SHIFT_CNT_1_RSTF_IN4 : X_INV
    port map (
      I => Q_OpTx_OpTx_FX_DC_18_INV_124_UIM,
      O => NlwInverterSignal_SHIFT_CNT_1_RSTF_IN4
    );
  NlwInverterBlock_SHIFT_CNT_2_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => SHIFT_CNT_2_RSTF,
      O => NlwInverterSignal_SHIFT_CNT_2_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_SHIFT_CNT_2_SETF_IN0 : X_INV
    port map (
      I => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_UIM,
      O => NlwInverterSignal_SHIFT_CNT_2_SETF_IN0
    );
  NlwInverterBlock_SHIFT_CNT_2_SETF_IN1 : X_INV
    port map (
      I => Q_OpTx_OpTx_FX_DC_23_INV_125_UIM,
      O => NlwInverterSignal_SHIFT_CNT_2_SETF_IN1
    );
  NlwInverterBlock_SHIFT_CNT_3_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => SHIFT_CNT_3_RSTF,
      O => NlwInverterSignal_SHIFT_CNT_3_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_SHIFT_CNT_3_SETF_IN0 : X_INV
    port map (
      I => Q_OpTx_OpTx_FX_DC_23_INV_125_UIM,
      O => NlwInverterSignal_SHIFT_CNT_3_SETF_IN0
    );
  NlwInverterBlock_SHIFT_CNT_3_SETF_IN1 : X_INV
    port map (
      I => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_UIM,
      O => NlwInverterSignal_SHIFT_CNT_3_SETF_IN1
    );
  NlwInverterBlock_SHIFT_CNT_3_RSTF_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_3_RSTF_IN0
    );
  NlwInverterBlock_SHIFT_CNT_3_RSTF_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_3_RSTF_IN1
    );
  NlwInverterBlock_SHIFT_CNT_3_RSTF_IN3 : X_INV
    port map (
      I => Msub_n0025_n00022_Msub_n0025_n00022_D2_UIM,
      O => NlwInverterSignal_SHIFT_CNT_3_RSTF_IN3
    );
  NlwInverterBlock_SHIFT_CNT_4_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => SHIFT_CNT_4_RSTF,
      O => NlwInverterSignal_SHIFT_CNT_4_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_SHIFT_CNT_4_SETF_IN0 : X_INV
    port map (
      I => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_UIM,
      O => NlwInverterSignal_SHIFT_CNT_4_SETF_IN0
    );
  NlwInverterBlock_SHIFT_CNT_4_SETF_IN1 : X_INV
    port map (
      I => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_UIM,
      O => NlwInverterSignal_SHIFT_CNT_4_SETF_IN1
    );
  NlwInverterBlock_SHIFT_CNT_4_RSTF_IN1 : X_INV
    port map (
      I => Q_OpTx_OpTx_FX_SC_22_INV_126_UIM,
      O => NlwInverterSignal_SHIFT_CNT_4_RSTF_IN1
    );
  NlwInverterBlock_VCLK_OBUF_CE_IN0 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_VCLK_OBUF_CE_IN0
    );
  NlwInverterBlock_VCLK_OBUF_CE_IN1 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_VCLK_OBUF_CE_IN1
    );
  NlwInverterBlock_VCLK_OBUF_CE_IN2 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_VCLK_OBUF_CE_IN2
    );
  NlwInverterBlock_VCLK_OBUF_CE_IN3 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_VCLK_OBUF_CE_IN3
    );
  NlwInverterBlock_VCLK_OBUF_CE_IN4 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_VCLK_OBUF_CE_IN4
    );
  NlwInverterBlock_VCLK_OBUF_CE_IN5 : X_INV
    port map (
      I => count(5),
      O => NlwInverterSignal_VCLK_OBUF_CE_IN5
    );
  NlwInverterBlock_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN0
    );
  NlwInverterBlock_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN2 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN2
    );
  NlwInverterBlock_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN3 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN3
    );
  NlwInverterBlock_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN4 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN4
    );
  NlwInverterBlock_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN5 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN5
    );
  NlwInverterBlock_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN6 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN6
    );
  NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0_IN1
    );
  NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0_IN2 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0_IN2
    );
  NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN0
    );
  NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN1
    );
  NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN2 : X_INV
    port map (
      I => SHIFT_EN,
      O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN2
    );
  NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2_IN0
    );
  NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2_IN1
    );
  NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN0
    );
  NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN1
    );
  NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN2 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN2
    );
  NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN3 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN3
    );
  NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN4 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN4
    );
  NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN5 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN5
    );
  NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0_IN1
    );
  NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0_IN2 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0_IN2
    );
  NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN0
    );
  NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN1
    );
  NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN2 : X_INV
    port map (
      I => SHIFT_EN,
      O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN2
    );
  NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN0
    );
  NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN1
    );
  NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN3 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN3
    );
  NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN0
    );
  NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN1
    );
  NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN2 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN2
    );
  NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN0
    );
  NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN1
    );
  NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN2 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN2
    );
  NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN3 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN3
    );
  NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN4 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN4
    );
  NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN5 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN5
    );
  NlwInverterBlock_Msub_n0025_n00002_Msub_n0025_n00002_D2_D2_IN0 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_Msub_n0025_n00002_Msub_n0025_n00002_D2_D2_IN0
    );
  NlwInverterBlock_Msub_n0025_n00002_Msub_n0025_n00002_D2_D2_IN1 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_Msub_n0025_n00002_Msub_n0025_n00002_D2_D2_IN1
    );
  NlwInverterBlock_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN0
    );
  NlwInverterBlock_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN1
    );
  NlwInverterBlock_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN4 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN4
    );
  NlwInverterBlock_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN0
    );
  NlwInverterBlock_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN1
    );
  NlwInverterBlock_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN4 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN4
    );
  NlwInverterBlock_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN0
    );
  NlwInverterBlock_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN1
    );
  NlwInverterBlock_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN3 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN3
    );
  NlwInverterBlock_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN4 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN4
    );
  NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0_IN1
    );
  NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0_IN2 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0_IN2
    );
  NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN0
    );
  NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN1
    );
  NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN2 : X_INV
    port map (
      I => SHIFT_EN,
      O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN2
    );
  NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN0
    );
  NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN1
    );
  NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN2 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN2
    );
  NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN3 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN3
    );
  NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN4 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN4
    );
  NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN5 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN5
    );
  NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN6 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN6
    );
  NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN0
    );
  NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN1
    );
  NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN4 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN4
    );
  NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN0
    );
  NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN1
    );
  NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN4 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN4
    );
  NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN0
    );
  NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN1
    );
  NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN4 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN4
    );
  NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN0
    );
  NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN1
    );
  NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN3 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN3
    );
  NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN4 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN4
    );
  NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN5 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN5
    );
  NlwInverterBlock_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN0 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN0
    );
  NlwInverterBlock_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN1 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN1
    );
  NlwInverterBlock_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN2 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN2
    );
  NlwInverterBlock_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN3 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN3
    );
  NlwInverterBlock_OpTx_FX_DC_20_D2_PT_0_IN0 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_OpTx_FX_DC_20_D2_PT_0_IN0
    );
  NlwInverterBlock_OpTx_FX_DC_20_D2_PT_0_IN1 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_OpTx_FX_DC_20_D2_PT_0_IN1
    );
  NlwInverterBlock_OpTx_FX_DC_20_D2_PT_1_IN0 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_OpTx_FX_DC_20_D2_PT_1_IN0
    );
  NlwInverterBlock_OpTx_FX_DC_20_D2_PT_1_IN1 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_OpTx_FX_DC_20_D2_PT_1_IN1
    );
  NlwInverterBlock_OpTx_FX_DC_20_D2_PT_1_IN2 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_OpTx_FX_DC_20_D2_PT_1_IN2
    );
  NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0_IN1
    );
  NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0_IN2 : X_INV
    port map (
      I => SREG_IS_EMPTY,
      O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0_IN2
    );
  NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN0
    );
  NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN1
    );
  NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN2 : X_INV
    port map (
      I => SHIFT_EN,
      O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN2
    );
  NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN0
    );
  NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN1
    );
  NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN2 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN2
    );
  NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN0 : X_INV
    port map (
      I => LOAD_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN0
    );
  NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN1 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN1
    );
  NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN2 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN2
    );
  NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN3 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN3
    );
  NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN4 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN4
    );
  NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN5 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN5
    );
  NlwInverterBlock_OpTx_FX_DC_21_D2_PT_0_IN0 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_0_IN0
    );
  NlwInverterBlock_OpTx_FX_DC_21_D2_PT_0_IN1 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_0_IN1
    );
  NlwInverterBlock_OpTx_FX_DC_21_D2_PT_1_IN0 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN0
    );
  NlwInverterBlock_OpTx_FX_DC_21_D2_PT_1_IN1 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN1
    );
  NlwInverterBlock_OpTx_FX_DC_21_D2_PT_1_IN2 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN2
    );
  NlwInverterBlock_OpTx_FX_DC_21_D2_PT_1_IN3 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN3
    );
  NlwInverterBlock_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2_IN0 : X_INV
    port map (
      I => SHIFT_EN,
      O => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2_IN0
    );
  NlwInverterBlock_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2_IN1 : X_INV
    port map (
      I => SHIFT_EN,
      O => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2_IN1
    );
  NlwInverterBlock_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN0 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN0
    );
  NlwInverterBlock_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN1 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN1
    );
  NlwInverterBlock_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN2 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN2
    );
  NlwInverterBlock_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN3 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN3
    );
  NlwInverterBlock_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN4 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN4
    );
  NlwInverterBlock_EXP18_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP18_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP18_EXP_PT_0_IN1 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_EXP18_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP18_EXP_PT_0_IN2 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_EXP18_EXP_PT_0_IN2
    );
  NlwInverterBlock_EXP18_EXP_PT_0_IN3 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_EXP18_EXP_PT_0_IN3
    );
  NlwInverterBlock_EXP18_EXP_PT_0_IN4 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_EXP18_EXP_PT_0_IN4
    );
  NlwInverterBlock_EXP18_EXP_PT_0_IN5 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_EXP18_EXP_PT_0_IN5
    );
  NlwInverterBlock_EXP18_EXP_PT_1_IN0 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_EXP18_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP18_EXP_PT_1_IN1 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_EXP18_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP18_EXP_PT_1_IN2 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_EXP18_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP18_EXP_PT_1_IN3 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_EXP18_EXP_PT_1_IN3
    );
  NlwInverterBlock_EXP18_EXP_PT_1_IN4 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_EXP18_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP18_EXP_PT_1_IN5 : X_INV
    port map (
      I => count(5),
      O => NlwInverterSignal_EXP18_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP19_EXP_PT_0_IN2 : X_INV
    port map (
      I => VCLK_PRESCALE_4_IBUF,
      O => NlwInverterSignal_EXP19_EXP_PT_0_IN2
    );
  NlwInverterBlock_EXP19_EXP_PT_1_IN1 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_EXP19_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP19_EXP_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP19_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP19_EXP_PT_2_IN1 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_EXP19_EXP_PT_2_IN1
    );
  NlwInverterBlock_EXP19_EXP_PT_2_IN3 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_EXP19_EXP_PT_2_IN3
    );
  NlwInverterBlock_EXP19_EXP_PT_2_IN4 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_EXP19_EXP_PT_2_IN4
    );
  NlwInverterBlock_EXP19_EXP_PT_2_IN5 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_EXP19_EXP_PT_2_IN5
    );
  NlwInverterBlock_EXP20_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP20_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP20_EXP_PT_0_IN2 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_EXP20_EXP_PT_0_IN2
    );
  NlwInverterBlock_EXP20_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP20_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP20_EXP_PT_1_IN2 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_EXP20_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP20_EXP_PT_2_IN0 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_EXP20_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP20_EXP_PT_2_IN1 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_EXP20_EXP_PT_2_IN1
    );
  NlwInverterBlock_EXP20_EXP_PT_2_IN2 : X_INV
    port map (
      I => count(5),
      O => NlwInverterSignal_EXP20_EXP_PT_2_IN2
    );
  NlwInverterBlock_EXP20_EXP_PT_2_IN3 : X_INV
    port map (
      I => VCLK_PRESCALE_3_IBUF,
      O => NlwInverterSignal_EXP20_EXP_PT_2_IN3
    );
  NlwInverterBlock_EXP20_EXP_PT_3_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP20_EXP_PT_3_IN0
    );
  NlwInverterBlock_EXP20_EXP_PT_3_IN1 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_EXP20_EXP_PT_3_IN1
    );
  NlwInverterBlock_EXP20_EXP_PT_3_IN2 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_EXP20_EXP_PT_3_IN2
    );
  NlwInverterBlock_EXP20_EXP_PT_3_IN3 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_EXP20_EXP_PT_3_IN3
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => PRLD);

end Structure;

