-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read

-- Copyright (C) 2007 J. Ahrensfeld

-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.

-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-- Lesser General Public License for more details.

-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA

-- For questions and ideas, please contact the author at jens@jayfield.org

-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w2r1c_sim.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
-----------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity dpram_1w2r1c is
	Generic 
	(
		addr_width : integer := 3;
		data_width : integer := 8
	);
	Port
	(
		clk			: in  STD_LOGIC;
		en_a		: in  STD_LOGIC;
		en_b		: in  STD_LOGIC;
		we_a		: in  STD_LOGIC;
		addr_a		: in  unsigned (addr_width-1 downto 0);
		addr_b		: in  unsigned (addr_width-1 downto 0);
		din_a		: in  unsigned (data_width-1 downto 0);
		dout_a		: out unsigned (data_width-1 downto 0);
		dout_b		: out unsigned (data_width-1 downto 0)
	);
end dpram_1w2r1c;

architecture Behavioral of dpram_1w2r1c is

	constant depth : integer := 2**addr_width;
	signal addr_a_r : unsigned (addr_width-1 downto 0);
	signal addr_b_r : unsigned (addr_width-1 downto 0);
	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
	signal RAM : RAMtype;
	
begin

	dout_a <= RAM(to_integer(addr_a_r));
	dout_b <= RAM(to_integer(addr_b_r));

process (clk)
begin
if clk'event and clk = '1' then
	if en_a = '1' then
		if we_a = '1' then
			RAM(to_integer(addr_a)) <= din_a;
		end if;
		addr_a_r	<= addr_a;
	end if;
end if;
end process;

process (clk)
begin
if clk'event and clk = '1' then
	if en_b = '1' then
		addr_b_r	<= addr_b;
	end if;
end if;
end process;

end Behavioral;

