vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
vhdl work "../../src/sdram_config.vhd"
vhdl work "../../../../lib/misc/utils_pkg.vhd"
vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
vhdl work "../../../../lib/uart/kcuart_tx.vhd"
vhdl work "../../../../lib/uart/kcuart_rx.vhd"
vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/dpram.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
vhdl work "../../../../lib/FIFO/src/async_fifo_ctrl.vhd"
vhdl work "../../src/sys_types.vhd"
vhdl work "../../src/ram_ld.vhd"
vhdl work "../../src/bootloader.ROM_ld.vhd"
vhdl work "../../../../lib/uart/uart_tx.vhd"
vhdl work "../../../../lib/uart/uart_rx.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
vhdl work "../../../../lib/uart/uart_wb.vhd"
vhdl work "../../../../lib/misc/rom_wb.vhd"
vhdl work "../../../../lib/misc/ram_wb.vhd"
vhdl work "../../../../lib/misc/lcd_port.vhd"
vhdl work "../../../../lib/misc/gpio_wb.vhd"
vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
vhdl work "../../../../lib/misc/async_port_wb.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
vhdl work "../../src/mips_sys.vhd"
