mips/src/libsys/cop0.c

/*
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 * and open the template in the editor.
 */

#include "cop0.h"

// ---------------------------------------------------------------------------------
// MIPS specific
// ---------------------------------------------------------------------------------
uint32_t CP0_SR_read(void)
{
	uint32_t result;

	__asm__
	(
		"mfc0   %[val], $12\n"
		: [val] "=r" (result)
	);

	return result;
}

void CP0_SR_write(uint32_t val)
{
	__asm__
	(
		"mtc0   %[val], $12\n"
		: /* no output */
		: [val] "r" (val)
	);
}

uint32_t CP0_CR_read(void)
{
	uint32_t result;

	__asm__
	(
		"mfc0   %[val], $13\n"
		: [val] "=r" (result)
	);

	return result;
}

void CP0_CR_write(uint32_t val)
{
	__asm__
	(
		"mtc0   %[val], $13\n"
		:
		: [val] "r" (val)
	);
}

uint32_t CP0_TR_read(void)
{
	uint32_t result;

	__asm__
	(
		"mfc0   %[val], $31\n"
		: [val] "=r" (result)
	);

	return result;
}

void CP0_TR_write(uint32_t val)
{
	__asm__
	(
		"mtc0   %[val], $31\n"
		:
		: [val] "r" (val)
	);
}

uint32_t CP0_PRID_read(void)
{
	uint32_t result;

	__asm__
	(
		"mfc0   %[val], $15\n"
		: [val] "=r" (result)
	);

	return result;
}

void CP0_TR_write_ptr(uint32_t* pPtr)
{
	__asm__
	(
		"swc0   $31, 0(%[pPtr])\n"
		:
		: [pPtr] "r" (pPtr)
	);
}

void CP0_TR_read_ptr(uint32_t* pPtr)
{
	__asm__
	(
		"lwc0   $31, 0(%[pPtr])\n"
		:
		: [pPtr] "r" (pPtr)
	);
}

void ICACHE_invalidate_all(void)
{
	__asm__
	(
		"cop0	32\n"
	);
}

void ICACHE_invalidate_at(uint32_t* pPtr)
{
	__asm__
	(
		"mtc0   %[pPtr], $31\n"
		"cop0	33\n"
		:
		: [pPtr] "r" (pPtr)
	);
}

void DCACHE_invalidate_all(void)
{
	__asm__
	(
		"cop0	34\n"
	);
}

void DCACHE_invalidate_at(uint32_t* pPtr)
{
	__asm__
	(
		"mtc0   %[pPtr], $31\n"
		"cop0	35\n"
		"nop"				// fix needed: don't work without nop on de-nano
		:
		: [pPtr] "r" (pPtr)
	);
}