mips/src/bootloader/test.c

#include "libsys_boot.h"

#define ARRAY_SIZE(a)	(sizeof(a)/sizeof(*a))
#define SDRAM_SIZE		(256)

void uart_isr(void)
{
	volatile uint32_t *pUART0_stat = (uint32_t*)SYS_UART_STAT;
	volatile uint32_t *pUART0_data = (uint32_t*)SYS_UART_DATA;

	while(0x200 & *pUART0_stat)
	{
		char data = (char)*pUART0_data;
		sputs(&data);
	}
}

void timer_isr(void)
{
	static uint8_t led = 0;

	volatile uint32_t *pTim_stat = (uint32_t*)SYS_ITIM_STAT;
	volatile uint32_t *pTim_ctrl = (uint32_t*)SYS_ITIM_CTRL;
	volatile uint32_t *pGPIO = (uint32_t*)SYS_GPIO_0_DATA;

	if (*pTim_stat & 1)
	{
		*pGPIO = led;
		led = (led+1) % 64;

		*pTim_stat = 1;	// Acknowledge IRQ
		*pTim_ctrl |= 1;
	}
}

void main()
{
	uint32_t i, j, k;
	uint32_t data;
	volatile uint32_t *pUART0_stat = (uint32_t*)SYS_UART_STAT;
	volatile uint32_t *pGPIODIR = (uint32_t*)SYS_GPIO_0_DIR;
	volatile uint32_t pSDRAM32[SDRAM_SIZE/4];
	volatile uint16_t *pSDRAM16 = (uint16_t*)pSDRAM32;
	volatile uint8_t *pSDRAM8 = (uint8_t*)pSDRAM32;
	volatile uint32_t *pFlashMem = (uint32_t*)FLASH_BASE_MEM + 0x100000/4;

	volatile uint32_t *pTim_ctrl = (uint32_t*)SYS_ITIM_CTRL;
	volatile uint32_t *pTim_stat = (uint32_t*)SYS_ITIM_STAT;
	volatile uint32_t *pTim0_cnt = (uint32_t*)SYS_ITIM0_CNT;
	volatile uint32_t *pTim0_cmp = (uint32_t*)SYS_ITIM0_CMP;
	volatile uint32_t *pSpiXferSize = (uint32_t*)SYS_SPI_XFER_SIZE;
	volatile uint32_t *pSpiDataSize = (uint32_t*)SYS_SPI_DATA_SIZE;
	volatile uint32_t *pSpiData = (uint32_t*)SYS_SPI_DATA;
	volatile uint32_t *pSpiStat = (uint32_t*)SYS_SPI_STAT;
	volatile uint32_t *pSpiCtrl = (uint32_t*)SYS_SPI_CTRL;
	*pTim0_cnt = 0;
	*pTim0_cmp = 2500000;	// 50 ms @ 50 Mhz
	*pTim_stat = (1 << 0);
	*pTim_ctrl = (3 << 0);
	
	uint32_t test_pattern [] = 
	{
		0x00000000,
		0xFFFFFFFF,
		0x55555555,
		0xAAAAAAAA,
		0x000000FF,
		0x0000FF00,
		0x00FF0000,
		0xFF000000
	};
	
	CP0_SR_write(0x0060000D);
	*pGPIODIR = GPIO_0_DFLT_DIR;

	interrupt_init();
	interrupt_register(3, (void*)uart_isr);
	interrupt_register(2, (void*)timer_isr);
	interrupt_enable(2);
	interrupt_enable(3);

	// UART: enable RX interrupt
	*pUART0_stat |= (1 << 6);

	sputs("Hello, world!\n");

	k = 0;
	while(1)
	{
		sputs("Iteration # ");print_word(k);sputs("\n");
#if 0
		// SPI Bit rate
		// fsys / (2*(1+div))
		*pSpiCtrl       = (*pSpiCtrl & 0xFFFFFF00) | 0;

		sputs("Test SPI\n");
		*pSpiData		= 0x9F000000;
		*pSpiDataSize	= 8;
		*pSpiXferSize	= 8+648;
		*pSpiStat		= SPI_STAT_COMMIT;

		sputs("SYS_SPI_XFER_SIZE : ");print_word(*pSpiXferSize);sputs("\n");
		sputs("SYS_SPI_DATA_SIZE : ");print_word(*pSpiDataSize);sputs("\n");
		sputs("SYS_SPI_CTRL      : ");print_word(*pSpiCtrl);sputs("\n");
		sputs("SYS_SPI_STAT      : ");print_word(*pSpiStat);sputs("\n");

		while(!(*pSpiStat & SPI_STAT_DOUTRDY))
		{
		}
		
		do
		{
			print_word(*pSpiData);sputs("\n");
		} while (*pSpiStat & SPI_STAT_DOUTRDY);
		
		sputs("SPI: Read at 0x100000\n");
		*pSpiData		= 0x03100000;
		*pSpiDataSize	= 32;
		*pSpiXferSize	= 32+8*256;
		*pSpiStat		= SPI_STAT_COMMIT;

		while(!(*pSpiStat & SPI_STAT_DOUTRDY))
		{
		}
		
		do
		{
			print_word(*pSpiData);sputs("\n");
		} while (*pSpiStat & SPI_STAT_DOUTRDY);

#endif
		
		sputs("Testing SDRAM (pattern)\n");
		for (j=0; j < ARRAY_SIZE(test_pattern); j++)
		{
			for (i=0; i < SDRAM_SIZE/4; i++)
			{
				pSDRAM32[i] = test_pattern[j];
			}
			DCACHE_invalidate_all();
			for (i=0; i < SDRAM_SIZE/4; i++)
			{
				data = pSDRAM32[i];
				if (data != test_pattern[j])
				{
					sputs("\n");
					sputs("Pattern "); print_word(test_pattern[j]); sputs("\n");
					sputs("Error at address "); print_word(i); sputs("\n");
					sputs("Read "); print_word(data); sputs("\n");
					break;
				}
			}
			sputs(".");
		}
		sputs("\n");

		sputs("Reading SPI Flash\n");
		DCACHE_invalidate_all();
		memdump((uint8_t*)pFlashMem, 0, 16, 512);
		sputs("\n");
		sputs("Size "); print_word(*(pFlashMem+3)); sputs("\n");
		
		sputs("Testing SDRAM (32-bit write)\n");
		data = 0x00010203;
		for (i=0; i < 256/4; i++)
		{
			pSDRAM32[i] = data;
			data += 0x04040404;
		}
		DCACHE_invalidate_all();
		memdump((uint8_t*)pSDRAM32, 0, 16, 256);
		sputs("\n");

		sputs("Testing SDRAM (16-bit write)\n");
		data = 0x0001;
		for (i=0; i < 256/2; i++)
		{
			pSDRAM16[i] = data;
			data += 0x0202;
		}
		DCACHE_invalidate_all();
		memdump((uint8_t*)pSDRAM16, 0, 16, 256);
		sputs("\n");
		
		sputs("Testing SDRAM (8-bit write)\n");
		data = 0x00;
		for (i=0; i < 256; i++)
		{
			pSDRAM8[i] = data;
			data += 0x01;
		}
		DCACHE_invalidate_all();
		memdump((uint8_t*)pSDRAM8, 0, 16, 256);
		sputs("\n");
		
		k++;
	}
}