jens
cf233c4d81
- bootloader added board file - refactored header files - constify constants git-svn-id: http://moon:8086/svn/mips@99 a8ebac50-d88d-4704-bea3-6648445a41b3
386 lines
13 KiB
C
386 lines
13 KiB
C
#ifndef HPI_H
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#define HPI_H
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#include <irq.h>
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// ---------------------------------------------------------
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// API related
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// ---------------------------------------------------------
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//#define IS_ERROR(e) (0 != (e & HPI_ERROR))
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#define HPI_NOERROR 0
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#define HPI_ERROR 0x80000000
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#define HPI_ERR_NOTIMPL (HPI_ERROR + 1)
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#define HPI_ERR_INVPARAM (HPI_ERROR + 2)
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#define HPI_ERR_TIMEOUT (HPI_ERROR + 3)
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#define HPI_ERR_PREFIX_MBX (HPI_ERROR + 0x00010000)
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#define MAX_NUM_REGS 14
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#define R0 0
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#define R1 1
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#define R2 2
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#define R3 3
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#define R4 4
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#define R5 5
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#define R6 6
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#define R7 7
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#define R8 8
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#define R9 9
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#define R10 10
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#define R11 11
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#define R12 12
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#define R13 13
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#define USB_MAX_NUM_PORTS 2
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#define USB_MAX_NUM_EPT 8
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#define USB_MAX_IMG_SIZE 512
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#define USB_IRP_BASE 0x0F80
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#define USB_IMG_BASE 0x1000
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typedef void (*fp_t)(void*);
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// Receive buffer on EP
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typedef struct _scy_req_t
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{
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uint16_t next;
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uint16_t addr;
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uint16_t size;
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uint16_t callback;
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} cy_req_t;
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typedef struct _sfifo_t
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{
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uint32_t size;
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uint8_t *pBuf;
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uint8_t * volatile pPtr_wr, * volatile pPtr_rd;
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} fifo_t;
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typedef struct _susb_irp_t
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{
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uint16_t tsize;
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uint32_t is_in, is_out;
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uint32_t port, ept;
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uint16_t cy_irp_addr;
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fifo_t fifo;
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uint32_t tx_in_progress;
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cy_req_t cy_req;
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} usb_irp_t;
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// ---------------------------------------------------------
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// CY7C67300 related
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// ---------------------------------------------------------
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#define HPI_WAITACK 1
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#define HPI_NOWAIT 0
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// ---------------------------------------------------------
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// HPI status flags
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#define HPI_STATUS_MBX_IN 0x0001
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#define HPI_STATUS_RESET1 0x0002
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#define HPI_STATUS_DONE1 0x0004
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#define HPI_STATUS_DONE2 0x0008
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#define HPI_STATUS_SIEMSG1 0x0010
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#define HPI_STATUS_SIEMSG2 0x0020
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#define HPI_STATUS_RESUME1 0x0040
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#define HPI_STATUS_RESUME2 0x0080
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#define HPI_STATUS_MBX_OUT 0x0100
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#define HPI_STATUS_RESET2 0x0200
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#define HPI_STATUS_SOFEOP1 0x0400
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#define HPI_STATUS_SOFEOP2 0x1000
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#define HPI_STATUS_ID 0x4000
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#define HPI_STATUS_VBUS 0x8000
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// ---------------------------------------------------------
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// LCP command codes
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#define COMM_RESET 0xFA50
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#define COMM_JUMP2CODE 0xCE00
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#define COMM_EXEC_INT 0xCE01
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#define COMM_READ_CTRL_REG 0xCE02
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#define COMM_WRITE_CTRL_REG 0xCE03
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#define COMM_CALL_CODE 0xCE04
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#define COMM_READ_XMEM 0xCE05
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#define COMM_WRITE_XMEM 0xCE06
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#define C0MM_CONFIG 0xCE07
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#define COMM_READ_MEM 0xCE08
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#define COMM_WRITE_MEM 0xCE09
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// LCP response codes
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#define COMM_ACK 0x0FED
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#define COMM_NAK 0xDEAD
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#define COMM_ASYNC 0xF00D
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// ---------------------------------------------------------
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// LCP memory addresses
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#define COMM_PORT_CMD 0x01BA // For PORT Command
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#define COMM_MEM_ADDR 0x01BC // Address for COMM_RD/WR_MEM
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#define COMM_MEM_LEN 0x01BE // Address for COMM_RD/WR_MEM
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#define COMM_LAST_DATA 0x01C0 // memory pointer for xmem
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#define COMM_CTRL_REG_ADDR 0x01BC // Address for COMM_RD/WR_CTRL_REG
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#define COMM_CTRL_REG_DATA 0x01BE // Address for COMM_RD/WR_CTRL_REG
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#define COMM_CTRL_REG_LOGIC 0x01C0 // Address used for AND/OR
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#define REG_WRITE_FLG 0x0000 // Value for COMM_CTRL_REG_LOGIC
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#define REG_AND_FLG 0x0001 // Value for COMM_CTRL_REG_LOGIC
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#define REG_OR_FLG 0x0002 // Value for COMM_CTRL_REG_LOGIC
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#define COMM_TIMEOUT 0x01BE // Address setting Timeout for sending response to host
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#define COMM_CODE_ADDR 0x01BC // Address for COMM_CALL_CODE and COMM_JUMP2CODE
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#define COMM_INT_NUM 0x01C2 // Address used for COMM_EXEC_INT
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#define COMM_R0 0x01C4 // CY16-R0 register
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#define COMM_R1 0x01C6 // CY16-R1 register
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#define COMM_R2 0x01C8 // CY16-R2 register
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#define COMM_R3 0x01CA // CY16-R3 register
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#define COMM_R4 0x01CC // CY16-R4 register
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#define COMM_R5 0x01CE // CY16-R5 register
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#define COMM_R6 0x01D0 // CY16-R6 register
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#define COMM_R7 0x01D2 // CY16-R7 register
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#define COMM_R8 0x01D4 // CY16-R8 register
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#define COMM_R9 0x01D6 // CY16-R9 register
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#define COMM_R10 0x01D8 // CY16-R10 register
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#define COMM_R11 0x01DA // CY16-R11 register
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#define COMM_R12 0x01DC // CY16-R12 register
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#define COMM_R13 0x01DE // CY16-R13 register
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// for COMM_CTRL_REG_LOGIC
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#define LOGIC_DIRECT 0
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#define LOGIC_AND 1
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#define LOGIC_OR 2
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// ---------------------------------------------------------
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// Software interrupts
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#define SUSB_INIT_INT 113
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// USB 1
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#define SUSB1_DEVICE_DESCRIPTOR_VEC 90
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#define SUSB1_CONFIGURATION_DESCRIPTOR_VEC 91
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#define SUSB1_STRING_DESCRIPTOR_VEC 92
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#define SUSB1_FINISH_INT 89
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#define SUSB1_STALL_INT 82
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#define SUSB1_STANDARD_INT 83
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#define SUSB1_SEND_INT 80
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#define SUSB1_RECEIVE_INT 81
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#define SUSB1_VENDOR_INT 85
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#define SUSB1_CLASS_INT 87
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#define SUSB1_LOADER_INT 94
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#define SUSB1_DELTA_CONFIG_INT 95
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// USB 2
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#define SUSB2_DEVICE_DESCRIPTOR_VEC 106
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#define SUSB2_CONFIGURATION_DESCRIPTOR_VEC 107
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#define SUSB2_STRING_DESCRIPTOR_VEC 108
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#define SUSB2_FINISH_INT 105
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#define SUSB2_STALL_INT 98
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#define SUSB2_STANDARD_INT 99
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#define SUSB2_SEND_INT 96
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#define SUSB2_RECEIVE_INT 97
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#define SUSB2_VENDOR_INT 101
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#define SUSB2_CLASS_INT 103
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#define SUSB2_LOADER_INT 110
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#define SUSB2_DELTA_CONFIG_INT 111
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// ---------------------------------------------------------
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// General USB Registers
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#define USB_REG_FLAGS 0xC000 // CPU Flags
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#define USB_REG_BANK 0xC002 // Register Bank
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#define USB_REG_REVISON 0xC004 // Hardware Revision
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#define USB_REG_SPEED 0xC008 // CPU Speed
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#define USB_REG_PWRCTRL 0xC00A // Power Control
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#define USB_REG_INTEN 0xC00E // Interrupt Enable
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#define USB_REG_BP 0xC014 // Breakpoint
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#define USB_REG_USBDIAG 0xC03C // USB Diagnostic
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#define USB_REG_MEMDIAG 0xC03E // Memory Diagnostic
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// HPI registers
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#define HPI_REG_BP 0x0140 // HPI Breakpoint
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#define HPI_REG_INTROUTE 0x0142 // Interrupt Routing
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#define HPI_REG_SIE1MSG 0x0144 // SIE1msg
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#define HPI_REG_SIE2MSG 0x0148 // SIE2msg
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#define HPI_REG_MAILBOX 0xC0C6 // HPI Mailbox
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// ---------------------------------------------------------
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// General Device Registers
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// Device 1
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#define SUSB1_REG_PORTSEL 0xC084 // Port select
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#define SUSB1_REG_USBCTRL 0xC08A // USB control
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#define SUSB1_REG_INTEN 0xC08C // Interrupt enable
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#define SUSB1_REG_ADDR 0xC08E // Address
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#define SUSB1_REG_STATUS 0xC090 // Status
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#define SUSB1_REG_FRAMENUM 0xC092 // Frame number
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#define SUSB1_REG_SOFEOPCNT 0xC094 // SOF/EOP count
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// Device 2
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#define SUSB2_REG_PORTSEL 0xC0A4 // Port select
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#define SUSB2_REG_USBCTRL 0xC0AA // USB control
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#define SUSB2_REG_INTEN 0xC0AC // Interrupt enable
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#define SUSB2_REG_ADDR 0xC0AE // Address
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#define SUSB2_REG_STATUS 0xC0B0 // Status
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#define SUSB2_REG_FRAMENUM 0xC0B2 // Frame number
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#define SUSB2_REG_SOFEOPCNT 0xC0B4 // SOF/EOP count
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// ---------------------------------------------------------
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// Endpoint Registers
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// Device 1 Control
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#define SUSB1_REG_EP_CTRL0 0x0200
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#define SUSB1_REG_EP_CTRL1 0x0210
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#define SUSB1_REG_EP_CTRL2 0x0220
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#define SUSB1_REG_EP_CTRL3 0x0230
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#define SUSB1_REG_EP_CTRL4 0x0240
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#define SUSB1_REG_EP_CTRL5 0x0250
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#define SUSB1_REG_EP_CTRL6 0x0260
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#define SUSB1_REG_EP_CTRL7 0x0270
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// Device 1 Address
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#define SUSB1_REG_EP_ADDR0 0x0202
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#define SUSB1_REG_EP_ADDR1 0x0212
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#define SUSB1_REG_EP_ADDR2 0x0222
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#define SUSB1_REG_EP_ADDR3 0x0232
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#define SUSB1_REG_EP_ADDR4 0x0242
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#define SUSB1_REG_EP_ADDR5 0x0252
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#define SUSB1_REG_EP_ADDR6 0x0262
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#define SUSB1_REG_EP_ADDR7 0x0272
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// Device 1 Count
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#define SUSB1_REG_EP_COUNT0 0x0204
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#define SUSB1_REG_EP_COUNT1 0x0214
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#define SUSB1_REG_EP_COUNT2 0x0224
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#define SUSB1_REG_EP_COUNT3 0x0234
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#define SUSB1_REG_EP_COUNT4 0x0244
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#define SUSB1_REG_EP_COUNT5 0x0254
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#define SUSB1_REG_EP_COUNT6 0x0264
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#define SUSB1_REG_EP_COUNT7 0x0274
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// Device 1 Status
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#define SUSB1_REG_EP_STATUS0 0x0206
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#define SUSB1_REG_EP_STATUS1 0x0216
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#define SUSB1_REG_EP_STATUS2 0x0226
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#define SUSB1_REG_EP_STATUS3 0x0236
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#define SUSB1_REG_EP_STATUS4 0x0246
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#define SUSB1_REG_EP_STATUS5 0x0256
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#define SUSB1_REG_EP_STATUS6 0x0266
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#define SUSB1_REG_EP_STATUS7 0x0276
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// Device 1 Count result
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#define SUSB1_REG_EP_CNTRES0 0x0208
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#define SUSB1_REG_EP_CNTRES1 0x0218
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#define SUSB1_REG_EP_CNTRES2 0x0228
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#define SUSB1_REG_EP_CNTRES3 0x0238
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#define SUSB1_REG_EP_CNTRES4 0x0248
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#define SUSB1_REG_EP_CNTRES5 0x0258
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#define SUSB1_REG_EP_CNTRES6 0x0268
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#define SUSB1_REG_EP_CNTRES7 0x0278
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// Device 2 Control
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#define SUSB2_REG_EP_CTRL0 0x0280
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#define SUSB2_REG_EP_CTRL1 0x0290
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#define SUSB2_REG_EP_CTRL2 0x02A0
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#define SUSB2_REG_EP_CTRL3 0x02B0
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#define SUSB2_REG_EP_CTRL4 0x02C0
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#define SUSB2_REG_EP_CTRL5 0x02D0
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#define SUSB2_REG_EP_CTRL6 0x02E0
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#define SUSB2_REG_EP_CTRL7 0x02F0
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// Device 2 Address
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#define SUSB2_REG_EP_ADDR0 0x0282
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#define SUSB2_REG_EP_ADDR1 0x0292
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#define SUSB2_REG_EP_ADDR2 0x02A2
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#define SUSB2_REG_EP_ADDR3 0x02B2
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#define SUSB2_REG_EP_ADDR4 0x02C2
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#define SUSB2_REG_EP_ADDR5 0x02D2
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#define SUSB2_REG_EP_ADDR6 0x02E2
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#define SUSB2_REG_EP_ADDR7 0x02F2
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// Device 2 Count
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#define SUSB2_REG_EP_COUNT0 0x0284
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#define SUSB2_REG_EP_COUNT1 0x0294
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#define SUSB2_REG_EP_COUNT2 0x02A4
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#define SUSB2_REG_EP_COUNT3 0x02B4
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#define SUSB2_REG_EP_COUNT4 0x02C4
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#define SUSB2_REG_EP_COUNT5 0x02D4
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#define SUSB2_REG_EP_COUNT6 0x02E4
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#define SUSB2_REG_EP_COUNT7 0x02F4
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// Device 2 Status
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#define SUSB2_REG_EP_STATUS0 0x0286
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#define SUSB2_REG_EP_STATUS1 0x0296
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#define SUSB2_REG_EP_STATUS2 0x02A6
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#define SUSB2_REG_EP_STATUS3 0x02B6
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#define SUSB2_REG_EP_STATUS4 0x02C6
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#define SUSB2_REG_EP_STATUS5 0x02D6
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#define SUSB2_REG_EP_STATUS6 0x02E6
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#define SUSB2_REG_EP_STATUS7 0x02F6
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// Device 2 Count result
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#define SUSB2_REG_EP_CNTRES0 0x0288
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#define SUSB2_REG_EP_CNTRES1 0x0298
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#define SUSB2_REG_EP_CNTRES2 0x02A8
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#define SUSB2_REG_EP_CNTRES3 0x02B8
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#define SUSB2_REG_EP_CNTRES4 0x02C8
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#define SUSB2_REG_EP_CNTRES5 0x02D8
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#define SUSB2_REG_EP_CNTRES6 0x02E8
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#define SUSB2_REG_EP_CNTRES7 0x02F8
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// ---------------------------------------------------------
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// others
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#define HUSB_TDLISTDONE 0x1000
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#define HUSB_SOF 0x2000
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#define HUSB_ARMV 0x0001
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#define HUSB_AINS_FS 0x0002
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#define HUSB_AINS_LS 0x0004
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#define HUSB_AWAKEUP 0x0008
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#define HUSB_BRMV 0x0010
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#define HUSB_BINS_FS 0x0020
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#define HUSB_BINS_LS 0x0040
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#define HUSB_BWAKEUP 0x0080
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#define SUSB_EP0_MSG 0x0001
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#define SUSB_EP1_MSG 0x0002
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#define SUSB_EP2_MSG 0x0004
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#define SUSB_EP3_MSG 0x0008
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#define SUSB_EP4_MSG 0x0010
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#define SUSB_EP5_MSG 0x0020
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#define SUSB_EP6_MSG 0x0040
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#define SUSB_EP7_MSG 0x0080
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#define SUSB_RST_MSG 0x0100
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#define SUSB_SOF_MSG 0x0200
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#define SUSB_CFG_MSG 0x0400
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#define SUSB_SUS_MSG 0x0800
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#define SUSB_ID_MSG 0x4000
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#define SUSB_VBUS_MSG 0x8000
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// ---------------------------------------------------------
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// Functions
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// ---------------------------------------------------------
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// HPI low-level routines
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void cy67k3_isr(struct xcptcontext *xcp);
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void cy67k3_reset(void);
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uint16_t cy67k3_read_HPI_DATA(void);
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uint16_t cy67k3_read_HPI_MAILBOX(void);
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uint16_t cy67k3_read_HPI_ADDRESS(void);
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uint16_t cy67k3_read_HPI_STATUS(void);
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void cy67k3_write_HPI_DATA(uint16_t data);
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void cy67k3_write_HPI_MAILBOX(uint16_t data);
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void cy67k3_write_HPI_ADDRESS(uint16_t data);
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void cy67k3_write_HPI_STATUS(uint16_t data);
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// HPI API
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uint32_t hpi_init(void);
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void hpi_mbx_write(uint16_t msgcode);
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uint32_t hpi_mbx_read(void);
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uint32_t hpi_read_reg(uint16_t addr);
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uint32_t hpi_write_reg(uint16_t addr, uint16_t data);
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uint32_t hpi_write_ram(uint16_t addr, uint16_t *pData, uint32_t num_words);
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uint32_t hpi_read_ram(uint16_t addr, uint16_t *pData, uint32_t num_words);
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uint32_t hpi_comm_reset(void);
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uint32_t hpi_comm_jump2code(uint16_t addr);
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uint32_t hpi_comm_callcode(uint16_t addr);
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uint32_t hpi_comm_write_ctrl_reg(uint16_t addr, uint16_t data, uint16_t logic);
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uint32_t hpi_comm_read_ctrl_reg(uint16_t addr);
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uint32_t hpi_comm_write_xmem(uint16_t addr, uint8_t *pData, uint16_t len);
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uint32_t hpi_comm_read_xmem(uint16_t addr, uint8_t *pData, uint16_t len);
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uint32_t hpi_comm_exec_int(uint16_t intnum, uint32_t nargs, ...);
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// USB API
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uint32_t usb_init(void);
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uint32_t usb_irp_register(usb_irp_t *pIRP, uint32_t port, uint32_t ept, uint32_t size, uint32_t is_out);
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uint32_t usb_irp_enqueue(usb_irp_t *pIRP);
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uint32_t usb_callback_register(uint32_t port, uint32_t type, fp_t pFunc, void *pArg);
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#define FIFO_BLOCK 1
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#define FIFO_NONBLOCK 0
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uint32_t fifo_alloc(fifo_t *pObj, uint32_t size);
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uint32_t fifo_free(fifo_t *pObj);
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uint32_t fifo_flush(fifo_t *pObj);
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uint32_t fifo_is_full(fifo_t *pObj);
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uint32_t fifo_is_empty(fifo_t *pObj);
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uint32_t fifo_read(fifo_t *pObj, uint8_t *pData, uint32_t size, uint32_t timeout, uint32_t do_block);
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uint32_t fifo_write(fifo_t *pObj, uint8_t *pData, uint32_t size, uint32_t timeout, uint32_t do_block);
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#endif // HPI_H
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