#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <sys/times.h>
#include <sys/time.h>

#define	CPU_FREQ_HZ	100000000
#include "libsys.h"
#include "gpio.h"
#include "irq.h"

char buffer[16384];
char * volatile pPtr_r;
char * volatile pPtr_w;
static volatile INT32 mouse_x;
static volatile INT32 mouse_y;
static volatile int _g_posx, _g_posy;
static volatile g_btn_l, g_btn_r;
static volatile UINT32 g_color;
uint8_t g_rx_buf[256];
volatile uint32_t g_rx_cmd_valid, g_rx_cid;
gpio_if_t gpio_if;

typedef struct _sbit_state_t
{
	uint32_t curr;
	uint32_t timeout_cnt;
} bit_state_t;

bit_state_t bit_state[8];

typedef struct _scmd_mwrite
{
	uint8_t value, mask;

} __attribute__ ((packed)) cmd_mwrite;

typedef struct _scmd_mread
{

} __attribute__ ((packed)) cmd_mread;

typedef struct _scmd_swrite
{
	uint8_t channel, value;

} __attribute__ ((packed)) cmd_swrite;

typedef struct _scmd_sread
{
	uint8_t channel;

} __attribute__ ((packed)) cmd_sread;

typedef struct _scmd_scycle
{
	uint8_t channel;
	uint32_t time_ms;

} __attribute__ ((packed)) cmd_scycle;

enum
{
	rx_idle = 0,
	rx_sync,
	rx_cid,
	rx_data
};

#define	NUM_COMMANDS	5
#define IS_VALID(cid)	((uint32_t)cid < NUM_COMMANDS)
uint32_t cmd_data_length_tbl[NUM_COMMANDS] = {sizeof(cmd_mread), sizeof(cmd_mwrite), sizeof(cmd_sread), sizeof(cmd_swrite), sizeof(cmd_scycle)};
// -------------------------------------------------------------
void handler0(void)
{
	printf("Interrupt 0\n");
	interrupt_clr(0);
}

void handler1(void)
{
	printf("Interrupt 1\n");
	interrupt_clr(1);
}

void handler2(void)
{
	printf("Interrupt 2\n");
}

void handler3(void)
{
	volatile UINT32 *pUART0_stat = (UINT32*)SYS_UART0_STAT;
	volatile UINT32 *pUART0_data = (UINT32*)SYS_UART0_DATA;
	volatile UINT32 *pUART1_stat = (UINT32*)SYS_UART1_STAT;
	volatile UINT32 *pUART1_data = (UINT32*)SYS_UART1_DATA;

	static uint32_t rx_state, rx_cmd, rx_remain;
	static uint8_t *pRxBuf;

	while(0x200 & *pUART0_stat)
	{

		switch (rx_state)
		{
			case rx_idle:
			if (*pUART0_data == 0x55)
			{
				rx_state = rx_sync;
			}
			break;

			case rx_sync:
			if (*pUART0_data == 0xAA)
			{
				rx_state = rx_cid;
			}
			break;

			case rx_cid:
				rx_cmd = *pUART0_data;
				if (IS_VALID(rx_cmd))
				{
					g_rx_cid = rx_cmd;
					rx_remain = cmd_data_length_tbl[rx_cmd];
					rx_state = rx_data;
					pRxBuf = g_rx_buf;
					if (!rx_remain)
					{
						rx_state = rx_idle;
						g_rx_cmd_valid = 1;
					}
				}
				else
				{
					rx_state = rx_idle;
				}
			break;

			case rx_data:
				*(pRxBuf++) = *pUART0_data;
				rx_remain--;
				if (!rx_remain)
				{
					rx_state = rx_idle;
					g_rx_cmd_valid = 1;
				}
			break;

			default:
			break;
		}

	}

}

void handler4(void)
{
	printf("Interrupt 4\n");
}

void handler5(void)
{
	printf("Interrupt 5\n");
}

void handler6(void)
{
	printf("Interrupt 6\n");
}

void handler7(void)
{
	UINT32 volatile *pTim_stat = (UINT32*)SYS_ITIM_STAT;
	UINT32 volatile *pTim_ctrl = (UINT32*)SYS_ITIM_CTRL;
	UINT32 volatile *pTim0_cmp = (UINT32*)SYS_ITIM0_CMP;
	UINT32 volatile *pUART0_data = (UINT32*)SYS_UART0_DATA;
	time_t curr_date;
	struct tm *pDate;
	uint32_t port;
	int i;

	cmd_sread *pCmd_sread;
	cmd_swrite *pCmd_swrite;
	cmd_mread *pCmd_mread;
	cmd_mwrite *pCmd_mwrite;
	cmd_scycle *pCmd_scycle;

	port = 0;
	if (*pTim_stat & 1)
	{
		*pTim_stat = 1;

		if (g_rx_cmd_valid)
		{
			g_rx_cmd_valid = 0;

			switch (g_rx_cid)
			{
				case 0:
				break;

				case 1:
				break;

				case 2:
				pCmd_sread = (cmd_sread*)g_rx_buf;
				*pUART0_data = bit_state[pCmd_sread->channel&0x07].curr;
				break;

				case 3:
				pCmd_swrite = (cmd_swrite*)g_rx_buf;
				bit_state[pCmd_swrite->channel&0x07].curr = pCmd_swrite->value != 0;
				bit_state[pCmd_swrite->channel&0x07].timeout_cnt = 0;
				break;

				case 4:
				pCmd_scycle = (cmd_scycle*)g_rx_buf;
				bit_state[pCmd_scycle->channel&0x07].timeout_cnt = pCmd_scycle->time_ms;
				bit_state[pCmd_scycle->channel&0x07].curr = !bit_state[pCmd_scycle->channel&0x07].curr;
				break;

				default:
				break;
			}
		}

		for (i=0; i < 8; i++)
		{
			port |= (bit_state[i].curr != 0) << i;
			if (bit_state[i].timeout_cnt)
			{
				bit_state[i].timeout_cnt--;
				if(!bit_state[i].timeout_cnt)
					bit_state[i].curr = !bit_state[i].curr;
			}
		}
		gpio_write(&gpio_if, GPIO_0_MASK_LED, GPIO_0_ALIGN_LED, GPIO_DATA_OFFSET, port);
	}

	if (*pTim_stat & 4)
	{
		*pTim_stat = 4;
	}

}

int main(void)
{

	int i;
	volatile UINT32 *pUART0_stat = (UINT32*)SYS_UART0_STAT;
	volatile UINT32 *pUART1_stat = (UINT32*)SYS_UART1_STAT;
	volatile UINT32 *pUART0_baud = (UINT32*)SYS_UART0_BAUD;
	volatile UINT32 *pUART1_baud = (UINT32*)SYS_UART1_BAUD;
	UINT32 volatile *pTim_ctrl = (UINT32*)SYS_ITIM_CTRL;
	UINT32 volatile *pTim_stat = (UINT32*)SYS_ITIM_STAT;
	UINT32 volatile *pTim0_cnt = (UINT32*)SYS_ITIM0_CNT;
	UINT32 volatile *pTim0_cmp = (UINT32*)SYS_ITIM0_CMP;
	UINT32 volatile *pTim1_cnt = (UINT32*)SYS_ITIM1_CNT;
	UINT32 volatile *pTim1_cmp = (UINT32*)SYS_ITIM1_CMP;
	UINT32 start, end;
	char string[65];

	sleep(1000);

	interrupt_register(0, (void*)handler0);
	interrupt_register(1, (void*)handler1);
//	interrupt_register(2, (void*)handler2);
	interrupt_register(3, (void*)handler3);
//	interrupt_register(4, (void*)handler4);
//	interrupt_register(5, (void*)handler5);
	interrupt_register(6, (void*)handler6);
	interrupt_register(7, (void*)handler7);

	memset(bit_state, 0, sizeof(bit_state));
	gpio_init(&gpio_if, SYS_GPIO_0_BASE);

	srand(clock());
	UART0_setbaud(115200);
	UART1_setbaud(115200);
	memset(buffer, 0, sizeof(buffer));

	pPtr_r = buffer;
	pPtr_w = buffer;

	// UART: enable RX interrupt
	*pUART0_stat |= (1 << 6);
	*pUART1_stat |= (1 << 6);
//	printf("UART0 Status = 0x%8.8X\n", *pUART0_stat);
//	printf("UART1 Status = 0x%8.8X\n", *pUART1_stat);

	*pTim0_cnt = 0;
	*pTim1_cnt = 0;
	*pTim0_cmp = 100000;
	*pTim1_cmp = 100000000;
	*pTim_stat = (1 << 2) | (1 << 0);
	*pTim_ctrl = (3 << 2);
//	printf("Timer Status = 0x%8.8X\n", *pTim_stat);
//	printf("Timer Ctrl   = 0x%8.8X\n", *pTim_ctrl);


	printf("Start\n");

//	interrupt_enable(0);
//	interrupt_enable(1);
//	interrupt_enable(2);
	interrupt_enable(3);
//	interrupt_enable(4);
//	interrupt_enable(5);
//	interrupt_enable(6);
	interrupt_enable(7);


	*pTim_ctrl |= 3;

	while(1)
	{
	}

	return 0;
}