#ifndef LIBSYS_H #define LIBSYS_H #include // --------------------------------------------------------- // Types // --------------------------------------------------------- #define LSYS_ERR_BASE 0x80000000 #define IS_ERROR(e) ((e & LSYS_ERR_BASE) == LSYS_ERR_BASE) #ifndef SYS_IO_BASE #define SYS_IO_BASE 0xA0000000 #endif #ifndef SDRAM_BASE #define SDRAM_BASE 0x40000000 #endif #ifndef FLASH_BASE_IO #define FLASH_BASE_IO 0xA4000000 #endif #ifndef FLASH_BASE_MEM #define FLASH_BASE_MEM 0x00000000 #endif #define SYS_GPIO_0_DATA (SYS_IO_BASE + 0x0) #define SYS_GPIO_0_DIR (SYS_IO_BASE + 0x4) #define GPIO_0_DFLT_DIR (GPIO_0_LED | GPIO_0_USB_RST | GPIO_0_USB_INTEN | GPIO_0_AC97_INTEN | GPIO_0_PHY_RST | GPIO_0_PHY_MDC) #define GPIO_0_DFLT_DATA ((~GPIO_0_LED & GPIO_0_LED) | GPIO_0_USB_RST | (~GPIO_0_USB_INTEN & GPIO_0_USB_INTEN) | (~GPIO_0_AC97_INTEN & GPIO_0_AC97_INTEN) | GPIO_0_PHY_RST | (~GPIO_0_PHY_MDC & GPIO_0_PHY_MDC)) #define GPIO_0_LED 0x000001FF #define GPIO_0_BTN 0x1F000000 #define GPIO_0_DIP 0x00FF0000 #define GPIO_0_USB_RST 0x00001000 #define GPIO_0_USB_INTEN 0x00002000 #define GPIO_0_AC97_INTEN 0x00008000 #define GPIO_0_PHY_RST 0x20000000 #define GPIO_0_PHY_MDC 0x40000000 #define GPIO_0_PHY_MDIO 0x80000000 #define GPIO_0_ALIGN_LED 0 #define GPIO_0_ALIGN_DIP 16 #define GPIO_0_ALIGN_BTN 24 #define GPIO_0_ALIGN_MDIO 31 #define SYS_TIMER_USEC (SYS_IO_BASE + 0x8) #define SYS_TIMER_SEC (SYS_IO_BASE + 0xC) #define SYS_ITIM_CTRL (SYS_IO_BASE + 0x18) #define SYS_ITIM_STAT (SYS_IO_BASE + 0x1C) #define SYS_ITIM0_CNT (SYS_IO_BASE + 0x20) #define SYS_ITIM1_CNT (SYS_IO_BASE + 0x24) #define SYS_ITIM2_CNT (SYS_IO_BASE + 0x28) #define SYS_ITIM3_CNT (SYS_IO_BASE + 0x2C) #define SYS_ITIM0_CMP (SYS_IO_BASE + 0x30) #define SYS_ITIM1_CMP (SYS_IO_BASE + 0x34) #define SYS_ITIM2_CMP (SYS_IO_BASE + 0x38) #define SYS_ITIM3_CMP (SYS_IO_BASE + 0x3C) #define SYS_UART_DATA (SYS_IO_BASE + 0x10000) #define SYS_UART_STAT (SYS_IO_BASE + 0x10004) #define SYS_UART_BAUD (SYS_IO_BASE + 0x10008) #define SYS_SPI_STAT (SYS_IO_BASE + 0x20000) // Read #define SPI_STAT_CMDRDY (0x01) #define SPI_STAT_DINRDY (0x02) #define SPI_STAT_DOUTRDY (0x04) #define SPI_STAT_CMD_FIFO_FULL (0x0100) #define SPI_STAT_CMD_FIFO_EMPTY (0x0200) #define SPI_STAT_WRITE_FIFO_FULL (0x0400) #define SPI_STAT_WRITE_FIFO_EMPTY (0x0800) #define SPI_STAT_READ_FIFO_FULL (0x1000) #define SPI_STAT_READ_FIFO_EMPTY (0x2000) #define SPI_STAT_RX_VALID (0x4000) #define SPI_STAT_SPI_HOLD (0x8000) // Write #define SPI_STAT_COMMIT (1) #define SYS_SPI_XFER_SIZE (SYS_IO_BASE + 0x20004) #define SYS_SPI_DATA_SIZE (SYS_IO_BASE + 0x20008) #define SYS_SPI_DATA (SYS_IO_BASE + 0x2000C) #define SYS_SPI_CTRL (SYS_IO_BASE + 0x20010) #define SYS_FLASH_IO FLASH_BASE_IO #define SYS_FLASH_MEM FLASH_BASE_MEM // RTC #define SYS_TIMER_USEC (SYS_IO_BASE + 0x8) #define SYS_TIMER_SEC (SYS_IO_BASE + 0xC) // TIMERs #define SYS_ITIM_CTRL (SYS_IO_BASE + 0x18) #define SYS_ITIM_STAT (SYS_IO_BASE + 0x1C) #define SYS_ITIM0_CNT (SYS_IO_BASE + 0x20) #define SYS_ITIM1_CNT (SYS_IO_BASE + 0x24) #define SYS_ITIM2_CNT (SYS_IO_BASE + 0x28) #define SYS_ITIM3_CNT (SYS_IO_BASE + 0x2C) #define SYS_ITIM0_CMP (SYS_IO_BASE + 0x30) #define SYS_ITIM1_CMP (SYS_IO_BASE + 0x34) #define SYS_ITIM2_CMP (SYS_IO_BASE + 0x38) #define SYS_ITIM3_CMP (SYS_IO_BASE + 0x3C) // MIPS specific uint32_t CP0_SR_read(void); void CP0_SR_write(uint32_t val); uint32_t CP0_CR_read(void); void CP0_CR_write(uint32_t val); uint32_t CP0_PRID_read(void); uint32_t CP0_TR_read(void); void CP0_TR_write(uint32_t val); void CP0_TR_write_ptr(uint32_t* pPtr); void CP0_TR_read_ptr(uint32_t* pPtr); void ICACHE_invalidate_all(void); void ICACHE_invalidate_at(uint32_t* pPtr); void DCACHE_invalidate_all(void); void DCACHE_invalidate_at(uint32_t* pPtr); // General char readchar(void); void writechar(char c); int write(int file, char *ptr, int len); int sputs(char const *pStr); void print_byte(char byte); void print_word(int word); void PrintBuffer8(uint8_t *pBuf, int nbpr, int len); void memdump(uint8_t *pBuf, int print_offset_only, int num_bytes_per_row, int len); #endif // LIBSYS_H