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- refactored libsys

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- added critical section
- added interrupt global enable/disable
- added console::getInstanveByName



git-svn-id: http://moon:8086/svn/mips@76 a8ebac50-d88d-4704-bea3-6648445a41b3
This commit is contained in:
jens
2017-01-12 16:25:20 +00:00
parent 0f4b7e015f
commit 5c9c50ebeb
21 changed files with 129 additions and 307 deletions
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src/libsys/libsys.h
+2 -70
View File
@@ -15,76 +15,8 @@
#define IS_ERROR(e) ((e & LSYS_ERR_BASE) == LSYS_ERR_BASE)
// ---------------------------------------------------------
// Chip registers
// ---------------------------------------------------------
// COP0 registers
#define COP0_REG_INVAT_POINTER 31
// COP0 instructions
#define COP0_INSTR_INVALL_ICACHE 32
#define COP0_INSTR_INVAT_ICACHE 33
#define COP0_INSTR_INVALL_DCACHE 34
#define COP0_INSTR_INVAT_DCACHE 35
#define CP0_read(idx) \
({ \
uint32_t result; \
__asm__ __volatile__ \
( \
"mfc0\t%0,$"#idx"\n" \
: "=r" (result) \
); \
result; \
})
#define CP0_write(idx, val) \
({ \
__asm__ __volatile__ \
( \
"mtc0\t%0,$"#idx"\n" \
"nop\n" \
: /* no output */ \
: "r" (val) \
); \
})
#define CP0_TLBR \
({ \
__asm__ __volatile__ \
( \
"tlbr\n" \
: /* no output */ \
: /* no input */ \
); \
})
#define CP0_TLBWI \
({ \
__asm__ __volatile__ \
( \
"tlbwi\n" \
: /* no output */ \
: /* no input */ \
); \
})
uint32_t CP0_SR_read(void);
void CP0_SR_write(uint32_t val);
uint32_t CP0_CR_read(void);
void CP0_CR_write(uint32_t val);
uint32_t CP0_PRID_read(void);
uint32_t CP0_TR_read(void);
void CP0_TR_write(uint32_t val);
void CP0_TR_write_ptr(uint32_t* pPtr);
void CP0_TR_read_ptr(uint32_t* pPtr);
void ICACHE_invalidate_all(void);
void ICACHE_invalidate_at(uint32_t* pPtr);
void DCACHE_invalidate_all(void);
void DCACHE_invalidate_at(uint32_t* pPtr);
void UART0_setbaud(uint32_t baudrate);
void UART1_setbaud(uint32_t baudrate);
void enter_critical();
void exit_critical();
int write(int file, char *ptr, int len);
int sputs(char const *pStr);