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- refactored libsys

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- added critical section
- added interrupt global enable/disable
- added console::getInstanveByName



git-svn-id: http://moon:8086/svn/mips@76 a8ebac50-d88d-4704-bea3-6648445a41b3
This commit is contained in:
jens
2017-01-12 16:25:20 +00:00
parent 0f4b7e015f
commit 5c9c50ebeb
21 changed files with 129 additions and 307 deletions
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src/libsys/libsys.c
+17 -151
View File
@@ -5,164 +5,30 @@
#include <errno.h>
#include <stdio.h>
#include <stdlib.h>
#include "console.h"
#include "libsys.h"
#include "regdef.h"
static uint32_t critical_nesting_counter = 0;
#define CALC_BAUD(b) \
((uint32_t)((float)CPU_FREQ_HZ/(16*b) + 0.5f) - 1);
void UART0_setbaud(uint32_t baudrate)
void enter_critical()
{
*((uint32_t*)SYS_UART0_BAUD) = CALC_BAUD(baudrate);
if (critical_nesting_counter == 0)
{
interrupt_disable_all();
}
critical_nesting_counter++;
}
void UART1_setbaud(uint32_t baudrate)
void exit_critical()
{
*((uint32_t*)SYS_UART1_BAUD) = CALC_BAUD(baudrate);
}
// ---------------------------------------------------------------------------------
// MIPS specific
// ---------------------------------------------------------------------------------
uint32_t CP0_SR_read(void)
{
uint32_t result;
__asm__
(
"mfc0 %[val], $12\n"
: [val] "=r" (result)
);
return result;
}
void CP0_SR_write(uint32_t val)
{
__asm__
(
"mtc0 %[val], $12\n"
: /* no output */
: [val] "r" (val)
);
}
uint32_t CP0_CR_read(void)
{
uint32_t result;
__asm__
(
"mfc0 %[val], $13\n"
: [val] "=r" (result)
);
return result;
}
void CP0_CR_write(uint32_t val)
{
__asm__
(
"mtc0 %[val], $13\n"
:
: [val] "r" (val)
);
}
uint32_t CP0_TR_read(void)
{
uint32_t result;
__asm__
(
"mfc0 %[val], $31\n"
: [val] "=r" (result)
);
return result;
}
void CP0_TR_write(uint32_t val)
{
__asm__
(
"mtc0 %[val], $31\n"
:
: [val] "r" (val)
);
}
uint32_t CP0_PRID_read(void)
{
uint32_t result;
__asm__
(
"mfc0 %[val], $15\n"
: [val] "=r" (result)
);
return result;
}
void CP0_TR_write_ptr(uint32_t* pPtr)
{
__asm__
(
"swc0 $31, 0(%[pPtr])\n"
:
: [pPtr] "r" (pPtr)
);
}
void CP0_TR_read_ptr(uint32_t* pPtr)
{
__asm__
(
"lwc0 $31, 0(%[pPtr])\n"
:
: [pPtr] "r" (pPtr)
);
}
void ICACHE_invalidate_all(void)
{
__asm__
(
"cop0 32\n"
);
}
void ICACHE_invalidate_at(uint32_t* pPtr)
{
__asm__
(
"mtc0 %[pPtr], $31\n"
"cop0 33\n"
:
: [pPtr] "r" (pPtr)
);
}
void DCACHE_invalidate_all(void)
{
__asm__
(
"cop0 34\n"
);
}
void DCACHE_invalidate_at(uint32_t* pPtr)
{
__asm__
(
"mtc0 %[pPtr], $31\n"
"cop0 35\n"
:
: [pPtr] "r" (pPtr)
);
if (critical_nesting_counter > 0)
{
critical_nesting_counter--;
if (critical_nesting_counter == 0)
{
interrupt_enable_all();
}
}
}
void _exit (int exitcode)