- added tests

git-svn-id: http://moon:8086/svn/mips@172 a8ebac50-d88d-4704-bea3-6648445a41b3

src/asm/Makefile

@@ -18,18 +18,22 @@ CFLAGS := $(ENDIAN_FLAGS) -march=$(TARGET) -L. -T link/link.ld -Wl,--gc-sections
 CFLAGS += -fno-exceptions -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -nostartfiles
 LIBS := -lsys -lc
 
+TEST_SRC := tests/test_dcache.c tests/test_uncached_cachemiss_bug.c
+
 all: testbench.elf
 
+
 libsys.a:
 	$(CC) $(CFLAGS) -c libsys/startup.s -o startup.o
 	$(CC) $(CFLAGS) -c libsys/kernel.s -o kernel.o
 	$(CC) $(CFLAGS) -c libsys/utils.c -o utils.o
+	$(CC) $(CFLAGS) -c ../libsys/cop0.c -o cop0.o
 	$(CC) $(CFLAGS) -c libsys/boards/sim/board.c -o board.o
-	$(AR) -r libsys.a startup.o kernel.o utils.o board.o
+	$(AR) -r libsys.a startup.o kernel.o utils.o board.o cop0.o
 
 
 testbench.elf: libsys.a
-	$(CC) $(CFLAGS) -o $@ testbench.c $(LIBS)
+	$(CC) $(CFLAGS) -o $@ testbench.c $(TEST_SRC) $(LIBS)
 	$(OBJDUMP) -d $@ > $@.dis
 	$(OBJCOPY) $@ -O binary $@.bin
 	$(ROMGEN) $@.bin $(ROM_WORDADDR_WIDTH)

src/asm/testbench.c

@@ -2,6 +2,9 @@
 #include <stdlib.h>
 #include "libsys/utils.h"
 
+#include "tests/test_dcache.h"
+#include "tests/test_uncached_cachemiss_bug.h"
+
 #define	NO_ERROR		0x00000000
 #define	ERROR			0x80000000
 #define	IS_ERROR(e)		((e & ERROR) == ERROR)
@@ -9,6 +12,8 @@
 #define	TEST10_ERROR	(ERROR | 0x10)
 #define	TEST11_ERROR	(ERROR | 0x11)
 #define	TEST12_ERROR	(ERROR | 0x12)
+#define	TEST13_ERROR	(ERROR | 0x13)
+#define	TEST14_ERROR	(ERROR | 0x14)
 
 int fibonacci(int f0, int f1, int *pDst, int len)
 {
@@ -264,14 +269,11 @@ int Test12_MulDiv()
 int main (void)
 {
 	int result, i, j, cnt;
-	volatile int *pReg = (int*)0x80000000;
 	PrintCPUinfo();
 
 	cnt = 0;
 	while (1)
 	{
-		*pReg = cnt & 0x3FFFFFFF;
-
 		result = Test10_LoadStore();
 		if (IS_ERROR(result))
 			break;
@@ -284,16 +286,28 @@ int main (void)
 		if (IS_ERROR(result))
 			break;
 
-//		printf("Iteration %d: Passed\n", cnt++);
+		result = test_dcache();
+		if (!result)
+		{
+			result = TEST13_ERROR;
+			break;
+		}
+		result = test_uncached_cachemiss_bug();
+		sputs("result "); print_word(result); sputs(" \n");
+		
+		if (!result)
+		{
+			result = TEST14_ERROR;
+			break;
+		}
+
+		
 		sputs("Iteration ");
 		print_word(cnt++);
 		sputs(": Passed\n");
 
 	}
-	*pReg = 0x40000000 | cnt;
+	sputs("Failed with error "); print_word(result); sputs(" \n");
-	sputs("Failed with error ");
-	print_word(result);
-	sputs(" \n");
 
 	return 1;
 

src/asm/tests/test_dcache.c

@@ -0,0 +1,57 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include "../libsys/utils.h"
+
+#define SIZE 256
+
+uint32_t _test_dcache(uint32_t *pMem)
+{
+	uint32_t result;
+	
+	__asm__
+	(
+		".set	noreorder\n"
+		".set	nomacro\n"
+		
+		"addiu  $t1, $0, 0x5555\n"
+		"lw     $t0, 0(%[pMem])\n"
+		"sw     $t1, 24(%[pMem])\n"
+		"addiu	$t0, 8\n"
+		"sw     $t0, 0(%[pMem])\n"
+		"nop\n"
+		"nop\n"
+		"nop\n"
+		"nop\n"
+		"nop\n"
+		"nop\n"
+		"nop\n"
+		"nop\n"
+		"nop\n"
+		"nop\n"
+		"nop\n"
+		"nop\n"
+		"lw     %[result], 24(%[pMem])\n"
+
+		".set	macro\n"
+		".set	reorder\n"
+		: [result] "=r" (result)
+		: [pMem] "r" (pMem)
+		: "t0", "t1"
+	);
+	
+	return result;
+}
+
+uint32_t test_dcache()
+{
+	uint64_t buffer[SIZE/sizeof(uint64_t)];
+	uint32_t *pPtr32 = (uint32_t*)buffer;
+
+	for(int i=0; i < SIZE/sizeof(uint32_t); i++)
+		pPtr32[i] = i;
+
+	DCACHE_invalidate_all();
+
+	return _test_dcache(pPtr32) == 0x00005555;
+}
+

src/asm/tests/test_dcache.h

@@ -0,0 +1,8 @@
+#ifndef _TEST_DCACHE_H_
+#define _TEST_DCACHE_H_
+
+uint32_t test_dcache();
+
+#endif // _TEST_DCACHE_H__TEST_DCACHE_H_
+
+

src/asm/tests/test_uncached_cachemiss_bug.c

@@ -0,0 +1,45 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include "../libsys/utils.h"
+
+
+uint32_t _test_uncached_cachemiss_bug(uint32_t* pMem)
+{
+	uint32_t result;
+
+	pMem[0] = 0x12345678;
+	pMem[1] = 0xFFFFFFFF;
+
+	DCACHE_invalidate_all();
+
+	__asm__
+	(
+		"move     $s0, %[pMem]\n"
+		"lw     $a0, 32($s0)\n"
+		"or		$s1, $a0, $0\n"
+		"or		$a2, $0, $0\n"
+		"addiu	$a2, 1\n"
+		"sw     $a2, 32($s0)\n"
+//		"lw     $a1, 0(%[pMem])\n"
+		"lw     $a0, 32($s0)\n"
+		"lw     $a2, 4(%[pMem])\n"
+		"lw     $a1, 0(%[pMem])\n"
+		"nop\n"
+		"sw     $s1, 8($s0)\n"
+		"or		%[result], $a0, $0\n"
+		: [result] "=r" (result)
+		: [pMem] "r" (pMem)
+		: "a0", "a1", "a2", "s0", "s1"
+	);
+	return result;
+}
+
+uint32_t test_uncached_cachemiss_bug()
+{
+	uint32_t buf[256], res;
+
+	res = _test_uncached_cachemiss_bug(buf);
+
+	return res;
+
+}

src/asm/tests/test_uncached_cachemiss_bug.h

@@ -0,0 +1,8 @@
+#ifndef _TEST_UNCACHED_CACHEMISS_BUG_H_
+#define _TEST_UNCACHED_CACHEMISS_BUG_H_
+
+uint32_t test_uncached_cachemiss_bug();
+
+#endif // _TEST_UNCACHED_CACHEMISS_BUG_H_
+
+