jensandClaude Sonnet 5 c60fdff74d docs: check off set_model_power gap in PID design backlog ...

Already fixed in 2f2067d (no-op stub on TempControllerBase, 2026-06-25)
but the TODO entry was never marked done.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01F4oEE99rkKVU8L8tkzXWdG

2026-07-11 12:17:13 +02:00

..

__init__.py

Consolidate States/DEFAULT_THRESHOLDS into temp_controller_base.py

2026-06-19 16:57:35 +02:00

kalman.py

Move PID matplotlib demo harnesses out of production modules

2026-06-19 08:21:47 +02:00

pid_factory.py

Extract shared factory dispatch into ComponentFactory base class

2026-06-25 20:44:43 +02:00

pid.py

fix: split inner-loop yi_max clamp to fix HOLD-state windup overshoot

2026-07-05 21:23:55 +02:00

temp_controller_base.py

fix: allow gentle negative HOLD floor to fix steady-state overshoot

2026-07-06 08:19:10 +02:00

temp_controller_fsm.py

fix: split inner-loop yi_max clamp to fix HOLD-state windup overshoot

2026-07-05 21:23:55 +02:00

temp_controller_smith.py

fix: smooth HOLD→HEAT power transition (bumpless transfer + cascade timing)

2026-06-30 20:33:12 +02:00

temp_controller.py

fix: smooth HOLD→HEAT power transition (bumpless transfer + cascade timing)

2026-06-30 20:33:12 +02:00

TODO.md

docs: check off set_model_power gap in PID design backlog

2026-07-11 12:17:13 +02:00