jensandClaude Sonnet 5 6d17419067 docs: note active-cooler architecture assessment in pid TODO ...

Captures the answer to "would the cascade/FSM design still hold up with
a real active cooler instead of heat-only + passive loss": PID/plant
model already generalize (symmetric y range, sign-agnostic plant math,
existing COOL state/pid_inner_cool), but the actor-level max(0, y)
clamp in tasks/heater.py is the one thing making today's tuning
mismatches free - removing it exposes both Outer.y_hold_min and
pid_inner_cool as live, untuned negative-power paths.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01M2ierBoxW3v7nUbDw3M2pE

2026-07-06 08:26:25 +02:00

..

__init__.py

Consolidate States/DEFAULT_THRESHOLDS into temp_controller_base.py

2026-06-19 16:57:35 +02:00

kalman.py

Move PID matplotlib demo harnesses out of production modules

2026-06-19 08:21:47 +02:00

pid_factory.py

Extract shared factory dispatch into ComponentFactory base class

2026-06-25 20:44:43 +02:00

pid.py

fix: split inner-loop yi_max clamp to fix HOLD-state windup overshoot

2026-07-05 21:23:55 +02:00

temp_controller_base.py

fix: allow gentle negative HOLD floor to fix steady-state overshoot

2026-07-06 08:19:10 +02:00

temp_controller_fsm.py

fix: split inner-loop yi_max clamp to fix HOLD-state windup overshoot

2026-07-05 21:23:55 +02:00

temp_controller_smith.py

fix: smooth HOLD→HEAT power transition (bumpless transfer + cascade timing)

2026-06-30 20:33:12 +02:00

temp_controller.py

fix: smooth HOLD→HEAT power transition (bumpless transfer + cascade timing)

2026-06-30 20:33:12 +02:00

TODO.md

docs: note active-cooler architecture assessment in pid TODO

2026-07-06 08:26:25 +02:00