- do data signal wiring at one central place

- fixed initializations
2021-10-11 13:05:18 +02:00
parent 80fa983c96
commit c5c39732cf
4 changed files with 10 additions and 7 deletions
@@ -16,7 +16,7 @@ class Pot(APlant):
 		self.L = params['L']
 		self.Td = params['Td']
 		self.kn = params['kn']
-		self.temp = 0
+		self.temp = params['theta']
 		self.temp_intermediate = params['theta']

 		self.theta_amb = theta_amb